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29a404f9 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
3072d30e | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, |
7cf0dbf3 | 3 | 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. |
29a404f9 | 4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
187b36cf | 6 | This file is part of GCC. |
29a404f9 | 7 | |
187b36cf | 8 | GCC is free software; you can redistribute it and/or modify |
29a404f9 | 9 | it under the terms of the GNU General Public License as published by |
038d1e19 | 10 | the Free Software Foundation; either version 3, or (at your option) |
29a404f9 | 11 | any later version. |
12 | ||
187b36cf | 13 | GCC is distributed in the hope that it will be useful, |
29a404f9 | 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
038d1e19 | 19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
29a404f9 | 21 | |
29a404f9 | 22 | #include "config.h" |
7014838c | 23 | #include "system.h" |
805e22b2 | 24 | #include "coretypes.h" |
25 | #include "tm.h" | |
29a404f9 | 26 | #include "rtl.h" |
4faf81b8 | 27 | #include "tree.h" |
29a404f9 | 28 | #include "regs.h" |
29 | #include "hard-reg-set.h" | |
29a404f9 | 30 | #include "insn-config.h" |
31 | #include "conditions.h" | |
29a404f9 | 32 | #include "output.h" |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
8b8be022 | 36 | #include "reload.h" |
29a404f9 | 37 | #include "expr.h" |
d8fc4d0b | 38 | #include "optabs.h" |
4faf81b8 | 39 | #include "function.h" |
29a404f9 | 40 | #include "obstack.h" |
0b205f4c | 41 | #include "diagnostic-core.h" |
59086782 | 42 | #include "toplev.h" |
43 | #include "tm_p.h" | |
a767736d | 44 | #include "target.h" |
45 | #include "target-def.h" | |
29a404f9 | 46 | |
b87a151a | 47 | /* This is used by GOTaddr2picreg to uniquely identify |
48 | UNSPEC_INT_LABELs. */ | |
49 | int mn10300_unspec_int_label_counter; | |
50 | ||
1acdfc69 | 51 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
52 | names are not prefixed by underscores, to tell whether to prefix a | |
53 | label with a plus sign or not, so that the assembler can tell | |
54 | symbol names from register names. */ | |
55 | int mn10300_protect_label; | |
56 | ||
8c2c40c5 | 57 | /* The selected processor. */ |
58 | enum processor_type mn10300_processor = PROCESSOR_DEFAULT; | |
59 | ||
8ecf154e | 60 | /* The size of the callee register save area. Right now we save everything |
61 | on entry since it costs us nothing in code size. It does cost us from a | |
62 | speed standpoint, so we want to optimize this sooner or later. */ | |
3072d30e | 63 | #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \ |
64 | + 4 * df_regs_ever_live_p (3) \ | |
65 | + 4 * df_regs_ever_live_p (6) \ | |
66 | + 4 * df_regs_ever_live_p (7) \ | |
67 | + 16 * (df_regs_ever_live_p (14) || df_regs_ever_live_p (15) \ | |
68 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17))) | |
fab7adbf | 69 | |
70 | ||
8c2c40c5 | 71 | static bool mn10300_handle_option (size_t, const char *, int); |
fd50b071 | 72 | static bool mn10300_legitimate_address_p (enum machine_mode, rtx, bool); |
0792f2cf | 73 | static int mn10300_address_cost_1 (rtx, int *); |
f529eb25 | 74 | static int mn10300_address_cost (rtx, bool); |
75 | static bool mn10300_rtx_costs (rtx, int, int, int *, bool); | |
0792f2cf | 76 | static void mn10300_file_start (void); |
fb80456a | 77 | static bool mn10300_return_in_memory (const_tree, const_tree); |
f2d49d02 | 78 | static rtx mn10300_builtin_saveregs (void); |
8a58ed0a | 79 | static void mn10300_va_start (tree, rtx); |
41e3a0c7 | 80 | static rtx mn10300_legitimize_address (rtx, rtx, enum machine_mode); |
b981d932 | 81 | static bool mn10300_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
fb80456a | 82 | const_tree, bool); |
f054eb3c | 83 | static int mn10300_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
84 | tree, bool); | |
906bb5c3 | 85 | static unsigned int mn10300_case_values_threshold (void); |
3e16f982 | 86 | static void mn10300_encode_section_info (tree, rtx, int); |
87 | static void mn10300_asm_trampoline_template (FILE *); | |
88 | static void mn10300_trampoline_init (rtx, tree, rtx); | |
b6713ba6 | 89 | static rtx mn10300_function_value (const_tree, const_tree, bool); |
90 | static rtx mn10300_libcall_value (enum machine_mode, const_rtx); | |
e92d3ba8 | 91 | static void mn10300_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); |
92 | static bool mn10300_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT, const_tree); | |
a767736d | 93 | \f |
94 | /* Initialize the GCC target structure. */ | |
58356836 | 95 | #undef TARGET_ASM_ALIGNED_HI_OP |
96 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
8ecf154e | 97 | |
41e3a0c7 | 98 | #undef TARGET_LEGITIMIZE_ADDRESS |
99 | #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address | |
100 | ||
fab7adbf | 101 | #undef TARGET_RTX_COSTS |
102 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
ec0457a8 | 103 | #undef TARGET_ADDRESS_COST |
104 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
fab7adbf | 105 | |
92c473b8 | 106 | #undef TARGET_ASM_FILE_START |
107 | #define TARGET_ASM_FILE_START mn10300_file_start | |
108 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
109 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
110 | ||
8c2c40c5 | 111 | #undef TARGET_DEFAULT_TARGET_FLAGS |
00b1da0e | 112 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0 |
8c2c40c5 | 113 | #undef TARGET_HANDLE_OPTION |
114 | #define TARGET_HANDLE_OPTION mn10300_handle_option | |
115 | ||
b87a151a | 116 | #undef TARGET_ENCODE_SECTION_INFO |
117 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
118 | ||
f2d49d02 | 119 | #undef TARGET_PROMOTE_PROTOTYPES |
fb80456a | 120 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
f2d49d02 | 121 | #undef TARGET_RETURN_IN_MEMORY |
122 | #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory | |
b981d932 | 123 | #undef TARGET_PASS_BY_REFERENCE |
124 | #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference | |
13f08ee7 | 125 | #undef TARGET_CALLEE_COPIES |
126 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
f054eb3c | 127 | #undef TARGET_ARG_PARTIAL_BYTES |
128 | #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes | |
f2d49d02 | 129 | |
130 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
131 | #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs | |
8a58ed0a | 132 | #undef TARGET_EXPAND_BUILTIN_VA_START |
133 | #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start | |
f2d49d02 | 134 | |
906bb5c3 | 135 | #undef TARGET_CASE_VALUES_THRESHOLD |
136 | #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold | |
137 | ||
fd50b071 | 138 | #undef TARGET_LEGITIMATE_ADDRESS_P |
139 | #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p | |
140 | ||
3e16f982 | 141 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
142 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE mn10300_asm_trampoline_template | |
143 | #undef TARGET_TRAMPOLINE_INIT | |
144 | #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init | |
145 | ||
b6713ba6 | 146 | #undef TARGET_FUNCTION_VALUE |
147 | #define TARGET_FUNCTION_VALUE mn10300_function_value | |
148 | #undef TARGET_LIBCALL_VALUE | |
149 | #define TARGET_LIBCALL_VALUE mn10300_libcall_value | |
150 | ||
e92d3ba8 | 151 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
152 | #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk | |
153 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
154 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk | |
155 | ||
57e4bbfb | 156 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 157 | \f |
8c2c40c5 | 158 | /* Implement TARGET_HANDLE_OPTION. */ |
159 | ||
160 | static bool | |
161 | mn10300_handle_option (size_t code, | |
162 | const char *arg ATTRIBUTE_UNUSED, | |
163 | int value) | |
164 | { | |
165 | switch (code) | |
166 | { | |
167 | case OPT_mam33: | |
168 | mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300; | |
169 | return true; | |
170 | case OPT_mam33_2: | |
171 | mn10300_processor = (value | |
172 | ? PROCESSOR_AM33_2 | |
173 | : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT)); | |
174 | return true; | |
175 | default: | |
176 | return true; | |
177 | } | |
178 | } | |
179 | ||
180 | /* Implement OVERRIDE_OPTIONS. */ | |
181 | ||
182 | void | |
183 | mn10300_override_options (void) | |
184 | { | |
185 | if (TARGET_AM33) | |
186 | target_flags &= ~MASK_MULT_BUG; | |
187 | } | |
188 | ||
92c473b8 | 189 | static void |
3285410a | 190 | mn10300_file_start (void) |
29a404f9 | 191 | { |
92c473b8 | 192 | default_file_start (); |
911517ac | 193 | |
b166356e | 194 | if (TARGET_AM33_2) |
195 | fprintf (asm_out_file, "\t.am33_2\n"); | |
196 | else if (TARGET_AM33) | |
92c473b8 | 197 | fprintf (asm_out_file, "\t.am33\n"); |
29a404f9 | 198 | } |
199 | \f | |
200 | ||
29a404f9 | 201 | /* Print operand X using operand code CODE to assembly language output file |
202 | FILE. */ | |
203 | ||
204 | void | |
3285410a | 205 | print_operand (FILE *file, rtx x, int code) |
29a404f9 | 206 | { |
207 | switch (code) | |
208 | { | |
209 | case 'b': | |
210 | case 'B': | |
b166356e | 211 | if (cc_status.mdep.fpCC) |
212 | { | |
213 | switch (code == 'b' ? GET_CODE (x) | |
214 | : reverse_condition_maybe_unordered (GET_CODE (x))) | |
215 | { | |
216 | case NE: | |
217 | fprintf (file, "ne"); | |
218 | break; | |
219 | case EQ: | |
220 | fprintf (file, "eq"); | |
221 | break; | |
222 | case GE: | |
223 | fprintf (file, "ge"); | |
224 | break; | |
225 | case GT: | |
226 | fprintf (file, "gt"); | |
227 | break; | |
228 | case LE: | |
229 | fprintf (file, "le"); | |
230 | break; | |
231 | case LT: | |
232 | fprintf (file, "lt"); | |
233 | break; | |
234 | case ORDERED: | |
235 | fprintf (file, "lge"); | |
236 | break; | |
237 | case UNORDERED: | |
238 | fprintf (file, "uo"); | |
239 | break; | |
240 | case LTGT: | |
241 | fprintf (file, "lg"); | |
242 | break; | |
243 | case UNEQ: | |
244 | fprintf (file, "ue"); | |
245 | break; | |
246 | case UNGE: | |
247 | fprintf (file, "uge"); | |
248 | break; | |
249 | case UNGT: | |
250 | fprintf (file, "ug"); | |
251 | break; | |
252 | case UNLE: | |
253 | fprintf (file, "ule"); | |
254 | break; | |
255 | case UNLT: | |
256 | fprintf (file, "ul"); | |
257 | break; | |
258 | default: | |
cf41bb03 | 259 | gcc_unreachable (); |
b166356e | 260 | } |
261 | break; | |
262 | } | |
29a404f9 | 263 | /* These are normal and reversed branches. */ |
264 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
265 | { | |
266 | case NE: | |
267 | fprintf (file, "ne"); | |
268 | break; | |
269 | case EQ: | |
270 | fprintf (file, "eq"); | |
271 | break; | |
272 | case GE: | |
273 | fprintf (file, "ge"); | |
274 | break; | |
275 | case GT: | |
276 | fprintf (file, "gt"); | |
277 | break; | |
278 | case LE: | |
279 | fprintf (file, "le"); | |
280 | break; | |
281 | case LT: | |
282 | fprintf (file, "lt"); | |
283 | break; | |
284 | case GEU: | |
285 | fprintf (file, "cc"); | |
286 | break; | |
287 | case GTU: | |
288 | fprintf (file, "hi"); | |
289 | break; | |
290 | case LEU: | |
291 | fprintf (file, "ls"); | |
292 | break; | |
293 | case LTU: | |
294 | fprintf (file, "cs"); | |
295 | break; | |
296 | default: | |
cf41bb03 | 297 | gcc_unreachable (); |
29a404f9 | 298 | } |
299 | break; | |
300 | case 'C': | |
301 | /* This is used for the operand to a call instruction; | |
302 | if it's a REG, enclose it in parens, else output | |
303 | the operand normally. */ | |
304 | if (GET_CODE (x) == REG) | |
305 | { | |
306 | fputc ('(', file); | |
307 | print_operand (file, x, 0); | |
308 | fputc (')', file); | |
309 | } | |
310 | else | |
311 | print_operand (file, x, 0); | |
312 | break; | |
fb16c776 | 313 | |
b166356e | 314 | case 'D': |
315 | switch (GET_CODE (x)) | |
316 | { | |
317 | case MEM: | |
318 | fputc ('(', file); | |
319 | output_address (XEXP (x, 0)); | |
320 | fputc (')', file); | |
321 | break; | |
322 | ||
323 | case REG: | |
324 | fprintf (file, "fd%d", REGNO (x) - 18); | |
325 | break; | |
326 | ||
327 | default: | |
cf41bb03 | 328 | gcc_unreachable (); |
b166356e | 329 | } |
330 | break; | |
331 | ||
6ce19398 | 332 | /* These are the least significant word in a 64bit value. */ |
333 | case 'L': | |
334 | switch (GET_CODE (x)) | |
335 | { | |
336 | case MEM: | |
337 | fputc ('(', file); | |
338 | output_address (XEXP (x, 0)); | |
339 | fputc (')', file); | |
340 | break; | |
341 | ||
342 | case REG: | |
343 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
344 | break; | |
345 | ||
346 | case SUBREG: | |
701e46d0 | 347 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
6ce19398 | 348 | break; |
349 | ||
350 | case CONST_DOUBLE: | |
351 | { | |
352 | long val[2]; | |
353 | REAL_VALUE_TYPE rv; | |
354 | ||
355 | switch (GET_MODE (x)) | |
356 | { | |
357 | case DFmode: | |
358 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
359 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 360 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 361 | break;; |
362 | case SFmode: | |
363 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
364 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
ad3c0f03 | 365 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 366 | break;; |
367 | case VOIDmode: | |
368 | case DImode: | |
369 | print_operand_address (file, | |
370 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
371 | break; | |
59086782 | 372 | default: |
373 | break; | |
6ce19398 | 374 | } |
375 | break; | |
376 | } | |
377 | ||
378 | case CONST_INT: | |
964d057c | 379 | { |
380 | rtx low, high; | |
381 | split_double (x, &low, &high); | |
382 | fprintf (file, "%ld", (long)INTVAL (low)); | |
383 | break; | |
384 | } | |
6ce19398 | 385 | |
386 | default: | |
cf41bb03 | 387 | gcc_unreachable (); |
6ce19398 | 388 | } |
389 | break; | |
390 | ||
391 | /* Similarly, but for the most significant word. */ | |
392 | case 'H': | |
393 | switch (GET_CODE (x)) | |
394 | { | |
395 | case MEM: | |
396 | fputc ('(', file); | |
eafc6604 | 397 | x = adjust_address (x, SImode, 4); |
6ce19398 | 398 | output_address (XEXP (x, 0)); |
399 | fputc (')', file); | |
400 | break; | |
401 | ||
402 | case REG: | |
403 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
404 | break; | |
405 | ||
406 | case SUBREG: | |
701e46d0 | 407 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
6ce19398 | 408 | break; |
409 | ||
410 | case CONST_DOUBLE: | |
411 | { | |
412 | long val[2]; | |
413 | REAL_VALUE_TYPE rv; | |
414 | ||
415 | switch (GET_MODE (x)) | |
416 | { | |
417 | case DFmode: | |
418 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
419 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 420 | fprintf (file, "0x%lx", val[1]); |
6ce19398 | 421 | break;; |
422 | case SFmode: | |
cf41bb03 | 423 | gcc_unreachable (); |
6ce19398 | 424 | case VOIDmode: |
425 | case DImode: | |
fb16c776 | 426 | print_operand_address (file, |
6ce19398 | 427 | GEN_INT (CONST_DOUBLE_HIGH (x))); |
428 | break; | |
59086782 | 429 | default: |
430 | break; | |
6ce19398 | 431 | } |
432 | break; | |
433 | } | |
434 | ||
435 | case CONST_INT: | |
964d057c | 436 | { |
437 | rtx low, high; | |
438 | split_double (x, &low, &high); | |
439 | fprintf (file, "%ld", (long)INTVAL (high)); | |
440 | break; | |
441 | } | |
442 | ||
6ce19398 | 443 | default: |
cf41bb03 | 444 | gcc_unreachable (); |
6ce19398 | 445 | } |
446 | break; | |
447 | ||
448 | case 'A': | |
449 | fputc ('(', file); | |
450 | if (GET_CODE (XEXP (x, 0)) == REG) | |
bcd9bd66 | 451 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx)); |
6ce19398 | 452 | else |
453 | output_address (XEXP (x, 0)); | |
454 | fputc (')', file); | |
455 | break; | |
456 | ||
167fa942 | 457 | case 'N': |
cf41bb03 | 458 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
058f71f0 | 459 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); |
460 | break; | |
461 | ||
462 | case 'U': | |
cf41bb03 | 463 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
058f71f0 | 464 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); |
167fa942 | 465 | break; |
466 | ||
63e678f2 | 467 | /* For shift counts. The hardware ignores the upper bits of |
468 | any immediate, but the assembler will flag an out of range | |
469 | shift count as an error. So we mask off the high bits | |
470 | of the immediate here. */ | |
471 | case 'S': | |
472 | if (GET_CODE (x) == CONST_INT) | |
473 | { | |
058f71f0 | 474 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
63e678f2 | 475 | break; |
476 | } | |
477 | /* FALL THROUGH */ | |
478 | ||
29a404f9 | 479 | default: |
480 | switch (GET_CODE (x)) | |
481 | { | |
482 | case MEM: | |
483 | fputc ('(', file); | |
484 | output_address (XEXP (x, 0)); | |
485 | fputc (')', file); | |
486 | break; | |
487 | ||
6ce19398 | 488 | case PLUS: |
489 | output_address (x); | |
490 | break; | |
491 | ||
29a404f9 | 492 | case REG: |
493 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
494 | break; | |
495 | ||
496 | case SUBREG: | |
701e46d0 | 497 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
29a404f9 | 498 | break; |
499 | ||
6ce19398 | 500 | /* This will only be single precision.... */ |
501 | case CONST_DOUBLE: | |
502 | { | |
503 | unsigned long val; | |
504 | REAL_VALUE_TYPE rv; | |
505 | ||
506 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
507 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
ad3c0f03 | 508 | fprintf (file, "0x%lx", val); |
6ce19398 | 509 | break; |
510 | } | |
511 | ||
29a404f9 | 512 | case CONST_INT: |
513 | case SYMBOL_REF: | |
514 | case CONST: | |
515 | case LABEL_REF: | |
516 | case CODE_LABEL: | |
b87a151a | 517 | case UNSPEC: |
29a404f9 | 518 | print_operand_address (file, x); |
519 | break; | |
520 | default: | |
cf41bb03 | 521 | gcc_unreachable (); |
29a404f9 | 522 | } |
523 | break; | |
524 | } | |
525 | } | |
526 | ||
527 | /* Output assembly language output for the address ADDR to FILE. */ | |
528 | ||
529 | void | |
3285410a | 530 | print_operand_address (FILE *file, rtx addr) |
29a404f9 | 531 | { |
532 | switch (GET_CODE (addr)) | |
533 | { | |
911517ac | 534 | case POST_INC: |
535 | print_operand_address (file, XEXP (addr, 0)); | |
536 | fputc ('+', file); | |
537 | break; | |
29a404f9 | 538 | case REG: |
49fd1b62 | 539 | print_operand (file, addr, 0); |
29a404f9 | 540 | break; |
541 | case PLUS: | |
542 | { | |
543 | rtx base, index; | |
544 | if (REG_P (XEXP (addr, 0)) | |
545 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
546 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
547 | else if (REG_P (XEXP (addr, 1)) | |
548 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
549 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
550 | else | |
cf41bb03 | 551 | gcc_unreachable (); |
29a404f9 | 552 | print_operand (file, index, 0); |
553 | fputc (',', file); | |
554 | print_operand (file, base, 0);; | |
555 | break; | |
556 | } | |
557 | case SYMBOL_REF: | |
558 | output_addr_const (file, addr); | |
559 | break; | |
560 | default: | |
561 | output_addr_const (file, addr); | |
562 | break; | |
563 | } | |
564 | } | |
565 | ||
b166356e | 566 | /* Count the number of FP registers that have to be saved. */ |
567 | static int | |
3285410a | 568 | fp_regs_to_save (void) |
b166356e | 569 | { |
570 | int i, n = 0; | |
571 | ||
572 | if (! TARGET_AM33_2) | |
573 | return 0; | |
574 | ||
575 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
d37e81ec | 576 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
b166356e | 577 | ++n; |
578 | ||
579 | return n; | |
580 | } | |
581 | ||
4caa3669 | 582 | /* Print a set of registers in the format required by "movm" and "ret". |
583 | Register K is saved if bit K of MASK is set. The data and address | |
584 | registers can be stored individually, but the extended registers cannot. | |
f2b32076 | 585 | We assume that the mask already takes that into account. For instance, |
09e5ce26 | 586 | bits 14 to 17 must have the same value. */ |
4caa3669 | 587 | |
588 | void | |
3285410a | 589 | mn10300_print_reg_list (FILE *file, int mask) |
4caa3669 | 590 | { |
591 | int need_comma; | |
592 | int i; | |
593 | ||
594 | need_comma = 0; | |
595 | fputc ('[', file); | |
596 | ||
597 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
598 | if ((mask & (1 << i)) != 0) | |
599 | { | |
600 | if (need_comma) | |
601 | fputc (',', file); | |
602 | fputs (reg_names [i], file); | |
603 | need_comma = 1; | |
604 | } | |
605 | ||
606 | if ((mask & 0x3c000) != 0) | |
607 | { | |
cf41bb03 | 608 | gcc_assert ((mask & 0x3c000) == 0x3c000); |
4caa3669 | 609 | if (need_comma) |
610 | fputc (',', file); | |
611 | fputs ("exreg1", file); | |
612 | need_comma = 1; | |
613 | } | |
614 | ||
615 | fputc (']', file); | |
616 | } | |
617 | ||
6ce19398 | 618 | int |
3285410a | 619 | can_use_return_insn (void) |
6ce19398 | 620 | { |
36ed4406 | 621 | /* size includes the fixed stack space needed for function calls. */ |
abe32cce | 622 | int size = get_frame_size () + crtl->outgoing_args_size; |
36ed4406 | 623 | |
624 | /* And space for the return pointer. */ | |
abe32cce | 625 | size += crtl->outgoing_args_size ? 4 : 0; |
6ce19398 | 626 | |
627 | return (reload_completed | |
628 | && size == 0 | |
3072d30e | 629 | && !df_regs_ever_live_p (2) |
630 | && !df_regs_ever_live_p (3) | |
631 | && !df_regs_ever_live_p (6) | |
632 | && !df_regs_ever_live_p (7) | |
633 | && !df_regs_ever_live_p (14) | |
634 | && !df_regs_ever_live_p (15) | |
635 | && !df_regs_ever_live_p (16) | |
636 | && !df_regs_ever_live_p (17) | |
b166356e | 637 | && fp_regs_to_save () == 0 |
6ce19398 | 638 | && !frame_pointer_needed); |
639 | } | |
640 | ||
4caa3669 | 641 | /* Returns the set of live, callee-saved registers as a bitmask. The |
642 | callee-saved extended registers cannot be stored individually, so | |
09e5ce26 | 643 | all of them will be included in the mask if any one of them is used. */ |
4caa3669 | 644 | |
645 | int | |
3285410a | 646 | mn10300_get_live_callee_saved_regs (void) |
4caa3669 | 647 | { |
648 | int mask; | |
649 | int i; | |
650 | ||
651 | mask = 0; | |
b166356e | 652 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
d37e81ec | 653 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
4caa3669 | 654 | mask |= (1 << i); |
655 | if ((mask & 0x3c000) != 0) | |
656 | mask |= 0x3c000; | |
657 | ||
658 | return mask; | |
659 | } | |
660 | ||
661 | /* Generate an instruction that pushes several registers onto the stack. | |
662 | Register K will be saved if bit K in MASK is set. The function does | |
663 | nothing if MASK is zero. | |
664 | ||
665 | To be compatible with the "movm" instruction, the lowest-numbered | |
666 | register must be stored in the lowest slot. If MASK is the set | |
667 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
668 | instruction will have the form: | |
669 | ||
670 | (parallel | |
671 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
672 | (set (mem:SI (plus:SI (reg:SI 9) | |
673 | (const_int -1*4))) | |
674 | (reg:SI RN)) | |
675 | ... | |
676 | (set (mem:SI (plus:SI (reg:SI 9) | |
677 | (const_int -N*4))) | |
678 | (reg:SI R1))) */ | |
679 | ||
680 | void | |
3285410a | 681 | mn10300_gen_multiple_store (int mask) |
4caa3669 | 682 | { |
683 | if (mask != 0) | |
684 | { | |
685 | int i; | |
686 | int count; | |
687 | rtx par; | |
688 | int pari; | |
689 | ||
09e5ce26 | 690 | /* Count how many registers need to be saved. */ |
4caa3669 | 691 | count = 0; |
b166356e | 692 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
4caa3669 | 693 | if ((mask & (1 << i)) != 0) |
694 | count += 1; | |
695 | ||
696 | /* We need one PARALLEL element to update the stack pointer and | |
09e5ce26 | 697 | an additional element for each register that is stored. */ |
4caa3669 | 698 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
699 | ||
09e5ce26 | 700 | /* Create the instruction that updates the stack pointer. */ |
4caa3669 | 701 | XVECEXP (par, 0, 0) |
702 | = gen_rtx_SET (SImode, | |
703 | stack_pointer_rtx, | |
704 | gen_rtx_PLUS (SImode, | |
705 | stack_pointer_rtx, | |
706 | GEN_INT (-count * 4))); | |
707 | ||
09e5ce26 | 708 | /* Create each store. */ |
4caa3669 | 709 | pari = 1; |
b166356e | 710 | for (i = LAST_EXTENDED_REGNUM; i >= 0; i--) |
4caa3669 | 711 | if ((mask & (1 << i)) != 0) |
712 | { | |
713 | rtx address = gen_rtx_PLUS (SImode, | |
714 | stack_pointer_rtx, | |
715 | GEN_INT (-pari * 4)); | |
716 | XVECEXP(par, 0, pari) | |
717 | = gen_rtx_SET (VOIDmode, | |
718 | gen_rtx_MEM (SImode, address), | |
719 | gen_rtx_REG (SImode, i)); | |
720 | pari += 1; | |
721 | } | |
722 | ||
723 | par = emit_insn (par); | |
724 | RTX_FRAME_RELATED_P (par) = 1; | |
725 | } | |
726 | } | |
727 | ||
29a404f9 | 728 | void |
3285410a | 729 | expand_prologue (void) |
29a404f9 | 730 | { |
e3f95b40 | 731 | HOST_WIDE_INT size; |
f1899bff | 732 | |
f1899bff | 733 | /* SIZE includes the fixed stack space needed for function calls. */ |
abe32cce | 734 | size = get_frame_size () + crtl->outgoing_args_size; |
735 | size += (crtl->outgoing_args_size ? 4 : 0); | |
29a404f9 | 736 | |
09e5ce26 | 737 | /* If we use any of the callee-saved registers, save them now. */ |
4caa3669 | 738 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); |
48cb86e3 | 739 | |
b166356e | 740 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
741 | { | |
742 | int num_regs_to_save = fp_regs_to_save (), i; | |
743 | HOST_WIDE_INT xsize; | |
744 | enum { save_sp_merge, | |
745 | save_sp_no_merge, | |
746 | save_sp_partial_merge, | |
747 | save_a0_merge, | |
748 | save_a0_no_merge } strategy; | |
749 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; | |
750 | rtx reg; | |
751 | rtx insn; | |
752 | ||
753 | /* We have several different strategies to save FP registers. | |
754 | We can store them using SP offsets, which is beneficial if | |
755 | there are just a few registers to save, or we can use `a0' in | |
756 | post-increment mode (`a0' is the only call-clobbered address | |
757 | register that is never used to pass information to a | |
758 | function). Furthermore, if we don't need a frame pointer, we | |
759 | can merge the two SP adds into a single one, but this isn't | |
760 | always beneficial; sometimes we can just split the two adds | |
761 | so that we don't exceed a 16-bit constant size. The code | |
762 | below will select which strategy to use, so as to generate | |
763 | smallest code. Ties are broken in favor or shorter sequences | |
764 | (in terms of number of instructions). */ | |
765 | ||
766 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
767 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
768 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
769 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
770 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ | |
771 | (((S) >= (L)) ? (SIZE1) * (N) \ | |
772 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ | |
773 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
774 | : (ELSE)) | |
775 | #define SIZE_FMOV_SP_(S,N) \ | |
776 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
777 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
778 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
779 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
780 | ||
781 | /* Consider alternative save_sp_merge only if we don't need the | |
fa483857 | 782 | frame pointer and size is nonzero. */ |
b166356e | 783 | if (! frame_pointer_needed && size) |
784 | { | |
785 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
786 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
787 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
788 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
789 | ||
790 | if (this_strategy_size < strategy_size) | |
791 | { | |
792 | strategy = save_sp_merge; | |
793 | strategy_size = this_strategy_size; | |
794 | } | |
795 | } | |
796 | ||
797 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
798 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
799 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
800 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
801 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
802 | if (size) | |
803 | { | |
804 | /* Insn: add -size, sp. */ | |
805 | this_strategy_size += SIZE_ADD_SP (-size); | |
806 | } | |
807 | ||
808 | if (this_strategy_size < strategy_size) | |
809 | { | |
810 | strategy = save_sp_no_merge; | |
811 | strategy_size = this_strategy_size; | |
812 | } | |
813 | ||
814 | /* Consider alternative save_sp_partial_merge only if we don't | |
815 | need a frame pointer and size is reasonably large. */ | |
816 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
817 | { | |
818 | /* Insn: add -128, sp. */ | |
819 | this_strategy_size = SIZE_ADD_SP (-128); | |
820 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
821 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
822 | num_regs_to_save); | |
823 | if (size) | |
824 | { | |
825 | /* Insn: add 128-size, sp. */ | |
826 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
827 | } | |
828 | ||
829 | if (this_strategy_size < strategy_size) | |
830 | { | |
831 | strategy = save_sp_partial_merge; | |
832 | strategy_size = this_strategy_size; | |
833 | } | |
834 | } | |
835 | ||
836 | /* Consider alternative save_a0_merge only if we don't need a | |
fa483857 | 837 | frame pointer, size is nonzero and the user hasn't |
b166356e | 838 | changed the calling conventions of a0. */ |
839 | if (! frame_pointer_needed && size | |
d37e81ec | 840 | && call_really_used_regs [FIRST_ADDRESS_REGNUM] |
b166356e | 841 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
842 | { | |
843 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
844 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
845 | /* Insn: mov sp, a0. */ | |
846 | this_strategy_size++; | |
847 | if (size) | |
848 | { | |
849 | /* Insn: add size, a0. */ | |
850 | this_strategy_size += SIZE_ADD_AX (size); | |
851 | } | |
852 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
853 | this_strategy_size += 3 * num_regs_to_save; | |
854 | ||
855 | if (this_strategy_size < strategy_size) | |
856 | { | |
857 | strategy = save_a0_merge; | |
858 | strategy_size = this_strategy_size; | |
859 | } | |
860 | } | |
861 | ||
862 | /* Consider alternative save_a0_no_merge if the user hasn't | |
09e5ce26 | 863 | changed the calling conventions of a0. */ |
d37e81ec | 864 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM] |
b166356e | 865 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
866 | { | |
867 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
868 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
869 | /* Insn: mov sp, a0. */ | |
870 | this_strategy_size++; | |
871 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
872 | this_strategy_size += 3 * num_regs_to_save; | |
873 | if (size) | |
874 | { | |
875 | /* Insn: add -size, sp. */ | |
876 | this_strategy_size += SIZE_ADD_SP (-size); | |
877 | } | |
878 | ||
879 | if (this_strategy_size < strategy_size) | |
880 | { | |
881 | strategy = save_a0_no_merge; | |
882 | strategy_size = this_strategy_size; | |
883 | } | |
884 | } | |
885 | ||
886 | /* Emit the initial SP add, common to all strategies. */ | |
887 | switch (strategy) | |
888 | { | |
889 | case save_sp_no_merge: | |
890 | case save_a0_no_merge: | |
891 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
892 | stack_pointer_rtx, | |
893 | GEN_INT (-4 * num_regs_to_save))); | |
894 | xsize = 0; | |
895 | break; | |
896 | ||
897 | case save_sp_partial_merge: | |
898 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
899 | stack_pointer_rtx, | |
900 | GEN_INT (-128))); | |
901 | xsize = 128 - 4 * num_regs_to_save; | |
902 | size -= xsize; | |
903 | break; | |
904 | ||
905 | case save_sp_merge: | |
906 | case save_a0_merge: | |
907 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
908 | stack_pointer_rtx, | |
909 | GEN_INT (-(size + 4 * num_regs_to_save)))); | |
910 | /* We'll have to adjust FP register saves according to the | |
09e5ce26 | 911 | frame size. */ |
b166356e | 912 | xsize = size; |
913 | /* Since we've already created the stack frame, don't do it | |
09e5ce26 | 914 | again at the end of the function. */ |
b166356e | 915 | size = 0; |
916 | break; | |
917 | ||
918 | default: | |
cf41bb03 | 919 | gcc_unreachable (); |
b166356e | 920 | } |
fb16c776 | 921 | |
b166356e | 922 | /* Now prepare register a0, if we have decided to use it. */ |
923 | switch (strategy) | |
924 | { | |
925 | case save_sp_merge: | |
926 | case save_sp_no_merge: | |
927 | case save_sp_partial_merge: | |
928 | reg = 0; | |
929 | break; | |
930 | ||
931 | case save_a0_merge: | |
932 | case save_a0_no_merge: | |
933 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
934 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
935 | if (xsize) | |
936 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))); | |
937 | reg = gen_rtx_POST_INC (SImode, reg); | |
938 | break; | |
fb16c776 | 939 | |
b166356e | 940 | default: |
cf41bb03 | 941 | gcc_unreachable (); |
b166356e | 942 | } |
fb16c776 | 943 | |
b166356e | 944 | /* Now actually save the FP registers. */ |
945 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
d37e81ec | 946 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
b166356e | 947 | { |
948 | rtx addr; | |
949 | ||
950 | if (reg) | |
951 | addr = reg; | |
952 | else | |
953 | { | |
954 | /* If we aren't using `a0', use an SP offset. */ | |
955 | if (xsize) | |
956 | { | |
957 | addr = gen_rtx_PLUS (SImode, | |
958 | stack_pointer_rtx, | |
959 | GEN_INT (xsize)); | |
960 | } | |
961 | else | |
962 | addr = stack_pointer_rtx; | |
fb16c776 | 963 | |
b166356e | 964 | xsize += 4; |
965 | } | |
966 | ||
967 | insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr), | |
968 | gen_rtx_REG (SImode, i))); | |
969 | ||
970 | RTX_FRAME_RELATED_P (insn) = 1; | |
971 | } | |
972 | } | |
973 | ||
48cb86e3 | 974 | /* Now put the frame pointer into the frame pointer register. */ |
29a404f9 | 975 | if (frame_pointer_needed) |
014546df | 976 | emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); |
29a404f9 | 977 | |
48cb86e3 | 978 | /* Allocate stack for this frame. */ |
29a404f9 | 979 | if (size) |
980 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
981 | stack_pointer_rtx, | |
982 | GEN_INT (-size))); | |
3072d30e | 983 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
984 | emit_insn (gen_GOTaddr2picreg ()); | |
29a404f9 | 985 | } |
986 | ||
987 | void | |
3285410a | 988 | expand_epilogue (void) |
29a404f9 | 989 | { |
e3f95b40 | 990 | HOST_WIDE_INT size; |
f1899bff | 991 | |
f1899bff | 992 | /* SIZE includes the fixed stack space needed for function calls. */ |
abe32cce | 993 | size = get_frame_size () + crtl->outgoing_args_size; |
994 | size += (crtl->outgoing_args_size ? 4 : 0); | |
29a404f9 | 995 | |
b166356e | 996 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
997 | { | |
998 | int num_regs_to_save = fp_regs_to_save (), i; | |
999 | rtx reg = 0; | |
1000 | ||
1001 | /* We have several options to restore FP registers. We could | |
1002 | load them from SP offsets, but, if there are enough FP | |
1003 | registers to restore, we win if we use a post-increment | |
1004 | addressing mode. */ | |
1005 | ||
1006 | /* If we have a frame pointer, it's the best option, because we | |
1007 | already know it has the value we want. */ | |
1008 | if (frame_pointer_needed) | |
1009 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
1010 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
1011 | it's never used for return values. But only do so if it's | |
1012 | smaller than using SP offsets. */ | |
1013 | else | |
1014 | { | |
1015 | enum { restore_sp_post_adjust, | |
1016 | restore_sp_pre_adjust, | |
1017 | restore_sp_partial_adjust, | |
1018 | restore_a1 } strategy; | |
1019 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
1020 | ||
1021 | /* Consider using sp offsets before adjusting sp. */ | |
1022 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1023 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
1024 | /* If size is too large, we'll have to adjust SP with an | |
1025 | add. */ | |
1026 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1027 | { | |
1028 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
1029 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
1030 | } | |
1031 | /* If we don't have to restore any non-FP registers, | |
1032 | we'll be able to save one byte by using rets. */ | |
1033 | if (! REG_SAVE_BYTES) | |
1034 | this_strategy_size--; | |
1035 | ||
1036 | if (this_strategy_size < strategy_size) | |
1037 | { | |
1038 | strategy = restore_sp_post_adjust; | |
1039 | strategy_size = this_strategy_size; | |
1040 | } | |
1041 | ||
1042 | /* Consider using sp offsets after adjusting sp. */ | |
1043 | /* Insn: add size, sp. */ | |
1044 | this_strategy_size = SIZE_ADD_SP (size); | |
1045 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1046 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
1047 | /* We're going to use ret to release the FP registers | |
09e5ce26 | 1048 | save area, so, no savings. */ |
b166356e | 1049 | |
1050 | if (this_strategy_size < strategy_size) | |
1051 | { | |
1052 | strategy = restore_sp_pre_adjust; | |
1053 | strategy_size = this_strategy_size; | |
1054 | } | |
1055 | ||
1056 | /* Consider using sp offsets after partially adjusting sp. | |
1057 | When size is close to 32Kb, we may be able to adjust SP | |
1058 | with an imm16 add instruction while still using fmov | |
1059 | (d8,sp). */ | |
1060 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1061 | { | |
1062 | /* Insn: add size + 4 * num_regs_to_save | |
1063 | + REG_SAVE_BYTES - 252,sp. */ | |
1064 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save | |
1065 | + REG_SAVE_BYTES - 252); | |
1066 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ | |
1067 | this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES | |
1068 | - 4 * num_regs_to_save, | |
1069 | num_regs_to_save); | |
1070 | /* We're going to use ret to release the FP registers | |
09e5ce26 | 1071 | save area, so, no savings. */ |
b166356e | 1072 | |
1073 | if (this_strategy_size < strategy_size) | |
1074 | { | |
1075 | strategy = restore_sp_partial_adjust; | |
1076 | strategy_size = this_strategy_size; | |
1077 | } | |
1078 | } | |
1079 | ||
1080 | /* Consider using a1 in post-increment mode, as long as the | |
1081 | user hasn't changed the calling conventions of a1. */ | |
d37e81ec | 1082 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1] |
b166356e | 1083 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) |
1084 | { | |
1085 | /* Insn: mov sp,a1. */ | |
1086 | this_strategy_size = 1; | |
1087 | if (size) | |
1088 | { | |
1089 | /* Insn: add size,a1. */ | |
1090 | this_strategy_size += SIZE_ADD_AX (size); | |
1091 | } | |
1092 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1093 | this_strategy_size += 3 * num_regs_to_save; | |
1094 | /* If size is large enough, we may be able to save a | |
1095 | couple of bytes. */ | |
1096 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1097 | { | |
1098 | /* Insn: mov a1,sp. */ | |
1099 | this_strategy_size += 2; | |
1100 | } | |
1101 | /* If we don't have to restore any non-FP registers, | |
1102 | we'll be able to save one byte by using rets. */ | |
1103 | if (! REG_SAVE_BYTES) | |
1104 | this_strategy_size--; | |
1105 | ||
1106 | if (this_strategy_size < strategy_size) | |
1107 | { | |
1108 | strategy = restore_a1; | |
1109 | strategy_size = this_strategy_size; | |
1110 | } | |
1111 | } | |
1112 | ||
1113 | switch (strategy) | |
1114 | { | |
1115 | case restore_sp_post_adjust: | |
1116 | break; | |
1117 | ||
1118 | case restore_sp_pre_adjust: | |
1119 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1120 | stack_pointer_rtx, | |
1121 | GEN_INT (size))); | |
1122 | size = 0; | |
1123 | break; | |
1124 | ||
1125 | case restore_sp_partial_adjust: | |
1126 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1127 | stack_pointer_rtx, | |
1128 | GEN_INT (size + 4 * num_regs_to_save | |
1129 | + REG_SAVE_BYTES - 252))); | |
1130 | size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save; | |
1131 | break; | |
fb16c776 | 1132 | |
b166356e | 1133 | case restore_a1: |
1134 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1135 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1136 | if (size) | |
1137 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1138 | break; | |
1139 | ||
1140 | default: | |
cf41bb03 | 1141 | gcc_unreachable (); |
b166356e | 1142 | } |
1143 | } | |
1144 | ||
1145 | /* Adjust the selected register, if any, for post-increment. */ | |
1146 | if (reg) | |
1147 | reg = gen_rtx_POST_INC (SImode, reg); | |
1148 | ||
1149 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
d37e81ec | 1150 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
b166356e | 1151 | { |
1152 | rtx addr; | |
fb16c776 | 1153 | |
b166356e | 1154 | if (reg) |
1155 | addr = reg; | |
1156 | else if (size) | |
1157 | { | |
1158 | /* If we aren't using a post-increment register, use an | |
09e5ce26 | 1159 | SP offset. */ |
b166356e | 1160 | addr = gen_rtx_PLUS (SImode, |
1161 | stack_pointer_rtx, | |
1162 | GEN_INT (size)); | |
1163 | } | |
1164 | else | |
1165 | addr = stack_pointer_rtx; | |
1166 | ||
1167 | size += 4; | |
1168 | ||
1169 | emit_insn (gen_movsi (gen_rtx_REG (SImode, i), | |
1170 | gen_rtx_MEM (SImode, addr))); | |
1171 | } | |
1172 | ||
1173 | /* If we were using the restore_a1 strategy and the number of | |
1174 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1175 | to `sp', to avoid having to use `add' to adjust it. */ | |
1176 | if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255) | |
1177 | { | |
1178 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1179 | size = 0; | |
1180 | } | |
1181 | } | |
1182 | ||
461cabcc | 1183 | /* Maybe cut back the stack, except for the register save area. |
1184 | ||
1185 | If the frame pointer exists, then use the frame pointer to | |
1186 | cut back the stack. | |
1187 | ||
1188 | If the stack size + register save area is more than 255 bytes, | |
1189 | then the stack must be cut back here since the size + register | |
fb16c776 | 1190 | save size is too big for a ret/retf instruction. |
461cabcc | 1191 | |
1192 | Else leave it alone, it will be cut back as part of the | |
1193 | ret/retf instruction, or there wasn't any stack to begin with. | |
1194 | ||
dfd1079d | 1195 | Under no circumstances should the register save area be |
461cabcc | 1196 | deallocated here, that would leave a window where an interrupt |
1197 | could occur and trash the register save area. */ | |
29a404f9 | 1198 | if (frame_pointer_needed) |
1199 | { | |
29a404f9 | 1200 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
b21218d6 | 1201 | size = 0; |
1202 | } | |
55daf463 | 1203 | else if (size + REG_SAVE_BYTES > 255) |
b21218d6 | 1204 | { |
1205 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1206 | stack_pointer_rtx, | |
1207 | GEN_INT (size))); | |
1208 | size = 0; | |
29a404f9 | 1209 | } |
29a404f9 | 1210 | |
55daf463 | 1211 | /* Adjust the stack and restore callee-saved registers, if any. */ |
3072d30e | 1212 | if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1213 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1214 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1215 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
48cb86e3 | 1216 | || frame_pointer_needed) |
55daf463 | 1217 | emit_jump_insn (gen_return_internal_regs |
1218 | (GEN_INT (size + REG_SAVE_BYTES))); | |
48cb86e3 | 1219 | else |
55daf463 | 1220 | emit_jump_insn (gen_return_internal ()); |
29a404f9 | 1221 | } |
1222 | ||
1223 | /* Update the condition code from the insn. */ | |
1224 | ||
1225 | void | |
3285410a | 1226 | notice_update_cc (rtx body, rtx insn) |
29a404f9 | 1227 | { |
29a404f9 | 1228 | switch (get_attr_cc (insn)) |
1229 | { | |
1230 | case CC_NONE: | |
1231 | /* Insn does not affect CC at all. */ | |
1232 | break; | |
1233 | ||
1234 | case CC_NONE_0HIT: | |
1235 | /* Insn does not change CC, but the 0'th operand has been changed. */ | |
1236 | if (cc_status.value1 != 0 | |
ed420a25 | 1237 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
29a404f9 | 1238 | cc_status.value1 = 0; |
1239 | break; | |
1240 | ||
14058057 | 1241 | case CC_SET_ZN: |
ed420a25 | 1242 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
14058057 | 1243 | V,C are unusable. */ |
29a404f9 | 1244 | CC_STATUS_INIT; |
14058057 | 1245 | cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; |
ed420a25 | 1246 | cc_status.value1 = recog_data.operand[0]; |
29a404f9 | 1247 | break; |
1248 | ||
14058057 | 1249 | case CC_SET_ZNV: |
ed420a25 | 1250 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
14058057 | 1251 | C is unusable. */ |
45e3d109 | 1252 | CC_STATUS_INIT; |
14058057 | 1253 | cc_status.flags |= CC_NO_CARRY; |
ed420a25 | 1254 | cc_status.value1 = recog_data.operand[0]; |
45e3d109 | 1255 | break; |
1256 | ||
29a404f9 | 1257 | case CC_COMPARE: |
1258 | /* The insn is a compare instruction. */ | |
1259 | CC_STATUS_INIT; | |
1260 | cc_status.value1 = SET_SRC (body); | |
b166356e | 1261 | if (GET_CODE (cc_status.value1) == COMPARE |
1262 | && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode) | |
1263 | cc_status.mdep.fpCC = 1; | |
29a404f9 | 1264 | break; |
1265 | ||
1266 | case CC_CLOBBER: | |
1267 | /* Insn doesn't leave CC in a usable state. */ | |
1268 | CC_STATUS_INIT; | |
1269 | break; | |
45e3d109 | 1270 | |
1271 | default: | |
cf41bb03 | 1272 | gcc_unreachable (); |
29a404f9 | 1273 | } |
29a404f9 | 1274 | } |
1275 | ||
a2f10574 | 1276 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
4caa3669 | 1277 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1278 | parallel. If OP is a multiple store, return a mask indicating which | |
1279 | registers it saves. Return 0 otherwise. */ | |
1280 | ||
1281 | int | |
3285410a | 1282 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
4caa3669 | 1283 | { |
1284 | int count; | |
1285 | int mask; | |
1286 | int i; | |
1287 | unsigned int last; | |
1288 | rtx elt; | |
1289 | ||
1290 | count = XVECLEN (op, 0); | |
1291 | if (count < 2) | |
1292 | return 0; | |
1293 | ||
1294 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1295 | elt = XVECEXP (op, 0, 0); | |
1296 | if (GET_CODE (elt) != SET | |
1297 | || GET_CODE (SET_DEST (elt)) != REG | |
1298 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM | |
1299 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1300 | return 0; | |
1301 | ||
1302 | /* Check that A is the stack pointer and B is the expected stack size. | |
1303 | For OP to match, each subsequent instruction should push a word onto | |
1304 | the stack. We therefore expect the first instruction to create | |
09e5ce26 | 1305 | COUNT-1 stack slots. */ |
4caa3669 | 1306 | elt = SET_SRC (elt); |
1307 | if (GET_CODE (XEXP (elt, 0)) != REG | |
1308 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1309 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1310 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) | |
1311 | return 0; | |
1312 | ||
1313 | /* Now go through the rest of the vector elements. They must be | |
1314 | ordered so that the first instruction stores the highest-numbered | |
1315 | register to the highest stack slot and that subsequent instructions | |
1316 | store a lower-numbered register to the slot below. | |
1317 | ||
1318 | LAST keeps track of the smallest-numbered register stored so far. | |
09e5ce26 | 1319 | MASK is the set of stored registers. */ |
b166356e | 1320 | last = LAST_EXTENDED_REGNUM + 1; |
4caa3669 | 1321 | mask = 0; |
1322 | for (i = 1; i < count; i++) | |
1323 | { | |
09e5ce26 | 1324 | /* Check that element i is a (set (mem M) R) and that R is valid. */ |
4caa3669 | 1325 | elt = XVECEXP (op, 0, i); |
1326 | if (GET_CODE (elt) != SET | |
1327 | || GET_CODE (SET_DEST (elt)) != MEM | |
1328 | || GET_CODE (SET_SRC (elt)) != REG | |
1329 | || REGNO (SET_SRC (elt)) >= last) | |
1330 | return 0; | |
1331 | ||
1332 | /* R was OK, so provisionally add it to MASK. We return 0 in any | |
09e5ce26 | 1333 | case if the rest of the instruction has a flaw. */ |
4caa3669 | 1334 | last = REGNO (SET_SRC (elt)); |
1335 | mask |= (1 << last); | |
1336 | ||
1337 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1338 | elt = XEXP (SET_DEST (elt), 0); | |
1339 | if (GET_CODE (elt) != PLUS | |
1340 | || GET_CODE (XEXP (elt, 0)) != REG | |
1341 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1342 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1343 | || INTVAL (XEXP (elt, 1)) != -i * 4) | |
1344 | return 0; | |
1345 | } | |
1346 | ||
09e5ce26 | 1347 | /* All or none of the callee-saved extended registers must be in the set. */ |
4caa3669 | 1348 | if ((mask & 0x3c000) != 0 |
1349 | && (mask & 0x3c000) != 0x3c000) | |
1350 | return 0; | |
1351 | ||
1352 | return mask; | |
1353 | } | |
1354 | ||
29a404f9 | 1355 | /* What (if any) secondary registers are needed to move IN with mode |
8deb3959 | 1356 | MODE into a register in register class RCLASS. |
29a404f9 | 1357 | |
1358 | We might be able to simplify this. */ | |
1359 | enum reg_class | |
8deb3959 | 1360 | mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode, |
51149d85 | 1361 | rtx in) |
29a404f9 | 1362 | { |
8b8be022 | 1363 | rtx inner = in; |
1364 | ||
1365 | /* Strip off any SUBREG expressions from IN. Basically we want | |
1366 | to know if IN is a pseudo or (subreg (pseudo)) as those can | |
1367 | turn into MEMs during reload. */ | |
1368 | while (GET_CODE (inner) == SUBREG) | |
1369 | inner = SUBREG_REG (inner); | |
1370 | ||
29a404f9 | 1371 | /* Memory loads less than a full word wide can't have an |
1372 | address or stack pointer destination. They must use | |
1373 | a data register as an intermediate register. */ | |
79ea832f | 1374 | if ((GET_CODE (in) == MEM |
8b8be022 | 1375 | || (GET_CODE (inner) == REG |
1376 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER)) | |
29a404f9 | 1377 | && (mode == QImode || mode == HImode) |
8deb3959 | 1378 | && (rclass == ADDRESS_REGS || rclass == SP_REGS |
1379 | || rclass == SP_OR_ADDRESS_REGS)) | |
8ecf154e | 1380 | { |
911517ac | 1381 | if (TARGET_AM33) |
1382 | return DATA_OR_EXTENDED_REGS; | |
8ecf154e | 1383 | return DATA_REGS; |
1384 | } | |
29a404f9 | 1385 | |
1386 | /* We can't directly load sp + const_int into a data register; | |
1387 | we must use an address register as an intermediate. */ | |
8deb3959 | 1388 | if (rclass != SP_REGS |
1389 | && rclass != ADDRESS_REGS | |
1390 | && rclass != SP_OR_ADDRESS_REGS | |
1391 | && rclass != SP_OR_EXTENDED_REGS | |
1392 | && rclass != ADDRESS_OR_EXTENDED_REGS | |
1393 | && rclass != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
29a404f9 | 1394 | && (in == stack_pointer_rtx |
1395 | || (GET_CODE (in) == PLUS | |
48cb86e3 | 1396 | && (XEXP (in, 0) == stack_pointer_rtx |
1397 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
29a404f9 | 1398 | return ADDRESS_REGS; |
1399 | ||
19de5de1 | 1400 | if (GET_CODE (in) == PLUS |
1401 | && (XEXP (in, 0) == stack_pointer_rtx | |
1402 | || XEXP (in, 1) == stack_pointer_rtx)) | |
55f3f40f | 1403 | return GENERAL_REGS; |
fb16c776 | 1404 | |
8b8be022 | 1405 | if (TARGET_AM33_2 |
1406 | && rclass == FP_REGS) | |
b166356e | 1407 | { |
8b8be022 | 1408 | /* We can't load directly into an FP register from a |
1409 | constant address. */ | |
1410 | if (GET_CODE (in) == MEM | |
1411 | && CONSTANT_ADDRESS_P (XEXP (in, 0))) | |
1412 | return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS); | |
1413 | ||
1414 | /* Handle case were a pseudo may not get a hard register | |
1415 | but has an equivalent memory location defined. */ | |
1416 | if (GET_CODE (inner) == REG | |
1417 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER | |
1418 | && reg_equiv_mem [REGNO (inner)] | |
1419 | && CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0))) | |
1420 | return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS); | |
b166356e | 1421 | } |
1422 | ||
48cb86e3 | 1423 | /* Otherwise assume no secondary reloads are needed. */ |
1424 | return NO_REGS; | |
1425 | } | |
1426 | ||
1427 | int | |
3285410a | 1428 | initial_offset (int from, int to) |
48cb86e3 | 1429 | { |
f1899bff | 1430 | /* The difference between the argument pointer and the frame pointer |
1431 | is the size of the callee register save area. */ | |
48cb86e3 | 1432 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
29a404f9 | 1433 | { |
3072d30e | 1434 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1435 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1436 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1437 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
b166356e | 1438 | || fp_regs_to_save () |
48cb86e3 | 1439 | || frame_pointer_needed) |
b166356e | 1440 | return REG_SAVE_BYTES |
1441 | + 4 * fp_regs_to_save (); | |
48cb86e3 | 1442 | else |
bb4959a8 | 1443 | return 0; |
29a404f9 | 1444 | } |
1445 | ||
f1899bff | 1446 | /* The difference between the argument pointer and the stack pointer is |
1447 | the sum of the size of this function's frame, the callee register save | |
1448 | area, and the fixed stack space needed for function calls (if any). */ | |
48cb86e3 | 1449 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
1450 | { | |
3072d30e | 1451 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1452 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1453 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1454 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
b166356e | 1455 | || fp_regs_to_save () |
48cb86e3 | 1456 | || frame_pointer_needed) |
8ecf154e | 1457 | return (get_frame_size () + REG_SAVE_BYTES |
b166356e | 1458 | + 4 * fp_regs_to_save () |
abe32cce | 1459 | + (crtl->outgoing_args_size |
1460 | ? crtl->outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1461 | else |
36ed4406 | 1462 | return (get_frame_size () |
abe32cce | 1463 | + (crtl->outgoing_args_size |
1464 | ? crtl->outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1465 | } |
29a404f9 | 1466 | |
f1899bff | 1467 | /* The difference between the frame pointer and stack pointer is the sum |
1468 | of the size of this function's frame and the fixed stack space needed | |
1469 | for function calls (if any). */ | |
48cb86e3 | 1470 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
36ed4406 | 1471 | return (get_frame_size () |
abe32cce | 1472 | + (crtl->outgoing_args_size |
1473 | ? crtl->outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1474 | |
cf41bb03 | 1475 | gcc_unreachable (); |
29a404f9 | 1476 | } |
bb4959a8 | 1477 | |
6644435d | 1478 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
1479 | ||
f2d49d02 | 1480 | static bool |
fb80456a | 1481 | mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
f2d49d02 | 1482 | { |
1483 | /* Return values > 8 bytes in length in memory. */ | |
00b1da0e | 1484 | return (int_size_in_bytes (type) > 8 |
1485 | || int_size_in_bytes (type) == 0 | |
1486 | || TYPE_MODE (type) == BLKmode); | |
f2d49d02 | 1487 | } |
1488 | ||
bb4959a8 | 1489 | /* Flush the argument registers to the stack for a stdarg function; |
1490 | return the new argument pointer. */ | |
f2d49d02 | 1491 | static rtx |
3285410a | 1492 | mn10300_builtin_saveregs (void) |
bb4959a8 | 1493 | { |
ed554036 | 1494 | rtx offset, mem; |
bb4959a8 | 1495 | tree fntype = TREE_TYPE (current_function_decl); |
257d99c3 | 1496 | int argadj = ((!stdarg_p (fntype)) |
bb4959a8 | 1497 | ? UNITS_PER_WORD : 0); |
32c2fdea | 1498 | alias_set_type set = get_varargs_alias_set (); |
bb4959a8 | 1499 | |
1500 | if (argadj) | |
abe32cce | 1501 | offset = plus_constant (crtl->args.arg_offset_rtx, argadj); |
bb4959a8 | 1502 | else |
abe32cce | 1503 | offset = crtl->args.arg_offset_rtx; |
bb4959a8 | 1504 | |
abe32cce | 1505 | mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer); |
ab6ab77e | 1506 | set_mem_alias_set (mem, set); |
ed554036 | 1507 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1508 | ||
1509 | mem = gen_rtx_MEM (SImode, | |
abe32cce | 1510 | plus_constant (crtl->args.internal_arg_pointer, 4)); |
ab6ab77e | 1511 | set_mem_alias_set (mem, set); |
ed554036 | 1512 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1513 | ||
bb4959a8 | 1514 | return copy_to_reg (expand_binop (Pmode, add_optab, |
abe32cce | 1515 | crtl->args.internal_arg_pointer, |
bb4959a8 | 1516 | offset, 0, 0, OPTAB_LIB_WIDEN)); |
1517 | } | |
1518 | ||
8a58ed0a | 1519 | static void |
3285410a | 1520 | mn10300_va_start (tree valist, rtx nextarg) |
ed554036 | 1521 | { |
7ccc713a | 1522 | nextarg = expand_builtin_saveregs (); |
7df226a2 | 1523 | std_expand_builtin_va_start (valist, nextarg); |
ed554036 | 1524 | } |
1525 | ||
b981d932 | 1526 | /* Return true when a parameter should be passed by reference. */ |
1527 | ||
1528 | static bool | |
1529 | mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
fb80456a | 1530 | enum machine_mode mode, const_tree type, |
b981d932 | 1531 | bool named ATTRIBUTE_UNUSED) |
1532 | { | |
1533 | unsigned HOST_WIDE_INT size; | |
1534 | ||
1535 | if (type) | |
1536 | size = int_size_in_bytes (type); | |
1537 | else | |
1538 | size = GET_MODE_SIZE (mode); | |
1539 | ||
00b1da0e | 1540 | return (size > 8 || size == 0); |
b981d932 | 1541 | } |
1542 | ||
bb4959a8 | 1543 | /* Return an RTX to represent where a value with mode MODE will be returned |
e92d3ba8 | 1544 | from a function. If the result is NULL_RTX, the argument is pushed. */ |
bb4959a8 | 1545 | |
1546 | rtx | |
3285410a | 1547 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
1548 | tree type, int named ATTRIBUTE_UNUSED) | |
bb4959a8 | 1549 | { |
e92d3ba8 | 1550 | rtx result = NULL_RTX; |
bb4959a8 | 1551 | int size, align; |
1552 | ||
1553 | /* We only support using 2 data registers as argument registers. */ | |
1554 | int nregs = 2; | |
1555 | ||
1556 | /* Figure out the size of the object to be passed. */ | |
1557 | if (mode == BLKmode) | |
1558 | size = int_size_in_bytes (type); | |
1559 | else | |
1560 | size = GET_MODE_SIZE (mode); | |
1561 | ||
1562 | /* Figure out the alignment of the object to be passed. */ | |
1563 | align = size; | |
1564 | ||
1565 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1566 | ||
1567 | /* Don't pass this arg via a register if all the argument registers | |
1568 | are used up. */ | |
1569 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
e92d3ba8 | 1570 | return result; |
bb4959a8 | 1571 | |
1572 | /* Don't pass this arg via a register if it would be split between | |
1573 | registers and memory. */ | |
1574 | if (type == NULL_TREE | |
1575 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
e92d3ba8 | 1576 | return result; |
bb4959a8 | 1577 | |
1578 | switch (cum->nbytes / UNITS_PER_WORD) | |
1579 | { | |
1580 | case 0: | |
e92d3ba8 | 1581 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM); |
bb4959a8 | 1582 | break; |
1583 | case 1: | |
e92d3ba8 | 1584 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1); |
bb4959a8 | 1585 | break; |
1586 | default: | |
e92d3ba8 | 1587 | break; |
bb4959a8 | 1588 | } |
1589 | ||
1590 | return result; | |
1591 | } | |
1592 | ||
f054eb3c | 1593 | /* Return the number of bytes of registers to use for an argument passed |
1594 | partially in registers and partially in memory. */ | |
bb4959a8 | 1595 | |
f054eb3c | 1596 | static int |
1597 | mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1598 | tree type, bool named ATTRIBUTE_UNUSED) | |
bb4959a8 | 1599 | { |
1600 | int size, align; | |
1601 | ||
1602 | /* We only support using 2 data registers as argument registers. */ | |
1603 | int nregs = 2; | |
1604 | ||
1605 | /* Figure out the size of the object to be passed. */ | |
1606 | if (mode == BLKmode) | |
1607 | size = int_size_in_bytes (type); | |
1608 | else | |
1609 | size = GET_MODE_SIZE (mode); | |
1610 | ||
1611 | /* Figure out the alignment of the object to be passed. */ | |
1612 | align = size; | |
1613 | ||
1614 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1615 | ||
1616 | /* Don't pass this arg via a register if all the argument registers | |
1617 | are used up. */ | |
1618 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1619 | return 0; | |
1620 | ||
1621 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1622 | return 0; | |
1623 | ||
1624 | /* Don't pass this arg via a register if it would be split between | |
1625 | registers and memory. */ | |
1626 | if (type == NULL_TREE | |
1627 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1628 | return 0; | |
1629 | ||
f054eb3c | 1630 | return nregs * UNITS_PER_WORD - cum->nbytes; |
bb4959a8 | 1631 | } |
1632 | ||
00b1da0e | 1633 | /* Return the location of the function's value. This will be either |
1634 | $d0 for integer functions, $a0 for pointers, or a PARALLEL of both | |
1635 | $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that | |
1636 | we only return the PARALLEL for outgoing values; we do not want | |
1637 | callers relying on this extra copy. */ | |
1638 | ||
b6713ba6 | 1639 | static rtx |
1640 | mn10300_function_value (const_tree valtype, | |
1641 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
1642 | bool outgoing) | |
00b1da0e | 1643 | { |
1644 | rtx rv; | |
1645 | enum machine_mode mode = TYPE_MODE (valtype); | |
1646 | ||
1647 | if (! POINTER_TYPE_P (valtype)) | |
1648 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1649 | else if (! TARGET_PTR_A0D0 || ! outgoing | |
18d50ae6 | 1650 | || cfun->returns_struct) |
00b1da0e | 1651 | return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM); |
1652 | ||
1653 | rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2)); | |
1654 | XVECEXP (rv, 0, 0) | |
1655 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1656 | gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM), | |
1657 | GEN_INT (0)); | |
fb16c776 | 1658 | |
00b1da0e | 1659 | XVECEXP (rv, 0, 1) |
1660 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1661 | gen_rtx_REG (mode, FIRST_DATA_REGNUM), | |
1662 | GEN_INT (0)); | |
1663 | return rv; | |
1664 | } | |
1665 | ||
b6713ba6 | 1666 | /* Implements TARGET_LIBCALL_VALUE. */ |
1667 | ||
1668 | static rtx | |
1669 | mn10300_libcall_value (enum machine_mode mode, | |
1670 | const_rtx fun ATTRIBUTE_UNUSED) | |
1671 | { | |
1672 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1673 | } | |
1674 | ||
1675 | /* Implements FUNCTION_VALUE_REGNO_P. */ | |
1676 | ||
1677 | bool | |
1678 | mn10300_function_value_regno_p (const unsigned int regno) | |
1679 | { | |
1680 | return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM); | |
1681 | } | |
1682 | ||
bb4959a8 | 1683 | /* Output a tst insn. */ |
feb9af9f | 1684 | const char * |
3285410a | 1685 | output_tst (rtx operand, rtx insn) |
bb4959a8 | 1686 | { |
bb4959a8 | 1687 | rtx temp; |
1688 | int past_call = 0; | |
1689 | ||
1690 | /* We can save a byte if we can find a register which has the value | |
1691 | zero in it. */ | |
1692 | temp = PREV_INSN (insn); | |
6e90c6cd | 1693 | while (optimize && temp) |
bb4959a8 | 1694 | { |
1695 | rtx set; | |
1696 | ||
1697 | /* We allow the search to go through call insns. We record | |
1698 | the fact that we've past a CALL_INSN and reject matches which | |
1699 | use call clobbered registers. */ | |
1700 | if (GET_CODE (temp) == CODE_LABEL | |
1701 | || GET_CODE (temp) == JUMP_INSN | |
1702 | || GET_CODE (temp) == BARRIER) | |
1703 | break; | |
1704 | ||
1705 | if (GET_CODE (temp) == CALL_INSN) | |
1706 | past_call = 1; | |
1707 | ||
1708 | if (GET_CODE (temp) == NOTE) | |
1709 | { | |
1710 | temp = PREV_INSN (temp); | |
1711 | continue; | |
1712 | } | |
1713 | ||
09e5ce26 | 1714 | /* It must be an insn, see if it is a simple set. */ |
bb4959a8 | 1715 | set = single_set (temp); |
1716 | if (!set) | |
1717 | { | |
1718 | temp = PREV_INSN (temp); | |
1719 | continue; | |
1720 | } | |
1721 | ||
1722 | /* Are we setting a data register to zero (this does not win for | |
fb16c776 | 1723 | address registers)? |
bb4959a8 | 1724 | |
1725 | If it's a call clobbered register, have we past a call? | |
1726 | ||
1727 | Make sure the register we find isn't the same as ourself; | |
8ecf154e | 1728 | the mn10300 can't encode that. |
1729 | ||
1730 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1731 | so the code to detect calls here isn't doing anything useful. */ | |
bb4959a8 | 1732 | if (REG_P (SET_DEST (set)) |
1733 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1734 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
6e90c6cd | 1735 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1736 | == REGNO_REG_CLASS (REGNO (operand))) | |
911517ac | 1737 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1738 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
fb16c776 | 1739 | && (!past_call |
d37e81ec | 1740 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
911517ac | 1741 | { |
1742 | rtx xoperands[2]; | |
1743 | xoperands[0] = operand; | |
1744 | xoperands[1] = SET_DEST (set); | |
1745 | ||
1746 | output_asm_insn ("cmp %1,%0", xoperands); | |
1747 | return ""; | |
1748 | } | |
1749 | ||
1750 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1751 | && REG_P (SET_DEST (set)) | |
1752 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1753 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1754 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1755 | != REGNO_REG_CLASS (REGNO (operand))) | |
1756 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
bb4959a8 | 1757 | && REGNO (SET_DEST (set)) != REGNO (operand) |
fb16c776 | 1758 | && (!past_call |
d37e81ec | 1759 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
bb4959a8 | 1760 | { |
1761 | rtx xoperands[2]; | |
1762 | xoperands[0] = operand; | |
1763 | xoperands[1] = SET_DEST (set); | |
1764 | ||
1765 | output_asm_insn ("cmp %1,%0", xoperands); | |
1766 | return ""; | |
1767 | } | |
1768 | temp = PREV_INSN (temp); | |
1769 | } | |
1770 | return "cmp 0,%0"; | |
1771 | } | |
36ed4406 | 1772 | |
1773 | int | |
3285410a | 1774 | impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
36ed4406 | 1775 | { |
36ed4406 | 1776 | if (GET_CODE (op) != PLUS) |
1777 | return 0; | |
1778 | ||
19de5de1 | 1779 | if (XEXP (op, 0) == stack_pointer_rtx |
1780 | || XEXP (op, 1) == stack_pointer_rtx) | |
36ed4406 | 1781 | return 1; |
1782 | ||
36ed4406 | 1783 | return 0; |
1784 | } | |
c4cd8f6a | 1785 | |
9d3b5b5e | 1786 | /* Similarly, but when using a zero_extract pattern for a btst where |
1787 | the source operand might end up in memory. */ | |
1788 | int | |
3285410a | 1789 | mask_ok_for_mem_btst (int len, int bit) |
9d3b5b5e | 1790 | { |
805e22b2 | 1791 | unsigned int mask = 0; |
9d3b5b5e | 1792 | |
1793 | while (len > 0) | |
1794 | { | |
1795 | mask |= (1 << bit); | |
1796 | bit++; | |
1797 | len--; | |
1798 | } | |
1799 | ||
1800 | /* MASK must bit into an 8bit value. */ | |
1801 | return (((mask & 0xff) == mask) | |
1802 | || ((mask & 0xff00) == mask) | |
1803 | || ((mask & 0xff0000) == mask) | |
1804 | || ((mask & 0xff000000) == mask)); | |
1805 | } | |
1806 | ||
c4cd8f6a | 1807 | /* Return 1 if X contains a symbolic expression. We know these |
1808 | expressions will have one of a few well defined forms, so | |
1809 | we need only check those forms. */ | |
1810 | int | |
3285410a | 1811 | symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
c4cd8f6a | 1812 | { |
1813 | switch (GET_CODE (op)) | |
1814 | { | |
1815 | case SYMBOL_REF: | |
1816 | case LABEL_REF: | |
1817 | return 1; | |
1818 | case CONST: | |
1819 | op = XEXP (op, 0); | |
1820 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1821 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
1822 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
1823 | default: | |
1824 | return 0; | |
1825 | } | |
1826 | } | |
1827 | ||
1828 | /* Try machine dependent ways of modifying an illegitimate address | |
1829 | to be legitimate. If we find one, return the new valid address. | |
1830 | This macro is used in only one place: `memory_address' in explow.c. | |
1831 | ||
1832 | OLDX is the address as it was before break_out_memory_refs was called. | |
1833 | In some cases it is useful to look at this to decide what needs to be done. | |
1834 | ||
c4cd8f6a | 1835 | Normally it is always safe for this macro to do nothing. It exists to |
1836 | recognize opportunities to optimize the output. | |
1837 | ||
1838 | But on a few ports with segmented architectures and indexed addressing | |
1839 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
1840 | rtx | |
41e3a0c7 | 1841 | mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1842 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
c4cd8f6a | 1843 | { |
b87a151a | 1844 | if (flag_pic && ! legitimate_pic_operand_p (x)) |
1845 | x = legitimize_pic_address (oldx, NULL_RTX); | |
1846 | ||
c4cd8f6a | 1847 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1848 | special handling to avoid creating an indexed memory address | |
1849 | with x-100000 as the base. */ | |
1850 | if (GET_CODE (x) == PLUS | |
1851 | && symbolic_operand (XEXP (x, 1), VOIDmode)) | |
1852 | { | |
1853 | /* Ugly. We modify things here so that the address offset specified | |
1854 | by the index expression is computed first, then added to x to form | |
1855 | the entire address. */ | |
1856 | ||
59086782 | 1857 | rtx regx1, regy1, regy2, y; |
c4cd8f6a | 1858 | |
1859 | /* Strip off any CONST. */ | |
1860 | y = XEXP (x, 1); | |
1861 | if (GET_CODE (y) == CONST) | |
1862 | y = XEXP (y, 0); | |
1863 | ||
c927a8ab | 1864 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1865 | { | |
1866 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1867 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1868 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1869 | regx1 = force_reg (Pmode, | |
29bb088d | 1870 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, regy2)); |
7014838c | 1871 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
c927a8ab | 1872 | } |
c4cd8f6a | 1873 | } |
11b4605c | 1874 | return x; |
c4cd8f6a | 1875 | } |
e2aead91 | 1876 | |
b87a151a | 1877 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
09e5ce26 | 1878 | @GOTOFF in `reg'. */ |
b87a151a | 1879 | rtx |
3285410a | 1880 | legitimize_pic_address (rtx orig, rtx reg) |
b87a151a | 1881 | { |
1882 | if (GET_CODE (orig) == LABEL_REF | |
1883 | || (GET_CODE (orig) == SYMBOL_REF | |
1884 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1885 | || ! MN10300_GLOBAL_P (orig)))) | |
1886 | { | |
1887 | if (reg == 0) | |
1888 | reg = gen_reg_rtx (Pmode); | |
1889 | ||
1890 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
1891 | return reg; | |
1892 | } | |
1893 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1894 | { | |
1895 | if (reg == 0) | |
1896 | reg = gen_reg_rtx (Pmode); | |
1897 | ||
1898 | emit_insn (gen_symGOT2reg (reg, orig)); | |
1899 | return reg; | |
1900 | } | |
1901 | return orig; | |
1902 | } | |
1903 | ||
1904 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
fa483857 | 1905 | isn't protected by a PIC unspec; nonzero otherwise. */ |
b87a151a | 1906 | int |
3285410a | 1907 | legitimate_pic_operand_p (rtx x) |
b87a151a | 1908 | { |
1909 | register const char *fmt; | |
1910 | register int i; | |
1911 | ||
1912 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1913 | return 0; | |
1914 | ||
1915 | if (GET_CODE (x) == UNSPEC | |
1916 | && (XINT (x, 1) == UNSPEC_PIC | |
1917 | || XINT (x, 1) == UNSPEC_GOT | |
1918 | || XINT (x, 1) == UNSPEC_GOTOFF | |
b6e3379c | 1919 | || XINT (x, 1) == UNSPEC_PLT |
1920 | || XINT (x, 1) == UNSPEC_GOTSYM_OFF)) | |
b87a151a | 1921 | return 1; |
1922 | ||
b87a151a | 1923 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
1924 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1925 | { | |
1926 | if (fmt[i] == 'E') | |
1927 | { | |
1928 | register int j; | |
1929 | ||
1930 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1931 | if (! legitimate_pic_operand_p (XVECEXP (x, i, j))) | |
1932 | return 0; | |
1933 | } | |
1934 | else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i))) | |
1935 | return 0; | |
1936 | } | |
1937 | ||
1938 | return 1; | |
1939 | } | |
1940 | ||
5411aa8c | 1941 | /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is |
fd50b071 | 1942 | legitimate, and FALSE otherwise. |
1943 | ||
1944 | On the mn10300, the value in the address register must be | |
1945 | in the same memory space/segment as the effective address. | |
1946 | ||
1947 | This is problematical for reload since it does not understand | |
1948 | that base+index != index+base in a memory reference. | |
1949 | ||
1950 | Note it is still possible to use reg+reg addressing modes, | |
1951 | it's just much more difficult. For a discussion of a possible | |
1952 | workaround and solution, see the comments in pa.c before the | |
1953 | function record_unscaled_index_insn_codes. */ | |
1954 | ||
5411aa8c | 1955 | bool |
fd50b071 | 1956 | mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) |
5411aa8c | 1957 | { |
1958 | if (CONSTANT_ADDRESS_P (x) | |
1959 | && (! flag_pic || legitimate_pic_operand_p (x))) | |
1960 | return TRUE; | |
1961 | ||
1962 | if (RTX_OK_FOR_BASE_P (x, strict)) | |
1963 | return TRUE; | |
1964 | ||
1965 | if (TARGET_AM33 | |
1966 | && GET_CODE (x) == POST_INC | |
1967 | && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict) | |
1968 | && (mode == SImode || mode == SFmode || mode == HImode)) | |
1969 | return TRUE; | |
1970 | ||
1971 | if (GET_CODE (x) == PLUS) | |
1972 | { | |
1973 | rtx base = 0, index = 0; | |
1974 | ||
1975 | if (REG_P (XEXP (x, 0)) | |
1976 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict)) | |
1977 | { | |
1978 | base = XEXP (x, 0); | |
1979 | index = XEXP (x, 1); | |
1980 | } | |
1981 | ||
1982 | if (REG_P (XEXP (x, 1)) | |
1983 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict)) | |
1984 | { | |
1985 | base = XEXP (x, 1); | |
1986 | index = XEXP (x, 0); | |
1987 | } | |
1988 | ||
1989 | if (base != 0 && index != 0) | |
1990 | { | |
1991 | if (GET_CODE (index) == CONST_INT) | |
1992 | return TRUE; | |
1993 | if (GET_CODE (index) == CONST | |
9247cc1c | 1994 | && GET_CODE (XEXP (index, 0)) != PLUS |
5411aa8c | 1995 | && (! flag_pic |
1996 | || legitimate_pic_operand_p (index))) | |
1997 | return TRUE; | |
1998 | } | |
1999 | } | |
2000 | ||
2001 | return FALSE; | |
2002 | } | |
2003 | ||
ec0457a8 | 2004 | static int |
db65aa2c | 2005 | mn10300_address_cost_1 (rtx x, int *unsig) |
e2aead91 | 2006 | { |
e2aead91 | 2007 | switch (GET_CODE (x)) |
2008 | { | |
2009 | case REG: | |
2010 | switch (REGNO_REG_CLASS (REGNO (x))) | |
2011 | { | |
2012 | case SP_REGS: | |
2013 | *unsig = 1; | |
2014 | return 0; | |
2015 | ||
2016 | case ADDRESS_REGS: | |
2017 | return 1; | |
2018 | ||
2019 | case DATA_REGS: | |
2020 | case EXTENDED_REGS: | |
b166356e | 2021 | case FP_REGS: |
e2aead91 | 2022 | return 3; |
2023 | ||
2024 | case NO_REGS: | |
2025 | return 5; | |
2026 | ||
2027 | default: | |
cf41bb03 | 2028 | gcc_unreachable (); |
e2aead91 | 2029 | } |
2030 | ||
2031 | case PLUS: | |
2032 | case MINUS: | |
cbe23f2f | 2033 | case ASHIFT: |
2034 | case AND: | |
e2aead91 | 2035 | case IOR: |
ec0457a8 | 2036 | return (mn10300_address_cost_1 (XEXP (x, 0), unsig) |
2037 | + mn10300_address_cost_1 (XEXP (x, 1), unsig)); | |
e2aead91 | 2038 | |
2039 | case EXPR_LIST: | |
2040 | case SUBREG: | |
2041 | case MEM: | |
db65aa2c | 2042 | return mn10300_address_cost (XEXP (x, 0), !optimize_size); |
e2aead91 | 2043 | |
2044 | case ZERO_EXTEND: | |
2045 | *unsig = 1; | |
ec0457a8 | 2046 | return mn10300_address_cost_1 (XEXP (x, 0), unsig); |
e2aead91 | 2047 | |
2048 | case CONST_INT: | |
2049 | if (INTVAL (x) == 0) | |
2050 | return 0; | |
2051 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
2052 | return 1; | |
2053 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
2054 | return 3; | |
2055 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
2056 | return 5; | |
2057 | return 7; | |
2058 | ||
2059 | case CONST: | |
2060 | case SYMBOL_REF: | |
cbe23f2f | 2061 | case LABEL_REF: |
e2aead91 | 2062 | return 8; |
2063 | ||
e2aead91 | 2064 | default: |
cf41bb03 | 2065 | gcc_unreachable (); |
e2aead91 | 2066 | |
2067 | } | |
2068 | } | |
fab7adbf | 2069 | |
ec0457a8 | 2070 | static int |
f529eb25 | 2071 | mn10300_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED) |
ec0457a8 | 2072 | { |
2073 | int s = 0; | |
2074 | return mn10300_address_cost_1 (x, &s); | |
2075 | } | |
2076 | ||
fab7adbf | 2077 | static bool |
f529eb25 | 2078 | mn10300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed ATTRIBUTE_UNUSED) |
fab7adbf | 2079 | { |
2080 | switch (code) | |
2081 | { | |
2082 | case CONST_INT: | |
2083 | /* Zeros are extremely cheap. */ | |
74f4459c | 2084 | if (INTVAL (x) == 0 && (outer_code == SET || outer_code == COMPARE)) |
fab7adbf | 2085 | *total = 0; |
2086 | /* If it fits in 8 bits, then it's still relatively cheap. */ | |
2087 | else if (INT_8_BITS (INTVAL (x))) | |
2088 | *total = 1; | |
2089 | /* This is the "base" cost, includes constants where either the | |
2090 | upper or lower 16bits are all zeros. */ | |
2091 | else if (INT_16_BITS (INTVAL (x)) | |
2092 | || (INTVAL (x) & 0xffff) == 0 | |
2093 | || (INTVAL (x) & 0xffff0000) == 0) | |
2094 | *total = 2; | |
2095 | else | |
2096 | *total = 4; | |
2097 | return true; | |
2098 | ||
2099 | case CONST: | |
2100 | case LABEL_REF: | |
2101 | case SYMBOL_REF: | |
2102 | /* These are more costly than a CONST_INT, but we can relax them, | |
2103 | so they're less costly than a CONST_DOUBLE. */ | |
2104 | *total = 6; | |
2105 | return true; | |
2106 | ||
2107 | case CONST_DOUBLE: | |
2108 | /* We don't optimize CONST_DOUBLEs well nor do we relax them well, | |
2109 | so their cost is very high. */ | |
2110 | *total = 8; | |
2111 | return true; | |
2112 | ||
74f4459c | 2113 | case ZERO_EXTRACT: |
2114 | /* This is cheap, we can use btst. */ | |
2115 | if (outer_code == COMPARE) | |
2116 | *total = 0; | |
2117 | return false; | |
2118 | ||
fab7adbf | 2119 | /* ??? This probably needs more work. */ |
2120 | case MOD: | |
2121 | case DIV: | |
2122 | case MULT: | |
2123 | *total = 8; | |
2124 | return true; | |
2125 | ||
2126 | default: | |
2127 | return false; | |
2128 | } | |
2129 | } | |
8935d57c | 2130 | |
2131 | /* Check whether a constant used to initialize a DImode or DFmode can | |
2132 | use a clr instruction. The code here must be kept in sync with | |
2133 | movdf and movdi. */ | |
2134 | ||
2135 | bool | |
3285410a | 2136 | mn10300_wide_const_load_uses_clr (rtx operands[2]) |
8935d57c | 2137 | { |
2138 | long val[2]; | |
2139 | ||
2140 | if (GET_CODE (operands[0]) != REG | |
2141 | || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS) | |
2142 | return false; | |
2143 | ||
2144 | switch (GET_CODE (operands[1])) | |
2145 | { | |
2146 | case CONST_INT: | |
2147 | { | |
2148 | rtx low, high; | |
2149 | split_double (operands[1], &low, &high); | |
2150 | val[0] = INTVAL (low); | |
2151 | val[1] = INTVAL (high); | |
2152 | } | |
2153 | break; | |
fb16c776 | 2154 | |
8935d57c | 2155 | case CONST_DOUBLE: |
2156 | if (GET_MODE (operands[1]) == DFmode) | |
2157 | { | |
2158 | REAL_VALUE_TYPE rv; | |
2159 | ||
2160 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
2161 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
2162 | } | |
2163 | else if (GET_MODE (operands[1]) == VOIDmode | |
2164 | || GET_MODE (operands[1]) == DImode) | |
2165 | { | |
2166 | val[0] = CONST_DOUBLE_LOW (operands[1]); | |
2167 | val[1] = CONST_DOUBLE_HIGH (operands[1]); | |
2168 | } | |
2169 | break; | |
fb16c776 | 2170 | |
8935d57c | 2171 | default: |
2172 | return false; | |
2173 | } | |
2174 | ||
2175 | return val[0] == 0 || val[1] == 0; | |
2176 | } | |
b87a151a | 2177 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2178 | may access it using GOTOFF instead of GOT. */ | |
2179 | ||
2180 | static void | |
48ed5fc2 | 2181 | mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED) |
b87a151a | 2182 | { |
2183 | rtx symbol; | |
2184 | ||
2185 | if (GET_CODE (rtl) != MEM) | |
2186 | return; | |
2187 | symbol = XEXP (rtl, 0); | |
2188 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2189 | return; | |
2190 | ||
2191 | if (flag_pic) | |
2192 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2193 | } | |
906bb5c3 | 2194 | |
2195 | /* Dispatch tables on the mn10300 are extremely expensive in terms of code | |
2196 | and readonly data size. So we crank up the case threshold value to | |
2197 | encourage a series of if/else comparisons to implement many small switch | |
2198 | statements. In theory, this value could be increased much more if we | |
2199 | were solely optimizing for space, but we keep it "reasonable" to avoid | |
2200 | serious code efficiency lossage. */ | |
2201 | ||
2202 | unsigned int mn10300_case_values_threshold (void) | |
2203 | { | |
2204 | return 6; | |
2205 | } | |
3e16f982 | 2206 | |
2207 | /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE. */ | |
2208 | ||
2209 | static void | |
2210 | mn10300_asm_trampoline_template (FILE *f) | |
2211 | { | |
2212 | fprintf (f, "\tadd -4,sp\n"); | |
2213 | fprintf (f, "\t.long 0x0004fffa\n"); | |
2214 | fprintf (f, "\tmov (0,sp),a0\n"); | |
2215 | fprintf (f, "\tadd 4,sp\n"); | |
2216 | fprintf (f, "\tmov (13,a0),a1\n"); | |
2217 | fprintf (f, "\tmov (17,a0),a0\n"); | |
2218 | fprintf (f, "\tjmp (a0)\n"); | |
2219 | fprintf (f, "\t.long 0\n"); | |
2220 | fprintf (f, "\t.long 0\n"); | |
2221 | } | |
2222 | ||
2223 | /* Worker function for TARGET_TRAMPOLINE_INIT. */ | |
2224 | ||
2225 | static void | |
2226 | mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2227 | { | |
2228 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
2229 | rtx mem; | |
2230 | ||
2231 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
2232 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
2233 | ||
2234 | mem = adjust_address (m_tramp, SImode, 0x14); | |
2235 | emit_move_insn (mem, chain_value); | |
2236 | mem = adjust_address (m_tramp, SImode, 0x18); | |
2237 | emit_move_insn (mem, fnaddr); | |
2238 | } | |
e92d3ba8 | 2239 | |
2240 | /* Output the assembler code for a C++ thunk function. | |
2241 | THUNK_DECL is the declaration for the thunk function itself, FUNCTION | |
2242 | is the decl for the target function. DELTA is an immediate constant | |
2243 | offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero | |
2244 | the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be | |
2245 | additionally added to THIS. Finally jump to the entry point of | |
2246 | FUNCTION. */ | |
2247 | ||
2248 | static void | |
2249 | mn10300_asm_output_mi_thunk (FILE * file, | |
2250 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2251 | HOST_WIDE_INT delta, | |
2252 | HOST_WIDE_INT vcall_offset, | |
2253 | tree function) | |
2254 | { | |
2255 | const char * _this; | |
2256 | ||
2257 | /* Get the register holding the THIS parameter. Handle the case | |
2258 | where there is a hidden first argument for a returned structure. */ | |
2259 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
2260 | _this = reg_names [FIRST_ARGUMENT_REGNUM + 1]; | |
2261 | else | |
2262 | _this = reg_names [FIRST_ARGUMENT_REGNUM]; | |
2263 | ||
2264 | fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START); | |
2265 | ||
2266 | if (delta) | |
2267 | fprintf (file, "\tadd %d, %s\n", (int) delta, _this); | |
2268 | ||
2269 | if (vcall_offset) | |
2270 | { | |
2271 | const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1]; | |
2272 | ||
2273 | fprintf (file, "\tmov %s, %s\n", _this, scratch); | |
2274 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2275 | fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch); | |
2276 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2277 | fprintf (file, "\tadd %s, %s\n", scratch, _this); | |
2278 | } | |
2279 | ||
2280 | fputs ("\tjmp ", file); | |
2281 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2282 | putc ('\n', file); | |
2283 | } | |
2284 | ||
2285 | /* Return true if mn10300_output_mi_thunk would be able to output the | |
2286 | assembler code for the thunk function specified by the arguments | |
2287 | it is passed, and false otherwise. */ | |
2288 | ||
2289 | static bool | |
2290 | mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2291 | HOST_WIDE_INT delta ATTRIBUTE_UNUSED, | |
2292 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2293 | const_tree function ATTRIBUTE_UNUSED) | |
2294 | { | |
2295 | return true; | |
2296 | } |