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29a404f9 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
8935d57c | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
6e31cc90 | 3 | Free Software Foundation, Inc. |
29a404f9 | 4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
187b36cf | 6 | This file is part of GCC. |
29a404f9 | 7 | |
187b36cf | 8 | GCC is free software; you can redistribute it and/or modify |
29a404f9 | 9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
187b36cf | 13 | GCC is distributed in the hope that it will be useful, |
29a404f9 | 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
187b36cf | 19 | along with GCC; see the file COPYING. If not, write to |
29a404f9 | 20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
29a404f9 | 23 | #include "config.h" |
7014838c | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
29a404f9 | 27 | #include "rtl.h" |
4faf81b8 | 28 | #include "tree.h" |
29a404f9 | 29 | #include "regs.h" |
30 | #include "hard-reg-set.h" | |
31 | #include "real.h" | |
32 | #include "insn-config.h" | |
33 | #include "conditions.h" | |
29a404f9 | 34 | #include "output.h" |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "recog.h" | |
38 | #include "expr.h" | |
d8fc4d0b | 39 | #include "optabs.h" |
4faf81b8 | 40 | #include "function.h" |
29a404f9 | 41 | #include "obstack.h" |
59086782 | 42 | #include "toplev.h" |
43 | #include "tm_p.h" | |
a767736d | 44 | #include "target.h" |
45 | #include "target-def.h" | |
29a404f9 | 46 | |
b87a151a | 47 | /* This is used by GOTaddr2picreg to uniquely identify |
48 | UNSPEC_INT_LABELs. */ | |
49 | int mn10300_unspec_int_label_counter; | |
50 | ||
1acdfc69 | 51 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
52 | names are not prefixed by underscores, to tell whether to prefix a | |
53 | label with a plus sign or not, so that the assembler can tell | |
54 | symbol names from register names. */ | |
55 | int mn10300_protect_label; | |
56 | ||
8ecf154e | 57 | /* The size of the callee register save area. Right now we save everything |
58 | on entry since it costs us nothing in code size. It does cost us from a | |
59 | speed standpoint, so we want to optimize this sooner or later. */ | |
3bcd7b00 | 60 | #define REG_SAVE_BYTES (4 * regs_ever_live[2] \ |
61 | + 4 * regs_ever_live[3] \ | |
911517ac | 62 | + 4 * regs_ever_live[6] \ |
63 | + 4 * regs_ever_live[7] \ | |
64 | + 16 * (regs_ever_live[14] || regs_ever_live[15] \ | |
65 | || regs_ever_live[16] || regs_ever_live[17])) | |
fab7adbf | 66 | |
67 | ||
0792f2cf | 68 | static int mn10300_address_cost_1 (rtx, int *); |
69 | static int mn10300_address_cost (rtx); | |
70 | static bool mn10300_rtx_costs (rtx, int, int, int *); | |
71 | static void mn10300_file_start (void); | |
fab7adbf | 72 | |
a767736d | 73 | \f |
74 | /* Initialize the GCC target structure. */ | |
58356836 | 75 | #undef TARGET_ASM_ALIGNED_HI_OP |
76 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
8ecf154e | 77 | |
fab7adbf | 78 | #undef TARGET_RTX_COSTS |
79 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
ec0457a8 | 80 | #undef TARGET_ADDRESS_COST |
81 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
fab7adbf | 82 | |
92c473b8 | 83 | #undef TARGET_ASM_FILE_START |
84 | #define TARGET_ASM_FILE_START mn10300_file_start | |
85 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
86 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
87 | ||
b87a151a | 88 | #undef TARGET_ENCODE_SECTION_INFO |
89 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
90 | ||
91 | static void mn10300_encode_section_info (tree, rtx, int); | |
57e4bbfb | 92 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 93 | \f |
92c473b8 | 94 | static void |
3285410a | 95 | mn10300_file_start (void) |
29a404f9 | 96 | { |
92c473b8 | 97 | default_file_start (); |
911517ac | 98 | |
b166356e | 99 | if (TARGET_AM33_2) |
100 | fprintf (asm_out_file, "\t.am33_2\n"); | |
101 | else if (TARGET_AM33) | |
92c473b8 | 102 | fprintf (asm_out_file, "\t.am33\n"); |
29a404f9 | 103 | } |
104 | \f | |
105 | ||
29a404f9 | 106 | /* Print operand X using operand code CODE to assembly language output file |
107 | FILE. */ | |
108 | ||
109 | void | |
3285410a | 110 | print_operand (FILE *file, rtx x, int code) |
29a404f9 | 111 | { |
112 | switch (code) | |
113 | { | |
114 | case 'b': | |
115 | case 'B': | |
b166356e | 116 | if (cc_status.mdep.fpCC) |
117 | { | |
118 | switch (code == 'b' ? GET_CODE (x) | |
119 | : reverse_condition_maybe_unordered (GET_CODE (x))) | |
120 | { | |
121 | case NE: | |
122 | fprintf (file, "ne"); | |
123 | break; | |
124 | case EQ: | |
125 | fprintf (file, "eq"); | |
126 | break; | |
127 | case GE: | |
128 | fprintf (file, "ge"); | |
129 | break; | |
130 | case GT: | |
131 | fprintf (file, "gt"); | |
132 | break; | |
133 | case LE: | |
134 | fprintf (file, "le"); | |
135 | break; | |
136 | case LT: | |
137 | fprintf (file, "lt"); | |
138 | break; | |
139 | case ORDERED: | |
140 | fprintf (file, "lge"); | |
141 | break; | |
142 | case UNORDERED: | |
143 | fprintf (file, "uo"); | |
144 | break; | |
145 | case LTGT: | |
146 | fprintf (file, "lg"); | |
147 | break; | |
148 | case UNEQ: | |
149 | fprintf (file, "ue"); | |
150 | break; | |
151 | case UNGE: | |
152 | fprintf (file, "uge"); | |
153 | break; | |
154 | case UNGT: | |
155 | fprintf (file, "ug"); | |
156 | break; | |
157 | case UNLE: | |
158 | fprintf (file, "ule"); | |
159 | break; | |
160 | case UNLT: | |
161 | fprintf (file, "ul"); | |
162 | break; | |
163 | default: | |
164 | abort (); | |
165 | } | |
166 | break; | |
167 | } | |
29a404f9 | 168 | /* These are normal and reversed branches. */ |
169 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
170 | { | |
171 | case NE: | |
172 | fprintf (file, "ne"); | |
173 | break; | |
174 | case EQ: | |
175 | fprintf (file, "eq"); | |
176 | break; | |
177 | case GE: | |
178 | fprintf (file, "ge"); | |
179 | break; | |
180 | case GT: | |
181 | fprintf (file, "gt"); | |
182 | break; | |
183 | case LE: | |
184 | fprintf (file, "le"); | |
185 | break; | |
186 | case LT: | |
187 | fprintf (file, "lt"); | |
188 | break; | |
189 | case GEU: | |
190 | fprintf (file, "cc"); | |
191 | break; | |
192 | case GTU: | |
193 | fprintf (file, "hi"); | |
194 | break; | |
195 | case LEU: | |
196 | fprintf (file, "ls"); | |
197 | break; | |
198 | case LTU: | |
199 | fprintf (file, "cs"); | |
200 | break; | |
201 | default: | |
202 | abort (); | |
203 | } | |
204 | break; | |
205 | case 'C': | |
206 | /* This is used for the operand to a call instruction; | |
207 | if it's a REG, enclose it in parens, else output | |
208 | the operand normally. */ | |
209 | if (GET_CODE (x) == REG) | |
210 | { | |
211 | fputc ('(', file); | |
212 | print_operand (file, x, 0); | |
213 | fputc (')', file); | |
214 | } | |
215 | else | |
216 | print_operand (file, x, 0); | |
217 | break; | |
218 | ||
b166356e | 219 | case 'D': |
220 | switch (GET_CODE (x)) | |
221 | { | |
222 | case MEM: | |
223 | fputc ('(', file); | |
224 | output_address (XEXP (x, 0)); | |
225 | fputc (')', file); | |
226 | break; | |
227 | ||
228 | case REG: | |
229 | fprintf (file, "fd%d", REGNO (x) - 18); | |
230 | break; | |
231 | ||
232 | default: | |
233 | abort (); | |
234 | } | |
235 | break; | |
236 | ||
6ce19398 | 237 | /* These are the least significant word in a 64bit value. */ |
238 | case 'L': | |
239 | switch (GET_CODE (x)) | |
240 | { | |
241 | case MEM: | |
242 | fputc ('(', file); | |
243 | output_address (XEXP (x, 0)); | |
244 | fputc (')', file); | |
245 | break; | |
246 | ||
247 | case REG: | |
248 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
249 | break; | |
250 | ||
251 | case SUBREG: | |
701e46d0 | 252 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
6ce19398 | 253 | break; |
254 | ||
255 | case CONST_DOUBLE: | |
256 | { | |
257 | long val[2]; | |
258 | REAL_VALUE_TYPE rv; | |
259 | ||
260 | switch (GET_MODE (x)) | |
261 | { | |
262 | case DFmode: | |
263 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
264 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 265 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 266 | break;; |
267 | case SFmode: | |
268 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
269 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
ad3c0f03 | 270 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 271 | break;; |
272 | case VOIDmode: | |
273 | case DImode: | |
274 | print_operand_address (file, | |
275 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
276 | break; | |
59086782 | 277 | default: |
278 | break; | |
6ce19398 | 279 | } |
280 | break; | |
281 | } | |
282 | ||
283 | case CONST_INT: | |
964d057c | 284 | { |
285 | rtx low, high; | |
286 | split_double (x, &low, &high); | |
287 | fprintf (file, "%ld", (long)INTVAL (low)); | |
288 | break; | |
289 | } | |
6ce19398 | 290 | |
291 | default: | |
292 | abort (); | |
293 | } | |
294 | break; | |
295 | ||
296 | /* Similarly, but for the most significant word. */ | |
297 | case 'H': | |
298 | switch (GET_CODE (x)) | |
299 | { | |
300 | case MEM: | |
301 | fputc ('(', file); | |
eafc6604 | 302 | x = adjust_address (x, SImode, 4); |
6ce19398 | 303 | output_address (XEXP (x, 0)); |
304 | fputc (')', file); | |
305 | break; | |
306 | ||
307 | case REG: | |
308 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
309 | break; | |
310 | ||
311 | case SUBREG: | |
701e46d0 | 312 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
6ce19398 | 313 | break; |
314 | ||
315 | case CONST_DOUBLE: | |
316 | { | |
317 | long val[2]; | |
318 | REAL_VALUE_TYPE rv; | |
319 | ||
320 | switch (GET_MODE (x)) | |
321 | { | |
322 | case DFmode: | |
323 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
324 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 325 | fprintf (file, "0x%lx", val[1]); |
6ce19398 | 326 | break;; |
327 | case SFmode: | |
328 | abort (); | |
329 | case VOIDmode: | |
330 | case DImode: | |
331 | print_operand_address (file, | |
332 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
333 | break; | |
59086782 | 334 | default: |
335 | break; | |
6ce19398 | 336 | } |
337 | break; | |
338 | } | |
339 | ||
340 | case CONST_INT: | |
964d057c | 341 | { |
342 | rtx low, high; | |
343 | split_double (x, &low, &high); | |
344 | fprintf (file, "%ld", (long)INTVAL (high)); | |
345 | break; | |
346 | } | |
347 | ||
6ce19398 | 348 | default: |
349 | abort (); | |
350 | } | |
351 | break; | |
352 | ||
353 | case 'A': | |
354 | fputc ('(', file); | |
355 | if (GET_CODE (XEXP (x, 0)) == REG) | |
7014838c | 356 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0))); |
6ce19398 | 357 | else |
358 | output_address (XEXP (x, 0)); | |
359 | fputc (')', file); | |
360 | break; | |
361 | ||
167fa942 | 362 | case 'N': |
058f71f0 | 363 | if (INTVAL (x) < -128 || INTVAL (x) > 255) |
364 | abort (); | |
365 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); | |
366 | break; | |
367 | ||
368 | case 'U': | |
369 | if (INTVAL (x) < -128 || INTVAL (x) > 255) | |
370 | abort (); | |
371 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); | |
167fa942 | 372 | break; |
373 | ||
63e678f2 | 374 | /* For shift counts. The hardware ignores the upper bits of |
375 | any immediate, but the assembler will flag an out of range | |
376 | shift count as an error. So we mask off the high bits | |
377 | of the immediate here. */ | |
378 | case 'S': | |
379 | if (GET_CODE (x) == CONST_INT) | |
380 | { | |
058f71f0 | 381 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
63e678f2 | 382 | break; |
383 | } | |
384 | /* FALL THROUGH */ | |
385 | ||
29a404f9 | 386 | default: |
387 | switch (GET_CODE (x)) | |
388 | { | |
389 | case MEM: | |
390 | fputc ('(', file); | |
391 | output_address (XEXP (x, 0)); | |
392 | fputc (')', file); | |
393 | break; | |
394 | ||
6ce19398 | 395 | case PLUS: |
396 | output_address (x); | |
397 | break; | |
398 | ||
29a404f9 | 399 | case REG: |
400 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
401 | break; | |
402 | ||
403 | case SUBREG: | |
701e46d0 | 404 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
29a404f9 | 405 | break; |
406 | ||
6ce19398 | 407 | /* This will only be single precision.... */ |
408 | case CONST_DOUBLE: | |
409 | { | |
410 | unsigned long val; | |
411 | REAL_VALUE_TYPE rv; | |
412 | ||
413 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
414 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
ad3c0f03 | 415 | fprintf (file, "0x%lx", val); |
6ce19398 | 416 | break; |
417 | } | |
418 | ||
29a404f9 | 419 | case CONST_INT: |
420 | case SYMBOL_REF: | |
421 | case CONST: | |
422 | case LABEL_REF: | |
423 | case CODE_LABEL: | |
b87a151a | 424 | case UNSPEC: |
29a404f9 | 425 | print_operand_address (file, x); |
426 | break; | |
427 | default: | |
428 | abort (); | |
429 | } | |
430 | break; | |
431 | } | |
432 | } | |
433 | ||
434 | /* Output assembly language output for the address ADDR to FILE. */ | |
435 | ||
436 | void | |
3285410a | 437 | print_operand_address (FILE *file, rtx addr) |
29a404f9 | 438 | { |
439 | switch (GET_CODE (addr)) | |
440 | { | |
911517ac | 441 | case POST_INC: |
442 | print_operand_address (file, XEXP (addr, 0)); | |
443 | fputc ('+', file); | |
444 | break; | |
29a404f9 | 445 | case REG: |
49fd1b62 | 446 | print_operand (file, addr, 0); |
29a404f9 | 447 | break; |
448 | case PLUS: | |
449 | { | |
450 | rtx base, index; | |
451 | if (REG_P (XEXP (addr, 0)) | |
452 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
453 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
454 | else if (REG_P (XEXP (addr, 1)) | |
455 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
456 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
457 | else | |
458 | abort (); | |
459 | print_operand (file, index, 0); | |
460 | fputc (',', file); | |
461 | print_operand (file, base, 0);; | |
462 | break; | |
463 | } | |
464 | case SYMBOL_REF: | |
465 | output_addr_const (file, addr); | |
466 | break; | |
467 | default: | |
468 | output_addr_const (file, addr); | |
469 | break; | |
470 | } | |
471 | } | |
472 | ||
b166356e | 473 | /* Count the number of FP registers that have to be saved. */ |
474 | static int | |
3285410a | 475 | fp_regs_to_save (void) |
b166356e | 476 | { |
477 | int i, n = 0; | |
478 | ||
479 | if (! TARGET_AM33_2) | |
480 | return 0; | |
481 | ||
482 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
483 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
484 | ++n; | |
485 | ||
486 | return n; | |
487 | } | |
488 | ||
4caa3669 | 489 | /* Print a set of registers in the format required by "movm" and "ret". |
490 | Register K is saved if bit K of MASK is set. The data and address | |
491 | registers can be stored individually, but the extended registers cannot. | |
492 | We assume that the mask alread takes that into account. For instance, | |
493 | bits 14 to 17 must have the same value. */ | |
494 | ||
495 | void | |
3285410a | 496 | mn10300_print_reg_list (FILE *file, int mask) |
4caa3669 | 497 | { |
498 | int need_comma; | |
499 | int i; | |
500 | ||
501 | need_comma = 0; | |
502 | fputc ('[', file); | |
503 | ||
504 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
505 | if ((mask & (1 << i)) != 0) | |
506 | { | |
507 | if (need_comma) | |
508 | fputc (',', file); | |
509 | fputs (reg_names [i], file); | |
510 | need_comma = 1; | |
511 | } | |
512 | ||
513 | if ((mask & 0x3c000) != 0) | |
514 | { | |
515 | if ((mask & 0x3c000) != 0x3c000) | |
516 | abort(); | |
517 | if (need_comma) | |
518 | fputc (',', file); | |
519 | fputs ("exreg1", file); | |
520 | need_comma = 1; | |
521 | } | |
522 | ||
523 | fputc (']', file); | |
524 | } | |
525 | ||
6ce19398 | 526 | int |
3285410a | 527 | can_use_return_insn (void) |
6ce19398 | 528 | { |
36ed4406 | 529 | /* size includes the fixed stack space needed for function calls. */ |
530 | int size = get_frame_size () + current_function_outgoing_args_size; | |
531 | ||
532 | /* And space for the return pointer. */ | |
533 | size += current_function_outgoing_args_size ? 4 : 0; | |
6ce19398 | 534 | |
535 | return (reload_completed | |
536 | && size == 0 | |
537 | && !regs_ever_live[2] | |
538 | && !regs_ever_live[3] | |
539 | && !regs_ever_live[6] | |
540 | && !regs_ever_live[7] | |
911517ac | 541 | && !regs_ever_live[14] |
542 | && !regs_ever_live[15] | |
543 | && !regs_ever_live[16] | |
544 | && !regs_ever_live[17] | |
b166356e | 545 | && fp_regs_to_save () == 0 |
6ce19398 | 546 | && !frame_pointer_needed); |
547 | } | |
548 | ||
4caa3669 | 549 | /* Returns the set of live, callee-saved registers as a bitmask. The |
550 | callee-saved extended registers cannot be stored individually, so | |
551 | all of them will be included in the mask if any one of them is used. */ | |
552 | ||
553 | int | |
3285410a | 554 | mn10300_get_live_callee_saved_regs (void) |
4caa3669 | 555 | { |
556 | int mask; | |
557 | int i; | |
558 | ||
559 | mask = 0; | |
b166356e | 560 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
4caa3669 | 561 | if (regs_ever_live[i] && ! call_used_regs[i]) |
562 | mask |= (1 << i); | |
563 | if ((mask & 0x3c000) != 0) | |
564 | mask |= 0x3c000; | |
565 | ||
566 | return mask; | |
567 | } | |
568 | ||
569 | /* Generate an instruction that pushes several registers onto the stack. | |
570 | Register K will be saved if bit K in MASK is set. The function does | |
571 | nothing if MASK is zero. | |
572 | ||
573 | To be compatible with the "movm" instruction, the lowest-numbered | |
574 | register must be stored in the lowest slot. If MASK is the set | |
575 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
576 | instruction will have the form: | |
577 | ||
578 | (parallel | |
579 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
580 | (set (mem:SI (plus:SI (reg:SI 9) | |
581 | (const_int -1*4))) | |
582 | (reg:SI RN)) | |
583 | ... | |
584 | (set (mem:SI (plus:SI (reg:SI 9) | |
585 | (const_int -N*4))) | |
586 | (reg:SI R1))) */ | |
587 | ||
588 | void | |
3285410a | 589 | mn10300_gen_multiple_store (int mask) |
4caa3669 | 590 | { |
591 | if (mask != 0) | |
592 | { | |
593 | int i; | |
594 | int count; | |
595 | rtx par; | |
596 | int pari; | |
597 | ||
598 | /* Count how many registers need to be saved. */ | |
599 | count = 0; | |
b166356e | 600 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
4caa3669 | 601 | if ((mask & (1 << i)) != 0) |
602 | count += 1; | |
603 | ||
604 | /* We need one PARALLEL element to update the stack pointer and | |
605 | an additional element for each register that is stored. */ | |
606 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); | |
607 | ||
608 | /* Create the instruction that updates the stack pointer. */ | |
609 | XVECEXP (par, 0, 0) | |
610 | = gen_rtx_SET (SImode, | |
611 | stack_pointer_rtx, | |
612 | gen_rtx_PLUS (SImode, | |
613 | stack_pointer_rtx, | |
614 | GEN_INT (-count * 4))); | |
615 | ||
616 | /* Create each store. */ | |
617 | pari = 1; | |
b166356e | 618 | for (i = LAST_EXTENDED_REGNUM; i >= 0; i--) |
4caa3669 | 619 | if ((mask & (1 << i)) != 0) |
620 | { | |
621 | rtx address = gen_rtx_PLUS (SImode, | |
622 | stack_pointer_rtx, | |
623 | GEN_INT (-pari * 4)); | |
624 | XVECEXP(par, 0, pari) | |
625 | = gen_rtx_SET (VOIDmode, | |
626 | gen_rtx_MEM (SImode, address), | |
627 | gen_rtx_REG (SImode, i)); | |
628 | pari += 1; | |
629 | } | |
630 | ||
631 | par = emit_insn (par); | |
632 | RTX_FRAME_RELATED_P (par) = 1; | |
633 | } | |
634 | } | |
635 | ||
29a404f9 | 636 | void |
3285410a | 637 | expand_prologue (void) |
29a404f9 | 638 | { |
e3f95b40 | 639 | HOST_WIDE_INT size; |
f1899bff | 640 | |
f1899bff | 641 | /* SIZE includes the fixed stack space needed for function calls. */ |
36ed4406 | 642 | size = get_frame_size () + current_function_outgoing_args_size; |
643 | size += (current_function_outgoing_args_size ? 4 : 0); | |
29a404f9 | 644 | |
4caa3669 | 645 | /* If we use any of the callee-saved registers, save them now. */ |
646 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); | |
48cb86e3 | 647 | |
b166356e | 648 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
649 | { | |
650 | int num_regs_to_save = fp_regs_to_save (), i; | |
651 | HOST_WIDE_INT xsize; | |
652 | enum { save_sp_merge, | |
653 | save_sp_no_merge, | |
654 | save_sp_partial_merge, | |
655 | save_a0_merge, | |
656 | save_a0_no_merge } strategy; | |
657 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; | |
658 | rtx reg; | |
659 | rtx insn; | |
660 | ||
661 | /* We have several different strategies to save FP registers. | |
662 | We can store them using SP offsets, which is beneficial if | |
663 | there are just a few registers to save, or we can use `a0' in | |
664 | post-increment mode (`a0' is the only call-clobbered address | |
665 | register that is never used to pass information to a | |
666 | function). Furthermore, if we don't need a frame pointer, we | |
667 | can merge the two SP adds into a single one, but this isn't | |
668 | always beneficial; sometimes we can just split the two adds | |
669 | so that we don't exceed a 16-bit constant size. The code | |
670 | below will select which strategy to use, so as to generate | |
671 | smallest code. Ties are broken in favor or shorter sequences | |
672 | (in terms of number of instructions). */ | |
673 | ||
674 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
675 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
676 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
677 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
678 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ | |
679 | (((S) >= (L)) ? (SIZE1) * (N) \ | |
680 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ | |
681 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
682 | : (ELSE)) | |
683 | #define SIZE_FMOV_SP_(S,N) \ | |
684 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
685 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
686 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
687 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
688 | ||
689 | /* Consider alternative save_sp_merge only if we don't need the | |
fa483857 | 690 | frame pointer and size is nonzero. */ |
b166356e | 691 | if (! frame_pointer_needed && size) |
692 | { | |
693 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
694 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
695 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
696 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
697 | ||
698 | if (this_strategy_size < strategy_size) | |
699 | { | |
700 | strategy = save_sp_merge; | |
701 | strategy_size = this_strategy_size; | |
702 | } | |
703 | } | |
704 | ||
705 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
706 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
707 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
708 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
709 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
710 | if (size) | |
711 | { | |
712 | /* Insn: add -size, sp. */ | |
713 | this_strategy_size += SIZE_ADD_SP (-size); | |
714 | } | |
715 | ||
716 | if (this_strategy_size < strategy_size) | |
717 | { | |
718 | strategy = save_sp_no_merge; | |
719 | strategy_size = this_strategy_size; | |
720 | } | |
721 | ||
722 | /* Consider alternative save_sp_partial_merge only if we don't | |
723 | need a frame pointer and size is reasonably large. */ | |
724 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
725 | { | |
726 | /* Insn: add -128, sp. */ | |
727 | this_strategy_size = SIZE_ADD_SP (-128); | |
728 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
729 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
730 | num_regs_to_save); | |
731 | if (size) | |
732 | { | |
733 | /* Insn: add 128-size, sp. */ | |
734 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
735 | } | |
736 | ||
737 | if (this_strategy_size < strategy_size) | |
738 | { | |
739 | strategy = save_sp_partial_merge; | |
740 | strategy_size = this_strategy_size; | |
741 | } | |
742 | } | |
743 | ||
744 | /* Consider alternative save_a0_merge only if we don't need a | |
fa483857 | 745 | frame pointer, size is nonzero and the user hasn't |
b166356e | 746 | changed the calling conventions of a0. */ |
747 | if (! frame_pointer_needed && size | |
748 | && call_used_regs[FIRST_ADDRESS_REGNUM] | |
749 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) | |
750 | { | |
751 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
752 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
753 | /* Insn: mov sp, a0. */ | |
754 | this_strategy_size++; | |
755 | if (size) | |
756 | { | |
757 | /* Insn: add size, a0. */ | |
758 | this_strategy_size += SIZE_ADD_AX (size); | |
759 | } | |
760 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
761 | this_strategy_size += 3 * num_regs_to_save; | |
762 | ||
763 | if (this_strategy_size < strategy_size) | |
764 | { | |
765 | strategy = save_a0_merge; | |
766 | strategy_size = this_strategy_size; | |
767 | } | |
768 | } | |
769 | ||
770 | /* Consider alternative save_a0_no_merge if the user hasn't | |
771 | changed the calling conventions of a0. */ | |
772 | if (call_used_regs[FIRST_ADDRESS_REGNUM] | |
773 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) | |
774 | { | |
775 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
776 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
777 | /* Insn: mov sp, a0. */ | |
778 | this_strategy_size++; | |
779 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
780 | this_strategy_size += 3 * num_regs_to_save; | |
781 | if (size) | |
782 | { | |
783 | /* Insn: add -size, sp. */ | |
784 | this_strategy_size += SIZE_ADD_SP (-size); | |
785 | } | |
786 | ||
787 | if (this_strategy_size < strategy_size) | |
788 | { | |
789 | strategy = save_a0_no_merge; | |
790 | strategy_size = this_strategy_size; | |
791 | } | |
792 | } | |
793 | ||
794 | /* Emit the initial SP add, common to all strategies. */ | |
795 | switch (strategy) | |
796 | { | |
797 | case save_sp_no_merge: | |
798 | case save_a0_no_merge: | |
799 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
800 | stack_pointer_rtx, | |
801 | GEN_INT (-4 * num_regs_to_save))); | |
802 | xsize = 0; | |
803 | break; | |
804 | ||
805 | case save_sp_partial_merge: | |
806 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
807 | stack_pointer_rtx, | |
808 | GEN_INT (-128))); | |
809 | xsize = 128 - 4 * num_regs_to_save; | |
810 | size -= xsize; | |
811 | break; | |
812 | ||
813 | case save_sp_merge: | |
814 | case save_a0_merge: | |
815 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
816 | stack_pointer_rtx, | |
817 | GEN_INT (-(size + 4 * num_regs_to_save)))); | |
818 | /* We'll have to adjust FP register saves according to the | |
819 | frame size. */ | |
820 | xsize = size; | |
821 | /* Since we've already created the stack frame, don't do it | |
822 | again at the end of the function. */ | |
823 | size = 0; | |
824 | break; | |
825 | ||
826 | default: | |
827 | abort (); | |
828 | } | |
829 | ||
830 | /* Now prepare register a0, if we have decided to use it. */ | |
831 | switch (strategy) | |
832 | { | |
833 | case save_sp_merge: | |
834 | case save_sp_no_merge: | |
835 | case save_sp_partial_merge: | |
836 | reg = 0; | |
837 | break; | |
838 | ||
839 | case save_a0_merge: | |
840 | case save_a0_no_merge: | |
841 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
842 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
843 | if (xsize) | |
844 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))); | |
845 | reg = gen_rtx_POST_INC (SImode, reg); | |
846 | break; | |
847 | ||
848 | default: | |
849 | abort (); | |
850 | } | |
851 | ||
852 | /* Now actually save the FP registers. */ | |
853 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
854 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
855 | { | |
856 | rtx addr; | |
857 | ||
858 | if (reg) | |
859 | addr = reg; | |
860 | else | |
861 | { | |
862 | /* If we aren't using `a0', use an SP offset. */ | |
863 | if (xsize) | |
864 | { | |
865 | addr = gen_rtx_PLUS (SImode, | |
866 | stack_pointer_rtx, | |
867 | GEN_INT (xsize)); | |
868 | } | |
869 | else | |
870 | addr = stack_pointer_rtx; | |
871 | ||
872 | xsize += 4; | |
873 | } | |
874 | ||
875 | insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr), | |
876 | gen_rtx_REG (SImode, i))); | |
877 | ||
878 | RTX_FRAME_RELATED_P (insn) = 1; | |
879 | } | |
880 | } | |
881 | ||
48cb86e3 | 882 | /* Now put the frame pointer into the frame pointer register. */ |
29a404f9 | 883 | if (frame_pointer_needed) |
014546df | 884 | emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); |
29a404f9 | 885 | |
48cb86e3 | 886 | /* Allocate stack for this frame. */ |
29a404f9 | 887 | if (size) |
888 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
889 | stack_pointer_rtx, | |
890 | GEN_INT (-size))); | |
b87a151a | 891 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
892 | { | |
893 | rtx insn = get_last_insn (); | |
894 | rtx last = emit_insn (gen_GOTaddr2picreg ()); | |
895 | ||
896 | /* Mark these insns as possibly dead. Sometimes, flow2 may | |
897 | delete all uses of the PIC register. In this case, let it | |
898 | delete the initialization too. */ | |
899 | do | |
900 | { | |
901 | insn = NEXT_INSN (insn); | |
902 | ||
903 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
904 | const0_rtx, | |
905 | REG_NOTES (insn)); | |
906 | } | |
907 | while (insn != last); | |
908 | } | |
29a404f9 | 909 | } |
910 | ||
911 | void | |
3285410a | 912 | expand_epilogue (void) |
29a404f9 | 913 | { |
e3f95b40 | 914 | HOST_WIDE_INT size; |
f1899bff | 915 | |
f1899bff | 916 | /* SIZE includes the fixed stack space needed for function calls. */ |
36ed4406 | 917 | size = get_frame_size () + current_function_outgoing_args_size; |
918 | size += (current_function_outgoing_args_size ? 4 : 0); | |
29a404f9 | 919 | |
b166356e | 920 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
921 | { | |
922 | int num_regs_to_save = fp_regs_to_save (), i; | |
923 | rtx reg = 0; | |
924 | ||
925 | /* We have several options to restore FP registers. We could | |
926 | load them from SP offsets, but, if there are enough FP | |
927 | registers to restore, we win if we use a post-increment | |
928 | addressing mode. */ | |
929 | ||
930 | /* If we have a frame pointer, it's the best option, because we | |
931 | already know it has the value we want. */ | |
932 | if (frame_pointer_needed) | |
933 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
934 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
935 | it's never used for return values. But only do so if it's | |
936 | smaller than using SP offsets. */ | |
937 | else | |
938 | { | |
939 | enum { restore_sp_post_adjust, | |
940 | restore_sp_pre_adjust, | |
941 | restore_sp_partial_adjust, | |
942 | restore_a1 } strategy; | |
943 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
944 | ||
945 | /* Consider using sp offsets before adjusting sp. */ | |
946 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
947 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
948 | /* If size is too large, we'll have to adjust SP with an | |
949 | add. */ | |
950 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
951 | { | |
952 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
953 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
954 | } | |
955 | /* If we don't have to restore any non-FP registers, | |
956 | we'll be able to save one byte by using rets. */ | |
957 | if (! REG_SAVE_BYTES) | |
958 | this_strategy_size--; | |
959 | ||
960 | if (this_strategy_size < strategy_size) | |
961 | { | |
962 | strategy = restore_sp_post_adjust; | |
963 | strategy_size = this_strategy_size; | |
964 | } | |
965 | ||
966 | /* Consider using sp offsets after adjusting sp. */ | |
967 | /* Insn: add size, sp. */ | |
968 | this_strategy_size = SIZE_ADD_SP (size); | |
969 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
970 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
971 | /* We're going to use ret to release the FP registers | |
972 | save area, so, no savings. */ | |
973 | ||
974 | if (this_strategy_size < strategy_size) | |
975 | { | |
976 | strategy = restore_sp_pre_adjust; | |
977 | strategy_size = this_strategy_size; | |
978 | } | |
979 | ||
980 | /* Consider using sp offsets after partially adjusting sp. | |
981 | When size is close to 32Kb, we may be able to adjust SP | |
982 | with an imm16 add instruction while still using fmov | |
983 | (d8,sp). */ | |
984 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
985 | { | |
986 | /* Insn: add size + 4 * num_regs_to_save | |
987 | + REG_SAVE_BYTES - 252,sp. */ | |
988 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save | |
989 | + REG_SAVE_BYTES - 252); | |
990 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ | |
991 | this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES | |
992 | - 4 * num_regs_to_save, | |
993 | num_regs_to_save); | |
994 | /* We're going to use ret to release the FP registers | |
995 | save area, so, no savings. */ | |
996 | ||
997 | if (this_strategy_size < strategy_size) | |
998 | { | |
999 | strategy = restore_sp_partial_adjust; | |
1000 | strategy_size = this_strategy_size; | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | /* Consider using a1 in post-increment mode, as long as the | |
1005 | user hasn't changed the calling conventions of a1. */ | |
1006 | if (call_used_regs[FIRST_ADDRESS_REGNUM+1] | |
1007 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) | |
1008 | { | |
1009 | /* Insn: mov sp,a1. */ | |
1010 | this_strategy_size = 1; | |
1011 | if (size) | |
1012 | { | |
1013 | /* Insn: add size,a1. */ | |
1014 | this_strategy_size += SIZE_ADD_AX (size); | |
1015 | } | |
1016 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1017 | this_strategy_size += 3 * num_regs_to_save; | |
1018 | /* If size is large enough, we may be able to save a | |
1019 | couple of bytes. */ | |
1020 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1021 | { | |
1022 | /* Insn: mov a1,sp. */ | |
1023 | this_strategy_size += 2; | |
1024 | } | |
1025 | /* If we don't have to restore any non-FP registers, | |
1026 | we'll be able to save one byte by using rets. */ | |
1027 | if (! REG_SAVE_BYTES) | |
1028 | this_strategy_size--; | |
1029 | ||
1030 | if (this_strategy_size < strategy_size) | |
1031 | { | |
1032 | strategy = restore_a1; | |
1033 | strategy_size = this_strategy_size; | |
1034 | } | |
1035 | } | |
1036 | ||
1037 | switch (strategy) | |
1038 | { | |
1039 | case restore_sp_post_adjust: | |
1040 | break; | |
1041 | ||
1042 | case restore_sp_pre_adjust: | |
1043 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1044 | stack_pointer_rtx, | |
1045 | GEN_INT (size))); | |
1046 | size = 0; | |
1047 | break; | |
1048 | ||
1049 | case restore_sp_partial_adjust: | |
1050 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1051 | stack_pointer_rtx, | |
1052 | GEN_INT (size + 4 * num_regs_to_save | |
1053 | + REG_SAVE_BYTES - 252))); | |
1054 | size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save; | |
1055 | break; | |
1056 | ||
1057 | case restore_a1: | |
1058 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1059 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1060 | if (size) | |
1061 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1062 | break; | |
1063 | ||
1064 | default: | |
1065 | abort (); | |
1066 | } | |
1067 | } | |
1068 | ||
1069 | /* Adjust the selected register, if any, for post-increment. */ | |
1070 | if (reg) | |
1071 | reg = gen_rtx_POST_INC (SImode, reg); | |
1072 | ||
1073 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
1074 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
1075 | { | |
1076 | rtx addr; | |
1077 | ||
1078 | if (reg) | |
1079 | addr = reg; | |
1080 | else if (size) | |
1081 | { | |
1082 | /* If we aren't using a post-increment register, use an | |
1083 | SP offset. */ | |
1084 | addr = gen_rtx_PLUS (SImode, | |
1085 | stack_pointer_rtx, | |
1086 | GEN_INT (size)); | |
1087 | } | |
1088 | else | |
1089 | addr = stack_pointer_rtx; | |
1090 | ||
1091 | size += 4; | |
1092 | ||
1093 | emit_insn (gen_movsi (gen_rtx_REG (SImode, i), | |
1094 | gen_rtx_MEM (SImode, addr))); | |
1095 | } | |
1096 | ||
1097 | /* If we were using the restore_a1 strategy and the number of | |
1098 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1099 | to `sp', to avoid having to use `add' to adjust it. */ | |
1100 | if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255) | |
1101 | { | |
1102 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1103 | size = 0; | |
1104 | } | |
1105 | } | |
1106 | ||
461cabcc | 1107 | /* Maybe cut back the stack, except for the register save area. |
1108 | ||
1109 | If the frame pointer exists, then use the frame pointer to | |
1110 | cut back the stack. | |
1111 | ||
1112 | If the stack size + register save area is more than 255 bytes, | |
1113 | then the stack must be cut back here since the size + register | |
1114 | save size is too big for a ret/retf instruction. | |
1115 | ||
1116 | Else leave it alone, it will be cut back as part of the | |
1117 | ret/retf instruction, or there wasn't any stack to begin with. | |
1118 | ||
dfd1079d | 1119 | Under no circumstances should the register save area be |
461cabcc | 1120 | deallocated here, that would leave a window where an interrupt |
1121 | could occur and trash the register save area. */ | |
29a404f9 | 1122 | if (frame_pointer_needed) |
1123 | { | |
29a404f9 | 1124 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
b21218d6 | 1125 | size = 0; |
1126 | } | |
55daf463 | 1127 | else if (size + REG_SAVE_BYTES > 255) |
b21218d6 | 1128 | { |
1129 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1130 | stack_pointer_rtx, | |
1131 | GEN_INT (size))); | |
1132 | size = 0; | |
29a404f9 | 1133 | } |
29a404f9 | 1134 | |
55daf463 | 1135 | /* Adjust the stack and restore callee-saved registers, if any. */ |
1136 | if (size || regs_ever_live[2] || regs_ever_live[3] | |
48cb86e3 | 1137 | || regs_ever_live[6] || regs_ever_live[7] |
911517ac | 1138 | || regs_ever_live[14] || regs_ever_live[15] |
1139 | || regs_ever_live[16] || regs_ever_live[17] | |
48cb86e3 | 1140 | || frame_pointer_needed) |
55daf463 | 1141 | emit_jump_insn (gen_return_internal_regs |
1142 | (GEN_INT (size + REG_SAVE_BYTES))); | |
48cb86e3 | 1143 | else |
55daf463 | 1144 | emit_jump_insn (gen_return_internal ()); |
29a404f9 | 1145 | } |
1146 | ||
1147 | /* Update the condition code from the insn. */ | |
1148 | ||
1149 | void | |
3285410a | 1150 | notice_update_cc (rtx body, rtx insn) |
29a404f9 | 1151 | { |
29a404f9 | 1152 | switch (get_attr_cc (insn)) |
1153 | { | |
1154 | case CC_NONE: | |
1155 | /* Insn does not affect CC at all. */ | |
1156 | break; | |
1157 | ||
1158 | case CC_NONE_0HIT: | |
1159 | /* Insn does not change CC, but the 0'th operand has been changed. */ | |
1160 | if (cc_status.value1 != 0 | |
ed420a25 | 1161 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
29a404f9 | 1162 | cc_status.value1 = 0; |
1163 | break; | |
1164 | ||
14058057 | 1165 | case CC_SET_ZN: |
ed420a25 | 1166 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
14058057 | 1167 | V,C are unusable. */ |
29a404f9 | 1168 | CC_STATUS_INIT; |
14058057 | 1169 | cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; |
ed420a25 | 1170 | cc_status.value1 = recog_data.operand[0]; |
29a404f9 | 1171 | break; |
1172 | ||
14058057 | 1173 | case CC_SET_ZNV: |
ed420a25 | 1174 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
14058057 | 1175 | C is unusable. */ |
45e3d109 | 1176 | CC_STATUS_INIT; |
14058057 | 1177 | cc_status.flags |= CC_NO_CARRY; |
ed420a25 | 1178 | cc_status.value1 = recog_data.operand[0]; |
45e3d109 | 1179 | break; |
1180 | ||
29a404f9 | 1181 | case CC_COMPARE: |
1182 | /* The insn is a compare instruction. */ | |
1183 | CC_STATUS_INIT; | |
1184 | cc_status.value1 = SET_SRC (body); | |
b166356e | 1185 | if (GET_CODE (cc_status.value1) == COMPARE |
1186 | && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode) | |
1187 | cc_status.mdep.fpCC = 1; | |
29a404f9 | 1188 | break; |
1189 | ||
952e42d8 | 1190 | case CC_INVERT: |
1191 | /* The insn is a compare instruction. */ | |
1192 | CC_STATUS_INIT; | |
1193 | cc_status.value1 = SET_SRC (body); | |
1194 | cc_status.flags |= CC_INVERTED; | |
1195 | break; | |
1196 | ||
29a404f9 | 1197 | case CC_CLOBBER: |
1198 | /* Insn doesn't leave CC in a usable state. */ | |
1199 | CC_STATUS_INIT; | |
1200 | break; | |
45e3d109 | 1201 | |
1202 | default: | |
1203 | abort (); | |
29a404f9 | 1204 | } |
29a404f9 | 1205 | } |
1206 | ||
a2f10574 | 1207 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
4caa3669 | 1208 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1209 | parallel. If OP is a multiple store, return a mask indicating which | |
1210 | registers it saves. Return 0 otherwise. */ | |
1211 | ||
1212 | int | |
3285410a | 1213 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
4caa3669 | 1214 | { |
1215 | int count; | |
1216 | int mask; | |
1217 | int i; | |
1218 | unsigned int last; | |
1219 | rtx elt; | |
1220 | ||
1221 | count = XVECLEN (op, 0); | |
1222 | if (count < 2) | |
1223 | return 0; | |
1224 | ||
1225 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1226 | elt = XVECEXP (op, 0, 0); | |
1227 | if (GET_CODE (elt) != SET | |
1228 | || GET_CODE (SET_DEST (elt)) != REG | |
1229 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM | |
1230 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1231 | return 0; | |
1232 | ||
1233 | /* Check that A is the stack pointer and B is the expected stack size. | |
1234 | For OP to match, each subsequent instruction should push a word onto | |
1235 | the stack. We therefore expect the first instruction to create | |
1236 | COUNT-1 stack slots. */ | |
1237 | elt = SET_SRC (elt); | |
1238 | if (GET_CODE (XEXP (elt, 0)) != REG | |
1239 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1240 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1241 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) | |
1242 | return 0; | |
1243 | ||
1244 | /* Now go through the rest of the vector elements. They must be | |
1245 | ordered so that the first instruction stores the highest-numbered | |
1246 | register to the highest stack slot and that subsequent instructions | |
1247 | store a lower-numbered register to the slot below. | |
1248 | ||
1249 | LAST keeps track of the smallest-numbered register stored so far. | |
1250 | MASK is the set of stored registers. */ | |
b166356e | 1251 | last = LAST_EXTENDED_REGNUM + 1; |
4caa3669 | 1252 | mask = 0; |
1253 | for (i = 1; i < count; i++) | |
1254 | { | |
1255 | /* Check that element i is a (set (mem M) R) and that R is valid. */ | |
1256 | elt = XVECEXP (op, 0, i); | |
1257 | if (GET_CODE (elt) != SET | |
1258 | || GET_CODE (SET_DEST (elt)) != MEM | |
1259 | || GET_CODE (SET_SRC (elt)) != REG | |
1260 | || REGNO (SET_SRC (elt)) >= last) | |
1261 | return 0; | |
1262 | ||
1263 | /* R was OK, so provisionally add it to MASK. We return 0 in any | |
1264 | case if the rest of the instruction has a flaw. */ | |
1265 | last = REGNO (SET_SRC (elt)); | |
1266 | mask |= (1 << last); | |
1267 | ||
1268 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1269 | elt = XEXP (SET_DEST (elt), 0); | |
1270 | if (GET_CODE (elt) != PLUS | |
1271 | || GET_CODE (XEXP (elt, 0)) != REG | |
1272 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1273 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1274 | || INTVAL (XEXP (elt, 1)) != -i * 4) | |
1275 | return 0; | |
1276 | } | |
1277 | ||
1278 | /* All or none of the callee-saved extended registers must be in the set. */ | |
1279 | if ((mask & 0x3c000) != 0 | |
1280 | && (mask & 0x3c000) != 0x3c000) | |
1281 | return 0; | |
1282 | ||
1283 | return mask; | |
1284 | } | |
1285 | ||
29a404f9 | 1286 | /* Return true if OP is a valid call operand. */ |
1287 | ||
1288 | int | |
3285410a | 1289 | call_address_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
29a404f9 | 1290 | { |
b87a151a | 1291 | if (flag_pic) |
1292 | return (EXTRA_CONSTRAINT (op, 'S') || GET_CODE (op) == REG); | |
1293 | ||
29a404f9 | 1294 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG); |
1295 | } | |
1296 | ||
1297 | /* What (if any) secondary registers are needed to move IN with mode | |
dc3d02df | 1298 | MODE into a register in register class CLASS. |
29a404f9 | 1299 | |
1300 | We might be able to simplify this. */ | |
1301 | enum reg_class | |
3285410a | 1302 | secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in) |
29a404f9 | 1303 | { |
29a404f9 | 1304 | /* Memory loads less than a full word wide can't have an |
1305 | address or stack pointer destination. They must use | |
1306 | a data register as an intermediate register. */ | |
79ea832f | 1307 | if ((GET_CODE (in) == MEM |
1308 | || (GET_CODE (in) == REG | |
1309 | && REGNO (in) >= FIRST_PSEUDO_REGISTER) | |
1310 | || (GET_CODE (in) == SUBREG | |
1311 | && GET_CODE (SUBREG_REG (in)) == REG | |
1312 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)) | |
29a404f9 | 1313 | && (mode == QImode || mode == HImode) |
79ea832f | 1314 | && (class == ADDRESS_REGS || class == SP_REGS |
b0ba03a6 | 1315 | || class == SP_OR_ADDRESS_REGS)) |
8ecf154e | 1316 | { |
911517ac | 1317 | if (TARGET_AM33) |
1318 | return DATA_OR_EXTENDED_REGS; | |
8ecf154e | 1319 | return DATA_REGS; |
1320 | } | |
29a404f9 | 1321 | |
1322 | /* We can't directly load sp + const_int into a data register; | |
1323 | we must use an address register as an intermediate. */ | |
48cb86e3 | 1324 | if (class != SP_REGS |
1325 | && class != ADDRESS_REGS | |
1326 | && class != SP_OR_ADDRESS_REGS | |
911517ac | 1327 | && class != SP_OR_EXTENDED_REGS |
1328 | && class != ADDRESS_OR_EXTENDED_REGS | |
1329 | && class != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
29a404f9 | 1330 | && (in == stack_pointer_rtx |
1331 | || (GET_CODE (in) == PLUS | |
48cb86e3 | 1332 | && (XEXP (in, 0) == stack_pointer_rtx |
1333 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
29a404f9 | 1334 | return ADDRESS_REGS; |
1335 | ||
19de5de1 | 1336 | if (GET_CODE (in) == PLUS |
1337 | && (XEXP (in, 0) == stack_pointer_rtx | |
1338 | || XEXP (in, 1) == stack_pointer_rtx)) | |
8ecf154e | 1339 | { |
911517ac | 1340 | if (TARGET_AM33) |
1341 | return DATA_OR_EXTENDED_REGS; | |
8ecf154e | 1342 | return DATA_REGS; |
1343 | } | |
19de5de1 | 1344 | |
b166356e | 1345 | if (TARGET_AM33_2 && class == FP_REGS |
1346 | && GET_CODE (in) == MEM && ! OK_FOR_Q (in)) | |
1347 | { | |
1348 | if (TARGET_AM33) | |
1349 | return DATA_OR_EXTENDED_REGS; | |
1350 | return DATA_REGS; | |
1351 | } | |
1352 | ||
48cb86e3 | 1353 | /* Otherwise assume no secondary reloads are needed. */ |
1354 | return NO_REGS; | |
1355 | } | |
1356 | ||
1357 | int | |
3285410a | 1358 | initial_offset (int from, int to) |
48cb86e3 | 1359 | { |
f1899bff | 1360 | /* The difference between the argument pointer and the frame pointer |
1361 | is the size of the callee register save area. */ | |
48cb86e3 | 1362 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
29a404f9 | 1363 | { |
48cb86e3 | 1364 | if (regs_ever_live[2] || regs_ever_live[3] |
1365 | || regs_ever_live[6] || regs_ever_live[7] | |
911517ac | 1366 | || regs_ever_live[14] || regs_ever_live[15] |
1367 | || regs_ever_live[16] || regs_ever_live[17] | |
b166356e | 1368 | || fp_regs_to_save () |
48cb86e3 | 1369 | || frame_pointer_needed) |
b166356e | 1370 | return REG_SAVE_BYTES |
1371 | + 4 * fp_regs_to_save (); | |
48cb86e3 | 1372 | else |
bb4959a8 | 1373 | return 0; |
29a404f9 | 1374 | } |
1375 | ||
f1899bff | 1376 | /* The difference between the argument pointer and the stack pointer is |
1377 | the sum of the size of this function's frame, the callee register save | |
1378 | area, and the fixed stack space needed for function calls (if any). */ | |
48cb86e3 | 1379 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
1380 | { | |
1381 | if (regs_ever_live[2] || regs_ever_live[3] | |
1382 | || regs_ever_live[6] || regs_ever_live[7] | |
911517ac | 1383 | || regs_ever_live[14] || regs_ever_live[15] |
1384 | || regs_ever_live[16] || regs_ever_live[17] | |
b166356e | 1385 | || fp_regs_to_save () |
48cb86e3 | 1386 | || frame_pointer_needed) |
8ecf154e | 1387 | return (get_frame_size () + REG_SAVE_BYTES |
b166356e | 1388 | + 4 * fp_regs_to_save () |
36ed4406 | 1389 | + (current_function_outgoing_args_size |
1390 | ? current_function_outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1391 | else |
36ed4406 | 1392 | return (get_frame_size () |
1393 | + (current_function_outgoing_args_size | |
1394 | ? current_function_outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1395 | } |
29a404f9 | 1396 | |
f1899bff | 1397 | /* The difference between the frame pointer and stack pointer is the sum |
1398 | of the size of this function's frame and the fixed stack space needed | |
1399 | for function calls (if any). */ | |
48cb86e3 | 1400 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
36ed4406 | 1401 | return (get_frame_size () |
1402 | + (current_function_outgoing_args_size | |
1403 | ? current_function_outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1404 | |
1405 | abort (); | |
29a404f9 | 1406 | } |
bb4959a8 | 1407 | |
1408 | /* Flush the argument registers to the stack for a stdarg function; | |
1409 | return the new argument pointer. */ | |
1410 | rtx | |
3285410a | 1411 | mn10300_builtin_saveregs (void) |
bb4959a8 | 1412 | { |
ed554036 | 1413 | rtx offset, mem; |
bb4959a8 | 1414 | tree fntype = TREE_TYPE (current_function_decl); |
1415 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
1416 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
1417 | != void_type_node))) | |
1418 | ? UNITS_PER_WORD : 0); | |
ed554036 | 1419 | int set = get_varargs_alias_set (); |
bb4959a8 | 1420 | |
1421 | if (argadj) | |
1422 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
1423 | else | |
1424 | offset = current_function_arg_offset_rtx; | |
1425 | ||
ed554036 | 1426 | mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer); |
ab6ab77e | 1427 | set_mem_alias_set (mem, set); |
ed554036 | 1428 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1429 | ||
1430 | mem = gen_rtx_MEM (SImode, | |
1431 | plus_constant (current_function_internal_arg_pointer, 4)); | |
ab6ab77e | 1432 | set_mem_alias_set (mem, set); |
ed554036 | 1433 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1434 | ||
bb4959a8 | 1435 | return copy_to_reg (expand_binop (Pmode, add_optab, |
1436 | current_function_internal_arg_pointer, | |
1437 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
1438 | } | |
1439 | ||
ed554036 | 1440 | void |
3285410a | 1441 | mn10300_va_start (tree valist, rtx nextarg) |
ed554036 | 1442 | { |
7ccc713a | 1443 | nextarg = expand_builtin_saveregs (); |
7df226a2 | 1444 | std_expand_builtin_va_start (valist, nextarg); |
ed554036 | 1445 | } |
1446 | ||
1447 | rtx | |
3285410a | 1448 | mn10300_va_arg (tree valist, tree type) |
ed554036 | 1449 | { |
1450 | HOST_WIDE_INT align, rsize; | |
1451 | tree t, ptr, pptr; | |
1452 | ||
1453 | /* Compute the rounded size of the type. */ | |
1454 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
1455 | rsize = (((int_size_in_bytes (type) + align - 1) / align) * align); | |
1456 | ||
1457 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
1458 | build_int_2 ((rsize > 8 ? 4 : rsize), 0)); | |
1459 | TREE_SIDE_EFFECTS (t) = 1; | |
1460 | ||
1461 | ptr = build_pointer_type (type); | |
1462 | ||
1463 | /* "Large" types are passed by reference. */ | |
1464 | if (rsize > 8) | |
1465 | { | |
1466 | pptr = build_pointer_type (ptr); | |
1467 | t = build1 (NOP_EXPR, pptr, t); | |
1468 | TREE_SIDE_EFFECTS (t) = 1; | |
1469 | ||
1470 | t = build1 (INDIRECT_REF, ptr, t); | |
1471 | TREE_SIDE_EFFECTS (t) = 1; | |
1472 | } | |
1473 | else | |
1474 | { | |
1475 | t = build1 (NOP_EXPR, ptr, t); | |
1476 | TREE_SIDE_EFFECTS (t) = 1; | |
1477 | } | |
1478 | ||
1479 | /* Calculate! */ | |
1480 | return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL); | |
1481 | } | |
1482 | ||
bb4959a8 | 1483 | /* Return an RTX to represent where a value with mode MODE will be returned |
1484 | from a function. If the result is 0, the argument is pushed. */ | |
1485 | ||
1486 | rtx | |
3285410a | 1487 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
1488 | tree type, int named ATTRIBUTE_UNUSED) | |
bb4959a8 | 1489 | { |
1490 | rtx result = 0; | |
1491 | int size, align; | |
1492 | ||
1493 | /* We only support using 2 data registers as argument registers. */ | |
1494 | int nregs = 2; | |
1495 | ||
1496 | /* Figure out the size of the object to be passed. */ | |
1497 | if (mode == BLKmode) | |
1498 | size = int_size_in_bytes (type); | |
1499 | else | |
1500 | size = GET_MODE_SIZE (mode); | |
1501 | ||
1502 | /* Figure out the alignment of the object to be passed. */ | |
1503 | align = size; | |
1504 | ||
1505 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1506 | ||
1507 | /* Don't pass this arg via a register if all the argument registers | |
1508 | are used up. */ | |
1509 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1510 | return 0; | |
1511 | ||
1512 | /* Don't pass this arg via a register if it would be split between | |
1513 | registers and memory. */ | |
1514 | if (type == NULL_TREE | |
1515 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1516 | return 0; | |
1517 | ||
1518 | switch (cum->nbytes / UNITS_PER_WORD) | |
1519 | { | |
1520 | case 0: | |
7014838c | 1521 | result = gen_rtx_REG (mode, 0); |
bb4959a8 | 1522 | break; |
1523 | case 1: | |
7014838c | 1524 | result = gen_rtx_REG (mode, 1); |
bb4959a8 | 1525 | break; |
1526 | default: | |
1527 | result = 0; | |
1528 | } | |
1529 | ||
1530 | return result; | |
1531 | } | |
1532 | ||
1533 | /* Return the number of registers to use for an argument passed partially | |
1534 | in registers and partially in memory. */ | |
1535 | ||
1536 | int | |
3285410a | 1537 | function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
1538 | tree type, int named ATTRIBUTE_UNUSED) | |
bb4959a8 | 1539 | { |
1540 | int size, align; | |
1541 | ||
1542 | /* We only support using 2 data registers as argument registers. */ | |
1543 | int nregs = 2; | |
1544 | ||
1545 | /* Figure out the size of the object to be passed. */ | |
1546 | if (mode == BLKmode) | |
1547 | size = int_size_in_bytes (type); | |
1548 | else | |
1549 | size = GET_MODE_SIZE (mode); | |
1550 | ||
1551 | /* Figure out the alignment of the object to be passed. */ | |
1552 | align = size; | |
1553 | ||
1554 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1555 | ||
1556 | /* Don't pass this arg via a register if all the argument registers | |
1557 | are used up. */ | |
1558 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1559 | return 0; | |
1560 | ||
1561 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1562 | return 0; | |
1563 | ||
1564 | /* Don't pass this arg via a register if it would be split between | |
1565 | registers and memory. */ | |
1566 | if (type == NULL_TREE | |
1567 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1568 | return 0; | |
1569 | ||
1570 | return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD; | |
1571 | } | |
1572 | ||
1573 | /* Output a tst insn. */ | |
feb9af9f | 1574 | const char * |
3285410a | 1575 | output_tst (rtx operand, rtx insn) |
bb4959a8 | 1576 | { |
bb4959a8 | 1577 | rtx temp; |
1578 | int past_call = 0; | |
1579 | ||
1580 | /* We can save a byte if we can find a register which has the value | |
1581 | zero in it. */ | |
1582 | temp = PREV_INSN (insn); | |
6e90c6cd | 1583 | while (optimize && temp) |
bb4959a8 | 1584 | { |
1585 | rtx set; | |
1586 | ||
1587 | /* We allow the search to go through call insns. We record | |
1588 | the fact that we've past a CALL_INSN and reject matches which | |
1589 | use call clobbered registers. */ | |
1590 | if (GET_CODE (temp) == CODE_LABEL | |
1591 | || GET_CODE (temp) == JUMP_INSN | |
1592 | || GET_CODE (temp) == BARRIER) | |
1593 | break; | |
1594 | ||
1595 | if (GET_CODE (temp) == CALL_INSN) | |
1596 | past_call = 1; | |
1597 | ||
1598 | if (GET_CODE (temp) == NOTE) | |
1599 | { | |
1600 | temp = PREV_INSN (temp); | |
1601 | continue; | |
1602 | } | |
1603 | ||
1604 | /* It must be an insn, see if it is a simple set. */ | |
1605 | set = single_set (temp); | |
1606 | if (!set) | |
1607 | { | |
1608 | temp = PREV_INSN (temp); | |
1609 | continue; | |
1610 | } | |
1611 | ||
1612 | /* Are we setting a data register to zero (this does not win for | |
1613 | address registers)? | |
1614 | ||
1615 | If it's a call clobbered register, have we past a call? | |
1616 | ||
1617 | Make sure the register we find isn't the same as ourself; | |
8ecf154e | 1618 | the mn10300 can't encode that. |
1619 | ||
1620 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1621 | so the code to detect calls here isn't doing anything useful. */ | |
bb4959a8 | 1622 | if (REG_P (SET_DEST (set)) |
1623 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1624 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
6e90c6cd | 1625 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1626 | == REGNO_REG_CLASS (REGNO (operand))) | |
911517ac | 1627 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1628 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
1629 | && (!past_call | |
1630 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1631 | { | |
1632 | rtx xoperands[2]; | |
1633 | xoperands[0] = operand; | |
1634 | xoperands[1] = SET_DEST (set); | |
1635 | ||
1636 | output_asm_insn ("cmp %1,%0", xoperands); | |
1637 | return ""; | |
1638 | } | |
1639 | ||
1640 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1641 | && REG_P (SET_DEST (set)) | |
1642 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1643 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1644 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1645 | != REGNO_REG_CLASS (REGNO (operand))) | |
1646 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
bb4959a8 | 1647 | && REGNO (SET_DEST (set)) != REGNO (operand) |
1648 | && (!past_call | |
1649 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1650 | { | |
1651 | rtx xoperands[2]; | |
1652 | xoperands[0] = operand; | |
1653 | xoperands[1] = SET_DEST (set); | |
1654 | ||
1655 | output_asm_insn ("cmp %1,%0", xoperands); | |
1656 | return ""; | |
1657 | } | |
1658 | temp = PREV_INSN (temp); | |
1659 | } | |
1660 | return "cmp 0,%0"; | |
1661 | } | |
36ed4406 | 1662 | |
1663 | int | |
3285410a | 1664 | impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
36ed4406 | 1665 | { |
36ed4406 | 1666 | if (GET_CODE (op) != PLUS) |
1667 | return 0; | |
1668 | ||
19de5de1 | 1669 | if (XEXP (op, 0) == stack_pointer_rtx |
1670 | || XEXP (op, 1) == stack_pointer_rtx) | |
36ed4406 | 1671 | return 1; |
1672 | ||
36ed4406 | 1673 | return 0; |
1674 | } | |
c4cd8f6a | 1675 | |
9d3b5b5e | 1676 | /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used |
1677 | for the btst insn which may examine memory or a register (the memory | |
1678 | variant only allows an unsigned 8 bit integer). */ | |
1679 | int | |
3285410a | 1680 | const_8bit_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9d3b5b5e | 1681 | { |
1682 | return (GET_CODE (op) == CONST_INT | |
1683 | && INTVAL (op) >= 0 | |
1684 | && INTVAL (op) < 256); | |
1685 | } | |
1686 | ||
b166356e | 1687 | /* Return true if the operand is the 1.0f constant. */ |
1688 | int | |
3285410a | 1689 | const_1f_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
b166356e | 1690 | { |
1691 | return (op == CONST1_RTX (SFmode)); | |
1692 | } | |
1693 | ||
9d3b5b5e | 1694 | /* Similarly, but when using a zero_extract pattern for a btst where |
1695 | the source operand might end up in memory. */ | |
1696 | int | |
3285410a | 1697 | mask_ok_for_mem_btst (int len, int bit) |
9d3b5b5e | 1698 | { |
805e22b2 | 1699 | unsigned int mask = 0; |
9d3b5b5e | 1700 | |
1701 | while (len > 0) | |
1702 | { | |
1703 | mask |= (1 << bit); | |
1704 | bit++; | |
1705 | len--; | |
1706 | } | |
1707 | ||
1708 | /* MASK must bit into an 8bit value. */ | |
1709 | return (((mask & 0xff) == mask) | |
1710 | || ((mask & 0xff00) == mask) | |
1711 | || ((mask & 0xff0000) == mask) | |
1712 | || ((mask & 0xff000000) == mask)); | |
1713 | } | |
1714 | ||
c4cd8f6a | 1715 | /* Return 1 if X contains a symbolic expression. We know these |
1716 | expressions will have one of a few well defined forms, so | |
1717 | we need only check those forms. */ | |
1718 | int | |
3285410a | 1719 | symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
c4cd8f6a | 1720 | { |
1721 | switch (GET_CODE (op)) | |
1722 | { | |
1723 | case SYMBOL_REF: | |
1724 | case LABEL_REF: | |
1725 | return 1; | |
1726 | case CONST: | |
1727 | op = XEXP (op, 0); | |
1728 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1729 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
1730 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
1731 | default: | |
1732 | return 0; | |
1733 | } | |
1734 | } | |
1735 | ||
1736 | /* Try machine dependent ways of modifying an illegitimate address | |
1737 | to be legitimate. If we find one, return the new valid address. | |
1738 | This macro is used in only one place: `memory_address' in explow.c. | |
1739 | ||
1740 | OLDX is the address as it was before break_out_memory_refs was called. | |
1741 | In some cases it is useful to look at this to decide what needs to be done. | |
1742 | ||
1743 | MODE and WIN are passed so that this macro can use | |
1744 | GO_IF_LEGITIMATE_ADDRESS. | |
1745 | ||
1746 | Normally it is always safe for this macro to do nothing. It exists to | |
1747 | recognize opportunities to optimize the output. | |
1748 | ||
1749 | But on a few ports with segmented architectures and indexed addressing | |
1750 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
1751 | rtx | |
3285410a | 1752 | legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1753 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
c4cd8f6a | 1754 | { |
b87a151a | 1755 | if (flag_pic && ! legitimate_pic_operand_p (x)) |
1756 | x = legitimize_pic_address (oldx, NULL_RTX); | |
1757 | ||
c4cd8f6a | 1758 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1759 | special handling to avoid creating an indexed memory address | |
1760 | with x-100000 as the base. */ | |
1761 | if (GET_CODE (x) == PLUS | |
1762 | && symbolic_operand (XEXP (x, 1), VOIDmode)) | |
1763 | { | |
1764 | /* Ugly. We modify things here so that the address offset specified | |
1765 | by the index expression is computed first, then added to x to form | |
1766 | the entire address. */ | |
1767 | ||
59086782 | 1768 | rtx regx1, regy1, regy2, y; |
c4cd8f6a | 1769 | |
1770 | /* Strip off any CONST. */ | |
1771 | y = XEXP (x, 1); | |
1772 | if (GET_CODE (y) == CONST) | |
1773 | y = XEXP (y, 0); | |
1774 | ||
c927a8ab | 1775 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1776 | { | |
1777 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1778 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1779 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1780 | regx1 = force_reg (Pmode, | |
1781 | gen_rtx (GET_CODE (y), Pmode, regx1, regy2)); | |
7014838c | 1782 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
c927a8ab | 1783 | } |
c4cd8f6a | 1784 | } |
11b4605c | 1785 | return x; |
c4cd8f6a | 1786 | } |
e2aead91 | 1787 | |
b87a151a | 1788 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
1789 | @GOTOFF in `reg'. */ | |
1790 | rtx | |
3285410a | 1791 | legitimize_pic_address (rtx orig, rtx reg) |
b87a151a | 1792 | { |
1793 | if (GET_CODE (orig) == LABEL_REF | |
1794 | || (GET_CODE (orig) == SYMBOL_REF | |
1795 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1796 | || ! MN10300_GLOBAL_P (orig)))) | |
1797 | { | |
1798 | if (reg == 0) | |
1799 | reg = gen_reg_rtx (Pmode); | |
1800 | ||
1801 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
1802 | return reg; | |
1803 | } | |
1804 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1805 | { | |
1806 | if (reg == 0) | |
1807 | reg = gen_reg_rtx (Pmode); | |
1808 | ||
1809 | emit_insn (gen_symGOT2reg (reg, orig)); | |
1810 | return reg; | |
1811 | } | |
1812 | return orig; | |
1813 | } | |
1814 | ||
1815 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
fa483857 | 1816 | isn't protected by a PIC unspec; nonzero otherwise. */ |
b87a151a | 1817 | int |
3285410a | 1818 | legitimate_pic_operand_p (rtx x) |
b87a151a | 1819 | { |
1820 | register const char *fmt; | |
1821 | register int i; | |
1822 | ||
1823 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1824 | return 0; | |
1825 | ||
1826 | if (GET_CODE (x) == UNSPEC | |
1827 | && (XINT (x, 1) == UNSPEC_PIC | |
1828 | || XINT (x, 1) == UNSPEC_GOT | |
1829 | || XINT (x, 1) == UNSPEC_GOTOFF | |
1830 | || XINT (x, 1) == UNSPEC_PLT)) | |
1831 | return 1; | |
1832 | ||
1833 | if (GET_CODE (x) == QUEUED) | |
1834 | return legitimate_pic_operand_p (QUEUED_VAR (x)); | |
1835 | ||
1836 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
1837 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1838 | { | |
1839 | if (fmt[i] == 'E') | |
1840 | { | |
1841 | register int j; | |
1842 | ||
1843 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1844 | if (! legitimate_pic_operand_p (XVECEXP (x, i, j))) | |
1845 | return 0; | |
1846 | } | |
1847 | else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i))) | |
1848 | return 0; | |
1849 | } | |
1850 | ||
1851 | return 1; | |
1852 | } | |
1853 | ||
ec0457a8 | 1854 | static int |
3285410a | 1855 | mn10300_address_cost_1 (rtx x, int *unsig) |
e2aead91 | 1856 | { |
e2aead91 | 1857 | switch (GET_CODE (x)) |
1858 | { | |
1859 | case REG: | |
1860 | switch (REGNO_REG_CLASS (REGNO (x))) | |
1861 | { | |
1862 | case SP_REGS: | |
1863 | *unsig = 1; | |
1864 | return 0; | |
1865 | ||
1866 | case ADDRESS_REGS: | |
1867 | return 1; | |
1868 | ||
1869 | case DATA_REGS: | |
1870 | case EXTENDED_REGS: | |
b166356e | 1871 | case FP_REGS: |
e2aead91 | 1872 | return 3; |
1873 | ||
1874 | case NO_REGS: | |
1875 | return 5; | |
1876 | ||
1877 | default: | |
1878 | abort (); | |
1879 | } | |
1880 | ||
1881 | case PLUS: | |
1882 | case MINUS: | |
cbe23f2f | 1883 | case ASHIFT: |
1884 | case AND: | |
e2aead91 | 1885 | case IOR: |
ec0457a8 | 1886 | return (mn10300_address_cost_1 (XEXP (x, 0), unsig) |
1887 | + mn10300_address_cost_1 (XEXP (x, 1), unsig)); | |
e2aead91 | 1888 | |
1889 | case EXPR_LIST: | |
1890 | case SUBREG: | |
1891 | case MEM: | |
ec0457a8 | 1892 | return mn10300_address_cost (XEXP (x, 0)); |
e2aead91 | 1893 | |
1894 | case ZERO_EXTEND: | |
1895 | *unsig = 1; | |
ec0457a8 | 1896 | return mn10300_address_cost_1 (XEXP (x, 0), unsig); |
e2aead91 | 1897 | |
1898 | case CONST_INT: | |
1899 | if (INTVAL (x) == 0) | |
1900 | return 0; | |
1901 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
1902 | return 1; | |
1903 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
1904 | return 3; | |
1905 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
1906 | return 5; | |
1907 | return 7; | |
1908 | ||
1909 | case CONST: | |
1910 | case SYMBOL_REF: | |
cbe23f2f | 1911 | case LABEL_REF: |
e2aead91 | 1912 | return 8; |
1913 | ||
1914 | case ADDRESSOF: | |
1915 | switch (GET_CODE (XEXP (x, 0))) | |
1916 | { | |
1917 | case MEM: | |
ec0457a8 | 1918 | return mn10300_address_cost (XEXP (x, 0)); |
e2aead91 | 1919 | |
1920 | case REG: | |
1921 | return 1; | |
1922 | ||
1923 | default: | |
1924 | abort (); | |
1925 | } | |
1926 | ||
1927 | default: | |
1928 | abort (); | |
1929 | ||
1930 | } | |
1931 | } | |
fab7adbf | 1932 | |
ec0457a8 | 1933 | static int |
3285410a | 1934 | mn10300_address_cost (rtx x) |
ec0457a8 | 1935 | { |
1936 | int s = 0; | |
1937 | return mn10300_address_cost_1 (x, &s); | |
1938 | } | |
1939 | ||
fab7adbf | 1940 | static bool |
3285410a | 1941 | mn10300_rtx_costs (rtx x, int code, int outer_code, int *total) |
fab7adbf | 1942 | { |
1943 | switch (code) | |
1944 | { | |
1945 | case CONST_INT: | |
1946 | /* Zeros are extremely cheap. */ | |
1947 | if (INTVAL (x) == 0 && outer_code == SET) | |
1948 | *total = 0; | |
1949 | /* If it fits in 8 bits, then it's still relatively cheap. */ | |
1950 | else if (INT_8_BITS (INTVAL (x))) | |
1951 | *total = 1; | |
1952 | /* This is the "base" cost, includes constants where either the | |
1953 | upper or lower 16bits are all zeros. */ | |
1954 | else if (INT_16_BITS (INTVAL (x)) | |
1955 | || (INTVAL (x) & 0xffff) == 0 | |
1956 | || (INTVAL (x) & 0xffff0000) == 0) | |
1957 | *total = 2; | |
1958 | else | |
1959 | *total = 4; | |
1960 | return true; | |
1961 | ||
1962 | case CONST: | |
1963 | case LABEL_REF: | |
1964 | case SYMBOL_REF: | |
1965 | /* These are more costly than a CONST_INT, but we can relax them, | |
1966 | so they're less costly than a CONST_DOUBLE. */ | |
1967 | *total = 6; | |
1968 | return true; | |
1969 | ||
1970 | case CONST_DOUBLE: | |
1971 | /* We don't optimize CONST_DOUBLEs well nor do we relax them well, | |
1972 | so their cost is very high. */ | |
1973 | *total = 8; | |
1974 | return true; | |
1975 | ||
1976 | /* ??? This probably needs more work. */ | |
1977 | case MOD: | |
1978 | case DIV: | |
1979 | case MULT: | |
1980 | *total = 8; | |
1981 | return true; | |
1982 | ||
1983 | default: | |
1984 | return false; | |
1985 | } | |
1986 | } | |
8935d57c | 1987 | |
1988 | /* Check whether a constant used to initialize a DImode or DFmode can | |
1989 | use a clr instruction. The code here must be kept in sync with | |
1990 | movdf and movdi. */ | |
1991 | ||
1992 | bool | |
3285410a | 1993 | mn10300_wide_const_load_uses_clr (rtx operands[2]) |
8935d57c | 1994 | { |
1995 | long val[2]; | |
1996 | ||
1997 | if (GET_CODE (operands[0]) != REG | |
1998 | || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS) | |
1999 | return false; | |
2000 | ||
2001 | switch (GET_CODE (operands[1])) | |
2002 | { | |
2003 | case CONST_INT: | |
2004 | { | |
2005 | rtx low, high; | |
2006 | split_double (operands[1], &low, &high); | |
2007 | val[0] = INTVAL (low); | |
2008 | val[1] = INTVAL (high); | |
2009 | } | |
2010 | break; | |
2011 | ||
2012 | case CONST_DOUBLE: | |
2013 | if (GET_MODE (operands[1]) == DFmode) | |
2014 | { | |
2015 | REAL_VALUE_TYPE rv; | |
2016 | ||
2017 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
2018 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
2019 | } | |
2020 | else if (GET_MODE (operands[1]) == VOIDmode | |
2021 | || GET_MODE (operands[1]) == DImode) | |
2022 | { | |
2023 | val[0] = CONST_DOUBLE_LOW (operands[1]); | |
2024 | val[1] = CONST_DOUBLE_HIGH (operands[1]); | |
2025 | } | |
2026 | break; | |
2027 | ||
2028 | default: | |
2029 | return false; | |
2030 | } | |
2031 | ||
2032 | return val[0] == 0 || val[1] == 0; | |
2033 | } | |
b87a151a | 2034 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2035 | may access it using GOTOFF instead of GOT. */ | |
2036 | ||
2037 | static void | |
48ed5fc2 | 2038 | mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED) |
b87a151a | 2039 | { |
2040 | rtx symbol; | |
2041 | ||
2042 | if (GET_CODE (rtl) != MEM) | |
2043 | return; | |
2044 | symbol = XEXP (rtl, 0); | |
2045 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2046 | return; | |
2047 | ||
2048 | if (flag_pic) | |
2049 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2050 | } |