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Commit | Line | Data |
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11bb1f11 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
fe9565ed | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
92547f12 | 3 | Free Software Foundation, Inc. |
11bb1f11 JL |
4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
7ec022b2 | 6 | This file is part of GCC. |
11bb1f11 | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
11bb1f11 JL |
9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
11bb1f11 JL |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 19 | along with GCC; see the file COPYING. If not, write to |
11bb1f11 JL |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
11bb1f11 | 23 | #include "config.h" |
c5c76735 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
11bb1f11 | 27 | #include "rtl.h" |
bf6bb899 | 28 | #include "tree.h" |
11bb1f11 JL |
29 | #include "regs.h" |
30 | #include "hard-reg-set.h" | |
31 | #include "real.h" | |
32 | #include "insn-config.h" | |
33 | #include "conditions.h" | |
11bb1f11 JL |
34 | #include "output.h" |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "recog.h" | |
38 | #include "expr.h" | |
e78d8e51 | 39 | #include "optabs.h" |
bf6bb899 | 40 | #include "function.h" |
11bb1f11 | 41 | #include "obstack.h" |
69bc71fa KG |
42 | #include "toplev.h" |
43 | #include "tm_p.h" | |
672a6f42 NB |
44 | #include "target.h" |
45 | #include "target-def.h" | |
11bb1f11 | 46 | |
d1776069 AO |
47 | /* This is used by GOTaddr2picreg to uniquely identify |
48 | UNSPEC_INT_LABELs. */ | |
49 | int mn10300_unspec_int_label_counter; | |
50 | ||
2beef00e AO |
51 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
52 | names are not prefixed by underscores, to tell whether to prefix a | |
53 | label with a plus sign or not, so that the assembler can tell | |
54 | symbol names from register names. */ | |
55 | int mn10300_protect_label; | |
56 | ||
13dd556c RS |
57 | /* The selected processor. */ |
58 | enum processor_type mn10300_processor = PROCESSOR_DEFAULT; | |
59 | ||
4d1a91c2 JL |
60 | /* The size of the callee register save area. Right now we save everything |
61 | on entry since it costs us nothing in code size. It does cost us from a | |
62 | speed standpoint, so we want to optimize this sooner or later. */ | |
980d0e81 JL |
63 | #define REG_SAVE_BYTES (4 * regs_ever_live[2] \ |
64 | + 4 * regs_ever_live[3] \ | |
705ac34f JL |
65 | + 4 * regs_ever_live[6] \ |
66 | + 4 * regs_ever_live[7] \ | |
67 | + 16 * (regs_ever_live[14] || regs_ever_live[15] \ | |
68 | || regs_ever_live[16] || regs_ever_live[17])) | |
3c50106f RH |
69 | |
70 | ||
13dd556c | 71 | static bool mn10300_handle_option (size_t, const char *, int); |
7f682641 SB |
72 | static int mn10300_address_cost_1 (rtx, int *); |
73 | static int mn10300_address_cost (rtx); | |
74 | static bool mn10300_rtx_costs (rtx, int, int, int *); | |
75 | static void mn10300_file_start (void); | |
9024ea92 KH |
76 | static bool mn10300_return_in_memory (tree, tree); |
77 | static rtx mn10300_builtin_saveregs (void); | |
8cd5a4e0 RH |
78 | static bool mn10300_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
79 | tree, bool); | |
78a52f11 RH |
80 | static int mn10300_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
81 | tree, bool); | |
672a6f42 NB |
82 | \f |
83 | /* Initialize the GCC target structure. */ | |
301d03af RS |
84 | #undef TARGET_ASM_ALIGNED_HI_OP |
85 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
4d1a91c2 | 86 | |
3c50106f RH |
87 | #undef TARGET_RTX_COSTS |
88 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
dcefdf67 RH |
89 | #undef TARGET_ADDRESS_COST |
90 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
3c50106f | 91 | |
1bc7c5b6 ZW |
92 | #undef TARGET_ASM_FILE_START |
93 | #define TARGET_ASM_FILE_START mn10300_file_start | |
94 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
95 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
96 | ||
13dd556c RS |
97 | #undef TARGET_DEFAULT_TARGET_FLAGS |
98 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | |
99 | #undef TARGET_HANDLE_OPTION | |
100 | #define TARGET_HANDLE_OPTION mn10300_handle_option | |
101 | ||
d1776069 AO |
102 | #undef TARGET_ENCODE_SECTION_INFO |
103 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
104 | ||
9024ea92 KH |
105 | #undef TARGET_PROMOTE_PROTOTYPES |
106 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
9024ea92 KH |
107 | #undef TARGET_RETURN_IN_MEMORY |
108 | #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory | |
8cd5a4e0 RH |
109 | #undef TARGET_PASS_BY_REFERENCE |
110 | #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference | |
6cdd5672 RH |
111 | #undef TARGET_CALLEE_COPIES |
112 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
78a52f11 RH |
113 | #undef TARGET_ARG_PARTIAL_BYTES |
114 | #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes | |
9024ea92 KH |
115 | |
116 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
117 | #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs | |
118 | ||
d1776069 | 119 | static void mn10300_encode_section_info (tree, rtx, int); |
f6897b10 | 120 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 121 | \f |
13dd556c RS |
122 | /* Implement TARGET_HANDLE_OPTION. */ |
123 | ||
124 | static bool | |
125 | mn10300_handle_option (size_t code, | |
126 | const char *arg ATTRIBUTE_UNUSED, | |
127 | int value) | |
128 | { | |
129 | switch (code) | |
130 | { | |
131 | case OPT_mam33: | |
132 | mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300; | |
133 | return true; | |
134 | case OPT_mam33_2: | |
135 | mn10300_processor = (value | |
136 | ? PROCESSOR_AM33_2 | |
137 | : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT)); | |
138 | return true; | |
139 | default: | |
140 | return true; | |
141 | } | |
142 | } | |
143 | ||
144 | /* Implement OVERRIDE_OPTIONS. */ | |
145 | ||
146 | void | |
147 | mn10300_override_options (void) | |
148 | { | |
149 | if (TARGET_AM33) | |
150 | target_flags &= ~MASK_MULT_BUG; | |
151 | } | |
152 | ||
1bc7c5b6 | 153 | static void |
f1777882 | 154 | mn10300_file_start (void) |
11bb1f11 | 155 | { |
1bc7c5b6 | 156 | default_file_start (); |
705ac34f | 157 | |
18e9d2f9 AO |
158 | if (TARGET_AM33_2) |
159 | fprintf (asm_out_file, "\t.am33_2\n"); | |
160 | else if (TARGET_AM33) | |
1bc7c5b6 | 161 | fprintf (asm_out_file, "\t.am33\n"); |
11bb1f11 JL |
162 | } |
163 | \f | |
164 | ||
11bb1f11 JL |
165 | /* Print operand X using operand code CODE to assembly language output file |
166 | FILE. */ | |
167 | ||
168 | void | |
f1777882 | 169 | print_operand (FILE *file, rtx x, int code) |
11bb1f11 JL |
170 | { |
171 | switch (code) | |
172 | { | |
173 | case 'b': | |
174 | case 'B': | |
18e9d2f9 AO |
175 | if (cc_status.mdep.fpCC) |
176 | { | |
177 | switch (code == 'b' ? GET_CODE (x) | |
178 | : reverse_condition_maybe_unordered (GET_CODE (x))) | |
179 | { | |
180 | case NE: | |
181 | fprintf (file, "ne"); | |
182 | break; | |
183 | case EQ: | |
184 | fprintf (file, "eq"); | |
185 | break; | |
186 | case GE: | |
187 | fprintf (file, "ge"); | |
188 | break; | |
189 | case GT: | |
190 | fprintf (file, "gt"); | |
191 | break; | |
192 | case LE: | |
193 | fprintf (file, "le"); | |
194 | break; | |
195 | case LT: | |
196 | fprintf (file, "lt"); | |
197 | break; | |
198 | case ORDERED: | |
199 | fprintf (file, "lge"); | |
200 | break; | |
201 | case UNORDERED: | |
202 | fprintf (file, "uo"); | |
203 | break; | |
204 | case LTGT: | |
205 | fprintf (file, "lg"); | |
206 | break; | |
207 | case UNEQ: | |
208 | fprintf (file, "ue"); | |
209 | break; | |
210 | case UNGE: | |
211 | fprintf (file, "uge"); | |
212 | break; | |
213 | case UNGT: | |
214 | fprintf (file, "ug"); | |
215 | break; | |
216 | case UNLE: | |
217 | fprintf (file, "ule"); | |
218 | break; | |
219 | case UNLT: | |
220 | fprintf (file, "ul"); | |
221 | break; | |
222 | default: | |
223 | abort (); | |
224 | } | |
225 | break; | |
226 | } | |
11bb1f11 JL |
227 | /* These are normal and reversed branches. */ |
228 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
229 | { | |
230 | case NE: | |
231 | fprintf (file, "ne"); | |
232 | break; | |
233 | case EQ: | |
234 | fprintf (file, "eq"); | |
235 | break; | |
236 | case GE: | |
237 | fprintf (file, "ge"); | |
238 | break; | |
239 | case GT: | |
240 | fprintf (file, "gt"); | |
241 | break; | |
242 | case LE: | |
243 | fprintf (file, "le"); | |
244 | break; | |
245 | case LT: | |
246 | fprintf (file, "lt"); | |
247 | break; | |
248 | case GEU: | |
249 | fprintf (file, "cc"); | |
250 | break; | |
251 | case GTU: | |
252 | fprintf (file, "hi"); | |
253 | break; | |
254 | case LEU: | |
255 | fprintf (file, "ls"); | |
256 | break; | |
257 | case LTU: | |
258 | fprintf (file, "cs"); | |
259 | break; | |
260 | default: | |
261 | abort (); | |
262 | } | |
263 | break; | |
264 | case 'C': | |
265 | /* This is used for the operand to a call instruction; | |
266 | if it's a REG, enclose it in parens, else output | |
267 | the operand normally. */ | |
268 | if (GET_CODE (x) == REG) | |
269 | { | |
270 | fputc ('(', file); | |
271 | print_operand (file, x, 0); | |
272 | fputc (')', file); | |
273 | } | |
274 | else | |
275 | print_operand (file, x, 0); | |
276 | break; | |
277 | ||
18e9d2f9 AO |
278 | case 'D': |
279 | switch (GET_CODE (x)) | |
280 | { | |
281 | case MEM: | |
282 | fputc ('(', file); | |
283 | output_address (XEXP (x, 0)); | |
284 | fputc (')', file); | |
285 | break; | |
286 | ||
287 | case REG: | |
288 | fprintf (file, "fd%d", REGNO (x) - 18); | |
289 | break; | |
290 | ||
291 | default: | |
292 | abort (); | |
293 | } | |
294 | break; | |
295 | ||
38c37a0e JL |
296 | /* These are the least significant word in a 64bit value. */ |
297 | case 'L': | |
298 | switch (GET_CODE (x)) | |
299 | { | |
300 | case MEM: | |
301 | fputc ('(', file); | |
302 | output_address (XEXP (x, 0)); | |
303 | fputc (')', file); | |
304 | break; | |
305 | ||
306 | case REG: | |
307 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
308 | break; | |
309 | ||
310 | case SUBREG: | |
ddef6bc7 | 311 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
38c37a0e JL |
312 | break; |
313 | ||
314 | case CONST_DOUBLE: | |
315 | { | |
316 | long val[2]; | |
317 | REAL_VALUE_TYPE rv; | |
318 | ||
319 | switch (GET_MODE (x)) | |
320 | { | |
321 | case DFmode: | |
322 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
323 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 324 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
325 | break;; |
326 | case SFmode: | |
327 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
328 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
cf31fafa | 329 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
330 | break;; |
331 | case VOIDmode: | |
332 | case DImode: | |
333 | print_operand_address (file, | |
334 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
335 | break; | |
69bc71fa KG |
336 | default: |
337 | break; | |
38c37a0e JL |
338 | } |
339 | break; | |
340 | } | |
341 | ||
342 | case CONST_INT: | |
212bc5fa AO |
343 | { |
344 | rtx low, high; | |
345 | split_double (x, &low, &high); | |
346 | fprintf (file, "%ld", (long)INTVAL (low)); | |
347 | break; | |
348 | } | |
38c37a0e JL |
349 | |
350 | default: | |
351 | abort (); | |
352 | } | |
353 | break; | |
354 | ||
355 | /* Similarly, but for the most significant word. */ | |
356 | case 'H': | |
357 | switch (GET_CODE (x)) | |
358 | { | |
359 | case MEM: | |
360 | fputc ('(', file); | |
b72f00af | 361 | x = adjust_address (x, SImode, 4); |
38c37a0e JL |
362 | output_address (XEXP (x, 0)); |
363 | fputc (')', file); | |
364 | break; | |
365 | ||
366 | case REG: | |
367 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
368 | break; | |
369 | ||
370 | case SUBREG: | |
ddef6bc7 | 371 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
38c37a0e JL |
372 | break; |
373 | ||
374 | case CONST_DOUBLE: | |
375 | { | |
376 | long val[2]; | |
377 | REAL_VALUE_TYPE rv; | |
378 | ||
379 | switch (GET_MODE (x)) | |
380 | { | |
381 | case DFmode: | |
382 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
383 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 384 | fprintf (file, "0x%lx", val[1]); |
38c37a0e JL |
385 | break;; |
386 | case SFmode: | |
387 | abort (); | |
388 | case VOIDmode: | |
389 | case DImode: | |
390 | print_operand_address (file, | |
391 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
392 | break; | |
69bc71fa KG |
393 | default: |
394 | break; | |
38c37a0e JL |
395 | } |
396 | break; | |
397 | } | |
398 | ||
399 | case CONST_INT: | |
212bc5fa AO |
400 | { |
401 | rtx low, high; | |
402 | split_double (x, &low, &high); | |
403 | fprintf (file, "%ld", (long)INTVAL (high)); | |
404 | break; | |
405 | } | |
406 | ||
38c37a0e JL |
407 | default: |
408 | abort (); | |
409 | } | |
410 | break; | |
411 | ||
412 | case 'A': | |
413 | fputc ('(', file); | |
414 | if (GET_CODE (XEXP (x, 0)) == REG) | |
a556fd39 | 415 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx)); |
38c37a0e JL |
416 | else |
417 | output_address (XEXP (x, 0)); | |
418 | fputc (')', file); | |
419 | break; | |
420 | ||
6fafc523 | 421 | case 'N': |
a58be199 AO |
422 | if (INTVAL (x) < -128 || INTVAL (x) > 255) |
423 | abort (); | |
424 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); | |
425 | break; | |
426 | ||
427 | case 'U': | |
428 | if (INTVAL (x) < -128 || INTVAL (x) > 255) | |
429 | abort (); | |
430 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); | |
6fafc523 JL |
431 | break; |
432 | ||
576e5acc JL |
433 | /* For shift counts. The hardware ignores the upper bits of |
434 | any immediate, but the assembler will flag an out of range | |
435 | shift count as an error. So we mask off the high bits | |
436 | of the immediate here. */ | |
437 | case 'S': | |
438 | if (GET_CODE (x) == CONST_INT) | |
439 | { | |
a58be199 | 440 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
576e5acc JL |
441 | break; |
442 | } | |
443 | /* FALL THROUGH */ | |
444 | ||
11bb1f11 JL |
445 | default: |
446 | switch (GET_CODE (x)) | |
447 | { | |
448 | case MEM: | |
449 | fputc ('(', file); | |
450 | output_address (XEXP (x, 0)); | |
451 | fputc (')', file); | |
452 | break; | |
453 | ||
38c37a0e JL |
454 | case PLUS: |
455 | output_address (x); | |
456 | break; | |
457 | ||
11bb1f11 JL |
458 | case REG: |
459 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
460 | break; | |
461 | ||
462 | case SUBREG: | |
ddef6bc7 | 463 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
11bb1f11 JL |
464 | break; |
465 | ||
38c37a0e JL |
466 | /* This will only be single precision.... */ |
467 | case CONST_DOUBLE: | |
468 | { | |
469 | unsigned long val; | |
470 | REAL_VALUE_TYPE rv; | |
471 | ||
472 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
473 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
cf31fafa | 474 | fprintf (file, "0x%lx", val); |
38c37a0e JL |
475 | break; |
476 | } | |
477 | ||
11bb1f11 JL |
478 | case CONST_INT: |
479 | case SYMBOL_REF: | |
480 | case CONST: | |
481 | case LABEL_REF: | |
482 | case CODE_LABEL: | |
d1776069 | 483 | case UNSPEC: |
11bb1f11 JL |
484 | print_operand_address (file, x); |
485 | break; | |
486 | default: | |
487 | abort (); | |
488 | } | |
489 | break; | |
490 | } | |
491 | } | |
492 | ||
493 | /* Output assembly language output for the address ADDR to FILE. */ | |
494 | ||
495 | void | |
f1777882 | 496 | print_operand_address (FILE *file, rtx addr) |
11bb1f11 JL |
497 | { |
498 | switch (GET_CODE (addr)) | |
499 | { | |
705ac34f JL |
500 | case POST_INC: |
501 | print_operand_address (file, XEXP (addr, 0)); | |
502 | fputc ('+', file); | |
503 | break; | |
11bb1f11 | 504 | case REG: |
79e4122c | 505 | print_operand (file, addr, 0); |
11bb1f11 JL |
506 | break; |
507 | case PLUS: | |
508 | { | |
509 | rtx base, index; | |
510 | if (REG_P (XEXP (addr, 0)) | |
511 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
512 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
513 | else if (REG_P (XEXP (addr, 1)) | |
514 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
515 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
516 | else | |
517 | abort (); | |
518 | print_operand (file, index, 0); | |
519 | fputc (',', file); | |
520 | print_operand (file, base, 0);; | |
521 | break; | |
522 | } | |
523 | case SYMBOL_REF: | |
524 | output_addr_const (file, addr); | |
525 | break; | |
526 | default: | |
527 | output_addr_const (file, addr); | |
528 | break; | |
529 | } | |
530 | } | |
531 | ||
18e9d2f9 AO |
532 | /* Count the number of FP registers that have to be saved. */ |
533 | static int | |
f1777882 | 534 | fp_regs_to_save (void) |
18e9d2f9 AO |
535 | { |
536 | int i, n = 0; | |
537 | ||
538 | if (! TARGET_AM33_2) | |
539 | return 0; | |
540 | ||
541 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
542 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
543 | ++n; | |
544 | ||
545 | return n; | |
546 | } | |
547 | ||
f6cd7c62 RS |
548 | /* Print a set of registers in the format required by "movm" and "ret". |
549 | Register K is saved if bit K of MASK is set. The data and address | |
550 | registers can be stored individually, but the extended registers cannot. | |
551 | We assume that the mask alread takes that into account. For instance, | |
8596d0a1 | 552 | bits 14 to 17 must have the same value. */ |
f6cd7c62 RS |
553 | |
554 | void | |
f1777882 | 555 | mn10300_print_reg_list (FILE *file, int mask) |
f6cd7c62 RS |
556 | { |
557 | int need_comma; | |
558 | int i; | |
559 | ||
560 | need_comma = 0; | |
561 | fputc ('[', file); | |
562 | ||
563 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
564 | if ((mask & (1 << i)) != 0) | |
565 | { | |
566 | if (need_comma) | |
567 | fputc (',', file); | |
568 | fputs (reg_names [i], file); | |
569 | need_comma = 1; | |
570 | } | |
571 | ||
572 | if ((mask & 0x3c000) != 0) | |
573 | { | |
574 | if ((mask & 0x3c000) != 0x3c000) | |
575 | abort(); | |
576 | if (need_comma) | |
577 | fputc (',', file); | |
578 | fputs ("exreg1", file); | |
579 | need_comma = 1; | |
580 | } | |
581 | ||
582 | fputc (']', file); | |
583 | } | |
584 | ||
38c37a0e | 585 | int |
f1777882 | 586 | can_use_return_insn (void) |
38c37a0e | 587 | { |
460f4b9d JL |
588 | /* size includes the fixed stack space needed for function calls. */ |
589 | int size = get_frame_size () + current_function_outgoing_args_size; | |
590 | ||
591 | /* And space for the return pointer. */ | |
592 | size += current_function_outgoing_args_size ? 4 : 0; | |
38c37a0e JL |
593 | |
594 | return (reload_completed | |
595 | && size == 0 | |
596 | && !regs_ever_live[2] | |
597 | && !regs_ever_live[3] | |
598 | && !regs_ever_live[6] | |
599 | && !regs_ever_live[7] | |
705ac34f JL |
600 | && !regs_ever_live[14] |
601 | && !regs_ever_live[15] | |
602 | && !regs_ever_live[16] | |
603 | && !regs_ever_live[17] | |
18e9d2f9 | 604 | && fp_regs_to_save () == 0 |
38c37a0e JL |
605 | && !frame_pointer_needed); |
606 | } | |
607 | ||
f6cd7c62 RS |
608 | /* Returns the set of live, callee-saved registers as a bitmask. The |
609 | callee-saved extended registers cannot be stored individually, so | |
8596d0a1 | 610 | all of them will be included in the mask if any one of them is used. */ |
f6cd7c62 RS |
611 | |
612 | int | |
f1777882 | 613 | mn10300_get_live_callee_saved_regs (void) |
f6cd7c62 RS |
614 | { |
615 | int mask; | |
616 | int i; | |
617 | ||
618 | mask = 0; | |
18e9d2f9 | 619 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
f6cd7c62 RS |
620 | if (regs_ever_live[i] && ! call_used_regs[i]) |
621 | mask |= (1 << i); | |
622 | if ((mask & 0x3c000) != 0) | |
623 | mask |= 0x3c000; | |
624 | ||
625 | return mask; | |
626 | } | |
627 | ||
628 | /* Generate an instruction that pushes several registers onto the stack. | |
629 | Register K will be saved if bit K in MASK is set. The function does | |
630 | nothing if MASK is zero. | |
631 | ||
632 | To be compatible with the "movm" instruction, the lowest-numbered | |
633 | register must be stored in the lowest slot. If MASK is the set | |
634 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
635 | instruction will have the form: | |
636 | ||
637 | (parallel | |
638 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
639 | (set (mem:SI (plus:SI (reg:SI 9) | |
640 | (const_int -1*4))) | |
641 | (reg:SI RN)) | |
642 | ... | |
643 | (set (mem:SI (plus:SI (reg:SI 9) | |
644 | (const_int -N*4))) | |
645 | (reg:SI R1))) */ | |
646 | ||
647 | void | |
f1777882 | 648 | mn10300_gen_multiple_store (int mask) |
f6cd7c62 RS |
649 | { |
650 | if (mask != 0) | |
651 | { | |
652 | int i; | |
653 | int count; | |
654 | rtx par; | |
655 | int pari; | |
656 | ||
8596d0a1 | 657 | /* Count how many registers need to be saved. */ |
f6cd7c62 | 658 | count = 0; |
18e9d2f9 | 659 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
f6cd7c62 RS |
660 | if ((mask & (1 << i)) != 0) |
661 | count += 1; | |
662 | ||
663 | /* We need one PARALLEL element to update the stack pointer and | |
8596d0a1 | 664 | an additional element for each register that is stored. */ |
f6cd7c62 RS |
665 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
666 | ||
8596d0a1 | 667 | /* Create the instruction that updates the stack pointer. */ |
f6cd7c62 RS |
668 | XVECEXP (par, 0, 0) |
669 | = gen_rtx_SET (SImode, | |
670 | stack_pointer_rtx, | |
671 | gen_rtx_PLUS (SImode, | |
672 | stack_pointer_rtx, | |
673 | GEN_INT (-count * 4))); | |
674 | ||
8596d0a1 | 675 | /* Create each store. */ |
f6cd7c62 | 676 | pari = 1; |
18e9d2f9 | 677 | for (i = LAST_EXTENDED_REGNUM; i >= 0; i--) |
f6cd7c62 RS |
678 | if ((mask & (1 << i)) != 0) |
679 | { | |
680 | rtx address = gen_rtx_PLUS (SImode, | |
681 | stack_pointer_rtx, | |
682 | GEN_INT (-pari * 4)); | |
683 | XVECEXP(par, 0, pari) | |
684 | = gen_rtx_SET (VOIDmode, | |
685 | gen_rtx_MEM (SImode, address), | |
686 | gen_rtx_REG (SImode, i)); | |
687 | pari += 1; | |
688 | } | |
689 | ||
690 | par = emit_insn (par); | |
691 | RTX_FRAME_RELATED_P (par) = 1; | |
692 | } | |
693 | } | |
694 | ||
11bb1f11 | 695 | void |
f1777882 | 696 | expand_prologue (void) |
11bb1f11 | 697 | { |
036182e7 | 698 | HOST_WIDE_INT size; |
3dbc43d1 | 699 | |
3dbc43d1 | 700 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
701 | size = get_frame_size () + current_function_outgoing_args_size; |
702 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 703 | |
8596d0a1 | 704 | /* If we use any of the callee-saved registers, save them now. */ |
f6cd7c62 | 705 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); |
777fbf09 | 706 | |
18e9d2f9 AO |
707 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
708 | { | |
709 | int num_regs_to_save = fp_regs_to_save (), i; | |
710 | HOST_WIDE_INT xsize; | |
711 | enum { save_sp_merge, | |
712 | save_sp_no_merge, | |
713 | save_sp_partial_merge, | |
714 | save_a0_merge, | |
715 | save_a0_no_merge } strategy; | |
716 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; | |
717 | rtx reg; | |
718 | rtx insn; | |
719 | ||
720 | /* We have several different strategies to save FP registers. | |
721 | We can store them using SP offsets, which is beneficial if | |
722 | there are just a few registers to save, or we can use `a0' in | |
723 | post-increment mode (`a0' is the only call-clobbered address | |
724 | register that is never used to pass information to a | |
725 | function). Furthermore, if we don't need a frame pointer, we | |
726 | can merge the two SP adds into a single one, but this isn't | |
727 | always beneficial; sometimes we can just split the two adds | |
728 | so that we don't exceed a 16-bit constant size. The code | |
729 | below will select which strategy to use, so as to generate | |
730 | smallest code. Ties are broken in favor or shorter sequences | |
731 | (in terms of number of instructions). */ | |
732 | ||
733 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
734 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
735 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
736 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
737 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ | |
738 | (((S) >= (L)) ? (SIZE1) * (N) \ | |
739 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ | |
740 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
741 | : (ELSE)) | |
742 | #define SIZE_FMOV_SP_(S,N) \ | |
743 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
744 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
745 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
746 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
747 | ||
748 | /* Consider alternative save_sp_merge only if we don't need the | |
4375e090 | 749 | frame pointer and size is nonzero. */ |
18e9d2f9 AO |
750 | if (! frame_pointer_needed && size) |
751 | { | |
752 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
753 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
754 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
755 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
756 | ||
757 | if (this_strategy_size < strategy_size) | |
758 | { | |
759 | strategy = save_sp_merge; | |
760 | strategy_size = this_strategy_size; | |
761 | } | |
762 | } | |
763 | ||
764 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
765 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
766 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
767 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
768 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
769 | if (size) | |
770 | { | |
771 | /* Insn: add -size, sp. */ | |
772 | this_strategy_size += SIZE_ADD_SP (-size); | |
773 | } | |
774 | ||
775 | if (this_strategy_size < strategy_size) | |
776 | { | |
777 | strategy = save_sp_no_merge; | |
778 | strategy_size = this_strategy_size; | |
779 | } | |
780 | ||
781 | /* Consider alternative save_sp_partial_merge only if we don't | |
782 | need a frame pointer and size is reasonably large. */ | |
783 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
784 | { | |
785 | /* Insn: add -128, sp. */ | |
786 | this_strategy_size = SIZE_ADD_SP (-128); | |
787 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
788 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
789 | num_regs_to_save); | |
790 | if (size) | |
791 | { | |
792 | /* Insn: add 128-size, sp. */ | |
793 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
794 | } | |
795 | ||
796 | if (this_strategy_size < strategy_size) | |
797 | { | |
798 | strategy = save_sp_partial_merge; | |
799 | strategy_size = this_strategy_size; | |
800 | } | |
801 | } | |
802 | ||
803 | /* Consider alternative save_a0_merge only if we don't need a | |
4375e090 | 804 | frame pointer, size is nonzero and the user hasn't |
18e9d2f9 AO |
805 | changed the calling conventions of a0. */ |
806 | if (! frame_pointer_needed && size | |
807 | && call_used_regs[FIRST_ADDRESS_REGNUM] | |
808 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) | |
809 | { | |
810 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
811 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
812 | /* Insn: mov sp, a0. */ | |
813 | this_strategy_size++; | |
814 | if (size) | |
815 | { | |
816 | /* Insn: add size, a0. */ | |
817 | this_strategy_size += SIZE_ADD_AX (size); | |
818 | } | |
819 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
820 | this_strategy_size += 3 * num_regs_to_save; | |
821 | ||
822 | if (this_strategy_size < strategy_size) | |
823 | { | |
824 | strategy = save_a0_merge; | |
825 | strategy_size = this_strategy_size; | |
826 | } | |
827 | } | |
828 | ||
829 | /* Consider alternative save_a0_no_merge if the user hasn't | |
8596d0a1 | 830 | changed the calling conventions of a0. */ |
18e9d2f9 AO |
831 | if (call_used_regs[FIRST_ADDRESS_REGNUM] |
832 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) | |
833 | { | |
834 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
835 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
836 | /* Insn: mov sp, a0. */ | |
837 | this_strategy_size++; | |
838 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
839 | this_strategy_size += 3 * num_regs_to_save; | |
840 | if (size) | |
841 | { | |
842 | /* Insn: add -size, sp. */ | |
843 | this_strategy_size += SIZE_ADD_SP (-size); | |
844 | } | |
845 | ||
846 | if (this_strategy_size < strategy_size) | |
847 | { | |
848 | strategy = save_a0_no_merge; | |
849 | strategy_size = this_strategy_size; | |
850 | } | |
851 | } | |
852 | ||
853 | /* Emit the initial SP add, common to all strategies. */ | |
854 | switch (strategy) | |
855 | { | |
856 | case save_sp_no_merge: | |
857 | case save_a0_no_merge: | |
858 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
859 | stack_pointer_rtx, | |
860 | GEN_INT (-4 * num_regs_to_save))); | |
861 | xsize = 0; | |
862 | break; | |
863 | ||
864 | case save_sp_partial_merge: | |
865 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
866 | stack_pointer_rtx, | |
867 | GEN_INT (-128))); | |
868 | xsize = 128 - 4 * num_regs_to_save; | |
869 | size -= xsize; | |
870 | break; | |
871 | ||
872 | case save_sp_merge: | |
873 | case save_a0_merge: | |
874 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
875 | stack_pointer_rtx, | |
876 | GEN_INT (-(size + 4 * num_regs_to_save)))); | |
877 | /* We'll have to adjust FP register saves according to the | |
8596d0a1 | 878 | frame size. */ |
18e9d2f9 AO |
879 | xsize = size; |
880 | /* Since we've already created the stack frame, don't do it | |
8596d0a1 | 881 | again at the end of the function. */ |
18e9d2f9 AO |
882 | size = 0; |
883 | break; | |
884 | ||
885 | default: | |
886 | abort (); | |
887 | } | |
888 | ||
889 | /* Now prepare register a0, if we have decided to use it. */ | |
890 | switch (strategy) | |
891 | { | |
892 | case save_sp_merge: | |
893 | case save_sp_no_merge: | |
894 | case save_sp_partial_merge: | |
895 | reg = 0; | |
896 | break; | |
897 | ||
898 | case save_a0_merge: | |
899 | case save_a0_no_merge: | |
900 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
901 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
902 | if (xsize) | |
903 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))); | |
904 | reg = gen_rtx_POST_INC (SImode, reg); | |
905 | break; | |
906 | ||
907 | default: | |
908 | abort (); | |
909 | } | |
910 | ||
911 | /* Now actually save the FP registers. */ | |
912 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
913 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
914 | { | |
915 | rtx addr; | |
916 | ||
917 | if (reg) | |
918 | addr = reg; | |
919 | else | |
920 | { | |
921 | /* If we aren't using `a0', use an SP offset. */ | |
922 | if (xsize) | |
923 | { | |
924 | addr = gen_rtx_PLUS (SImode, | |
925 | stack_pointer_rtx, | |
926 | GEN_INT (xsize)); | |
927 | } | |
928 | else | |
929 | addr = stack_pointer_rtx; | |
930 | ||
931 | xsize += 4; | |
932 | } | |
933 | ||
934 | insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr), | |
935 | gen_rtx_REG (SImode, i))); | |
936 | ||
937 | RTX_FRAME_RELATED_P (insn) = 1; | |
938 | } | |
939 | } | |
940 | ||
777fbf09 | 941 | /* Now put the frame pointer into the frame pointer register. */ |
11bb1f11 | 942 | if (frame_pointer_needed) |
6e86170d | 943 | emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); |
11bb1f11 | 944 | |
777fbf09 | 945 | /* Allocate stack for this frame. */ |
11bb1f11 JL |
946 | if (size) |
947 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
948 | stack_pointer_rtx, | |
949 | GEN_INT (-size))); | |
d1776069 AO |
950 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
951 | { | |
952 | rtx insn = get_last_insn (); | |
953 | rtx last = emit_insn (gen_GOTaddr2picreg ()); | |
954 | ||
955 | /* Mark these insns as possibly dead. Sometimes, flow2 may | |
956 | delete all uses of the PIC register. In this case, let it | |
957 | delete the initialization too. */ | |
958 | do | |
959 | { | |
960 | insn = NEXT_INSN (insn); | |
961 | ||
962 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
963 | const0_rtx, | |
964 | REG_NOTES (insn)); | |
965 | } | |
966 | while (insn != last); | |
967 | } | |
11bb1f11 JL |
968 | } |
969 | ||
970 | void | |
f1777882 | 971 | expand_epilogue (void) |
11bb1f11 | 972 | { |
036182e7 | 973 | HOST_WIDE_INT size; |
3dbc43d1 | 974 | |
3dbc43d1 | 975 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
976 | size = get_frame_size () + current_function_outgoing_args_size; |
977 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 978 | |
18e9d2f9 AO |
979 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
980 | { | |
981 | int num_regs_to_save = fp_regs_to_save (), i; | |
982 | rtx reg = 0; | |
983 | ||
984 | /* We have several options to restore FP registers. We could | |
985 | load them from SP offsets, but, if there are enough FP | |
986 | registers to restore, we win if we use a post-increment | |
987 | addressing mode. */ | |
988 | ||
989 | /* If we have a frame pointer, it's the best option, because we | |
990 | already know it has the value we want. */ | |
991 | if (frame_pointer_needed) | |
992 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
993 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
994 | it's never used for return values. But only do so if it's | |
995 | smaller than using SP offsets. */ | |
996 | else | |
997 | { | |
998 | enum { restore_sp_post_adjust, | |
999 | restore_sp_pre_adjust, | |
1000 | restore_sp_partial_adjust, | |
1001 | restore_a1 } strategy; | |
1002 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
1003 | ||
1004 | /* Consider using sp offsets before adjusting sp. */ | |
1005 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1006 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
1007 | /* If size is too large, we'll have to adjust SP with an | |
1008 | add. */ | |
1009 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1010 | { | |
1011 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
1012 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
1013 | } | |
1014 | /* If we don't have to restore any non-FP registers, | |
1015 | we'll be able to save one byte by using rets. */ | |
1016 | if (! REG_SAVE_BYTES) | |
1017 | this_strategy_size--; | |
1018 | ||
1019 | if (this_strategy_size < strategy_size) | |
1020 | { | |
1021 | strategy = restore_sp_post_adjust; | |
1022 | strategy_size = this_strategy_size; | |
1023 | } | |
1024 | ||
1025 | /* Consider using sp offsets after adjusting sp. */ | |
1026 | /* Insn: add size, sp. */ | |
1027 | this_strategy_size = SIZE_ADD_SP (size); | |
1028 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1029 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
1030 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1031 | save area, so, no savings. */ |
18e9d2f9 AO |
1032 | |
1033 | if (this_strategy_size < strategy_size) | |
1034 | { | |
1035 | strategy = restore_sp_pre_adjust; | |
1036 | strategy_size = this_strategy_size; | |
1037 | } | |
1038 | ||
1039 | /* Consider using sp offsets after partially adjusting sp. | |
1040 | When size is close to 32Kb, we may be able to adjust SP | |
1041 | with an imm16 add instruction while still using fmov | |
1042 | (d8,sp). */ | |
1043 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1044 | { | |
1045 | /* Insn: add size + 4 * num_regs_to_save | |
1046 | + REG_SAVE_BYTES - 252,sp. */ | |
1047 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save | |
1048 | + REG_SAVE_BYTES - 252); | |
1049 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ | |
1050 | this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES | |
1051 | - 4 * num_regs_to_save, | |
1052 | num_regs_to_save); | |
1053 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1054 | save area, so, no savings. */ |
18e9d2f9 AO |
1055 | |
1056 | if (this_strategy_size < strategy_size) | |
1057 | { | |
1058 | strategy = restore_sp_partial_adjust; | |
1059 | strategy_size = this_strategy_size; | |
1060 | } | |
1061 | } | |
1062 | ||
1063 | /* Consider using a1 in post-increment mode, as long as the | |
1064 | user hasn't changed the calling conventions of a1. */ | |
1065 | if (call_used_regs[FIRST_ADDRESS_REGNUM+1] | |
1066 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) | |
1067 | { | |
1068 | /* Insn: mov sp,a1. */ | |
1069 | this_strategy_size = 1; | |
1070 | if (size) | |
1071 | { | |
1072 | /* Insn: add size,a1. */ | |
1073 | this_strategy_size += SIZE_ADD_AX (size); | |
1074 | } | |
1075 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1076 | this_strategy_size += 3 * num_regs_to_save; | |
1077 | /* If size is large enough, we may be able to save a | |
1078 | couple of bytes. */ | |
1079 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1080 | { | |
1081 | /* Insn: mov a1,sp. */ | |
1082 | this_strategy_size += 2; | |
1083 | } | |
1084 | /* If we don't have to restore any non-FP registers, | |
1085 | we'll be able to save one byte by using rets. */ | |
1086 | if (! REG_SAVE_BYTES) | |
1087 | this_strategy_size--; | |
1088 | ||
1089 | if (this_strategy_size < strategy_size) | |
1090 | { | |
1091 | strategy = restore_a1; | |
1092 | strategy_size = this_strategy_size; | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | switch (strategy) | |
1097 | { | |
1098 | case restore_sp_post_adjust: | |
1099 | break; | |
1100 | ||
1101 | case restore_sp_pre_adjust: | |
1102 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1103 | stack_pointer_rtx, | |
1104 | GEN_INT (size))); | |
1105 | size = 0; | |
1106 | break; | |
1107 | ||
1108 | case restore_sp_partial_adjust: | |
1109 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1110 | stack_pointer_rtx, | |
1111 | GEN_INT (size + 4 * num_regs_to_save | |
1112 | + REG_SAVE_BYTES - 252))); | |
1113 | size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save; | |
1114 | break; | |
1115 | ||
1116 | case restore_a1: | |
1117 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1118 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1119 | if (size) | |
1120 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1121 | break; | |
1122 | ||
1123 | default: | |
1124 | abort (); | |
1125 | } | |
1126 | } | |
1127 | ||
1128 | /* Adjust the selected register, if any, for post-increment. */ | |
1129 | if (reg) | |
1130 | reg = gen_rtx_POST_INC (SImode, reg); | |
1131 | ||
1132 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
1133 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
1134 | { | |
1135 | rtx addr; | |
1136 | ||
1137 | if (reg) | |
1138 | addr = reg; | |
1139 | else if (size) | |
1140 | { | |
1141 | /* If we aren't using a post-increment register, use an | |
8596d0a1 | 1142 | SP offset. */ |
18e9d2f9 AO |
1143 | addr = gen_rtx_PLUS (SImode, |
1144 | stack_pointer_rtx, | |
1145 | GEN_INT (size)); | |
1146 | } | |
1147 | else | |
1148 | addr = stack_pointer_rtx; | |
1149 | ||
1150 | size += 4; | |
1151 | ||
1152 | emit_insn (gen_movsi (gen_rtx_REG (SImode, i), | |
1153 | gen_rtx_MEM (SImode, addr))); | |
1154 | } | |
1155 | ||
1156 | /* If we were using the restore_a1 strategy and the number of | |
1157 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1158 | to `sp', to avoid having to use `add' to adjust it. */ | |
1159 | if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255) | |
1160 | { | |
1161 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1162 | size = 0; | |
1163 | } | |
1164 | } | |
1165 | ||
5d29a95f JL |
1166 | /* Maybe cut back the stack, except for the register save area. |
1167 | ||
1168 | If the frame pointer exists, then use the frame pointer to | |
1169 | cut back the stack. | |
1170 | ||
1171 | If the stack size + register save area is more than 255 bytes, | |
1172 | then the stack must be cut back here since the size + register | |
1173 | save size is too big for a ret/retf instruction. | |
1174 | ||
1175 | Else leave it alone, it will be cut back as part of the | |
1176 | ret/retf instruction, or there wasn't any stack to begin with. | |
1177 | ||
dab66575 | 1178 | Under no circumstances should the register save area be |
5d29a95f JL |
1179 | deallocated here, that would leave a window where an interrupt |
1180 | could occur and trash the register save area. */ | |
11bb1f11 JL |
1181 | if (frame_pointer_needed) |
1182 | { | |
11bb1f11 | 1183 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
4246e0c5 JL |
1184 | size = 0; |
1185 | } | |
ed6089d6 | 1186 | else if (size + REG_SAVE_BYTES > 255) |
4246e0c5 JL |
1187 | { |
1188 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1189 | stack_pointer_rtx, | |
1190 | GEN_INT (size))); | |
1191 | size = 0; | |
11bb1f11 | 1192 | } |
11bb1f11 | 1193 | |
ed6089d6 AO |
1194 | /* Adjust the stack and restore callee-saved registers, if any. */ |
1195 | if (size || regs_ever_live[2] || regs_ever_live[3] | |
777fbf09 | 1196 | || regs_ever_live[6] || regs_ever_live[7] |
705ac34f JL |
1197 | || regs_ever_live[14] || regs_ever_live[15] |
1198 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 | 1199 | || frame_pointer_needed) |
ed6089d6 AO |
1200 | emit_jump_insn (gen_return_internal_regs |
1201 | (GEN_INT (size + REG_SAVE_BYTES))); | |
777fbf09 | 1202 | else |
ed6089d6 | 1203 | emit_jump_insn (gen_return_internal ()); |
11bb1f11 JL |
1204 | } |
1205 | ||
1206 | /* Update the condition code from the insn. */ | |
1207 | ||
1208 | void | |
f1777882 | 1209 | notice_update_cc (rtx body, rtx insn) |
11bb1f11 | 1210 | { |
11bb1f11 JL |
1211 | switch (get_attr_cc (insn)) |
1212 | { | |
1213 | case CC_NONE: | |
1214 | /* Insn does not affect CC at all. */ | |
1215 | break; | |
1216 | ||
1217 | case CC_NONE_0HIT: | |
1218 | /* Insn does not change CC, but the 0'th operand has been changed. */ | |
1219 | if (cc_status.value1 != 0 | |
1ccbefce | 1220 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
11bb1f11 JL |
1221 | cc_status.value1 = 0; |
1222 | break; | |
1223 | ||
d116300b | 1224 | case CC_SET_ZN: |
1ccbefce | 1225 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
d116300b | 1226 | V,C are unusable. */ |
11bb1f11 | 1227 | CC_STATUS_INIT; |
d116300b | 1228 | cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; |
1ccbefce | 1229 | cc_status.value1 = recog_data.operand[0]; |
11bb1f11 JL |
1230 | break; |
1231 | ||
d116300b | 1232 | case CC_SET_ZNV: |
1ccbefce | 1233 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
d116300b | 1234 | C is unusable. */ |
82c6faa8 | 1235 | CC_STATUS_INIT; |
d116300b | 1236 | cc_status.flags |= CC_NO_CARRY; |
1ccbefce | 1237 | cc_status.value1 = recog_data.operand[0]; |
82c6faa8 JL |
1238 | break; |
1239 | ||
11bb1f11 JL |
1240 | case CC_COMPARE: |
1241 | /* The insn is a compare instruction. */ | |
1242 | CC_STATUS_INIT; | |
1243 | cc_status.value1 = SET_SRC (body); | |
18e9d2f9 AO |
1244 | if (GET_CODE (cc_status.value1) == COMPARE |
1245 | && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode) | |
1246 | cc_status.mdep.fpCC = 1; | |
11bb1f11 JL |
1247 | break; |
1248 | ||
1249 | case CC_CLOBBER: | |
1250 | /* Insn doesn't leave CC in a usable state. */ | |
1251 | CC_STATUS_INIT; | |
1252 | break; | |
82c6faa8 JL |
1253 | |
1254 | default: | |
1255 | abort (); | |
11bb1f11 | 1256 | } |
11bb1f11 JL |
1257 | } |
1258 | ||
05713b80 | 1259 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
f6cd7c62 RS |
1260 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1261 | parallel. If OP is a multiple store, return a mask indicating which | |
1262 | registers it saves. Return 0 otherwise. */ | |
1263 | ||
1264 | int | |
f1777882 | 1265 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
f6cd7c62 RS |
1266 | { |
1267 | int count; | |
1268 | int mask; | |
1269 | int i; | |
1270 | unsigned int last; | |
1271 | rtx elt; | |
1272 | ||
1273 | count = XVECLEN (op, 0); | |
1274 | if (count < 2) | |
1275 | return 0; | |
1276 | ||
1277 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1278 | elt = XVECEXP (op, 0, 0); | |
1279 | if (GET_CODE (elt) != SET | |
1280 | || GET_CODE (SET_DEST (elt)) != REG | |
1281 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM | |
1282 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1283 | return 0; | |
1284 | ||
1285 | /* Check that A is the stack pointer and B is the expected stack size. | |
1286 | For OP to match, each subsequent instruction should push a word onto | |
1287 | the stack. We therefore expect the first instruction to create | |
8596d0a1 | 1288 | COUNT-1 stack slots. */ |
f6cd7c62 RS |
1289 | elt = SET_SRC (elt); |
1290 | if (GET_CODE (XEXP (elt, 0)) != REG | |
1291 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1292 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1293 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) | |
1294 | return 0; | |
1295 | ||
1296 | /* Now go through the rest of the vector elements. They must be | |
1297 | ordered so that the first instruction stores the highest-numbered | |
1298 | register to the highest stack slot and that subsequent instructions | |
1299 | store a lower-numbered register to the slot below. | |
1300 | ||
1301 | LAST keeps track of the smallest-numbered register stored so far. | |
8596d0a1 | 1302 | MASK is the set of stored registers. */ |
18e9d2f9 | 1303 | last = LAST_EXTENDED_REGNUM + 1; |
f6cd7c62 RS |
1304 | mask = 0; |
1305 | for (i = 1; i < count; i++) | |
1306 | { | |
8596d0a1 | 1307 | /* Check that element i is a (set (mem M) R) and that R is valid. */ |
f6cd7c62 RS |
1308 | elt = XVECEXP (op, 0, i); |
1309 | if (GET_CODE (elt) != SET | |
1310 | || GET_CODE (SET_DEST (elt)) != MEM | |
1311 | || GET_CODE (SET_SRC (elt)) != REG | |
1312 | || REGNO (SET_SRC (elt)) >= last) | |
1313 | return 0; | |
1314 | ||
1315 | /* R was OK, so provisionally add it to MASK. We return 0 in any | |
8596d0a1 | 1316 | case if the rest of the instruction has a flaw. */ |
f6cd7c62 RS |
1317 | last = REGNO (SET_SRC (elt)); |
1318 | mask |= (1 << last); | |
1319 | ||
1320 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1321 | elt = XEXP (SET_DEST (elt), 0); | |
1322 | if (GET_CODE (elt) != PLUS | |
1323 | || GET_CODE (XEXP (elt, 0)) != REG | |
1324 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1325 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1326 | || INTVAL (XEXP (elt, 1)) != -i * 4) | |
1327 | return 0; | |
1328 | } | |
1329 | ||
8596d0a1 | 1330 | /* All or none of the callee-saved extended registers must be in the set. */ |
f6cd7c62 RS |
1331 | if ((mask & 0x3c000) != 0 |
1332 | && (mask & 0x3c000) != 0x3c000) | |
1333 | return 0; | |
1334 | ||
1335 | return mask; | |
1336 | } | |
1337 | ||
11bb1f11 | 1338 | /* What (if any) secondary registers are needed to move IN with mode |
8493cfcb | 1339 | MODE into a register in register class CLASS. |
11bb1f11 JL |
1340 | |
1341 | We might be able to simplify this. */ | |
1342 | enum reg_class | |
f1777882 | 1343 | secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in) |
11bb1f11 | 1344 | { |
11bb1f11 JL |
1345 | /* Memory loads less than a full word wide can't have an |
1346 | address or stack pointer destination. They must use | |
1347 | a data register as an intermediate register. */ | |
15c09738 AH |
1348 | if ((GET_CODE (in) == MEM |
1349 | || (GET_CODE (in) == REG | |
1350 | && REGNO (in) >= FIRST_PSEUDO_REGISTER) | |
1351 | || (GET_CODE (in) == SUBREG | |
1352 | && GET_CODE (SUBREG_REG (in)) == REG | |
1353 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)) | |
11bb1f11 | 1354 | && (mode == QImode || mode == HImode) |
15c09738 | 1355 | && (class == ADDRESS_REGS || class == SP_REGS |
842a0788 | 1356 | || class == SP_OR_ADDRESS_REGS)) |
4d1a91c2 | 1357 | { |
705ac34f JL |
1358 | if (TARGET_AM33) |
1359 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
1360 | return DATA_REGS; |
1361 | } | |
11bb1f11 JL |
1362 | |
1363 | /* We can't directly load sp + const_int into a data register; | |
1364 | we must use an address register as an intermediate. */ | |
777fbf09 JL |
1365 | if (class != SP_REGS |
1366 | && class != ADDRESS_REGS | |
1367 | && class != SP_OR_ADDRESS_REGS | |
705ac34f JL |
1368 | && class != SP_OR_EXTENDED_REGS |
1369 | && class != ADDRESS_OR_EXTENDED_REGS | |
1370 | && class != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
11bb1f11 JL |
1371 | && (in == stack_pointer_rtx |
1372 | || (GET_CODE (in) == PLUS | |
777fbf09 JL |
1373 | && (XEXP (in, 0) == stack_pointer_rtx |
1374 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
11bb1f11 JL |
1375 | return ADDRESS_REGS; |
1376 | ||
4c742813 JL |
1377 | if (GET_CODE (in) == PLUS |
1378 | && (XEXP (in, 0) == stack_pointer_rtx | |
1379 | || XEXP (in, 1) == stack_pointer_rtx)) | |
4d1a91c2 | 1380 | { |
705ac34f JL |
1381 | if (TARGET_AM33) |
1382 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
1383 | return DATA_REGS; |
1384 | } | |
4c742813 | 1385 | |
18e9d2f9 AO |
1386 | if (TARGET_AM33_2 && class == FP_REGS |
1387 | && GET_CODE (in) == MEM && ! OK_FOR_Q (in)) | |
1388 | { | |
1389 | if (TARGET_AM33) | |
1390 | return DATA_OR_EXTENDED_REGS; | |
1391 | return DATA_REGS; | |
1392 | } | |
1393 | ||
777fbf09 JL |
1394 | /* Otherwise assume no secondary reloads are needed. */ |
1395 | return NO_REGS; | |
1396 | } | |
1397 | ||
1398 | int | |
f1777882 | 1399 | initial_offset (int from, int to) |
777fbf09 | 1400 | { |
3dbc43d1 JL |
1401 | /* The difference between the argument pointer and the frame pointer |
1402 | is the size of the callee register save area. */ | |
777fbf09 | 1403 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
11bb1f11 | 1404 | { |
777fbf09 JL |
1405 | if (regs_ever_live[2] || regs_ever_live[3] |
1406 | || regs_ever_live[6] || regs_ever_live[7] | |
705ac34f JL |
1407 | || regs_ever_live[14] || regs_ever_live[15] |
1408 | || regs_ever_live[16] || regs_ever_live[17] | |
18e9d2f9 | 1409 | || fp_regs_to_save () |
777fbf09 | 1410 | || frame_pointer_needed) |
18e9d2f9 AO |
1411 | return REG_SAVE_BYTES |
1412 | + 4 * fp_regs_to_save (); | |
777fbf09 | 1413 | else |
22ef4e9b | 1414 | return 0; |
11bb1f11 JL |
1415 | } |
1416 | ||
3dbc43d1 JL |
1417 | /* The difference between the argument pointer and the stack pointer is |
1418 | the sum of the size of this function's frame, the callee register save | |
1419 | area, and the fixed stack space needed for function calls (if any). */ | |
777fbf09 JL |
1420 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
1421 | { | |
1422 | if (regs_ever_live[2] || regs_ever_live[3] | |
1423 | || regs_ever_live[6] || regs_ever_live[7] | |
705ac34f JL |
1424 | || regs_ever_live[14] || regs_ever_live[15] |
1425 | || regs_ever_live[16] || regs_ever_live[17] | |
18e9d2f9 | 1426 | || fp_regs_to_save () |
777fbf09 | 1427 | || frame_pointer_needed) |
4d1a91c2 | 1428 | return (get_frame_size () + REG_SAVE_BYTES |
18e9d2f9 | 1429 | + 4 * fp_regs_to_save () |
460f4b9d JL |
1430 | + (current_function_outgoing_args_size |
1431 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 | 1432 | else |
460f4b9d JL |
1433 | return (get_frame_size () |
1434 | + (current_function_outgoing_args_size | |
1435 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 | 1436 | } |
11bb1f11 | 1437 | |
3dbc43d1 JL |
1438 | /* The difference between the frame pointer and stack pointer is the sum |
1439 | of the size of this function's frame and the fixed stack space needed | |
1440 | for function calls (if any). */ | |
777fbf09 | 1441 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
460f4b9d JL |
1442 | return (get_frame_size () |
1443 | + (current_function_outgoing_args_size | |
1444 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 JL |
1445 | |
1446 | abort (); | |
11bb1f11 | 1447 | } |
22ef4e9b | 1448 | |
bd5bd7ac KH |
1449 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
1450 | ||
9024ea92 KH |
1451 | static bool |
1452 | mn10300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
1453 | { | |
1454 | /* Return values > 8 bytes in length in memory. */ | |
1455 | return int_size_in_bytes (type) > 8 || TYPE_MODE (type) == BLKmode; | |
1456 | } | |
1457 | ||
22ef4e9b JL |
1458 | /* Flush the argument registers to the stack for a stdarg function; |
1459 | return the new argument pointer. */ | |
9024ea92 | 1460 | static rtx |
f1777882 | 1461 | mn10300_builtin_saveregs (void) |
22ef4e9b | 1462 | { |
fc2acc87 | 1463 | rtx offset, mem; |
22ef4e9b JL |
1464 | tree fntype = TREE_TYPE (current_function_decl); |
1465 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
1466 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
1467 | != void_type_node))) | |
1468 | ? UNITS_PER_WORD : 0); | |
fc2acc87 | 1469 | int set = get_varargs_alias_set (); |
22ef4e9b JL |
1470 | |
1471 | if (argadj) | |
1472 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
1473 | else | |
1474 | offset = current_function_arg_offset_rtx; | |
1475 | ||
fc2acc87 | 1476 | mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer); |
ba4828e0 | 1477 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1478 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1479 | ||
1480 | mem = gen_rtx_MEM (SImode, | |
1481 | plus_constant (current_function_internal_arg_pointer, 4)); | |
ba4828e0 | 1482 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1483 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1484 | ||
22ef4e9b JL |
1485 | return copy_to_reg (expand_binop (Pmode, add_optab, |
1486 | current_function_internal_arg_pointer, | |
1487 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
1488 | } | |
1489 | ||
fc2acc87 | 1490 | void |
f1777882 | 1491 | mn10300_va_start (tree valist, rtx nextarg) |
fc2acc87 | 1492 | { |
6c535c69 | 1493 | nextarg = expand_builtin_saveregs (); |
e5faf155 | 1494 | std_expand_builtin_va_start (valist, nextarg); |
fc2acc87 RH |
1495 | } |
1496 | ||
8cd5a4e0 RH |
1497 | /* Return true when a parameter should be passed by reference. */ |
1498 | ||
1499 | static bool | |
1500 | mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
1501 | enum machine_mode mode, tree type, | |
1502 | bool named ATTRIBUTE_UNUSED) | |
1503 | { | |
1504 | unsigned HOST_WIDE_INT size; | |
1505 | ||
1506 | if (type) | |
1507 | size = int_size_in_bytes (type); | |
1508 | else | |
1509 | size = GET_MODE_SIZE (mode); | |
1510 | ||
1511 | return size > 8; | |
1512 | } | |
1513 | ||
22ef4e9b JL |
1514 | /* Return an RTX to represent where a value with mode MODE will be returned |
1515 | from a function. If the result is 0, the argument is pushed. */ | |
1516 | ||
1517 | rtx | |
f1777882 KH |
1518 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
1519 | tree type, int named ATTRIBUTE_UNUSED) | |
22ef4e9b JL |
1520 | { |
1521 | rtx result = 0; | |
1522 | int size, align; | |
1523 | ||
1524 | /* We only support using 2 data registers as argument registers. */ | |
1525 | int nregs = 2; | |
1526 | ||
1527 | /* Figure out the size of the object to be passed. */ | |
1528 | if (mode == BLKmode) | |
1529 | size = int_size_in_bytes (type); | |
1530 | else | |
1531 | size = GET_MODE_SIZE (mode); | |
1532 | ||
1533 | /* Figure out the alignment of the object to be passed. */ | |
1534 | align = size; | |
1535 | ||
1536 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1537 | ||
1538 | /* Don't pass this arg via a register if all the argument registers | |
1539 | are used up. */ | |
1540 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1541 | return 0; | |
1542 | ||
1543 | /* Don't pass this arg via a register if it would be split between | |
1544 | registers and memory. */ | |
1545 | if (type == NULL_TREE | |
1546 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1547 | return 0; | |
1548 | ||
1549 | switch (cum->nbytes / UNITS_PER_WORD) | |
1550 | { | |
1551 | case 0: | |
c5c76735 | 1552 | result = gen_rtx_REG (mode, 0); |
22ef4e9b JL |
1553 | break; |
1554 | case 1: | |
c5c76735 | 1555 | result = gen_rtx_REG (mode, 1); |
22ef4e9b JL |
1556 | break; |
1557 | default: | |
1558 | result = 0; | |
1559 | } | |
1560 | ||
1561 | return result; | |
1562 | } | |
1563 | ||
78a52f11 RH |
1564 | /* Return the number of bytes of registers to use for an argument passed |
1565 | partially in registers and partially in memory. */ | |
22ef4e9b | 1566 | |
78a52f11 RH |
1567 | static int |
1568 | mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1569 | tree type, bool named ATTRIBUTE_UNUSED) | |
22ef4e9b JL |
1570 | { |
1571 | int size, align; | |
1572 | ||
1573 | /* We only support using 2 data registers as argument registers. */ | |
1574 | int nregs = 2; | |
1575 | ||
1576 | /* Figure out the size of the object to be passed. */ | |
1577 | if (mode == BLKmode) | |
1578 | size = int_size_in_bytes (type); | |
1579 | else | |
1580 | size = GET_MODE_SIZE (mode); | |
1581 | ||
1582 | /* Figure out the alignment of the object to be passed. */ | |
1583 | align = size; | |
1584 | ||
1585 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1586 | ||
1587 | /* Don't pass this arg via a register if all the argument registers | |
1588 | are used up. */ | |
1589 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1590 | return 0; | |
1591 | ||
1592 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1593 | return 0; | |
1594 | ||
1595 | /* Don't pass this arg via a register if it would be split between | |
1596 | registers and memory. */ | |
1597 | if (type == NULL_TREE | |
1598 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1599 | return 0; | |
1600 | ||
78a52f11 | 1601 | return nregs * UNITS_PER_WORD - cum->nbytes; |
22ef4e9b JL |
1602 | } |
1603 | ||
1604 | /* Output a tst insn. */ | |
1943c2c1 | 1605 | const char * |
f1777882 | 1606 | output_tst (rtx operand, rtx insn) |
22ef4e9b | 1607 | { |
22ef4e9b JL |
1608 | rtx temp; |
1609 | int past_call = 0; | |
1610 | ||
1611 | /* We can save a byte if we can find a register which has the value | |
1612 | zero in it. */ | |
1613 | temp = PREV_INSN (insn); | |
74452ac3 | 1614 | while (optimize && temp) |
22ef4e9b JL |
1615 | { |
1616 | rtx set; | |
1617 | ||
1618 | /* We allow the search to go through call insns. We record | |
1619 | the fact that we've past a CALL_INSN and reject matches which | |
1620 | use call clobbered registers. */ | |
1621 | if (GET_CODE (temp) == CODE_LABEL | |
1622 | || GET_CODE (temp) == JUMP_INSN | |
1623 | || GET_CODE (temp) == BARRIER) | |
1624 | break; | |
1625 | ||
1626 | if (GET_CODE (temp) == CALL_INSN) | |
1627 | past_call = 1; | |
1628 | ||
1629 | if (GET_CODE (temp) == NOTE) | |
1630 | { | |
1631 | temp = PREV_INSN (temp); | |
1632 | continue; | |
1633 | } | |
1634 | ||
8596d0a1 | 1635 | /* It must be an insn, see if it is a simple set. */ |
22ef4e9b JL |
1636 | set = single_set (temp); |
1637 | if (!set) | |
1638 | { | |
1639 | temp = PREV_INSN (temp); | |
1640 | continue; | |
1641 | } | |
1642 | ||
1643 | /* Are we setting a data register to zero (this does not win for | |
1644 | address registers)? | |
1645 | ||
1646 | If it's a call clobbered register, have we past a call? | |
1647 | ||
1648 | Make sure the register we find isn't the same as ourself; | |
4d1a91c2 JL |
1649 | the mn10300 can't encode that. |
1650 | ||
1651 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1652 | so the code to detect calls here isn't doing anything useful. */ | |
22ef4e9b JL |
1653 | if (REG_P (SET_DEST (set)) |
1654 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1655 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
74452ac3 JL |
1656 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1657 | == REGNO_REG_CLASS (REGNO (operand))) | |
705ac34f JL |
1658 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1659 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
1660 | && (!past_call | |
1661 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1662 | { | |
1663 | rtx xoperands[2]; | |
1664 | xoperands[0] = operand; | |
1665 | xoperands[1] = SET_DEST (set); | |
1666 | ||
1667 | output_asm_insn ("cmp %1,%0", xoperands); | |
1668 | return ""; | |
1669 | } | |
1670 | ||
1671 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1672 | && REG_P (SET_DEST (set)) | |
1673 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1674 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1675 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1676 | != REGNO_REG_CLASS (REGNO (operand))) | |
1677 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
22ef4e9b JL |
1678 | && REGNO (SET_DEST (set)) != REGNO (operand) |
1679 | && (!past_call | |
1680 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1681 | { | |
1682 | rtx xoperands[2]; | |
1683 | xoperands[0] = operand; | |
1684 | xoperands[1] = SET_DEST (set); | |
1685 | ||
1686 | output_asm_insn ("cmp %1,%0", xoperands); | |
1687 | return ""; | |
1688 | } | |
1689 | temp = PREV_INSN (temp); | |
1690 | } | |
1691 | return "cmp 0,%0"; | |
1692 | } | |
460f4b9d JL |
1693 | |
1694 | int | |
f1777882 | 1695 | impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
460f4b9d | 1696 | { |
460f4b9d JL |
1697 | if (GET_CODE (op) != PLUS) |
1698 | return 0; | |
1699 | ||
4c742813 JL |
1700 | if (XEXP (op, 0) == stack_pointer_rtx |
1701 | || XEXP (op, 1) == stack_pointer_rtx) | |
460f4b9d JL |
1702 | return 1; |
1703 | ||
460f4b9d JL |
1704 | return 0; |
1705 | } | |
e9ad4573 | 1706 | |
f8912297 JL |
1707 | /* Similarly, but when using a zero_extract pattern for a btst where |
1708 | the source operand might end up in memory. */ | |
1709 | int | |
f1777882 | 1710 | mask_ok_for_mem_btst (int len, int bit) |
f8912297 | 1711 | { |
4977bab6 | 1712 | unsigned int mask = 0; |
f8912297 JL |
1713 | |
1714 | while (len > 0) | |
1715 | { | |
1716 | mask |= (1 << bit); | |
1717 | bit++; | |
1718 | len--; | |
1719 | } | |
1720 | ||
1721 | /* MASK must bit into an 8bit value. */ | |
1722 | return (((mask & 0xff) == mask) | |
1723 | || ((mask & 0xff00) == mask) | |
1724 | || ((mask & 0xff0000) == mask) | |
1725 | || ((mask & 0xff000000) == mask)); | |
1726 | } | |
1727 | ||
e9ad4573 JL |
1728 | /* Return 1 if X contains a symbolic expression. We know these |
1729 | expressions will have one of a few well defined forms, so | |
1730 | we need only check those forms. */ | |
1731 | int | |
f1777882 | 1732 | symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e9ad4573 JL |
1733 | { |
1734 | switch (GET_CODE (op)) | |
1735 | { | |
1736 | case SYMBOL_REF: | |
1737 | case LABEL_REF: | |
1738 | return 1; | |
1739 | case CONST: | |
1740 | op = XEXP (op, 0); | |
1741 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1742 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
1743 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
1744 | default: | |
1745 | return 0; | |
1746 | } | |
1747 | } | |
1748 | ||
1749 | /* Try machine dependent ways of modifying an illegitimate address | |
1750 | to be legitimate. If we find one, return the new valid address. | |
1751 | This macro is used in only one place: `memory_address' in explow.c. | |
1752 | ||
1753 | OLDX is the address as it was before break_out_memory_refs was called. | |
1754 | In some cases it is useful to look at this to decide what needs to be done. | |
1755 | ||
1756 | MODE and WIN are passed so that this macro can use | |
1757 | GO_IF_LEGITIMATE_ADDRESS. | |
1758 | ||
1759 | Normally it is always safe for this macro to do nothing. It exists to | |
1760 | recognize opportunities to optimize the output. | |
1761 | ||
1762 | But on a few ports with segmented architectures and indexed addressing | |
1763 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
1764 | rtx | |
f1777882 KH |
1765 | legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1766 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
e9ad4573 | 1767 | { |
d1776069 AO |
1768 | if (flag_pic && ! legitimate_pic_operand_p (x)) |
1769 | x = legitimize_pic_address (oldx, NULL_RTX); | |
1770 | ||
e9ad4573 JL |
1771 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1772 | special handling to avoid creating an indexed memory address | |
1773 | with x-100000 as the base. */ | |
1774 | if (GET_CODE (x) == PLUS | |
1775 | && symbolic_operand (XEXP (x, 1), VOIDmode)) | |
1776 | { | |
1777 | /* Ugly. We modify things here so that the address offset specified | |
1778 | by the index expression is computed first, then added to x to form | |
1779 | the entire address. */ | |
1780 | ||
69bc71fa | 1781 | rtx regx1, regy1, regy2, y; |
e9ad4573 JL |
1782 | |
1783 | /* Strip off any CONST. */ | |
1784 | y = XEXP (x, 1); | |
1785 | if (GET_CODE (y) == CONST) | |
1786 | y = XEXP (y, 0); | |
1787 | ||
bf4219f0 JL |
1788 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1789 | { | |
1790 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1791 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1792 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1793 | regx1 = force_reg (Pmode, | |
1c563bed | 1794 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, regy2)); |
c5c76735 | 1795 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
bf4219f0 | 1796 | } |
e9ad4573 | 1797 | } |
371036e0 | 1798 | return x; |
e9ad4573 | 1799 | } |
460ad325 | 1800 | |
d1776069 | 1801 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
8596d0a1 | 1802 | @GOTOFF in `reg'. */ |
d1776069 | 1803 | rtx |
f1777882 | 1804 | legitimize_pic_address (rtx orig, rtx reg) |
d1776069 AO |
1805 | { |
1806 | if (GET_CODE (orig) == LABEL_REF | |
1807 | || (GET_CODE (orig) == SYMBOL_REF | |
1808 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1809 | || ! MN10300_GLOBAL_P (orig)))) | |
1810 | { | |
1811 | if (reg == 0) | |
1812 | reg = gen_reg_rtx (Pmode); | |
1813 | ||
1814 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
1815 | return reg; | |
1816 | } | |
1817 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1818 | { | |
1819 | if (reg == 0) | |
1820 | reg = gen_reg_rtx (Pmode); | |
1821 | ||
1822 | emit_insn (gen_symGOT2reg (reg, orig)); | |
1823 | return reg; | |
1824 | } | |
1825 | return orig; | |
1826 | } | |
1827 | ||
1828 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
4375e090 | 1829 | isn't protected by a PIC unspec; nonzero otherwise. */ |
d1776069 | 1830 | int |
f1777882 | 1831 | legitimate_pic_operand_p (rtx x) |
d1776069 AO |
1832 | { |
1833 | register const char *fmt; | |
1834 | register int i; | |
1835 | ||
1836 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1837 | return 0; | |
1838 | ||
1839 | if (GET_CODE (x) == UNSPEC | |
1840 | && (XINT (x, 1) == UNSPEC_PIC | |
1841 | || XINT (x, 1) == UNSPEC_GOT | |
1842 | || XINT (x, 1) == UNSPEC_GOTOFF | |
1843 | || XINT (x, 1) == UNSPEC_PLT)) | |
1844 | return 1; | |
1845 | ||
d1776069 AO |
1846 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
1847 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1848 | { | |
1849 | if (fmt[i] == 'E') | |
1850 | { | |
1851 | register int j; | |
1852 | ||
1853 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1854 | if (! legitimate_pic_operand_p (XVECEXP (x, i, j))) | |
1855 | return 0; | |
1856 | } | |
1857 | else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i))) | |
1858 | return 0; | |
1859 | } | |
1860 | ||
1861 | return 1; | |
1862 | } | |
1863 | ||
e733134f AO |
1864 | /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is |
1865 | legitimate, and FALSE otherwise. */ | |
1866 | bool | |
1867 | legitimate_address_p (enum machine_mode mode, rtx x, int strict) | |
1868 | { | |
1869 | if (CONSTANT_ADDRESS_P (x) | |
1870 | && (! flag_pic || legitimate_pic_operand_p (x))) | |
1871 | return TRUE; | |
1872 | ||
1873 | if (RTX_OK_FOR_BASE_P (x, strict)) | |
1874 | return TRUE; | |
1875 | ||
1876 | if (TARGET_AM33 | |
1877 | && GET_CODE (x) == POST_INC | |
1878 | && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict) | |
1879 | && (mode == SImode || mode == SFmode || mode == HImode)) | |
1880 | return TRUE; | |
1881 | ||
1882 | if (GET_CODE (x) == PLUS) | |
1883 | { | |
1884 | rtx base = 0, index = 0; | |
1885 | ||
1886 | if (REG_P (XEXP (x, 0)) | |
1887 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict)) | |
1888 | { | |
1889 | base = XEXP (x, 0); | |
1890 | index = XEXP (x, 1); | |
1891 | } | |
1892 | ||
1893 | if (REG_P (XEXP (x, 1)) | |
1894 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict)) | |
1895 | { | |
1896 | base = XEXP (x, 1); | |
1897 | index = XEXP (x, 0); | |
1898 | } | |
1899 | ||
1900 | if (base != 0 && index != 0) | |
1901 | { | |
1902 | if (GET_CODE (index) == CONST_INT) | |
1903 | return TRUE; | |
1904 | if (GET_CODE (index) == CONST | |
5542b23d | 1905 | && GET_CODE (XEXP (index, 0)) != PLUS |
e733134f AO |
1906 | && (! flag_pic |
1907 | || legitimate_pic_operand_p (index))) | |
1908 | return TRUE; | |
1909 | } | |
1910 | } | |
1911 | ||
1912 | return FALSE; | |
1913 | } | |
1914 | ||
dcefdf67 | 1915 | static int |
f1777882 | 1916 | mn10300_address_cost_1 (rtx x, int *unsig) |
460ad325 | 1917 | { |
460ad325 AO |
1918 | switch (GET_CODE (x)) |
1919 | { | |
1920 | case REG: | |
1921 | switch (REGNO_REG_CLASS (REGNO (x))) | |
1922 | { | |
1923 | case SP_REGS: | |
1924 | *unsig = 1; | |
1925 | return 0; | |
1926 | ||
1927 | case ADDRESS_REGS: | |
1928 | return 1; | |
1929 | ||
1930 | case DATA_REGS: | |
1931 | case EXTENDED_REGS: | |
18e9d2f9 | 1932 | case FP_REGS: |
460ad325 AO |
1933 | return 3; |
1934 | ||
1935 | case NO_REGS: | |
1936 | return 5; | |
1937 | ||
1938 | default: | |
1939 | abort (); | |
1940 | } | |
1941 | ||
1942 | case PLUS: | |
1943 | case MINUS: | |
d82704fb AO |
1944 | case ASHIFT: |
1945 | case AND: | |
460ad325 | 1946 | case IOR: |
dcefdf67 RH |
1947 | return (mn10300_address_cost_1 (XEXP (x, 0), unsig) |
1948 | + mn10300_address_cost_1 (XEXP (x, 1), unsig)); | |
460ad325 AO |
1949 | |
1950 | case EXPR_LIST: | |
1951 | case SUBREG: | |
1952 | case MEM: | |
dcefdf67 | 1953 | return mn10300_address_cost (XEXP (x, 0)); |
460ad325 AO |
1954 | |
1955 | case ZERO_EXTEND: | |
1956 | *unsig = 1; | |
dcefdf67 | 1957 | return mn10300_address_cost_1 (XEXP (x, 0), unsig); |
460ad325 AO |
1958 | |
1959 | case CONST_INT: | |
1960 | if (INTVAL (x) == 0) | |
1961 | return 0; | |
1962 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
1963 | return 1; | |
1964 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
1965 | return 3; | |
1966 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
1967 | return 5; | |
1968 | return 7; | |
1969 | ||
1970 | case CONST: | |
1971 | case SYMBOL_REF: | |
d82704fb | 1972 | case LABEL_REF: |
460ad325 AO |
1973 | return 8; |
1974 | ||
460ad325 AO |
1975 | default: |
1976 | abort (); | |
1977 | ||
1978 | } | |
1979 | } | |
3c50106f | 1980 | |
dcefdf67 | 1981 | static int |
f1777882 | 1982 | mn10300_address_cost (rtx x) |
dcefdf67 RH |
1983 | { |
1984 | int s = 0; | |
1985 | return mn10300_address_cost_1 (x, &s); | |
1986 | } | |
1987 | ||
3c50106f | 1988 | static bool |
f1777882 | 1989 | mn10300_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
1990 | { |
1991 | switch (code) | |
1992 | { | |
1993 | case CONST_INT: | |
1994 | /* Zeros are extremely cheap. */ | |
1995 | if (INTVAL (x) == 0 && outer_code == SET) | |
1996 | *total = 0; | |
1997 | /* If it fits in 8 bits, then it's still relatively cheap. */ | |
1998 | else if (INT_8_BITS (INTVAL (x))) | |
1999 | *total = 1; | |
2000 | /* This is the "base" cost, includes constants where either the | |
2001 | upper or lower 16bits are all zeros. */ | |
2002 | else if (INT_16_BITS (INTVAL (x)) | |
2003 | || (INTVAL (x) & 0xffff) == 0 | |
2004 | || (INTVAL (x) & 0xffff0000) == 0) | |
2005 | *total = 2; | |
2006 | else | |
2007 | *total = 4; | |
2008 | return true; | |
2009 | ||
2010 | case CONST: | |
2011 | case LABEL_REF: | |
2012 | case SYMBOL_REF: | |
2013 | /* These are more costly than a CONST_INT, but we can relax them, | |
2014 | so they're less costly than a CONST_DOUBLE. */ | |
2015 | *total = 6; | |
2016 | return true; | |
2017 | ||
2018 | case CONST_DOUBLE: | |
2019 | /* We don't optimize CONST_DOUBLEs well nor do we relax them well, | |
2020 | so their cost is very high. */ | |
2021 | *total = 8; | |
2022 | return true; | |
2023 | ||
2024 | /* ??? This probably needs more work. */ | |
2025 | case MOD: | |
2026 | case DIV: | |
2027 | case MULT: | |
2028 | *total = 8; | |
2029 | return true; | |
2030 | ||
2031 | default: | |
2032 | return false; | |
2033 | } | |
2034 | } | |
fe7496dd AO |
2035 | |
2036 | /* Check whether a constant used to initialize a DImode or DFmode can | |
2037 | use a clr instruction. The code here must be kept in sync with | |
2038 | movdf and movdi. */ | |
2039 | ||
2040 | bool | |
f1777882 | 2041 | mn10300_wide_const_load_uses_clr (rtx operands[2]) |
fe7496dd AO |
2042 | { |
2043 | long val[2]; | |
2044 | ||
2045 | if (GET_CODE (operands[0]) != REG | |
2046 | || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS) | |
2047 | return false; | |
2048 | ||
2049 | switch (GET_CODE (operands[1])) | |
2050 | { | |
2051 | case CONST_INT: | |
2052 | { | |
2053 | rtx low, high; | |
2054 | split_double (operands[1], &low, &high); | |
2055 | val[0] = INTVAL (low); | |
2056 | val[1] = INTVAL (high); | |
2057 | } | |
2058 | break; | |
2059 | ||
2060 | case CONST_DOUBLE: | |
2061 | if (GET_MODE (operands[1]) == DFmode) | |
2062 | { | |
2063 | REAL_VALUE_TYPE rv; | |
2064 | ||
2065 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
2066 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
2067 | } | |
2068 | else if (GET_MODE (operands[1]) == VOIDmode | |
2069 | || GET_MODE (operands[1]) == DImode) | |
2070 | { | |
2071 | val[0] = CONST_DOUBLE_LOW (operands[1]); | |
2072 | val[1] = CONST_DOUBLE_HIGH (operands[1]); | |
2073 | } | |
2074 | break; | |
2075 | ||
2076 | default: | |
2077 | return false; | |
2078 | } | |
2079 | ||
2080 | return val[0] == 0 || val[1] == 0; | |
2081 | } | |
d1776069 AO |
2082 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2083 | may access it using GOTOFF instead of GOT. */ | |
2084 | ||
2085 | static void | |
3bc5e4ef | 2086 | mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED) |
d1776069 AO |
2087 | { |
2088 | rtx symbol; | |
2089 | ||
2090 | if (GET_CODE (rtl) != MEM) | |
2091 | return; | |
2092 | symbol = XEXP (rtl, 0); | |
2093 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2094 | return; | |
2095 | ||
2096 | if (flag_pic) | |
2097 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2098 | } |