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Commit | Line | Data |
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11bb1f11 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
6fb5fa3c | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, |
c75c517d | 3 | 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. |
11bb1f11 JL |
4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
7ec022b2 | 6 | This file is part of GCC. |
11bb1f11 | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
11bb1f11 | 9 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
11bb1f11 JL |
11 | any later version. |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
11bb1f11 JL |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
20 | <http://www.gnu.org/licenses/>. */ | |
11bb1f11 | 21 | |
11bb1f11 | 22 | #include "config.h" |
c5c76735 | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
11bb1f11 | 26 | #include "rtl.h" |
bf6bb899 | 27 | #include "tree.h" |
11bb1f11 JL |
28 | #include "regs.h" |
29 | #include "hard-reg-set.h" | |
11bb1f11 JL |
30 | #include "insn-config.h" |
31 | #include "conditions.h" | |
11bb1f11 JL |
32 | #include "output.h" |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
6528281d | 36 | #include "reload.h" |
11bb1f11 | 37 | #include "expr.h" |
e78d8e51 | 38 | #include "optabs.h" |
bf6bb899 | 39 | #include "function.h" |
11bb1f11 | 40 | #include "obstack.h" |
718f9c0f | 41 | #include "diagnostic-core.h" |
69bc71fa KG |
42 | #include "toplev.h" |
43 | #include "tm_p.h" | |
672a6f42 NB |
44 | #include "target.h" |
45 | #include "target-def.h" | |
11bb1f11 | 46 | |
d1776069 AO |
47 | /* This is used by GOTaddr2picreg to uniquely identify |
48 | UNSPEC_INT_LABELs. */ | |
49 | int mn10300_unspec_int_label_counter; | |
50 | ||
2beef00e AO |
51 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
52 | names are not prefixed by underscores, to tell whether to prefix a | |
53 | label with a plus sign or not, so that the assembler can tell | |
54 | symbol names from register names. */ | |
55 | int mn10300_protect_label; | |
56 | ||
13dd556c RS |
57 | /* The selected processor. */ |
58 | enum processor_type mn10300_processor = PROCESSOR_DEFAULT; | |
59 | ||
4d1a91c2 JL |
60 | /* The size of the callee register save area. Right now we save everything |
61 | on entry since it costs us nothing in code size. It does cost us from a | |
62 | speed standpoint, so we want to optimize this sooner or later. */ | |
6fb5fa3c DB |
63 | #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \ |
64 | + 4 * df_regs_ever_live_p (3) \ | |
65 | + 4 * df_regs_ever_live_p (6) \ | |
66 | + 4 * df_regs_ever_live_p (7) \ | |
67 | + 16 * (df_regs_ever_live_p (14) || df_regs_ever_live_p (15) \ | |
68 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17))) | |
3c50106f RH |
69 | |
70 | ||
13dd556c | 71 | static bool mn10300_handle_option (size_t, const char *, int); |
c5387660 | 72 | static void mn10300_option_override (void); |
c6c3dba9 | 73 | static bool mn10300_legitimate_address_p (enum machine_mode, rtx, bool); |
7f682641 | 74 | static int mn10300_address_cost_1 (rtx, int *); |
f40751dd JH |
75 | static int mn10300_address_cost (rtx, bool); |
76 | static bool mn10300_rtx_costs (rtx, int, int, int *, bool); | |
7f682641 | 77 | static void mn10300_file_start (void); |
586de218 | 78 | static bool mn10300_return_in_memory (const_tree, const_tree); |
9024ea92 | 79 | static rtx mn10300_builtin_saveregs (void); |
d7bd8aeb | 80 | static void mn10300_va_start (tree, rtx); |
506d7b68 | 81 | static rtx mn10300_legitimize_address (rtx, rtx, enum machine_mode); |
8cd5a4e0 | 82 | static bool mn10300_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
586de218 | 83 | const_tree, bool); |
78a52f11 RH |
84 | static int mn10300_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
85 | tree, bool); | |
e6ff3083 | 86 | static unsigned int mn10300_case_values_threshold (void); |
bdeb5f0c RH |
87 | static void mn10300_encode_section_info (tree, rtx, int); |
88 | static void mn10300_asm_trampoline_template (FILE *); | |
89 | static void mn10300_trampoline_init (rtx, tree, rtx); | |
34732b0a AS |
90 | static rtx mn10300_function_value (const_tree, const_tree, bool); |
91 | static rtx mn10300_libcall_value (enum machine_mode, const_rtx); | |
990dc016 NC |
92 | static void mn10300_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); |
93 | static bool mn10300_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT, const_tree); | |
672a6f42 NB |
94 | \f |
95 | /* Initialize the GCC target structure. */ | |
2720cc47 NC |
96 | #undef TARGET_EXCEPT_UNWIND_INFO |
97 | #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info | |
98 | ||
301d03af RS |
99 | #undef TARGET_ASM_ALIGNED_HI_OP |
100 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
4d1a91c2 | 101 | |
506d7b68 PB |
102 | #undef TARGET_LEGITIMIZE_ADDRESS |
103 | #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address | |
104 | ||
3c50106f RH |
105 | #undef TARGET_RTX_COSTS |
106 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
dcefdf67 RH |
107 | #undef TARGET_ADDRESS_COST |
108 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
3c50106f | 109 | |
1bc7c5b6 ZW |
110 | #undef TARGET_ASM_FILE_START |
111 | #define TARGET_ASM_FILE_START mn10300_file_start | |
112 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
113 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
114 | ||
13dd556c | 115 | #undef TARGET_DEFAULT_TARGET_FLAGS |
b1eb8119 | 116 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0 |
13dd556c RS |
117 | #undef TARGET_HANDLE_OPTION |
118 | #define TARGET_HANDLE_OPTION mn10300_handle_option | |
c5387660 JM |
119 | #undef TARGET_OPTION_OVERRIDE |
120 | #define TARGET_OPTION_OVERRIDE mn10300_option_override | |
13dd556c | 121 | |
d1776069 AO |
122 | #undef TARGET_ENCODE_SECTION_INFO |
123 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
124 | ||
9024ea92 | 125 | #undef TARGET_PROMOTE_PROTOTYPES |
586de218 | 126 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
9024ea92 KH |
127 | #undef TARGET_RETURN_IN_MEMORY |
128 | #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory | |
8cd5a4e0 RH |
129 | #undef TARGET_PASS_BY_REFERENCE |
130 | #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference | |
6cdd5672 RH |
131 | #undef TARGET_CALLEE_COPIES |
132 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
78a52f11 RH |
133 | #undef TARGET_ARG_PARTIAL_BYTES |
134 | #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes | |
9024ea92 KH |
135 | |
136 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
137 | #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs | |
d7bd8aeb JJ |
138 | #undef TARGET_EXPAND_BUILTIN_VA_START |
139 | #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start | |
9024ea92 | 140 | |
e6ff3083 AS |
141 | #undef TARGET_CASE_VALUES_THRESHOLD |
142 | #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold | |
143 | ||
c6c3dba9 PB |
144 | #undef TARGET_LEGITIMATE_ADDRESS_P |
145 | #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p | |
146 | ||
bdeb5f0c RH |
147 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
148 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE mn10300_asm_trampoline_template | |
149 | #undef TARGET_TRAMPOLINE_INIT | |
150 | #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init | |
151 | ||
34732b0a AS |
152 | #undef TARGET_FUNCTION_VALUE |
153 | #define TARGET_FUNCTION_VALUE mn10300_function_value | |
154 | #undef TARGET_LIBCALL_VALUE | |
155 | #define TARGET_LIBCALL_VALUE mn10300_libcall_value | |
156 | ||
990dc016 NC |
157 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
158 | #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk | |
159 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
160 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk | |
161 | ||
f6897b10 | 162 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 163 | \f |
13dd556c RS |
164 | /* Implement TARGET_HANDLE_OPTION. */ |
165 | ||
166 | static bool | |
167 | mn10300_handle_option (size_t code, | |
168 | const char *arg ATTRIBUTE_UNUSED, | |
169 | int value) | |
170 | { | |
171 | switch (code) | |
172 | { | |
173 | case OPT_mam33: | |
174 | mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300; | |
175 | return true; | |
176 | case OPT_mam33_2: | |
177 | mn10300_processor = (value | |
178 | ? PROCESSOR_AM33_2 | |
179 | : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT)); | |
180 | return true; | |
181 | default: | |
182 | return true; | |
183 | } | |
184 | } | |
185 | ||
c5387660 | 186 | /* Implement TARGET_OPTION_OVERRIDE. */ |
13dd556c | 187 | |
c5387660 JM |
188 | static void |
189 | mn10300_option_override (void) | |
13dd556c RS |
190 | { |
191 | if (TARGET_AM33) | |
192 | target_flags &= ~MASK_MULT_BUG; | |
2720cc47 NC |
193 | |
194 | /* FIXME: The combine stack adjustments pass is breaking | |
195 | cc0-setter/cc0-user relationship by inserting a jump | |
196 | instruction. This should be investigated, but for now | |
197 | just disable the pass. */ | |
198 | flag_combine_stack_adjustments = 0; | |
13dd556c RS |
199 | } |
200 | ||
1bc7c5b6 | 201 | static void |
f1777882 | 202 | mn10300_file_start (void) |
11bb1f11 | 203 | { |
1bc7c5b6 | 204 | default_file_start (); |
705ac34f | 205 | |
18e9d2f9 AO |
206 | if (TARGET_AM33_2) |
207 | fprintf (asm_out_file, "\t.am33_2\n"); | |
208 | else if (TARGET_AM33) | |
1bc7c5b6 | 209 | fprintf (asm_out_file, "\t.am33\n"); |
11bb1f11 JL |
210 | } |
211 | \f | |
212 | ||
11bb1f11 JL |
213 | /* Print operand X using operand code CODE to assembly language output file |
214 | FILE. */ | |
215 | ||
216 | void | |
f1777882 | 217 | print_operand (FILE *file, rtx x, int code) |
11bb1f11 JL |
218 | { |
219 | switch (code) | |
220 | { | |
221 | case 'b': | |
222 | case 'B': | |
18e9d2f9 AO |
223 | if (cc_status.mdep.fpCC) |
224 | { | |
225 | switch (code == 'b' ? GET_CODE (x) | |
226 | : reverse_condition_maybe_unordered (GET_CODE (x))) | |
227 | { | |
228 | case NE: | |
229 | fprintf (file, "ne"); | |
230 | break; | |
231 | case EQ: | |
232 | fprintf (file, "eq"); | |
233 | break; | |
234 | case GE: | |
235 | fprintf (file, "ge"); | |
236 | break; | |
237 | case GT: | |
238 | fprintf (file, "gt"); | |
239 | break; | |
240 | case LE: | |
241 | fprintf (file, "le"); | |
242 | break; | |
243 | case LT: | |
244 | fprintf (file, "lt"); | |
245 | break; | |
246 | case ORDERED: | |
247 | fprintf (file, "lge"); | |
248 | break; | |
249 | case UNORDERED: | |
250 | fprintf (file, "uo"); | |
251 | break; | |
252 | case LTGT: | |
253 | fprintf (file, "lg"); | |
254 | break; | |
255 | case UNEQ: | |
256 | fprintf (file, "ue"); | |
257 | break; | |
258 | case UNGE: | |
259 | fprintf (file, "uge"); | |
260 | break; | |
261 | case UNGT: | |
262 | fprintf (file, "ug"); | |
263 | break; | |
264 | case UNLE: | |
265 | fprintf (file, "ule"); | |
266 | break; | |
267 | case UNLT: | |
268 | fprintf (file, "ul"); | |
269 | break; | |
270 | default: | |
dc759020 | 271 | gcc_unreachable (); |
18e9d2f9 AO |
272 | } |
273 | break; | |
274 | } | |
11bb1f11 JL |
275 | /* These are normal and reversed branches. */ |
276 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
277 | { | |
278 | case NE: | |
279 | fprintf (file, "ne"); | |
280 | break; | |
281 | case EQ: | |
282 | fprintf (file, "eq"); | |
283 | break; | |
284 | case GE: | |
285 | fprintf (file, "ge"); | |
286 | break; | |
287 | case GT: | |
288 | fprintf (file, "gt"); | |
289 | break; | |
290 | case LE: | |
291 | fprintf (file, "le"); | |
292 | break; | |
293 | case LT: | |
294 | fprintf (file, "lt"); | |
295 | break; | |
296 | case GEU: | |
297 | fprintf (file, "cc"); | |
298 | break; | |
299 | case GTU: | |
300 | fprintf (file, "hi"); | |
301 | break; | |
302 | case LEU: | |
303 | fprintf (file, "ls"); | |
304 | break; | |
305 | case LTU: | |
306 | fprintf (file, "cs"); | |
307 | break; | |
308 | default: | |
dc759020 | 309 | gcc_unreachable (); |
11bb1f11 JL |
310 | } |
311 | break; | |
312 | case 'C': | |
313 | /* This is used for the operand to a call instruction; | |
314 | if it's a REG, enclose it in parens, else output | |
315 | the operand normally. */ | |
316 | if (GET_CODE (x) == REG) | |
317 | { | |
318 | fputc ('(', file); | |
319 | print_operand (file, x, 0); | |
320 | fputc (')', file); | |
321 | } | |
322 | else | |
323 | print_operand (file, x, 0); | |
324 | break; | |
5abc5de9 | 325 | |
18e9d2f9 AO |
326 | case 'D': |
327 | switch (GET_CODE (x)) | |
328 | { | |
329 | case MEM: | |
330 | fputc ('(', file); | |
331 | output_address (XEXP (x, 0)); | |
332 | fputc (')', file); | |
333 | break; | |
334 | ||
335 | case REG: | |
336 | fprintf (file, "fd%d", REGNO (x) - 18); | |
337 | break; | |
338 | ||
339 | default: | |
dc759020 | 340 | gcc_unreachable (); |
18e9d2f9 AO |
341 | } |
342 | break; | |
343 | ||
38c37a0e JL |
344 | /* These are the least significant word in a 64bit value. */ |
345 | case 'L': | |
346 | switch (GET_CODE (x)) | |
347 | { | |
348 | case MEM: | |
349 | fputc ('(', file); | |
350 | output_address (XEXP (x, 0)); | |
351 | fputc (')', file); | |
352 | break; | |
353 | ||
354 | case REG: | |
355 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
356 | break; | |
357 | ||
358 | case SUBREG: | |
ddef6bc7 | 359 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
38c37a0e JL |
360 | break; |
361 | ||
362 | case CONST_DOUBLE: | |
363 | { | |
364 | long val[2]; | |
365 | REAL_VALUE_TYPE rv; | |
366 | ||
367 | switch (GET_MODE (x)) | |
368 | { | |
369 | case DFmode: | |
370 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
371 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 372 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
373 | break;; |
374 | case SFmode: | |
375 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
376 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
cf31fafa | 377 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
378 | break;; |
379 | case VOIDmode: | |
380 | case DImode: | |
381 | print_operand_address (file, | |
382 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
383 | break; | |
69bc71fa KG |
384 | default: |
385 | break; | |
38c37a0e JL |
386 | } |
387 | break; | |
388 | } | |
389 | ||
390 | case CONST_INT: | |
212bc5fa AO |
391 | { |
392 | rtx low, high; | |
393 | split_double (x, &low, &high); | |
394 | fprintf (file, "%ld", (long)INTVAL (low)); | |
395 | break; | |
396 | } | |
38c37a0e JL |
397 | |
398 | default: | |
dc759020 | 399 | gcc_unreachable (); |
38c37a0e JL |
400 | } |
401 | break; | |
402 | ||
403 | /* Similarly, but for the most significant word. */ | |
404 | case 'H': | |
405 | switch (GET_CODE (x)) | |
406 | { | |
407 | case MEM: | |
408 | fputc ('(', file); | |
b72f00af | 409 | x = adjust_address (x, SImode, 4); |
38c37a0e JL |
410 | output_address (XEXP (x, 0)); |
411 | fputc (')', file); | |
412 | break; | |
413 | ||
414 | case REG: | |
415 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
416 | break; | |
417 | ||
418 | case SUBREG: | |
ddef6bc7 | 419 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
38c37a0e JL |
420 | break; |
421 | ||
422 | case CONST_DOUBLE: | |
423 | { | |
424 | long val[2]; | |
425 | REAL_VALUE_TYPE rv; | |
426 | ||
427 | switch (GET_MODE (x)) | |
428 | { | |
429 | case DFmode: | |
430 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
431 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 432 | fprintf (file, "0x%lx", val[1]); |
38c37a0e JL |
433 | break;; |
434 | case SFmode: | |
dc759020 | 435 | gcc_unreachable (); |
38c37a0e JL |
436 | case VOIDmode: |
437 | case DImode: | |
5abc5de9 | 438 | print_operand_address (file, |
38c37a0e JL |
439 | GEN_INT (CONST_DOUBLE_HIGH (x))); |
440 | break; | |
69bc71fa KG |
441 | default: |
442 | break; | |
38c37a0e JL |
443 | } |
444 | break; | |
445 | } | |
446 | ||
447 | case CONST_INT: | |
212bc5fa AO |
448 | { |
449 | rtx low, high; | |
450 | split_double (x, &low, &high); | |
451 | fprintf (file, "%ld", (long)INTVAL (high)); | |
452 | break; | |
453 | } | |
454 | ||
38c37a0e | 455 | default: |
dc759020 | 456 | gcc_unreachable (); |
38c37a0e JL |
457 | } |
458 | break; | |
459 | ||
460 | case 'A': | |
461 | fputc ('(', file); | |
462 | if (GET_CODE (XEXP (x, 0)) == REG) | |
a556fd39 | 463 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx)); |
38c37a0e JL |
464 | else |
465 | output_address (XEXP (x, 0)); | |
466 | fputc (')', file); | |
467 | break; | |
468 | ||
6fafc523 | 469 | case 'N': |
dc759020 | 470 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
a58be199 AO |
471 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); |
472 | break; | |
473 | ||
474 | case 'U': | |
dc759020 | 475 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
a58be199 | 476 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); |
6fafc523 JL |
477 | break; |
478 | ||
576e5acc JL |
479 | /* For shift counts. The hardware ignores the upper bits of |
480 | any immediate, but the assembler will flag an out of range | |
481 | shift count as an error. So we mask off the high bits | |
482 | of the immediate here. */ | |
483 | case 'S': | |
484 | if (GET_CODE (x) == CONST_INT) | |
485 | { | |
a58be199 | 486 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
576e5acc JL |
487 | break; |
488 | } | |
489 | /* FALL THROUGH */ | |
490 | ||
11bb1f11 JL |
491 | default: |
492 | switch (GET_CODE (x)) | |
493 | { | |
494 | case MEM: | |
495 | fputc ('(', file); | |
496 | output_address (XEXP (x, 0)); | |
497 | fputc (')', file); | |
498 | break; | |
499 | ||
38c37a0e JL |
500 | case PLUS: |
501 | output_address (x); | |
502 | break; | |
503 | ||
11bb1f11 JL |
504 | case REG: |
505 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
506 | break; | |
507 | ||
508 | case SUBREG: | |
ddef6bc7 | 509 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
11bb1f11 JL |
510 | break; |
511 | ||
38c37a0e JL |
512 | /* This will only be single precision.... */ |
513 | case CONST_DOUBLE: | |
514 | { | |
515 | unsigned long val; | |
516 | REAL_VALUE_TYPE rv; | |
517 | ||
518 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
519 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
cf31fafa | 520 | fprintf (file, "0x%lx", val); |
38c37a0e JL |
521 | break; |
522 | } | |
523 | ||
11bb1f11 JL |
524 | case CONST_INT: |
525 | case SYMBOL_REF: | |
526 | case CONST: | |
527 | case LABEL_REF: | |
528 | case CODE_LABEL: | |
d1776069 | 529 | case UNSPEC: |
11bb1f11 JL |
530 | print_operand_address (file, x); |
531 | break; | |
532 | default: | |
dc759020 | 533 | gcc_unreachable (); |
11bb1f11 JL |
534 | } |
535 | break; | |
536 | } | |
537 | } | |
538 | ||
539 | /* Output assembly language output for the address ADDR to FILE. */ | |
540 | ||
541 | void | |
f1777882 | 542 | print_operand_address (FILE *file, rtx addr) |
11bb1f11 JL |
543 | { |
544 | switch (GET_CODE (addr)) | |
545 | { | |
705ac34f JL |
546 | case POST_INC: |
547 | print_operand_address (file, XEXP (addr, 0)); | |
548 | fputc ('+', file); | |
549 | break; | |
11bb1f11 | 550 | case REG: |
79e4122c | 551 | print_operand (file, addr, 0); |
11bb1f11 JL |
552 | break; |
553 | case PLUS: | |
554 | { | |
555 | rtx base, index; | |
556 | if (REG_P (XEXP (addr, 0)) | |
557 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
558 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
559 | else if (REG_P (XEXP (addr, 1)) | |
560 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
561 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
562 | else | |
dc759020 | 563 | gcc_unreachable (); |
11bb1f11 JL |
564 | print_operand (file, index, 0); |
565 | fputc (',', file); | |
566 | print_operand (file, base, 0);; | |
567 | break; | |
568 | } | |
569 | case SYMBOL_REF: | |
570 | output_addr_const (file, addr); | |
571 | break; | |
572 | default: | |
573 | output_addr_const (file, addr); | |
574 | break; | |
575 | } | |
576 | } | |
577 | ||
18e9d2f9 AO |
578 | /* Count the number of FP registers that have to be saved. */ |
579 | static int | |
f1777882 | 580 | fp_regs_to_save (void) |
18e9d2f9 AO |
581 | { |
582 | int i, n = 0; | |
583 | ||
584 | if (! TARGET_AM33_2) | |
585 | return 0; | |
586 | ||
587 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 588 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
18e9d2f9 AO |
589 | ++n; |
590 | ||
591 | return n; | |
592 | } | |
593 | ||
f6cd7c62 RS |
594 | /* Print a set of registers in the format required by "movm" and "ret". |
595 | Register K is saved if bit K of MASK is set. The data and address | |
596 | registers can be stored individually, but the extended registers cannot. | |
9f5ed61a | 597 | We assume that the mask already takes that into account. For instance, |
8596d0a1 | 598 | bits 14 to 17 must have the same value. */ |
f6cd7c62 RS |
599 | |
600 | void | |
f1777882 | 601 | mn10300_print_reg_list (FILE *file, int mask) |
f6cd7c62 RS |
602 | { |
603 | int need_comma; | |
604 | int i; | |
605 | ||
606 | need_comma = 0; | |
607 | fputc ('[', file); | |
608 | ||
609 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
610 | if ((mask & (1 << i)) != 0) | |
611 | { | |
612 | if (need_comma) | |
613 | fputc (',', file); | |
614 | fputs (reg_names [i], file); | |
615 | need_comma = 1; | |
616 | } | |
617 | ||
618 | if ((mask & 0x3c000) != 0) | |
619 | { | |
dc759020 | 620 | gcc_assert ((mask & 0x3c000) == 0x3c000); |
f6cd7c62 RS |
621 | if (need_comma) |
622 | fputc (',', file); | |
623 | fputs ("exreg1", file); | |
624 | need_comma = 1; | |
625 | } | |
626 | ||
627 | fputc (']', file); | |
628 | } | |
629 | ||
38c37a0e | 630 | int |
f1777882 | 631 | can_use_return_insn (void) |
38c37a0e | 632 | { |
460f4b9d | 633 | /* size includes the fixed stack space needed for function calls. */ |
38173d38 | 634 | int size = get_frame_size () + crtl->outgoing_args_size; |
460f4b9d JL |
635 | |
636 | /* And space for the return pointer. */ | |
38173d38 | 637 | size += crtl->outgoing_args_size ? 4 : 0; |
38c37a0e JL |
638 | |
639 | return (reload_completed | |
640 | && size == 0 | |
6fb5fa3c DB |
641 | && !df_regs_ever_live_p (2) |
642 | && !df_regs_ever_live_p (3) | |
643 | && !df_regs_ever_live_p (6) | |
644 | && !df_regs_ever_live_p (7) | |
645 | && !df_regs_ever_live_p (14) | |
646 | && !df_regs_ever_live_p (15) | |
647 | && !df_regs_ever_live_p (16) | |
648 | && !df_regs_ever_live_p (17) | |
18e9d2f9 | 649 | && fp_regs_to_save () == 0 |
38c37a0e JL |
650 | && !frame_pointer_needed); |
651 | } | |
652 | ||
f6cd7c62 RS |
653 | /* Returns the set of live, callee-saved registers as a bitmask. The |
654 | callee-saved extended registers cannot be stored individually, so | |
8596d0a1 | 655 | all of them will be included in the mask if any one of them is used. */ |
f6cd7c62 RS |
656 | |
657 | int | |
f1777882 | 658 | mn10300_get_live_callee_saved_regs (void) |
f6cd7c62 RS |
659 | { |
660 | int mask; | |
661 | int i; | |
662 | ||
663 | mask = 0; | |
18e9d2f9 | 664 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
9d54866d | 665 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
f6cd7c62 RS |
666 | mask |= (1 << i); |
667 | if ((mask & 0x3c000) != 0) | |
668 | mask |= 0x3c000; | |
669 | ||
670 | return mask; | |
671 | } | |
672 | ||
2720cc47 NC |
673 | static rtx |
674 | F (rtx r) | |
675 | { | |
676 | RTX_FRAME_RELATED_P (r) = 1; | |
677 | return r; | |
678 | } | |
679 | ||
f6cd7c62 RS |
680 | /* Generate an instruction that pushes several registers onto the stack. |
681 | Register K will be saved if bit K in MASK is set. The function does | |
682 | nothing if MASK is zero. | |
683 | ||
684 | To be compatible with the "movm" instruction, the lowest-numbered | |
685 | register must be stored in the lowest slot. If MASK is the set | |
686 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
687 | instruction will have the form: | |
688 | ||
689 | (parallel | |
690 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
691 | (set (mem:SI (plus:SI (reg:SI 9) | |
692 | (const_int -1*4))) | |
693 | (reg:SI RN)) | |
694 | ... | |
695 | (set (mem:SI (plus:SI (reg:SI 9) | |
696 | (const_int -N*4))) | |
697 | (reg:SI R1))) */ | |
698 | ||
699 | void | |
f1777882 | 700 | mn10300_gen_multiple_store (int mask) |
f6cd7c62 RS |
701 | { |
702 | if (mask != 0) | |
703 | { | |
704 | int i; | |
705 | int count; | |
706 | rtx par; | |
707 | int pari; | |
708 | ||
8596d0a1 | 709 | /* Count how many registers need to be saved. */ |
f6cd7c62 | 710 | count = 0; |
18e9d2f9 | 711 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
f6cd7c62 RS |
712 | if ((mask & (1 << i)) != 0) |
713 | count += 1; | |
714 | ||
715 | /* We need one PARALLEL element to update the stack pointer and | |
8596d0a1 | 716 | an additional element for each register that is stored. */ |
f6cd7c62 RS |
717 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
718 | ||
8596d0a1 | 719 | /* Create the instruction that updates the stack pointer. */ |
f6cd7c62 | 720 | XVECEXP (par, 0, 0) |
2720cc47 NC |
721 | = F (gen_rtx_SET (SImode, |
722 | stack_pointer_rtx, | |
723 | gen_rtx_PLUS (SImode, | |
724 | stack_pointer_rtx, | |
725 | GEN_INT (-count * 4)))); | |
f6cd7c62 | 726 | |
8596d0a1 | 727 | /* Create each store. */ |
f6cd7c62 | 728 | pari = 1; |
18e9d2f9 | 729 | for (i = LAST_EXTENDED_REGNUM; i >= 0; i--) |
f6cd7c62 RS |
730 | if ((mask & (1 << i)) != 0) |
731 | { | |
732 | rtx address = gen_rtx_PLUS (SImode, | |
733 | stack_pointer_rtx, | |
734 | GEN_INT (-pari * 4)); | |
735 | XVECEXP(par, 0, pari) | |
2720cc47 NC |
736 | = F (gen_rtx_SET (VOIDmode, |
737 | gen_rtx_MEM (SImode, address), | |
738 | gen_rtx_REG (SImode, i))); | |
f6cd7c62 RS |
739 | pari += 1; |
740 | } | |
741 | ||
2720cc47 | 742 | F (emit_insn (par)); |
f6cd7c62 RS |
743 | } |
744 | } | |
745 | ||
11bb1f11 | 746 | void |
f1777882 | 747 | expand_prologue (void) |
11bb1f11 | 748 | { |
036182e7 | 749 | HOST_WIDE_INT size; |
3dbc43d1 | 750 | |
3dbc43d1 | 751 | /* SIZE includes the fixed stack space needed for function calls. */ |
38173d38 JH |
752 | size = get_frame_size () + crtl->outgoing_args_size; |
753 | size += (crtl->outgoing_args_size ? 4 : 0); | |
11bb1f11 | 754 | |
8596d0a1 | 755 | /* If we use any of the callee-saved registers, save them now. */ |
f6cd7c62 | 756 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); |
777fbf09 | 757 | |
18e9d2f9 AO |
758 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
759 | { | |
760 | int num_regs_to_save = fp_regs_to_save (), i; | |
761 | HOST_WIDE_INT xsize; | |
762 | enum { save_sp_merge, | |
763 | save_sp_no_merge, | |
764 | save_sp_partial_merge, | |
765 | save_a0_merge, | |
766 | save_a0_no_merge } strategy; | |
767 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; | |
768 | rtx reg; | |
18e9d2f9 AO |
769 | |
770 | /* We have several different strategies to save FP registers. | |
771 | We can store them using SP offsets, which is beneficial if | |
772 | there are just a few registers to save, or we can use `a0' in | |
773 | post-increment mode (`a0' is the only call-clobbered address | |
774 | register that is never used to pass information to a | |
775 | function). Furthermore, if we don't need a frame pointer, we | |
776 | can merge the two SP adds into a single one, but this isn't | |
777 | always beneficial; sometimes we can just split the two adds | |
778 | so that we don't exceed a 16-bit constant size. The code | |
779 | below will select which strategy to use, so as to generate | |
780 | smallest code. Ties are broken in favor or shorter sequences | |
781 | (in terms of number of instructions). */ | |
782 | ||
783 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
784 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
785 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
786 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
787 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ | |
788 | (((S) >= (L)) ? (SIZE1) * (N) \ | |
789 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ | |
790 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
791 | : (ELSE)) | |
792 | #define SIZE_FMOV_SP_(S,N) \ | |
793 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
794 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
795 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
796 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
797 | ||
798 | /* Consider alternative save_sp_merge only if we don't need the | |
4375e090 | 799 | frame pointer and size is nonzero. */ |
18e9d2f9 AO |
800 | if (! frame_pointer_needed && size) |
801 | { | |
802 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
803 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
804 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
805 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
806 | ||
807 | if (this_strategy_size < strategy_size) | |
808 | { | |
809 | strategy = save_sp_merge; | |
810 | strategy_size = this_strategy_size; | |
811 | } | |
812 | } | |
813 | ||
814 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
815 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
816 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
817 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
818 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
819 | if (size) | |
820 | { | |
821 | /* Insn: add -size, sp. */ | |
822 | this_strategy_size += SIZE_ADD_SP (-size); | |
823 | } | |
824 | ||
825 | if (this_strategy_size < strategy_size) | |
826 | { | |
827 | strategy = save_sp_no_merge; | |
828 | strategy_size = this_strategy_size; | |
829 | } | |
830 | ||
831 | /* Consider alternative save_sp_partial_merge only if we don't | |
832 | need a frame pointer and size is reasonably large. */ | |
833 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
834 | { | |
835 | /* Insn: add -128, sp. */ | |
836 | this_strategy_size = SIZE_ADD_SP (-128); | |
837 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
838 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
839 | num_regs_to_save); | |
840 | if (size) | |
841 | { | |
842 | /* Insn: add 128-size, sp. */ | |
843 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
844 | } | |
845 | ||
846 | if (this_strategy_size < strategy_size) | |
847 | { | |
848 | strategy = save_sp_partial_merge; | |
849 | strategy_size = this_strategy_size; | |
850 | } | |
851 | } | |
852 | ||
853 | /* Consider alternative save_a0_merge only if we don't need a | |
4375e090 | 854 | frame pointer, size is nonzero and the user hasn't |
18e9d2f9 AO |
855 | changed the calling conventions of a0. */ |
856 | if (! frame_pointer_needed && size | |
9d54866d | 857 | && call_really_used_regs [FIRST_ADDRESS_REGNUM] |
18e9d2f9 AO |
858 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
859 | { | |
860 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
861 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
862 | /* Insn: mov sp, a0. */ | |
863 | this_strategy_size++; | |
864 | if (size) | |
865 | { | |
866 | /* Insn: add size, a0. */ | |
867 | this_strategy_size += SIZE_ADD_AX (size); | |
868 | } | |
869 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
870 | this_strategy_size += 3 * num_regs_to_save; | |
871 | ||
872 | if (this_strategy_size < strategy_size) | |
873 | { | |
874 | strategy = save_a0_merge; | |
875 | strategy_size = this_strategy_size; | |
876 | } | |
877 | } | |
878 | ||
879 | /* Consider alternative save_a0_no_merge if the user hasn't | |
8596d0a1 | 880 | changed the calling conventions of a0. */ |
9d54866d | 881 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM] |
18e9d2f9 AO |
882 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
883 | { | |
884 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
885 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
886 | /* Insn: mov sp, a0. */ | |
887 | this_strategy_size++; | |
888 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
889 | this_strategy_size += 3 * num_regs_to_save; | |
890 | if (size) | |
891 | { | |
892 | /* Insn: add -size, sp. */ | |
893 | this_strategy_size += SIZE_ADD_SP (-size); | |
894 | } | |
895 | ||
896 | if (this_strategy_size < strategy_size) | |
897 | { | |
898 | strategy = save_a0_no_merge; | |
899 | strategy_size = this_strategy_size; | |
900 | } | |
901 | } | |
902 | ||
903 | /* Emit the initial SP add, common to all strategies. */ | |
904 | switch (strategy) | |
905 | { | |
906 | case save_sp_no_merge: | |
907 | case save_a0_no_merge: | |
2720cc47 NC |
908 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
909 | stack_pointer_rtx, | |
910 | GEN_INT (-4 * num_regs_to_save)))); | |
18e9d2f9 AO |
911 | xsize = 0; |
912 | break; | |
913 | ||
914 | case save_sp_partial_merge: | |
2720cc47 NC |
915 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
916 | stack_pointer_rtx, | |
917 | GEN_INT (-128)))); | |
18e9d2f9 AO |
918 | xsize = 128 - 4 * num_regs_to_save; |
919 | size -= xsize; | |
920 | break; | |
921 | ||
922 | case save_sp_merge: | |
923 | case save_a0_merge: | |
2720cc47 NC |
924 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
925 | stack_pointer_rtx, | |
926 | GEN_INT (-(size + 4 * num_regs_to_save))))); | |
18e9d2f9 | 927 | /* We'll have to adjust FP register saves according to the |
8596d0a1 | 928 | frame size. */ |
18e9d2f9 AO |
929 | xsize = size; |
930 | /* Since we've already created the stack frame, don't do it | |
8596d0a1 | 931 | again at the end of the function. */ |
18e9d2f9 AO |
932 | size = 0; |
933 | break; | |
934 | ||
935 | default: | |
dc759020 | 936 | gcc_unreachable (); |
18e9d2f9 | 937 | } |
5abc5de9 | 938 | |
18e9d2f9 AO |
939 | /* Now prepare register a0, if we have decided to use it. */ |
940 | switch (strategy) | |
941 | { | |
942 | case save_sp_merge: | |
943 | case save_sp_no_merge: | |
944 | case save_sp_partial_merge: | |
945 | reg = 0; | |
946 | break; | |
947 | ||
948 | case save_a0_merge: | |
949 | case save_a0_no_merge: | |
950 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
2720cc47 | 951 | F (emit_insn (gen_movsi (reg, stack_pointer_rtx))); |
18e9d2f9 | 952 | if (xsize) |
2720cc47 | 953 | F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)))); |
18e9d2f9 AO |
954 | reg = gen_rtx_POST_INC (SImode, reg); |
955 | break; | |
5abc5de9 | 956 | |
18e9d2f9 | 957 | default: |
dc759020 | 958 | gcc_unreachable (); |
18e9d2f9 | 959 | } |
5abc5de9 | 960 | |
18e9d2f9 AO |
961 | /* Now actually save the FP registers. */ |
962 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 963 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
18e9d2f9 AO |
964 | { |
965 | rtx addr; | |
966 | ||
967 | if (reg) | |
968 | addr = reg; | |
969 | else | |
970 | { | |
971 | /* If we aren't using `a0', use an SP offset. */ | |
972 | if (xsize) | |
973 | { | |
974 | addr = gen_rtx_PLUS (SImode, | |
975 | stack_pointer_rtx, | |
976 | GEN_INT (xsize)); | |
977 | } | |
978 | else | |
979 | addr = stack_pointer_rtx; | |
5abc5de9 | 980 | |
18e9d2f9 AO |
981 | xsize += 4; |
982 | } | |
983 | ||
2720cc47 NC |
984 | F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr), |
985 | gen_rtx_REG (SFmode, i)))); | |
18e9d2f9 AO |
986 | } |
987 | } | |
988 | ||
777fbf09 | 989 | /* Now put the frame pointer into the frame pointer register. */ |
11bb1f11 | 990 | if (frame_pointer_needed) |
2720cc47 | 991 | F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx)); |
11bb1f11 | 992 | |
777fbf09 | 993 | /* Allocate stack for this frame. */ |
11bb1f11 | 994 | if (size) |
2720cc47 NC |
995 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
996 | stack_pointer_rtx, | |
997 | GEN_INT (-size)))); | |
998 | ||
6fb5fa3c DB |
999 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
1000 | emit_insn (gen_GOTaddr2picreg ()); | |
11bb1f11 JL |
1001 | } |
1002 | ||
1003 | void | |
f1777882 | 1004 | expand_epilogue (void) |
11bb1f11 | 1005 | { |
036182e7 | 1006 | HOST_WIDE_INT size; |
3dbc43d1 | 1007 | |
3dbc43d1 | 1008 | /* SIZE includes the fixed stack space needed for function calls. */ |
38173d38 JH |
1009 | size = get_frame_size () + crtl->outgoing_args_size; |
1010 | size += (crtl->outgoing_args_size ? 4 : 0); | |
11bb1f11 | 1011 | |
18e9d2f9 AO |
1012 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
1013 | { | |
1014 | int num_regs_to_save = fp_regs_to_save (), i; | |
1015 | rtx reg = 0; | |
1016 | ||
1017 | /* We have several options to restore FP registers. We could | |
1018 | load them from SP offsets, but, if there are enough FP | |
1019 | registers to restore, we win if we use a post-increment | |
1020 | addressing mode. */ | |
1021 | ||
1022 | /* If we have a frame pointer, it's the best option, because we | |
1023 | already know it has the value we want. */ | |
1024 | if (frame_pointer_needed) | |
1025 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
1026 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
1027 | it's never used for return values. But only do so if it's | |
1028 | smaller than using SP offsets. */ | |
1029 | else | |
1030 | { | |
1031 | enum { restore_sp_post_adjust, | |
1032 | restore_sp_pre_adjust, | |
1033 | restore_sp_partial_adjust, | |
1034 | restore_a1 } strategy; | |
1035 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
1036 | ||
1037 | /* Consider using sp offsets before adjusting sp. */ | |
1038 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1039 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
1040 | /* If size is too large, we'll have to adjust SP with an | |
1041 | add. */ | |
1042 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1043 | { | |
1044 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
1045 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
1046 | } | |
1047 | /* If we don't have to restore any non-FP registers, | |
1048 | we'll be able to save one byte by using rets. */ | |
1049 | if (! REG_SAVE_BYTES) | |
1050 | this_strategy_size--; | |
1051 | ||
1052 | if (this_strategy_size < strategy_size) | |
1053 | { | |
1054 | strategy = restore_sp_post_adjust; | |
1055 | strategy_size = this_strategy_size; | |
1056 | } | |
1057 | ||
1058 | /* Consider using sp offsets after adjusting sp. */ | |
1059 | /* Insn: add size, sp. */ | |
1060 | this_strategy_size = SIZE_ADD_SP (size); | |
1061 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1062 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
1063 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1064 | save area, so, no savings. */ |
18e9d2f9 AO |
1065 | |
1066 | if (this_strategy_size < strategy_size) | |
1067 | { | |
1068 | strategy = restore_sp_pre_adjust; | |
1069 | strategy_size = this_strategy_size; | |
1070 | } | |
1071 | ||
1072 | /* Consider using sp offsets after partially adjusting sp. | |
1073 | When size is close to 32Kb, we may be able to adjust SP | |
1074 | with an imm16 add instruction while still using fmov | |
1075 | (d8,sp). */ | |
1076 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1077 | { | |
1078 | /* Insn: add size + 4 * num_regs_to_save | |
1079 | + REG_SAVE_BYTES - 252,sp. */ | |
1080 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save | |
1081 | + REG_SAVE_BYTES - 252); | |
1082 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ | |
1083 | this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES | |
1084 | - 4 * num_regs_to_save, | |
1085 | num_regs_to_save); | |
1086 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1087 | save area, so, no savings. */ |
18e9d2f9 AO |
1088 | |
1089 | if (this_strategy_size < strategy_size) | |
1090 | { | |
1091 | strategy = restore_sp_partial_adjust; | |
1092 | strategy_size = this_strategy_size; | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | /* Consider using a1 in post-increment mode, as long as the | |
1097 | user hasn't changed the calling conventions of a1. */ | |
9d54866d | 1098 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1] |
18e9d2f9 AO |
1099 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) |
1100 | { | |
1101 | /* Insn: mov sp,a1. */ | |
1102 | this_strategy_size = 1; | |
1103 | if (size) | |
1104 | { | |
1105 | /* Insn: add size,a1. */ | |
1106 | this_strategy_size += SIZE_ADD_AX (size); | |
1107 | } | |
1108 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1109 | this_strategy_size += 3 * num_regs_to_save; | |
1110 | /* If size is large enough, we may be able to save a | |
1111 | couple of bytes. */ | |
1112 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1113 | { | |
1114 | /* Insn: mov a1,sp. */ | |
1115 | this_strategy_size += 2; | |
1116 | } | |
1117 | /* If we don't have to restore any non-FP registers, | |
1118 | we'll be able to save one byte by using rets. */ | |
1119 | if (! REG_SAVE_BYTES) | |
1120 | this_strategy_size--; | |
1121 | ||
1122 | if (this_strategy_size < strategy_size) | |
1123 | { | |
1124 | strategy = restore_a1; | |
1125 | strategy_size = this_strategy_size; | |
1126 | } | |
1127 | } | |
1128 | ||
1129 | switch (strategy) | |
1130 | { | |
1131 | case restore_sp_post_adjust: | |
1132 | break; | |
1133 | ||
1134 | case restore_sp_pre_adjust: | |
1135 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1136 | stack_pointer_rtx, | |
1137 | GEN_INT (size))); | |
1138 | size = 0; | |
1139 | break; | |
1140 | ||
1141 | case restore_sp_partial_adjust: | |
1142 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1143 | stack_pointer_rtx, | |
1144 | GEN_INT (size + 4 * num_regs_to_save | |
1145 | + REG_SAVE_BYTES - 252))); | |
1146 | size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save; | |
1147 | break; | |
5abc5de9 | 1148 | |
18e9d2f9 AO |
1149 | case restore_a1: |
1150 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1151 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1152 | if (size) | |
1153 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1154 | break; | |
1155 | ||
1156 | default: | |
dc759020 | 1157 | gcc_unreachable (); |
18e9d2f9 AO |
1158 | } |
1159 | } | |
1160 | ||
1161 | /* Adjust the selected register, if any, for post-increment. */ | |
1162 | if (reg) | |
1163 | reg = gen_rtx_POST_INC (SImode, reg); | |
1164 | ||
1165 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 1166 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
18e9d2f9 AO |
1167 | { |
1168 | rtx addr; | |
5abc5de9 | 1169 | |
18e9d2f9 AO |
1170 | if (reg) |
1171 | addr = reg; | |
1172 | else if (size) | |
1173 | { | |
1174 | /* If we aren't using a post-increment register, use an | |
8596d0a1 | 1175 | SP offset. */ |
18e9d2f9 AO |
1176 | addr = gen_rtx_PLUS (SImode, |
1177 | stack_pointer_rtx, | |
1178 | GEN_INT (size)); | |
1179 | } | |
1180 | else | |
1181 | addr = stack_pointer_rtx; | |
1182 | ||
1183 | size += 4; | |
1184 | ||
2720cc47 NC |
1185 | emit_insn (gen_movsf (gen_rtx_REG (SFmode, i), |
1186 | gen_rtx_MEM (SFmode, addr))); | |
18e9d2f9 AO |
1187 | } |
1188 | ||
1189 | /* If we were using the restore_a1 strategy and the number of | |
1190 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1191 | to `sp', to avoid having to use `add' to adjust it. */ | |
1192 | if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255) | |
1193 | { | |
1194 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1195 | size = 0; | |
1196 | } | |
1197 | } | |
1198 | ||
5d29a95f JL |
1199 | /* Maybe cut back the stack, except for the register save area. |
1200 | ||
1201 | If the frame pointer exists, then use the frame pointer to | |
1202 | cut back the stack. | |
1203 | ||
1204 | If the stack size + register save area is more than 255 bytes, | |
1205 | then the stack must be cut back here since the size + register | |
5abc5de9 | 1206 | save size is too big for a ret/retf instruction. |
5d29a95f JL |
1207 | |
1208 | Else leave it alone, it will be cut back as part of the | |
1209 | ret/retf instruction, or there wasn't any stack to begin with. | |
1210 | ||
dab66575 | 1211 | Under no circumstances should the register save area be |
5d29a95f JL |
1212 | deallocated here, that would leave a window where an interrupt |
1213 | could occur and trash the register save area. */ | |
11bb1f11 JL |
1214 | if (frame_pointer_needed) |
1215 | { | |
11bb1f11 | 1216 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
4246e0c5 JL |
1217 | size = 0; |
1218 | } | |
ed6089d6 | 1219 | else if (size + REG_SAVE_BYTES > 255) |
4246e0c5 JL |
1220 | { |
1221 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1222 | stack_pointer_rtx, | |
1223 | GEN_INT (size))); | |
1224 | size = 0; | |
11bb1f11 | 1225 | } |
11bb1f11 | 1226 | |
ed6089d6 | 1227 | /* Adjust the stack and restore callee-saved registers, if any. */ |
6fb5fa3c DB |
1228 | if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1229 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1230 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1231 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
777fbf09 | 1232 | || frame_pointer_needed) |
ed6089d6 AO |
1233 | emit_jump_insn (gen_return_internal_regs |
1234 | (GEN_INT (size + REG_SAVE_BYTES))); | |
777fbf09 | 1235 | else |
ed6089d6 | 1236 | emit_jump_insn (gen_return_internal ()); |
11bb1f11 JL |
1237 | } |
1238 | ||
1239 | /* Update the condition code from the insn. */ | |
1240 | ||
1241 | void | |
f1777882 | 1242 | notice_update_cc (rtx body, rtx insn) |
11bb1f11 | 1243 | { |
11bb1f11 JL |
1244 | switch (get_attr_cc (insn)) |
1245 | { | |
1246 | case CC_NONE: | |
1247 | /* Insn does not affect CC at all. */ | |
1248 | break; | |
1249 | ||
1250 | case CC_NONE_0HIT: | |
1251 | /* Insn does not change CC, but the 0'th operand has been changed. */ | |
1252 | if (cc_status.value1 != 0 | |
1ccbefce | 1253 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
11bb1f11 JL |
1254 | cc_status.value1 = 0; |
1255 | break; | |
1256 | ||
d116300b | 1257 | case CC_SET_ZN: |
1ccbefce | 1258 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
d116300b | 1259 | V,C are unusable. */ |
11bb1f11 | 1260 | CC_STATUS_INIT; |
d116300b | 1261 | cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; |
1ccbefce | 1262 | cc_status.value1 = recog_data.operand[0]; |
11bb1f11 JL |
1263 | break; |
1264 | ||
d116300b | 1265 | case CC_SET_ZNV: |
1ccbefce | 1266 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
d116300b | 1267 | C is unusable. */ |
82c6faa8 | 1268 | CC_STATUS_INIT; |
d116300b | 1269 | cc_status.flags |= CC_NO_CARRY; |
1ccbefce | 1270 | cc_status.value1 = recog_data.operand[0]; |
82c6faa8 JL |
1271 | break; |
1272 | ||
11bb1f11 JL |
1273 | case CC_COMPARE: |
1274 | /* The insn is a compare instruction. */ | |
1275 | CC_STATUS_INIT; | |
1276 | cc_status.value1 = SET_SRC (body); | |
2720cc47 NC |
1277 | if (GET_CODE (SET_SRC (body)) == COMPARE |
1278 | && GET_MODE (XEXP (SET_SRC (body), 0)) == SFmode) | |
18e9d2f9 | 1279 | cc_status.mdep.fpCC = 1; |
11bb1f11 JL |
1280 | break; |
1281 | ||
1282 | case CC_CLOBBER: | |
1283 | /* Insn doesn't leave CC in a usable state. */ | |
1284 | CC_STATUS_INIT; | |
1285 | break; | |
82c6faa8 JL |
1286 | |
1287 | default: | |
dc759020 | 1288 | gcc_unreachable (); |
11bb1f11 | 1289 | } |
11bb1f11 JL |
1290 | } |
1291 | ||
05713b80 | 1292 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
f6cd7c62 RS |
1293 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1294 | parallel. If OP is a multiple store, return a mask indicating which | |
1295 | registers it saves. Return 0 otherwise. */ | |
1296 | ||
1297 | int | |
f1777882 | 1298 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
f6cd7c62 RS |
1299 | { |
1300 | int count; | |
1301 | int mask; | |
1302 | int i; | |
1303 | unsigned int last; | |
1304 | rtx elt; | |
1305 | ||
1306 | count = XVECLEN (op, 0); | |
1307 | if (count < 2) | |
1308 | return 0; | |
1309 | ||
1310 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1311 | elt = XVECEXP (op, 0, 0); | |
1312 | if (GET_CODE (elt) != SET | |
1313 | || GET_CODE (SET_DEST (elt)) != REG | |
1314 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM | |
1315 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1316 | return 0; | |
1317 | ||
1318 | /* Check that A is the stack pointer and B is the expected stack size. | |
1319 | For OP to match, each subsequent instruction should push a word onto | |
1320 | the stack. We therefore expect the first instruction to create | |
8596d0a1 | 1321 | COUNT-1 stack slots. */ |
f6cd7c62 RS |
1322 | elt = SET_SRC (elt); |
1323 | if (GET_CODE (XEXP (elt, 0)) != REG | |
1324 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1325 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1326 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) | |
1327 | return 0; | |
1328 | ||
1329 | /* Now go through the rest of the vector elements. They must be | |
1330 | ordered so that the first instruction stores the highest-numbered | |
1331 | register to the highest stack slot and that subsequent instructions | |
1332 | store a lower-numbered register to the slot below. | |
1333 | ||
1334 | LAST keeps track of the smallest-numbered register stored so far. | |
8596d0a1 | 1335 | MASK is the set of stored registers. */ |
18e9d2f9 | 1336 | last = LAST_EXTENDED_REGNUM + 1; |
f6cd7c62 RS |
1337 | mask = 0; |
1338 | for (i = 1; i < count; i++) | |
1339 | { | |
8596d0a1 | 1340 | /* Check that element i is a (set (mem M) R) and that R is valid. */ |
f6cd7c62 RS |
1341 | elt = XVECEXP (op, 0, i); |
1342 | if (GET_CODE (elt) != SET | |
1343 | || GET_CODE (SET_DEST (elt)) != MEM | |
1344 | || GET_CODE (SET_SRC (elt)) != REG | |
1345 | || REGNO (SET_SRC (elt)) >= last) | |
1346 | return 0; | |
1347 | ||
1348 | /* R was OK, so provisionally add it to MASK. We return 0 in any | |
8596d0a1 | 1349 | case if the rest of the instruction has a flaw. */ |
f6cd7c62 RS |
1350 | last = REGNO (SET_SRC (elt)); |
1351 | mask |= (1 << last); | |
1352 | ||
1353 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1354 | elt = XEXP (SET_DEST (elt), 0); | |
1355 | if (GET_CODE (elt) != PLUS | |
1356 | || GET_CODE (XEXP (elt, 0)) != REG | |
1357 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1358 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1359 | || INTVAL (XEXP (elt, 1)) != -i * 4) | |
1360 | return 0; | |
1361 | } | |
1362 | ||
8596d0a1 | 1363 | /* All or none of the callee-saved extended registers must be in the set. */ |
f6cd7c62 RS |
1364 | if ((mask & 0x3c000) != 0 |
1365 | && (mask & 0x3c000) != 0x3c000) | |
1366 | return 0; | |
1367 | ||
1368 | return mask; | |
1369 | } | |
1370 | ||
11bb1f11 | 1371 | /* What (if any) secondary registers are needed to move IN with mode |
0a2aaacc | 1372 | MODE into a register in register class RCLASS. |
11bb1f11 JL |
1373 | |
1374 | We might be able to simplify this. */ | |
1375 | enum reg_class | |
0a2aaacc | 1376 | mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode, |
3c4774e0 | 1377 | rtx in) |
11bb1f11 | 1378 | { |
6528281d JL |
1379 | rtx inner = in; |
1380 | ||
1381 | /* Strip off any SUBREG expressions from IN. Basically we want | |
1382 | to know if IN is a pseudo or (subreg (pseudo)) as those can | |
1383 | turn into MEMs during reload. */ | |
1384 | while (GET_CODE (inner) == SUBREG) | |
1385 | inner = SUBREG_REG (inner); | |
1386 | ||
11bb1f11 JL |
1387 | /* Memory loads less than a full word wide can't have an |
1388 | address or stack pointer destination. They must use | |
1389 | a data register as an intermediate register. */ | |
15c09738 | 1390 | if ((GET_CODE (in) == MEM |
6528281d JL |
1391 | || (GET_CODE (inner) == REG |
1392 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER)) | |
11bb1f11 | 1393 | && (mode == QImode || mode == HImode) |
0a2aaacc KG |
1394 | && (rclass == ADDRESS_REGS || rclass == SP_REGS |
1395 | || rclass == SP_OR_ADDRESS_REGS)) | |
4d1a91c2 | 1396 | { |
705ac34f JL |
1397 | if (TARGET_AM33) |
1398 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
1399 | return DATA_REGS; |
1400 | } | |
11bb1f11 JL |
1401 | |
1402 | /* We can't directly load sp + const_int into a data register; | |
1403 | we must use an address register as an intermediate. */ | |
0a2aaacc KG |
1404 | if (rclass != SP_REGS |
1405 | && rclass != ADDRESS_REGS | |
1406 | && rclass != SP_OR_ADDRESS_REGS | |
1407 | && rclass != SP_OR_EXTENDED_REGS | |
1408 | && rclass != ADDRESS_OR_EXTENDED_REGS | |
1409 | && rclass != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
11bb1f11 JL |
1410 | && (in == stack_pointer_rtx |
1411 | || (GET_CODE (in) == PLUS | |
777fbf09 JL |
1412 | && (XEXP (in, 0) == stack_pointer_rtx |
1413 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
11bb1f11 JL |
1414 | return ADDRESS_REGS; |
1415 | ||
4c742813 JL |
1416 | if (GET_CODE (in) == PLUS |
1417 | && (XEXP (in, 0) == stack_pointer_rtx | |
1418 | || XEXP (in, 1) == stack_pointer_rtx)) | |
fc4f3261 | 1419 | return GENERAL_REGS; |
5abc5de9 | 1420 | |
6528281d JL |
1421 | if (TARGET_AM33_2 |
1422 | && rclass == FP_REGS) | |
18e9d2f9 | 1423 | { |
6528281d JL |
1424 | /* We can't load directly into an FP register from a |
1425 | constant address. */ | |
1426 | if (GET_CODE (in) == MEM | |
1427 | && CONSTANT_ADDRESS_P (XEXP (in, 0))) | |
1428 | return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS); | |
1429 | ||
1430 | /* Handle case were a pseudo may not get a hard register | |
1431 | but has an equivalent memory location defined. */ | |
1432 | if (GET_CODE (inner) == REG | |
1433 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER | |
1434 | && reg_equiv_mem [REGNO (inner)] | |
1435 | && CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0))) | |
1436 | return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS); | |
18e9d2f9 AO |
1437 | } |
1438 | ||
777fbf09 JL |
1439 | /* Otherwise assume no secondary reloads are needed. */ |
1440 | return NO_REGS; | |
1441 | } | |
1442 | ||
1443 | int | |
f1777882 | 1444 | initial_offset (int from, int to) |
777fbf09 | 1445 | { |
3dbc43d1 JL |
1446 | /* The difference between the argument pointer and the frame pointer |
1447 | is the size of the callee register save area. */ | |
777fbf09 | 1448 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
11bb1f11 | 1449 | { |
6fb5fa3c DB |
1450 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1451 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1452 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1453 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
18e9d2f9 | 1454 | || fp_regs_to_save () |
777fbf09 | 1455 | || frame_pointer_needed) |
18e9d2f9 AO |
1456 | return REG_SAVE_BYTES |
1457 | + 4 * fp_regs_to_save (); | |
777fbf09 | 1458 | else |
22ef4e9b | 1459 | return 0; |
11bb1f11 JL |
1460 | } |
1461 | ||
3dbc43d1 JL |
1462 | /* The difference between the argument pointer and the stack pointer is |
1463 | the sum of the size of this function's frame, the callee register save | |
1464 | area, and the fixed stack space needed for function calls (if any). */ | |
777fbf09 JL |
1465 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
1466 | { | |
6fb5fa3c DB |
1467 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1468 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1469 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1470 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
18e9d2f9 | 1471 | || fp_regs_to_save () |
777fbf09 | 1472 | || frame_pointer_needed) |
4d1a91c2 | 1473 | return (get_frame_size () + REG_SAVE_BYTES |
18e9d2f9 | 1474 | + 4 * fp_regs_to_save () |
38173d38 JH |
1475 | + (crtl->outgoing_args_size |
1476 | ? crtl->outgoing_args_size + 4 : 0)); | |
777fbf09 | 1477 | else |
460f4b9d | 1478 | return (get_frame_size () |
38173d38 JH |
1479 | + (crtl->outgoing_args_size |
1480 | ? crtl->outgoing_args_size + 4 : 0)); | |
777fbf09 | 1481 | } |
11bb1f11 | 1482 | |
3dbc43d1 JL |
1483 | /* The difference between the frame pointer and stack pointer is the sum |
1484 | of the size of this function's frame and the fixed stack space needed | |
1485 | for function calls (if any). */ | |
777fbf09 | 1486 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
460f4b9d | 1487 | return (get_frame_size () |
38173d38 JH |
1488 | + (crtl->outgoing_args_size |
1489 | ? crtl->outgoing_args_size + 4 : 0)); | |
777fbf09 | 1490 | |
dc759020 | 1491 | gcc_unreachable (); |
11bb1f11 | 1492 | } |
22ef4e9b | 1493 | |
bd5bd7ac KH |
1494 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
1495 | ||
9024ea92 | 1496 | static bool |
586de218 | 1497 | mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
9024ea92 KH |
1498 | { |
1499 | /* Return values > 8 bytes in length in memory. */ | |
b1eb8119 DD |
1500 | return (int_size_in_bytes (type) > 8 |
1501 | || int_size_in_bytes (type) == 0 | |
1502 | || TYPE_MODE (type) == BLKmode); | |
9024ea92 KH |
1503 | } |
1504 | ||
22ef4e9b JL |
1505 | /* Flush the argument registers to the stack for a stdarg function; |
1506 | return the new argument pointer. */ | |
9024ea92 | 1507 | static rtx |
f1777882 | 1508 | mn10300_builtin_saveregs (void) |
22ef4e9b | 1509 | { |
fc2acc87 | 1510 | rtx offset, mem; |
22ef4e9b | 1511 | tree fntype = TREE_TYPE (current_function_decl); |
f38958e8 | 1512 | int argadj = ((!stdarg_p (fntype)) |
22ef4e9b | 1513 | ? UNITS_PER_WORD : 0); |
4862826d | 1514 | alias_set_type set = get_varargs_alias_set (); |
22ef4e9b JL |
1515 | |
1516 | if (argadj) | |
38173d38 | 1517 | offset = plus_constant (crtl->args.arg_offset_rtx, argadj); |
22ef4e9b | 1518 | else |
38173d38 | 1519 | offset = crtl->args.arg_offset_rtx; |
22ef4e9b | 1520 | |
38173d38 | 1521 | mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer); |
ba4828e0 | 1522 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1523 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1524 | ||
1525 | mem = gen_rtx_MEM (SImode, | |
38173d38 | 1526 | plus_constant (crtl->args.internal_arg_pointer, 4)); |
ba4828e0 | 1527 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1528 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1529 | ||
22ef4e9b | 1530 | return copy_to_reg (expand_binop (Pmode, add_optab, |
38173d38 | 1531 | crtl->args.internal_arg_pointer, |
22ef4e9b JL |
1532 | offset, 0, 0, OPTAB_LIB_WIDEN)); |
1533 | } | |
1534 | ||
d7bd8aeb | 1535 | static void |
f1777882 | 1536 | mn10300_va_start (tree valist, rtx nextarg) |
fc2acc87 | 1537 | { |
6c535c69 | 1538 | nextarg = expand_builtin_saveregs (); |
e5faf155 | 1539 | std_expand_builtin_va_start (valist, nextarg); |
fc2acc87 RH |
1540 | } |
1541 | ||
8cd5a4e0 RH |
1542 | /* Return true when a parameter should be passed by reference. */ |
1543 | ||
1544 | static bool | |
1545 | mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
586de218 | 1546 | enum machine_mode mode, const_tree type, |
8cd5a4e0 RH |
1547 | bool named ATTRIBUTE_UNUSED) |
1548 | { | |
1549 | unsigned HOST_WIDE_INT size; | |
1550 | ||
1551 | if (type) | |
1552 | size = int_size_in_bytes (type); | |
1553 | else | |
1554 | size = GET_MODE_SIZE (mode); | |
1555 | ||
b1eb8119 | 1556 | return (size > 8 || size == 0); |
8cd5a4e0 RH |
1557 | } |
1558 | ||
22ef4e9b | 1559 | /* Return an RTX to represent where a value with mode MODE will be returned |
990dc016 | 1560 | from a function. If the result is NULL_RTX, the argument is pushed. */ |
22ef4e9b JL |
1561 | |
1562 | rtx | |
f1777882 KH |
1563 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
1564 | tree type, int named ATTRIBUTE_UNUSED) | |
22ef4e9b | 1565 | { |
990dc016 | 1566 | rtx result = NULL_RTX; |
22ef4e9b JL |
1567 | int size, align; |
1568 | ||
1569 | /* We only support using 2 data registers as argument registers. */ | |
1570 | int nregs = 2; | |
1571 | ||
1572 | /* Figure out the size of the object to be passed. */ | |
1573 | if (mode == BLKmode) | |
1574 | size = int_size_in_bytes (type); | |
1575 | else | |
1576 | size = GET_MODE_SIZE (mode); | |
1577 | ||
1578 | /* Figure out the alignment of the object to be passed. */ | |
1579 | align = size; | |
1580 | ||
1581 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1582 | ||
1583 | /* Don't pass this arg via a register if all the argument registers | |
1584 | are used up. */ | |
1585 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
990dc016 | 1586 | return result; |
22ef4e9b JL |
1587 | |
1588 | /* Don't pass this arg via a register if it would be split between | |
1589 | registers and memory. */ | |
1590 | if (type == NULL_TREE | |
1591 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
990dc016 | 1592 | return result; |
22ef4e9b JL |
1593 | |
1594 | switch (cum->nbytes / UNITS_PER_WORD) | |
1595 | { | |
1596 | case 0: | |
990dc016 | 1597 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM); |
22ef4e9b JL |
1598 | break; |
1599 | case 1: | |
990dc016 | 1600 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1); |
22ef4e9b JL |
1601 | break; |
1602 | default: | |
990dc016 | 1603 | break; |
22ef4e9b JL |
1604 | } |
1605 | ||
1606 | return result; | |
1607 | } | |
1608 | ||
78a52f11 RH |
1609 | /* Return the number of bytes of registers to use for an argument passed |
1610 | partially in registers and partially in memory. */ | |
22ef4e9b | 1611 | |
78a52f11 RH |
1612 | static int |
1613 | mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1614 | tree type, bool named ATTRIBUTE_UNUSED) | |
22ef4e9b JL |
1615 | { |
1616 | int size, align; | |
1617 | ||
1618 | /* We only support using 2 data registers as argument registers. */ | |
1619 | int nregs = 2; | |
1620 | ||
1621 | /* Figure out the size of the object to be passed. */ | |
1622 | if (mode == BLKmode) | |
1623 | size = int_size_in_bytes (type); | |
1624 | else | |
1625 | size = GET_MODE_SIZE (mode); | |
1626 | ||
1627 | /* Figure out the alignment of the object to be passed. */ | |
1628 | align = size; | |
1629 | ||
1630 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1631 | ||
1632 | /* Don't pass this arg via a register if all the argument registers | |
1633 | are used up. */ | |
1634 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1635 | return 0; | |
1636 | ||
1637 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1638 | return 0; | |
1639 | ||
1640 | /* Don't pass this arg via a register if it would be split between | |
1641 | registers and memory. */ | |
1642 | if (type == NULL_TREE | |
1643 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1644 | return 0; | |
1645 | ||
78a52f11 | 1646 | return nregs * UNITS_PER_WORD - cum->nbytes; |
22ef4e9b JL |
1647 | } |
1648 | ||
b1eb8119 DD |
1649 | /* Return the location of the function's value. This will be either |
1650 | $d0 for integer functions, $a0 for pointers, or a PARALLEL of both | |
1651 | $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that | |
1652 | we only return the PARALLEL for outgoing values; we do not want | |
1653 | callers relying on this extra copy. */ | |
1654 | ||
34732b0a AS |
1655 | static rtx |
1656 | mn10300_function_value (const_tree valtype, | |
1657 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
1658 | bool outgoing) | |
b1eb8119 DD |
1659 | { |
1660 | rtx rv; | |
1661 | enum machine_mode mode = TYPE_MODE (valtype); | |
1662 | ||
1663 | if (! POINTER_TYPE_P (valtype)) | |
1664 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1665 | else if (! TARGET_PTR_A0D0 || ! outgoing | |
e3b5732b | 1666 | || cfun->returns_struct) |
b1eb8119 DD |
1667 | return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM); |
1668 | ||
1669 | rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2)); | |
1670 | XVECEXP (rv, 0, 0) | |
1671 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1672 | gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM), | |
1673 | GEN_INT (0)); | |
5abc5de9 | 1674 | |
b1eb8119 DD |
1675 | XVECEXP (rv, 0, 1) |
1676 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1677 | gen_rtx_REG (mode, FIRST_DATA_REGNUM), | |
1678 | GEN_INT (0)); | |
1679 | return rv; | |
1680 | } | |
1681 | ||
34732b0a AS |
1682 | /* Implements TARGET_LIBCALL_VALUE. */ |
1683 | ||
1684 | static rtx | |
1685 | mn10300_libcall_value (enum machine_mode mode, | |
1686 | const_rtx fun ATTRIBUTE_UNUSED) | |
1687 | { | |
1688 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1689 | } | |
1690 | ||
1691 | /* Implements FUNCTION_VALUE_REGNO_P. */ | |
1692 | ||
1693 | bool | |
1694 | mn10300_function_value_regno_p (const unsigned int regno) | |
1695 | { | |
1696 | return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM); | |
1697 | } | |
1698 | ||
22ef4e9b | 1699 | /* Output a tst insn. */ |
1943c2c1 | 1700 | const char * |
f1777882 | 1701 | output_tst (rtx operand, rtx insn) |
22ef4e9b | 1702 | { |
22ef4e9b JL |
1703 | rtx temp; |
1704 | int past_call = 0; | |
1705 | ||
1706 | /* We can save a byte if we can find a register which has the value | |
1707 | zero in it. */ | |
1708 | temp = PREV_INSN (insn); | |
74452ac3 | 1709 | while (optimize && temp) |
22ef4e9b JL |
1710 | { |
1711 | rtx set; | |
1712 | ||
1713 | /* We allow the search to go through call insns. We record | |
1714 | the fact that we've past a CALL_INSN and reject matches which | |
1715 | use call clobbered registers. */ | |
1716 | if (GET_CODE (temp) == CODE_LABEL | |
1717 | || GET_CODE (temp) == JUMP_INSN | |
1718 | || GET_CODE (temp) == BARRIER) | |
1719 | break; | |
1720 | ||
1721 | if (GET_CODE (temp) == CALL_INSN) | |
1722 | past_call = 1; | |
1723 | ||
1724 | if (GET_CODE (temp) == NOTE) | |
1725 | { | |
1726 | temp = PREV_INSN (temp); | |
1727 | continue; | |
1728 | } | |
1729 | ||
8596d0a1 | 1730 | /* It must be an insn, see if it is a simple set. */ |
22ef4e9b JL |
1731 | set = single_set (temp); |
1732 | if (!set) | |
1733 | { | |
1734 | temp = PREV_INSN (temp); | |
1735 | continue; | |
1736 | } | |
1737 | ||
1738 | /* Are we setting a data register to zero (this does not win for | |
5abc5de9 | 1739 | address registers)? |
22ef4e9b JL |
1740 | |
1741 | If it's a call clobbered register, have we past a call? | |
1742 | ||
1743 | Make sure the register we find isn't the same as ourself; | |
4d1a91c2 JL |
1744 | the mn10300 can't encode that. |
1745 | ||
1746 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1747 | so the code to detect calls here isn't doing anything useful. */ | |
22ef4e9b JL |
1748 | if (REG_P (SET_DEST (set)) |
1749 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1750 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
74452ac3 JL |
1751 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1752 | == REGNO_REG_CLASS (REGNO (operand))) | |
705ac34f JL |
1753 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1754 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
5abc5de9 | 1755 | && (!past_call |
9d54866d | 1756 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
705ac34f JL |
1757 | { |
1758 | rtx xoperands[2]; | |
1759 | xoperands[0] = operand; | |
1760 | xoperands[1] = SET_DEST (set); | |
1761 | ||
1762 | output_asm_insn ("cmp %1,%0", xoperands); | |
1763 | return ""; | |
1764 | } | |
1765 | ||
1766 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1767 | && REG_P (SET_DEST (set)) | |
1768 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1769 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1770 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1771 | != REGNO_REG_CLASS (REGNO (operand))) | |
1772 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
22ef4e9b | 1773 | && REGNO (SET_DEST (set)) != REGNO (operand) |
5abc5de9 | 1774 | && (!past_call |
9d54866d | 1775 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
22ef4e9b JL |
1776 | { |
1777 | rtx xoperands[2]; | |
1778 | xoperands[0] = operand; | |
1779 | xoperands[1] = SET_DEST (set); | |
1780 | ||
1781 | output_asm_insn ("cmp %1,%0", xoperands); | |
1782 | return ""; | |
1783 | } | |
1784 | temp = PREV_INSN (temp); | |
1785 | } | |
1786 | return "cmp 0,%0"; | |
1787 | } | |
460f4b9d JL |
1788 | |
1789 | int | |
f1777882 | 1790 | impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
460f4b9d | 1791 | { |
460f4b9d JL |
1792 | if (GET_CODE (op) != PLUS) |
1793 | return 0; | |
1794 | ||
4c742813 JL |
1795 | if (XEXP (op, 0) == stack_pointer_rtx |
1796 | || XEXP (op, 1) == stack_pointer_rtx) | |
460f4b9d JL |
1797 | return 1; |
1798 | ||
460f4b9d JL |
1799 | return 0; |
1800 | } | |
e9ad4573 | 1801 | |
f8912297 JL |
1802 | /* Similarly, but when using a zero_extract pattern for a btst where |
1803 | the source operand might end up in memory. */ | |
1804 | int | |
f1777882 | 1805 | mask_ok_for_mem_btst (int len, int bit) |
f8912297 | 1806 | { |
4977bab6 | 1807 | unsigned int mask = 0; |
f8912297 JL |
1808 | |
1809 | while (len > 0) | |
1810 | { | |
1811 | mask |= (1 << bit); | |
1812 | bit++; | |
1813 | len--; | |
1814 | } | |
1815 | ||
1816 | /* MASK must bit into an 8bit value. */ | |
1817 | return (((mask & 0xff) == mask) | |
1818 | || ((mask & 0xff00) == mask) | |
1819 | || ((mask & 0xff0000) == mask) | |
1820 | || ((mask & 0xff000000) == mask)); | |
1821 | } | |
1822 | ||
e9ad4573 JL |
1823 | /* Return 1 if X contains a symbolic expression. We know these |
1824 | expressions will have one of a few well defined forms, so | |
1825 | we need only check those forms. */ | |
1826 | int | |
f1777882 | 1827 | symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e9ad4573 JL |
1828 | { |
1829 | switch (GET_CODE (op)) | |
1830 | { | |
1831 | case SYMBOL_REF: | |
1832 | case LABEL_REF: | |
1833 | return 1; | |
1834 | case CONST: | |
1835 | op = XEXP (op, 0); | |
1836 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1837 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
1838 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
1839 | default: | |
1840 | return 0; | |
1841 | } | |
1842 | } | |
1843 | ||
1844 | /* Try machine dependent ways of modifying an illegitimate address | |
1845 | to be legitimate. If we find one, return the new valid address. | |
1846 | This macro is used in only one place: `memory_address' in explow.c. | |
1847 | ||
1848 | OLDX is the address as it was before break_out_memory_refs was called. | |
1849 | In some cases it is useful to look at this to decide what needs to be done. | |
1850 | ||
e9ad4573 JL |
1851 | Normally it is always safe for this macro to do nothing. It exists to |
1852 | recognize opportunities to optimize the output. | |
1853 | ||
1854 | But on a few ports with segmented architectures and indexed addressing | |
1855 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
1856 | rtx | |
506d7b68 PB |
1857 | mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1858 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
e9ad4573 | 1859 | { |
d1776069 AO |
1860 | if (flag_pic && ! legitimate_pic_operand_p (x)) |
1861 | x = legitimize_pic_address (oldx, NULL_RTX); | |
1862 | ||
e9ad4573 JL |
1863 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1864 | special handling to avoid creating an indexed memory address | |
1865 | with x-100000 as the base. */ | |
1866 | if (GET_CODE (x) == PLUS | |
1867 | && symbolic_operand (XEXP (x, 1), VOIDmode)) | |
1868 | { | |
1869 | /* Ugly. We modify things here so that the address offset specified | |
1870 | by the index expression is computed first, then added to x to form | |
1871 | the entire address. */ | |
1872 | ||
69bc71fa | 1873 | rtx regx1, regy1, regy2, y; |
e9ad4573 JL |
1874 | |
1875 | /* Strip off any CONST. */ | |
1876 | y = XEXP (x, 1); | |
1877 | if (GET_CODE (y) == CONST) | |
1878 | y = XEXP (y, 0); | |
1879 | ||
bf4219f0 JL |
1880 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1881 | { | |
1882 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1883 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1884 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1885 | regx1 = force_reg (Pmode, | |
1c563bed | 1886 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, regy2)); |
c5c76735 | 1887 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
bf4219f0 | 1888 | } |
e9ad4573 | 1889 | } |
371036e0 | 1890 | return x; |
e9ad4573 | 1891 | } |
460ad325 | 1892 | |
d1776069 | 1893 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
8596d0a1 | 1894 | @GOTOFF in `reg'. */ |
d1776069 | 1895 | rtx |
f1777882 | 1896 | legitimize_pic_address (rtx orig, rtx reg) |
d1776069 AO |
1897 | { |
1898 | if (GET_CODE (orig) == LABEL_REF | |
1899 | || (GET_CODE (orig) == SYMBOL_REF | |
1900 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1901 | || ! MN10300_GLOBAL_P (orig)))) | |
1902 | { | |
1903 | if (reg == 0) | |
1904 | reg = gen_reg_rtx (Pmode); | |
1905 | ||
1906 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
1907 | return reg; | |
1908 | } | |
1909 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1910 | { | |
1911 | if (reg == 0) | |
1912 | reg = gen_reg_rtx (Pmode); | |
1913 | ||
1914 | emit_insn (gen_symGOT2reg (reg, orig)); | |
1915 | return reg; | |
1916 | } | |
1917 | return orig; | |
1918 | } | |
1919 | ||
1920 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
4375e090 | 1921 | isn't protected by a PIC unspec; nonzero otherwise. */ |
d1776069 | 1922 | int |
f1777882 | 1923 | legitimate_pic_operand_p (rtx x) |
d1776069 AO |
1924 | { |
1925 | register const char *fmt; | |
1926 | register int i; | |
1927 | ||
1928 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1929 | return 0; | |
1930 | ||
1931 | if (GET_CODE (x) == UNSPEC | |
1932 | && (XINT (x, 1) == UNSPEC_PIC | |
1933 | || XINT (x, 1) == UNSPEC_GOT | |
1934 | || XINT (x, 1) == UNSPEC_GOTOFF | |
d4e2d7d2 RS |
1935 | || XINT (x, 1) == UNSPEC_PLT |
1936 | || XINT (x, 1) == UNSPEC_GOTSYM_OFF)) | |
d1776069 AO |
1937 | return 1; |
1938 | ||
d1776069 AO |
1939 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
1940 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1941 | { | |
1942 | if (fmt[i] == 'E') | |
1943 | { | |
1944 | register int j; | |
1945 | ||
1946 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1947 | if (! legitimate_pic_operand_p (XVECEXP (x, i, j))) | |
1948 | return 0; | |
1949 | } | |
1950 | else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i))) | |
1951 | return 0; | |
1952 | } | |
1953 | ||
1954 | return 1; | |
1955 | } | |
1956 | ||
e733134f | 1957 | /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is |
c6c3dba9 PB |
1958 | legitimate, and FALSE otherwise. |
1959 | ||
1960 | On the mn10300, the value in the address register must be | |
1961 | in the same memory space/segment as the effective address. | |
1962 | ||
1963 | This is problematical for reload since it does not understand | |
1964 | that base+index != index+base in a memory reference. | |
1965 | ||
1966 | Note it is still possible to use reg+reg addressing modes, | |
1967 | it's just much more difficult. For a discussion of a possible | |
1968 | workaround and solution, see the comments in pa.c before the | |
1969 | function record_unscaled_index_insn_codes. */ | |
1970 | ||
e733134f | 1971 | bool |
c6c3dba9 | 1972 | mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) |
e733134f AO |
1973 | { |
1974 | if (CONSTANT_ADDRESS_P (x) | |
1975 | && (! flag_pic || legitimate_pic_operand_p (x))) | |
1976 | return TRUE; | |
1977 | ||
1978 | if (RTX_OK_FOR_BASE_P (x, strict)) | |
1979 | return TRUE; | |
1980 | ||
1981 | if (TARGET_AM33 | |
1982 | && GET_CODE (x) == POST_INC | |
1983 | && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict) | |
1984 | && (mode == SImode || mode == SFmode || mode == HImode)) | |
1985 | return TRUE; | |
1986 | ||
1987 | if (GET_CODE (x) == PLUS) | |
1988 | { | |
1989 | rtx base = 0, index = 0; | |
1990 | ||
1991 | if (REG_P (XEXP (x, 0)) | |
1992 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict)) | |
1993 | { | |
1994 | base = XEXP (x, 0); | |
1995 | index = XEXP (x, 1); | |
1996 | } | |
1997 | ||
1998 | if (REG_P (XEXP (x, 1)) | |
1999 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict)) | |
2000 | { | |
2001 | base = XEXP (x, 1); | |
2002 | index = XEXP (x, 0); | |
2003 | } | |
2004 | ||
2005 | if (base != 0 && index != 0) | |
2006 | { | |
2007 | if (GET_CODE (index) == CONST_INT) | |
2008 | return TRUE; | |
2009 | if (GET_CODE (index) == CONST | |
5542b23d | 2010 | && GET_CODE (XEXP (index, 0)) != PLUS |
e733134f AO |
2011 | && (! flag_pic |
2012 | || legitimate_pic_operand_p (index))) | |
2013 | return TRUE; | |
2014 | } | |
2015 | } | |
2016 | ||
2017 | return FALSE; | |
2018 | } | |
2019 | ||
dcefdf67 | 2020 | static int |
899cc0f4 | 2021 | mn10300_address_cost_1 (rtx x, int *unsig) |
460ad325 | 2022 | { |
460ad325 AO |
2023 | switch (GET_CODE (x)) |
2024 | { | |
2025 | case REG: | |
2026 | switch (REGNO_REG_CLASS (REGNO (x))) | |
2027 | { | |
2028 | case SP_REGS: | |
2029 | *unsig = 1; | |
2030 | return 0; | |
2031 | ||
2032 | case ADDRESS_REGS: | |
2033 | return 1; | |
2034 | ||
2035 | case DATA_REGS: | |
2036 | case EXTENDED_REGS: | |
18e9d2f9 | 2037 | case FP_REGS: |
460ad325 AO |
2038 | return 3; |
2039 | ||
2040 | case NO_REGS: | |
2041 | return 5; | |
2042 | ||
2043 | default: | |
dc759020 | 2044 | gcc_unreachable (); |
460ad325 AO |
2045 | } |
2046 | ||
2047 | case PLUS: | |
2048 | case MINUS: | |
d82704fb AO |
2049 | case ASHIFT: |
2050 | case AND: | |
460ad325 | 2051 | case IOR: |
dcefdf67 RH |
2052 | return (mn10300_address_cost_1 (XEXP (x, 0), unsig) |
2053 | + mn10300_address_cost_1 (XEXP (x, 1), unsig)); | |
460ad325 AO |
2054 | |
2055 | case EXPR_LIST: | |
2056 | case SUBREG: | |
2057 | case MEM: | |
899cc0f4 | 2058 | return mn10300_address_cost (XEXP (x, 0), !optimize_size); |
460ad325 AO |
2059 | |
2060 | case ZERO_EXTEND: | |
2061 | *unsig = 1; | |
dcefdf67 | 2062 | return mn10300_address_cost_1 (XEXP (x, 0), unsig); |
460ad325 AO |
2063 | |
2064 | case CONST_INT: | |
2065 | if (INTVAL (x) == 0) | |
2066 | return 0; | |
2067 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
2068 | return 1; | |
2069 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
2070 | return 3; | |
2071 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
2072 | return 5; | |
2073 | return 7; | |
2074 | ||
2075 | case CONST: | |
2076 | case SYMBOL_REF: | |
d82704fb | 2077 | case LABEL_REF: |
460ad325 AO |
2078 | return 8; |
2079 | ||
460ad325 | 2080 | default: |
dc759020 | 2081 | gcc_unreachable (); |
460ad325 AO |
2082 | |
2083 | } | |
2084 | } | |
3c50106f | 2085 | |
dcefdf67 | 2086 | static int |
f40751dd | 2087 | mn10300_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED) |
dcefdf67 RH |
2088 | { |
2089 | int s = 0; | |
2090 | return mn10300_address_cost_1 (x, &s); | |
2091 | } | |
2092 | ||
3c50106f | 2093 | static bool |
f40751dd | 2094 | mn10300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed ATTRIBUTE_UNUSED) |
3c50106f RH |
2095 | { |
2096 | switch (code) | |
2097 | { | |
2098 | case CONST_INT: | |
2099 | /* Zeros are extremely cheap. */ | |
f90b7a5a | 2100 | if (INTVAL (x) == 0 && (outer_code == SET || outer_code == COMPARE)) |
3c50106f RH |
2101 | *total = 0; |
2102 | /* If it fits in 8 bits, then it's still relatively cheap. */ | |
2103 | else if (INT_8_BITS (INTVAL (x))) | |
2104 | *total = 1; | |
2105 | /* This is the "base" cost, includes constants where either the | |
2106 | upper or lower 16bits are all zeros. */ | |
2107 | else if (INT_16_BITS (INTVAL (x)) | |
2108 | || (INTVAL (x) & 0xffff) == 0 | |
2109 | || (INTVAL (x) & 0xffff0000) == 0) | |
2110 | *total = 2; | |
2111 | else | |
2112 | *total = 4; | |
2113 | return true; | |
2114 | ||
2115 | case CONST: | |
2116 | case LABEL_REF: | |
2117 | case SYMBOL_REF: | |
2118 | /* These are more costly than a CONST_INT, but we can relax them, | |
2119 | so they're less costly than a CONST_DOUBLE. */ | |
2120 | *total = 6; | |
2121 | return true; | |
2122 | ||
2123 | case CONST_DOUBLE: | |
2124 | /* We don't optimize CONST_DOUBLEs well nor do we relax them well, | |
2125 | so their cost is very high. */ | |
2126 | *total = 8; | |
2127 | return true; | |
2128 | ||
f90b7a5a PB |
2129 | case ZERO_EXTRACT: |
2130 | /* This is cheap, we can use btst. */ | |
2131 | if (outer_code == COMPARE) | |
2132 | *total = 0; | |
2133 | return false; | |
2134 | ||
3c50106f RH |
2135 | /* ??? This probably needs more work. */ |
2136 | case MOD: | |
2137 | case DIV: | |
2138 | case MULT: | |
2139 | *total = 8; | |
2140 | return true; | |
2141 | ||
2142 | default: | |
2143 | return false; | |
2144 | } | |
2145 | } | |
fe7496dd AO |
2146 | |
2147 | /* Check whether a constant used to initialize a DImode or DFmode can | |
2148 | use a clr instruction. The code here must be kept in sync with | |
2149 | movdf and movdi. */ | |
2150 | ||
2151 | bool | |
f1777882 | 2152 | mn10300_wide_const_load_uses_clr (rtx operands[2]) |
fe7496dd | 2153 | { |
2720cc47 | 2154 | long val[2] = {0, 0}; |
fe7496dd AO |
2155 | |
2156 | if (GET_CODE (operands[0]) != REG | |
2157 | || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS) | |
2158 | return false; | |
2159 | ||
2160 | switch (GET_CODE (operands[1])) | |
2161 | { | |
2162 | case CONST_INT: | |
2163 | { | |
2164 | rtx low, high; | |
2165 | split_double (operands[1], &low, &high); | |
2166 | val[0] = INTVAL (low); | |
2167 | val[1] = INTVAL (high); | |
2168 | } | |
2169 | break; | |
5abc5de9 | 2170 | |
fe7496dd AO |
2171 | case CONST_DOUBLE: |
2172 | if (GET_MODE (operands[1]) == DFmode) | |
2173 | { | |
2174 | REAL_VALUE_TYPE rv; | |
2175 | ||
2176 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
2177 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
2178 | } | |
2179 | else if (GET_MODE (operands[1]) == VOIDmode | |
2180 | || GET_MODE (operands[1]) == DImode) | |
2181 | { | |
2182 | val[0] = CONST_DOUBLE_LOW (operands[1]); | |
2183 | val[1] = CONST_DOUBLE_HIGH (operands[1]); | |
2184 | } | |
2185 | break; | |
5abc5de9 | 2186 | |
fe7496dd AO |
2187 | default: |
2188 | return false; | |
2189 | } | |
2190 | ||
2191 | return val[0] == 0 || val[1] == 0; | |
2192 | } | |
d1776069 AO |
2193 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2194 | may access it using GOTOFF instead of GOT. */ | |
2195 | ||
2196 | static void | |
3bc5e4ef | 2197 | mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED) |
d1776069 AO |
2198 | { |
2199 | rtx symbol; | |
2200 | ||
2201 | if (GET_CODE (rtl) != MEM) | |
2202 | return; | |
2203 | symbol = XEXP (rtl, 0); | |
2204 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2205 | return; | |
2206 | ||
2207 | if (flag_pic) | |
2208 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2209 | } | |
e6ff3083 AS |
2210 | |
2211 | /* Dispatch tables on the mn10300 are extremely expensive in terms of code | |
2212 | and readonly data size. So we crank up the case threshold value to | |
2213 | encourage a series of if/else comparisons to implement many small switch | |
2214 | statements. In theory, this value could be increased much more if we | |
2215 | were solely optimizing for space, but we keep it "reasonable" to avoid | |
2216 | serious code efficiency lossage. */ | |
2217 | ||
2218 | unsigned int mn10300_case_values_threshold (void) | |
2219 | { | |
2220 | return 6; | |
2221 | } | |
bdeb5f0c RH |
2222 | |
2223 | /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE. */ | |
2224 | ||
2225 | static void | |
2226 | mn10300_asm_trampoline_template (FILE *f) | |
2227 | { | |
2228 | fprintf (f, "\tadd -4,sp\n"); | |
2229 | fprintf (f, "\t.long 0x0004fffa\n"); | |
2230 | fprintf (f, "\tmov (0,sp),a0\n"); | |
2231 | fprintf (f, "\tadd 4,sp\n"); | |
2232 | fprintf (f, "\tmov (13,a0),a1\n"); | |
2233 | fprintf (f, "\tmov (17,a0),a0\n"); | |
2234 | fprintf (f, "\tjmp (a0)\n"); | |
2235 | fprintf (f, "\t.long 0\n"); | |
2236 | fprintf (f, "\t.long 0\n"); | |
2237 | } | |
2238 | ||
2239 | /* Worker function for TARGET_TRAMPOLINE_INIT. */ | |
2240 | ||
2241 | static void | |
2242 | mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2243 | { | |
2244 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
2245 | rtx mem; | |
2246 | ||
2247 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
2248 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
2249 | ||
2250 | mem = adjust_address (m_tramp, SImode, 0x14); | |
2251 | emit_move_insn (mem, chain_value); | |
2252 | mem = adjust_address (m_tramp, SImode, 0x18); | |
2253 | emit_move_insn (mem, fnaddr); | |
2254 | } | |
990dc016 NC |
2255 | |
2256 | /* Output the assembler code for a C++ thunk function. | |
2257 | THUNK_DECL is the declaration for the thunk function itself, FUNCTION | |
2258 | is the decl for the target function. DELTA is an immediate constant | |
2259 | offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero | |
2260 | the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be | |
2261 | additionally added to THIS. Finally jump to the entry point of | |
2262 | FUNCTION. */ | |
2263 | ||
2264 | static void | |
2265 | mn10300_asm_output_mi_thunk (FILE * file, | |
2266 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2267 | HOST_WIDE_INT delta, | |
2268 | HOST_WIDE_INT vcall_offset, | |
2269 | tree function) | |
2270 | { | |
2271 | const char * _this; | |
2272 | ||
2273 | /* Get the register holding the THIS parameter. Handle the case | |
2274 | where there is a hidden first argument for a returned structure. */ | |
2275 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
2276 | _this = reg_names [FIRST_ARGUMENT_REGNUM + 1]; | |
2277 | else | |
2278 | _this = reg_names [FIRST_ARGUMENT_REGNUM]; | |
2279 | ||
2280 | fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START); | |
2281 | ||
2282 | if (delta) | |
2283 | fprintf (file, "\tadd %d, %s\n", (int) delta, _this); | |
2284 | ||
2285 | if (vcall_offset) | |
2286 | { | |
2287 | const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1]; | |
2288 | ||
2289 | fprintf (file, "\tmov %s, %s\n", _this, scratch); | |
2290 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2291 | fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch); | |
2292 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2293 | fprintf (file, "\tadd %s, %s\n", scratch, _this); | |
2294 | } | |
2295 | ||
2296 | fputs ("\tjmp ", file); | |
2297 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2298 | putc ('\n', file); | |
2299 | } | |
2300 | ||
2301 | /* Return true if mn10300_output_mi_thunk would be able to output the | |
2302 | assembler code for the thunk function specified by the arguments | |
2303 | it is passed, and false otherwise. */ | |
2304 | ||
2305 | static bool | |
2306 | mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2307 | HOST_WIDE_INT delta ATTRIBUTE_UNUSED, | |
2308 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2309 | const_tree function ATTRIBUTE_UNUSED) | |
2310 | { | |
2311 | return true; | |
2312 | } |