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11bb1f11 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
69bc71fa | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. |
11bb1f11 JL |
3 | Contributed by Jeff Law (law@cygnus.com). |
4 | ||
5 | This file is part of GNU CC. | |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
11bb1f11 | 22 | #include "config.h" |
c5c76735 | 23 | #include "system.h" |
11bb1f11 | 24 | #include "rtl.h" |
bf6bb899 | 25 | #include "tree.h" |
11bb1f11 JL |
26 | #include "regs.h" |
27 | #include "hard-reg-set.h" | |
28 | #include "real.h" | |
29 | #include "insn-config.h" | |
30 | #include "conditions.h" | |
31 | #include "insn-flags.h" | |
32 | #include "output.h" | |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
36 | #include "expr.h" | |
bf6bb899 | 37 | #include "function.h" |
11bb1f11 | 38 | #include "obstack.h" |
69bc71fa KG |
39 | #include "toplev.h" |
40 | #include "tm_p.h" | |
11bb1f11 | 41 | |
4d1a91c2 JL |
42 | /* The size of the callee register save area. Right now we save everything |
43 | on entry since it costs us nothing in code size. It does cost us from a | |
44 | speed standpoint, so we want to optimize this sooner or later. */ | |
980d0e81 JL |
45 | #define REG_SAVE_BYTES (4 * regs_ever_live[2] \ |
46 | + 4 * regs_ever_live[3] \ | |
705ac34f JL |
47 | + 4 * regs_ever_live[6] \ |
48 | + 4 * regs_ever_live[7] \ | |
49 | + 16 * (regs_ever_live[14] || regs_ever_live[15] \ | |
50 | || regs_ever_live[16] || regs_ever_live[17])) | |
4d1a91c2 | 51 | |
11bb1f11 JL |
52 | void |
53 | asm_file_start (file) | |
54 | FILE *file; | |
55 | { | |
56 | fprintf (file, "#\tGCC For the Matsushita MN10300\n"); | |
57 | if (optimize) | |
58 | fprintf (file, "# -O%d\n", optimize); | |
59 | else | |
60 | fprintf (file, "\n\n"); | |
705ac34f JL |
61 | |
62 | if (TARGET_AM33) | |
63 | fprintf (file, "\t.am33\n"); | |
11bb1f11 JL |
64 | output_file_directive (file, main_input_filename); |
65 | } | |
66 | \f | |
67 | ||
11bb1f11 JL |
68 | /* Print operand X using operand code CODE to assembly language output file |
69 | FILE. */ | |
70 | ||
71 | void | |
72 | print_operand (file, x, code) | |
73 | FILE *file; | |
74 | rtx x; | |
75 | int code; | |
76 | { | |
77 | switch (code) | |
78 | { | |
79 | case 'b': | |
80 | case 'B': | |
81 | /* These are normal and reversed branches. */ | |
82 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
83 | { | |
84 | case NE: | |
85 | fprintf (file, "ne"); | |
86 | break; | |
87 | case EQ: | |
88 | fprintf (file, "eq"); | |
89 | break; | |
90 | case GE: | |
91 | fprintf (file, "ge"); | |
92 | break; | |
93 | case GT: | |
94 | fprintf (file, "gt"); | |
95 | break; | |
96 | case LE: | |
97 | fprintf (file, "le"); | |
98 | break; | |
99 | case LT: | |
100 | fprintf (file, "lt"); | |
101 | break; | |
102 | case GEU: | |
103 | fprintf (file, "cc"); | |
104 | break; | |
105 | case GTU: | |
106 | fprintf (file, "hi"); | |
107 | break; | |
108 | case LEU: | |
109 | fprintf (file, "ls"); | |
110 | break; | |
111 | case LTU: | |
112 | fprintf (file, "cs"); | |
113 | break; | |
114 | default: | |
115 | abort (); | |
116 | } | |
117 | break; | |
118 | case 'C': | |
119 | /* This is used for the operand to a call instruction; | |
120 | if it's a REG, enclose it in parens, else output | |
121 | the operand normally. */ | |
122 | if (GET_CODE (x) == REG) | |
123 | { | |
124 | fputc ('(', file); | |
125 | print_operand (file, x, 0); | |
126 | fputc (')', file); | |
127 | } | |
128 | else | |
129 | print_operand (file, x, 0); | |
130 | break; | |
131 | ||
38c37a0e JL |
132 | /* These are the least significant word in a 64bit value. */ |
133 | case 'L': | |
134 | switch (GET_CODE (x)) | |
135 | { | |
136 | case MEM: | |
137 | fputc ('(', file); | |
138 | output_address (XEXP (x, 0)); | |
139 | fputc (')', file); | |
140 | break; | |
141 | ||
142 | case REG: | |
143 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
144 | break; | |
145 | ||
146 | case SUBREG: | |
147 | fprintf (file, "%s", | |
148 | reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); | |
149 | break; | |
150 | ||
151 | case CONST_DOUBLE: | |
152 | { | |
153 | long val[2]; | |
154 | REAL_VALUE_TYPE rv; | |
155 | ||
156 | switch (GET_MODE (x)) | |
157 | { | |
158 | case DFmode: | |
159 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
160 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 161 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
162 | break;; |
163 | case SFmode: | |
164 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
165 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
cf31fafa | 166 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
167 | break;; |
168 | case VOIDmode: | |
169 | case DImode: | |
170 | print_operand_address (file, | |
171 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
172 | break; | |
69bc71fa KG |
173 | default: |
174 | break; | |
38c37a0e JL |
175 | } |
176 | break; | |
177 | } | |
178 | ||
179 | case CONST_INT: | |
180 | print_operand_address (file, x); | |
181 | break; | |
182 | ||
183 | default: | |
184 | abort (); | |
185 | } | |
186 | break; | |
187 | ||
188 | /* Similarly, but for the most significant word. */ | |
189 | case 'H': | |
190 | switch (GET_CODE (x)) | |
191 | { | |
192 | case MEM: | |
193 | fputc ('(', file); | |
194 | x = adj_offsettable_operand (x, 4); | |
195 | output_address (XEXP (x, 0)); | |
196 | fputc (')', file); | |
197 | break; | |
198 | ||
199 | case REG: | |
200 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
201 | break; | |
202 | ||
203 | case SUBREG: | |
204 | fprintf (file, "%s", | |
205 | reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)] + 1); | |
206 | break; | |
207 | ||
208 | case CONST_DOUBLE: | |
209 | { | |
210 | long val[2]; | |
211 | REAL_VALUE_TYPE rv; | |
212 | ||
213 | switch (GET_MODE (x)) | |
214 | { | |
215 | case DFmode: | |
216 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
217 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 218 | fprintf (file, "0x%lx", val[1]); |
38c37a0e JL |
219 | break;; |
220 | case SFmode: | |
221 | abort (); | |
222 | case VOIDmode: | |
223 | case DImode: | |
224 | print_operand_address (file, | |
225 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
226 | break; | |
69bc71fa KG |
227 | default: |
228 | break; | |
38c37a0e JL |
229 | } |
230 | break; | |
231 | } | |
232 | ||
233 | case CONST_INT: | |
234 | if (INTVAL (x) < 0) | |
235 | print_operand_address (file, GEN_INT (-1)); | |
236 | else | |
237 | print_operand_address (file, GEN_INT (0)); | |
238 | break; | |
239 | default: | |
240 | abort (); | |
241 | } | |
242 | break; | |
243 | ||
244 | case 'A': | |
245 | fputc ('(', file); | |
246 | if (GET_CODE (XEXP (x, 0)) == REG) | |
c5c76735 | 247 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0))); |
38c37a0e JL |
248 | else |
249 | output_address (XEXP (x, 0)); | |
250 | fputc (')', file); | |
251 | break; | |
252 | ||
6fafc523 JL |
253 | case 'N': |
254 | output_address (GEN_INT ((~INTVAL (x)) & 0xff)); | |
255 | break; | |
256 | ||
576e5acc JL |
257 | /* For shift counts. The hardware ignores the upper bits of |
258 | any immediate, but the assembler will flag an out of range | |
259 | shift count as an error. So we mask off the high bits | |
260 | of the immediate here. */ | |
261 | case 'S': | |
262 | if (GET_CODE (x) == CONST_INT) | |
263 | { | |
264 | fprintf (file, "%d", INTVAL (x) & 0x1f); | |
265 | break; | |
266 | } | |
267 | /* FALL THROUGH */ | |
268 | ||
11bb1f11 JL |
269 | default: |
270 | switch (GET_CODE (x)) | |
271 | { | |
272 | case MEM: | |
273 | fputc ('(', file); | |
274 | output_address (XEXP (x, 0)); | |
275 | fputc (')', file); | |
276 | break; | |
277 | ||
38c37a0e JL |
278 | case PLUS: |
279 | output_address (x); | |
280 | break; | |
281 | ||
11bb1f11 JL |
282 | case REG: |
283 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
284 | break; | |
285 | ||
286 | case SUBREG: | |
287 | fprintf (file, "%s", | |
288 | reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]); | |
289 | break; | |
290 | ||
38c37a0e JL |
291 | /* This will only be single precision.... */ |
292 | case CONST_DOUBLE: | |
293 | { | |
294 | unsigned long val; | |
295 | REAL_VALUE_TYPE rv; | |
296 | ||
297 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
298 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
cf31fafa | 299 | fprintf (file, "0x%lx", val); |
38c37a0e JL |
300 | break; |
301 | } | |
302 | ||
11bb1f11 JL |
303 | case CONST_INT: |
304 | case SYMBOL_REF: | |
305 | case CONST: | |
306 | case LABEL_REF: | |
307 | case CODE_LABEL: | |
308 | print_operand_address (file, x); | |
309 | break; | |
310 | default: | |
311 | abort (); | |
312 | } | |
313 | break; | |
314 | } | |
315 | } | |
316 | ||
317 | /* Output assembly language output for the address ADDR to FILE. */ | |
318 | ||
319 | void | |
320 | print_operand_address (file, addr) | |
321 | FILE *file; | |
322 | rtx addr; | |
323 | { | |
324 | switch (GET_CODE (addr)) | |
325 | { | |
705ac34f JL |
326 | case POST_INC: |
327 | print_operand_address (file, XEXP (addr, 0)); | |
328 | fputc ('+', file); | |
329 | break; | |
11bb1f11 | 330 | case REG: |
79e4122c | 331 | print_operand (file, addr, 0); |
11bb1f11 JL |
332 | break; |
333 | case PLUS: | |
334 | { | |
335 | rtx base, index; | |
336 | if (REG_P (XEXP (addr, 0)) | |
337 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
338 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
339 | else if (REG_P (XEXP (addr, 1)) | |
340 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
341 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
342 | else | |
343 | abort (); | |
344 | print_operand (file, index, 0); | |
345 | fputc (',', file); | |
346 | print_operand (file, base, 0);; | |
347 | break; | |
348 | } | |
349 | case SYMBOL_REF: | |
350 | output_addr_const (file, addr); | |
351 | break; | |
352 | default: | |
353 | output_addr_const (file, addr); | |
354 | break; | |
355 | } | |
356 | } | |
357 | ||
38c37a0e JL |
358 | int |
359 | can_use_return_insn () | |
360 | { | |
460f4b9d JL |
361 | /* size includes the fixed stack space needed for function calls. */ |
362 | int size = get_frame_size () + current_function_outgoing_args_size; | |
363 | ||
364 | /* And space for the return pointer. */ | |
365 | size += current_function_outgoing_args_size ? 4 : 0; | |
38c37a0e JL |
366 | |
367 | return (reload_completed | |
368 | && size == 0 | |
369 | && !regs_ever_live[2] | |
370 | && !regs_ever_live[3] | |
371 | && !regs_ever_live[6] | |
372 | && !regs_ever_live[7] | |
705ac34f JL |
373 | && !regs_ever_live[14] |
374 | && !regs_ever_live[15] | |
375 | && !regs_ever_live[16] | |
376 | && !regs_ever_live[17] | |
38c37a0e JL |
377 | && !frame_pointer_needed); |
378 | } | |
379 | ||
11bb1f11 JL |
380 | void |
381 | expand_prologue () | |
382 | { | |
036182e7 | 383 | HOST_WIDE_INT size; |
3dbc43d1 | 384 | |
3dbc43d1 | 385 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
386 | size = get_frame_size () + current_function_outgoing_args_size; |
387 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 388 | |
22ef4e9b JL |
389 | /* If this is an old-style varargs function, then its arguments |
390 | need to be flushed back to the stack. */ | |
391 | if (current_function_varargs) | |
392 | { | |
c5c76735 JL |
393 | emit_move_insn (gen_rtx_MEM (SImode, |
394 | plus_constant (stack_pointer_rtx, 4)), | |
395 | gen_rtx_REG (SImode, 0)); | |
396 | emit_move_insn (gen_rtx_MEM (SImode, | |
397 | plus_constant (stack_pointer_rtx, 8)), | |
398 | gen_rtx_REG (SImode, 1)); | |
22ef4e9b JL |
399 | } |
400 | ||
777fbf09 JL |
401 | /* And now store all the registers onto the stack with a |
402 | single two byte instruction. */ | |
403 | if (regs_ever_live[2] || regs_ever_live[3] | |
404 | || regs_ever_live[6] || regs_ever_live[7] | |
705ac34f JL |
405 | || regs_ever_live[14] || regs_ever_live[15] |
406 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 JL |
407 | || frame_pointer_needed) |
408 | emit_insn (gen_store_movm ()); | |
409 | ||
410 | /* Now put the frame pointer into the frame pointer register. */ | |
11bb1f11 | 411 | if (frame_pointer_needed) |
6e86170d | 412 | emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); |
11bb1f11 | 413 | |
777fbf09 | 414 | /* Allocate stack for this frame. */ |
11bb1f11 JL |
415 | if (size) |
416 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
417 | stack_pointer_rtx, | |
418 | GEN_INT (-size))); | |
419 | } | |
420 | ||
421 | void | |
422 | expand_epilogue () | |
423 | { | |
036182e7 | 424 | HOST_WIDE_INT size; |
3dbc43d1 | 425 | |
3dbc43d1 | 426 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
427 | size = get_frame_size () + current_function_outgoing_args_size; |
428 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 429 | |
5d29a95f JL |
430 | /* Maybe cut back the stack, except for the register save area. |
431 | ||
432 | If the frame pointer exists, then use the frame pointer to | |
433 | cut back the stack. | |
434 | ||
435 | If the stack size + register save area is more than 255 bytes, | |
436 | then the stack must be cut back here since the size + register | |
437 | save size is too big for a ret/retf instruction. | |
438 | ||
439 | Else leave it alone, it will be cut back as part of the | |
440 | ret/retf instruction, or there wasn't any stack to begin with. | |
441 | ||
442 | Under no circumstanes should the register save area be | |
443 | deallocated here, that would leave a window where an interrupt | |
444 | could occur and trash the register save area. */ | |
11bb1f11 JL |
445 | if (frame_pointer_needed) |
446 | { | |
11bb1f11 | 447 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
4246e0c5 JL |
448 | size = 0; |
449 | } | |
ed6089d6 | 450 | else if (size + REG_SAVE_BYTES > 255) |
4246e0c5 JL |
451 | { |
452 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
453 | stack_pointer_rtx, | |
454 | GEN_INT (size))); | |
455 | size = 0; | |
11bb1f11 | 456 | } |
11bb1f11 | 457 | |
ed6089d6 AO |
458 | /* Adjust the stack and restore callee-saved registers, if any. */ |
459 | if (size || regs_ever_live[2] || regs_ever_live[3] | |
777fbf09 | 460 | || regs_ever_live[6] || regs_ever_live[7] |
705ac34f JL |
461 | || regs_ever_live[14] || regs_ever_live[15] |
462 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 | 463 | || frame_pointer_needed) |
ed6089d6 AO |
464 | emit_jump_insn (gen_return_internal_regs |
465 | (GEN_INT (size + REG_SAVE_BYTES))); | |
777fbf09 | 466 | else |
ed6089d6 | 467 | emit_jump_insn (gen_return_internal ()); |
11bb1f11 JL |
468 | } |
469 | ||
470 | /* Update the condition code from the insn. */ | |
471 | ||
472 | void | |
473 | notice_update_cc (body, insn) | |
474 | rtx body; | |
475 | rtx insn; | |
476 | { | |
11bb1f11 JL |
477 | switch (get_attr_cc (insn)) |
478 | { | |
479 | case CC_NONE: | |
480 | /* Insn does not affect CC at all. */ | |
481 | break; | |
482 | ||
483 | case CC_NONE_0HIT: | |
484 | /* Insn does not change CC, but the 0'th operand has been changed. */ | |
485 | if (cc_status.value1 != 0 | |
1ccbefce | 486 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
11bb1f11 JL |
487 | cc_status.value1 = 0; |
488 | break; | |
489 | ||
d116300b | 490 | case CC_SET_ZN: |
1ccbefce | 491 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
d116300b | 492 | V,C are unusable. */ |
11bb1f11 | 493 | CC_STATUS_INIT; |
d116300b | 494 | cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; |
1ccbefce | 495 | cc_status.value1 = recog_data.operand[0]; |
11bb1f11 JL |
496 | break; |
497 | ||
d116300b | 498 | case CC_SET_ZNV: |
1ccbefce | 499 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
d116300b | 500 | C is unusable. */ |
82c6faa8 | 501 | CC_STATUS_INIT; |
d116300b | 502 | cc_status.flags |= CC_NO_CARRY; |
1ccbefce | 503 | cc_status.value1 = recog_data.operand[0]; |
82c6faa8 JL |
504 | break; |
505 | ||
11bb1f11 JL |
506 | case CC_COMPARE: |
507 | /* The insn is a compare instruction. */ | |
508 | CC_STATUS_INIT; | |
509 | cc_status.value1 = SET_SRC (body); | |
510 | break; | |
511 | ||
3b800f71 JL |
512 | case CC_INVERT: |
513 | /* The insn is a compare instruction. */ | |
514 | CC_STATUS_INIT; | |
515 | cc_status.value1 = SET_SRC (body); | |
516 | cc_status.flags |= CC_INVERTED; | |
517 | break; | |
518 | ||
11bb1f11 JL |
519 | case CC_CLOBBER: |
520 | /* Insn doesn't leave CC in a usable state. */ | |
521 | CC_STATUS_INIT; | |
522 | break; | |
82c6faa8 JL |
523 | |
524 | default: | |
525 | abort (); | |
11bb1f11 | 526 | } |
11bb1f11 JL |
527 | } |
528 | ||
529 | /* Return true if OP is a valid call operand. */ | |
530 | ||
531 | int | |
532 | call_address_operand (op, mode) | |
533 | rtx op; | |
69bc71fa | 534 | enum machine_mode mode ATTRIBUTE_UNUSED; |
11bb1f11 JL |
535 | { |
536 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG); | |
537 | } | |
538 | ||
539 | /* What (if any) secondary registers are needed to move IN with mode | |
8493cfcb | 540 | MODE into a register in register class CLASS. |
11bb1f11 JL |
541 | |
542 | We might be able to simplify this. */ | |
543 | enum reg_class | |
544 | secondary_reload_class (class, mode, in) | |
545 | enum reg_class class; | |
546 | enum machine_mode mode; | |
547 | rtx in; | |
548 | { | |
11bb1f11 JL |
549 | /* Memory loads less than a full word wide can't have an |
550 | address or stack pointer destination. They must use | |
551 | a data register as an intermediate register. */ | |
552 | if (GET_CODE (in) == MEM | |
553 | && (mode == QImode || mode == HImode) | |
554 | && (class == ADDRESS_REGS || class == SP_REGS)) | |
4d1a91c2 | 555 | { |
705ac34f JL |
556 | if (TARGET_AM33) |
557 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
558 | return DATA_REGS; |
559 | } | |
11bb1f11 JL |
560 | |
561 | /* We can't directly load sp + const_int into a data register; | |
562 | we must use an address register as an intermediate. */ | |
777fbf09 JL |
563 | if (class != SP_REGS |
564 | && class != ADDRESS_REGS | |
565 | && class != SP_OR_ADDRESS_REGS | |
705ac34f JL |
566 | && class != SP_OR_EXTENDED_REGS |
567 | && class != ADDRESS_OR_EXTENDED_REGS | |
568 | && class != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
11bb1f11 JL |
569 | && (in == stack_pointer_rtx |
570 | || (GET_CODE (in) == PLUS | |
777fbf09 JL |
571 | && (XEXP (in, 0) == stack_pointer_rtx |
572 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
11bb1f11 JL |
573 | return ADDRESS_REGS; |
574 | ||
4c742813 JL |
575 | if (GET_CODE (in) == PLUS |
576 | && (XEXP (in, 0) == stack_pointer_rtx | |
577 | || XEXP (in, 1) == stack_pointer_rtx)) | |
4d1a91c2 | 578 | { |
705ac34f JL |
579 | if (TARGET_AM33) |
580 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
581 | return DATA_REGS; |
582 | } | |
4c742813 | 583 | |
777fbf09 JL |
584 | /* Otherwise assume no secondary reloads are needed. */ |
585 | return NO_REGS; | |
586 | } | |
587 | ||
588 | int | |
589 | initial_offset (from, to) | |
590 | int from, to; | |
591 | { | |
3dbc43d1 JL |
592 | /* The difference between the argument pointer and the frame pointer |
593 | is the size of the callee register save area. */ | |
777fbf09 | 594 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
11bb1f11 | 595 | { |
777fbf09 JL |
596 | if (regs_ever_live[2] || regs_ever_live[3] |
597 | || regs_ever_live[6] || regs_ever_live[7] | |
705ac34f JL |
598 | || regs_ever_live[14] || regs_ever_live[15] |
599 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 | 600 | || frame_pointer_needed) |
4d1a91c2 | 601 | return REG_SAVE_BYTES; |
777fbf09 | 602 | else |
22ef4e9b | 603 | return 0; |
11bb1f11 JL |
604 | } |
605 | ||
3dbc43d1 JL |
606 | /* The difference between the argument pointer and the stack pointer is |
607 | the sum of the size of this function's frame, the callee register save | |
608 | area, and the fixed stack space needed for function calls (if any). */ | |
777fbf09 JL |
609 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
610 | { | |
611 | if (regs_ever_live[2] || regs_ever_live[3] | |
612 | || regs_ever_live[6] || regs_ever_live[7] | |
705ac34f JL |
613 | || regs_ever_live[14] || regs_ever_live[15] |
614 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 | 615 | || frame_pointer_needed) |
4d1a91c2 | 616 | return (get_frame_size () + REG_SAVE_BYTES |
460f4b9d JL |
617 | + (current_function_outgoing_args_size |
618 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 | 619 | else |
460f4b9d JL |
620 | return (get_frame_size () |
621 | + (current_function_outgoing_args_size | |
622 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 | 623 | } |
11bb1f11 | 624 | |
3dbc43d1 JL |
625 | /* The difference between the frame pointer and stack pointer is the sum |
626 | of the size of this function's frame and the fixed stack space needed | |
627 | for function calls (if any). */ | |
777fbf09 | 628 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
460f4b9d JL |
629 | return (get_frame_size () |
630 | + (current_function_outgoing_args_size | |
631 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 JL |
632 | |
633 | abort (); | |
11bb1f11 | 634 | } |
22ef4e9b JL |
635 | |
636 | /* Flush the argument registers to the stack for a stdarg function; | |
637 | return the new argument pointer. */ | |
638 | rtx | |
648d2ffc | 639 | mn10300_builtin_saveregs () |
22ef4e9b | 640 | { |
fc2acc87 | 641 | rtx offset, mem; |
22ef4e9b JL |
642 | tree fntype = TREE_TYPE (current_function_decl); |
643 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
644 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
645 | != void_type_node))) | |
646 | ? UNITS_PER_WORD : 0); | |
fc2acc87 | 647 | int set = get_varargs_alias_set (); |
22ef4e9b JL |
648 | |
649 | if (argadj) | |
650 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
651 | else | |
652 | offset = current_function_arg_offset_rtx; | |
653 | ||
fc2acc87 RH |
654 | mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer); |
655 | MEM_ALIAS_SET (mem) = set; | |
656 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); | |
657 | ||
658 | mem = gen_rtx_MEM (SImode, | |
659 | plus_constant (current_function_internal_arg_pointer, 4)); | |
660 | MEM_ALIAS_SET (mem) = set; | |
661 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); | |
662 | ||
22ef4e9b JL |
663 | return copy_to_reg (expand_binop (Pmode, add_optab, |
664 | current_function_internal_arg_pointer, | |
665 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
666 | } | |
667 | ||
fc2acc87 RH |
668 | void |
669 | mn10300_va_start (stdarg_p, valist, nextarg) | |
670 | int stdarg_p; | |
671 | tree valist; | |
672 | rtx nextarg; | |
673 | { | |
674 | if (stdarg_p) | |
675 | nextarg = expand_builtin_saveregs (); | |
676 | ||
677 | std_expand_builtin_va_start (stdarg_p, valist, nextarg); | |
678 | } | |
679 | ||
680 | rtx | |
681 | mn10300_va_arg (valist, type) | |
682 | tree valist, type; | |
683 | { | |
684 | HOST_WIDE_INT align, rsize; | |
685 | tree t, ptr, pptr; | |
686 | ||
687 | /* Compute the rounded size of the type. */ | |
688 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
689 | rsize = (((int_size_in_bytes (type) + align - 1) / align) * align); | |
690 | ||
691 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
692 | build_int_2 ((rsize > 8 ? 4 : rsize), 0)); | |
693 | TREE_SIDE_EFFECTS (t) = 1; | |
694 | ||
695 | ptr = build_pointer_type (type); | |
696 | ||
697 | /* "Large" types are passed by reference. */ | |
698 | if (rsize > 8) | |
699 | { | |
700 | pptr = build_pointer_type (ptr); | |
701 | t = build1 (NOP_EXPR, pptr, t); | |
702 | TREE_SIDE_EFFECTS (t) = 1; | |
703 | ||
704 | t = build1 (INDIRECT_REF, ptr, t); | |
705 | TREE_SIDE_EFFECTS (t) = 1; | |
706 | } | |
707 | else | |
708 | { | |
709 | t = build1 (NOP_EXPR, ptr, t); | |
710 | TREE_SIDE_EFFECTS (t) = 1; | |
711 | } | |
712 | ||
713 | /* Calculate! */ | |
714 | return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL); | |
715 | } | |
716 | ||
22ef4e9b JL |
717 | /* Return an RTX to represent where a value with mode MODE will be returned |
718 | from a function. If the result is 0, the argument is pushed. */ | |
719 | ||
720 | rtx | |
721 | function_arg (cum, mode, type, named) | |
722 | CUMULATIVE_ARGS *cum; | |
723 | enum machine_mode mode; | |
724 | tree type; | |
69bc71fa | 725 | int named ATTRIBUTE_UNUSED; |
22ef4e9b JL |
726 | { |
727 | rtx result = 0; | |
728 | int size, align; | |
729 | ||
730 | /* We only support using 2 data registers as argument registers. */ | |
731 | int nregs = 2; | |
732 | ||
733 | /* Figure out the size of the object to be passed. */ | |
734 | if (mode == BLKmode) | |
735 | size = int_size_in_bytes (type); | |
736 | else | |
737 | size = GET_MODE_SIZE (mode); | |
738 | ||
739 | /* Figure out the alignment of the object to be passed. */ | |
740 | align = size; | |
741 | ||
742 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
743 | ||
744 | /* Don't pass this arg via a register if all the argument registers | |
745 | are used up. */ | |
746 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
747 | return 0; | |
748 | ||
749 | /* Don't pass this arg via a register if it would be split between | |
750 | registers and memory. */ | |
751 | if (type == NULL_TREE | |
752 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
753 | return 0; | |
754 | ||
755 | switch (cum->nbytes / UNITS_PER_WORD) | |
756 | { | |
757 | case 0: | |
c5c76735 | 758 | result = gen_rtx_REG (mode, 0); |
22ef4e9b JL |
759 | break; |
760 | case 1: | |
c5c76735 | 761 | result = gen_rtx_REG (mode, 1); |
22ef4e9b JL |
762 | break; |
763 | default: | |
764 | result = 0; | |
765 | } | |
766 | ||
767 | return result; | |
768 | } | |
769 | ||
770 | /* Return the number of registers to use for an argument passed partially | |
771 | in registers and partially in memory. */ | |
772 | ||
773 | int | |
774 | function_arg_partial_nregs (cum, mode, type, named) | |
775 | CUMULATIVE_ARGS *cum; | |
776 | enum machine_mode mode; | |
777 | tree type; | |
69bc71fa | 778 | int named ATTRIBUTE_UNUSED; |
22ef4e9b JL |
779 | { |
780 | int size, align; | |
781 | ||
782 | /* We only support using 2 data registers as argument registers. */ | |
783 | int nregs = 2; | |
784 | ||
785 | /* Figure out the size of the object to be passed. */ | |
786 | if (mode == BLKmode) | |
787 | size = int_size_in_bytes (type); | |
788 | else | |
789 | size = GET_MODE_SIZE (mode); | |
790 | ||
791 | /* Figure out the alignment of the object to be passed. */ | |
792 | align = size; | |
793 | ||
794 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
795 | ||
796 | /* Don't pass this arg via a register if all the argument registers | |
797 | are used up. */ | |
798 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
799 | return 0; | |
800 | ||
801 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
802 | return 0; | |
803 | ||
804 | /* Don't pass this arg via a register if it would be split between | |
805 | registers and memory. */ | |
806 | if (type == NULL_TREE | |
807 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
808 | return 0; | |
809 | ||
810 | return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD; | |
811 | } | |
812 | ||
813 | /* Output a tst insn. */ | |
814 | char * | |
815 | output_tst (operand, insn) | |
816 | rtx operand, insn; | |
817 | { | |
22ef4e9b JL |
818 | rtx temp; |
819 | int past_call = 0; | |
820 | ||
821 | /* We can save a byte if we can find a register which has the value | |
822 | zero in it. */ | |
823 | temp = PREV_INSN (insn); | |
74452ac3 | 824 | while (optimize && temp) |
22ef4e9b JL |
825 | { |
826 | rtx set; | |
827 | ||
828 | /* We allow the search to go through call insns. We record | |
829 | the fact that we've past a CALL_INSN and reject matches which | |
830 | use call clobbered registers. */ | |
831 | if (GET_CODE (temp) == CODE_LABEL | |
832 | || GET_CODE (temp) == JUMP_INSN | |
833 | || GET_CODE (temp) == BARRIER) | |
834 | break; | |
835 | ||
836 | if (GET_CODE (temp) == CALL_INSN) | |
837 | past_call = 1; | |
838 | ||
839 | if (GET_CODE (temp) == NOTE) | |
840 | { | |
841 | temp = PREV_INSN (temp); | |
842 | continue; | |
843 | } | |
844 | ||
845 | /* It must be an insn, see if it is a simple set. */ | |
846 | set = single_set (temp); | |
847 | if (!set) | |
848 | { | |
849 | temp = PREV_INSN (temp); | |
850 | continue; | |
851 | } | |
852 | ||
853 | /* Are we setting a data register to zero (this does not win for | |
854 | address registers)? | |
855 | ||
856 | If it's a call clobbered register, have we past a call? | |
857 | ||
858 | Make sure the register we find isn't the same as ourself; | |
4d1a91c2 JL |
859 | the mn10300 can't encode that. |
860 | ||
861 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
862 | so the code to detect calls here isn't doing anything useful. */ | |
22ef4e9b JL |
863 | if (REG_P (SET_DEST (set)) |
864 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
865 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
74452ac3 JL |
866 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
867 | == REGNO_REG_CLASS (REGNO (operand))) | |
705ac34f JL |
868 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
869 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
870 | && (!past_call | |
871 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
872 | { | |
873 | rtx xoperands[2]; | |
874 | xoperands[0] = operand; | |
875 | xoperands[1] = SET_DEST (set); | |
876 | ||
877 | output_asm_insn ("cmp %1,%0", xoperands); | |
878 | return ""; | |
879 | } | |
880 | ||
881 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
882 | && REG_P (SET_DEST (set)) | |
883 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
884 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
885 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
886 | != REGNO_REG_CLASS (REGNO (operand))) | |
887 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
22ef4e9b JL |
888 | && REGNO (SET_DEST (set)) != REGNO (operand) |
889 | && (!past_call | |
890 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
891 | { | |
892 | rtx xoperands[2]; | |
893 | xoperands[0] = operand; | |
894 | xoperands[1] = SET_DEST (set); | |
895 | ||
896 | output_asm_insn ("cmp %1,%0", xoperands); | |
897 | return ""; | |
898 | } | |
899 | temp = PREV_INSN (temp); | |
900 | } | |
901 | return "cmp 0,%0"; | |
902 | } | |
460f4b9d JL |
903 | |
904 | int | |
905 | impossible_plus_operand (op, mode) | |
906 | rtx op; | |
69bc71fa | 907 | enum machine_mode mode ATTRIBUTE_UNUSED; |
460f4b9d | 908 | { |
460f4b9d JL |
909 | if (GET_CODE (op) != PLUS) |
910 | return 0; | |
911 | ||
4c742813 JL |
912 | if (XEXP (op, 0) == stack_pointer_rtx |
913 | || XEXP (op, 1) == stack_pointer_rtx) | |
460f4b9d JL |
914 | return 1; |
915 | ||
460f4b9d JL |
916 | return 0; |
917 | } | |
e9ad4573 | 918 | |
f8912297 JL |
919 | /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used |
920 | for the btst insn which may examine memory or a register (the memory | |
921 | variant only allows an unsigned 8 bit integer). */ | |
922 | int | |
923 | const_8bit_operand (op, mode) | |
924 | register rtx op; | |
69bc71fa | 925 | enum machine_mode mode ATTRIBUTE_UNUSED; |
f8912297 JL |
926 | { |
927 | return (GET_CODE (op) == CONST_INT | |
928 | && INTVAL (op) >= 0 | |
929 | && INTVAL (op) < 256); | |
930 | } | |
931 | ||
932 | /* Similarly, but when using a zero_extract pattern for a btst where | |
933 | the source operand might end up in memory. */ | |
934 | int | |
935 | mask_ok_for_mem_btst (len, bit) | |
936 | int len; | |
937 | int bit; | |
938 | { | |
939 | int mask = 0; | |
940 | ||
941 | while (len > 0) | |
942 | { | |
943 | mask |= (1 << bit); | |
944 | bit++; | |
945 | len--; | |
946 | } | |
947 | ||
948 | /* MASK must bit into an 8bit value. */ | |
949 | return (((mask & 0xff) == mask) | |
950 | || ((mask & 0xff00) == mask) | |
951 | || ((mask & 0xff0000) == mask) | |
952 | || ((mask & 0xff000000) == mask)); | |
953 | } | |
954 | ||
e9ad4573 JL |
955 | /* Return 1 if X contains a symbolic expression. We know these |
956 | expressions will have one of a few well defined forms, so | |
957 | we need only check those forms. */ | |
958 | int | |
959 | symbolic_operand (op, mode) | |
960 | register rtx op; | |
69bc71fa | 961 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e9ad4573 JL |
962 | { |
963 | switch (GET_CODE (op)) | |
964 | { | |
965 | case SYMBOL_REF: | |
966 | case LABEL_REF: | |
967 | return 1; | |
968 | case CONST: | |
969 | op = XEXP (op, 0); | |
970 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
971 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
972 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
973 | default: | |
974 | return 0; | |
975 | } | |
976 | } | |
977 | ||
978 | /* Try machine dependent ways of modifying an illegitimate address | |
979 | to be legitimate. If we find one, return the new valid address. | |
980 | This macro is used in only one place: `memory_address' in explow.c. | |
981 | ||
982 | OLDX is the address as it was before break_out_memory_refs was called. | |
983 | In some cases it is useful to look at this to decide what needs to be done. | |
984 | ||
985 | MODE and WIN are passed so that this macro can use | |
986 | GO_IF_LEGITIMATE_ADDRESS. | |
987 | ||
988 | Normally it is always safe for this macro to do nothing. It exists to | |
989 | recognize opportunities to optimize the output. | |
990 | ||
991 | But on a few ports with segmented architectures and indexed addressing | |
992 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
993 | rtx | |
994 | legitimize_address (x, oldx, mode) | |
995 | rtx x; | |
69bc71fa KG |
996 | rtx oldx ATTRIBUTE_UNUSED; |
997 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
e9ad4573 JL |
998 | { |
999 | /* Uh-oh. We might have an address for x[n-100000]. This needs | |
1000 | special handling to avoid creating an indexed memory address | |
1001 | with x-100000 as the base. */ | |
1002 | if (GET_CODE (x) == PLUS | |
1003 | && symbolic_operand (XEXP (x, 1), VOIDmode)) | |
1004 | { | |
1005 | /* Ugly. We modify things here so that the address offset specified | |
1006 | by the index expression is computed first, then added to x to form | |
1007 | the entire address. */ | |
1008 | ||
69bc71fa | 1009 | rtx regx1, regy1, regy2, y; |
e9ad4573 JL |
1010 | |
1011 | /* Strip off any CONST. */ | |
1012 | y = XEXP (x, 1); | |
1013 | if (GET_CODE (y) == CONST) | |
1014 | y = XEXP (y, 0); | |
1015 | ||
bf4219f0 JL |
1016 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1017 | { | |
1018 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1019 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1020 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1021 | regx1 = force_reg (Pmode, | |
1022 | gen_rtx (GET_CODE (y), Pmode, regx1, regy2)); | |
c5c76735 | 1023 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
bf4219f0 | 1024 | } |
e9ad4573 | 1025 | } |
371036e0 | 1026 | return x; |
e9ad4573 | 1027 | } |
460ad325 AO |
1028 | |
1029 | int | |
1030 | mn10300_address_cost (x, unsig) | |
1031 | rtx x; | |
1032 | int *unsig; | |
1033 | { | |
1034 | int _s = 0; | |
1035 | if (unsig == 0) | |
1036 | unsig = &_s; | |
1037 | ||
1038 | switch (GET_CODE (x)) | |
1039 | { | |
1040 | case REG: | |
1041 | switch (REGNO_REG_CLASS (REGNO (x))) | |
1042 | { | |
1043 | case SP_REGS: | |
1044 | *unsig = 1; | |
1045 | return 0; | |
1046 | ||
1047 | case ADDRESS_REGS: | |
1048 | return 1; | |
1049 | ||
1050 | case DATA_REGS: | |
1051 | case EXTENDED_REGS: | |
1052 | return 3; | |
1053 | ||
1054 | case NO_REGS: | |
1055 | return 5; | |
1056 | ||
1057 | default: | |
1058 | abort (); | |
1059 | } | |
1060 | ||
1061 | case PLUS: | |
1062 | case MINUS: | |
d82704fb AO |
1063 | case ASHIFT: |
1064 | case AND: | |
460ad325 AO |
1065 | case IOR: |
1066 | return (mn10300_address_cost (XEXP (x, 0), unsig) | |
1067 | + mn10300_address_cost (XEXP (x, 1), unsig)); | |
1068 | ||
1069 | case EXPR_LIST: | |
1070 | case SUBREG: | |
1071 | case MEM: | |
1072 | return ADDRESS_COST (XEXP (x, 0)); | |
1073 | ||
1074 | case ZERO_EXTEND: | |
1075 | *unsig = 1; | |
1076 | return mn10300_address_cost (XEXP (x, 0), unsig); | |
1077 | ||
1078 | case CONST_INT: | |
1079 | if (INTVAL (x) == 0) | |
1080 | return 0; | |
1081 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
1082 | return 1; | |
1083 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
1084 | return 3; | |
1085 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
1086 | return 5; | |
1087 | return 7; | |
1088 | ||
1089 | case CONST: | |
1090 | case SYMBOL_REF: | |
d82704fb | 1091 | case LABEL_REF: |
460ad325 AO |
1092 | return 8; |
1093 | ||
1094 | case ADDRESSOF: | |
1095 | switch (GET_CODE (XEXP (x, 0))) | |
1096 | { | |
1097 | case MEM: | |
1098 | return ADDRESS_COST (XEXP (x, 0)); | |
1099 | ||
1100 | case REG: | |
1101 | return 1; | |
1102 | ||
1103 | default: | |
1104 | abort (); | |
1105 | } | |
1106 | ||
1107 | default: | |
1108 | abort (); | |
1109 | ||
1110 | } | |
1111 | } |