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Commit | Line | Data |
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11bb1f11 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
9024ea92 | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 |
92547f12 | 3 | Free Software Foundation, Inc. |
11bb1f11 JL |
4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
7ec022b2 | 6 | This file is part of GCC. |
11bb1f11 | 7 | |
7ec022b2 | 8 | GCC is free software; you can redistribute it and/or modify |
11bb1f11 JL |
9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
7ec022b2 | 13 | GCC is distributed in the hope that it will be useful, |
11bb1f11 JL |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
7ec022b2 | 19 | along with GCC; see the file COPYING. If not, write to |
11bb1f11 JL |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
11bb1f11 | 23 | #include "config.h" |
c5c76735 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
11bb1f11 | 27 | #include "rtl.h" |
bf6bb899 | 28 | #include "tree.h" |
11bb1f11 JL |
29 | #include "regs.h" |
30 | #include "hard-reg-set.h" | |
31 | #include "real.h" | |
32 | #include "insn-config.h" | |
33 | #include "conditions.h" | |
11bb1f11 JL |
34 | #include "output.h" |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "recog.h" | |
38 | #include "expr.h" | |
e78d8e51 | 39 | #include "optabs.h" |
bf6bb899 | 40 | #include "function.h" |
11bb1f11 | 41 | #include "obstack.h" |
69bc71fa KG |
42 | #include "toplev.h" |
43 | #include "tm_p.h" | |
672a6f42 NB |
44 | #include "target.h" |
45 | #include "target-def.h" | |
11bb1f11 | 46 | |
d1776069 AO |
47 | /* This is used by GOTaddr2picreg to uniquely identify |
48 | UNSPEC_INT_LABELs. */ | |
49 | int mn10300_unspec_int_label_counter; | |
50 | ||
2beef00e AO |
51 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
52 | names are not prefixed by underscores, to tell whether to prefix a | |
53 | label with a plus sign or not, so that the assembler can tell | |
54 | symbol names from register names. */ | |
55 | int mn10300_protect_label; | |
56 | ||
4d1a91c2 JL |
57 | /* The size of the callee register save area. Right now we save everything |
58 | on entry since it costs us nothing in code size. It does cost us from a | |
59 | speed standpoint, so we want to optimize this sooner or later. */ | |
980d0e81 JL |
60 | #define REG_SAVE_BYTES (4 * regs_ever_live[2] \ |
61 | + 4 * regs_ever_live[3] \ | |
705ac34f JL |
62 | + 4 * regs_ever_live[6] \ |
63 | + 4 * regs_ever_live[7] \ | |
64 | + 16 * (regs_ever_live[14] || regs_ever_live[15] \ | |
65 | || regs_ever_live[16] || regs_ever_live[17])) | |
3c50106f RH |
66 | |
67 | ||
7f682641 SB |
68 | static int mn10300_address_cost_1 (rtx, int *); |
69 | static int mn10300_address_cost (rtx); | |
70 | static bool mn10300_rtx_costs (rtx, int, int, int *); | |
71 | static void mn10300_file_start (void); | |
9024ea92 KH |
72 | static bool mn10300_return_in_memory (tree, tree); |
73 | static rtx mn10300_builtin_saveregs (void); | |
3c50106f | 74 | |
672a6f42 NB |
75 | \f |
76 | /* Initialize the GCC target structure. */ | |
301d03af RS |
77 | #undef TARGET_ASM_ALIGNED_HI_OP |
78 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
4d1a91c2 | 79 | |
3c50106f RH |
80 | #undef TARGET_RTX_COSTS |
81 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
dcefdf67 RH |
82 | #undef TARGET_ADDRESS_COST |
83 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
3c50106f | 84 | |
1bc7c5b6 ZW |
85 | #undef TARGET_ASM_FILE_START |
86 | #define TARGET_ASM_FILE_START mn10300_file_start | |
87 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
88 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
89 | ||
d1776069 AO |
90 | #undef TARGET_ENCODE_SECTION_INFO |
91 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
92 | ||
9024ea92 KH |
93 | #undef TARGET_PROMOTE_PROTOTYPES |
94 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
95 | ||
96 | #undef TARGET_STRUCT_VALUE_RTX | |
97 | #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null | |
98 | #undef TARGET_RETURN_IN_MEMORY | |
99 | #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory | |
100 | ||
101 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
102 | #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs | |
103 | ||
d1776069 | 104 | static void mn10300_encode_section_info (tree, rtx, int); |
f6897b10 | 105 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 106 | \f |
1bc7c5b6 | 107 | static void |
f1777882 | 108 | mn10300_file_start (void) |
11bb1f11 | 109 | { |
1bc7c5b6 | 110 | default_file_start (); |
705ac34f | 111 | |
18e9d2f9 AO |
112 | if (TARGET_AM33_2) |
113 | fprintf (asm_out_file, "\t.am33_2\n"); | |
114 | else if (TARGET_AM33) | |
1bc7c5b6 | 115 | fprintf (asm_out_file, "\t.am33\n"); |
11bb1f11 JL |
116 | } |
117 | \f | |
118 | ||
11bb1f11 JL |
119 | /* Print operand X using operand code CODE to assembly language output file |
120 | FILE. */ | |
121 | ||
122 | void | |
f1777882 | 123 | print_operand (FILE *file, rtx x, int code) |
11bb1f11 JL |
124 | { |
125 | switch (code) | |
126 | { | |
127 | case 'b': | |
128 | case 'B': | |
18e9d2f9 AO |
129 | if (cc_status.mdep.fpCC) |
130 | { | |
131 | switch (code == 'b' ? GET_CODE (x) | |
132 | : reverse_condition_maybe_unordered (GET_CODE (x))) | |
133 | { | |
134 | case NE: | |
135 | fprintf (file, "ne"); | |
136 | break; | |
137 | case EQ: | |
138 | fprintf (file, "eq"); | |
139 | break; | |
140 | case GE: | |
141 | fprintf (file, "ge"); | |
142 | break; | |
143 | case GT: | |
144 | fprintf (file, "gt"); | |
145 | break; | |
146 | case LE: | |
147 | fprintf (file, "le"); | |
148 | break; | |
149 | case LT: | |
150 | fprintf (file, "lt"); | |
151 | break; | |
152 | case ORDERED: | |
153 | fprintf (file, "lge"); | |
154 | break; | |
155 | case UNORDERED: | |
156 | fprintf (file, "uo"); | |
157 | break; | |
158 | case LTGT: | |
159 | fprintf (file, "lg"); | |
160 | break; | |
161 | case UNEQ: | |
162 | fprintf (file, "ue"); | |
163 | break; | |
164 | case UNGE: | |
165 | fprintf (file, "uge"); | |
166 | break; | |
167 | case UNGT: | |
168 | fprintf (file, "ug"); | |
169 | break; | |
170 | case UNLE: | |
171 | fprintf (file, "ule"); | |
172 | break; | |
173 | case UNLT: | |
174 | fprintf (file, "ul"); | |
175 | break; | |
176 | default: | |
177 | abort (); | |
178 | } | |
179 | break; | |
180 | } | |
11bb1f11 JL |
181 | /* These are normal and reversed branches. */ |
182 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
183 | { | |
184 | case NE: | |
185 | fprintf (file, "ne"); | |
186 | break; | |
187 | case EQ: | |
188 | fprintf (file, "eq"); | |
189 | break; | |
190 | case GE: | |
191 | fprintf (file, "ge"); | |
192 | break; | |
193 | case GT: | |
194 | fprintf (file, "gt"); | |
195 | break; | |
196 | case LE: | |
197 | fprintf (file, "le"); | |
198 | break; | |
199 | case LT: | |
200 | fprintf (file, "lt"); | |
201 | break; | |
202 | case GEU: | |
203 | fprintf (file, "cc"); | |
204 | break; | |
205 | case GTU: | |
206 | fprintf (file, "hi"); | |
207 | break; | |
208 | case LEU: | |
209 | fprintf (file, "ls"); | |
210 | break; | |
211 | case LTU: | |
212 | fprintf (file, "cs"); | |
213 | break; | |
214 | default: | |
215 | abort (); | |
216 | } | |
217 | break; | |
218 | case 'C': | |
219 | /* This is used for the operand to a call instruction; | |
220 | if it's a REG, enclose it in parens, else output | |
221 | the operand normally. */ | |
222 | if (GET_CODE (x) == REG) | |
223 | { | |
224 | fputc ('(', file); | |
225 | print_operand (file, x, 0); | |
226 | fputc (')', file); | |
227 | } | |
228 | else | |
229 | print_operand (file, x, 0); | |
230 | break; | |
231 | ||
18e9d2f9 AO |
232 | case 'D': |
233 | switch (GET_CODE (x)) | |
234 | { | |
235 | case MEM: | |
236 | fputc ('(', file); | |
237 | output_address (XEXP (x, 0)); | |
238 | fputc (')', file); | |
239 | break; | |
240 | ||
241 | case REG: | |
242 | fprintf (file, "fd%d", REGNO (x) - 18); | |
243 | break; | |
244 | ||
245 | default: | |
246 | abort (); | |
247 | } | |
248 | break; | |
249 | ||
38c37a0e JL |
250 | /* These are the least significant word in a 64bit value. */ |
251 | case 'L': | |
252 | switch (GET_CODE (x)) | |
253 | { | |
254 | case MEM: | |
255 | fputc ('(', file); | |
256 | output_address (XEXP (x, 0)); | |
257 | fputc (')', file); | |
258 | break; | |
259 | ||
260 | case REG: | |
261 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
262 | break; | |
263 | ||
264 | case SUBREG: | |
ddef6bc7 | 265 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
38c37a0e JL |
266 | break; |
267 | ||
268 | case CONST_DOUBLE: | |
269 | { | |
270 | long val[2]; | |
271 | REAL_VALUE_TYPE rv; | |
272 | ||
273 | switch (GET_MODE (x)) | |
274 | { | |
275 | case DFmode: | |
276 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
277 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 278 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
279 | break;; |
280 | case SFmode: | |
281 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
282 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
cf31fafa | 283 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
284 | break;; |
285 | case VOIDmode: | |
286 | case DImode: | |
287 | print_operand_address (file, | |
288 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
289 | break; | |
69bc71fa KG |
290 | default: |
291 | break; | |
38c37a0e JL |
292 | } |
293 | break; | |
294 | } | |
295 | ||
296 | case CONST_INT: | |
212bc5fa AO |
297 | { |
298 | rtx low, high; | |
299 | split_double (x, &low, &high); | |
300 | fprintf (file, "%ld", (long)INTVAL (low)); | |
301 | break; | |
302 | } | |
38c37a0e JL |
303 | |
304 | default: | |
305 | abort (); | |
306 | } | |
307 | break; | |
308 | ||
309 | /* Similarly, but for the most significant word. */ | |
310 | case 'H': | |
311 | switch (GET_CODE (x)) | |
312 | { | |
313 | case MEM: | |
314 | fputc ('(', file); | |
b72f00af | 315 | x = adjust_address (x, SImode, 4); |
38c37a0e JL |
316 | output_address (XEXP (x, 0)); |
317 | fputc (')', file); | |
318 | break; | |
319 | ||
320 | case REG: | |
321 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
322 | break; | |
323 | ||
324 | case SUBREG: | |
ddef6bc7 | 325 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
38c37a0e JL |
326 | break; |
327 | ||
328 | case CONST_DOUBLE: | |
329 | { | |
330 | long val[2]; | |
331 | REAL_VALUE_TYPE rv; | |
332 | ||
333 | switch (GET_MODE (x)) | |
334 | { | |
335 | case DFmode: | |
336 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
337 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 338 | fprintf (file, "0x%lx", val[1]); |
38c37a0e JL |
339 | break;; |
340 | case SFmode: | |
341 | abort (); | |
342 | case VOIDmode: | |
343 | case DImode: | |
344 | print_operand_address (file, | |
345 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
346 | break; | |
69bc71fa KG |
347 | default: |
348 | break; | |
38c37a0e JL |
349 | } |
350 | break; | |
351 | } | |
352 | ||
353 | case CONST_INT: | |
212bc5fa AO |
354 | { |
355 | rtx low, high; | |
356 | split_double (x, &low, &high); | |
357 | fprintf (file, "%ld", (long)INTVAL (high)); | |
358 | break; | |
359 | } | |
360 | ||
38c37a0e JL |
361 | default: |
362 | abort (); | |
363 | } | |
364 | break; | |
365 | ||
366 | case 'A': | |
367 | fputc ('(', file); | |
368 | if (GET_CODE (XEXP (x, 0)) == REG) | |
c5c76735 | 369 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0))); |
38c37a0e JL |
370 | else |
371 | output_address (XEXP (x, 0)); | |
372 | fputc (')', file); | |
373 | break; | |
374 | ||
6fafc523 | 375 | case 'N': |
a58be199 AO |
376 | if (INTVAL (x) < -128 || INTVAL (x) > 255) |
377 | abort (); | |
378 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); | |
379 | break; | |
380 | ||
381 | case 'U': | |
382 | if (INTVAL (x) < -128 || INTVAL (x) > 255) | |
383 | abort (); | |
384 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); | |
6fafc523 JL |
385 | break; |
386 | ||
576e5acc JL |
387 | /* For shift counts. The hardware ignores the upper bits of |
388 | any immediate, but the assembler will flag an out of range | |
389 | shift count as an error. So we mask off the high bits | |
390 | of the immediate here. */ | |
391 | case 'S': | |
392 | if (GET_CODE (x) == CONST_INT) | |
393 | { | |
a58be199 | 394 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
576e5acc JL |
395 | break; |
396 | } | |
397 | /* FALL THROUGH */ | |
398 | ||
11bb1f11 JL |
399 | default: |
400 | switch (GET_CODE (x)) | |
401 | { | |
402 | case MEM: | |
403 | fputc ('(', file); | |
404 | output_address (XEXP (x, 0)); | |
405 | fputc (')', file); | |
406 | break; | |
407 | ||
38c37a0e JL |
408 | case PLUS: |
409 | output_address (x); | |
410 | break; | |
411 | ||
11bb1f11 JL |
412 | case REG: |
413 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
414 | break; | |
415 | ||
416 | case SUBREG: | |
ddef6bc7 | 417 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
11bb1f11 JL |
418 | break; |
419 | ||
38c37a0e JL |
420 | /* This will only be single precision.... */ |
421 | case CONST_DOUBLE: | |
422 | { | |
423 | unsigned long val; | |
424 | REAL_VALUE_TYPE rv; | |
425 | ||
426 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
427 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
cf31fafa | 428 | fprintf (file, "0x%lx", val); |
38c37a0e JL |
429 | break; |
430 | } | |
431 | ||
11bb1f11 JL |
432 | case CONST_INT: |
433 | case SYMBOL_REF: | |
434 | case CONST: | |
435 | case LABEL_REF: | |
436 | case CODE_LABEL: | |
d1776069 | 437 | case UNSPEC: |
11bb1f11 JL |
438 | print_operand_address (file, x); |
439 | break; | |
440 | default: | |
441 | abort (); | |
442 | } | |
443 | break; | |
444 | } | |
445 | } | |
446 | ||
447 | /* Output assembly language output for the address ADDR to FILE. */ | |
448 | ||
449 | void | |
f1777882 | 450 | print_operand_address (FILE *file, rtx addr) |
11bb1f11 JL |
451 | { |
452 | switch (GET_CODE (addr)) | |
453 | { | |
705ac34f JL |
454 | case POST_INC: |
455 | print_operand_address (file, XEXP (addr, 0)); | |
456 | fputc ('+', file); | |
457 | break; | |
11bb1f11 | 458 | case REG: |
79e4122c | 459 | print_operand (file, addr, 0); |
11bb1f11 JL |
460 | break; |
461 | case PLUS: | |
462 | { | |
463 | rtx base, index; | |
464 | if (REG_P (XEXP (addr, 0)) | |
465 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
466 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
467 | else if (REG_P (XEXP (addr, 1)) | |
468 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
469 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
470 | else | |
471 | abort (); | |
472 | print_operand (file, index, 0); | |
473 | fputc (',', file); | |
474 | print_operand (file, base, 0);; | |
475 | break; | |
476 | } | |
477 | case SYMBOL_REF: | |
478 | output_addr_const (file, addr); | |
479 | break; | |
480 | default: | |
481 | output_addr_const (file, addr); | |
482 | break; | |
483 | } | |
484 | } | |
485 | ||
18e9d2f9 AO |
486 | /* Count the number of FP registers that have to be saved. */ |
487 | static int | |
f1777882 | 488 | fp_regs_to_save (void) |
18e9d2f9 AO |
489 | { |
490 | int i, n = 0; | |
491 | ||
492 | if (! TARGET_AM33_2) | |
493 | return 0; | |
494 | ||
495 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
496 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
497 | ++n; | |
498 | ||
499 | return n; | |
500 | } | |
501 | ||
f6cd7c62 RS |
502 | /* Print a set of registers in the format required by "movm" and "ret". |
503 | Register K is saved if bit K of MASK is set. The data and address | |
504 | registers can be stored individually, but the extended registers cannot. | |
505 | We assume that the mask alread takes that into account. For instance, | |
8596d0a1 | 506 | bits 14 to 17 must have the same value. */ |
f6cd7c62 RS |
507 | |
508 | void | |
f1777882 | 509 | mn10300_print_reg_list (FILE *file, int mask) |
f6cd7c62 RS |
510 | { |
511 | int need_comma; | |
512 | int i; | |
513 | ||
514 | need_comma = 0; | |
515 | fputc ('[', file); | |
516 | ||
517 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
518 | if ((mask & (1 << i)) != 0) | |
519 | { | |
520 | if (need_comma) | |
521 | fputc (',', file); | |
522 | fputs (reg_names [i], file); | |
523 | need_comma = 1; | |
524 | } | |
525 | ||
526 | if ((mask & 0x3c000) != 0) | |
527 | { | |
528 | if ((mask & 0x3c000) != 0x3c000) | |
529 | abort(); | |
530 | if (need_comma) | |
531 | fputc (',', file); | |
532 | fputs ("exreg1", file); | |
533 | need_comma = 1; | |
534 | } | |
535 | ||
536 | fputc (']', file); | |
537 | } | |
538 | ||
38c37a0e | 539 | int |
f1777882 | 540 | can_use_return_insn (void) |
38c37a0e | 541 | { |
460f4b9d JL |
542 | /* size includes the fixed stack space needed for function calls. */ |
543 | int size = get_frame_size () + current_function_outgoing_args_size; | |
544 | ||
545 | /* And space for the return pointer. */ | |
546 | size += current_function_outgoing_args_size ? 4 : 0; | |
38c37a0e JL |
547 | |
548 | return (reload_completed | |
549 | && size == 0 | |
550 | && !regs_ever_live[2] | |
551 | && !regs_ever_live[3] | |
552 | && !regs_ever_live[6] | |
553 | && !regs_ever_live[7] | |
705ac34f JL |
554 | && !regs_ever_live[14] |
555 | && !regs_ever_live[15] | |
556 | && !regs_ever_live[16] | |
557 | && !regs_ever_live[17] | |
18e9d2f9 | 558 | && fp_regs_to_save () == 0 |
38c37a0e JL |
559 | && !frame_pointer_needed); |
560 | } | |
561 | ||
f6cd7c62 RS |
562 | /* Returns the set of live, callee-saved registers as a bitmask. The |
563 | callee-saved extended registers cannot be stored individually, so | |
8596d0a1 | 564 | all of them will be included in the mask if any one of them is used. */ |
f6cd7c62 RS |
565 | |
566 | int | |
f1777882 | 567 | mn10300_get_live_callee_saved_regs (void) |
f6cd7c62 RS |
568 | { |
569 | int mask; | |
570 | int i; | |
571 | ||
572 | mask = 0; | |
18e9d2f9 | 573 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
f6cd7c62 RS |
574 | if (regs_ever_live[i] && ! call_used_regs[i]) |
575 | mask |= (1 << i); | |
576 | if ((mask & 0x3c000) != 0) | |
577 | mask |= 0x3c000; | |
578 | ||
579 | return mask; | |
580 | } | |
581 | ||
582 | /* Generate an instruction that pushes several registers onto the stack. | |
583 | Register K will be saved if bit K in MASK is set. The function does | |
584 | nothing if MASK is zero. | |
585 | ||
586 | To be compatible with the "movm" instruction, the lowest-numbered | |
587 | register must be stored in the lowest slot. If MASK is the set | |
588 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
589 | instruction will have the form: | |
590 | ||
591 | (parallel | |
592 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
593 | (set (mem:SI (plus:SI (reg:SI 9) | |
594 | (const_int -1*4))) | |
595 | (reg:SI RN)) | |
596 | ... | |
597 | (set (mem:SI (plus:SI (reg:SI 9) | |
598 | (const_int -N*4))) | |
599 | (reg:SI R1))) */ | |
600 | ||
601 | void | |
f1777882 | 602 | mn10300_gen_multiple_store (int mask) |
f6cd7c62 RS |
603 | { |
604 | if (mask != 0) | |
605 | { | |
606 | int i; | |
607 | int count; | |
608 | rtx par; | |
609 | int pari; | |
610 | ||
8596d0a1 | 611 | /* Count how many registers need to be saved. */ |
f6cd7c62 | 612 | count = 0; |
18e9d2f9 | 613 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
f6cd7c62 RS |
614 | if ((mask & (1 << i)) != 0) |
615 | count += 1; | |
616 | ||
617 | /* We need one PARALLEL element to update the stack pointer and | |
8596d0a1 | 618 | an additional element for each register that is stored. */ |
f6cd7c62 RS |
619 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
620 | ||
8596d0a1 | 621 | /* Create the instruction that updates the stack pointer. */ |
f6cd7c62 RS |
622 | XVECEXP (par, 0, 0) |
623 | = gen_rtx_SET (SImode, | |
624 | stack_pointer_rtx, | |
625 | gen_rtx_PLUS (SImode, | |
626 | stack_pointer_rtx, | |
627 | GEN_INT (-count * 4))); | |
628 | ||
8596d0a1 | 629 | /* Create each store. */ |
f6cd7c62 | 630 | pari = 1; |
18e9d2f9 | 631 | for (i = LAST_EXTENDED_REGNUM; i >= 0; i--) |
f6cd7c62 RS |
632 | if ((mask & (1 << i)) != 0) |
633 | { | |
634 | rtx address = gen_rtx_PLUS (SImode, | |
635 | stack_pointer_rtx, | |
636 | GEN_INT (-pari * 4)); | |
637 | XVECEXP(par, 0, pari) | |
638 | = gen_rtx_SET (VOIDmode, | |
639 | gen_rtx_MEM (SImode, address), | |
640 | gen_rtx_REG (SImode, i)); | |
641 | pari += 1; | |
642 | } | |
643 | ||
644 | par = emit_insn (par); | |
645 | RTX_FRAME_RELATED_P (par) = 1; | |
646 | } | |
647 | } | |
648 | ||
11bb1f11 | 649 | void |
f1777882 | 650 | expand_prologue (void) |
11bb1f11 | 651 | { |
036182e7 | 652 | HOST_WIDE_INT size; |
3dbc43d1 | 653 | |
3dbc43d1 | 654 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
655 | size = get_frame_size () + current_function_outgoing_args_size; |
656 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 657 | |
8596d0a1 | 658 | /* If we use any of the callee-saved registers, save them now. */ |
f6cd7c62 | 659 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); |
777fbf09 | 660 | |
18e9d2f9 AO |
661 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
662 | { | |
663 | int num_regs_to_save = fp_regs_to_save (), i; | |
664 | HOST_WIDE_INT xsize; | |
665 | enum { save_sp_merge, | |
666 | save_sp_no_merge, | |
667 | save_sp_partial_merge, | |
668 | save_a0_merge, | |
669 | save_a0_no_merge } strategy; | |
670 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; | |
671 | rtx reg; | |
672 | rtx insn; | |
673 | ||
674 | /* We have several different strategies to save FP registers. | |
675 | We can store them using SP offsets, which is beneficial if | |
676 | there are just a few registers to save, or we can use `a0' in | |
677 | post-increment mode (`a0' is the only call-clobbered address | |
678 | register that is never used to pass information to a | |
679 | function). Furthermore, if we don't need a frame pointer, we | |
680 | can merge the two SP adds into a single one, but this isn't | |
681 | always beneficial; sometimes we can just split the two adds | |
682 | so that we don't exceed a 16-bit constant size. The code | |
683 | below will select which strategy to use, so as to generate | |
684 | smallest code. Ties are broken in favor or shorter sequences | |
685 | (in terms of number of instructions). */ | |
686 | ||
687 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
688 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
689 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
690 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
691 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ | |
692 | (((S) >= (L)) ? (SIZE1) * (N) \ | |
693 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ | |
694 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
695 | : (ELSE)) | |
696 | #define SIZE_FMOV_SP_(S,N) \ | |
697 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
698 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
699 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
700 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
701 | ||
702 | /* Consider alternative save_sp_merge only if we don't need the | |
4375e090 | 703 | frame pointer and size is nonzero. */ |
18e9d2f9 AO |
704 | if (! frame_pointer_needed && size) |
705 | { | |
706 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
707 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
708 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
709 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
710 | ||
711 | if (this_strategy_size < strategy_size) | |
712 | { | |
713 | strategy = save_sp_merge; | |
714 | strategy_size = this_strategy_size; | |
715 | } | |
716 | } | |
717 | ||
718 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
719 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
720 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
721 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
722 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
723 | if (size) | |
724 | { | |
725 | /* Insn: add -size, sp. */ | |
726 | this_strategy_size += SIZE_ADD_SP (-size); | |
727 | } | |
728 | ||
729 | if (this_strategy_size < strategy_size) | |
730 | { | |
731 | strategy = save_sp_no_merge; | |
732 | strategy_size = this_strategy_size; | |
733 | } | |
734 | ||
735 | /* Consider alternative save_sp_partial_merge only if we don't | |
736 | need a frame pointer and size is reasonably large. */ | |
737 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
738 | { | |
739 | /* Insn: add -128, sp. */ | |
740 | this_strategy_size = SIZE_ADD_SP (-128); | |
741 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
742 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
743 | num_regs_to_save); | |
744 | if (size) | |
745 | { | |
746 | /* Insn: add 128-size, sp. */ | |
747 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
748 | } | |
749 | ||
750 | if (this_strategy_size < strategy_size) | |
751 | { | |
752 | strategy = save_sp_partial_merge; | |
753 | strategy_size = this_strategy_size; | |
754 | } | |
755 | } | |
756 | ||
757 | /* Consider alternative save_a0_merge only if we don't need a | |
4375e090 | 758 | frame pointer, size is nonzero and the user hasn't |
18e9d2f9 AO |
759 | changed the calling conventions of a0. */ |
760 | if (! frame_pointer_needed && size | |
761 | && call_used_regs[FIRST_ADDRESS_REGNUM] | |
762 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) | |
763 | { | |
764 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
765 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
766 | /* Insn: mov sp, a0. */ | |
767 | this_strategy_size++; | |
768 | if (size) | |
769 | { | |
770 | /* Insn: add size, a0. */ | |
771 | this_strategy_size += SIZE_ADD_AX (size); | |
772 | } | |
773 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
774 | this_strategy_size += 3 * num_regs_to_save; | |
775 | ||
776 | if (this_strategy_size < strategy_size) | |
777 | { | |
778 | strategy = save_a0_merge; | |
779 | strategy_size = this_strategy_size; | |
780 | } | |
781 | } | |
782 | ||
783 | /* Consider alternative save_a0_no_merge if the user hasn't | |
8596d0a1 | 784 | changed the calling conventions of a0. */ |
18e9d2f9 AO |
785 | if (call_used_regs[FIRST_ADDRESS_REGNUM] |
786 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) | |
787 | { | |
788 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
789 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
790 | /* Insn: mov sp, a0. */ | |
791 | this_strategy_size++; | |
792 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
793 | this_strategy_size += 3 * num_regs_to_save; | |
794 | if (size) | |
795 | { | |
796 | /* Insn: add -size, sp. */ | |
797 | this_strategy_size += SIZE_ADD_SP (-size); | |
798 | } | |
799 | ||
800 | if (this_strategy_size < strategy_size) | |
801 | { | |
802 | strategy = save_a0_no_merge; | |
803 | strategy_size = this_strategy_size; | |
804 | } | |
805 | } | |
806 | ||
807 | /* Emit the initial SP add, common to all strategies. */ | |
808 | switch (strategy) | |
809 | { | |
810 | case save_sp_no_merge: | |
811 | case save_a0_no_merge: | |
812 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
813 | stack_pointer_rtx, | |
814 | GEN_INT (-4 * num_regs_to_save))); | |
815 | xsize = 0; | |
816 | break; | |
817 | ||
818 | case save_sp_partial_merge: | |
819 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
820 | stack_pointer_rtx, | |
821 | GEN_INT (-128))); | |
822 | xsize = 128 - 4 * num_regs_to_save; | |
823 | size -= xsize; | |
824 | break; | |
825 | ||
826 | case save_sp_merge: | |
827 | case save_a0_merge: | |
828 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
829 | stack_pointer_rtx, | |
830 | GEN_INT (-(size + 4 * num_regs_to_save)))); | |
831 | /* We'll have to adjust FP register saves according to the | |
8596d0a1 | 832 | frame size. */ |
18e9d2f9 AO |
833 | xsize = size; |
834 | /* Since we've already created the stack frame, don't do it | |
8596d0a1 | 835 | again at the end of the function. */ |
18e9d2f9 AO |
836 | size = 0; |
837 | break; | |
838 | ||
839 | default: | |
840 | abort (); | |
841 | } | |
842 | ||
843 | /* Now prepare register a0, if we have decided to use it. */ | |
844 | switch (strategy) | |
845 | { | |
846 | case save_sp_merge: | |
847 | case save_sp_no_merge: | |
848 | case save_sp_partial_merge: | |
849 | reg = 0; | |
850 | break; | |
851 | ||
852 | case save_a0_merge: | |
853 | case save_a0_no_merge: | |
854 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
855 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
856 | if (xsize) | |
857 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))); | |
858 | reg = gen_rtx_POST_INC (SImode, reg); | |
859 | break; | |
860 | ||
861 | default: | |
862 | abort (); | |
863 | } | |
864 | ||
865 | /* Now actually save the FP registers. */ | |
866 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
867 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
868 | { | |
869 | rtx addr; | |
870 | ||
871 | if (reg) | |
872 | addr = reg; | |
873 | else | |
874 | { | |
875 | /* If we aren't using `a0', use an SP offset. */ | |
876 | if (xsize) | |
877 | { | |
878 | addr = gen_rtx_PLUS (SImode, | |
879 | stack_pointer_rtx, | |
880 | GEN_INT (xsize)); | |
881 | } | |
882 | else | |
883 | addr = stack_pointer_rtx; | |
884 | ||
885 | xsize += 4; | |
886 | } | |
887 | ||
888 | insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr), | |
889 | gen_rtx_REG (SImode, i))); | |
890 | ||
891 | RTX_FRAME_RELATED_P (insn) = 1; | |
892 | } | |
893 | } | |
894 | ||
777fbf09 | 895 | /* Now put the frame pointer into the frame pointer register. */ |
11bb1f11 | 896 | if (frame_pointer_needed) |
6e86170d | 897 | emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); |
11bb1f11 | 898 | |
777fbf09 | 899 | /* Allocate stack for this frame. */ |
11bb1f11 JL |
900 | if (size) |
901 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
902 | stack_pointer_rtx, | |
903 | GEN_INT (-size))); | |
d1776069 AO |
904 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
905 | { | |
906 | rtx insn = get_last_insn (); | |
907 | rtx last = emit_insn (gen_GOTaddr2picreg ()); | |
908 | ||
909 | /* Mark these insns as possibly dead. Sometimes, flow2 may | |
910 | delete all uses of the PIC register. In this case, let it | |
911 | delete the initialization too. */ | |
912 | do | |
913 | { | |
914 | insn = NEXT_INSN (insn); | |
915 | ||
916 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
917 | const0_rtx, | |
918 | REG_NOTES (insn)); | |
919 | } | |
920 | while (insn != last); | |
921 | } | |
11bb1f11 JL |
922 | } |
923 | ||
924 | void | |
f1777882 | 925 | expand_epilogue (void) |
11bb1f11 | 926 | { |
036182e7 | 927 | HOST_WIDE_INT size; |
3dbc43d1 | 928 | |
3dbc43d1 | 929 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
930 | size = get_frame_size () + current_function_outgoing_args_size; |
931 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 932 | |
18e9d2f9 AO |
933 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
934 | { | |
935 | int num_regs_to_save = fp_regs_to_save (), i; | |
936 | rtx reg = 0; | |
937 | ||
938 | /* We have several options to restore FP registers. We could | |
939 | load them from SP offsets, but, if there are enough FP | |
940 | registers to restore, we win if we use a post-increment | |
941 | addressing mode. */ | |
942 | ||
943 | /* If we have a frame pointer, it's the best option, because we | |
944 | already know it has the value we want. */ | |
945 | if (frame_pointer_needed) | |
946 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
947 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
948 | it's never used for return values. But only do so if it's | |
949 | smaller than using SP offsets. */ | |
950 | else | |
951 | { | |
952 | enum { restore_sp_post_adjust, | |
953 | restore_sp_pre_adjust, | |
954 | restore_sp_partial_adjust, | |
955 | restore_a1 } strategy; | |
956 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
957 | ||
958 | /* Consider using sp offsets before adjusting sp. */ | |
959 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
960 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
961 | /* If size is too large, we'll have to adjust SP with an | |
962 | add. */ | |
963 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
964 | { | |
965 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
966 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
967 | } | |
968 | /* If we don't have to restore any non-FP registers, | |
969 | we'll be able to save one byte by using rets. */ | |
970 | if (! REG_SAVE_BYTES) | |
971 | this_strategy_size--; | |
972 | ||
973 | if (this_strategy_size < strategy_size) | |
974 | { | |
975 | strategy = restore_sp_post_adjust; | |
976 | strategy_size = this_strategy_size; | |
977 | } | |
978 | ||
979 | /* Consider using sp offsets after adjusting sp. */ | |
980 | /* Insn: add size, sp. */ | |
981 | this_strategy_size = SIZE_ADD_SP (size); | |
982 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
983 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
984 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 985 | save area, so, no savings. */ |
18e9d2f9 AO |
986 | |
987 | if (this_strategy_size < strategy_size) | |
988 | { | |
989 | strategy = restore_sp_pre_adjust; | |
990 | strategy_size = this_strategy_size; | |
991 | } | |
992 | ||
993 | /* Consider using sp offsets after partially adjusting sp. | |
994 | When size is close to 32Kb, we may be able to adjust SP | |
995 | with an imm16 add instruction while still using fmov | |
996 | (d8,sp). */ | |
997 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
998 | { | |
999 | /* Insn: add size + 4 * num_regs_to_save | |
1000 | + REG_SAVE_BYTES - 252,sp. */ | |
1001 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save | |
1002 | + REG_SAVE_BYTES - 252); | |
1003 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ | |
1004 | this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES | |
1005 | - 4 * num_regs_to_save, | |
1006 | num_regs_to_save); | |
1007 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1008 | save area, so, no savings. */ |
18e9d2f9 AO |
1009 | |
1010 | if (this_strategy_size < strategy_size) | |
1011 | { | |
1012 | strategy = restore_sp_partial_adjust; | |
1013 | strategy_size = this_strategy_size; | |
1014 | } | |
1015 | } | |
1016 | ||
1017 | /* Consider using a1 in post-increment mode, as long as the | |
1018 | user hasn't changed the calling conventions of a1. */ | |
1019 | if (call_used_regs[FIRST_ADDRESS_REGNUM+1] | |
1020 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) | |
1021 | { | |
1022 | /* Insn: mov sp,a1. */ | |
1023 | this_strategy_size = 1; | |
1024 | if (size) | |
1025 | { | |
1026 | /* Insn: add size,a1. */ | |
1027 | this_strategy_size += SIZE_ADD_AX (size); | |
1028 | } | |
1029 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1030 | this_strategy_size += 3 * num_regs_to_save; | |
1031 | /* If size is large enough, we may be able to save a | |
1032 | couple of bytes. */ | |
1033 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1034 | { | |
1035 | /* Insn: mov a1,sp. */ | |
1036 | this_strategy_size += 2; | |
1037 | } | |
1038 | /* If we don't have to restore any non-FP registers, | |
1039 | we'll be able to save one byte by using rets. */ | |
1040 | if (! REG_SAVE_BYTES) | |
1041 | this_strategy_size--; | |
1042 | ||
1043 | if (this_strategy_size < strategy_size) | |
1044 | { | |
1045 | strategy = restore_a1; | |
1046 | strategy_size = this_strategy_size; | |
1047 | } | |
1048 | } | |
1049 | ||
1050 | switch (strategy) | |
1051 | { | |
1052 | case restore_sp_post_adjust: | |
1053 | break; | |
1054 | ||
1055 | case restore_sp_pre_adjust: | |
1056 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1057 | stack_pointer_rtx, | |
1058 | GEN_INT (size))); | |
1059 | size = 0; | |
1060 | break; | |
1061 | ||
1062 | case restore_sp_partial_adjust: | |
1063 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1064 | stack_pointer_rtx, | |
1065 | GEN_INT (size + 4 * num_regs_to_save | |
1066 | + REG_SAVE_BYTES - 252))); | |
1067 | size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save; | |
1068 | break; | |
1069 | ||
1070 | case restore_a1: | |
1071 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1072 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1073 | if (size) | |
1074 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1075 | break; | |
1076 | ||
1077 | default: | |
1078 | abort (); | |
1079 | } | |
1080 | } | |
1081 | ||
1082 | /* Adjust the selected register, if any, for post-increment. */ | |
1083 | if (reg) | |
1084 | reg = gen_rtx_POST_INC (SImode, reg); | |
1085 | ||
1086 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
1087 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
1088 | { | |
1089 | rtx addr; | |
1090 | ||
1091 | if (reg) | |
1092 | addr = reg; | |
1093 | else if (size) | |
1094 | { | |
1095 | /* If we aren't using a post-increment register, use an | |
8596d0a1 | 1096 | SP offset. */ |
18e9d2f9 AO |
1097 | addr = gen_rtx_PLUS (SImode, |
1098 | stack_pointer_rtx, | |
1099 | GEN_INT (size)); | |
1100 | } | |
1101 | else | |
1102 | addr = stack_pointer_rtx; | |
1103 | ||
1104 | size += 4; | |
1105 | ||
1106 | emit_insn (gen_movsi (gen_rtx_REG (SImode, i), | |
1107 | gen_rtx_MEM (SImode, addr))); | |
1108 | } | |
1109 | ||
1110 | /* If we were using the restore_a1 strategy and the number of | |
1111 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1112 | to `sp', to avoid having to use `add' to adjust it. */ | |
1113 | if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255) | |
1114 | { | |
1115 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1116 | size = 0; | |
1117 | } | |
1118 | } | |
1119 | ||
5d29a95f JL |
1120 | /* Maybe cut back the stack, except for the register save area. |
1121 | ||
1122 | If the frame pointer exists, then use the frame pointer to | |
1123 | cut back the stack. | |
1124 | ||
1125 | If the stack size + register save area is more than 255 bytes, | |
1126 | then the stack must be cut back here since the size + register | |
1127 | save size is too big for a ret/retf instruction. | |
1128 | ||
1129 | Else leave it alone, it will be cut back as part of the | |
1130 | ret/retf instruction, or there wasn't any stack to begin with. | |
1131 | ||
dab66575 | 1132 | Under no circumstances should the register save area be |
5d29a95f JL |
1133 | deallocated here, that would leave a window where an interrupt |
1134 | could occur and trash the register save area. */ | |
11bb1f11 JL |
1135 | if (frame_pointer_needed) |
1136 | { | |
11bb1f11 | 1137 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
4246e0c5 JL |
1138 | size = 0; |
1139 | } | |
ed6089d6 | 1140 | else if (size + REG_SAVE_BYTES > 255) |
4246e0c5 JL |
1141 | { |
1142 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1143 | stack_pointer_rtx, | |
1144 | GEN_INT (size))); | |
1145 | size = 0; | |
11bb1f11 | 1146 | } |
11bb1f11 | 1147 | |
ed6089d6 AO |
1148 | /* Adjust the stack and restore callee-saved registers, if any. */ |
1149 | if (size || regs_ever_live[2] || regs_ever_live[3] | |
777fbf09 | 1150 | || regs_ever_live[6] || regs_ever_live[7] |
705ac34f JL |
1151 | || regs_ever_live[14] || regs_ever_live[15] |
1152 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 | 1153 | || frame_pointer_needed) |
ed6089d6 AO |
1154 | emit_jump_insn (gen_return_internal_regs |
1155 | (GEN_INT (size + REG_SAVE_BYTES))); | |
777fbf09 | 1156 | else |
ed6089d6 | 1157 | emit_jump_insn (gen_return_internal ()); |
11bb1f11 JL |
1158 | } |
1159 | ||
1160 | /* Update the condition code from the insn. */ | |
1161 | ||
1162 | void | |
f1777882 | 1163 | notice_update_cc (rtx body, rtx insn) |
11bb1f11 | 1164 | { |
11bb1f11 JL |
1165 | switch (get_attr_cc (insn)) |
1166 | { | |
1167 | case CC_NONE: | |
1168 | /* Insn does not affect CC at all. */ | |
1169 | break; | |
1170 | ||
1171 | case CC_NONE_0HIT: | |
1172 | /* Insn does not change CC, but the 0'th operand has been changed. */ | |
1173 | if (cc_status.value1 != 0 | |
1ccbefce | 1174 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
11bb1f11 JL |
1175 | cc_status.value1 = 0; |
1176 | break; | |
1177 | ||
d116300b | 1178 | case CC_SET_ZN: |
1ccbefce | 1179 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
d116300b | 1180 | V,C are unusable. */ |
11bb1f11 | 1181 | CC_STATUS_INIT; |
d116300b | 1182 | cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; |
1ccbefce | 1183 | cc_status.value1 = recog_data.operand[0]; |
11bb1f11 JL |
1184 | break; |
1185 | ||
d116300b | 1186 | case CC_SET_ZNV: |
1ccbefce | 1187 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
d116300b | 1188 | C is unusable. */ |
82c6faa8 | 1189 | CC_STATUS_INIT; |
d116300b | 1190 | cc_status.flags |= CC_NO_CARRY; |
1ccbefce | 1191 | cc_status.value1 = recog_data.operand[0]; |
82c6faa8 JL |
1192 | break; |
1193 | ||
11bb1f11 JL |
1194 | case CC_COMPARE: |
1195 | /* The insn is a compare instruction. */ | |
1196 | CC_STATUS_INIT; | |
1197 | cc_status.value1 = SET_SRC (body); | |
18e9d2f9 AO |
1198 | if (GET_CODE (cc_status.value1) == COMPARE |
1199 | && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode) | |
1200 | cc_status.mdep.fpCC = 1; | |
11bb1f11 JL |
1201 | break; |
1202 | ||
3b800f71 JL |
1203 | case CC_INVERT: |
1204 | /* The insn is a compare instruction. */ | |
1205 | CC_STATUS_INIT; | |
1206 | cc_status.value1 = SET_SRC (body); | |
1207 | cc_status.flags |= CC_INVERTED; | |
1208 | break; | |
1209 | ||
11bb1f11 JL |
1210 | case CC_CLOBBER: |
1211 | /* Insn doesn't leave CC in a usable state. */ | |
1212 | CC_STATUS_INIT; | |
1213 | break; | |
82c6faa8 JL |
1214 | |
1215 | default: | |
1216 | abort (); | |
11bb1f11 | 1217 | } |
11bb1f11 JL |
1218 | } |
1219 | ||
05713b80 | 1220 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
f6cd7c62 RS |
1221 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1222 | parallel. If OP is a multiple store, return a mask indicating which | |
1223 | registers it saves. Return 0 otherwise. */ | |
1224 | ||
1225 | int | |
f1777882 | 1226 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
f6cd7c62 RS |
1227 | { |
1228 | int count; | |
1229 | int mask; | |
1230 | int i; | |
1231 | unsigned int last; | |
1232 | rtx elt; | |
1233 | ||
1234 | count = XVECLEN (op, 0); | |
1235 | if (count < 2) | |
1236 | return 0; | |
1237 | ||
1238 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1239 | elt = XVECEXP (op, 0, 0); | |
1240 | if (GET_CODE (elt) != SET | |
1241 | || GET_CODE (SET_DEST (elt)) != REG | |
1242 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM | |
1243 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1244 | return 0; | |
1245 | ||
1246 | /* Check that A is the stack pointer and B is the expected stack size. | |
1247 | For OP to match, each subsequent instruction should push a word onto | |
1248 | the stack. We therefore expect the first instruction to create | |
8596d0a1 | 1249 | COUNT-1 stack slots. */ |
f6cd7c62 RS |
1250 | elt = SET_SRC (elt); |
1251 | if (GET_CODE (XEXP (elt, 0)) != REG | |
1252 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1253 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1254 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) | |
1255 | return 0; | |
1256 | ||
1257 | /* Now go through the rest of the vector elements. They must be | |
1258 | ordered so that the first instruction stores the highest-numbered | |
1259 | register to the highest stack slot and that subsequent instructions | |
1260 | store a lower-numbered register to the slot below. | |
1261 | ||
1262 | LAST keeps track of the smallest-numbered register stored so far. | |
8596d0a1 | 1263 | MASK is the set of stored registers. */ |
18e9d2f9 | 1264 | last = LAST_EXTENDED_REGNUM + 1; |
f6cd7c62 RS |
1265 | mask = 0; |
1266 | for (i = 1; i < count; i++) | |
1267 | { | |
8596d0a1 | 1268 | /* Check that element i is a (set (mem M) R) and that R is valid. */ |
f6cd7c62 RS |
1269 | elt = XVECEXP (op, 0, i); |
1270 | if (GET_CODE (elt) != SET | |
1271 | || GET_CODE (SET_DEST (elt)) != MEM | |
1272 | || GET_CODE (SET_SRC (elt)) != REG | |
1273 | || REGNO (SET_SRC (elt)) >= last) | |
1274 | return 0; | |
1275 | ||
1276 | /* R was OK, so provisionally add it to MASK. We return 0 in any | |
8596d0a1 | 1277 | case if the rest of the instruction has a flaw. */ |
f6cd7c62 RS |
1278 | last = REGNO (SET_SRC (elt)); |
1279 | mask |= (1 << last); | |
1280 | ||
1281 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1282 | elt = XEXP (SET_DEST (elt), 0); | |
1283 | if (GET_CODE (elt) != PLUS | |
1284 | || GET_CODE (XEXP (elt, 0)) != REG | |
1285 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1286 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1287 | || INTVAL (XEXP (elt, 1)) != -i * 4) | |
1288 | return 0; | |
1289 | } | |
1290 | ||
8596d0a1 | 1291 | /* All or none of the callee-saved extended registers must be in the set. */ |
f6cd7c62 RS |
1292 | if ((mask & 0x3c000) != 0 |
1293 | && (mask & 0x3c000) != 0x3c000) | |
1294 | return 0; | |
1295 | ||
1296 | return mask; | |
1297 | } | |
1298 | ||
11bb1f11 JL |
1299 | /* Return true if OP is a valid call operand. */ |
1300 | ||
1301 | int | |
f1777882 | 1302 | call_address_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
11bb1f11 | 1303 | { |
d1776069 AO |
1304 | if (flag_pic) |
1305 | return (EXTRA_CONSTRAINT (op, 'S') || GET_CODE (op) == REG); | |
1306 | ||
11bb1f11 JL |
1307 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG); |
1308 | } | |
1309 | ||
1310 | /* What (if any) secondary registers are needed to move IN with mode | |
8493cfcb | 1311 | MODE into a register in register class CLASS. |
11bb1f11 JL |
1312 | |
1313 | We might be able to simplify this. */ | |
1314 | enum reg_class | |
f1777882 | 1315 | secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in) |
11bb1f11 | 1316 | { |
11bb1f11 JL |
1317 | /* Memory loads less than a full word wide can't have an |
1318 | address or stack pointer destination. They must use | |
1319 | a data register as an intermediate register. */ | |
15c09738 AH |
1320 | if ((GET_CODE (in) == MEM |
1321 | || (GET_CODE (in) == REG | |
1322 | && REGNO (in) >= FIRST_PSEUDO_REGISTER) | |
1323 | || (GET_CODE (in) == SUBREG | |
1324 | && GET_CODE (SUBREG_REG (in)) == REG | |
1325 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)) | |
11bb1f11 | 1326 | && (mode == QImode || mode == HImode) |
15c09738 | 1327 | && (class == ADDRESS_REGS || class == SP_REGS |
842a0788 | 1328 | || class == SP_OR_ADDRESS_REGS)) |
4d1a91c2 | 1329 | { |
705ac34f JL |
1330 | if (TARGET_AM33) |
1331 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
1332 | return DATA_REGS; |
1333 | } | |
11bb1f11 JL |
1334 | |
1335 | /* We can't directly load sp + const_int into a data register; | |
1336 | we must use an address register as an intermediate. */ | |
777fbf09 JL |
1337 | if (class != SP_REGS |
1338 | && class != ADDRESS_REGS | |
1339 | && class != SP_OR_ADDRESS_REGS | |
705ac34f JL |
1340 | && class != SP_OR_EXTENDED_REGS |
1341 | && class != ADDRESS_OR_EXTENDED_REGS | |
1342 | && class != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
11bb1f11 JL |
1343 | && (in == stack_pointer_rtx |
1344 | || (GET_CODE (in) == PLUS | |
777fbf09 JL |
1345 | && (XEXP (in, 0) == stack_pointer_rtx |
1346 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
11bb1f11 JL |
1347 | return ADDRESS_REGS; |
1348 | ||
4c742813 JL |
1349 | if (GET_CODE (in) == PLUS |
1350 | && (XEXP (in, 0) == stack_pointer_rtx | |
1351 | || XEXP (in, 1) == stack_pointer_rtx)) | |
4d1a91c2 | 1352 | { |
705ac34f JL |
1353 | if (TARGET_AM33) |
1354 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
1355 | return DATA_REGS; |
1356 | } | |
4c742813 | 1357 | |
18e9d2f9 AO |
1358 | if (TARGET_AM33_2 && class == FP_REGS |
1359 | && GET_CODE (in) == MEM && ! OK_FOR_Q (in)) | |
1360 | { | |
1361 | if (TARGET_AM33) | |
1362 | return DATA_OR_EXTENDED_REGS; | |
1363 | return DATA_REGS; | |
1364 | } | |
1365 | ||
777fbf09 JL |
1366 | /* Otherwise assume no secondary reloads are needed. */ |
1367 | return NO_REGS; | |
1368 | } | |
1369 | ||
1370 | int | |
f1777882 | 1371 | initial_offset (int from, int to) |
777fbf09 | 1372 | { |
3dbc43d1 JL |
1373 | /* The difference between the argument pointer and the frame pointer |
1374 | is the size of the callee register save area. */ | |
777fbf09 | 1375 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
11bb1f11 | 1376 | { |
777fbf09 JL |
1377 | if (regs_ever_live[2] || regs_ever_live[3] |
1378 | || regs_ever_live[6] || regs_ever_live[7] | |
705ac34f JL |
1379 | || regs_ever_live[14] || regs_ever_live[15] |
1380 | || regs_ever_live[16] || regs_ever_live[17] | |
18e9d2f9 | 1381 | || fp_regs_to_save () |
777fbf09 | 1382 | || frame_pointer_needed) |
18e9d2f9 AO |
1383 | return REG_SAVE_BYTES |
1384 | + 4 * fp_regs_to_save (); | |
777fbf09 | 1385 | else |
22ef4e9b | 1386 | return 0; |
11bb1f11 JL |
1387 | } |
1388 | ||
3dbc43d1 JL |
1389 | /* The difference between the argument pointer and the stack pointer is |
1390 | the sum of the size of this function's frame, the callee register save | |
1391 | area, and the fixed stack space needed for function calls (if any). */ | |
777fbf09 JL |
1392 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
1393 | { | |
1394 | if (regs_ever_live[2] || regs_ever_live[3] | |
1395 | || regs_ever_live[6] || regs_ever_live[7] | |
705ac34f JL |
1396 | || regs_ever_live[14] || regs_ever_live[15] |
1397 | || regs_ever_live[16] || regs_ever_live[17] | |
18e9d2f9 | 1398 | || fp_regs_to_save () |
777fbf09 | 1399 | || frame_pointer_needed) |
4d1a91c2 | 1400 | return (get_frame_size () + REG_SAVE_BYTES |
18e9d2f9 | 1401 | + 4 * fp_regs_to_save () |
460f4b9d JL |
1402 | + (current_function_outgoing_args_size |
1403 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 | 1404 | else |
460f4b9d JL |
1405 | return (get_frame_size () |
1406 | + (current_function_outgoing_args_size | |
1407 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 | 1408 | } |
11bb1f11 | 1409 | |
3dbc43d1 JL |
1410 | /* The difference between the frame pointer and stack pointer is the sum |
1411 | of the size of this function's frame and the fixed stack space needed | |
1412 | for function calls (if any). */ | |
777fbf09 | 1413 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
460f4b9d JL |
1414 | return (get_frame_size () |
1415 | + (current_function_outgoing_args_size | |
1416 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 JL |
1417 | |
1418 | abort (); | |
11bb1f11 | 1419 | } |
22ef4e9b | 1420 | |
9024ea92 KH |
1421 | static bool |
1422 | mn10300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
1423 | { | |
1424 | /* Return values > 8 bytes in length in memory. */ | |
1425 | return int_size_in_bytes (type) > 8 || TYPE_MODE (type) == BLKmode; | |
1426 | } | |
1427 | ||
22ef4e9b JL |
1428 | /* Flush the argument registers to the stack for a stdarg function; |
1429 | return the new argument pointer. */ | |
9024ea92 | 1430 | static rtx |
f1777882 | 1431 | mn10300_builtin_saveregs (void) |
22ef4e9b | 1432 | { |
fc2acc87 | 1433 | rtx offset, mem; |
22ef4e9b JL |
1434 | tree fntype = TREE_TYPE (current_function_decl); |
1435 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
1436 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
1437 | != void_type_node))) | |
1438 | ? UNITS_PER_WORD : 0); | |
fc2acc87 | 1439 | int set = get_varargs_alias_set (); |
22ef4e9b JL |
1440 | |
1441 | if (argadj) | |
1442 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
1443 | else | |
1444 | offset = current_function_arg_offset_rtx; | |
1445 | ||
fc2acc87 | 1446 | mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer); |
ba4828e0 | 1447 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1448 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1449 | ||
1450 | mem = gen_rtx_MEM (SImode, | |
1451 | plus_constant (current_function_internal_arg_pointer, 4)); | |
ba4828e0 | 1452 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1453 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1454 | ||
22ef4e9b JL |
1455 | return copy_to_reg (expand_binop (Pmode, add_optab, |
1456 | current_function_internal_arg_pointer, | |
1457 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
1458 | } | |
1459 | ||
fc2acc87 | 1460 | void |
f1777882 | 1461 | mn10300_va_start (tree valist, rtx nextarg) |
fc2acc87 | 1462 | { |
6c535c69 | 1463 | nextarg = expand_builtin_saveregs (); |
e5faf155 | 1464 | std_expand_builtin_va_start (valist, nextarg); |
fc2acc87 RH |
1465 | } |
1466 | ||
1467 | rtx | |
f1777882 | 1468 | mn10300_va_arg (tree valist, tree type) |
fc2acc87 RH |
1469 | { |
1470 | HOST_WIDE_INT align, rsize; | |
1471 | tree t, ptr, pptr; | |
1472 | ||
1473 | /* Compute the rounded size of the type. */ | |
1474 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
1475 | rsize = (((int_size_in_bytes (type) + align - 1) / align) * align); | |
1476 | ||
1477 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
1478 | build_int_2 ((rsize > 8 ? 4 : rsize), 0)); | |
1479 | TREE_SIDE_EFFECTS (t) = 1; | |
1480 | ||
1481 | ptr = build_pointer_type (type); | |
1482 | ||
1483 | /* "Large" types are passed by reference. */ | |
1484 | if (rsize > 8) | |
1485 | { | |
1486 | pptr = build_pointer_type (ptr); | |
1487 | t = build1 (NOP_EXPR, pptr, t); | |
1488 | TREE_SIDE_EFFECTS (t) = 1; | |
1489 | ||
1490 | t = build1 (INDIRECT_REF, ptr, t); | |
1491 | TREE_SIDE_EFFECTS (t) = 1; | |
1492 | } | |
1493 | else | |
1494 | { | |
1495 | t = build1 (NOP_EXPR, ptr, t); | |
1496 | TREE_SIDE_EFFECTS (t) = 1; | |
1497 | } | |
1498 | ||
1499 | /* Calculate! */ | |
1500 | return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL); | |
1501 | } | |
1502 | ||
22ef4e9b JL |
1503 | /* Return an RTX to represent where a value with mode MODE will be returned |
1504 | from a function. If the result is 0, the argument is pushed. */ | |
1505 | ||
1506 | rtx | |
f1777882 KH |
1507 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
1508 | tree type, int named ATTRIBUTE_UNUSED) | |
22ef4e9b JL |
1509 | { |
1510 | rtx result = 0; | |
1511 | int size, align; | |
1512 | ||
1513 | /* We only support using 2 data registers as argument registers. */ | |
1514 | int nregs = 2; | |
1515 | ||
1516 | /* Figure out the size of the object to be passed. */ | |
1517 | if (mode == BLKmode) | |
1518 | size = int_size_in_bytes (type); | |
1519 | else | |
1520 | size = GET_MODE_SIZE (mode); | |
1521 | ||
1522 | /* Figure out the alignment of the object to be passed. */ | |
1523 | align = size; | |
1524 | ||
1525 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1526 | ||
1527 | /* Don't pass this arg via a register if all the argument registers | |
1528 | are used up. */ | |
1529 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1530 | return 0; | |
1531 | ||
1532 | /* Don't pass this arg via a register if it would be split between | |
1533 | registers and memory. */ | |
1534 | if (type == NULL_TREE | |
1535 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1536 | return 0; | |
1537 | ||
1538 | switch (cum->nbytes / UNITS_PER_WORD) | |
1539 | { | |
1540 | case 0: | |
c5c76735 | 1541 | result = gen_rtx_REG (mode, 0); |
22ef4e9b JL |
1542 | break; |
1543 | case 1: | |
c5c76735 | 1544 | result = gen_rtx_REG (mode, 1); |
22ef4e9b JL |
1545 | break; |
1546 | default: | |
1547 | result = 0; | |
1548 | } | |
1549 | ||
1550 | return result; | |
1551 | } | |
1552 | ||
1553 | /* Return the number of registers to use for an argument passed partially | |
1554 | in registers and partially in memory. */ | |
1555 | ||
1556 | int | |
f1777882 KH |
1557 | function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
1558 | tree type, int named ATTRIBUTE_UNUSED) | |
22ef4e9b JL |
1559 | { |
1560 | int size, align; | |
1561 | ||
1562 | /* We only support using 2 data registers as argument registers. */ | |
1563 | int nregs = 2; | |
1564 | ||
1565 | /* Figure out the size of the object to be passed. */ | |
1566 | if (mode == BLKmode) | |
1567 | size = int_size_in_bytes (type); | |
1568 | else | |
1569 | size = GET_MODE_SIZE (mode); | |
1570 | ||
1571 | /* Figure out the alignment of the object to be passed. */ | |
1572 | align = size; | |
1573 | ||
1574 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1575 | ||
1576 | /* Don't pass this arg via a register if all the argument registers | |
1577 | are used up. */ | |
1578 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1579 | return 0; | |
1580 | ||
1581 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1582 | return 0; | |
1583 | ||
1584 | /* Don't pass this arg via a register if it would be split between | |
1585 | registers and memory. */ | |
1586 | if (type == NULL_TREE | |
1587 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1588 | return 0; | |
1589 | ||
1590 | return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD; | |
1591 | } | |
1592 | ||
1593 | /* Output a tst insn. */ | |
1943c2c1 | 1594 | const char * |
f1777882 | 1595 | output_tst (rtx operand, rtx insn) |
22ef4e9b | 1596 | { |
22ef4e9b JL |
1597 | rtx temp; |
1598 | int past_call = 0; | |
1599 | ||
1600 | /* We can save a byte if we can find a register which has the value | |
1601 | zero in it. */ | |
1602 | temp = PREV_INSN (insn); | |
74452ac3 | 1603 | while (optimize && temp) |
22ef4e9b JL |
1604 | { |
1605 | rtx set; | |
1606 | ||
1607 | /* We allow the search to go through call insns. We record | |
1608 | the fact that we've past a CALL_INSN and reject matches which | |
1609 | use call clobbered registers. */ | |
1610 | if (GET_CODE (temp) == CODE_LABEL | |
1611 | || GET_CODE (temp) == JUMP_INSN | |
1612 | || GET_CODE (temp) == BARRIER) | |
1613 | break; | |
1614 | ||
1615 | if (GET_CODE (temp) == CALL_INSN) | |
1616 | past_call = 1; | |
1617 | ||
1618 | if (GET_CODE (temp) == NOTE) | |
1619 | { | |
1620 | temp = PREV_INSN (temp); | |
1621 | continue; | |
1622 | } | |
1623 | ||
8596d0a1 | 1624 | /* It must be an insn, see if it is a simple set. */ |
22ef4e9b JL |
1625 | set = single_set (temp); |
1626 | if (!set) | |
1627 | { | |
1628 | temp = PREV_INSN (temp); | |
1629 | continue; | |
1630 | } | |
1631 | ||
1632 | /* Are we setting a data register to zero (this does not win for | |
1633 | address registers)? | |
1634 | ||
1635 | If it's a call clobbered register, have we past a call? | |
1636 | ||
1637 | Make sure the register we find isn't the same as ourself; | |
4d1a91c2 JL |
1638 | the mn10300 can't encode that. |
1639 | ||
1640 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1641 | so the code to detect calls here isn't doing anything useful. */ | |
22ef4e9b JL |
1642 | if (REG_P (SET_DEST (set)) |
1643 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1644 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
74452ac3 JL |
1645 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1646 | == REGNO_REG_CLASS (REGNO (operand))) | |
705ac34f JL |
1647 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1648 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
1649 | && (!past_call | |
1650 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1651 | { | |
1652 | rtx xoperands[2]; | |
1653 | xoperands[0] = operand; | |
1654 | xoperands[1] = SET_DEST (set); | |
1655 | ||
1656 | output_asm_insn ("cmp %1,%0", xoperands); | |
1657 | return ""; | |
1658 | } | |
1659 | ||
1660 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1661 | && REG_P (SET_DEST (set)) | |
1662 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1663 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1664 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1665 | != REGNO_REG_CLASS (REGNO (operand))) | |
1666 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
22ef4e9b JL |
1667 | && REGNO (SET_DEST (set)) != REGNO (operand) |
1668 | && (!past_call | |
1669 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1670 | { | |
1671 | rtx xoperands[2]; | |
1672 | xoperands[0] = operand; | |
1673 | xoperands[1] = SET_DEST (set); | |
1674 | ||
1675 | output_asm_insn ("cmp %1,%0", xoperands); | |
1676 | return ""; | |
1677 | } | |
1678 | temp = PREV_INSN (temp); | |
1679 | } | |
1680 | return "cmp 0,%0"; | |
1681 | } | |
460f4b9d JL |
1682 | |
1683 | int | |
f1777882 | 1684 | impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
460f4b9d | 1685 | { |
460f4b9d JL |
1686 | if (GET_CODE (op) != PLUS) |
1687 | return 0; | |
1688 | ||
4c742813 JL |
1689 | if (XEXP (op, 0) == stack_pointer_rtx |
1690 | || XEXP (op, 1) == stack_pointer_rtx) | |
460f4b9d JL |
1691 | return 1; |
1692 | ||
460f4b9d JL |
1693 | return 0; |
1694 | } | |
e9ad4573 | 1695 | |
f8912297 JL |
1696 | /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used |
1697 | for the btst insn which may examine memory or a register (the memory | |
1698 | variant only allows an unsigned 8 bit integer). */ | |
1699 | int | |
f1777882 | 1700 | const_8bit_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
f8912297 JL |
1701 | { |
1702 | return (GET_CODE (op) == CONST_INT | |
1703 | && INTVAL (op) >= 0 | |
1704 | && INTVAL (op) < 256); | |
1705 | } | |
1706 | ||
18e9d2f9 AO |
1707 | /* Return true if the operand is the 1.0f constant. */ |
1708 | int | |
f1777882 | 1709 | const_1f_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
18e9d2f9 AO |
1710 | { |
1711 | return (op == CONST1_RTX (SFmode)); | |
1712 | } | |
1713 | ||
f8912297 JL |
1714 | /* Similarly, but when using a zero_extract pattern for a btst where |
1715 | the source operand might end up in memory. */ | |
1716 | int | |
f1777882 | 1717 | mask_ok_for_mem_btst (int len, int bit) |
f8912297 | 1718 | { |
4977bab6 | 1719 | unsigned int mask = 0; |
f8912297 JL |
1720 | |
1721 | while (len > 0) | |
1722 | { | |
1723 | mask |= (1 << bit); | |
1724 | bit++; | |
1725 | len--; | |
1726 | } | |
1727 | ||
1728 | /* MASK must bit into an 8bit value. */ | |
1729 | return (((mask & 0xff) == mask) | |
1730 | || ((mask & 0xff00) == mask) | |
1731 | || ((mask & 0xff0000) == mask) | |
1732 | || ((mask & 0xff000000) == mask)); | |
1733 | } | |
1734 | ||
e9ad4573 JL |
1735 | /* Return 1 if X contains a symbolic expression. We know these |
1736 | expressions will have one of a few well defined forms, so | |
1737 | we need only check those forms. */ | |
1738 | int | |
f1777882 | 1739 | symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e9ad4573 JL |
1740 | { |
1741 | switch (GET_CODE (op)) | |
1742 | { | |
1743 | case SYMBOL_REF: | |
1744 | case LABEL_REF: | |
1745 | return 1; | |
1746 | case CONST: | |
1747 | op = XEXP (op, 0); | |
1748 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1749 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
1750 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
1751 | default: | |
1752 | return 0; | |
1753 | } | |
1754 | } | |
1755 | ||
1756 | /* Try machine dependent ways of modifying an illegitimate address | |
1757 | to be legitimate. If we find one, return the new valid address. | |
1758 | This macro is used in only one place: `memory_address' in explow.c. | |
1759 | ||
1760 | OLDX is the address as it was before break_out_memory_refs was called. | |
1761 | In some cases it is useful to look at this to decide what needs to be done. | |
1762 | ||
1763 | MODE and WIN are passed so that this macro can use | |
1764 | GO_IF_LEGITIMATE_ADDRESS. | |
1765 | ||
1766 | Normally it is always safe for this macro to do nothing. It exists to | |
1767 | recognize opportunities to optimize the output. | |
1768 | ||
1769 | But on a few ports with segmented architectures and indexed addressing | |
1770 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
1771 | rtx | |
f1777882 KH |
1772 | legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1773 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
e9ad4573 | 1774 | { |
d1776069 AO |
1775 | if (flag_pic && ! legitimate_pic_operand_p (x)) |
1776 | x = legitimize_pic_address (oldx, NULL_RTX); | |
1777 | ||
e9ad4573 JL |
1778 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1779 | special handling to avoid creating an indexed memory address | |
1780 | with x-100000 as the base. */ | |
1781 | if (GET_CODE (x) == PLUS | |
1782 | && symbolic_operand (XEXP (x, 1), VOIDmode)) | |
1783 | { | |
1784 | /* Ugly. We modify things here so that the address offset specified | |
1785 | by the index expression is computed first, then added to x to form | |
1786 | the entire address. */ | |
1787 | ||
69bc71fa | 1788 | rtx regx1, regy1, regy2, y; |
e9ad4573 JL |
1789 | |
1790 | /* Strip off any CONST. */ | |
1791 | y = XEXP (x, 1); | |
1792 | if (GET_CODE (y) == CONST) | |
1793 | y = XEXP (y, 0); | |
1794 | ||
bf4219f0 JL |
1795 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1796 | { | |
1797 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1798 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1799 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1800 | regx1 = force_reg (Pmode, | |
1801 | gen_rtx (GET_CODE (y), Pmode, regx1, regy2)); | |
c5c76735 | 1802 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
bf4219f0 | 1803 | } |
e9ad4573 | 1804 | } |
371036e0 | 1805 | return x; |
e9ad4573 | 1806 | } |
460ad325 | 1807 | |
d1776069 | 1808 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
8596d0a1 | 1809 | @GOTOFF in `reg'. */ |
d1776069 | 1810 | rtx |
f1777882 | 1811 | legitimize_pic_address (rtx orig, rtx reg) |
d1776069 AO |
1812 | { |
1813 | if (GET_CODE (orig) == LABEL_REF | |
1814 | || (GET_CODE (orig) == SYMBOL_REF | |
1815 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1816 | || ! MN10300_GLOBAL_P (orig)))) | |
1817 | { | |
1818 | if (reg == 0) | |
1819 | reg = gen_reg_rtx (Pmode); | |
1820 | ||
1821 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
1822 | return reg; | |
1823 | } | |
1824 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1825 | { | |
1826 | if (reg == 0) | |
1827 | reg = gen_reg_rtx (Pmode); | |
1828 | ||
1829 | emit_insn (gen_symGOT2reg (reg, orig)); | |
1830 | return reg; | |
1831 | } | |
1832 | return orig; | |
1833 | } | |
1834 | ||
1835 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
4375e090 | 1836 | isn't protected by a PIC unspec; nonzero otherwise. */ |
d1776069 | 1837 | int |
f1777882 | 1838 | legitimate_pic_operand_p (rtx x) |
d1776069 AO |
1839 | { |
1840 | register const char *fmt; | |
1841 | register int i; | |
1842 | ||
1843 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1844 | return 0; | |
1845 | ||
1846 | if (GET_CODE (x) == UNSPEC | |
1847 | && (XINT (x, 1) == UNSPEC_PIC | |
1848 | || XINT (x, 1) == UNSPEC_GOT | |
1849 | || XINT (x, 1) == UNSPEC_GOTOFF | |
1850 | || XINT (x, 1) == UNSPEC_PLT)) | |
1851 | return 1; | |
1852 | ||
1853 | if (GET_CODE (x) == QUEUED) | |
1854 | return legitimate_pic_operand_p (QUEUED_VAR (x)); | |
1855 | ||
1856 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
1857 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1858 | { | |
1859 | if (fmt[i] == 'E') | |
1860 | { | |
1861 | register int j; | |
1862 | ||
1863 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1864 | if (! legitimate_pic_operand_p (XVECEXP (x, i, j))) | |
1865 | return 0; | |
1866 | } | |
1867 | else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i))) | |
1868 | return 0; | |
1869 | } | |
1870 | ||
1871 | return 1; | |
1872 | } | |
1873 | ||
dcefdf67 | 1874 | static int |
f1777882 | 1875 | mn10300_address_cost_1 (rtx x, int *unsig) |
460ad325 | 1876 | { |
460ad325 AO |
1877 | switch (GET_CODE (x)) |
1878 | { | |
1879 | case REG: | |
1880 | switch (REGNO_REG_CLASS (REGNO (x))) | |
1881 | { | |
1882 | case SP_REGS: | |
1883 | *unsig = 1; | |
1884 | return 0; | |
1885 | ||
1886 | case ADDRESS_REGS: | |
1887 | return 1; | |
1888 | ||
1889 | case DATA_REGS: | |
1890 | case EXTENDED_REGS: | |
18e9d2f9 | 1891 | case FP_REGS: |
460ad325 AO |
1892 | return 3; |
1893 | ||
1894 | case NO_REGS: | |
1895 | return 5; | |
1896 | ||
1897 | default: | |
1898 | abort (); | |
1899 | } | |
1900 | ||
1901 | case PLUS: | |
1902 | case MINUS: | |
d82704fb AO |
1903 | case ASHIFT: |
1904 | case AND: | |
460ad325 | 1905 | case IOR: |
dcefdf67 RH |
1906 | return (mn10300_address_cost_1 (XEXP (x, 0), unsig) |
1907 | + mn10300_address_cost_1 (XEXP (x, 1), unsig)); | |
460ad325 AO |
1908 | |
1909 | case EXPR_LIST: | |
1910 | case SUBREG: | |
1911 | case MEM: | |
dcefdf67 | 1912 | return mn10300_address_cost (XEXP (x, 0)); |
460ad325 AO |
1913 | |
1914 | case ZERO_EXTEND: | |
1915 | *unsig = 1; | |
dcefdf67 | 1916 | return mn10300_address_cost_1 (XEXP (x, 0), unsig); |
460ad325 AO |
1917 | |
1918 | case CONST_INT: | |
1919 | if (INTVAL (x) == 0) | |
1920 | return 0; | |
1921 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
1922 | return 1; | |
1923 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
1924 | return 3; | |
1925 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
1926 | return 5; | |
1927 | return 7; | |
1928 | ||
1929 | case CONST: | |
1930 | case SYMBOL_REF: | |
d82704fb | 1931 | case LABEL_REF: |
460ad325 AO |
1932 | return 8; |
1933 | ||
1934 | case ADDRESSOF: | |
1935 | switch (GET_CODE (XEXP (x, 0))) | |
1936 | { | |
1937 | case MEM: | |
dcefdf67 | 1938 | return mn10300_address_cost (XEXP (x, 0)); |
460ad325 AO |
1939 | |
1940 | case REG: | |
1941 | return 1; | |
1942 | ||
1943 | default: | |
1944 | abort (); | |
1945 | } | |
1946 | ||
1947 | default: | |
1948 | abort (); | |
1949 | ||
1950 | } | |
1951 | } | |
3c50106f | 1952 | |
dcefdf67 | 1953 | static int |
f1777882 | 1954 | mn10300_address_cost (rtx x) |
dcefdf67 RH |
1955 | { |
1956 | int s = 0; | |
1957 | return mn10300_address_cost_1 (x, &s); | |
1958 | } | |
1959 | ||
3c50106f | 1960 | static bool |
f1777882 | 1961 | mn10300_rtx_costs (rtx x, int code, int outer_code, int *total) |
3c50106f RH |
1962 | { |
1963 | switch (code) | |
1964 | { | |
1965 | case CONST_INT: | |
1966 | /* Zeros are extremely cheap. */ | |
1967 | if (INTVAL (x) == 0 && outer_code == SET) | |
1968 | *total = 0; | |
1969 | /* If it fits in 8 bits, then it's still relatively cheap. */ | |
1970 | else if (INT_8_BITS (INTVAL (x))) | |
1971 | *total = 1; | |
1972 | /* This is the "base" cost, includes constants where either the | |
1973 | upper or lower 16bits are all zeros. */ | |
1974 | else if (INT_16_BITS (INTVAL (x)) | |
1975 | || (INTVAL (x) & 0xffff) == 0 | |
1976 | || (INTVAL (x) & 0xffff0000) == 0) | |
1977 | *total = 2; | |
1978 | else | |
1979 | *total = 4; | |
1980 | return true; | |
1981 | ||
1982 | case CONST: | |
1983 | case LABEL_REF: | |
1984 | case SYMBOL_REF: | |
1985 | /* These are more costly than a CONST_INT, but we can relax them, | |
1986 | so they're less costly than a CONST_DOUBLE. */ | |
1987 | *total = 6; | |
1988 | return true; | |
1989 | ||
1990 | case CONST_DOUBLE: | |
1991 | /* We don't optimize CONST_DOUBLEs well nor do we relax them well, | |
1992 | so their cost is very high. */ | |
1993 | *total = 8; | |
1994 | return true; | |
1995 | ||
1996 | /* ??? This probably needs more work. */ | |
1997 | case MOD: | |
1998 | case DIV: | |
1999 | case MULT: | |
2000 | *total = 8; | |
2001 | return true; | |
2002 | ||
2003 | default: | |
2004 | return false; | |
2005 | } | |
2006 | } | |
fe7496dd AO |
2007 | |
2008 | /* Check whether a constant used to initialize a DImode or DFmode can | |
2009 | use a clr instruction. The code here must be kept in sync with | |
2010 | movdf and movdi. */ | |
2011 | ||
2012 | bool | |
f1777882 | 2013 | mn10300_wide_const_load_uses_clr (rtx operands[2]) |
fe7496dd AO |
2014 | { |
2015 | long val[2]; | |
2016 | ||
2017 | if (GET_CODE (operands[0]) != REG | |
2018 | || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS) | |
2019 | return false; | |
2020 | ||
2021 | switch (GET_CODE (operands[1])) | |
2022 | { | |
2023 | case CONST_INT: | |
2024 | { | |
2025 | rtx low, high; | |
2026 | split_double (operands[1], &low, &high); | |
2027 | val[0] = INTVAL (low); | |
2028 | val[1] = INTVAL (high); | |
2029 | } | |
2030 | break; | |
2031 | ||
2032 | case CONST_DOUBLE: | |
2033 | if (GET_MODE (operands[1]) == DFmode) | |
2034 | { | |
2035 | REAL_VALUE_TYPE rv; | |
2036 | ||
2037 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
2038 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
2039 | } | |
2040 | else if (GET_MODE (operands[1]) == VOIDmode | |
2041 | || GET_MODE (operands[1]) == DImode) | |
2042 | { | |
2043 | val[0] = CONST_DOUBLE_LOW (operands[1]); | |
2044 | val[1] = CONST_DOUBLE_HIGH (operands[1]); | |
2045 | } | |
2046 | break; | |
2047 | ||
2048 | default: | |
2049 | return false; | |
2050 | } | |
2051 | ||
2052 | return val[0] == 0 || val[1] == 0; | |
2053 | } | |
d1776069 AO |
2054 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2055 | may access it using GOTOFF instead of GOT. */ | |
2056 | ||
2057 | static void | |
3bc5e4ef | 2058 | mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED) |
d1776069 AO |
2059 | { |
2060 | rtx symbol; | |
2061 | ||
2062 | if (GET_CODE (rtl) != MEM) | |
2063 | return; | |
2064 | symbol = XEXP (rtl, 0); | |
2065 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2066 | return; | |
2067 | ||
2068 | if (flag_pic) | |
2069 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2070 | } |