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11bb1f11 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
d1e082c2 | 2 | Copyright (C) 1996-2013 Free Software Foundation, Inc. |
11bb1f11 JL |
3 | Contributed by Jeff Law (law@cygnus.com). |
4 | ||
e7ab5593 | 5 | This file is part of GCC. |
11bb1f11 | 6 | |
e7ab5593 NC |
7 | GCC is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11bb1f11 | 11 | |
e7ab5593 NC |
12 | GCC is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
11bb1f11 | 16 | |
e7ab5593 NC |
17 | You should have received a copy of the GNU General Public License |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
11bb1f11 | 20 | |
11bb1f11 | 21 | #include "config.h" |
c5c76735 | 22 | #include "system.h" |
4977bab6 ZW |
23 | #include "coretypes.h" |
24 | #include "tm.h" | |
11bb1f11 | 25 | #include "rtl.h" |
bf6bb899 | 26 | #include "tree.h" |
11bb1f11 JL |
27 | #include "regs.h" |
28 | #include "hard-reg-set.h" | |
11bb1f11 JL |
29 | #include "insn-config.h" |
30 | #include "conditions.h" | |
11bb1f11 JL |
31 | #include "output.h" |
32 | #include "insn-attr.h" | |
33 | #include "flags.h" | |
34 | #include "recog.h" | |
6528281d | 35 | #include "reload.h" |
11bb1f11 | 36 | #include "expr.h" |
e78d8e51 | 37 | #include "optabs.h" |
bf6bb899 | 38 | #include "function.h" |
11bb1f11 | 39 | #include "obstack.h" |
718f9c0f | 40 | #include "diagnostic-core.h" |
69bc71fa | 41 | #include "tm_p.h" |
a45d420a | 42 | #include "tm-constrs.h" |
672a6f42 NB |
43 | #include "target.h" |
44 | #include "target-def.h" | |
4af476d7 | 45 | #include "df.h" |
96e45421 | 46 | #include "opts.h" |
662c03f4 | 47 | #include "cfgloop.h" |
7ee2468b | 48 | #include "dumpfile.h" |
11bb1f11 | 49 | |
2beef00e AO |
50 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
51 | names are not prefixed by underscores, to tell whether to prefix a | |
52 | label with a plus sign or not, so that the assembler can tell | |
53 | symbol names from register names. */ | |
54 | int mn10300_protect_label; | |
55 | ||
f3f63737 NC |
56 | /* Selected processor type for tuning. */ |
57 | enum processor_type mn10300_tune_cpu = PROCESSOR_DEFAULT; | |
58 | ||
bad41521 RH |
59 | #define CC_FLAG_Z 1 |
60 | #define CC_FLAG_N 2 | |
61 | #define CC_FLAG_C 4 | |
62 | #define CC_FLAG_V 8 | |
63 | ||
64 | static int cc_flags_for_mode(enum machine_mode); | |
65 | static int cc_flags_for_code(enum rtx_code); | |
672a6f42 | 66 | \f |
c5387660 | 67 | /* Implement TARGET_OPTION_OVERRIDE. */ |
13dd556c | 68 | |
c5387660 JM |
69 | static void |
70 | mn10300_option_override (void) | |
13dd556c RS |
71 | { |
72 | if (TARGET_AM33) | |
73 | target_flags &= ~MASK_MULT_BUG; | |
f3f63737 NC |
74 | else |
75 | { | |
76 | /* Disable scheduling for the MN10300 as we do | |
77 | not have timing information available for it. */ | |
78 | flag_schedule_insns = 0; | |
79 | flag_schedule_insns_after_reload = 0; | |
ec815d65 RH |
80 | |
81 | /* Force enable splitting of wide types, as otherwise it is trivial | |
82 | to run out of registers. Indeed, this works so well that register | |
83 | allocation problems are now more common *without* optimization, | |
84 | when this flag is not enabled by default. */ | |
85 | flag_split_wide_types = 1; | |
f3f63737 | 86 | } |
bad41521 | 87 | |
f3f63737 NC |
88 | if (mn10300_tune_string) |
89 | { | |
90 | if (strcasecmp (mn10300_tune_string, "mn10300") == 0) | |
91 | mn10300_tune_cpu = PROCESSOR_MN10300; | |
92 | else if (strcasecmp (mn10300_tune_string, "am33") == 0) | |
93 | mn10300_tune_cpu = PROCESSOR_AM33; | |
94 | else if (strcasecmp (mn10300_tune_string, "am33-2") == 0) | |
95 | mn10300_tune_cpu = PROCESSOR_AM33_2; | |
96 | else if (strcasecmp (mn10300_tune_string, "am34") == 0) | |
97 | mn10300_tune_cpu = PROCESSOR_AM34; | |
98 | else | |
99 | error ("-mtune= expects mn10300, am33, am33-2, or am34"); | |
100 | } | |
13dd556c RS |
101 | } |
102 | ||
1bc7c5b6 | 103 | static void |
f1777882 | 104 | mn10300_file_start (void) |
11bb1f11 | 105 | { |
1bc7c5b6 | 106 | default_file_start (); |
705ac34f | 107 | |
18e9d2f9 AO |
108 | if (TARGET_AM33_2) |
109 | fprintf (asm_out_file, "\t.am33_2\n"); | |
110 | else if (TARGET_AM33) | |
1bc7c5b6 | 111 | fprintf (asm_out_file, "\t.am33\n"); |
11bb1f11 JL |
112 | } |
113 | \f | |
298362c8 NC |
114 | /* Note: This list must match the liw_op attribute in mn10300.md. */ |
115 | ||
116 | static const char *liw_op_names[] = | |
117 | { | |
118 | "add", "cmp", "sub", "mov", | |
119 | "and", "or", "xor", | |
120 | "asr", "lsr", "asl", | |
121 | "none", "max" | |
122 | }; | |
123 | ||
11bb1f11 JL |
124 | /* Print operand X using operand code CODE to assembly language output file |
125 | FILE. */ | |
126 | ||
127 | void | |
e7ab5593 | 128 | mn10300_print_operand (FILE *file, rtx x, int code) |
11bb1f11 JL |
129 | { |
130 | switch (code) | |
131 | { | |
298362c8 NC |
132 | case 'W': |
133 | { | |
134 | unsigned int liw_op = UINTVAL (x); | |
bad41521 | 135 | |
298362c8 NC |
136 | gcc_assert (TARGET_ALLOW_LIW); |
137 | gcc_assert (liw_op < LIW_OP_MAX); | |
138 | fputs (liw_op_names[liw_op], file); | |
11bb1f11 | 139 | break; |
298362c8 | 140 | } |
bad41521 | 141 | |
298362c8 NC |
142 | case 'b': |
143 | case 'B': | |
144 | { | |
145 | enum rtx_code cmp = GET_CODE (x); | |
146 | enum machine_mode mode = GET_MODE (XEXP (x, 0)); | |
147 | const char *str; | |
148 | int have_flags; | |
149 | ||
150 | if (code == 'B') | |
151 | cmp = reverse_condition (cmp); | |
152 | have_flags = cc_flags_for_mode (mode); | |
5abc5de9 | 153 | |
298362c8 | 154 | switch (cmp) |
18e9d2f9 | 155 | { |
298362c8 NC |
156 | case NE: |
157 | str = "ne"; | |
18e9d2f9 | 158 | break; |
298362c8 NC |
159 | case EQ: |
160 | str = "eq"; | |
161 | break; | |
162 | case GE: | |
163 | /* bge is smaller than bnc. */ | |
164 | str = (have_flags & CC_FLAG_V ? "ge" : "nc"); | |
165 | break; | |
166 | case LT: | |
167 | str = (have_flags & CC_FLAG_V ? "lt" : "ns"); | |
168 | break; | |
169 | case GT: | |
170 | str = "gt"; | |
171 | break; | |
172 | case LE: | |
173 | str = "le"; | |
174 | break; | |
175 | case GEU: | |
176 | str = "cc"; | |
177 | break; | |
178 | case GTU: | |
179 | str = "hi"; | |
180 | break; | |
181 | case LEU: | |
182 | str = "ls"; | |
183 | break; | |
184 | case LTU: | |
185 | str = "cs"; | |
186 | break; | |
187 | case ORDERED: | |
188 | str = "lge"; | |
189 | break; | |
190 | case UNORDERED: | |
191 | str = "uo"; | |
192 | break; | |
193 | case LTGT: | |
194 | str = "lg"; | |
195 | break; | |
196 | case UNEQ: | |
197 | str = "ue"; | |
198 | break; | |
199 | case UNGE: | |
200 | str = "uge"; | |
201 | break; | |
202 | case UNGT: | |
203 | str = "ug"; | |
204 | break; | |
205 | case UNLE: | |
206 | str = "ule"; | |
207 | break; | |
208 | case UNLT: | |
209 | str = "ul"; | |
18e9d2f9 | 210 | break; |
18e9d2f9 | 211 | default: |
dc759020 | 212 | gcc_unreachable (); |
18e9d2f9 | 213 | } |
298362c8 NC |
214 | |
215 | gcc_checking_assert ((cc_flags_for_code (cmp) & ~have_flags) == 0); | |
216 | fputs (str, file); | |
217 | } | |
218 | break; | |
219 | ||
220 | case 'C': | |
221 | /* This is used for the operand to a call instruction; | |
222 | if it's a REG, enclose it in parens, else output | |
223 | the operand normally. */ | |
224 | if (REG_P (x)) | |
225 | { | |
226 | fputc ('(', file); | |
227 | mn10300_print_operand (file, x, 0); | |
228 | fputc (')', file); | |
229 | } | |
230 | else | |
231 | mn10300_print_operand (file, x, 0); | |
232 | break; | |
233 | ||
234 | case 'D': | |
235 | switch (GET_CODE (x)) | |
236 | { | |
237 | case MEM: | |
238 | fputc ('(', file); | |
239 | output_address (XEXP (x, 0)); | |
240 | fputc (')', file); | |
241 | break; | |
242 | ||
243 | case REG: | |
244 | fprintf (file, "fd%d", REGNO (x) - 18); | |
245 | break; | |
246 | ||
247 | default: | |
248 | gcc_unreachable (); | |
249 | } | |
250 | break; | |
18e9d2f9 | 251 | |
38c37a0e | 252 | /* These are the least significant word in a 64bit value. */ |
298362c8 NC |
253 | case 'L': |
254 | switch (GET_CODE (x)) | |
255 | { | |
256 | case MEM: | |
257 | fputc ('(', file); | |
258 | output_address (XEXP (x, 0)); | |
259 | fputc (')', file); | |
260 | break; | |
38c37a0e | 261 | |
298362c8 NC |
262 | case REG: |
263 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
264 | break; | |
38c37a0e | 265 | |
298362c8 NC |
266 | case SUBREG: |
267 | fprintf (file, "%s", reg_names[subreg_regno (x)]); | |
268 | break; | |
38c37a0e | 269 | |
298362c8 NC |
270 | case CONST_DOUBLE: |
271 | { | |
272 | long val[2]; | |
273 | REAL_VALUE_TYPE rv; | |
38c37a0e | 274 | |
298362c8 NC |
275 | switch (GET_MODE (x)) |
276 | { | |
277 | case DFmode: | |
278 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
279 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
280 | fprintf (file, "0x%lx", val[0]); | |
281 | break;; | |
282 | case SFmode: | |
283 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
284 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
285 | fprintf (file, "0x%lx", val[0]); | |
286 | break;; | |
287 | case VOIDmode: | |
288 | case DImode: | |
289 | mn10300_print_operand_address (file, | |
290 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
291 | break; | |
292 | default: | |
38c37a0e JL |
293 | break; |
294 | } | |
298362c8 NC |
295 | break; |
296 | } | |
38c37a0e | 297 | |
298362c8 NC |
298 | case CONST_INT: |
299 | { | |
300 | rtx low, high; | |
301 | split_double (x, &low, &high); | |
302 | fprintf (file, "%ld", (long)INTVAL (low)); | |
303 | break; | |
212bc5fa | 304 | } |
38c37a0e | 305 | |
298362c8 NC |
306 | default: |
307 | gcc_unreachable (); | |
308 | } | |
309 | break; | |
38c37a0e JL |
310 | |
311 | /* Similarly, but for the most significant word. */ | |
298362c8 NC |
312 | case 'H': |
313 | switch (GET_CODE (x)) | |
314 | { | |
315 | case MEM: | |
316 | fputc ('(', file); | |
317 | x = adjust_address (x, SImode, 4); | |
318 | output_address (XEXP (x, 0)); | |
319 | fputc (')', file); | |
320 | break; | |
38c37a0e | 321 | |
298362c8 NC |
322 | case REG: |
323 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
324 | break; | |
38c37a0e | 325 | |
298362c8 NC |
326 | case SUBREG: |
327 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); | |
328 | break; | |
38c37a0e | 329 | |
298362c8 NC |
330 | case CONST_DOUBLE: |
331 | { | |
332 | long val[2]; | |
333 | REAL_VALUE_TYPE rv; | |
38c37a0e | 334 | |
298362c8 NC |
335 | switch (GET_MODE (x)) |
336 | { | |
337 | case DFmode: | |
338 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
339 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
340 | fprintf (file, "0x%lx", val[1]); | |
341 | break;; | |
342 | case SFmode: | |
343 | gcc_unreachable (); | |
344 | case VOIDmode: | |
345 | case DImode: | |
346 | mn10300_print_operand_address (file, | |
347 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
348 | break; | |
349 | default: | |
38c37a0e JL |
350 | break; |
351 | } | |
298362c8 NC |
352 | break; |
353 | } | |
38c37a0e | 354 | |
298362c8 NC |
355 | case CONST_INT: |
356 | { | |
357 | rtx low, high; | |
358 | split_double (x, &low, &high); | |
359 | fprintf (file, "%ld", (long)INTVAL (high)); | |
360 | break; | |
38c37a0e | 361 | } |
38c37a0e | 362 | |
298362c8 NC |
363 | default: |
364 | gcc_unreachable (); | |
365 | } | |
366 | break; | |
38c37a0e | 367 | |
298362c8 NC |
368 | case 'A': |
369 | fputc ('(', file); | |
370 | if (REG_P (XEXP (x, 0))) | |
371 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx)); | |
372 | else | |
373 | output_address (XEXP (x, 0)); | |
374 | fputc (')', file); | |
375 | break; | |
a58be199 | 376 | |
298362c8 NC |
377 | case 'N': |
378 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); | |
379 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); | |
380 | break; | |
381 | ||
382 | case 'U': | |
383 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); | |
384 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); | |
385 | break; | |
6fafc523 | 386 | |
576e5acc JL |
387 | /* For shift counts. The hardware ignores the upper bits of |
388 | any immediate, but the assembler will flag an out of range | |
389 | shift count as an error. So we mask off the high bits | |
390 | of the immediate here. */ | |
298362c8 NC |
391 | case 'S': |
392 | if (CONST_INT_P (x)) | |
393 | { | |
394 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); | |
395 | break; | |
396 | } | |
397 | /* FALL THROUGH */ | |
576e5acc | 398 | |
298362c8 NC |
399 | default: |
400 | switch (GET_CODE (x)) | |
401 | { | |
402 | case MEM: | |
403 | fputc ('(', file); | |
404 | output_address (XEXP (x, 0)); | |
405 | fputc (')', file); | |
406 | break; | |
11bb1f11 | 407 | |
298362c8 NC |
408 | case PLUS: |
409 | output_address (x); | |
410 | break; | |
38c37a0e | 411 | |
298362c8 NC |
412 | case REG: |
413 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
414 | break; | |
11bb1f11 | 415 | |
298362c8 NC |
416 | case SUBREG: |
417 | fprintf (file, "%s", reg_names[subreg_regno (x)]); | |
418 | break; | |
11bb1f11 | 419 | |
38c37a0e | 420 | /* This will only be single precision.... */ |
298362c8 NC |
421 | case CONST_DOUBLE: |
422 | { | |
423 | unsigned long val; | |
424 | REAL_VALUE_TYPE rv; | |
38c37a0e | 425 | |
298362c8 NC |
426 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); |
427 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
428 | fprintf (file, "0x%lx", val); | |
11bb1f11 | 429 | break; |
11bb1f11 | 430 | } |
298362c8 NC |
431 | |
432 | case CONST_INT: | |
433 | case SYMBOL_REF: | |
434 | case CONST: | |
435 | case LABEL_REF: | |
436 | case CODE_LABEL: | |
437 | case UNSPEC: | |
438 | mn10300_print_operand_address (file, x); | |
439 | break; | |
440 | default: | |
441 | gcc_unreachable (); | |
442 | } | |
443 | break; | |
444 | } | |
11bb1f11 JL |
445 | } |
446 | ||
447 | /* Output assembly language output for the address ADDR to FILE. */ | |
448 | ||
449 | void | |
e7ab5593 | 450 | mn10300_print_operand_address (FILE *file, rtx addr) |
11bb1f11 JL |
451 | { |
452 | switch (GET_CODE (addr)) | |
453 | { | |
705ac34f | 454 | case POST_INC: |
36846b26 | 455 | mn10300_print_operand (file, XEXP (addr, 0), 0); |
705ac34f JL |
456 | fputc ('+', file); |
457 | break; | |
36846b26 RH |
458 | |
459 | case POST_MODIFY: | |
460 | mn10300_print_operand (file, XEXP (addr, 0), 0); | |
461 | fputc ('+', file); | |
462 | fputc (',', file); | |
463 | mn10300_print_operand (file, XEXP (addr, 1), 0); | |
464 | break; | |
465 | ||
11bb1f11 | 466 | case REG: |
e7ab5593 | 467 | mn10300_print_operand (file, addr, 0); |
11bb1f11 JL |
468 | break; |
469 | case PLUS: | |
470 | { | |
36846b26 RH |
471 | rtx base = XEXP (addr, 0); |
472 | rtx index = XEXP (addr, 1); | |
473 | ||
474 | if (REG_P (index) && !REG_OK_FOR_INDEX_P (index)) | |
475 | { | |
476 | rtx x = base; | |
477 | base = index; | |
478 | index = x; | |
479 | ||
480 | gcc_assert (REG_P (index) && REG_OK_FOR_INDEX_P (index)); | |
481 | } | |
482 | gcc_assert (REG_OK_FOR_BASE_P (base)); | |
483 | ||
e7ab5593 | 484 | mn10300_print_operand (file, index, 0); |
11bb1f11 | 485 | fputc (',', file); |
36846b26 | 486 | mn10300_print_operand (file, base, 0); |
11bb1f11 JL |
487 | break; |
488 | } | |
489 | case SYMBOL_REF: | |
490 | output_addr_const (file, addr); | |
491 | break; | |
492 | default: | |
493 | output_addr_const (file, addr); | |
494 | break; | |
495 | } | |
496 | } | |
497 | ||
535bd17c AS |
498 | /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. |
499 | ||
500 | Used for PIC-specific UNSPECs. */ | |
501 | ||
502 | static bool | |
503 | mn10300_asm_output_addr_const_extra (FILE *file, rtx x) | |
504 | { | |
505 | if (GET_CODE (x) == UNSPEC) | |
506 | { | |
507 | switch (XINT (x, 1)) | |
508 | { | |
535bd17c AS |
509 | case UNSPEC_PIC: |
510 | /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ | |
511 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
512 | break; | |
513 | case UNSPEC_GOT: | |
514 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
515 | fputs ("@GOT", file); | |
516 | break; | |
517 | case UNSPEC_GOTOFF: | |
518 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
519 | fputs ("@GOTOFF", file); | |
520 | break; | |
521 | case UNSPEC_PLT: | |
522 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
523 | fputs ("@PLT", file); | |
524 | break; | |
525 | case UNSPEC_GOTSYM_OFF: | |
526 | assemble_name (file, GOT_SYMBOL_NAME); | |
527 | fputs ("-(", file); | |
528 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
529 | fputs ("-.)", file); | |
530 | break; | |
531 | default: | |
532 | return false; | |
533 | } | |
534 | return true; | |
535 | } | |
536 | else | |
537 | return false; | |
538 | } | |
539 | ||
18e9d2f9 AO |
540 | /* Count the number of FP registers that have to be saved. */ |
541 | static int | |
f1777882 | 542 | fp_regs_to_save (void) |
18e9d2f9 AO |
543 | { |
544 | int i, n = 0; | |
545 | ||
546 | if (! TARGET_AM33_2) | |
547 | return 0; | |
548 | ||
549 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 550 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
18e9d2f9 AO |
551 | ++n; |
552 | ||
553 | return n; | |
554 | } | |
555 | ||
f6cd7c62 RS |
556 | /* Print a set of registers in the format required by "movm" and "ret". |
557 | Register K is saved if bit K of MASK is set. The data and address | |
558 | registers can be stored individually, but the extended registers cannot. | |
9f5ed61a | 559 | We assume that the mask already takes that into account. For instance, |
8596d0a1 | 560 | bits 14 to 17 must have the same value. */ |
f6cd7c62 RS |
561 | |
562 | void | |
f1777882 | 563 | mn10300_print_reg_list (FILE *file, int mask) |
f6cd7c62 RS |
564 | { |
565 | int need_comma; | |
566 | int i; | |
567 | ||
568 | need_comma = 0; | |
569 | fputc ('[', file); | |
570 | ||
571 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
572 | if ((mask & (1 << i)) != 0) | |
573 | { | |
574 | if (need_comma) | |
575 | fputc (',', file); | |
576 | fputs (reg_names [i], file); | |
577 | need_comma = 1; | |
578 | } | |
579 | ||
580 | if ((mask & 0x3c000) != 0) | |
581 | { | |
dc759020 | 582 | gcc_assert ((mask & 0x3c000) == 0x3c000); |
f6cd7c62 RS |
583 | if (need_comma) |
584 | fputc (',', file); | |
585 | fputs ("exreg1", file); | |
586 | need_comma = 1; | |
587 | } | |
588 | ||
589 | fputc (']', file); | |
590 | } | |
591 | ||
37a185d7 RH |
592 | /* If the MDR register is never clobbered, we can use the RETF instruction |
593 | which takes the address from the MDR register. This is 3 cycles faster | |
594 | than having to load the address from the stack. */ | |
595 | ||
596 | bool | |
597 | mn10300_can_use_retf_insn (void) | |
598 | { | |
599 | /* Don't bother if we're not optimizing. In this case we won't | |
600 | have proper access to df_regs_ever_live_p. */ | |
601 | if (!optimize) | |
602 | return false; | |
603 | ||
604 | /* EH returns alter the saved return address; MDR is not current. */ | |
605 | if (crtl->calls_eh_return) | |
606 | return false; | |
607 | ||
608 | /* Obviously not if MDR is ever clobbered. */ | |
609 | if (df_regs_ever_live_p (MDR_REG)) | |
610 | return false; | |
611 | ||
612 | /* ??? Careful not to use this during expand_epilogue etc. */ | |
613 | gcc_assert (!in_sequence_p ()); | |
614 | return leaf_function_p (); | |
615 | } | |
616 | ||
617 | bool | |
618 | mn10300_can_use_rets_insn (void) | |
38c37a0e | 619 | { |
040c5757 | 620 | return !mn10300_initial_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM); |
38c37a0e JL |
621 | } |
622 | ||
f6cd7c62 RS |
623 | /* Returns the set of live, callee-saved registers as a bitmask. The |
624 | callee-saved extended registers cannot be stored individually, so | |
e902c266 NC |
625 | Also returns the number of bytes in the registers in the mask if |
626 | BYTES_SAVED is not NULL. */ | |
f6cd7c62 | 627 | |
e902c266 NC |
628 | unsigned int |
629 | mn10300_get_live_callee_saved_regs (unsigned int * bytes_saved) | |
f6cd7c62 RS |
630 | { |
631 | int mask; | |
632 | int i; | |
e902c266 | 633 | unsigned int count; |
f6cd7c62 | 634 | |
e902c266 | 635 | count = mask = 0; |
18e9d2f9 | 636 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
9d54866d | 637 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
e902c266 NC |
638 | { |
639 | mask |= (1 << i); | |
640 | ++ count; | |
641 | } | |
642 | ||
f6cd7c62 | 643 | if ((mask & 0x3c000) != 0) |
e902c266 NC |
644 | { |
645 | for (i = 0x04000; i < 0x40000; i <<= 1) | |
646 | if ((mask & i) == 0) | |
647 | ++ count; | |
648 | ||
649 | mask |= 0x3c000; | |
650 | } | |
651 | ||
652 | if (bytes_saved) | |
653 | * bytes_saved = count * UNITS_PER_WORD; | |
f6cd7c62 RS |
654 | |
655 | return mask; | |
656 | } | |
657 | ||
2720cc47 NC |
658 | static rtx |
659 | F (rtx r) | |
660 | { | |
661 | RTX_FRAME_RELATED_P (r) = 1; | |
662 | return r; | |
663 | } | |
664 | ||
f6cd7c62 RS |
665 | /* Generate an instruction that pushes several registers onto the stack. |
666 | Register K will be saved if bit K in MASK is set. The function does | |
667 | nothing if MASK is zero. | |
668 | ||
669 | To be compatible with the "movm" instruction, the lowest-numbered | |
670 | register must be stored in the lowest slot. If MASK is the set | |
671 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
672 | instruction will have the form: | |
673 | ||
674 | (parallel | |
675 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
676 | (set (mem:SI (plus:SI (reg:SI 9) | |
677 | (const_int -1*4))) | |
678 | (reg:SI RN)) | |
679 | ... | |
680 | (set (mem:SI (plus:SI (reg:SI 9) | |
681 | (const_int -N*4))) | |
682 | (reg:SI R1))) */ | |
683 | ||
cc909bba RH |
684 | static void |
685 | mn10300_gen_multiple_store (unsigned int mask) | |
f6cd7c62 | 686 | { |
cc909bba RH |
687 | /* The order in which registers are stored, from SP-4 through SP-N*4. */ |
688 | static const unsigned int store_order[8] = { | |
689 | /* e2, e3: never saved */ | |
690 | FIRST_EXTENDED_REGNUM + 4, | |
691 | FIRST_EXTENDED_REGNUM + 5, | |
692 | FIRST_EXTENDED_REGNUM + 6, | |
693 | FIRST_EXTENDED_REGNUM + 7, | |
694 | /* e0, e1, mdrq, mcrh, mcrl, mcvf: never saved. */ | |
695 | FIRST_DATA_REGNUM + 2, | |
696 | FIRST_DATA_REGNUM + 3, | |
697 | FIRST_ADDRESS_REGNUM + 2, | |
698 | FIRST_ADDRESS_REGNUM + 3, | |
699 | /* d0, d1, a0, a1, mdr, lir, lar: never saved. */ | |
700 | }; | |
701 | ||
702 | rtx x, elts[9]; | |
703 | unsigned int i; | |
704 | int count; | |
705 | ||
706 | if (mask == 0) | |
707 | return; | |
708 | ||
709 | for (i = count = 0; i < ARRAY_SIZE(store_order); ++i) | |
f6cd7c62 | 710 | { |
cc909bba RH |
711 | unsigned regno = store_order[i]; |
712 | ||
713 | if (((mask >> regno) & 1) == 0) | |
714 | continue; | |
f6cd7c62 | 715 | |
cc909bba | 716 | ++count; |
0a81f074 | 717 | x = plus_constant (Pmode, stack_pointer_rtx, count * -4); |
cc909bba RH |
718 | x = gen_frame_mem (SImode, x); |
719 | x = gen_rtx_SET (VOIDmode, x, gen_rtx_REG (SImode, regno)); | |
720 | elts[count] = F(x); | |
721 | ||
722 | /* Remove the register from the mask so that... */ | |
723 | mask &= ~(1u << regno); | |
f6cd7c62 | 724 | } |
cc909bba RH |
725 | |
726 | /* ... we can make sure that we didn't try to use a register | |
727 | not listed in the store order. */ | |
728 | gcc_assert (mask == 0); | |
729 | ||
730 | /* Create the instruction that updates the stack pointer. */ | |
0a81f074 | 731 | x = plus_constant (Pmode, stack_pointer_rtx, count * -4); |
cc909bba RH |
732 | x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x); |
733 | elts[0] = F(x); | |
734 | ||
735 | /* We need one PARALLEL element to update the stack pointer and | |
736 | an additional element for each register that is stored. */ | |
737 | x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (count + 1, elts)); | |
738 | F (emit_insn (x)); | |
f6cd7c62 RS |
739 | } |
740 | ||
11bb1f11 | 741 | void |
e7ab5593 | 742 | mn10300_expand_prologue (void) |
11bb1f11 | 743 | { |
040c5757 | 744 | HOST_WIDE_INT size = mn10300_frame_size (); |
11bb1f11 | 745 | |
d13abe1e NC |
746 | if (flag_stack_usage_info) |
747 | current_function_static_stack_size = size; | |
748 | ||
8596d0a1 | 749 | /* If we use any of the callee-saved registers, save them now. */ |
e902c266 | 750 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs (NULL)); |
777fbf09 | 751 | |
18e9d2f9 AO |
752 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
753 | { | |
754 | int num_regs_to_save = fp_regs_to_save (), i; | |
755 | HOST_WIDE_INT xsize; | |
e7ab5593 NC |
756 | enum |
757 | { | |
758 | save_sp_merge, | |
759 | save_sp_no_merge, | |
760 | save_sp_partial_merge, | |
761 | save_a0_merge, | |
762 | save_a0_no_merge | |
763 | } strategy; | |
18e9d2f9 AO |
764 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; |
765 | rtx reg; | |
18e9d2f9 AO |
766 | |
767 | /* We have several different strategies to save FP registers. | |
768 | We can store them using SP offsets, which is beneficial if | |
769 | there are just a few registers to save, or we can use `a0' in | |
770 | post-increment mode (`a0' is the only call-clobbered address | |
771 | register that is never used to pass information to a | |
772 | function). Furthermore, if we don't need a frame pointer, we | |
773 | can merge the two SP adds into a single one, but this isn't | |
774 | always beneficial; sometimes we can just split the two adds | |
775 | so that we don't exceed a 16-bit constant size. The code | |
776 | below will select which strategy to use, so as to generate | |
777 | smallest code. Ties are broken in favor or shorter sequences | |
778 | (in terms of number of instructions). */ | |
779 | ||
780 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
781 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
782 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
783 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
f4a88680 JR |
784 | |
785 | /* We add 0 * (S) in two places to promote to the type of S, | |
786 | so that all arms of the conditional have the same type. */ | |
18e9d2f9 | 787 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ |
f4a88680 | 788 | (((S) >= (L)) ? 0 * (S) + (SIZE1) * (N) \ |
18e9d2f9 AO |
789 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ |
790 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
f4a88680 | 791 | : 0 * (S) + (ELSE)) |
18e9d2f9 AO |
792 | #define SIZE_FMOV_SP_(S,N) \ |
793 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
794 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
795 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
796 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
797 | ||
798 | /* Consider alternative save_sp_merge only if we don't need the | |
4375e090 | 799 | frame pointer and size is nonzero. */ |
18e9d2f9 AO |
800 | if (! frame_pointer_needed && size) |
801 | { | |
802 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
803 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
804 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
805 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
806 | ||
807 | if (this_strategy_size < strategy_size) | |
808 | { | |
809 | strategy = save_sp_merge; | |
810 | strategy_size = this_strategy_size; | |
811 | } | |
812 | } | |
813 | ||
814 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
815 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
816 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
817 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
818 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
819 | if (size) | |
820 | { | |
821 | /* Insn: add -size, sp. */ | |
822 | this_strategy_size += SIZE_ADD_SP (-size); | |
823 | } | |
824 | ||
825 | if (this_strategy_size < strategy_size) | |
826 | { | |
827 | strategy = save_sp_no_merge; | |
828 | strategy_size = this_strategy_size; | |
829 | } | |
830 | ||
831 | /* Consider alternative save_sp_partial_merge only if we don't | |
832 | need a frame pointer and size is reasonably large. */ | |
833 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
834 | { | |
835 | /* Insn: add -128, sp. */ | |
836 | this_strategy_size = SIZE_ADD_SP (-128); | |
837 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
838 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
839 | num_regs_to_save); | |
840 | if (size) | |
841 | { | |
842 | /* Insn: add 128-size, sp. */ | |
843 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
844 | } | |
845 | ||
846 | if (this_strategy_size < strategy_size) | |
847 | { | |
848 | strategy = save_sp_partial_merge; | |
849 | strategy_size = this_strategy_size; | |
850 | } | |
851 | } | |
852 | ||
853 | /* Consider alternative save_a0_merge only if we don't need a | |
4375e090 | 854 | frame pointer, size is nonzero and the user hasn't |
18e9d2f9 AO |
855 | changed the calling conventions of a0. */ |
856 | if (! frame_pointer_needed && size | |
9d54866d | 857 | && call_really_used_regs [FIRST_ADDRESS_REGNUM] |
18e9d2f9 AO |
858 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
859 | { | |
860 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
861 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
862 | /* Insn: mov sp, a0. */ | |
863 | this_strategy_size++; | |
864 | if (size) | |
865 | { | |
866 | /* Insn: add size, a0. */ | |
867 | this_strategy_size += SIZE_ADD_AX (size); | |
868 | } | |
869 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
870 | this_strategy_size += 3 * num_regs_to_save; | |
871 | ||
872 | if (this_strategy_size < strategy_size) | |
873 | { | |
874 | strategy = save_a0_merge; | |
875 | strategy_size = this_strategy_size; | |
876 | } | |
877 | } | |
878 | ||
879 | /* Consider alternative save_a0_no_merge if the user hasn't | |
8596d0a1 | 880 | changed the calling conventions of a0. */ |
9d54866d | 881 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM] |
18e9d2f9 AO |
882 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
883 | { | |
884 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
885 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
886 | /* Insn: mov sp, a0. */ | |
887 | this_strategy_size++; | |
888 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
889 | this_strategy_size += 3 * num_regs_to_save; | |
890 | if (size) | |
891 | { | |
892 | /* Insn: add -size, sp. */ | |
893 | this_strategy_size += SIZE_ADD_SP (-size); | |
894 | } | |
895 | ||
896 | if (this_strategy_size < strategy_size) | |
897 | { | |
898 | strategy = save_a0_no_merge; | |
899 | strategy_size = this_strategy_size; | |
900 | } | |
901 | } | |
902 | ||
903 | /* Emit the initial SP add, common to all strategies. */ | |
904 | switch (strategy) | |
905 | { | |
906 | case save_sp_no_merge: | |
907 | case save_a0_no_merge: | |
2720cc47 NC |
908 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
909 | stack_pointer_rtx, | |
910 | GEN_INT (-4 * num_regs_to_save)))); | |
18e9d2f9 AO |
911 | xsize = 0; |
912 | break; | |
913 | ||
914 | case save_sp_partial_merge: | |
2720cc47 NC |
915 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
916 | stack_pointer_rtx, | |
917 | GEN_INT (-128)))); | |
18e9d2f9 AO |
918 | xsize = 128 - 4 * num_regs_to_save; |
919 | size -= xsize; | |
920 | break; | |
921 | ||
922 | case save_sp_merge: | |
923 | case save_a0_merge: | |
2720cc47 NC |
924 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
925 | stack_pointer_rtx, | |
926 | GEN_INT (-(size + 4 * num_regs_to_save))))); | |
18e9d2f9 | 927 | /* We'll have to adjust FP register saves according to the |
8596d0a1 | 928 | frame size. */ |
18e9d2f9 AO |
929 | xsize = size; |
930 | /* Since we've already created the stack frame, don't do it | |
8596d0a1 | 931 | again at the end of the function. */ |
18e9d2f9 AO |
932 | size = 0; |
933 | break; | |
934 | ||
935 | default: | |
dc759020 | 936 | gcc_unreachable (); |
18e9d2f9 | 937 | } |
5abc5de9 | 938 | |
18e9d2f9 AO |
939 | /* Now prepare register a0, if we have decided to use it. */ |
940 | switch (strategy) | |
941 | { | |
942 | case save_sp_merge: | |
943 | case save_sp_no_merge: | |
944 | case save_sp_partial_merge: | |
945 | reg = 0; | |
946 | break; | |
947 | ||
948 | case save_a0_merge: | |
949 | case save_a0_no_merge: | |
950 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
2720cc47 | 951 | F (emit_insn (gen_movsi (reg, stack_pointer_rtx))); |
18e9d2f9 | 952 | if (xsize) |
2720cc47 | 953 | F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)))); |
18e9d2f9 AO |
954 | reg = gen_rtx_POST_INC (SImode, reg); |
955 | break; | |
5abc5de9 | 956 | |
18e9d2f9 | 957 | default: |
dc759020 | 958 | gcc_unreachable (); |
18e9d2f9 | 959 | } |
5abc5de9 | 960 | |
18e9d2f9 AO |
961 | /* Now actually save the FP registers. */ |
962 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 963 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
18e9d2f9 AO |
964 | { |
965 | rtx addr; | |
966 | ||
967 | if (reg) | |
968 | addr = reg; | |
969 | else | |
970 | { | |
971 | /* If we aren't using `a0', use an SP offset. */ | |
972 | if (xsize) | |
973 | { | |
974 | addr = gen_rtx_PLUS (SImode, | |
975 | stack_pointer_rtx, | |
976 | GEN_INT (xsize)); | |
977 | } | |
978 | else | |
979 | addr = stack_pointer_rtx; | |
5abc5de9 | 980 | |
18e9d2f9 AO |
981 | xsize += 4; |
982 | } | |
983 | ||
2720cc47 NC |
984 | F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr), |
985 | gen_rtx_REG (SFmode, i)))); | |
18e9d2f9 AO |
986 | } |
987 | } | |
988 | ||
777fbf09 | 989 | /* Now put the frame pointer into the frame pointer register. */ |
11bb1f11 | 990 | if (frame_pointer_needed) |
2720cc47 | 991 | F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx)); |
11bb1f11 | 992 | |
777fbf09 | 993 | /* Allocate stack for this frame. */ |
11bb1f11 | 994 | if (size) |
2720cc47 NC |
995 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
996 | stack_pointer_rtx, | |
997 | GEN_INT (-size)))); | |
998 | ||
6fb5fa3c | 999 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
040c5757 | 1000 | emit_insn (gen_load_pic ()); |
11bb1f11 JL |
1001 | } |
1002 | ||
1003 | void | |
e7ab5593 | 1004 | mn10300_expand_epilogue (void) |
11bb1f11 | 1005 | { |
040c5757 | 1006 | HOST_WIDE_INT size = mn10300_frame_size (); |
e902c266 NC |
1007 | unsigned int reg_save_bytes; |
1008 | ||
1009 | mn10300_get_live_callee_saved_regs (& reg_save_bytes); | |
1010 | ||
18e9d2f9 AO |
1011 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
1012 | { | |
1013 | int num_regs_to_save = fp_regs_to_save (), i; | |
1014 | rtx reg = 0; | |
1015 | ||
1016 | /* We have several options to restore FP registers. We could | |
1017 | load them from SP offsets, but, if there are enough FP | |
1018 | registers to restore, we win if we use a post-increment | |
1019 | addressing mode. */ | |
1020 | ||
1021 | /* If we have a frame pointer, it's the best option, because we | |
1022 | already know it has the value we want. */ | |
1023 | if (frame_pointer_needed) | |
1024 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
1025 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
1026 | it's never used for return values. But only do so if it's | |
1027 | smaller than using SP offsets. */ | |
1028 | else | |
1029 | { | |
1030 | enum { restore_sp_post_adjust, | |
1031 | restore_sp_pre_adjust, | |
1032 | restore_sp_partial_adjust, | |
1033 | restore_a1 } strategy; | |
1034 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
1035 | ||
1036 | /* Consider using sp offsets before adjusting sp. */ | |
1037 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1038 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
1039 | /* If size is too large, we'll have to adjust SP with an | |
1040 | add. */ | |
37a185d7 | 1041 | if (size + 4 * num_regs_to_save + reg_save_bytes > 255) |
18e9d2f9 AO |
1042 | { |
1043 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
1044 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
1045 | } | |
1046 | /* If we don't have to restore any non-FP registers, | |
1047 | we'll be able to save one byte by using rets. */ | |
37a185d7 | 1048 | if (! reg_save_bytes) |
18e9d2f9 AO |
1049 | this_strategy_size--; |
1050 | ||
1051 | if (this_strategy_size < strategy_size) | |
1052 | { | |
1053 | strategy = restore_sp_post_adjust; | |
1054 | strategy_size = this_strategy_size; | |
1055 | } | |
1056 | ||
1057 | /* Consider using sp offsets after adjusting sp. */ | |
1058 | /* Insn: add size, sp. */ | |
1059 | this_strategy_size = SIZE_ADD_SP (size); | |
1060 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1061 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
1062 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1063 | save area, so, no savings. */ |
18e9d2f9 AO |
1064 | |
1065 | if (this_strategy_size < strategy_size) | |
1066 | { | |
1067 | strategy = restore_sp_pre_adjust; | |
1068 | strategy_size = this_strategy_size; | |
1069 | } | |
1070 | ||
1071 | /* Consider using sp offsets after partially adjusting sp. | |
1072 | When size is close to 32Kb, we may be able to adjust SP | |
1073 | with an imm16 add instruction while still using fmov | |
1074 | (d8,sp). */ | |
37a185d7 | 1075 | if (size + 4 * num_regs_to_save + reg_save_bytes > 255) |
18e9d2f9 AO |
1076 | { |
1077 | /* Insn: add size + 4 * num_regs_to_save | |
37a185d7 | 1078 | + reg_save_bytes - 252,sp. */ |
18e9d2f9 | 1079 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save |
c81369fa | 1080 | + (int) reg_save_bytes - 252); |
18e9d2f9 | 1081 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ |
37a185d7 | 1082 | this_strategy_size += SIZE_FMOV_SP (252 - reg_save_bytes |
18e9d2f9 AO |
1083 | - 4 * num_regs_to_save, |
1084 | num_regs_to_save); | |
1085 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1086 | save area, so, no savings. */ |
18e9d2f9 AO |
1087 | |
1088 | if (this_strategy_size < strategy_size) | |
1089 | { | |
1090 | strategy = restore_sp_partial_adjust; | |
1091 | strategy_size = this_strategy_size; | |
1092 | } | |
1093 | } | |
1094 | ||
1095 | /* Consider using a1 in post-increment mode, as long as the | |
1096 | user hasn't changed the calling conventions of a1. */ | |
9d54866d | 1097 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1] |
18e9d2f9 AO |
1098 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) |
1099 | { | |
1100 | /* Insn: mov sp,a1. */ | |
1101 | this_strategy_size = 1; | |
1102 | if (size) | |
1103 | { | |
1104 | /* Insn: add size,a1. */ | |
1105 | this_strategy_size += SIZE_ADD_AX (size); | |
1106 | } | |
1107 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1108 | this_strategy_size += 3 * num_regs_to_save; | |
1109 | /* If size is large enough, we may be able to save a | |
1110 | couple of bytes. */ | |
37a185d7 | 1111 | if (size + 4 * num_regs_to_save + reg_save_bytes > 255) |
18e9d2f9 AO |
1112 | { |
1113 | /* Insn: mov a1,sp. */ | |
1114 | this_strategy_size += 2; | |
1115 | } | |
1116 | /* If we don't have to restore any non-FP registers, | |
1117 | we'll be able to save one byte by using rets. */ | |
37a185d7 | 1118 | if (! reg_save_bytes) |
18e9d2f9 AO |
1119 | this_strategy_size--; |
1120 | ||
1121 | if (this_strategy_size < strategy_size) | |
1122 | { | |
1123 | strategy = restore_a1; | |
1124 | strategy_size = this_strategy_size; | |
1125 | } | |
1126 | } | |
1127 | ||
1128 | switch (strategy) | |
1129 | { | |
1130 | case restore_sp_post_adjust: | |
1131 | break; | |
1132 | ||
1133 | case restore_sp_pre_adjust: | |
1134 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1135 | stack_pointer_rtx, | |
1136 | GEN_INT (size))); | |
1137 | size = 0; | |
1138 | break; | |
1139 | ||
1140 | case restore_sp_partial_adjust: | |
1141 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1142 | stack_pointer_rtx, | |
1143 | GEN_INT (size + 4 * num_regs_to_save | |
37a185d7 RH |
1144 | + reg_save_bytes - 252))); |
1145 | size = 252 - reg_save_bytes - 4 * num_regs_to_save; | |
18e9d2f9 | 1146 | break; |
5abc5de9 | 1147 | |
18e9d2f9 AO |
1148 | case restore_a1: |
1149 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1150 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1151 | if (size) | |
1152 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1153 | break; | |
1154 | ||
1155 | default: | |
dc759020 | 1156 | gcc_unreachable (); |
18e9d2f9 AO |
1157 | } |
1158 | } | |
1159 | ||
1160 | /* Adjust the selected register, if any, for post-increment. */ | |
1161 | if (reg) | |
1162 | reg = gen_rtx_POST_INC (SImode, reg); | |
1163 | ||
1164 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 1165 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
18e9d2f9 AO |
1166 | { |
1167 | rtx addr; | |
5abc5de9 | 1168 | |
18e9d2f9 AO |
1169 | if (reg) |
1170 | addr = reg; | |
1171 | else if (size) | |
1172 | { | |
1173 | /* If we aren't using a post-increment register, use an | |
8596d0a1 | 1174 | SP offset. */ |
18e9d2f9 AO |
1175 | addr = gen_rtx_PLUS (SImode, |
1176 | stack_pointer_rtx, | |
1177 | GEN_INT (size)); | |
1178 | } | |
1179 | else | |
1180 | addr = stack_pointer_rtx; | |
1181 | ||
1182 | size += 4; | |
1183 | ||
2720cc47 NC |
1184 | emit_insn (gen_movsf (gen_rtx_REG (SFmode, i), |
1185 | gen_rtx_MEM (SFmode, addr))); | |
18e9d2f9 AO |
1186 | } |
1187 | ||
1188 | /* If we were using the restore_a1 strategy and the number of | |
1189 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1190 | to `sp', to avoid having to use `add' to adjust it. */ | |
37a185d7 | 1191 | if (! frame_pointer_needed && reg && size + reg_save_bytes > 255) |
18e9d2f9 AO |
1192 | { |
1193 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1194 | size = 0; | |
1195 | } | |
1196 | } | |
1197 | ||
5d29a95f JL |
1198 | /* Maybe cut back the stack, except for the register save area. |
1199 | ||
1200 | If the frame pointer exists, then use the frame pointer to | |
1201 | cut back the stack. | |
1202 | ||
1203 | If the stack size + register save area is more than 255 bytes, | |
1204 | then the stack must be cut back here since the size + register | |
5abc5de9 | 1205 | save size is too big for a ret/retf instruction. |
5d29a95f JL |
1206 | |
1207 | Else leave it alone, it will be cut back as part of the | |
1208 | ret/retf instruction, or there wasn't any stack to begin with. | |
1209 | ||
dab66575 | 1210 | Under no circumstances should the register save area be |
5d29a95f JL |
1211 | deallocated here, that would leave a window where an interrupt |
1212 | could occur and trash the register save area. */ | |
11bb1f11 JL |
1213 | if (frame_pointer_needed) |
1214 | { | |
11bb1f11 | 1215 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
4246e0c5 JL |
1216 | size = 0; |
1217 | } | |
37a185d7 | 1218 | else if (size + reg_save_bytes > 255) |
4246e0c5 JL |
1219 | { |
1220 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1221 | stack_pointer_rtx, | |
1222 | GEN_INT (size))); | |
1223 | size = 0; | |
11bb1f11 | 1224 | } |
11bb1f11 | 1225 | |
ed6089d6 | 1226 | /* Adjust the stack and restore callee-saved registers, if any. */ |
37a185d7 | 1227 | if (mn10300_can_use_rets_insn ()) |
3810076b | 1228 | emit_jump_insn (ret_rtx); |
777fbf09 | 1229 | else |
e902c266 | 1230 | emit_jump_insn (gen_return_ret (GEN_INT (size + reg_save_bytes))); |
11bb1f11 JL |
1231 | } |
1232 | ||
05713b80 | 1233 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
f6cd7c62 RS |
1234 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1235 | parallel. If OP is a multiple store, return a mask indicating which | |
1236 | registers it saves. Return 0 otherwise. */ | |
1237 | ||
1238 | int | |
e7ab5593 NC |
1239 | mn10300_store_multiple_operation (rtx op, |
1240 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
f6cd7c62 RS |
1241 | { |
1242 | int count; | |
1243 | int mask; | |
1244 | int i; | |
1245 | unsigned int last; | |
1246 | rtx elt; | |
1247 | ||
1248 | count = XVECLEN (op, 0); | |
1249 | if (count < 2) | |
1250 | return 0; | |
1251 | ||
1252 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1253 | elt = XVECEXP (op, 0, 0); | |
1254 | if (GET_CODE (elt) != SET | |
e7ab5593 | 1255 | || (! REG_P (SET_DEST (elt))) |
f6cd7c62 RS |
1256 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM |
1257 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1258 | return 0; | |
1259 | ||
1260 | /* Check that A is the stack pointer and B is the expected stack size. | |
1261 | For OP to match, each subsequent instruction should push a word onto | |
1262 | the stack. We therefore expect the first instruction to create | |
8596d0a1 | 1263 | COUNT-1 stack slots. */ |
f6cd7c62 | 1264 | elt = SET_SRC (elt); |
e7ab5593 | 1265 | if ((! REG_P (XEXP (elt, 0))) |
f6cd7c62 | 1266 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM |
e7ab5593 | 1267 | || (! CONST_INT_P (XEXP (elt, 1))) |
f6cd7c62 RS |
1268 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) |
1269 | return 0; | |
1270 | ||
f6cd7c62 RS |
1271 | mask = 0; |
1272 | for (i = 1; i < count; i++) | |
1273 | { | |
cc909bba RH |
1274 | /* Check that element i is a (set (mem M) R). */ |
1275 | /* ??? Validate the register order a-la mn10300_gen_multiple_store. | |
1276 | Remember: the ordering is *not* monotonic. */ | |
f6cd7c62 RS |
1277 | elt = XVECEXP (op, 0, i); |
1278 | if (GET_CODE (elt) != SET | |
e7ab5593 | 1279 | || (! MEM_P (SET_DEST (elt))) |
cc909bba | 1280 | || (! REG_P (SET_SRC (elt)))) |
f6cd7c62 RS |
1281 | return 0; |
1282 | ||
cc909bba | 1283 | /* Remember which registers are to be saved. */ |
f6cd7c62 RS |
1284 | last = REGNO (SET_SRC (elt)); |
1285 | mask |= (1 << last); | |
1286 | ||
1287 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1288 | elt = XEXP (SET_DEST (elt), 0); | |
1289 | if (GET_CODE (elt) != PLUS | |
e7ab5593 | 1290 | || (! REG_P (XEXP (elt, 0))) |
f6cd7c62 | 1291 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM |
e7ab5593 | 1292 | || (! CONST_INT_P (XEXP (elt, 1))) |
f6cd7c62 RS |
1293 | || INTVAL (XEXP (elt, 1)) != -i * 4) |
1294 | return 0; | |
1295 | } | |
1296 | ||
8596d0a1 | 1297 | /* All or none of the callee-saved extended registers must be in the set. */ |
f6cd7c62 RS |
1298 | if ((mask & 0x3c000) != 0 |
1299 | && (mask & 0x3c000) != 0x3c000) | |
1300 | return 0; | |
1301 | ||
1302 | return mask; | |
1303 | } | |
1304 | ||
f2831cc9 AS |
1305 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. */ |
1306 | ||
1307 | static reg_class_t | |
1308 | mn10300_preferred_reload_class (rtx x, reg_class_t rclass) | |
1309 | { | |
1310 | if (x == stack_pointer_rtx && rclass != SP_REGS) | |
8b119bb6 | 1311 | return (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS); |
f2831cc9 AS |
1312 | else if (MEM_P (x) |
1313 | || (REG_P (x) | |
1314 | && !HARD_REGISTER_P (x)) | |
1315 | || (GET_CODE (x) == SUBREG | |
1316 | && REG_P (SUBREG_REG (x)) | |
1317 | && !HARD_REGISTER_P (SUBREG_REG (x)))) | |
1318 | return LIMIT_RELOAD_CLASS (GET_MODE (x), rclass); | |
1319 | else | |
1320 | return rclass; | |
1321 | } | |
1322 | ||
1323 | /* Implement TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */ | |
1324 | ||
1325 | static reg_class_t | |
1326 | mn10300_preferred_output_reload_class (rtx x, reg_class_t rclass) | |
1327 | { | |
1328 | if (x == stack_pointer_rtx && rclass != SP_REGS) | |
8b119bb6 | 1329 | return (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS); |
f2831cc9 AS |
1330 | return rclass; |
1331 | } | |
1332 | ||
8b119bb6 | 1333 | /* Implement TARGET_SECONDARY_RELOAD. */ |
e7ab5593 | 1334 | |
8b119bb6 RH |
1335 | static reg_class_t |
1336 | mn10300_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, | |
1337 | enum machine_mode mode, secondary_reload_info *sri) | |
11bb1f11 | 1338 | { |
8b119bb6 RH |
1339 | enum reg_class rclass = (enum reg_class) rclass_i; |
1340 | enum reg_class xclass = NO_REGS; | |
1341 | unsigned int xregno = INVALID_REGNUM; | |
1342 | ||
1343 | if (REG_P (x)) | |
4d1a91c2 | 1344 | { |
8b119bb6 RH |
1345 | xregno = REGNO (x); |
1346 | if (xregno >= FIRST_PSEUDO_REGISTER) | |
1347 | xregno = true_regnum (x); | |
1348 | if (xregno != INVALID_REGNUM) | |
1349 | xclass = REGNO_REG_CLASS (xregno); | |
1350 | } | |
1351 | ||
1352 | if (!TARGET_AM33) | |
1353 | { | |
1354 | /* Memory load/stores less than a full word wide can't have an | |
1355 | address or stack pointer destination. They must use a data | |
1356 | register as an intermediate register. */ | |
1357 | if (rclass != DATA_REGS | |
1358 | && (mode == QImode || mode == HImode) | |
1359 | && xclass == NO_REGS) | |
1360 | return DATA_REGS; | |
1361 | ||
1362 | /* We can only move SP to/from an address register. */ | |
1363 | if (in_p | |
1364 | && rclass == SP_REGS | |
1365 | && xclass != ADDRESS_REGS) | |
1366 | return ADDRESS_REGS; | |
1367 | if (!in_p | |
1368 | && xclass == SP_REGS | |
1369 | && rclass != ADDRESS_REGS | |
1370 | && rclass != SP_OR_ADDRESS_REGS) | |
1371 | return ADDRESS_REGS; | |
4d1a91c2 | 1372 | } |
11bb1f11 | 1373 | |
8b119bb6 RH |
1374 | /* We can't directly load sp + const_int into a register; |
1375 | we must use an address register as an scratch. */ | |
1376 | if (in_p | |
1377 | && rclass != SP_REGS | |
0a2aaacc | 1378 | && rclass != SP_OR_ADDRESS_REGS |
36846b26 | 1379 | && rclass != SP_OR_GENERAL_REGS |
8b119bb6 RH |
1380 | && GET_CODE (x) == PLUS |
1381 | && (XEXP (x, 0) == stack_pointer_rtx | |
1382 | || XEXP (x, 1) == stack_pointer_rtx)) | |
1383 | { | |
1384 | sri->icode = CODE_FOR_reload_plus_sp_const; | |
1385 | return NO_REGS; | |
1386 | } | |
11bb1f11 | 1387 | |
c25a21f5 RH |
1388 | /* We can only move MDR to/from a data register. */ |
1389 | if (rclass == MDR_REGS && xclass != DATA_REGS) | |
1390 | return DATA_REGS; | |
1391 | if (xclass == MDR_REGS && rclass != DATA_REGS) | |
1392 | return DATA_REGS; | |
1393 | ||
8b119bb6 | 1394 | /* We can't load/store an FP register from a constant address. */ |
6528281d | 1395 | if (TARGET_AM33_2 |
8b119bb6 RH |
1396 | && (rclass == FP_REGS || xclass == FP_REGS) |
1397 | && (xclass == NO_REGS || rclass == NO_REGS)) | |
18e9d2f9 | 1398 | { |
8b119bb6 RH |
1399 | rtx addr = NULL; |
1400 | ||
1401 | if (xregno >= FIRST_PSEUDO_REGISTER && xregno != INVALID_REGNUM) | |
1402 | { | |
f2034d06 | 1403 | addr = reg_equiv_mem (xregno); |
8b119bb6 RH |
1404 | if (addr) |
1405 | addr = XEXP (addr, 0); | |
1406 | } | |
1407 | else if (MEM_P (x)) | |
1408 | addr = XEXP (x, 0); | |
6528281d | 1409 | |
8b119bb6 | 1410 | if (addr && CONSTANT_ADDRESS_P (addr)) |
36846b26 | 1411 | return GENERAL_REGS; |
18e9d2f9 AO |
1412 | } |
1413 | ||
777fbf09 JL |
1414 | /* Otherwise assume no secondary reloads are needed. */ |
1415 | return NO_REGS; | |
1416 | } | |
1417 | ||
040c5757 RH |
1418 | int |
1419 | mn10300_frame_size (void) | |
1420 | { | |
1421 | /* size includes the fixed stack space needed for function calls. */ | |
1422 | int size = get_frame_size () + crtl->outgoing_args_size; | |
1423 | ||
1424 | /* And space for the return pointer. */ | |
1425 | size += crtl->outgoing_args_size ? 4 : 0; | |
1426 | ||
1427 | return size; | |
1428 | } | |
1429 | ||
777fbf09 | 1430 | int |
e7ab5593 | 1431 | mn10300_initial_offset (int from, int to) |
777fbf09 | 1432 | { |
040c5757 RH |
1433 | int diff = 0; |
1434 | ||
1435 | gcc_assert (from == ARG_POINTER_REGNUM || from == FRAME_POINTER_REGNUM); | |
1436 | gcc_assert (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); | |
1437 | ||
1438 | if (to == STACK_POINTER_REGNUM) | |
1439 | diff = mn10300_frame_size (); | |
1440 | ||
3dbc43d1 JL |
1441 | /* The difference between the argument pointer and the frame pointer |
1442 | is the size of the callee register save area. */ | |
040c5757 | 1443 | if (from == ARG_POINTER_REGNUM) |
11bb1f11 | 1444 | { |
e902c266 NC |
1445 | unsigned int reg_save_bytes; |
1446 | ||
1447 | mn10300_get_live_callee_saved_regs (& reg_save_bytes); | |
1448 | diff += reg_save_bytes; | |
040c5757 | 1449 | diff += 4 * fp_regs_to_save (); |
11bb1f11 JL |
1450 | } |
1451 | ||
040c5757 | 1452 | return diff; |
11bb1f11 | 1453 | } |
22ef4e9b | 1454 | |
bd5bd7ac KH |
1455 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
1456 | ||
9024ea92 | 1457 | static bool |
586de218 | 1458 | mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
9024ea92 KH |
1459 | { |
1460 | /* Return values > 8 bytes in length in memory. */ | |
b1eb8119 DD |
1461 | return (int_size_in_bytes (type) > 8 |
1462 | || int_size_in_bytes (type) == 0 | |
1463 | || TYPE_MODE (type) == BLKmode); | |
9024ea92 KH |
1464 | } |
1465 | ||
22ef4e9b JL |
1466 | /* Flush the argument registers to the stack for a stdarg function; |
1467 | return the new argument pointer. */ | |
9024ea92 | 1468 | static rtx |
f1777882 | 1469 | mn10300_builtin_saveregs (void) |
22ef4e9b | 1470 | { |
fc2acc87 | 1471 | rtx offset, mem; |
22ef4e9b | 1472 | tree fntype = TREE_TYPE (current_function_decl); |
f38958e8 | 1473 | int argadj = ((!stdarg_p (fntype)) |
22ef4e9b | 1474 | ? UNITS_PER_WORD : 0); |
4862826d | 1475 | alias_set_type set = get_varargs_alias_set (); |
22ef4e9b JL |
1476 | |
1477 | if (argadj) | |
0a81f074 | 1478 | offset = plus_constant (Pmode, crtl->args.arg_offset_rtx, argadj); |
22ef4e9b | 1479 | else |
38173d38 | 1480 | offset = crtl->args.arg_offset_rtx; |
22ef4e9b | 1481 | |
38173d38 | 1482 | mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer); |
ba4828e0 | 1483 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1484 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1485 | ||
1486 | mem = gen_rtx_MEM (SImode, | |
0a81f074 RS |
1487 | plus_constant (Pmode, |
1488 | crtl->args.internal_arg_pointer, 4)); | |
ba4828e0 | 1489 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1490 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1491 | ||
22ef4e9b | 1492 | return copy_to_reg (expand_binop (Pmode, add_optab, |
38173d38 | 1493 | crtl->args.internal_arg_pointer, |
22ef4e9b JL |
1494 | offset, 0, 0, OPTAB_LIB_WIDEN)); |
1495 | } | |
1496 | ||
d7bd8aeb | 1497 | static void |
f1777882 | 1498 | mn10300_va_start (tree valist, rtx nextarg) |
fc2acc87 | 1499 | { |
6c535c69 | 1500 | nextarg = expand_builtin_saveregs (); |
e5faf155 | 1501 | std_expand_builtin_va_start (valist, nextarg); |
fc2acc87 RH |
1502 | } |
1503 | ||
8cd5a4e0 RH |
1504 | /* Return true when a parameter should be passed by reference. */ |
1505 | ||
1506 | static bool | |
d5cc9181 | 1507 | mn10300_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, |
586de218 | 1508 | enum machine_mode mode, const_tree type, |
8cd5a4e0 RH |
1509 | bool named ATTRIBUTE_UNUSED) |
1510 | { | |
1511 | unsigned HOST_WIDE_INT size; | |
1512 | ||
1513 | if (type) | |
1514 | size = int_size_in_bytes (type); | |
1515 | else | |
1516 | size = GET_MODE_SIZE (mode); | |
1517 | ||
b1eb8119 | 1518 | return (size > 8 || size == 0); |
8cd5a4e0 RH |
1519 | } |
1520 | ||
22ef4e9b | 1521 | /* Return an RTX to represent where a value with mode MODE will be returned |
990dc016 | 1522 | from a function. If the result is NULL_RTX, the argument is pushed. */ |
22ef4e9b | 1523 | |
ce236858 | 1524 | static rtx |
d5cc9181 | 1525 | mn10300_function_arg (cumulative_args_t cum_v, enum machine_mode mode, |
ce236858 | 1526 | const_tree type, bool named ATTRIBUTE_UNUSED) |
22ef4e9b | 1527 | { |
d5cc9181 | 1528 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
990dc016 | 1529 | rtx result = NULL_RTX; |
f4a88680 | 1530 | int size; |
22ef4e9b JL |
1531 | |
1532 | /* We only support using 2 data registers as argument registers. */ | |
1533 | int nregs = 2; | |
1534 | ||
1535 | /* Figure out the size of the object to be passed. */ | |
1536 | if (mode == BLKmode) | |
1537 | size = int_size_in_bytes (type); | |
1538 | else | |
1539 | size = GET_MODE_SIZE (mode); | |
1540 | ||
22ef4e9b JL |
1541 | cum->nbytes = (cum->nbytes + 3) & ~3; |
1542 | ||
1543 | /* Don't pass this arg via a register if all the argument registers | |
1544 | are used up. */ | |
1545 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
990dc016 | 1546 | return result; |
22ef4e9b JL |
1547 | |
1548 | /* Don't pass this arg via a register if it would be split between | |
1549 | registers and memory. */ | |
1550 | if (type == NULL_TREE | |
1551 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
990dc016 | 1552 | return result; |
22ef4e9b JL |
1553 | |
1554 | switch (cum->nbytes / UNITS_PER_WORD) | |
1555 | { | |
1556 | case 0: | |
990dc016 | 1557 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM); |
22ef4e9b JL |
1558 | break; |
1559 | case 1: | |
990dc016 | 1560 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1); |
22ef4e9b JL |
1561 | break; |
1562 | default: | |
990dc016 | 1563 | break; |
22ef4e9b JL |
1564 | } |
1565 | ||
1566 | return result; | |
1567 | } | |
1568 | ||
ce236858 NF |
1569 | /* Update the data in CUM to advance over an argument |
1570 | of mode MODE and data type TYPE. | |
1571 | (TYPE is null for libcalls where that information may not be available.) */ | |
1572 | ||
1573 | static void | |
d5cc9181 | 1574 | mn10300_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, |
ce236858 NF |
1575 | const_tree type, bool named ATTRIBUTE_UNUSED) |
1576 | { | |
d5cc9181 JR |
1577 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
1578 | ||
ce236858 NF |
1579 | cum->nbytes += (mode != BLKmode |
1580 | ? (GET_MODE_SIZE (mode) + 3) & ~3 | |
1581 | : (int_size_in_bytes (type) + 3) & ~3); | |
1582 | } | |
1583 | ||
78a52f11 RH |
1584 | /* Return the number of bytes of registers to use for an argument passed |
1585 | partially in registers and partially in memory. */ | |
22ef4e9b | 1586 | |
78a52f11 | 1587 | static int |
d5cc9181 | 1588 | mn10300_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode, |
78a52f11 | 1589 | tree type, bool named ATTRIBUTE_UNUSED) |
22ef4e9b | 1590 | { |
d5cc9181 | 1591 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
f4a88680 | 1592 | int size; |
22ef4e9b JL |
1593 | |
1594 | /* We only support using 2 data registers as argument registers. */ | |
1595 | int nregs = 2; | |
1596 | ||
1597 | /* Figure out the size of the object to be passed. */ | |
1598 | if (mode == BLKmode) | |
1599 | size = int_size_in_bytes (type); | |
1600 | else | |
1601 | size = GET_MODE_SIZE (mode); | |
1602 | ||
22ef4e9b JL |
1603 | cum->nbytes = (cum->nbytes + 3) & ~3; |
1604 | ||
1605 | /* Don't pass this arg via a register if all the argument registers | |
1606 | are used up. */ | |
1607 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1608 | return 0; | |
1609 | ||
1610 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1611 | return 0; | |
1612 | ||
1613 | /* Don't pass this arg via a register if it would be split between | |
1614 | registers and memory. */ | |
1615 | if (type == NULL_TREE | |
1616 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1617 | return 0; | |
1618 | ||
78a52f11 | 1619 | return nregs * UNITS_PER_WORD - cum->nbytes; |
22ef4e9b JL |
1620 | } |
1621 | ||
b1eb8119 DD |
1622 | /* Return the location of the function's value. This will be either |
1623 | $d0 for integer functions, $a0 for pointers, or a PARALLEL of both | |
1624 | $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that | |
1625 | we only return the PARALLEL for outgoing values; we do not want | |
1626 | callers relying on this extra copy. */ | |
1627 | ||
34732b0a AS |
1628 | static rtx |
1629 | mn10300_function_value (const_tree valtype, | |
1630 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
1631 | bool outgoing) | |
b1eb8119 DD |
1632 | { |
1633 | rtx rv; | |
1634 | enum machine_mode mode = TYPE_MODE (valtype); | |
1635 | ||
1636 | if (! POINTER_TYPE_P (valtype)) | |
1637 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1638 | else if (! TARGET_PTR_A0D0 || ! outgoing | |
e3b5732b | 1639 | || cfun->returns_struct) |
b1eb8119 DD |
1640 | return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM); |
1641 | ||
1642 | rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2)); | |
1643 | XVECEXP (rv, 0, 0) | |
1644 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1645 | gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM), | |
1646 | GEN_INT (0)); | |
5abc5de9 | 1647 | |
b1eb8119 DD |
1648 | XVECEXP (rv, 0, 1) |
1649 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1650 | gen_rtx_REG (mode, FIRST_DATA_REGNUM), | |
1651 | GEN_INT (0)); | |
1652 | return rv; | |
1653 | } | |
1654 | ||
34732b0a AS |
1655 | /* Implements TARGET_LIBCALL_VALUE. */ |
1656 | ||
1657 | static rtx | |
1658 | mn10300_libcall_value (enum machine_mode mode, | |
1659 | const_rtx fun ATTRIBUTE_UNUSED) | |
1660 | { | |
1661 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1662 | } | |
1663 | ||
1664 | /* Implements FUNCTION_VALUE_REGNO_P. */ | |
1665 | ||
1666 | bool | |
1667 | mn10300_function_value_regno_p (const unsigned int regno) | |
1668 | { | |
1669 | return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM); | |
1670 | } | |
1671 | ||
bad41521 | 1672 | /* Output an addition operation. */ |
4af476d7 | 1673 | |
1943c2c1 | 1674 | const char * |
bad41521 | 1675 | mn10300_output_add (rtx operands[3], bool need_flags) |
22ef4e9b | 1676 | { |
bad41521 RH |
1677 | rtx dest, src1, src2; |
1678 | unsigned int dest_regnum, src1_regnum, src2_regnum; | |
1679 | enum reg_class src1_class, src2_class, dest_class; | |
22ef4e9b | 1680 | |
bad41521 RH |
1681 | dest = operands[0]; |
1682 | src1 = operands[1]; | |
1683 | src2 = operands[2]; | |
22ef4e9b | 1684 | |
bad41521 RH |
1685 | dest_regnum = true_regnum (dest); |
1686 | src1_regnum = true_regnum (src1); | |
22ef4e9b | 1687 | |
bad41521 RH |
1688 | dest_class = REGNO_REG_CLASS (dest_regnum); |
1689 | src1_class = REGNO_REG_CLASS (src1_regnum); | |
22ef4e9b | 1690 | |
298362c8 | 1691 | if (CONST_INT_P (src2)) |
bad41521 RH |
1692 | { |
1693 | gcc_assert (dest_regnum == src1_regnum); | |
22ef4e9b | 1694 | |
bad41521 RH |
1695 | if (src2 == const1_rtx && !need_flags) |
1696 | return "inc %0"; | |
1697 | if (INTVAL (src2) == 4 && !need_flags && dest_class != DATA_REGS) | |
1698 | return "inc4 %0"; | |
705ac34f | 1699 | |
bad41521 RH |
1700 | gcc_assert (!need_flags || dest_class != SP_REGS); |
1701 | return "add %2,%0"; | |
1702 | } | |
1703 | else if (CONSTANT_P (src2)) | |
1704 | return "add %2,%0"; | |
1705 | ||
1706 | src2_regnum = true_regnum (src2); | |
1707 | src2_class = REGNO_REG_CLASS (src2_regnum); | |
1708 | ||
1709 | if (dest_regnum == src1_regnum) | |
1710 | return "add %2,%0"; | |
1711 | if (dest_regnum == src2_regnum) | |
1712 | return "add %1,%0"; | |
1713 | ||
1714 | /* The rest of the cases are reg = reg+reg. For AM33, we can implement | |
1715 | this directly, as below, but when optimizing for space we can sometimes | |
1716 | do better by using a mov+add. For MN103, we claimed that we could | |
1717 | implement a three-operand add because the various move and add insns | |
1718 | change sizes across register classes, and we can often do better than | |
1719 | reload in choosing which operand to move. */ | |
1720 | if (TARGET_AM33 && optimize_insn_for_speed_p ()) | |
1721 | return "add %2,%1,%0"; | |
1722 | ||
1723 | /* Catch cases where no extended register was used. */ | |
1724 | if (src1_class != EXTENDED_REGS | |
1725 | && src2_class != EXTENDED_REGS | |
1726 | && dest_class != EXTENDED_REGS) | |
1727 | { | |
1728 | /* We have to copy one of the sources into the destination, then | |
1729 | add the other source to the destination. | |
1730 | ||
1731 | Carefully select which source to copy to the destination; a | |
1732 | naive implementation will waste a byte when the source classes | |
1733 | are different and the destination is an address register. | |
1734 | Selecting the lowest cost register copy will optimize this | |
1735 | sequence. */ | |
1736 | if (src1_class == dest_class) | |
1737 | return "mov %1,%0\n\tadd %2,%0"; | |
1738 | else | |
1739 | return "mov %2,%0\n\tadd %1,%0"; | |
1740 | } | |
705ac34f | 1741 | |
bad41521 | 1742 | /* At least one register is an extended register. */ |
22ef4e9b | 1743 | |
bad41521 RH |
1744 | /* The three operand add instruction on the am33 is a win iff the |
1745 | output register is an extended register, or if both source | |
1746 | registers are extended registers. */ | |
1747 | if (dest_class == EXTENDED_REGS || src1_class == src2_class) | |
1748 | return "add %2,%1,%0"; | |
1749 | ||
1750 | /* It is better to copy one of the sources to the destination, then | |
1751 | perform a 2 address add. The destination in this case must be | |
1752 | an address or data register and one of the sources must be an | |
1753 | extended register and the remaining source must not be an extended | |
1754 | register. | |
1755 | ||
1756 | The best code for this case is to copy the extended reg to the | |
1757 | destination, then emit a two address add. */ | |
1758 | if (src1_class == EXTENDED_REGS) | |
1759 | return "mov %1,%0\n\tadd %2,%0"; | |
1760 | else | |
1761 | return "mov %2,%0\n\tadd %1,%0"; | |
22ef4e9b | 1762 | } |
460f4b9d | 1763 | |
e9ad4573 JL |
1764 | /* Return 1 if X contains a symbolic expression. We know these |
1765 | expressions will have one of a few well defined forms, so | |
1766 | we need only check those forms. */ | |
e7ab5593 | 1767 | |
e9ad4573 | 1768 | int |
e7ab5593 NC |
1769 | mn10300_symbolic_operand (rtx op, |
1770 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
e9ad4573 JL |
1771 | { |
1772 | switch (GET_CODE (op)) | |
1773 | { | |
1774 | case SYMBOL_REF: | |
1775 | case LABEL_REF: | |
1776 | return 1; | |
1777 | case CONST: | |
1778 | op = XEXP (op, 0); | |
1779 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1780 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
f3f63737 | 1781 | && CONST_INT_P (XEXP (op, 1))); |
e9ad4573 JL |
1782 | default: |
1783 | return 0; | |
1784 | } | |
1785 | } | |
1786 | ||
1787 | /* Try machine dependent ways of modifying an illegitimate address | |
1788 | to be legitimate. If we find one, return the new valid address. | |
1789 | This macro is used in only one place: `memory_address' in explow.c. | |
1790 | ||
1791 | OLDX is the address as it was before break_out_memory_refs was called. | |
1792 | In some cases it is useful to look at this to decide what needs to be done. | |
1793 | ||
e9ad4573 JL |
1794 | Normally it is always safe for this macro to do nothing. It exists to |
1795 | recognize opportunities to optimize the output. | |
1796 | ||
1797 | But on a few ports with segmented architectures and indexed addressing | |
1798 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
e7ab5593 | 1799 | |
4af476d7 | 1800 | static rtx |
506d7b68 PB |
1801 | mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1802 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
e9ad4573 | 1803 | { |
e7ab5593 NC |
1804 | if (flag_pic && ! mn10300_legitimate_pic_operand_p (x)) |
1805 | x = mn10300_legitimize_pic_address (oldx, NULL_RTX); | |
d1776069 | 1806 | |
e9ad4573 JL |
1807 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1808 | special handling to avoid creating an indexed memory address | |
1809 | with x-100000 as the base. */ | |
1810 | if (GET_CODE (x) == PLUS | |
e7ab5593 | 1811 | && mn10300_symbolic_operand (XEXP (x, 1), VOIDmode)) |
e9ad4573 JL |
1812 | { |
1813 | /* Ugly. We modify things here so that the address offset specified | |
1814 | by the index expression is computed first, then added to x to form | |
1815 | the entire address. */ | |
1816 | ||
69bc71fa | 1817 | rtx regx1, regy1, regy2, y; |
e9ad4573 JL |
1818 | |
1819 | /* Strip off any CONST. */ | |
1820 | y = XEXP (x, 1); | |
1821 | if (GET_CODE (y) == CONST) | |
1822 | y = XEXP (y, 0); | |
1823 | ||
bf4219f0 JL |
1824 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1825 | { | |
1826 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1827 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1828 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1829 | regx1 = force_reg (Pmode, | |
e7ab5593 NC |
1830 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, |
1831 | regy2)); | |
c5c76735 | 1832 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
bf4219f0 | 1833 | } |
e9ad4573 | 1834 | } |
371036e0 | 1835 | return x; |
e9ad4573 | 1836 | } |
460ad325 | 1837 | |
d1776069 | 1838 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
8596d0a1 | 1839 | @GOTOFF in `reg'. */ |
e7ab5593 | 1840 | |
d1776069 | 1841 | rtx |
e7ab5593 | 1842 | mn10300_legitimize_pic_address (rtx orig, rtx reg) |
d1776069 | 1843 | { |
53855940 RH |
1844 | rtx x; |
1845 | ||
d1776069 AO |
1846 | if (GET_CODE (orig) == LABEL_REF |
1847 | || (GET_CODE (orig) == SYMBOL_REF | |
1848 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1849 | || ! MN10300_GLOBAL_P (orig)))) | |
1850 | { | |
53855940 | 1851 | if (reg == NULL) |
d1776069 AO |
1852 | reg = gen_reg_rtx (Pmode); |
1853 | ||
53855940 RH |
1854 | x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOTOFF); |
1855 | x = gen_rtx_CONST (SImode, x); | |
1856 | emit_move_insn (reg, x); | |
1857 | ||
1858 | x = emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx)); | |
d1776069 AO |
1859 | } |
1860 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1861 | { | |
53855940 | 1862 | if (reg == NULL) |
d1776069 AO |
1863 | reg = gen_reg_rtx (Pmode); |
1864 | ||
53855940 RH |
1865 | x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOT); |
1866 | x = gen_rtx_CONST (SImode, x); | |
1867 | x = gen_rtx_PLUS (SImode, pic_offset_table_rtx, x); | |
1868 | x = gen_const_mem (SImode, x); | |
1869 | ||
1870 | x = emit_move_insn (reg, x); | |
d1776069 | 1871 | } |
53855940 RH |
1872 | else |
1873 | return orig; | |
1874 | ||
1875 | set_unique_reg_note (x, REG_EQUAL, orig); | |
1876 | return reg; | |
d1776069 AO |
1877 | } |
1878 | ||
1879 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
4375e090 | 1880 | isn't protected by a PIC unspec; nonzero otherwise. */ |
e7ab5593 | 1881 | |
d1776069 | 1882 | int |
e7ab5593 | 1883 | mn10300_legitimate_pic_operand_p (rtx x) |
d1776069 | 1884 | { |
e7ab5593 NC |
1885 | const char *fmt; |
1886 | int i; | |
d1776069 AO |
1887 | |
1888 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1889 | return 0; | |
1890 | ||
1891 | if (GET_CODE (x) == UNSPEC | |
1892 | && (XINT (x, 1) == UNSPEC_PIC | |
1893 | || XINT (x, 1) == UNSPEC_GOT | |
1894 | || XINT (x, 1) == UNSPEC_GOTOFF | |
d4e2d7d2 RS |
1895 | || XINT (x, 1) == UNSPEC_PLT |
1896 | || XINT (x, 1) == UNSPEC_GOTSYM_OFF)) | |
d1776069 AO |
1897 | return 1; |
1898 | ||
d1776069 AO |
1899 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
1900 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1901 | { | |
1902 | if (fmt[i] == 'E') | |
1903 | { | |
4af476d7 | 1904 | int j; |
d1776069 AO |
1905 | |
1906 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
e7ab5593 | 1907 | if (! mn10300_legitimate_pic_operand_p (XVECEXP (x, i, j))) |
d1776069 AO |
1908 | return 0; |
1909 | } | |
e7ab5593 NC |
1910 | else if (fmt[i] == 'e' |
1911 | && ! mn10300_legitimate_pic_operand_p (XEXP (x, i))) | |
d1776069 AO |
1912 | return 0; |
1913 | } | |
1914 | ||
1915 | return 1; | |
1916 | } | |
1917 | ||
e733134f | 1918 | /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is |
c6c3dba9 PB |
1919 | legitimate, and FALSE otherwise. |
1920 | ||
1921 | On the mn10300, the value in the address register must be | |
1922 | in the same memory space/segment as the effective address. | |
1923 | ||
1924 | This is problematical for reload since it does not understand | |
1925 | that base+index != index+base in a memory reference. | |
1926 | ||
1927 | Note it is still possible to use reg+reg addressing modes, | |
1928 | it's just much more difficult. For a discussion of a possible | |
1929 | workaround and solution, see the comments in pa.c before the | |
1930 | function record_unscaled_index_insn_codes. */ | |
1931 | ||
4af476d7 | 1932 | static bool |
c6c3dba9 | 1933 | mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) |
e733134f | 1934 | { |
36846b26 RH |
1935 | rtx base, index; |
1936 | ||
1937 | if (CONSTANT_ADDRESS_P (x)) | |
1938 | return !flag_pic || mn10300_legitimate_pic_operand_p (x); | |
e733134f AO |
1939 | |
1940 | if (RTX_OK_FOR_BASE_P (x, strict)) | |
36846b26 RH |
1941 | return true; |
1942 | ||
1943 | if (TARGET_AM33 && (mode == SImode || mode == SFmode || mode == HImode)) | |
1944 | { | |
1945 | if (GET_CODE (x) == POST_INC) | |
1946 | return RTX_OK_FOR_BASE_P (XEXP (x, 0), strict); | |
1947 | if (GET_CODE (x) == POST_MODIFY) | |
1948 | return (RTX_OK_FOR_BASE_P (XEXP (x, 0), strict) | |
1949 | && CONSTANT_ADDRESS_P (XEXP (x, 1))); | |
1950 | } | |
1951 | ||
1952 | if (GET_CODE (x) != PLUS) | |
1953 | return false; | |
e733134f | 1954 | |
36846b26 RH |
1955 | base = XEXP (x, 0); |
1956 | index = XEXP (x, 1); | |
e733134f | 1957 | |
36846b26 RH |
1958 | if (!REG_P (base)) |
1959 | return false; | |
1960 | if (REG_P (index)) | |
e733134f | 1961 | { |
36846b26 RH |
1962 | /* ??? Without AM33 generalized (Ri,Rn) addressing, reg+reg |
1963 | addressing is hard to satisfy. */ | |
1964 | if (!TARGET_AM33) | |
1965 | return false; | |
e733134f | 1966 | |
36846b26 RH |
1967 | return (REGNO_GENERAL_P (REGNO (base), strict) |
1968 | && REGNO_GENERAL_P (REGNO (index), strict)); | |
1969 | } | |
e733134f | 1970 | |
36846b26 RH |
1971 | if (!REGNO_STRICT_OK_FOR_BASE_P (REGNO (base), strict)) |
1972 | return false; | |
e733134f | 1973 | |
36846b26 RH |
1974 | if (CONST_INT_P (index)) |
1975 | return IN_RANGE (INTVAL (index), -1 - 0x7fffffff, 0x7fffffff); | |
1976 | ||
1977 | if (CONSTANT_ADDRESS_P (index)) | |
1978 | return !flag_pic || mn10300_legitimate_pic_operand_p (index); | |
1979 | ||
1980 | return false; | |
1981 | } | |
1982 | ||
1983 | bool | |
1984 | mn10300_regno_in_class_p (unsigned regno, int rclass, bool strict) | |
1985 | { | |
1986 | if (regno >= FIRST_PSEUDO_REGISTER) | |
1987 | { | |
1988 | if (!strict) | |
1989 | return true; | |
1990 | if (!reg_renumber) | |
1991 | return false; | |
1992 | regno = reg_renumber[regno]; | |
ba4ec0e0 NC |
1993 | if (regno == INVALID_REGNUM) |
1994 | return false; | |
36846b26 RH |
1995 | } |
1996 | return TEST_HARD_REG_BIT (reg_class_contents[rclass], regno); | |
1997 | } | |
1998 | ||
1999 | rtx | |
2000 | mn10300_legitimize_reload_address (rtx x, | |
2001 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
2002 | int opnum, int type, | |
2003 | int ind_levels ATTRIBUTE_UNUSED) | |
2004 | { | |
2005 | bool any_change = false; | |
2006 | ||
2007 | /* See above re disabling reg+reg addressing for MN103. */ | |
2008 | if (!TARGET_AM33) | |
2009 | return NULL_RTX; | |
2010 | ||
2011 | if (GET_CODE (x) != PLUS) | |
2012 | return NULL_RTX; | |
2013 | ||
2014 | if (XEXP (x, 0) == stack_pointer_rtx) | |
2015 | { | |
2016 | push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, | |
2017 | GENERAL_REGS, GET_MODE (x), VOIDmode, 0, 0, | |
2018 | opnum, (enum reload_type) type); | |
2019 | any_change = true; | |
2020 | } | |
2021 | if (XEXP (x, 1) == stack_pointer_rtx) | |
2022 | { | |
2023 | push_reload (XEXP (x, 1), NULL_RTX, &XEXP (x, 1), NULL, | |
2024 | GENERAL_REGS, GET_MODE (x), VOIDmode, 0, 0, | |
2025 | opnum, (enum reload_type) type); | |
2026 | any_change = true; | |
e733134f AO |
2027 | } |
2028 | ||
36846b26 | 2029 | return any_change ? x : NULL_RTX; |
e733134f AO |
2030 | } |
2031 | ||
1a627b35 | 2032 | /* Implement TARGET_LEGITIMATE_CONSTANT_P. Returns TRUE if X is a valid |
4af476d7 NC |
2033 | constant. Note that some "constants" aren't valid, such as TLS |
2034 | symbols and unconverted GOT-based references, so we eliminate | |
2035 | those here. */ | |
2036 | ||
1a627b35 RS |
2037 | static bool |
2038 | mn10300_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
4af476d7 NC |
2039 | { |
2040 | switch (GET_CODE (x)) | |
2041 | { | |
2042 | case CONST: | |
2043 | x = XEXP (x, 0); | |
2044 | ||
2045 | if (GET_CODE (x) == PLUS) | |
2046 | { | |
e7ab5593 | 2047 | if (! CONST_INT_P (XEXP (x, 1))) |
4af476d7 NC |
2048 | return false; |
2049 | x = XEXP (x, 0); | |
2050 | } | |
2051 | ||
2052 | /* Only some unspecs are valid as "constants". */ | |
2053 | if (GET_CODE (x) == UNSPEC) | |
2054 | { | |
4af476d7 NC |
2055 | switch (XINT (x, 1)) |
2056 | { | |
4af476d7 NC |
2057 | case UNSPEC_PIC: |
2058 | case UNSPEC_GOT: | |
2059 | case UNSPEC_GOTOFF: | |
2060 | case UNSPEC_PLT: | |
2061 | return true; | |
2062 | default: | |
2063 | return false; | |
2064 | } | |
2065 | } | |
2066 | ||
2067 | /* We must have drilled down to a symbol. */ | |
e7ab5593 | 2068 | if (! mn10300_symbolic_operand (x, Pmode)) |
4af476d7 NC |
2069 | return false; |
2070 | break; | |
2071 | ||
2072 | default: | |
2073 | break; | |
2074 | } | |
2075 | ||
2076 | return true; | |
2077 | } | |
2078 | ||
126b1483 RH |
2079 | /* Undo pic address legitimization for the benefit of debug info. */ |
2080 | ||
2081 | static rtx | |
2082 | mn10300_delegitimize_address (rtx orig_x) | |
2083 | { | |
2084 | rtx x = orig_x, ret, addend = NULL; | |
2085 | bool need_mem; | |
2086 | ||
2087 | if (MEM_P (x)) | |
2088 | x = XEXP (x, 0); | |
2089 | if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode) | |
2090 | return orig_x; | |
2091 | ||
2092 | if (XEXP (x, 0) == pic_offset_table_rtx) | |
2093 | ; | |
2094 | /* With the REG+REG addressing of AM33, var-tracking can re-assemble | |
2095 | some odd-looking "addresses" that were never valid in the first place. | |
2096 | We need to look harder to avoid warnings being emitted. */ | |
2097 | else if (GET_CODE (XEXP (x, 0)) == PLUS) | |
2098 | { | |
2099 | rtx x0 = XEXP (x, 0); | |
2100 | rtx x00 = XEXP (x0, 0); | |
2101 | rtx x01 = XEXP (x0, 1); | |
2102 | ||
2103 | if (x00 == pic_offset_table_rtx) | |
2104 | addend = x01; | |
2105 | else if (x01 == pic_offset_table_rtx) | |
2106 | addend = x00; | |
2107 | else | |
2108 | return orig_x; | |
2109 | ||
2110 | } | |
2111 | else | |
2112 | return orig_x; | |
2113 | x = XEXP (x, 1); | |
2114 | ||
2115 | if (GET_CODE (x) != CONST) | |
2116 | return orig_x; | |
2117 | x = XEXP (x, 0); | |
2118 | if (GET_CODE (x) != UNSPEC) | |
2119 | return orig_x; | |
2120 | ||
2121 | ret = XVECEXP (x, 0, 0); | |
2122 | if (XINT (x, 1) == UNSPEC_GOTOFF) | |
2123 | need_mem = false; | |
2124 | else if (XINT (x, 1) == UNSPEC_GOT) | |
2125 | need_mem = true; | |
2126 | else | |
2127 | return orig_x; | |
2128 | ||
2129 | gcc_assert (GET_CODE (ret) == SYMBOL_REF); | |
2130 | if (need_mem != MEM_P (orig_x)) | |
2131 | return orig_x; | |
2132 | if (need_mem && addend) | |
2133 | return orig_x; | |
2134 | if (addend) | |
2135 | ret = gen_rtx_PLUS (Pmode, addend, ret); | |
2136 | return ret; | |
2137 | } | |
2138 | ||
72d6e3c5 RH |
2139 | /* For addresses, costs are relative to "MOV (Rm),Rn". For AM33 this is |
2140 | the 3-byte fully general instruction; for MN103 this is the 2-byte form | |
2141 | with an address register. */ | |
2142 | ||
dcefdf67 | 2143 | static int |
b413068c OE |
2144 | mn10300_address_cost (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED, |
2145 | addr_space_t as ATTRIBUTE_UNUSED, bool speed) | |
460ad325 | 2146 | { |
72d6e3c5 RH |
2147 | HOST_WIDE_INT i; |
2148 | rtx base, index; | |
2149 | ||
460ad325 AO |
2150 | switch (GET_CODE (x)) |
2151 | { | |
72d6e3c5 RH |
2152 | case CONST: |
2153 | case SYMBOL_REF: | |
2154 | case LABEL_REF: | |
2155 | /* We assume all of these require a 32-bit constant, even though | |
2156 | some symbol and label references can be relaxed. */ | |
2157 | return speed ? 1 : 4; | |
2158 | ||
460ad325 | 2159 | case REG: |
72d6e3c5 RH |
2160 | case SUBREG: |
2161 | case POST_INC: | |
2162 | return 0; | |
2163 | ||
2164 | case POST_MODIFY: | |
2165 | /* Assume any symbolic offset is a 32-bit constant. */ | |
2166 | i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678); | |
2167 | if (IN_RANGE (i, -128, 127)) | |
2168 | return speed ? 0 : 1; | |
2169 | if (speed) | |
2170 | return 1; | |
2171 | if (IN_RANGE (i, -0x800000, 0x7fffff)) | |
2172 | return 3; | |
2173 | return 4; | |
2174 | ||
2175 | case PLUS: | |
2176 | base = XEXP (x, 0); | |
2177 | index = XEXP (x, 1); | |
2178 | if (register_operand (index, SImode)) | |
460ad325 | 2179 | { |
72d6e3c5 RH |
2180 | /* Attempt to minimize the number of registers in the address. |
2181 | This is similar to what other ports do. */ | |
2182 | if (register_operand (base, SImode)) | |
2183 | return 1; | |
460ad325 | 2184 | |
72d6e3c5 RH |
2185 | base = XEXP (x, 1); |
2186 | index = XEXP (x, 0); | |
2187 | } | |
460ad325 | 2188 | |
72d6e3c5 RH |
2189 | /* Assume any symbolic offset is a 32-bit constant. */ |
2190 | i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678); | |
2191 | if (IN_RANGE (i, -128, 127)) | |
2192 | return speed ? 0 : 1; | |
2193 | if (IN_RANGE (i, -32768, 32767)) | |
2194 | return speed ? 0 : 2; | |
2195 | return speed ? 2 : 6; | |
460ad325 | 2196 | |
72d6e3c5 | 2197 | default: |
68f932c4 | 2198 | return rtx_cost (x, MEM, 0, speed); |
72d6e3c5 RH |
2199 | } |
2200 | } | |
460ad325 | 2201 | |
72d6e3c5 | 2202 | /* Implement the TARGET_REGISTER_MOVE_COST hook. |
460ad325 | 2203 | |
72d6e3c5 RH |
2204 | Recall that the base value of 2 is required by assumptions elsewhere |
2205 | in the body of the compiler, and that cost 2 is special-cased as an | |
2206 | early exit from reload meaning no work is required. */ | |
460ad325 | 2207 | |
72d6e3c5 RH |
2208 | static int |
2209 | mn10300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
2210 | reg_class_t ifrom, reg_class_t ito) | |
2211 | { | |
2212 | enum reg_class from = (enum reg_class) ifrom; | |
2213 | enum reg_class to = (enum reg_class) ito; | |
2214 | enum reg_class scratch, test; | |
2215 | ||
2216 | /* Simplify the following code by unifying the fp register classes. */ | |
2217 | if (to == FP_ACC_REGS) | |
2218 | to = FP_REGS; | |
2219 | if (from == FP_ACC_REGS) | |
2220 | from = FP_REGS; | |
2221 | ||
2222 | /* Diagnose invalid moves by costing them as two moves. */ | |
2223 | ||
2224 | scratch = NO_REGS; | |
2225 | test = from; | |
2226 | if (to == SP_REGS) | |
2227 | scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS); | |
c25a21f5 RH |
2228 | else if (to == MDR_REGS) |
2229 | scratch = DATA_REGS; | |
72d6e3c5 RH |
2230 | else if (to == FP_REGS && to != from) |
2231 | scratch = GENERAL_REGS; | |
2232 | else | |
2233 | { | |
2234 | test = to; | |
2235 | if (from == SP_REGS) | |
2236 | scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS); | |
c25a21f5 RH |
2237 | else if (from == MDR_REGS) |
2238 | scratch = DATA_REGS; | |
72d6e3c5 RH |
2239 | else if (from == FP_REGS && to != from) |
2240 | scratch = GENERAL_REGS; | |
2241 | } | |
2242 | if (scratch != NO_REGS && !reg_class_subset_p (test, scratch)) | |
2243 | return (mn10300_register_move_cost (VOIDmode, from, scratch) | |
2244 | + mn10300_register_move_cost (VOIDmode, scratch, to)); | |
460ad325 | 2245 | |
72d6e3c5 | 2246 | /* From here on, all we need consider are legal combinations. */ |
460ad325 | 2247 | |
72d6e3c5 RH |
2248 | if (optimize_size) |
2249 | { | |
2250 | /* The scale here is bytes * 2. */ | |
460ad325 | 2251 | |
72d6e3c5 RH |
2252 | if (from == to && (to == ADDRESS_REGS || to == DATA_REGS)) |
2253 | return 2; | |
460ad325 | 2254 | |
72d6e3c5 RH |
2255 | if (from == SP_REGS) |
2256 | return (to == ADDRESS_REGS ? 2 : 6); | |
2257 | ||
2258 | /* For MN103, all remaining legal moves are two bytes. */ | |
2259 | if (TARGET_AM33) | |
2260 | return 4; | |
2261 | ||
2262 | if (to == SP_REGS) | |
2263 | return (from == ADDRESS_REGS ? 4 : 6); | |
2264 | ||
2265 | if ((from == ADDRESS_REGS || from == DATA_REGS) | |
2266 | && (to == ADDRESS_REGS || to == DATA_REGS)) | |
2267 | return 4; | |
2268 | ||
2269 | if (to == EXTENDED_REGS) | |
2270 | return (to == from ? 6 : 4); | |
460ad325 | 2271 | |
72d6e3c5 RH |
2272 | /* What's left are SP_REGS, FP_REGS, or combinations of the above. */ |
2273 | return 6; | |
2274 | } | |
2275 | else | |
2276 | { | |
2277 | /* The scale here is cycles * 2. */ | |
2278 | ||
2279 | if (to == FP_REGS) | |
2280 | return 8; | |
2281 | if (from == FP_REGS) | |
2282 | return 4; | |
2283 | ||
2284 | /* All legal moves between integral registers are single cycle. */ | |
2285 | return 2; | |
460ad325 AO |
2286 | } |
2287 | } | |
3c50106f | 2288 | |
72d6e3c5 RH |
2289 | /* Implement the TARGET_MEMORY_MOVE_COST hook. |
2290 | ||
2291 | Given lack of the form of the address, this must be speed-relative, | |
2292 | though we should never be less expensive than a size-relative register | |
2293 | move cost above. This is not a problem. */ | |
2294 | ||
dcefdf67 | 2295 | static int |
72d6e3c5 RH |
2296 | mn10300_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, |
2297 | reg_class_t iclass, bool in ATTRIBUTE_UNUSED) | |
dcefdf67 | 2298 | { |
72d6e3c5 RH |
2299 | enum reg_class rclass = (enum reg_class) iclass; |
2300 | ||
2301 | if (rclass == FP_REGS) | |
2302 | return 8; | |
2303 | return 6; | |
dcefdf67 RH |
2304 | } |
2305 | ||
72d6e3c5 RH |
2306 | /* Implement the TARGET_RTX_COSTS hook. |
2307 | ||
2308 | Speed-relative costs are relative to COSTS_N_INSNS, which is intended | |
2309 | to represent cycles. Size-relative costs are in bytes. */ | |
2310 | ||
3c50106f | 2311 | static bool |
68f932c4 RS |
2312 | mn10300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
2313 | int *ptotal, bool speed) | |
3c50106f | 2314 | { |
72d6e3c5 RH |
2315 | /* This value is used for SYMBOL_REF etc where we want to pretend |
2316 | we have a full 32-bit constant. */ | |
2317 | HOST_WIDE_INT i = 0x12345678; | |
2318 | int total; | |
2319 | ||
3c50106f RH |
2320 | switch (code) |
2321 | { | |
2322 | case CONST_INT: | |
72d6e3c5 RH |
2323 | i = INTVAL (x); |
2324 | do_int_costs: | |
2325 | if (speed) | |
2326 | { | |
2327 | if (outer_code == SET) | |
2328 | { | |
2329 | /* 16-bit integer loads have latency 1, 32-bit loads 2. */ | |
2330 | if (IN_RANGE (i, -32768, 32767)) | |
2331 | total = COSTS_N_INSNS (1); | |
2332 | else | |
2333 | total = COSTS_N_INSNS (2); | |
2334 | } | |
2335 | else | |
2336 | { | |
2337 | /* 16-bit integer operands don't affect latency; | |
2338 | 24-bit and 32-bit operands add a cycle. */ | |
2339 | if (IN_RANGE (i, -32768, 32767)) | |
2340 | total = 0; | |
2341 | else | |
2342 | total = COSTS_N_INSNS (1); | |
2343 | } | |
2344 | } | |
3c50106f | 2345 | else |
72d6e3c5 RH |
2346 | { |
2347 | if (outer_code == SET) | |
2348 | { | |
2349 | if (i == 0) | |
2350 | total = 1; | |
2351 | else if (IN_RANGE (i, -128, 127)) | |
2352 | total = 2; | |
2353 | else if (IN_RANGE (i, -32768, 32767)) | |
2354 | total = 3; | |
2355 | else | |
2356 | total = 6; | |
2357 | } | |
2358 | else | |
2359 | { | |
2360 | /* Reference here is ADD An,Dn, vs ADD imm,Dn. */ | |
2361 | if (IN_RANGE (i, -128, 127)) | |
2362 | total = 0; | |
2363 | else if (IN_RANGE (i, -32768, 32767)) | |
2364 | total = 2; | |
2365 | else if (TARGET_AM33 && IN_RANGE (i, -0x01000000, 0x00ffffff)) | |
2366 | total = 3; | |
2367 | else | |
2368 | total = 4; | |
2369 | } | |
2370 | } | |
2371 | goto alldone; | |
3c50106f RH |
2372 | |
2373 | case CONST: | |
2374 | case LABEL_REF: | |
2375 | case SYMBOL_REF: | |
3c50106f | 2376 | case CONST_DOUBLE: |
72d6e3c5 RH |
2377 | /* We assume all of these require a 32-bit constant, even though |
2378 | some symbol and label references can be relaxed. */ | |
2379 | goto do_int_costs; | |
f90b7a5a | 2380 | |
72d6e3c5 RH |
2381 | case UNSPEC: |
2382 | switch (XINT (x, 1)) | |
2383 | { | |
2384 | case UNSPEC_PIC: | |
2385 | case UNSPEC_GOT: | |
2386 | case UNSPEC_GOTOFF: | |
2387 | case UNSPEC_PLT: | |
2388 | case UNSPEC_GOTSYM_OFF: | |
2389 | /* The PIC unspecs also resolve to a 32-bit constant. */ | |
2390 | goto do_int_costs; | |
3c50106f | 2391 | |
72d6e3c5 RH |
2392 | default: |
2393 | /* Assume any non-listed unspec is some sort of arithmetic. */ | |
2394 | goto do_arith_costs; | |
2395 | } | |
fe7496dd | 2396 | |
72d6e3c5 RH |
2397 | case PLUS: |
2398 | /* Notice the size difference of INC and INC4. */ | |
2399 | if (!speed && outer_code == SET && CONST_INT_P (XEXP (x, 1))) | |
2400 | { | |
2401 | i = INTVAL (XEXP (x, 1)); | |
2402 | if (i == 1 || i == 4) | |
2403 | { | |
68f932c4 | 2404 | total = 1 + rtx_cost (XEXP (x, 0), PLUS, 0, speed); |
72d6e3c5 RH |
2405 | goto alldone; |
2406 | } | |
2407 | } | |
2408 | goto do_arith_costs; | |
2409 | ||
2410 | case MINUS: | |
2411 | case AND: | |
2412 | case IOR: | |
2413 | case XOR: | |
2414 | case NOT: | |
2415 | case NEG: | |
2416 | case ZERO_EXTEND: | |
2417 | case SIGN_EXTEND: | |
2418 | case COMPARE: | |
2419 | case BSWAP: | |
2420 | case CLZ: | |
2421 | do_arith_costs: | |
2422 | total = (speed ? COSTS_N_INSNS (1) : 2); | |
2423 | break; | |
fe7496dd | 2424 | |
72d6e3c5 RH |
2425 | case ASHIFT: |
2426 | /* Notice the size difference of ASL2 and variants. */ | |
2427 | if (!speed && CONST_INT_P (XEXP (x, 1))) | |
2428 | switch (INTVAL (XEXP (x, 1))) | |
2429 | { | |
2430 | case 1: | |
2431 | case 2: | |
2432 | total = 1; | |
2433 | goto alldone; | |
2434 | case 3: | |
2435 | case 4: | |
2436 | total = 2; | |
2437 | goto alldone; | |
2438 | } | |
2439 | /* FALLTHRU */ | |
fe7496dd | 2440 | |
72d6e3c5 RH |
2441 | case ASHIFTRT: |
2442 | case LSHIFTRT: | |
2443 | total = (speed ? COSTS_N_INSNS (1) : 3); | |
2444 | goto alldone; | |
fe7496dd | 2445 | |
72d6e3c5 RH |
2446 | case MULT: |
2447 | total = (speed ? COSTS_N_INSNS (3) : 2); | |
fe7496dd | 2448 | break; |
5abc5de9 | 2449 | |
72d6e3c5 RH |
2450 | case DIV: |
2451 | case UDIV: | |
2452 | case MOD: | |
2453 | case UMOD: | |
2454 | total = (speed ? COSTS_N_INSNS (39) | |
2455 | /* Include space to load+retrieve MDR. */ | |
2456 | : code == MOD || code == UMOD ? 6 : 4); | |
fe7496dd | 2457 | break; |
5abc5de9 | 2458 | |
72d6e3c5 | 2459 | case MEM: |
b413068c OE |
2460 | total = mn10300_address_cost (XEXP (x, 0), GET_MODE (x), |
2461 | MEM_ADDR_SPACE (x), speed); | |
72d6e3c5 RH |
2462 | if (speed) |
2463 | total = COSTS_N_INSNS (2 + total); | |
2464 | goto alldone; | |
2465 | ||
fe7496dd | 2466 | default: |
72d6e3c5 RH |
2467 | /* Probably not implemented. Assume external call. */ |
2468 | total = (speed ? COSTS_N_INSNS (10) : 7); | |
2469 | break; | |
fe7496dd AO |
2470 | } |
2471 | ||
72d6e3c5 RH |
2472 | *ptotal = total; |
2473 | return false; | |
2474 | ||
2475 | alldone: | |
2476 | *ptotal = total; | |
2477 | return true; | |
fe7496dd | 2478 | } |
72d6e3c5 | 2479 | |
d1776069 AO |
2480 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2481 | may access it using GOTOFF instead of GOT. */ | |
2482 | ||
2483 | static void | |
2ba3d2a9 | 2484 | mn10300_encode_section_info (tree decl, rtx rtl, int first) |
d1776069 AO |
2485 | { |
2486 | rtx symbol; | |
2487 | ||
2ba3d2a9 NC |
2488 | default_encode_section_info (decl, rtl, first); |
2489 | ||
e7ab5593 | 2490 | if (! MEM_P (rtl)) |
d1776069 | 2491 | return; |
2ba3d2a9 | 2492 | |
d1776069 AO |
2493 | symbol = XEXP (rtl, 0); |
2494 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2495 | return; | |
2496 | ||
2497 | if (flag_pic) | |
2498 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2499 | } | |
e6ff3083 AS |
2500 | |
2501 | /* Dispatch tables on the mn10300 are extremely expensive in terms of code | |
2502 | and readonly data size. So we crank up the case threshold value to | |
2503 | encourage a series of if/else comparisons to implement many small switch | |
2504 | statements. In theory, this value could be increased much more if we | |
2505 | were solely optimizing for space, but we keep it "reasonable" to avoid | |
2506 | serious code efficiency lossage. */ | |
2507 | ||
4af476d7 NC |
2508 | static unsigned int |
2509 | mn10300_case_values_threshold (void) | |
e6ff3083 AS |
2510 | { |
2511 | return 6; | |
2512 | } | |
bdeb5f0c | 2513 | |
bdeb5f0c RH |
2514 | /* Worker function for TARGET_TRAMPOLINE_INIT. */ |
2515 | ||
2516 | static void | |
2517 | mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2518 | { | |
d6a3e264 RH |
2519 | rtx mem, disp, fnaddr = XEXP (DECL_RTL (fndecl), 0); |
2520 | ||
2521 | /* This is a strict alignment target, which means that we play | |
2522 | some games to make sure that the locations at which we need | |
2523 | to store <chain> and <disp> wind up at aligned addresses. | |
2524 | ||
2525 | 0x28 0x00 add 0,d0 | |
2526 | 0xfc 0xdd mov chain,a1 | |
2527 | <chain> | |
2528 | 0xf8 0xed 0x00 btst 0,d1 | |
2529 | 0xdc jmp fnaddr | |
2530 | <disp> | |
2531 | ||
2532 | Note that the two extra insns are effectively nops; they | |
2533 | clobber the flags but do not affect the contents of D0 or D1. */ | |
bdeb5f0c | 2534 | |
d6a3e264 | 2535 | disp = expand_binop (SImode, sub_optab, fnaddr, |
0a81f074 | 2536 | plus_constant (Pmode, XEXP (m_tramp, 0), 11), |
d6a3e264 | 2537 | NULL_RTX, 1, OPTAB_DIRECT); |
bdeb5f0c | 2538 | |
d6a3e264 RH |
2539 | mem = adjust_address (m_tramp, SImode, 0); |
2540 | emit_move_insn (mem, gen_int_mode (0xddfc0028, SImode)); | |
2541 | mem = adjust_address (m_tramp, SImode, 4); | |
bdeb5f0c | 2542 | emit_move_insn (mem, chain_value); |
d6a3e264 RH |
2543 | mem = adjust_address (m_tramp, SImode, 8); |
2544 | emit_move_insn (mem, gen_int_mode (0xdc00edf8, SImode)); | |
2545 | mem = adjust_address (m_tramp, SImode, 12); | |
2546 | emit_move_insn (mem, disp); | |
bdeb5f0c | 2547 | } |
990dc016 NC |
2548 | |
2549 | /* Output the assembler code for a C++ thunk function. | |
2550 | THUNK_DECL is the declaration for the thunk function itself, FUNCTION | |
2551 | is the decl for the target function. DELTA is an immediate constant | |
2552 | offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero | |
2553 | the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be | |
2554 | additionally added to THIS. Finally jump to the entry point of | |
2555 | FUNCTION. */ | |
2556 | ||
2557 | static void | |
2558 | mn10300_asm_output_mi_thunk (FILE * file, | |
2559 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2560 | HOST_WIDE_INT delta, | |
2561 | HOST_WIDE_INT vcall_offset, | |
2562 | tree function) | |
2563 | { | |
2564 | const char * _this; | |
2565 | ||
2566 | /* Get the register holding the THIS parameter. Handle the case | |
2567 | where there is a hidden first argument for a returned structure. */ | |
2568 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
2569 | _this = reg_names [FIRST_ARGUMENT_REGNUM + 1]; | |
2570 | else | |
2571 | _this = reg_names [FIRST_ARGUMENT_REGNUM]; | |
2572 | ||
2573 | fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START); | |
2574 | ||
2575 | if (delta) | |
2576 | fprintf (file, "\tadd %d, %s\n", (int) delta, _this); | |
2577 | ||
2578 | if (vcall_offset) | |
2579 | { | |
2580 | const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1]; | |
2581 | ||
2582 | fprintf (file, "\tmov %s, %s\n", _this, scratch); | |
2583 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2584 | fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch); | |
2585 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2586 | fprintf (file, "\tadd %s, %s\n", scratch, _this); | |
2587 | } | |
2588 | ||
2589 | fputs ("\tjmp ", file); | |
2590 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2591 | putc ('\n', file); | |
2592 | } | |
2593 | ||
2594 | /* Return true if mn10300_output_mi_thunk would be able to output the | |
2595 | assembler code for the thunk function specified by the arguments | |
2596 | it is passed, and false otherwise. */ | |
2597 | ||
2598 | static bool | |
2599 | mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2600 | HOST_WIDE_INT delta ATTRIBUTE_UNUSED, | |
2601 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2602 | const_tree function ATTRIBUTE_UNUSED) | |
2603 | { | |
2604 | return true; | |
2605 | } | |
4af476d7 NC |
2606 | |
2607 | bool | |
2608 | mn10300_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) | |
2609 | { | |
2610 | if (REGNO_REG_CLASS (regno) == FP_REGS | |
2611 | || REGNO_REG_CLASS (regno) == FP_ACC_REGS) | |
2612 | /* Do not store integer values in FP registers. */ | |
2613 | return GET_MODE_CLASS (mode) == MODE_FLOAT && ((regno & 1) == 0); | |
2614 | ||
2615 | if (((regno) & 1) == 0 || GET_MODE_SIZE (mode) == 4) | |
2616 | return true; | |
2617 | ||
2618 | if (REGNO_REG_CLASS (regno) == DATA_REGS | |
2619 | || (TARGET_AM33 && REGNO_REG_CLASS (regno) == ADDRESS_REGS) | |
2620 | || REGNO_REG_CLASS (regno) == EXTENDED_REGS) | |
2621 | return GET_MODE_SIZE (mode) <= 4; | |
2622 | ||
2623 | return false; | |
2624 | } | |
2625 | ||
2626 | bool | |
2627 | mn10300_modes_tieable (enum machine_mode mode1, enum machine_mode mode2) | |
2628 | { | |
2629 | if (GET_MODE_CLASS (mode1) == MODE_FLOAT | |
2630 | && GET_MODE_CLASS (mode2) != MODE_FLOAT) | |
2631 | return false; | |
2632 | ||
2633 | if (GET_MODE_CLASS (mode2) == MODE_FLOAT | |
2634 | && GET_MODE_CLASS (mode1) != MODE_FLOAT) | |
2635 | return false; | |
2636 | ||
2637 | if (TARGET_AM33 | |
2638 | || mode1 == mode2 | |
2639 | || (GET_MODE_SIZE (mode1) <= 4 && GET_MODE_SIZE (mode2) <= 4)) | |
2640 | return true; | |
2641 | ||
2642 | return false; | |
2643 | } | |
2644 | ||
bad41521 RH |
2645 | static int |
2646 | cc_flags_for_mode (enum machine_mode mode) | |
2647 | { | |
2648 | switch (mode) | |
2649 | { | |
2650 | case CCmode: | |
2651 | return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C | CC_FLAG_V; | |
2652 | case CCZNCmode: | |
2653 | return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C; | |
2654 | case CCZNmode: | |
2655 | return CC_FLAG_Z | CC_FLAG_N; | |
2656 | case CC_FLOATmode: | |
2657 | return -1; | |
2658 | default: | |
2659 | gcc_unreachable (); | |
2660 | } | |
2661 | } | |
2662 | ||
2663 | static int | |
2664 | cc_flags_for_code (enum rtx_code code) | |
2665 | { | |
2666 | switch (code) | |
2667 | { | |
2668 | case EQ: /* Z */ | |
2669 | case NE: /* ~Z */ | |
2670 | return CC_FLAG_Z; | |
2671 | ||
2672 | case LT: /* N */ | |
2673 | case GE: /* ~N */ | |
2674 | return CC_FLAG_N; | |
2675 | break; | |
2676 | ||
2677 | case GT: /* ~(Z|(N^V)) */ | |
2678 | case LE: /* Z|(N^V) */ | |
2679 | return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_V; | |
2680 | ||
2681 | case GEU: /* ~C */ | |
2682 | case LTU: /* C */ | |
2683 | return CC_FLAG_C; | |
2684 | ||
2685 | case GTU: /* ~(C | Z) */ | |
2686 | case LEU: /* C | Z */ | |
2687 | return CC_FLAG_Z | CC_FLAG_C; | |
2688 | ||
2689 | case ORDERED: | |
2690 | case UNORDERED: | |
2691 | case LTGT: | |
2692 | case UNEQ: | |
2693 | case UNGE: | |
2694 | case UNGT: | |
2695 | case UNLE: | |
2696 | case UNLT: | |
2697 | return -1; | |
2698 | ||
2699 | default: | |
2700 | gcc_unreachable (); | |
2701 | } | |
2702 | } | |
2703 | ||
4af476d7 | 2704 | enum machine_mode |
bad41521 | 2705 | mn10300_select_cc_mode (enum rtx_code code, rtx x, rtx y ATTRIBUTE_UNUSED) |
4af476d7 | 2706 | { |
bad41521 RH |
2707 | int req; |
2708 | ||
2709 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
2710 | return CC_FLOATmode; | |
2711 | ||
2712 | req = cc_flags_for_code (code); | |
2713 | ||
2714 | if (req & CC_FLAG_V) | |
2715 | return CCmode; | |
2716 | if (req & CC_FLAG_C) | |
2717 | return CCZNCmode; | |
2718 | return CCZNmode; | |
4af476d7 | 2719 | } |
f3f63737 NC |
2720 | |
2721 | static inline bool | |
2722 | is_load_insn (rtx insn) | |
2723 | { | |
2724 | if (GET_CODE (PATTERN (insn)) != SET) | |
2725 | return false; | |
2726 | ||
2727 | return MEM_P (SET_SRC (PATTERN (insn))); | |
2728 | } | |
2729 | ||
2730 | static inline bool | |
2731 | is_store_insn (rtx insn) | |
2732 | { | |
2733 | if (GET_CODE (PATTERN (insn)) != SET) | |
2734 | return false; | |
2735 | ||
2736 | return MEM_P (SET_DEST (PATTERN (insn))); | |
2737 | } | |
2738 | ||
2739 | /* Update scheduling costs for situations that cannot be | |
2740 | described using the attributes and DFA machinery. | |
2741 | DEP is the insn being scheduled. | |
2742 | INSN is the previous insn. | |
2743 | COST is the current cycle cost for DEP. */ | |
2744 | ||
2745 | static int | |
2746 | mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost) | |
2747 | { | |
2748 | int timings = get_attr_timings (insn); | |
2749 | ||
2750 | if (!TARGET_AM33) | |
2751 | return 1; | |
2752 | ||
2753 | if (GET_CODE (insn) == PARALLEL) | |
2754 | insn = XVECEXP (insn, 0, 0); | |
2755 | ||
2756 | if (GET_CODE (dep) == PARALLEL) | |
2757 | dep = XVECEXP (dep, 0, 0); | |
2758 | ||
2759 | /* For the AM34 a load instruction that follows a | |
2760 | store instruction incurs an extra cycle of delay. */ | |
2761 | if (mn10300_tune_cpu == PROCESSOR_AM34 | |
2762 | && is_load_insn (dep) | |
2763 | && is_store_insn (insn)) | |
2764 | cost += 1; | |
2765 | ||
2766 | /* For the AM34 a non-store, non-branch FPU insn that follows | |
2767 | another FPU insn incurs a one cycle throughput increase. */ | |
2768 | else if (mn10300_tune_cpu == PROCESSOR_AM34 | |
2769 | && ! is_store_insn (insn) | |
2770 | && ! JUMP_P (insn) | |
2771 | && GET_CODE (PATTERN (dep)) == SET | |
2772 | && GET_CODE (PATTERN (insn)) == SET | |
2773 | && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) == MODE_FLOAT | |
2774 | && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT) | |
2775 | cost += 1; | |
2776 | ||
2777 | /* Resolve the conflict described in section 1-7-4 of | |
2778 | Chapter 3 of the MN103E Series Instruction Manual | |
2779 | where it says: | |
2780 | ||
073a8998 | 2781 | "When the preceding instruction is a CPU load or |
f3f63737 NC |
2782 | store instruction, a following FPU instruction |
2783 | cannot be executed until the CPU completes the | |
2784 | latency period even though there are no register | |
2785 | or flag dependencies between them." */ | |
2786 | ||
2787 | /* Only the AM33-2 (and later) CPUs have FPU instructions. */ | |
2788 | if (! TARGET_AM33_2) | |
2789 | return cost; | |
2790 | ||
2791 | /* If a data dependence already exists then the cost is correct. */ | |
2792 | if (REG_NOTE_KIND (link) == 0) | |
2793 | return cost; | |
2794 | ||
2795 | /* Check that the instruction about to scheduled is an FPU instruction. */ | |
2796 | if (GET_CODE (PATTERN (dep)) != SET) | |
2797 | return cost; | |
2798 | ||
2799 | if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) != MODE_FLOAT) | |
2800 | return cost; | |
2801 | ||
2802 | /* Now check to see if the previous instruction is a load or store. */ | |
2803 | if (! is_load_insn (insn) && ! is_store_insn (insn)) | |
2804 | return cost; | |
2805 | ||
2806 | /* XXX: Verify: The text of 1-7-4 implies that the restriction | |
073a8998 | 2807 | only applies when an INTEGER load/store precedes an FPU |
f3f63737 NC |
2808 | instruction, but is this true ? For now we assume that it is. */ |
2809 | if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT) | |
2810 | return cost; | |
2811 | ||
2812 | /* Extract the latency value from the timings attribute. */ | |
2813 | return timings < 100 ? (timings % 10) : (timings % 100); | |
2814 | } | |
5efd84c5 NF |
2815 | |
2816 | static void | |
2817 | mn10300_conditional_register_usage (void) | |
2818 | { | |
2819 | unsigned int i; | |
2820 | ||
2821 | if (!TARGET_AM33) | |
2822 | { | |
2823 | for (i = FIRST_EXTENDED_REGNUM; | |
2824 | i <= LAST_EXTENDED_REGNUM; i++) | |
2825 | fixed_regs[i] = call_used_regs[i] = 1; | |
2826 | } | |
2827 | if (!TARGET_AM33_2) | |
2828 | { | |
2829 | for (i = FIRST_FP_REGNUM; | |
2830 | i <= LAST_FP_REGNUM; i++) | |
2831 | fixed_regs[i] = call_used_regs[i] = 1; | |
2832 | } | |
2833 | if (flag_pic) | |
2834 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = | |
2835 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
2836 | } | |
a49b692a RH |
2837 | |
2838 | /* Worker function for TARGET_MD_ASM_CLOBBERS. | |
2839 | We do this in the mn10300 backend to maintain source compatibility | |
2840 | with the old cc0-based compiler. */ | |
2841 | ||
2842 | static tree | |
2843 | mn10300_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED, | |
2844 | tree inputs ATTRIBUTE_UNUSED, | |
2845 | tree clobbers) | |
2846 | { | |
2847 | clobbers = tree_cons (NULL_TREE, build_string (5, "EPSW"), | |
2848 | clobbers); | |
2849 | return clobbers; | |
2850 | } | |
4af476d7 | 2851 | \f |
bad41521 RH |
2852 | /* A helper function for splitting cbranch patterns after reload. */ |
2853 | ||
2854 | void | |
2855 | mn10300_split_cbranch (enum machine_mode cmp_mode, rtx cmp_op, rtx label_ref) | |
2856 | { | |
2857 | rtx flags, x; | |
2858 | ||
2859 | flags = gen_rtx_REG (cmp_mode, CC_REG); | |
2860 | x = gen_rtx_COMPARE (cmp_mode, XEXP (cmp_op, 0), XEXP (cmp_op, 1)); | |
2861 | x = gen_rtx_SET (VOIDmode, flags, x); | |
2862 | emit_insn (x); | |
2863 | ||
2864 | x = gen_rtx_fmt_ee (GET_CODE (cmp_op), VOIDmode, flags, const0_rtx); | |
2865 | x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label_ref, pc_rtx); | |
2866 | x = gen_rtx_SET (VOIDmode, pc_rtx, x); | |
2867 | emit_jump_insn (x); | |
2868 | } | |
2869 | ||
2870 | /* A helper function for matching parallels that set the flags. */ | |
2871 | ||
2872 | bool | |
2873 | mn10300_match_ccmode (rtx insn, enum machine_mode cc_mode) | |
2874 | { | |
2875 | rtx op1, flags; | |
2876 | enum machine_mode flags_mode; | |
2877 | ||
2878 | gcc_checking_assert (XVECLEN (PATTERN (insn), 0) == 2); | |
2879 | ||
2880 | op1 = XVECEXP (PATTERN (insn), 0, 1); | |
2881 | gcc_checking_assert (GET_CODE (SET_SRC (op1)) == COMPARE); | |
2882 | ||
2883 | flags = SET_DEST (op1); | |
2884 | flags_mode = GET_MODE (flags); | |
2885 | ||
2886 | if (GET_MODE (SET_SRC (op1)) != flags_mode) | |
2887 | return false; | |
2888 | if (GET_MODE_CLASS (flags_mode) != MODE_CC) | |
2889 | return false; | |
2890 | ||
2891 | /* Ensure that the mode of FLAGS is compatible with CC_MODE. */ | |
2892 | if (cc_flags_for_mode (flags_mode) & ~cc_flags_for_mode (cc_mode)) | |
2893 | return false; | |
2894 | ||
2895 | return true; | |
2896 | } | |
2897 | ||
cf13d9cf NC |
2898 | /* This function is used to help split: |
2899 | ||
2900 | (set (reg) (and (reg) (int))) | |
2901 | ||
2902 | into: | |
2903 | ||
2904 | (set (reg) (shift (reg) (int)) | |
2905 | (set (reg) (shift (reg) (int)) | |
2906 | ||
2907 | where the shitfs will be shorter than the "and" insn. | |
2908 | ||
2909 | It returns the number of bits that should be shifted. A positive | |
2910 | values means that the low bits are to be cleared (and hence the | |
2911 | shifts should be right followed by left) whereas a negative value | |
2912 | means that the high bits are to be cleared (left followed by right). | |
2913 | Zero is returned when it would not be economical to split the AND. */ | |
2914 | ||
bad41521 RH |
2915 | int |
2916 | mn10300_split_and_operand_count (rtx op) | |
2917 | { | |
2918 | HOST_WIDE_INT val = INTVAL (op); | |
2919 | int count; | |
2920 | ||
2921 | if (val < 0) | |
2922 | { | |
2923 | /* High bit is set, look for bits clear at the bottom. */ | |
2924 | count = exact_log2 (-val); | |
2925 | if (count < 0) | |
2926 | return 0; | |
2927 | /* This is only size win if we can use the asl2 insn. Otherwise we | |
2928 | would be replacing 1 6-byte insn with 2 3-byte insns. */ | |
2929 | if (count > (optimize_insn_for_speed_p () ? 2 : 4)) | |
2930 | return 0; | |
cf13d9cf | 2931 | return count; |
bad41521 RH |
2932 | } |
2933 | else | |
2934 | { | |
2935 | /* High bit is clear, look for bits set at the bottom. */ | |
2936 | count = exact_log2 (val + 1); | |
2937 | count = 32 - count; | |
2938 | /* Again, this is only a size win with asl2. */ | |
2939 | if (count > (optimize_insn_for_speed_p () ? 2 : 4)) | |
2940 | return 0; | |
2941 | return -count; | |
2942 | } | |
2943 | } | |
2944 | \f | |
a45d420a NC |
2945 | struct liw_data |
2946 | { | |
2947 | enum attr_liw slot; | |
2948 | enum attr_liw_op op; | |
2949 | rtx dest; | |
2950 | rtx src; | |
2951 | }; | |
2952 | ||
2953 | /* Decide if the given insn is a candidate for LIW bundling. If it is then | |
2954 | extract the operands and LIW attributes from the insn and use them to fill | |
2955 | in the liw_data structure. Return true upon success or false if the insn | |
2956 | cannot be bundled. */ | |
298362c8 NC |
2957 | |
2958 | static bool | |
a45d420a | 2959 | extract_bundle (rtx insn, struct liw_data * pdata) |
298362c8 | 2960 | { |
a45d420a | 2961 | bool allow_consts = true; |
2cf320a8 | 2962 | rtx p; |
298362c8 | 2963 | |
a45d420a NC |
2964 | gcc_assert (pdata != NULL); |
2965 | ||
2966 | if (insn == NULL_RTX) | |
2967 | return false; | |
2968 | /* Make sure that we are dealing with a simple SET insn. */ | |
298362c8 | 2969 | p = single_set (insn); |
a45d420a NC |
2970 | if (p == NULL_RTX) |
2971 | return false; | |
2972 | ||
2973 | /* Make sure that it could go into one of the LIW pipelines. */ | |
2974 | pdata->slot = get_attr_liw (insn); | |
2975 | if (pdata->slot == LIW_BOTH) | |
2976 | return false; | |
2977 | ||
2978 | pdata->op = get_attr_liw_op (insn); | |
2979 | ||
a45d420a | 2980 | switch (pdata->op) |
298362c8 NC |
2981 | { |
2982 | case LIW_OP_MOV: | |
a45d420a NC |
2983 | pdata->dest = SET_DEST (p); |
2984 | pdata->src = SET_SRC (p); | |
298362c8 NC |
2985 | break; |
2986 | case LIW_OP_CMP: | |
a45d420a NC |
2987 | pdata->dest = XEXP (SET_SRC (p), 0); |
2988 | pdata->src = XEXP (SET_SRC (p), 1); | |
298362c8 NC |
2989 | break; |
2990 | case LIW_OP_NONE: | |
2991 | return false; | |
a45d420a NC |
2992 | case LIW_OP_AND: |
2993 | case LIW_OP_OR: | |
2994 | case LIW_OP_XOR: | |
2995 | /* The AND, OR and XOR long instruction words only accept register arguments. */ | |
2996 | allow_consts = false; | |
2997 | /* Fall through. */ | |
298362c8 | 2998 | default: |
a45d420a NC |
2999 | pdata->dest = SET_DEST (p); |
3000 | pdata->src = XEXP (SET_SRC (p), 1); | |
298362c8 NC |
3001 | break; |
3002 | } | |
3003 | ||
a45d420a NC |
3004 | if (! REG_P (pdata->dest)) |
3005 | return false; | |
3006 | ||
3007 | if (REG_P (pdata->src)) | |
3008 | return true; | |
3009 | ||
3010 | return allow_consts && satisfies_constraint_O (pdata->src); | |
298362c8 NC |
3011 | } |
3012 | ||
a45d420a NC |
3013 | /* Make sure that it is OK to execute LIW1 and LIW2 in parallel. GCC generated |
3014 | the instructions with the assumption that LIW1 would be executed before LIW2 | |
3015 | so we must check for overlaps between their sources and destinations. */ | |
298362c8 NC |
3016 | |
3017 | static bool | |
a45d420a NC |
3018 | check_liw_constraints (struct liw_data * pliw1, struct liw_data * pliw2) |
3019 | { | |
3020 | /* Check for slot conflicts. */ | |
3021 | if (pliw2->slot == pliw1->slot && pliw1->slot != LIW_EITHER) | |
298362c8 NC |
3022 | return false; |
3023 | ||
a45d420a NC |
3024 | /* If either operation is a compare, then "dest" is really an input; the real |
3025 | destination is CC_REG. So these instructions need different checks. */ | |
3026 | ||
3027 | /* Changing "CMP ; OP" into "CMP | OP" is OK because the comparison will | |
3028 | check its values prior to any changes made by OP. */ | |
3029 | if (pliw1->op == LIW_OP_CMP) | |
3030 | { | |
3031 | /* Two sequential comparisons means dead code, which ought to | |
3032 | have been eliminated given that bundling only happens with | |
3033 | optimization. We cannot bundle them in any case. */ | |
3034 | gcc_assert (pliw1->op != pliw2->op); | |
3035 | return true; | |
3036 | } | |
298362c8 | 3037 | |
a45d420a NC |
3038 | /* Changing "OP ; CMP" into "OP | CMP" does not work if the value being compared |
3039 | is the destination of OP, as the CMP will look at the old value, not the new | |
3040 | one. */ | |
3041 | if (pliw2->op == LIW_OP_CMP) | |
298362c8 | 3042 | { |
a45d420a NC |
3043 | if (REGNO (pliw2->dest) == REGNO (pliw1->dest)) |
3044 | return false; | |
3045 | ||
3046 | if (REG_P (pliw2->src)) | |
3047 | return REGNO (pliw2->src) != REGNO (pliw1->dest); | |
3048 | ||
3049 | return true; | |
3050 | } | |
3051 | ||
3052 | /* Changing "OP1 ; OP2" into "OP1 | OP2" does not work if they both write to the | |
3053 | same destination register. */ | |
3054 | if (REGNO (pliw2->dest) == REGNO (pliw1->dest)) | |
3055 | return false; | |
3056 | ||
3057 | /* Changing "OP1 ; OP2" into "OP1 | OP2" generally does not work if the destination | |
3058 | of OP1 is the source of OP2. The exception is when OP1 is a MOVE instruction when | |
3059 | we can replace the source in OP2 with the source of OP1. */ | |
3060 | if (REG_P (pliw2->src) && REGNO (pliw2->src) == REGNO (pliw1->dest)) | |
3061 | { | |
3062 | if (pliw1->op == LIW_OP_MOV && REG_P (pliw1->src)) | |
298362c8 | 3063 | { |
a45d420a NC |
3064 | if (! REG_P (pliw1->src) |
3065 | && (pliw2->op == LIW_OP_AND | |
3066 | || pliw2->op == LIW_OP_OR | |
3067 | || pliw2->op == LIW_OP_XOR)) | |
3068 | return false; | |
3069 | ||
3070 | pliw2->src = pliw1->src; | |
298362c8 NC |
3071 | return true; |
3072 | } | |
3073 | return false; | |
3074 | } | |
3075 | ||
a45d420a | 3076 | /* Everything else is OK. */ |
298362c8 NC |
3077 | return true; |
3078 | } | |
3079 | ||
298362c8 NC |
3080 | /* Combine pairs of insns into LIW bundles. */ |
3081 | ||
3082 | static void | |
3083 | mn10300_bundle_liw (void) | |
3084 | { | |
3085 | rtx r; | |
3086 | ||
3087 | for (r = get_insns (); r != NULL_RTX; r = next_nonnote_nondebug_insn (r)) | |
3088 | { | |
a45d420a NC |
3089 | rtx insn1, insn2; |
3090 | struct liw_data liw1, liw2; | |
298362c8 NC |
3091 | |
3092 | insn1 = r; | |
a45d420a | 3093 | if (! extract_bundle (insn1, & liw1)) |
298362c8 NC |
3094 | continue; |
3095 | ||
3096 | insn2 = next_nonnote_nondebug_insn (insn1); | |
a45d420a | 3097 | if (! extract_bundle (insn2, & liw2)) |
298362c8 NC |
3098 | continue; |
3099 | ||
a45d420a NC |
3100 | /* Check for source/destination overlap. */ |
3101 | if (! check_liw_constraints (& liw1, & liw2)) | |
298362c8 NC |
3102 | continue; |
3103 | ||
a45d420a | 3104 | if (liw1.slot == LIW_OP2 || liw2.slot == LIW_OP1) |
298362c8 | 3105 | { |
a45d420a NC |
3106 | struct liw_data temp; |
3107 | ||
3108 | temp = liw1; | |
298362c8 | 3109 | liw1 = liw2; |
a45d420a | 3110 | liw2 = temp; |
298362c8 NC |
3111 | } |
3112 | ||
298362c8 NC |
3113 | delete_insn (insn2); |
3114 | ||
a45d420a NC |
3115 | if (liw1.op == LIW_OP_CMP) |
3116 | insn2 = gen_cmp_liw (liw2.dest, liw2.src, liw1.dest, liw1.src, | |
3117 | GEN_INT (liw2.op)); | |
3118 | else if (liw2.op == LIW_OP_CMP) | |
3119 | insn2 = gen_liw_cmp (liw1.dest, liw1.src, liw2.dest, liw2.src, | |
3120 | GEN_INT (liw1.op)); | |
298362c8 | 3121 | else |
a45d420a NC |
3122 | insn2 = gen_liw (liw1.dest, liw2.dest, liw1.src, liw2.src, |
3123 | GEN_INT (liw1.op), GEN_INT (liw2.op)); | |
298362c8 NC |
3124 | |
3125 | insn2 = emit_insn_after (insn2, insn1); | |
3126 | delete_insn (insn1); | |
3127 | r = insn2; | |
3128 | } | |
3129 | } | |
3130 | ||
662c03f4 NC |
3131 | #define DUMP(reason, insn) \ |
3132 | do \ | |
3133 | { \ | |
3134 | if (dump_file) \ | |
3135 | { \ | |
3136 | fprintf (dump_file, reason "\n"); \ | |
3137 | if (insn != NULL_RTX) \ | |
3138 | print_rtl_single (dump_file, insn); \ | |
3139 | fprintf(dump_file, "\n"); \ | |
3140 | } \ | |
3141 | } \ | |
3142 | while (0) | |
3143 | ||
3144 | /* Replace the BRANCH insn with a Lcc insn that goes to LABEL. | |
3145 | Insert a SETLB insn just before LABEL. */ | |
3146 | ||
3147 | static void | |
3148 | mn10300_insert_setlb_lcc (rtx label, rtx branch) | |
3149 | { | |
3150 | rtx lcc, comparison, cmp_reg; | |
3151 | ||
3152 | if (LABEL_NUSES (label) > 1) | |
3153 | { | |
3154 | rtx insn; | |
3155 | ||
3156 | /* This label is used both as an entry point to the loop | |
3157 | and as a loop-back point for the loop. We need to separate | |
3158 | these two functions so that the SETLB happens upon entry, | |
3159 | but the loop-back does not go to the SETLB instruction. */ | |
3160 | DUMP ("Inserting SETLB insn after:", label); | |
3161 | insn = emit_insn_after (gen_setlb (), label); | |
3162 | label = gen_label_rtx (); | |
3163 | emit_label_after (label, insn); | |
3164 | DUMP ("Created new loop-back label:", label); | |
3165 | } | |
3166 | else | |
3167 | { | |
3168 | DUMP ("Inserting SETLB insn before:", label); | |
3169 | emit_insn_before (gen_setlb (), label); | |
3170 | } | |
3171 | ||
3172 | comparison = XEXP (SET_SRC (PATTERN (branch)), 0); | |
3173 | cmp_reg = XEXP (comparison, 0); | |
3174 | gcc_assert (REG_P (cmp_reg)); | |
3175 | ||
3176 | /* If the comparison has not already been split out of the branch | |
3177 | then do so now. */ | |
3178 | gcc_assert (REGNO (cmp_reg) == CC_REG); | |
3179 | ||
3180 | if (GET_MODE (cmp_reg) == CC_FLOATmode) | |
3181 | lcc = gen_FLcc (comparison, label); | |
3182 | else | |
3183 | lcc = gen_Lcc (comparison, label); | |
3184 | ||
3185 | lcc = emit_jump_insn_before (lcc, branch); | |
3186 | mark_jump_label (XVECEXP (PATTERN (lcc), 0, 0), lcc, 0); | |
da73162f | 3187 | JUMP_LABEL (lcc) = label; |
662c03f4 NC |
3188 | DUMP ("Replacing branch insn...", branch); |
3189 | DUMP ("... with Lcc insn:", lcc); | |
3190 | delete_insn (branch); | |
3191 | } | |
3192 | ||
3193 | static bool | |
b8244d74 | 3194 | mn10300_block_contains_call (basic_block block) |
662c03f4 NC |
3195 | { |
3196 | rtx insn; | |
3197 | ||
3198 | FOR_BB_INSNS (block, insn) | |
3199 | if (CALL_P (insn)) | |
3200 | return true; | |
3201 | ||
3202 | return false; | |
3203 | } | |
3204 | ||
3205 | static bool | |
3206 | mn10300_loop_contains_call_insn (loop_p loop) | |
3207 | { | |
3208 | basic_block * bbs; | |
3209 | bool result = false; | |
3210 | unsigned int i; | |
3211 | ||
3212 | bbs = get_loop_body (loop); | |
3213 | ||
3214 | for (i = 0; i < loop->num_nodes; i++) | |
3215 | if (mn10300_block_contains_call (bbs[i])) | |
3216 | { | |
3217 | result = true; | |
3218 | break; | |
3219 | } | |
3220 | ||
3221 | free (bbs); | |
3222 | return result; | |
3223 | } | |
3224 | ||
3225 | static void | |
3226 | mn10300_scan_for_setlb_lcc (void) | |
3227 | { | |
662c03f4 NC |
3228 | loop_iterator liter; |
3229 | loop_p loop; | |
3230 | ||
3231 | DUMP ("Looking for loops that can use the SETLB insn", NULL_RTX); | |
3232 | ||
3233 | df_analyze (); | |
3234 | compute_bb_for_insn (); | |
3235 | ||
3236 | /* Find the loops. */ | |
4861a1f7 | 3237 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS); |
662c03f4 NC |
3238 | |
3239 | /* FIXME: For now we only investigate innermost loops. In practice however | |
3240 | if an inner loop is not suitable for use with the SETLB/Lcc insns, it may | |
3241 | be the case that its parent loop is suitable. Thus we should check all | |
3242 | loops, but work from the innermost outwards. */ | |
3243 | FOR_EACH_LOOP (liter, loop, LI_ONLY_INNERMOST) | |
3244 | { | |
3245 | const char * reason = NULL; | |
3246 | ||
3247 | /* Check to see if we can modify this loop. If we cannot | |
3248 | then set 'reason' to describe why it could not be done. */ | |
3249 | if (loop->latch == NULL) | |
3250 | reason = "it contains multiple latches"; | |
3251 | else if (loop->header != loop->latch) | |
3252 | /* FIXME: We could handle loops that span multiple blocks, | |
3253 | but this requires a lot more work tracking down the branches | |
3254 | that need altering, so for now keep things simple. */ | |
3255 | reason = "the loop spans multiple blocks"; | |
3256 | else if (mn10300_loop_contains_call_insn (loop)) | |
3257 | reason = "it contains CALL insns"; | |
3258 | else | |
3259 | { | |
3260 | rtx branch = BB_END (loop->latch); | |
3261 | ||
3262 | gcc_assert (JUMP_P (branch)); | |
3263 | if (single_set (branch) == NULL_RTX || ! any_condjump_p (branch)) | |
3264 | /* We cannot optimize tablejumps and the like. */ | |
3265 | /* FIXME: We could handle unconditional jumps. */ | |
3266 | reason = "it is not a simple loop"; | |
3267 | else | |
3268 | { | |
3269 | rtx label; | |
3270 | ||
3271 | if (dump_file) | |
3272 | flow_loop_dump (loop, dump_file, NULL, 0); | |
3273 | ||
3274 | label = BB_HEAD (loop->header); | |
3275 | gcc_assert (LABEL_P (label)); | |
3276 | ||
3277 | mn10300_insert_setlb_lcc (label, branch); | |
3278 | } | |
3279 | } | |
3280 | ||
3281 | if (dump_file && reason != NULL) | |
3282 | fprintf (dump_file, "Loop starting with insn %d is not suitable because %s\n", | |
3283 | INSN_UID (BB_HEAD (loop->header)), | |
3284 | reason); | |
3285 | } | |
3286 | ||
4861a1f7 | 3287 | loop_optimizer_finalize (); |
662c03f4 NC |
3288 | |
3289 | df_finish_pass (false); | |
3290 | ||
3291 | DUMP ("SETLB scan complete", NULL_RTX); | |
3292 | } | |
3293 | ||
298362c8 NC |
3294 | static void |
3295 | mn10300_reorg (void) | |
3296 | { | |
662c03f4 NC |
3297 | /* These are optimizations, so only run them if optimizing. */ |
3298 | if (TARGET_AM33 && (optimize > 0 || optimize_size)) | |
298362c8 | 3299 | { |
662c03f4 NC |
3300 | if (TARGET_ALLOW_SETLB) |
3301 | mn10300_scan_for_setlb_lcc (); | |
3302 | ||
298362c8 NC |
3303 | if (TARGET_ALLOW_LIW) |
3304 | mn10300_bundle_liw (); | |
3305 | } | |
3306 | } | |
3307 | \f | |
e7ab5593 NC |
3308 | /* Initialize the GCC target structure. */ |
3309 | ||
298362c8 NC |
3310 | #undef TARGET_MACHINE_DEPENDENT_REORG |
3311 | #define TARGET_MACHINE_DEPENDENT_REORG mn10300_reorg | |
3312 | ||
e7ab5593 NC |
3313 | #undef TARGET_ASM_ALIGNED_HI_OP |
3314 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
3315 | ||
3316 | #undef TARGET_LEGITIMIZE_ADDRESS | |
3317 | #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address | |
3318 | ||
72d6e3c5 RH |
3319 | #undef TARGET_ADDRESS_COST |
3320 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
3321 | #undef TARGET_REGISTER_MOVE_COST | |
3322 | #define TARGET_REGISTER_MOVE_COST mn10300_register_move_cost | |
3323 | #undef TARGET_MEMORY_MOVE_COST | |
3324 | #define TARGET_MEMORY_MOVE_COST mn10300_memory_move_cost | |
e7ab5593 NC |
3325 | #undef TARGET_RTX_COSTS |
3326 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
e7ab5593 NC |
3327 | |
3328 | #undef TARGET_ASM_FILE_START | |
3329 | #define TARGET_ASM_FILE_START mn10300_file_start | |
3330 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
3331 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
3332 | ||
535bd17c AS |
3333 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
3334 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA mn10300_asm_output_addr_const_extra | |
3335 | ||
e7ab5593 NC |
3336 | #undef TARGET_OPTION_OVERRIDE |
3337 | #define TARGET_OPTION_OVERRIDE mn10300_option_override | |
3338 | ||
3339 | #undef TARGET_ENCODE_SECTION_INFO | |
3340 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
3341 | ||
3342 | #undef TARGET_PROMOTE_PROTOTYPES | |
3343 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
3344 | #undef TARGET_RETURN_IN_MEMORY | |
3345 | #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory | |
3346 | #undef TARGET_PASS_BY_REFERENCE | |
3347 | #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference | |
3348 | #undef TARGET_CALLEE_COPIES | |
3349 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
3350 | #undef TARGET_ARG_PARTIAL_BYTES | |
3351 | #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes | |
ce236858 NF |
3352 | #undef TARGET_FUNCTION_ARG |
3353 | #define TARGET_FUNCTION_ARG mn10300_function_arg | |
3354 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
3355 | #define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance | |
e7ab5593 NC |
3356 | |
3357 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
3358 | #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs | |
3359 | #undef TARGET_EXPAND_BUILTIN_VA_START | |
3360 | #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start | |
3361 | ||
3362 | #undef TARGET_CASE_VALUES_THRESHOLD | |
3363 | #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold | |
3364 | ||
3365 | #undef TARGET_LEGITIMATE_ADDRESS_P | |
3366 | #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p | |
126b1483 RH |
3367 | #undef TARGET_DELEGITIMIZE_ADDRESS |
3368 | #define TARGET_DELEGITIMIZE_ADDRESS mn10300_delegitimize_address | |
1a627b35 RS |
3369 | #undef TARGET_LEGITIMATE_CONSTANT_P |
3370 | #define TARGET_LEGITIMATE_CONSTANT_P mn10300_legitimate_constant_p | |
e7ab5593 | 3371 | |
f2831cc9 AS |
3372 | #undef TARGET_PREFERRED_RELOAD_CLASS |
3373 | #define TARGET_PREFERRED_RELOAD_CLASS mn10300_preferred_reload_class | |
3374 | #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS | |
8b119bb6 RH |
3375 | #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS \ |
3376 | mn10300_preferred_output_reload_class | |
3377 | #undef TARGET_SECONDARY_RELOAD | |
3378 | #define TARGET_SECONDARY_RELOAD mn10300_secondary_reload | |
f2831cc9 | 3379 | |
e7ab5593 NC |
3380 | #undef TARGET_TRAMPOLINE_INIT |
3381 | #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init | |
3382 | ||
3383 | #undef TARGET_FUNCTION_VALUE | |
3384 | #define TARGET_FUNCTION_VALUE mn10300_function_value | |
3385 | #undef TARGET_LIBCALL_VALUE | |
3386 | #define TARGET_LIBCALL_VALUE mn10300_libcall_value | |
3387 | ||
3388 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
3389 | #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk | |
3390 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
3391 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk | |
3392 | ||
f3f63737 NC |
3393 | #undef TARGET_SCHED_ADJUST_COST |
3394 | #define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost | |
3395 | ||
5efd84c5 NF |
3396 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
3397 | #define TARGET_CONDITIONAL_REGISTER_USAGE mn10300_conditional_register_usage | |
3398 | ||
a49b692a RH |
3399 | #undef TARGET_MD_ASM_CLOBBERS |
3400 | #define TARGET_MD_ASM_CLOBBERS mn10300_md_asm_clobbers | |
3401 | ||
3843787f RH |
3402 | #undef TARGET_FLAGS_REGNUM |
3403 | #define TARGET_FLAGS_REGNUM CC_REG | |
3404 | ||
e7ab5593 | 3405 | struct gcc_target targetm = TARGET_INITIALIZER; |