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29a404f9 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
f2d49d02 | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 |
6e31cc90 | 3 | Free Software Foundation, Inc. |
29a404f9 | 4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
187b36cf | 6 | This file is part of GCC. |
29a404f9 | 7 | |
187b36cf | 8 | GCC is free software; you can redistribute it and/or modify |
29a404f9 | 9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
187b36cf | 13 | GCC is distributed in the hope that it will be useful, |
29a404f9 | 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
187b36cf | 19 | along with GCC; see the file COPYING. If not, write to |
29a404f9 | 20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
29a404f9 | 23 | #include "config.h" |
7014838c | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
29a404f9 | 27 | #include "rtl.h" |
4faf81b8 | 28 | #include "tree.h" |
29a404f9 | 29 | #include "regs.h" |
30 | #include "hard-reg-set.h" | |
31 | #include "real.h" | |
32 | #include "insn-config.h" | |
33 | #include "conditions.h" | |
29a404f9 | 34 | #include "output.h" |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "recog.h" | |
38 | #include "expr.h" | |
d8fc4d0b | 39 | #include "optabs.h" |
4faf81b8 | 40 | #include "function.h" |
29a404f9 | 41 | #include "obstack.h" |
59086782 | 42 | #include "toplev.h" |
43 | #include "tm_p.h" | |
a767736d | 44 | #include "target.h" |
45 | #include "target-def.h" | |
29a404f9 | 46 | |
b87a151a | 47 | /* This is used by GOTaddr2picreg to uniquely identify |
48 | UNSPEC_INT_LABELs. */ | |
49 | int mn10300_unspec_int_label_counter; | |
50 | ||
1acdfc69 | 51 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
52 | names are not prefixed by underscores, to tell whether to prefix a | |
53 | label with a plus sign or not, so that the assembler can tell | |
54 | symbol names from register names. */ | |
55 | int mn10300_protect_label; | |
56 | ||
8ecf154e | 57 | /* The size of the callee register save area. Right now we save everything |
58 | on entry since it costs us nothing in code size. It does cost us from a | |
59 | speed standpoint, so we want to optimize this sooner or later. */ | |
3bcd7b00 | 60 | #define REG_SAVE_BYTES (4 * regs_ever_live[2] \ |
61 | + 4 * regs_ever_live[3] \ | |
911517ac | 62 | + 4 * regs_ever_live[6] \ |
63 | + 4 * regs_ever_live[7] \ | |
64 | + 16 * (regs_ever_live[14] || regs_ever_live[15] \ | |
65 | || regs_ever_live[16] || regs_ever_live[17])) | |
fab7adbf | 66 | |
67 | ||
0792f2cf | 68 | static int mn10300_address_cost_1 (rtx, int *); |
69 | static int mn10300_address_cost (rtx); | |
70 | static bool mn10300_rtx_costs (rtx, int, int, int *); | |
71 | static void mn10300_file_start (void); | |
f2d49d02 | 72 | static bool mn10300_return_in_memory (tree, tree); |
73 | static rtx mn10300_builtin_saveregs (void); | |
b981d932 | 74 | static bool mn10300_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
75 | tree, bool); | |
a767736d | 76 | \f |
77 | /* Initialize the GCC target structure. */ | |
58356836 | 78 | #undef TARGET_ASM_ALIGNED_HI_OP |
79 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
8ecf154e | 80 | |
fab7adbf | 81 | #undef TARGET_RTX_COSTS |
82 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
ec0457a8 | 83 | #undef TARGET_ADDRESS_COST |
84 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
fab7adbf | 85 | |
92c473b8 | 86 | #undef TARGET_ASM_FILE_START |
87 | #define TARGET_ASM_FILE_START mn10300_file_start | |
88 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
89 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
90 | ||
b87a151a | 91 | #undef TARGET_ENCODE_SECTION_INFO |
92 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
93 | ||
f2d49d02 | 94 | #undef TARGET_PROMOTE_PROTOTYPES |
95 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
f2d49d02 | 96 | #undef TARGET_RETURN_IN_MEMORY |
97 | #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory | |
b981d932 | 98 | #undef TARGET_PASS_BY_REFERENCE |
99 | #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference | |
13f08ee7 | 100 | #undef TARGET_CALLEE_COPIES |
101 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
f2d49d02 | 102 | |
103 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
104 | #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs | |
105 | ||
b87a151a | 106 | static void mn10300_encode_section_info (tree, rtx, int); |
57e4bbfb | 107 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 108 | \f |
92c473b8 | 109 | static void |
3285410a | 110 | mn10300_file_start (void) |
29a404f9 | 111 | { |
92c473b8 | 112 | default_file_start (); |
911517ac | 113 | |
b166356e | 114 | if (TARGET_AM33_2) |
115 | fprintf (asm_out_file, "\t.am33_2\n"); | |
116 | else if (TARGET_AM33) | |
92c473b8 | 117 | fprintf (asm_out_file, "\t.am33\n"); |
29a404f9 | 118 | } |
119 | \f | |
120 | ||
29a404f9 | 121 | /* Print operand X using operand code CODE to assembly language output file |
122 | FILE. */ | |
123 | ||
124 | void | |
3285410a | 125 | print_operand (FILE *file, rtx x, int code) |
29a404f9 | 126 | { |
127 | switch (code) | |
128 | { | |
129 | case 'b': | |
130 | case 'B': | |
b166356e | 131 | if (cc_status.mdep.fpCC) |
132 | { | |
133 | switch (code == 'b' ? GET_CODE (x) | |
134 | : reverse_condition_maybe_unordered (GET_CODE (x))) | |
135 | { | |
136 | case NE: | |
137 | fprintf (file, "ne"); | |
138 | break; | |
139 | case EQ: | |
140 | fprintf (file, "eq"); | |
141 | break; | |
142 | case GE: | |
143 | fprintf (file, "ge"); | |
144 | break; | |
145 | case GT: | |
146 | fprintf (file, "gt"); | |
147 | break; | |
148 | case LE: | |
149 | fprintf (file, "le"); | |
150 | break; | |
151 | case LT: | |
152 | fprintf (file, "lt"); | |
153 | break; | |
154 | case ORDERED: | |
155 | fprintf (file, "lge"); | |
156 | break; | |
157 | case UNORDERED: | |
158 | fprintf (file, "uo"); | |
159 | break; | |
160 | case LTGT: | |
161 | fprintf (file, "lg"); | |
162 | break; | |
163 | case UNEQ: | |
164 | fprintf (file, "ue"); | |
165 | break; | |
166 | case UNGE: | |
167 | fprintf (file, "uge"); | |
168 | break; | |
169 | case UNGT: | |
170 | fprintf (file, "ug"); | |
171 | break; | |
172 | case UNLE: | |
173 | fprintf (file, "ule"); | |
174 | break; | |
175 | case UNLT: | |
176 | fprintf (file, "ul"); | |
177 | break; | |
178 | default: | |
179 | abort (); | |
180 | } | |
181 | break; | |
182 | } | |
29a404f9 | 183 | /* These are normal and reversed branches. */ |
184 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
185 | { | |
186 | case NE: | |
187 | fprintf (file, "ne"); | |
188 | break; | |
189 | case EQ: | |
190 | fprintf (file, "eq"); | |
191 | break; | |
192 | case GE: | |
193 | fprintf (file, "ge"); | |
194 | break; | |
195 | case GT: | |
196 | fprintf (file, "gt"); | |
197 | break; | |
198 | case LE: | |
199 | fprintf (file, "le"); | |
200 | break; | |
201 | case LT: | |
202 | fprintf (file, "lt"); | |
203 | break; | |
204 | case GEU: | |
205 | fprintf (file, "cc"); | |
206 | break; | |
207 | case GTU: | |
208 | fprintf (file, "hi"); | |
209 | break; | |
210 | case LEU: | |
211 | fprintf (file, "ls"); | |
212 | break; | |
213 | case LTU: | |
214 | fprintf (file, "cs"); | |
215 | break; | |
216 | default: | |
217 | abort (); | |
218 | } | |
219 | break; | |
220 | case 'C': | |
221 | /* This is used for the operand to a call instruction; | |
222 | if it's a REG, enclose it in parens, else output | |
223 | the operand normally. */ | |
224 | if (GET_CODE (x) == REG) | |
225 | { | |
226 | fputc ('(', file); | |
227 | print_operand (file, x, 0); | |
228 | fputc (')', file); | |
229 | } | |
230 | else | |
231 | print_operand (file, x, 0); | |
232 | break; | |
233 | ||
b166356e | 234 | case 'D': |
235 | switch (GET_CODE (x)) | |
236 | { | |
237 | case MEM: | |
238 | fputc ('(', file); | |
239 | output_address (XEXP (x, 0)); | |
240 | fputc (')', file); | |
241 | break; | |
242 | ||
243 | case REG: | |
244 | fprintf (file, "fd%d", REGNO (x) - 18); | |
245 | break; | |
246 | ||
247 | default: | |
248 | abort (); | |
249 | } | |
250 | break; | |
251 | ||
6ce19398 | 252 | /* These are the least significant word in a 64bit value. */ |
253 | case 'L': | |
254 | switch (GET_CODE (x)) | |
255 | { | |
256 | case MEM: | |
257 | fputc ('(', file); | |
258 | output_address (XEXP (x, 0)); | |
259 | fputc (')', file); | |
260 | break; | |
261 | ||
262 | case REG: | |
263 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
264 | break; | |
265 | ||
266 | case SUBREG: | |
701e46d0 | 267 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
6ce19398 | 268 | break; |
269 | ||
270 | case CONST_DOUBLE: | |
271 | { | |
272 | long val[2]; | |
273 | REAL_VALUE_TYPE rv; | |
274 | ||
275 | switch (GET_MODE (x)) | |
276 | { | |
277 | case DFmode: | |
278 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
279 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 280 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 281 | break;; |
282 | case SFmode: | |
283 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
284 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
ad3c0f03 | 285 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 286 | break;; |
287 | case VOIDmode: | |
288 | case DImode: | |
289 | print_operand_address (file, | |
290 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
291 | break; | |
59086782 | 292 | default: |
293 | break; | |
6ce19398 | 294 | } |
295 | break; | |
296 | } | |
297 | ||
298 | case CONST_INT: | |
964d057c | 299 | { |
300 | rtx low, high; | |
301 | split_double (x, &low, &high); | |
302 | fprintf (file, "%ld", (long)INTVAL (low)); | |
303 | break; | |
304 | } | |
6ce19398 | 305 | |
306 | default: | |
307 | abort (); | |
308 | } | |
309 | break; | |
310 | ||
311 | /* Similarly, but for the most significant word. */ | |
312 | case 'H': | |
313 | switch (GET_CODE (x)) | |
314 | { | |
315 | case MEM: | |
316 | fputc ('(', file); | |
eafc6604 | 317 | x = adjust_address (x, SImode, 4); |
6ce19398 | 318 | output_address (XEXP (x, 0)); |
319 | fputc (')', file); | |
320 | break; | |
321 | ||
322 | case REG: | |
323 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
324 | break; | |
325 | ||
326 | case SUBREG: | |
701e46d0 | 327 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
6ce19398 | 328 | break; |
329 | ||
330 | case CONST_DOUBLE: | |
331 | { | |
332 | long val[2]; | |
333 | REAL_VALUE_TYPE rv; | |
334 | ||
335 | switch (GET_MODE (x)) | |
336 | { | |
337 | case DFmode: | |
338 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
339 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 340 | fprintf (file, "0x%lx", val[1]); |
6ce19398 | 341 | break;; |
342 | case SFmode: | |
343 | abort (); | |
344 | case VOIDmode: | |
345 | case DImode: | |
346 | print_operand_address (file, | |
347 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
348 | break; | |
59086782 | 349 | default: |
350 | break; | |
6ce19398 | 351 | } |
352 | break; | |
353 | } | |
354 | ||
355 | case CONST_INT: | |
964d057c | 356 | { |
357 | rtx low, high; | |
358 | split_double (x, &low, &high); | |
359 | fprintf (file, "%ld", (long)INTVAL (high)); | |
360 | break; | |
361 | } | |
362 | ||
6ce19398 | 363 | default: |
364 | abort (); | |
365 | } | |
366 | break; | |
367 | ||
368 | case 'A': | |
369 | fputc ('(', file); | |
370 | if (GET_CODE (XEXP (x, 0)) == REG) | |
bcd9bd66 | 371 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx)); |
6ce19398 | 372 | else |
373 | output_address (XEXP (x, 0)); | |
374 | fputc (')', file); | |
375 | break; | |
376 | ||
167fa942 | 377 | case 'N': |
058f71f0 | 378 | if (INTVAL (x) < -128 || INTVAL (x) > 255) |
379 | abort (); | |
380 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); | |
381 | break; | |
382 | ||
383 | case 'U': | |
384 | if (INTVAL (x) < -128 || INTVAL (x) > 255) | |
385 | abort (); | |
386 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); | |
167fa942 | 387 | break; |
388 | ||
63e678f2 | 389 | /* For shift counts. The hardware ignores the upper bits of |
390 | any immediate, but the assembler will flag an out of range | |
391 | shift count as an error. So we mask off the high bits | |
392 | of the immediate here. */ | |
393 | case 'S': | |
394 | if (GET_CODE (x) == CONST_INT) | |
395 | { | |
058f71f0 | 396 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
63e678f2 | 397 | break; |
398 | } | |
399 | /* FALL THROUGH */ | |
400 | ||
29a404f9 | 401 | default: |
402 | switch (GET_CODE (x)) | |
403 | { | |
404 | case MEM: | |
405 | fputc ('(', file); | |
406 | output_address (XEXP (x, 0)); | |
407 | fputc (')', file); | |
408 | break; | |
409 | ||
6ce19398 | 410 | case PLUS: |
411 | output_address (x); | |
412 | break; | |
413 | ||
29a404f9 | 414 | case REG: |
415 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
416 | break; | |
417 | ||
418 | case SUBREG: | |
701e46d0 | 419 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
29a404f9 | 420 | break; |
421 | ||
6ce19398 | 422 | /* This will only be single precision.... */ |
423 | case CONST_DOUBLE: | |
424 | { | |
425 | unsigned long val; | |
426 | REAL_VALUE_TYPE rv; | |
427 | ||
428 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
429 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
ad3c0f03 | 430 | fprintf (file, "0x%lx", val); |
6ce19398 | 431 | break; |
432 | } | |
433 | ||
29a404f9 | 434 | case CONST_INT: |
435 | case SYMBOL_REF: | |
436 | case CONST: | |
437 | case LABEL_REF: | |
438 | case CODE_LABEL: | |
b87a151a | 439 | case UNSPEC: |
29a404f9 | 440 | print_operand_address (file, x); |
441 | break; | |
442 | default: | |
443 | abort (); | |
444 | } | |
445 | break; | |
446 | } | |
447 | } | |
448 | ||
449 | /* Output assembly language output for the address ADDR to FILE. */ | |
450 | ||
451 | void | |
3285410a | 452 | print_operand_address (FILE *file, rtx addr) |
29a404f9 | 453 | { |
454 | switch (GET_CODE (addr)) | |
455 | { | |
911517ac | 456 | case POST_INC: |
457 | print_operand_address (file, XEXP (addr, 0)); | |
458 | fputc ('+', file); | |
459 | break; | |
29a404f9 | 460 | case REG: |
49fd1b62 | 461 | print_operand (file, addr, 0); |
29a404f9 | 462 | break; |
463 | case PLUS: | |
464 | { | |
465 | rtx base, index; | |
466 | if (REG_P (XEXP (addr, 0)) | |
467 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
468 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
469 | else if (REG_P (XEXP (addr, 1)) | |
470 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
471 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
472 | else | |
473 | abort (); | |
474 | print_operand (file, index, 0); | |
475 | fputc (',', file); | |
476 | print_operand (file, base, 0);; | |
477 | break; | |
478 | } | |
479 | case SYMBOL_REF: | |
480 | output_addr_const (file, addr); | |
481 | break; | |
482 | default: | |
483 | output_addr_const (file, addr); | |
484 | break; | |
485 | } | |
486 | } | |
487 | ||
b166356e | 488 | /* Count the number of FP registers that have to be saved. */ |
489 | static int | |
3285410a | 490 | fp_regs_to_save (void) |
b166356e | 491 | { |
492 | int i, n = 0; | |
493 | ||
494 | if (! TARGET_AM33_2) | |
495 | return 0; | |
496 | ||
497 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
498 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
499 | ++n; | |
500 | ||
501 | return n; | |
502 | } | |
503 | ||
4caa3669 | 504 | /* Print a set of registers in the format required by "movm" and "ret". |
505 | Register K is saved if bit K of MASK is set. The data and address | |
506 | registers can be stored individually, but the extended registers cannot. | |
507 | We assume that the mask alread takes that into account. For instance, | |
09e5ce26 | 508 | bits 14 to 17 must have the same value. */ |
4caa3669 | 509 | |
510 | void | |
3285410a | 511 | mn10300_print_reg_list (FILE *file, int mask) |
4caa3669 | 512 | { |
513 | int need_comma; | |
514 | int i; | |
515 | ||
516 | need_comma = 0; | |
517 | fputc ('[', file); | |
518 | ||
519 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
520 | if ((mask & (1 << i)) != 0) | |
521 | { | |
522 | if (need_comma) | |
523 | fputc (',', file); | |
524 | fputs (reg_names [i], file); | |
525 | need_comma = 1; | |
526 | } | |
527 | ||
528 | if ((mask & 0x3c000) != 0) | |
529 | { | |
530 | if ((mask & 0x3c000) != 0x3c000) | |
531 | abort(); | |
532 | if (need_comma) | |
533 | fputc (',', file); | |
534 | fputs ("exreg1", file); | |
535 | need_comma = 1; | |
536 | } | |
537 | ||
538 | fputc (']', file); | |
539 | } | |
540 | ||
6ce19398 | 541 | int |
3285410a | 542 | can_use_return_insn (void) |
6ce19398 | 543 | { |
36ed4406 | 544 | /* size includes the fixed stack space needed for function calls. */ |
545 | int size = get_frame_size () + current_function_outgoing_args_size; | |
546 | ||
547 | /* And space for the return pointer. */ | |
548 | size += current_function_outgoing_args_size ? 4 : 0; | |
6ce19398 | 549 | |
550 | return (reload_completed | |
551 | && size == 0 | |
552 | && !regs_ever_live[2] | |
553 | && !regs_ever_live[3] | |
554 | && !regs_ever_live[6] | |
555 | && !regs_ever_live[7] | |
911517ac | 556 | && !regs_ever_live[14] |
557 | && !regs_ever_live[15] | |
558 | && !regs_ever_live[16] | |
559 | && !regs_ever_live[17] | |
b166356e | 560 | && fp_regs_to_save () == 0 |
6ce19398 | 561 | && !frame_pointer_needed); |
562 | } | |
563 | ||
4caa3669 | 564 | /* Returns the set of live, callee-saved registers as a bitmask. The |
565 | callee-saved extended registers cannot be stored individually, so | |
09e5ce26 | 566 | all of them will be included in the mask if any one of them is used. */ |
4caa3669 | 567 | |
568 | int | |
3285410a | 569 | mn10300_get_live_callee_saved_regs (void) |
4caa3669 | 570 | { |
571 | int mask; | |
572 | int i; | |
573 | ||
574 | mask = 0; | |
b166356e | 575 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
4caa3669 | 576 | if (regs_ever_live[i] && ! call_used_regs[i]) |
577 | mask |= (1 << i); | |
578 | if ((mask & 0x3c000) != 0) | |
579 | mask |= 0x3c000; | |
580 | ||
581 | return mask; | |
582 | } | |
583 | ||
584 | /* Generate an instruction that pushes several registers onto the stack. | |
585 | Register K will be saved if bit K in MASK is set. The function does | |
586 | nothing if MASK is zero. | |
587 | ||
588 | To be compatible with the "movm" instruction, the lowest-numbered | |
589 | register must be stored in the lowest slot. If MASK is the set | |
590 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
591 | instruction will have the form: | |
592 | ||
593 | (parallel | |
594 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
595 | (set (mem:SI (plus:SI (reg:SI 9) | |
596 | (const_int -1*4))) | |
597 | (reg:SI RN)) | |
598 | ... | |
599 | (set (mem:SI (plus:SI (reg:SI 9) | |
600 | (const_int -N*4))) | |
601 | (reg:SI R1))) */ | |
602 | ||
603 | void | |
3285410a | 604 | mn10300_gen_multiple_store (int mask) |
4caa3669 | 605 | { |
606 | if (mask != 0) | |
607 | { | |
608 | int i; | |
609 | int count; | |
610 | rtx par; | |
611 | int pari; | |
612 | ||
09e5ce26 | 613 | /* Count how many registers need to be saved. */ |
4caa3669 | 614 | count = 0; |
b166356e | 615 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
4caa3669 | 616 | if ((mask & (1 << i)) != 0) |
617 | count += 1; | |
618 | ||
619 | /* We need one PARALLEL element to update the stack pointer and | |
09e5ce26 | 620 | an additional element for each register that is stored. */ |
4caa3669 | 621 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
622 | ||
09e5ce26 | 623 | /* Create the instruction that updates the stack pointer. */ |
4caa3669 | 624 | XVECEXP (par, 0, 0) |
625 | = gen_rtx_SET (SImode, | |
626 | stack_pointer_rtx, | |
627 | gen_rtx_PLUS (SImode, | |
628 | stack_pointer_rtx, | |
629 | GEN_INT (-count * 4))); | |
630 | ||
09e5ce26 | 631 | /* Create each store. */ |
4caa3669 | 632 | pari = 1; |
b166356e | 633 | for (i = LAST_EXTENDED_REGNUM; i >= 0; i--) |
4caa3669 | 634 | if ((mask & (1 << i)) != 0) |
635 | { | |
636 | rtx address = gen_rtx_PLUS (SImode, | |
637 | stack_pointer_rtx, | |
638 | GEN_INT (-pari * 4)); | |
639 | XVECEXP(par, 0, pari) | |
640 | = gen_rtx_SET (VOIDmode, | |
641 | gen_rtx_MEM (SImode, address), | |
642 | gen_rtx_REG (SImode, i)); | |
643 | pari += 1; | |
644 | } | |
645 | ||
646 | par = emit_insn (par); | |
647 | RTX_FRAME_RELATED_P (par) = 1; | |
648 | } | |
649 | } | |
650 | ||
29a404f9 | 651 | void |
3285410a | 652 | expand_prologue (void) |
29a404f9 | 653 | { |
e3f95b40 | 654 | HOST_WIDE_INT size; |
f1899bff | 655 | |
f1899bff | 656 | /* SIZE includes the fixed stack space needed for function calls. */ |
36ed4406 | 657 | size = get_frame_size () + current_function_outgoing_args_size; |
658 | size += (current_function_outgoing_args_size ? 4 : 0); | |
29a404f9 | 659 | |
09e5ce26 | 660 | /* If we use any of the callee-saved registers, save them now. */ |
4caa3669 | 661 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); |
48cb86e3 | 662 | |
b166356e | 663 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
664 | { | |
665 | int num_regs_to_save = fp_regs_to_save (), i; | |
666 | HOST_WIDE_INT xsize; | |
667 | enum { save_sp_merge, | |
668 | save_sp_no_merge, | |
669 | save_sp_partial_merge, | |
670 | save_a0_merge, | |
671 | save_a0_no_merge } strategy; | |
672 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; | |
673 | rtx reg; | |
674 | rtx insn; | |
675 | ||
676 | /* We have several different strategies to save FP registers. | |
677 | We can store them using SP offsets, which is beneficial if | |
678 | there are just a few registers to save, or we can use `a0' in | |
679 | post-increment mode (`a0' is the only call-clobbered address | |
680 | register that is never used to pass information to a | |
681 | function). Furthermore, if we don't need a frame pointer, we | |
682 | can merge the two SP adds into a single one, but this isn't | |
683 | always beneficial; sometimes we can just split the two adds | |
684 | so that we don't exceed a 16-bit constant size. The code | |
685 | below will select which strategy to use, so as to generate | |
686 | smallest code. Ties are broken in favor or shorter sequences | |
687 | (in terms of number of instructions). */ | |
688 | ||
689 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
690 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
691 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
692 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
693 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ | |
694 | (((S) >= (L)) ? (SIZE1) * (N) \ | |
695 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ | |
696 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
697 | : (ELSE)) | |
698 | #define SIZE_FMOV_SP_(S,N) \ | |
699 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
700 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
701 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
702 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
703 | ||
704 | /* Consider alternative save_sp_merge only if we don't need the | |
fa483857 | 705 | frame pointer and size is nonzero. */ |
b166356e | 706 | if (! frame_pointer_needed && size) |
707 | { | |
708 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
709 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
710 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
711 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
712 | ||
713 | if (this_strategy_size < strategy_size) | |
714 | { | |
715 | strategy = save_sp_merge; | |
716 | strategy_size = this_strategy_size; | |
717 | } | |
718 | } | |
719 | ||
720 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
721 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
722 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
723 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
724 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
725 | if (size) | |
726 | { | |
727 | /* Insn: add -size, sp. */ | |
728 | this_strategy_size += SIZE_ADD_SP (-size); | |
729 | } | |
730 | ||
731 | if (this_strategy_size < strategy_size) | |
732 | { | |
733 | strategy = save_sp_no_merge; | |
734 | strategy_size = this_strategy_size; | |
735 | } | |
736 | ||
737 | /* Consider alternative save_sp_partial_merge only if we don't | |
738 | need a frame pointer and size is reasonably large. */ | |
739 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
740 | { | |
741 | /* Insn: add -128, sp. */ | |
742 | this_strategy_size = SIZE_ADD_SP (-128); | |
743 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
744 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
745 | num_regs_to_save); | |
746 | if (size) | |
747 | { | |
748 | /* Insn: add 128-size, sp. */ | |
749 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
750 | } | |
751 | ||
752 | if (this_strategy_size < strategy_size) | |
753 | { | |
754 | strategy = save_sp_partial_merge; | |
755 | strategy_size = this_strategy_size; | |
756 | } | |
757 | } | |
758 | ||
759 | /* Consider alternative save_a0_merge only if we don't need a | |
fa483857 | 760 | frame pointer, size is nonzero and the user hasn't |
b166356e | 761 | changed the calling conventions of a0. */ |
762 | if (! frame_pointer_needed && size | |
763 | && call_used_regs[FIRST_ADDRESS_REGNUM] | |
764 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) | |
765 | { | |
766 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
767 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
768 | /* Insn: mov sp, a0. */ | |
769 | this_strategy_size++; | |
770 | if (size) | |
771 | { | |
772 | /* Insn: add size, a0. */ | |
773 | this_strategy_size += SIZE_ADD_AX (size); | |
774 | } | |
775 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
776 | this_strategy_size += 3 * num_regs_to_save; | |
777 | ||
778 | if (this_strategy_size < strategy_size) | |
779 | { | |
780 | strategy = save_a0_merge; | |
781 | strategy_size = this_strategy_size; | |
782 | } | |
783 | } | |
784 | ||
785 | /* Consider alternative save_a0_no_merge if the user hasn't | |
09e5ce26 | 786 | changed the calling conventions of a0. */ |
b166356e | 787 | if (call_used_regs[FIRST_ADDRESS_REGNUM] |
788 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) | |
789 | { | |
790 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
791 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
792 | /* Insn: mov sp, a0. */ | |
793 | this_strategy_size++; | |
794 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
795 | this_strategy_size += 3 * num_regs_to_save; | |
796 | if (size) | |
797 | { | |
798 | /* Insn: add -size, sp. */ | |
799 | this_strategy_size += SIZE_ADD_SP (-size); | |
800 | } | |
801 | ||
802 | if (this_strategy_size < strategy_size) | |
803 | { | |
804 | strategy = save_a0_no_merge; | |
805 | strategy_size = this_strategy_size; | |
806 | } | |
807 | } | |
808 | ||
809 | /* Emit the initial SP add, common to all strategies. */ | |
810 | switch (strategy) | |
811 | { | |
812 | case save_sp_no_merge: | |
813 | case save_a0_no_merge: | |
814 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
815 | stack_pointer_rtx, | |
816 | GEN_INT (-4 * num_regs_to_save))); | |
817 | xsize = 0; | |
818 | break; | |
819 | ||
820 | case save_sp_partial_merge: | |
821 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
822 | stack_pointer_rtx, | |
823 | GEN_INT (-128))); | |
824 | xsize = 128 - 4 * num_regs_to_save; | |
825 | size -= xsize; | |
826 | break; | |
827 | ||
828 | case save_sp_merge: | |
829 | case save_a0_merge: | |
830 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
831 | stack_pointer_rtx, | |
832 | GEN_INT (-(size + 4 * num_regs_to_save)))); | |
833 | /* We'll have to adjust FP register saves according to the | |
09e5ce26 | 834 | frame size. */ |
b166356e | 835 | xsize = size; |
836 | /* Since we've already created the stack frame, don't do it | |
09e5ce26 | 837 | again at the end of the function. */ |
b166356e | 838 | size = 0; |
839 | break; | |
840 | ||
841 | default: | |
842 | abort (); | |
843 | } | |
844 | ||
845 | /* Now prepare register a0, if we have decided to use it. */ | |
846 | switch (strategy) | |
847 | { | |
848 | case save_sp_merge: | |
849 | case save_sp_no_merge: | |
850 | case save_sp_partial_merge: | |
851 | reg = 0; | |
852 | break; | |
853 | ||
854 | case save_a0_merge: | |
855 | case save_a0_no_merge: | |
856 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
857 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
858 | if (xsize) | |
859 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))); | |
860 | reg = gen_rtx_POST_INC (SImode, reg); | |
861 | break; | |
862 | ||
863 | default: | |
864 | abort (); | |
865 | } | |
866 | ||
867 | /* Now actually save the FP registers. */ | |
868 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
869 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
870 | { | |
871 | rtx addr; | |
872 | ||
873 | if (reg) | |
874 | addr = reg; | |
875 | else | |
876 | { | |
877 | /* If we aren't using `a0', use an SP offset. */ | |
878 | if (xsize) | |
879 | { | |
880 | addr = gen_rtx_PLUS (SImode, | |
881 | stack_pointer_rtx, | |
882 | GEN_INT (xsize)); | |
883 | } | |
884 | else | |
885 | addr = stack_pointer_rtx; | |
886 | ||
887 | xsize += 4; | |
888 | } | |
889 | ||
890 | insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr), | |
891 | gen_rtx_REG (SImode, i))); | |
892 | ||
893 | RTX_FRAME_RELATED_P (insn) = 1; | |
894 | } | |
895 | } | |
896 | ||
48cb86e3 | 897 | /* Now put the frame pointer into the frame pointer register. */ |
29a404f9 | 898 | if (frame_pointer_needed) |
014546df | 899 | emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); |
29a404f9 | 900 | |
48cb86e3 | 901 | /* Allocate stack for this frame. */ |
29a404f9 | 902 | if (size) |
903 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
904 | stack_pointer_rtx, | |
905 | GEN_INT (-size))); | |
b87a151a | 906 | if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) |
907 | { | |
908 | rtx insn = get_last_insn (); | |
909 | rtx last = emit_insn (gen_GOTaddr2picreg ()); | |
910 | ||
911 | /* Mark these insns as possibly dead. Sometimes, flow2 may | |
912 | delete all uses of the PIC register. In this case, let it | |
913 | delete the initialization too. */ | |
914 | do | |
915 | { | |
916 | insn = NEXT_INSN (insn); | |
917 | ||
918 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, | |
919 | const0_rtx, | |
920 | REG_NOTES (insn)); | |
921 | } | |
922 | while (insn != last); | |
923 | } | |
29a404f9 | 924 | } |
925 | ||
926 | void | |
3285410a | 927 | expand_epilogue (void) |
29a404f9 | 928 | { |
e3f95b40 | 929 | HOST_WIDE_INT size; |
f1899bff | 930 | |
f1899bff | 931 | /* SIZE includes the fixed stack space needed for function calls. */ |
36ed4406 | 932 | size = get_frame_size () + current_function_outgoing_args_size; |
933 | size += (current_function_outgoing_args_size ? 4 : 0); | |
29a404f9 | 934 | |
b166356e | 935 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
936 | { | |
937 | int num_regs_to_save = fp_regs_to_save (), i; | |
938 | rtx reg = 0; | |
939 | ||
940 | /* We have several options to restore FP registers. We could | |
941 | load them from SP offsets, but, if there are enough FP | |
942 | registers to restore, we win if we use a post-increment | |
943 | addressing mode. */ | |
944 | ||
945 | /* If we have a frame pointer, it's the best option, because we | |
946 | already know it has the value we want. */ | |
947 | if (frame_pointer_needed) | |
948 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
949 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
950 | it's never used for return values. But only do so if it's | |
951 | smaller than using SP offsets. */ | |
952 | else | |
953 | { | |
954 | enum { restore_sp_post_adjust, | |
955 | restore_sp_pre_adjust, | |
956 | restore_sp_partial_adjust, | |
957 | restore_a1 } strategy; | |
958 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
959 | ||
960 | /* Consider using sp offsets before adjusting sp. */ | |
961 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
962 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
963 | /* If size is too large, we'll have to adjust SP with an | |
964 | add. */ | |
965 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
966 | { | |
967 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
968 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
969 | } | |
970 | /* If we don't have to restore any non-FP registers, | |
971 | we'll be able to save one byte by using rets. */ | |
972 | if (! REG_SAVE_BYTES) | |
973 | this_strategy_size--; | |
974 | ||
975 | if (this_strategy_size < strategy_size) | |
976 | { | |
977 | strategy = restore_sp_post_adjust; | |
978 | strategy_size = this_strategy_size; | |
979 | } | |
980 | ||
981 | /* Consider using sp offsets after adjusting sp. */ | |
982 | /* Insn: add size, sp. */ | |
983 | this_strategy_size = SIZE_ADD_SP (size); | |
984 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
985 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
986 | /* We're going to use ret to release the FP registers | |
09e5ce26 | 987 | save area, so, no savings. */ |
b166356e | 988 | |
989 | if (this_strategy_size < strategy_size) | |
990 | { | |
991 | strategy = restore_sp_pre_adjust; | |
992 | strategy_size = this_strategy_size; | |
993 | } | |
994 | ||
995 | /* Consider using sp offsets after partially adjusting sp. | |
996 | When size is close to 32Kb, we may be able to adjust SP | |
997 | with an imm16 add instruction while still using fmov | |
998 | (d8,sp). */ | |
999 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1000 | { | |
1001 | /* Insn: add size + 4 * num_regs_to_save | |
1002 | + REG_SAVE_BYTES - 252,sp. */ | |
1003 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save | |
1004 | + REG_SAVE_BYTES - 252); | |
1005 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ | |
1006 | this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES | |
1007 | - 4 * num_regs_to_save, | |
1008 | num_regs_to_save); | |
1009 | /* We're going to use ret to release the FP registers | |
09e5ce26 | 1010 | save area, so, no savings. */ |
b166356e | 1011 | |
1012 | if (this_strategy_size < strategy_size) | |
1013 | { | |
1014 | strategy = restore_sp_partial_adjust; | |
1015 | strategy_size = this_strategy_size; | |
1016 | } | |
1017 | } | |
1018 | ||
1019 | /* Consider using a1 in post-increment mode, as long as the | |
1020 | user hasn't changed the calling conventions of a1. */ | |
1021 | if (call_used_regs[FIRST_ADDRESS_REGNUM+1] | |
1022 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) | |
1023 | { | |
1024 | /* Insn: mov sp,a1. */ | |
1025 | this_strategy_size = 1; | |
1026 | if (size) | |
1027 | { | |
1028 | /* Insn: add size,a1. */ | |
1029 | this_strategy_size += SIZE_ADD_AX (size); | |
1030 | } | |
1031 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1032 | this_strategy_size += 3 * num_regs_to_save; | |
1033 | /* If size is large enough, we may be able to save a | |
1034 | couple of bytes. */ | |
1035 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1036 | { | |
1037 | /* Insn: mov a1,sp. */ | |
1038 | this_strategy_size += 2; | |
1039 | } | |
1040 | /* If we don't have to restore any non-FP registers, | |
1041 | we'll be able to save one byte by using rets. */ | |
1042 | if (! REG_SAVE_BYTES) | |
1043 | this_strategy_size--; | |
1044 | ||
1045 | if (this_strategy_size < strategy_size) | |
1046 | { | |
1047 | strategy = restore_a1; | |
1048 | strategy_size = this_strategy_size; | |
1049 | } | |
1050 | } | |
1051 | ||
1052 | switch (strategy) | |
1053 | { | |
1054 | case restore_sp_post_adjust: | |
1055 | break; | |
1056 | ||
1057 | case restore_sp_pre_adjust: | |
1058 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1059 | stack_pointer_rtx, | |
1060 | GEN_INT (size))); | |
1061 | size = 0; | |
1062 | break; | |
1063 | ||
1064 | case restore_sp_partial_adjust: | |
1065 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1066 | stack_pointer_rtx, | |
1067 | GEN_INT (size + 4 * num_regs_to_save | |
1068 | + REG_SAVE_BYTES - 252))); | |
1069 | size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save; | |
1070 | break; | |
1071 | ||
1072 | case restore_a1: | |
1073 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1074 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1075 | if (size) | |
1076 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1077 | break; | |
1078 | ||
1079 | default: | |
1080 | abort (); | |
1081 | } | |
1082 | } | |
1083 | ||
1084 | /* Adjust the selected register, if any, for post-increment. */ | |
1085 | if (reg) | |
1086 | reg = gen_rtx_POST_INC (SImode, reg); | |
1087 | ||
1088 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
1089 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
1090 | { | |
1091 | rtx addr; | |
1092 | ||
1093 | if (reg) | |
1094 | addr = reg; | |
1095 | else if (size) | |
1096 | { | |
1097 | /* If we aren't using a post-increment register, use an | |
09e5ce26 | 1098 | SP offset. */ |
b166356e | 1099 | addr = gen_rtx_PLUS (SImode, |
1100 | stack_pointer_rtx, | |
1101 | GEN_INT (size)); | |
1102 | } | |
1103 | else | |
1104 | addr = stack_pointer_rtx; | |
1105 | ||
1106 | size += 4; | |
1107 | ||
1108 | emit_insn (gen_movsi (gen_rtx_REG (SImode, i), | |
1109 | gen_rtx_MEM (SImode, addr))); | |
1110 | } | |
1111 | ||
1112 | /* If we were using the restore_a1 strategy and the number of | |
1113 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1114 | to `sp', to avoid having to use `add' to adjust it. */ | |
1115 | if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255) | |
1116 | { | |
1117 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1118 | size = 0; | |
1119 | } | |
1120 | } | |
1121 | ||
461cabcc | 1122 | /* Maybe cut back the stack, except for the register save area. |
1123 | ||
1124 | If the frame pointer exists, then use the frame pointer to | |
1125 | cut back the stack. | |
1126 | ||
1127 | If the stack size + register save area is more than 255 bytes, | |
1128 | then the stack must be cut back here since the size + register | |
1129 | save size is too big for a ret/retf instruction. | |
1130 | ||
1131 | Else leave it alone, it will be cut back as part of the | |
1132 | ret/retf instruction, or there wasn't any stack to begin with. | |
1133 | ||
dfd1079d | 1134 | Under no circumstances should the register save area be |
461cabcc | 1135 | deallocated here, that would leave a window where an interrupt |
1136 | could occur and trash the register save area. */ | |
29a404f9 | 1137 | if (frame_pointer_needed) |
1138 | { | |
29a404f9 | 1139 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
b21218d6 | 1140 | size = 0; |
1141 | } | |
55daf463 | 1142 | else if (size + REG_SAVE_BYTES > 255) |
b21218d6 | 1143 | { |
1144 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1145 | stack_pointer_rtx, | |
1146 | GEN_INT (size))); | |
1147 | size = 0; | |
29a404f9 | 1148 | } |
29a404f9 | 1149 | |
55daf463 | 1150 | /* Adjust the stack and restore callee-saved registers, if any. */ |
1151 | if (size || regs_ever_live[2] || regs_ever_live[3] | |
48cb86e3 | 1152 | || regs_ever_live[6] || regs_ever_live[7] |
911517ac | 1153 | || regs_ever_live[14] || regs_ever_live[15] |
1154 | || regs_ever_live[16] || regs_ever_live[17] | |
48cb86e3 | 1155 | || frame_pointer_needed) |
55daf463 | 1156 | emit_jump_insn (gen_return_internal_regs |
1157 | (GEN_INT (size + REG_SAVE_BYTES))); | |
48cb86e3 | 1158 | else |
55daf463 | 1159 | emit_jump_insn (gen_return_internal ()); |
29a404f9 | 1160 | } |
1161 | ||
1162 | /* Update the condition code from the insn. */ | |
1163 | ||
1164 | void | |
3285410a | 1165 | notice_update_cc (rtx body, rtx insn) |
29a404f9 | 1166 | { |
29a404f9 | 1167 | switch (get_attr_cc (insn)) |
1168 | { | |
1169 | case CC_NONE: | |
1170 | /* Insn does not affect CC at all. */ | |
1171 | break; | |
1172 | ||
1173 | case CC_NONE_0HIT: | |
1174 | /* Insn does not change CC, but the 0'th operand has been changed. */ | |
1175 | if (cc_status.value1 != 0 | |
ed420a25 | 1176 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
29a404f9 | 1177 | cc_status.value1 = 0; |
1178 | break; | |
1179 | ||
14058057 | 1180 | case CC_SET_ZN: |
ed420a25 | 1181 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
14058057 | 1182 | V,C are unusable. */ |
29a404f9 | 1183 | CC_STATUS_INIT; |
14058057 | 1184 | cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; |
ed420a25 | 1185 | cc_status.value1 = recog_data.operand[0]; |
29a404f9 | 1186 | break; |
1187 | ||
14058057 | 1188 | case CC_SET_ZNV: |
ed420a25 | 1189 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
14058057 | 1190 | C is unusable. */ |
45e3d109 | 1191 | CC_STATUS_INIT; |
14058057 | 1192 | cc_status.flags |= CC_NO_CARRY; |
ed420a25 | 1193 | cc_status.value1 = recog_data.operand[0]; |
45e3d109 | 1194 | break; |
1195 | ||
29a404f9 | 1196 | case CC_COMPARE: |
1197 | /* The insn is a compare instruction. */ | |
1198 | CC_STATUS_INIT; | |
1199 | cc_status.value1 = SET_SRC (body); | |
b166356e | 1200 | if (GET_CODE (cc_status.value1) == COMPARE |
1201 | && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode) | |
1202 | cc_status.mdep.fpCC = 1; | |
29a404f9 | 1203 | break; |
1204 | ||
1205 | case CC_CLOBBER: | |
1206 | /* Insn doesn't leave CC in a usable state. */ | |
1207 | CC_STATUS_INIT; | |
1208 | break; | |
45e3d109 | 1209 | |
1210 | default: | |
1211 | abort (); | |
29a404f9 | 1212 | } |
29a404f9 | 1213 | } |
1214 | ||
a2f10574 | 1215 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
4caa3669 | 1216 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1217 | parallel. If OP is a multiple store, return a mask indicating which | |
1218 | registers it saves. Return 0 otherwise. */ | |
1219 | ||
1220 | int | |
3285410a | 1221 | store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
4caa3669 | 1222 | { |
1223 | int count; | |
1224 | int mask; | |
1225 | int i; | |
1226 | unsigned int last; | |
1227 | rtx elt; | |
1228 | ||
1229 | count = XVECLEN (op, 0); | |
1230 | if (count < 2) | |
1231 | return 0; | |
1232 | ||
1233 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1234 | elt = XVECEXP (op, 0, 0); | |
1235 | if (GET_CODE (elt) != SET | |
1236 | || GET_CODE (SET_DEST (elt)) != REG | |
1237 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM | |
1238 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1239 | return 0; | |
1240 | ||
1241 | /* Check that A is the stack pointer and B is the expected stack size. | |
1242 | For OP to match, each subsequent instruction should push a word onto | |
1243 | the stack. We therefore expect the first instruction to create | |
09e5ce26 | 1244 | COUNT-1 stack slots. */ |
4caa3669 | 1245 | elt = SET_SRC (elt); |
1246 | if (GET_CODE (XEXP (elt, 0)) != REG | |
1247 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1248 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1249 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) | |
1250 | return 0; | |
1251 | ||
1252 | /* Now go through the rest of the vector elements. They must be | |
1253 | ordered so that the first instruction stores the highest-numbered | |
1254 | register to the highest stack slot and that subsequent instructions | |
1255 | store a lower-numbered register to the slot below. | |
1256 | ||
1257 | LAST keeps track of the smallest-numbered register stored so far. | |
09e5ce26 | 1258 | MASK is the set of stored registers. */ |
b166356e | 1259 | last = LAST_EXTENDED_REGNUM + 1; |
4caa3669 | 1260 | mask = 0; |
1261 | for (i = 1; i < count; i++) | |
1262 | { | |
09e5ce26 | 1263 | /* Check that element i is a (set (mem M) R) and that R is valid. */ |
4caa3669 | 1264 | elt = XVECEXP (op, 0, i); |
1265 | if (GET_CODE (elt) != SET | |
1266 | || GET_CODE (SET_DEST (elt)) != MEM | |
1267 | || GET_CODE (SET_SRC (elt)) != REG | |
1268 | || REGNO (SET_SRC (elt)) >= last) | |
1269 | return 0; | |
1270 | ||
1271 | /* R was OK, so provisionally add it to MASK. We return 0 in any | |
09e5ce26 | 1272 | case if the rest of the instruction has a flaw. */ |
4caa3669 | 1273 | last = REGNO (SET_SRC (elt)); |
1274 | mask |= (1 << last); | |
1275 | ||
1276 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1277 | elt = XEXP (SET_DEST (elt), 0); | |
1278 | if (GET_CODE (elt) != PLUS | |
1279 | || GET_CODE (XEXP (elt, 0)) != REG | |
1280 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
1281 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
1282 | || INTVAL (XEXP (elt, 1)) != -i * 4) | |
1283 | return 0; | |
1284 | } | |
1285 | ||
09e5ce26 | 1286 | /* All or none of the callee-saved extended registers must be in the set. */ |
4caa3669 | 1287 | if ((mask & 0x3c000) != 0 |
1288 | && (mask & 0x3c000) != 0x3c000) | |
1289 | return 0; | |
1290 | ||
1291 | return mask; | |
1292 | } | |
1293 | ||
29a404f9 | 1294 | /* Return true if OP is a valid call operand. */ |
1295 | ||
1296 | int | |
3285410a | 1297 | call_address_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
29a404f9 | 1298 | { |
b87a151a | 1299 | if (flag_pic) |
1300 | return (EXTRA_CONSTRAINT (op, 'S') || GET_CODE (op) == REG); | |
1301 | ||
29a404f9 | 1302 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG); |
1303 | } | |
1304 | ||
1305 | /* What (if any) secondary registers are needed to move IN with mode | |
dc3d02df | 1306 | MODE into a register in register class CLASS. |
29a404f9 | 1307 | |
1308 | We might be able to simplify this. */ | |
1309 | enum reg_class | |
3285410a | 1310 | secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in) |
29a404f9 | 1311 | { |
29a404f9 | 1312 | /* Memory loads less than a full word wide can't have an |
1313 | address or stack pointer destination. They must use | |
1314 | a data register as an intermediate register. */ | |
79ea832f | 1315 | if ((GET_CODE (in) == MEM |
1316 | || (GET_CODE (in) == REG | |
1317 | && REGNO (in) >= FIRST_PSEUDO_REGISTER) | |
1318 | || (GET_CODE (in) == SUBREG | |
1319 | && GET_CODE (SUBREG_REG (in)) == REG | |
1320 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)) | |
29a404f9 | 1321 | && (mode == QImode || mode == HImode) |
79ea832f | 1322 | && (class == ADDRESS_REGS || class == SP_REGS |
b0ba03a6 | 1323 | || class == SP_OR_ADDRESS_REGS)) |
8ecf154e | 1324 | { |
911517ac | 1325 | if (TARGET_AM33) |
1326 | return DATA_OR_EXTENDED_REGS; | |
8ecf154e | 1327 | return DATA_REGS; |
1328 | } | |
29a404f9 | 1329 | |
1330 | /* We can't directly load sp + const_int into a data register; | |
1331 | we must use an address register as an intermediate. */ | |
48cb86e3 | 1332 | if (class != SP_REGS |
1333 | && class != ADDRESS_REGS | |
1334 | && class != SP_OR_ADDRESS_REGS | |
911517ac | 1335 | && class != SP_OR_EXTENDED_REGS |
1336 | && class != ADDRESS_OR_EXTENDED_REGS | |
1337 | && class != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
29a404f9 | 1338 | && (in == stack_pointer_rtx |
1339 | || (GET_CODE (in) == PLUS | |
48cb86e3 | 1340 | && (XEXP (in, 0) == stack_pointer_rtx |
1341 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
29a404f9 | 1342 | return ADDRESS_REGS; |
1343 | ||
19de5de1 | 1344 | if (GET_CODE (in) == PLUS |
1345 | && (XEXP (in, 0) == stack_pointer_rtx | |
1346 | || XEXP (in, 1) == stack_pointer_rtx)) | |
8ecf154e | 1347 | { |
911517ac | 1348 | if (TARGET_AM33) |
1349 | return DATA_OR_EXTENDED_REGS; | |
8ecf154e | 1350 | return DATA_REGS; |
1351 | } | |
19de5de1 | 1352 | |
b166356e | 1353 | if (TARGET_AM33_2 && class == FP_REGS |
1354 | && GET_CODE (in) == MEM && ! OK_FOR_Q (in)) | |
1355 | { | |
1356 | if (TARGET_AM33) | |
1357 | return DATA_OR_EXTENDED_REGS; | |
1358 | return DATA_REGS; | |
1359 | } | |
1360 | ||
48cb86e3 | 1361 | /* Otherwise assume no secondary reloads are needed. */ |
1362 | return NO_REGS; | |
1363 | } | |
1364 | ||
1365 | int | |
3285410a | 1366 | initial_offset (int from, int to) |
48cb86e3 | 1367 | { |
f1899bff | 1368 | /* The difference between the argument pointer and the frame pointer |
1369 | is the size of the callee register save area. */ | |
48cb86e3 | 1370 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
29a404f9 | 1371 | { |
48cb86e3 | 1372 | if (regs_ever_live[2] || regs_ever_live[3] |
1373 | || regs_ever_live[6] || regs_ever_live[7] | |
911517ac | 1374 | || regs_ever_live[14] || regs_ever_live[15] |
1375 | || regs_ever_live[16] || regs_ever_live[17] | |
b166356e | 1376 | || fp_regs_to_save () |
48cb86e3 | 1377 | || frame_pointer_needed) |
b166356e | 1378 | return REG_SAVE_BYTES |
1379 | + 4 * fp_regs_to_save (); | |
48cb86e3 | 1380 | else |
bb4959a8 | 1381 | return 0; |
29a404f9 | 1382 | } |
1383 | ||
f1899bff | 1384 | /* The difference between the argument pointer and the stack pointer is |
1385 | the sum of the size of this function's frame, the callee register save | |
1386 | area, and the fixed stack space needed for function calls (if any). */ | |
48cb86e3 | 1387 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
1388 | { | |
1389 | if (regs_ever_live[2] || regs_ever_live[3] | |
1390 | || regs_ever_live[6] || regs_ever_live[7] | |
911517ac | 1391 | || regs_ever_live[14] || regs_ever_live[15] |
1392 | || regs_ever_live[16] || regs_ever_live[17] | |
b166356e | 1393 | || fp_regs_to_save () |
48cb86e3 | 1394 | || frame_pointer_needed) |
8ecf154e | 1395 | return (get_frame_size () + REG_SAVE_BYTES |
b166356e | 1396 | + 4 * fp_regs_to_save () |
36ed4406 | 1397 | + (current_function_outgoing_args_size |
1398 | ? current_function_outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1399 | else |
36ed4406 | 1400 | return (get_frame_size () |
1401 | + (current_function_outgoing_args_size | |
1402 | ? current_function_outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1403 | } |
29a404f9 | 1404 | |
f1899bff | 1405 | /* The difference between the frame pointer and stack pointer is the sum |
1406 | of the size of this function's frame and the fixed stack space needed | |
1407 | for function calls (if any). */ | |
48cb86e3 | 1408 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
36ed4406 | 1409 | return (get_frame_size () |
1410 | + (current_function_outgoing_args_size | |
1411 | ? current_function_outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1412 | |
1413 | abort (); | |
29a404f9 | 1414 | } |
bb4959a8 | 1415 | |
6644435d | 1416 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
1417 | ||
f2d49d02 | 1418 | static bool |
1419 | mn10300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
1420 | { | |
1421 | /* Return values > 8 bytes in length in memory. */ | |
1422 | return int_size_in_bytes (type) > 8 || TYPE_MODE (type) == BLKmode; | |
1423 | } | |
1424 | ||
bb4959a8 | 1425 | /* Flush the argument registers to the stack for a stdarg function; |
1426 | return the new argument pointer. */ | |
f2d49d02 | 1427 | static rtx |
3285410a | 1428 | mn10300_builtin_saveregs (void) |
bb4959a8 | 1429 | { |
ed554036 | 1430 | rtx offset, mem; |
bb4959a8 | 1431 | tree fntype = TREE_TYPE (current_function_decl); |
1432 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
1433 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
1434 | != void_type_node))) | |
1435 | ? UNITS_PER_WORD : 0); | |
ed554036 | 1436 | int set = get_varargs_alias_set (); |
bb4959a8 | 1437 | |
1438 | if (argadj) | |
1439 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
1440 | else | |
1441 | offset = current_function_arg_offset_rtx; | |
1442 | ||
ed554036 | 1443 | mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer); |
ab6ab77e | 1444 | set_mem_alias_set (mem, set); |
ed554036 | 1445 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1446 | ||
1447 | mem = gen_rtx_MEM (SImode, | |
1448 | plus_constant (current_function_internal_arg_pointer, 4)); | |
ab6ab77e | 1449 | set_mem_alias_set (mem, set); |
ed554036 | 1450 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1451 | ||
bb4959a8 | 1452 | return copy_to_reg (expand_binop (Pmode, add_optab, |
1453 | current_function_internal_arg_pointer, | |
1454 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
1455 | } | |
1456 | ||
ed554036 | 1457 | void |
3285410a | 1458 | mn10300_va_start (tree valist, rtx nextarg) |
ed554036 | 1459 | { |
7ccc713a | 1460 | nextarg = expand_builtin_saveregs (); |
7df226a2 | 1461 | std_expand_builtin_va_start (valist, nextarg); |
ed554036 | 1462 | } |
1463 | ||
b981d932 | 1464 | /* Return true when a parameter should be passed by reference. */ |
1465 | ||
1466 | static bool | |
1467 | mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
1468 | enum machine_mode mode, tree type, | |
1469 | bool named ATTRIBUTE_UNUSED) | |
1470 | { | |
1471 | unsigned HOST_WIDE_INT size; | |
1472 | ||
1473 | if (type) | |
1474 | size = int_size_in_bytes (type); | |
1475 | else | |
1476 | size = GET_MODE_SIZE (mode); | |
1477 | ||
1478 | return size > 8; | |
1479 | } | |
1480 | ||
bb4959a8 | 1481 | /* Return an RTX to represent where a value with mode MODE will be returned |
1482 | from a function. If the result is 0, the argument is pushed. */ | |
1483 | ||
1484 | rtx | |
3285410a | 1485 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
1486 | tree type, int named ATTRIBUTE_UNUSED) | |
bb4959a8 | 1487 | { |
1488 | rtx result = 0; | |
1489 | int size, align; | |
1490 | ||
1491 | /* We only support using 2 data registers as argument registers. */ | |
1492 | int nregs = 2; | |
1493 | ||
1494 | /* Figure out the size of the object to be passed. */ | |
1495 | if (mode == BLKmode) | |
1496 | size = int_size_in_bytes (type); | |
1497 | else | |
1498 | size = GET_MODE_SIZE (mode); | |
1499 | ||
1500 | /* Figure out the alignment of the object to be passed. */ | |
1501 | align = size; | |
1502 | ||
1503 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1504 | ||
1505 | /* Don't pass this arg via a register if all the argument registers | |
1506 | are used up. */ | |
1507 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1508 | return 0; | |
1509 | ||
1510 | /* Don't pass this arg via a register if it would be split between | |
1511 | registers and memory. */ | |
1512 | if (type == NULL_TREE | |
1513 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1514 | return 0; | |
1515 | ||
1516 | switch (cum->nbytes / UNITS_PER_WORD) | |
1517 | { | |
1518 | case 0: | |
7014838c | 1519 | result = gen_rtx_REG (mode, 0); |
bb4959a8 | 1520 | break; |
1521 | case 1: | |
7014838c | 1522 | result = gen_rtx_REG (mode, 1); |
bb4959a8 | 1523 | break; |
1524 | default: | |
1525 | result = 0; | |
1526 | } | |
1527 | ||
1528 | return result; | |
1529 | } | |
1530 | ||
1531 | /* Return the number of registers to use for an argument passed partially | |
1532 | in registers and partially in memory. */ | |
1533 | ||
1534 | int | |
3285410a | 1535 | function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
1536 | tree type, int named ATTRIBUTE_UNUSED) | |
bb4959a8 | 1537 | { |
1538 | int size, align; | |
1539 | ||
1540 | /* We only support using 2 data registers as argument registers. */ | |
1541 | int nregs = 2; | |
1542 | ||
1543 | /* Figure out the size of the object to be passed. */ | |
1544 | if (mode == BLKmode) | |
1545 | size = int_size_in_bytes (type); | |
1546 | else | |
1547 | size = GET_MODE_SIZE (mode); | |
1548 | ||
1549 | /* Figure out the alignment of the object to be passed. */ | |
1550 | align = size; | |
1551 | ||
1552 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1553 | ||
1554 | /* Don't pass this arg via a register if all the argument registers | |
1555 | are used up. */ | |
1556 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1557 | return 0; | |
1558 | ||
1559 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1560 | return 0; | |
1561 | ||
1562 | /* Don't pass this arg via a register if it would be split between | |
1563 | registers and memory. */ | |
1564 | if (type == NULL_TREE | |
1565 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1566 | return 0; | |
1567 | ||
1568 | return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD; | |
1569 | } | |
1570 | ||
1571 | /* Output a tst insn. */ | |
feb9af9f | 1572 | const char * |
3285410a | 1573 | output_tst (rtx operand, rtx insn) |
bb4959a8 | 1574 | { |
bb4959a8 | 1575 | rtx temp; |
1576 | int past_call = 0; | |
1577 | ||
1578 | /* We can save a byte if we can find a register which has the value | |
1579 | zero in it. */ | |
1580 | temp = PREV_INSN (insn); | |
6e90c6cd | 1581 | while (optimize && temp) |
bb4959a8 | 1582 | { |
1583 | rtx set; | |
1584 | ||
1585 | /* We allow the search to go through call insns. We record | |
1586 | the fact that we've past a CALL_INSN and reject matches which | |
1587 | use call clobbered registers. */ | |
1588 | if (GET_CODE (temp) == CODE_LABEL | |
1589 | || GET_CODE (temp) == JUMP_INSN | |
1590 | || GET_CODE (temp) == BARRIER) | |
1591 | break; | |
1592 | ||
1593 | if (GET_CODE (temp) == CALL_INSN) | |
1594 | past_call = 1; | |
1595 | ||
1596 | if (GET_CODE (temp) == NOTE) | |
1597 | { | |
1598 | temp = PREV_INSN (temp); | |
1599 | continue; | |
1600 | } | |
1601 | ||
09e5ce26 | 1602 | /* It must be an insn, see if it is a simple set. */ |
bb4959a8 | 1603 | set = single_set (temp); |
1604 | if (!set) | |
1605 | { | |
1606 | temp = PREV_INSN (temp); | |
1607 | continue; | |
1608 | } | |
1609 | ||
1610 | /* Are we setting a data register to zero (this does not win for | |
1611 | address registers)? | |
1612 | ||
1613 | If it's a call clobbered register, have we past a call? | |
1614 | ||
1615 | Make sure the register we find isn't the same as ourself; | |
8ecf154e | 1616 | the mn10300 can't encode that. |
1617 | ||
1618 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1619 | so the code to detect calls here isn't doing anything useful. */ | |
bb4959a8 | 1620 | if (REG_P (SET_DEST (set)) |
1621 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1622 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
6e90c6cd | 1623 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1624 | == REGNO_REG_CLASS (REGNO (operand))) | |
911517ac | 1625 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1626 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
1627 | && (!past_call | |
1628 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1629 | { | |
1630 | rtx xoperands[2]; | |
1631 | xoperands[0] = operand; | |
1632 | xoperands[1] = SET_DEST (set); | |
1633 | ||
1634 | output_asm_insn ("cmp %1,%0", xoperands); | |
1635 | return ""; | |
1636 | } | |
1637 | ||
1638 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1639 | && REG_P (SET_DEST (set)) | |
1640 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1641 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1642 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1643 | != REGNO_REG_CLASS (REGNO (operand))) | |
1644 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
bb4959a8 | 1645 | && REGNO (SET_DEST (set)) != REGNO (operand) |
1646 | && (!past_call | |
1647 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1648 | { | |
1649 | rtx xoperands[2]; | |
1650 | xoperands[0] = operand; | |
1651 | xoperands[1] = SET_DEST (set); | |
1652 | ||
1653 | output_asm_insn ("cmp %1,%0", xoperands); | |
1654 | return ""; | |
1655 | } | |
1656 | temp = PREV_INSN (temp); | |
1657 | } | |
1658 | return "cmp 0,%0"; | |
1659 | } | |
36ed4406 | 1660 | |
1661 | int | |
3285410a | 1662 | impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
36ed4406 | 1663 | { |
36ed4406 | 1664 | if (GET_CODE (op) != PLUS) |
1665 | return 0; | |
1666 | ||
19de5de1 | 1667 | if (XEXP (op, 0) == stack_pointer_rtx |
1668 | || XEXP (op, 1) == stack_pointer_rtx) | |
36ed4406 | 1669 | return 1; |
1670 | ||
36ed4406 | 1671 | return 0; |
1672 | } | |
c4cd8f6a | 1673 | |
9d3b5b5e | 1674 | /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used |
1675 | for the btst insn which may examine memory or a register (the memory | |
1676 | variant only allows an unsigned 8 bit integer). */ | |
1677 | int | |
3285410a | 1678 | const_8bit_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
9d3b5b5e | 1679 | { |
1680 | return (GET_CODE (op) == CONST_INT | |
1681 | && INTVAL (op) >= 0 | |
1682 | && INTVAL (op) < 256); | |
1683 | } | |
1684 | ||
b166356e | 1685 | /* Return true if the operand is the 1.0f constant. */ |
1686 | int | |
3285410a | 1687 | const_1f_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
b166356e | 1688 | { |
1689 | return (op == CONST1_RTX (SFmode)); | |
1690 | } | |
1691 | ||
9d3b5b5e | 1692 | /* Similarly, but when using a zero_extract pattern for a btst where |
1693 | the source operand might end up in memory. */ | |
1694 | int | |
3285410a | 1695 | mask_ok_for_mem_btst (int len, int bit) |
9d3b5b5e | 1696 | { |
805e22b2 | 1697 | unsigned int mask = 0; |
9d3b5b5e | 1698 | |
1699 | while (len > 0) | |
1700 | { | |
1701 | mask |= (1 << bit); | |
1702 | bit++; | |
1703 | len--; | |
1704 | } | |
1705 | ||
1706 | /* MASK must bit into an 8bit value. */ | |
1707 | return (((mask & 0xff) == mask) | |
1708 | || ((mask & 0xff00) == mask) | |
1709 | || ((mask & 0xff0000) == mask) | |
1710 | || ((mask & 0xff000000) == mask)); | |
1711 | } | |
1712 | ||
c4cd8f6a | 1713 | /* Return 1 if X contains a symbolic expression. We know these |
1714 | expressions will have one of a few well defined forms, so | |
1715 | we need only check those forms. */ | |
1716 | int | |
3285410a | 1717 | symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
c4cd8f6a | 1718 | { |
1719 | switch (GET_CODE (op)) | |
1720 | { | |
1721 | case SYMBOL_REF: | |
1722 | case LABEL_REF: | |
1723 | return 1; | |
1724 | case CONST: | |
1725 | op = XEXP (op, 0); | |
1726 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1727 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
1728 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
1729 | default: | |
1730 | return 0; | |
1731 | } | |
1732 | } | |
1733 | ||
1734 | /* Try machine dependent ways of modifying an illegitimate address | |
1735 | to be legitimate. If we find one, return the new valid address. | |
1736 | This macro is used in only one place: `memory_address' in explow.c. | |
1737 | ||
1738 | OLDX is the address as it was before break_out_memory_refs was called. | |
1739 | In some cases it is useful to look at this to decide what needs to be done. | |
1740 | ||
1741 | MODE and WIN are passed so that this macro can use | |
1742 | GO_IF_LEGITIMATE_ADDRESS. | |
1743 | ||
1744 | Normally it is always safe for this macro to do nothing. It exists to | |
1745 | recognize opportunities to optimize the output. | |
1746 | ||
1747 | But on a few ports with segmented architectures and indexed addressing | |
1748 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
1749 | rtx | |
3285410a | 1750 | legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1751 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
c4cd8f6a | 1752 | { |
b87a151a | 1753 | if (flag_pic && ! legitimate_pic_operand_p (x)) |
1754 | x = legitimize_pic_address (oldx, NULL_RTX); | |
1755 | ||
c4cd8f6a | 1756 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1757 | special handling to avoid creating an indexed memory address | |
1758 | with x-100000 as the base. */ | |
1759 | if (GET_CODE (x) == PLUS | |
1760 | && symbolic_operand (XEXP (x, 1), VOIDmode)) | |
1761 | { | |
1762 | /* Ugly. We modify things here so that the address offset specified | |
1763 | by the index expression is computed first, then added to x to form | |
1764 | the entire address. */ | |
1765 | ||
59086782 | 1766 | rtx regx1, regy1, regy2, y; |
c4cd8f6a | 1767 | |
1768 | /* Strip off any CONST. */ | |
1769 | y = XEXP (x, 1); | |
1770 | if (GET_CODE (y) == CONST) | |
1771 | y = XEXP (y, 0); | |
1772 | ||
c927a8ab | 1773 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1774 | { | |
1775 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1776 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1777 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1778 | regx1 = force_reg (Pmode, | |
29bb088d | 1779 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, regy2)); |
7014838c | 1780 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
c927a8ab | 1781 | } |
c4cd8f6a | 1782 | } |
11b4605c | 1783 | return x; |
c4cd8f6a | 1784 | } |
e2aead91 | 1785 | |
b87a151a | 1786 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
09e5ce26 | 1787 | @GOTOFF in `reg'. */ |
b87a151a | 1788 | rtx |
3285410a | 1789 | legitimize_pic_address (rtx orig, rtx reg) |
b87a151a | 1790 | { |
1791 | if (GET_CODE (orig) == LABEL_REF | |
1792 | || (GET_CODE (orig) == SYMBOL_REF | |
1793 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1794 | || ! MN10300_GLOBAL_P (orig)))) | |
1795 | { | |
1796 | if (reg == 0) | |
1797 | reg = gen_reg_rtx (Pmode); | |
1798 | ||
1799 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
1800 | return reg; | |
1801 | } | |
1802 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1803 | { | |
1804 | if (reg == 0) | |
1805 | reg = gen_reg_rtx (Pmode); | |
1806 | ||
1807 | emit_insn (gen_symGOT2reg (reg, orig)); | |
1808 | return reg; | |
1809 | } | |
1810 | return orig; | |
1811 | } | |
1812 | ||
1813 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
fa483857 | 1814 | isn't protected by a PIC unspec; nonzero otherwise. */ |
b87a151a | 1815 | int |
3285410a | 1816 | legitimate_pic_operand_p (rtx x) |
b87a151a | 1817 | { |
1818 | register const char *fmt; | |
1819 | register int i; | |
1820 | ||
1821 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1822 | return 0; | |
1823 | ||
1824 | if (GET_CODE (x) == UNSPEC | |
1825 | && (XINT (x, 1) == UNSPEC_PIC | |
1826 | || XINT (x, 1) == UNSPEC_GOT | |
1827 | || XINT (x, 1) == UNSPEC_GOTOFF | |
1828 | || XINT (x, 1) == UNSPEC_PLT)) | |
1829 | return 1; | |
1830 | ||
b87a151a | 1831 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
1832 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1833 | { | |
1834 | if (fmt[i] == 'E') | |
1835 | { | |
1836 | register int j; | |
1837 | ||
1838 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
1839 | if (! legitimate_pic_operand_p (XVECEXP (x, i, j))) | |
1840 | return 0; | |
1841 | } | |
1842 | else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i))) | |
1843 | return 0; | |
1844 | } | |
1845 | ||
1846 | return 1; | |
1847 | } | |
1848 | ||
5411aa8c | 1849 | /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is |
1850 | legitimate, and FALSE otherwise. */ | |
1851 | bool | |
1852 | legitimate_address_p (enum machine_mode mode, rtx x, int strict) | |
1853 | { | |
1854 | if (CONSTANT_ADDRESS_P (x) | |
1855 | && (! flag_pic || legitimate_pic_operand_p (x))) | |
1856 | return TRUE; | |
1857 | ||
1858 | if (RTX_OK_FOR_BASE_P (x, strict)) | |
1859 | return TRUE; | |
1860 | ||
1861 | if (TARGET_AM33 | |
1862 | && GET_CODE (x) == POST_INC | |
1863 | && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict) | |
1864 | && (mode == SImode || mode == SFmode || mode == HImode)) | |
1865 | return TRUE; | |
1866 | ||
1867 | if (GET_CODE (x) == PLUS) | |
1868 | { | |
1869 | rtx base = 0, index = 0; | |
1870 | ||
1871 | if (REG_P (XEXP (x, 0)) | |
1872 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict)) | |
1873 | { | |
1874 | base = XEXP (x, 0); | |
1875 | index = XEXP (x, 1); | |
1876 | } | |
1877 | ||
1878 | if (REG_P (XEXP (x, 1)) | |
1879 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict)) | |
1880 | { | |
1881 | base = XEXP (x, 1); | |
1882 | index = XEXP (x, 0); | |
1883 | } | |
1884 | ||
1885 | if (base != 0 && index != 0) | |
1886 | { | |
1887 | if (GET_CODE (index) == CONST_INT) | |
1888 | return TRUE; | |
1889 | if (GET_CODE (index) == CONST | |
9247cc1c | 1890 | && GET_CODE (XEXP (index, 0)) != PLUS |
5411aa8c | 1891 | && (! flag_pic |
1892 | || legitimate_pic_operand_p (index))) | |
1893 | return TRUE; | |
1894 | } | |
1895 | } | |
1896 | ||
1897 | return FALSE; | |
1898 | } | |
1899 | ||
ec0457a8 | 1900 | static int |
3285410a | 1901 | mn10300_address_cost_1 (rtx x, int *unsig) |
e2aead91 | 1902 | { |
e2aead91 | 1903 | switch (GET_CODE (x)) |
1904 | { | |
1905 | case REG: | |
1906 | switch (REGNO_REG_CLASS (REGNO (x))) | |
1907 | { | |
1908 | case SP_REGS: | |
1909 | *unsig = 1; | |
1910 | return 0; | |
1911 | ||
1912 | case ADDRESS_REGS: | |
1913 | return 1; | |
1914 | ||
1915 | case DATA_REGS: | |
1916 | case EXTENDED_REGS: | |
b166356e | 1917 | case FP_REGS: |
e2aead91 | 1918 | return 3; |
1919 | ||
1920 | case NO_REGS: | |
1921 | return 5; | |
1922 | ||
1923 | default: | |
1924 | abort (); | |
1925 | } | |
1926 | ||
1927 | case PLUS: | |
1928 | case MINUS: | |
cbe23f2f | 1929 | case ASHIFT: |
1930 | case AND: | |
e2aead91 | 1931 | case IOR: |
ec0457a8 | 1932 | return (mn10300_address_cost_1 (XEXP (x, 0), unsig) |
1933 | + mn10300_address_cost_1 (XEXP (x, 1), unsig)); | |
e2aead91 | 1934 | |
1935 | case EXPR_LIST: | |
1936 | case SUBREG: | |
1937 | case MEM: | |
ec0457a8 | 1938 | return mn10300_address_cost (XEXP (x, 0)); |
e2aead91 | 1939 | |
1940 | case ZERO_EXTEND: | |
1941 | *unsig = 1; | |
ec0457a8 | 1942 | return mn10300_address_cost_1 (XEXP (x, 0), unsig); |
e2aead91 | 1943 | |
1944 | case CONST_INT: | |
1945 | if (INTVAL (x) == 0) | |
1946 | return 0; | |
1947 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
1948 | return 1; | |
1949 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
1950 | return 3; | |
1951 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
1952 | return 5; | |
1953 | return 7; | |
1954 | ||
1955 | case CONST: | |
1956 | case SYMBOL_REF: | |
cbe23f2f | 1957 | case LABEL_REF: |
e2aead91 | 1958 | return 8; |
1959 | ||
e2aead91 | 1960 | default: |
1961 | abort (); | |
1962 | ||
1963 | } | |
1964 | } | |
fab7adbf | 1965 | |
ec0457a8 | 1966 | static int |
3285410a | 1967 | mn10300_address_cost (rtx x) |
ec0457a8 | 1968 | { |
1969 | int s = 0; | |
1970 | return mn10300_address_cost_1 (x, &s); | |
1971 | } | |
1972 | ||
fab7adbf | 1973 | static bool |
3285410a | 1974 | mn10300_rtx_costs (rtx x, int code, int outer_code, int *total) |
fab7adbf | 1975 | { |
1976 | switch (code) | |
1977 | { | |
1978 | case CONST_INT: | |
1979 | /* Zeros are extremely cheap. */ | |
1980 | if (INTVAL (x) == 0 && outer_code == SET) | |
1981 | *total = 0; | |
1982 | /* If it fits in 8 bits, then it's still relatively cheap. */ | |
1983 | else if (INT_8_BITS (INTVAL (x))) | |
1984 | *total = 1; | |
1985 | /* This is the "base" cost, includes constants where either the | |
1986 | upper or lower 16bits are all zeros. */ | |
1987 | else if (INT_16_BITS (INTVAL (x)) | |
1988 | || (INTVAL (x) & 0xffff) == 0 | |
1989 | || (INTVAL (x) & 0xffff0000) == 0) | |
1990 | *total = 2; | |
1991 | else | |
1992 | *total = 4; | |
1993 | return true; | |
1994 | ||
1995 | case CONST: | |
1996 | case LABEL_REF: | |
1997 | case SYMBOL_REF: | |
1998 | /* These are more costly than a CONST_INT, but we can relax them, | |
1999 | so they're less costly than a CONST_DOUBLE. */ | |
2000 | *total = 6; | |
2001 | return true; | |
2002 | ||
2003 | case CONST_DOUBLE: | |
2004 | /* We don't optimize CONST_DOUBLEs well nor do we relax them well, | |
2005 | so their cost is very high. */ | |
2006 | *total = 8; | |
2007 | return true; | |
2008 | ||
2009 | /* ??? This probably needs more work. */ | |
2010 | case MOD: | |
2011 | case DIV: | |
2012 | case MULT: | |
2013 | *total = 8; | |
2014 | return true; | |
2015 | ||
2016 | default: | |
2017 | return false; | |
2018 | } | |
2019 | } | |
8935d57c | 2020 | |
2021 | /* Check whether a constant used to initialize a DImode or DFmode can | |
2022 | use a clr instruction. The code here must be kept in sync with | |
2023 | movdf and movdi. */ | |
2024 | ||
2025 | bool | |
3285410a | 2026 | mn10300_wide_const_load_uses_clr (rtx operands[2]) |
8935d57c | 2027 | { |
2028 | long val[2]; | |
2029 | ||
2030 | if (GET_CODE (operands[0]) != REG | |
2031 | || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS) | |
2032 | return false; | |
2033 | ||
2034 | switch (GET_CODE (operands[1])) | |
2035 | { | |
2036 | case CONST_INT: | |
2037 | { | |
2038 | rtx low, high; | |
2039 | split_double (operands[1], &low, &high); | |
2040 | val[0] = INTVAL (low); | |
2041 | val[1] = INTVAL (high); | |
2042 | } | |
2043 | break; | |
2044 | ||
2045 | case CONST_DOUBLE: | |
2046 | if (GET_MODE (operands[1]) == DFmode) | |
2047 | { | |
2048 | REAL_VALUE_TYPE rv; | |
2049 | ||
2050 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
2051 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
2052 | } | |
2053 | else if (GET_MODE (operands[1]) == VOIDmode | |
2054 | || GET_MODE (operands[1]) == DImode) | |
2055 | { | |
2056 | val[0] = CONST_DOUBLE_LOW (operands[1]); | |
2057 | val[1] = CONST_DOUBLE_HIGH (operands[1]); | |
2058 | } | |
2059 | break; | |
2060 | ||
2061 | default: | |
2062 | return false; | |
2063 | } | |
2064 | ||
2065 | return val[0] == 0 || val[1] == 0; | |
2066 | } | |
b87a151a | 2067 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2068 | may access it using GOTOFF instead of GOT. */ | |
2069 | ||
2070 | static void | |
48ed5fc2 | 2071 | mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED) |
b87a151a | 2072 | { |
2073 | rtx symbol; | |
2074 | ||
2075 | if (GET_CODE (rtl) != MEM) | |
2076 | return; | |
2077 | symbol = XEXP (rtl, 0); | |
2078 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2079 | return; | |
2080 | ||
2081 | if (flag_pic) | |
2082 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2083 | } |