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11bb1f11 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
6fb5fa3c | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, |
c75c517d | 3 | 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. |
11bb1f11 JL |
4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
e7ab5593 | 6 | This file is part of GCC. |
11bb1f11 | 7 | |
e7ab5593 NC |
8 | GCC is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
11bb1f11 | 12 | |
e7ab5593 NC |
13 | GCC is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
11bb1f11 | 17 | |
e7ab5593 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
11bb1f11 | 21 | |
11bb1f11 | 22 | #include "config.h" |
c5c76735 | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
11bb1f11 | 26 | #include "rtl.h" |
bf6bb899 | 27 | #include "tree.h" |
11bb1f11 JL |
28 | #include "regs.h" |
29 | #include "hard-reg-set.h" | |
11bb1f11 JL |
30 | #include "insn-config.h" |
31 | #include "conditions.h" | |
11bb1f11 JL |
32 | #include "output.h" |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
6528281d | 36 | #include "reload.h" |
11bb1f11 | 37 | #include "expr.h" |
e78d8e51 | 38 | #include "optabs.h" |
bf6bb899 | 39 | #include "function.h" |
11bb1f11 | 40 | #include "obstack.h" |
718f9c0f | 41 | #include "diagnostic-core.h" |
69bc71fa | 42 | #include "tm_p.h" |
672a6f42 NB |
43 | #include "target.h" |
44 | #include "target-def.h" | |
4af476d7 | 45 | #include "df.h" |
11bb1f11 | 46 | |
d1776069 AO |
47 | /* This is used by GOTaddr2picreg to uniquely identify |
48 | UNSPEC_INT_LABELs. */ | |
49 | int mn10300_unspec_int_label_counter; | |
50 | ||
2beef00e AO |
51 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
52 | names are not prefixed by underscores, to tell whether to prefix a | |
53 | label with a plus sign or not, so that the assembler can tell | |
54 | symbol names from register names. */ | |
55 | int mn10300_protect_label; | |
56 | ||
13dd556c RS |
57 | /* The selected processor. */ |
58 | enum processor_type mn10300_processor = PROCESSOR_DEFAULT; | |
59 | ||
f3f63737 NC |
60 | /* Processor type to select for tuning. */ |
61 | static const char * mn10300_tune_string = NULL; | |
62 | ||
63 | /* Selected processor type for tuning. */ | |
64 | enum processor_type mn10300_tune_cpu = PROCESSOR_DEFAULT; | |
65 | ||
4d1a91c2 JL |
66 | /* The size of the callee register save area. Right now we save everything |
67 | on entry since it costs us nothing in code size. It does cost us from a | |
68 | speed standpoint, so we want to optimize this sooner or later. */ | |
e7ab5593 NC |
69 | #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \ |
70 | + 4 * df_regs_ever_live_p (3) \ | |
71 | + 4 * df_regs_ever_live_p (6) \ | |
72 | + 4 * df_regs_ever_live_p (7) \ | |
73 | + 16 * (df_regs_ever_live_p (14) \ | |
74 | || df_regs_ever_live_p (15) \ | |
75 | || df_regs_ever_live_p (16) \ | |
76 | || df_regs_ever_live_p (17))) | |
990dc016 | 77 | |
3020190e JM |
78 | /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ |
79 | static const struct default_options mn10300_option_optimization_table[] = | |
80 | { | |
81 | { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, | |
82 | { OPT_LEVELS_NONE, 0, NULL, 0 } | |
83 | }; | |
672a6f42 | 84 | \f |
13dd556c RS |
85 | /* Implement TARGET_HANDLE_OPTION. */ |
86 | ||
87 | static bool | |
88 | mn10300_handle_option (size_t code, | |
89 | const char *arg ATTRIBUTE_UNUSED, | |
90 | int value) | |
91 | { | |
92 | switch (code) | |
93 | { | |
94 | case OPT_mam33: | |
95 | mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300; | |
96 | return true; | |
f3f63737 | 97 | |
13dd556c RS |
98 | case OPT_mam33_2: |
99 | mn10300_processor = (value | |
100 | ? PROCESSOR_AM33_2 | |
101 | : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT)); | |
102 | return true; | |
f3f63737 NC |
103 | |
104 | case OPT_mam34: | |
105 | mn10300_processor = (value ? PROCESSOR_AM34 : PROCESSOR_DEFAULT); | |
106 | return true; | |
107 | ||
108 | case OPT_mtune_: | |
109 | mn10300_tune_string = arg; | |
110 | return true; | |
111 | ||
13dd556c RS |
112 | default: |
113 | return true; | |
114 | } | |
115 | } | |
116 | ||
c5387660 | 117 | /* Implement TARGET_OPTION_OVERRIDE. */ |
13dd556c | 118 | |
c5387660 JM |
119 | static void |
120 | mn10300_option_override (void) | |
13dd556c RS |
121 | { |
122 | if (TARGET_AM33) | |
123 | target_flags &= ~MASK_MULT_BUG; | |
f3f63737 NC |
124 | else |
125 | { | |
126 | /* Disable scheduling for the MN10300 as we do | |
127 | not have timing information available for it. */ | |
128 | flag_schedule_insns = 0; | |
129 | flag_schedule_insns_after_reload = 0; | |
ec815d65 RH |
130 | |
131 | /* Force enable splitting of wide types, as otherwise it is trivial | |
132 | to run out of registers. Indeed, this works so well that register | |
133 | allocation problems are now more common *without* optimization, | |
134 | when this flag is not enabled by default. */ | |
135 | flag_split_wide_types = 1; | |
f3f63737 NC |
136 | } |
137 | ||
138 | if (mn10300_tune_string) | |
139 | { | |
140 | if (strcasecmp (mn10300_tune_string, "mn10300") == 0) | |
141 | mn10300_tune_cpu = PROCESSOR_MN10300; | |
142 | else if (strcasecmp (mn10300_tune_string, "am33") == 0) | |
143 | mn10300_tune_cpu = PROCESSOR_AM33; | |
144 | else if (strcasecmp (mn10300_tune_string, "am33-2") == 0) | |
145 | mn10300_tune_cpu = PROCESSOR_AM33_2; | |
146 | else if (strcasecmp (mn10300_tune_string, "am34") == 0) | |
147 | mn10300_tune_cpu = PROCESSOR_AM34; | |
148 | else | |
149 | error ("-mtune= expects mn10300, am33, am33-2, or am34"); | |
150 | } | |
13dd556c RS |
151 | } |
152 | ||
1bc7c5b6 | 153 | static void |
f1777882 | 154 | mn10300_file_start (void) |
11bb1f11 | 155 | { |
1bc7c5b6 | 156 | default_file_start (); |
705ac34f | 157 | |
18e9d2f9 AO |
158 | if (TARGET_AM33_2) |
159 | fprintf (asm_out_file, "\t.am33_2\n"); | |
160 | else if (TARGET_AM33) | |
1bc7c5b6 | 161 | fprintf (asm_out_file, "\t.am33\n"); |
11bb1f11 JL |
162 | } |
163 | \f | |
11bb1f11 JL |
164 | /* Print operand X using operand code CODE to assembly language output file |
165 | FILE. */ | |
166 | ||
167 | void | |
e7ab5593 | 168 | mn10300_print_operand (FILE *file, rtx x, int code) |
11bb1f11 JL |
169 | { |
170 | switch (code) | |
171 | { | |
172 | case 'b': | |
173 | case 'B': | |
4af476d7 | 174 | if (GET_MODE (XEXP (x, 0)) == CC_FLOATmode) |
18e9d2f9 AO |
175 | { |
176 | switch (code == 'b' ? GET_CODE (x) | |
177 | : reverse_condition_maybe_unordered (GET_CODE (x))) | |
178 | { | |
179 | case NE: | |
180 | fprintf (file, "ne"); | |
181 | break; | |
182 | case EQ: | |
183 | fprintf (file, "eq"); | |
184 | break; | |
185 | case GE: | |
186 | fprintf (file, "ge"); | |
187 | break; | |
188 | case GT: | |
189 | fprintf (file, "gt"); | |
190 | break; | |
191 | case LE: | |
192 | fprintf (file, "le"); | |
193 | break; | |
194 | case LT: | |
195 | fprintf (file, "lt"); | |
196 | break; | |
197 | case ORDERED: | |
198 | fprintf (file, "lge"); | |
199 | break; | |
200 | case UNORDERED: | |
201 | fprintf (file, "uo"); | |
202 | break; | |
203 | case LTGT: | |
204 | fprintf (file, "lg"); | |
205 | break; | |
206 | case UNEQ: | |
207 | fprintf (file, "ue"); | |
208 | break; | |
209 | case UNGE: | |
210 | fprintf (file, "uge"); | |
211 | break; | |
212 | case UNGT: | |
213 | fprintf (file, "ug"); | |
214 | break; | |
215 | case UNLE: | |
216 | fprintf (file, "ule"); | |
217 | break; | |
218 | case UNLT: | |
219 | fprintf (file, "ul"); | |
220 | break; | |
221 | default: | |
dc759020 | 222 | gcc_unreachable (); |
18e9d2f9 AO |
223 | } |
224 | break; | |
225 | } | |
11bb1f11 JL |
226 | /* These are normal and reversed branches. */ |
227 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
228 | { | |
229 | case NE: | |
230 | fprintf (file, "ne"); | |
231 | break; | |
232 | case EQ: | |
233 | fprintf (file, "eq"); | |
234 | break; | |
235 | case GE: | |
236 | fprintf (file, "ge"); | |
237 | break; | |
238 | case GT: | |
239 | fprintf (file, "gt"); | |
240 | break; | |
241 | case LE: | |
242 | fprintf (file, "le"); | |
243 | break; | |
244 | case LT: | |
245 | fprintf (file, "lt"); | |
246 | break; | |
247 | case GEU: | |
248 | fprintf (file, "cc"); | |
249 | break; | |
250 | case GTU: | |
251 | fprintf (file, "hi"); | |
252 | break; | |
253 | case LEU: | |
254 | fprintf (file, "ls"); | |
255 | break; | |
256 | case LTU: | |
257 | fprintf (file, "cs"); | |
258 | break; | |
259 | default: | |
dc759020 | 260 | gcc_unreachable (); |
11bb1f11 JL |
261 | } |
262 | break; | |
263 | case 'C': | |
264 | /* This is used for the operand to a call instruction; | |
265 | if it's a REG, enclose it in parens, else output | |
266 | the operand normally. */ | |
e7ab5593 | 267 | if (REG_P (x)) |
11bb1f11 JL |
268 | { |
269 | fputc ('(', file); | |
e7ab5593 | 270 | mn10300_print_operand (file, x, 0); |
11bb1f11 JL |
271 | fputc (')', file); |
272 | } | |
273 | else | |
e7ab5593 | 274 | mn10300_print_operand (file, x, 0); |
11bb1f11 | 275 | break; |
5abc5de9 | 276 | |
18e9d2f9 AO |
277 | case 'D': |
278 | switch (GET_CODE (x)) | |
279 | { | |
280 | case MEM: | |
281 | fputc ('(', file); | |
282 | output_address (XEXP (x, 0)); | |
283 | fputc (')', file); | |
284 | break; | |
285 | ||
286 | case REG: | |
287 | fprintf (file, "fd%d", REGNO (x) - 18); | |
288 | break; | |
289 | ||
290 | default: | |
dc759020 | 291 | gcc_unreachable (); |
18e9d2f9 AO |
292 | } |
293 | break; | |
294 | ||
38c37a0e JL |
295 | /* These are the least significant word in a 64bit value. */ |
296 | case 'L': | |
297 | switch (GET_CODE (x)) | |
298 | { | |
299 | case MEM: | |
300 | fputc ('(', file); | |
301 | output_address (XEXP (x, 0)); | |
302 | fputc (')', file); | |
303 | break; | |
304 | ||
305 | case REG: | |
306 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
307 | break; | |
308 | ||
309 | case SUBREG: | |
ddef6bc7 | 310 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
38c37a0e JL |
311 | break; |
312 | ||
313 | case CONST_DOUBLE: | |
314 | { | |
315 | long val[2]; | |
316 | REAL_VALUE_TYPE rv; | |
317 | ||
318 | switch (GET_MODE (x)) | |
319 | { | |
320 | case DFmode: | |
321 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
322 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 323 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
324 | break;; |
325 | case SFmode: | |
326 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
327 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
cf31fafa | 328 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
329 | break;; |
330 | case VOIDmode: | |
331 | case DImode: | |
e7ab5593 NC |
332 | mn10300_print_operand_address (file, |
333 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
38c37a0e | 334 | break; |
69bc71fa KG |
335 | default: |
336 | break; | |
38c37a0e JL |
337 | } |
338 | break; | |
339 | } | |
340 | ||
341 | case CONST_INT: | |
212bc5fa AO |
342 | { |
343 | rtx low, high; | |
344 | split_double (x, &low, &high); | |
345 | fprintf (file, "%ld", (long)INTVAL (low)); | |
346 | break; | |
347 | } | |
38c37a0e JL |
348 | |
349 | default: | |
dc759020 | 350 | gcc_unreachable (); |
38c37a0e JL |
351 | } |
352 | break; | |
353 | ||
354 | /* Similarly, but for the most significant word. */ | |
355 | case 'H': | |
356 | switch (GET_CODE (x)) | |
357 | { | |
358 | case MEM: | |
359 | fputc ('(', file); | |
b72f00af | 360 | x = adjust_address (x, SImode, 4); |
38c37a0e JL |
361 | output_address (XEXP (x, 0)); |
362 | fputc (')', file); | |
363 | break; | |
364 | ||
365 | case REG: | |
366 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
367 | break; | |
368 | ||
369 | case SUBREG: | |
ddef6bc7 | 370 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
38c37a0e JL |
371 | break; |
372 | ||
373 | case CONST_DOUBLE: | |
374 | { | |
375 | long val[2]; | |
376 | REAL_VALUE_TYPE rv; | |
377 | ||
378 | switch (GET_MODE (x)) | |
379 | { | |
380 | case DFmode: | |
381 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
382 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 383 | fprintf (file, "0x%lx", val[1]); |
38c37a0e JL |
384 | break;; |
385 | case SFmode: | |
dc759020 | 386 | gcc_unreachable (); |
38c37a0e JL |
387 | case VOIDmode: |
388 | case DImode: | |
e7ab5593 NC |
389 | mn10300_print_operand_address (file, |
390 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
38c37a0e | 391 | break; |
69bc71fa KG |
392 | default: |
393 | break; | |
38c37a0e JL |
394 | } |
395 | break; | |
396 | } | |
397 | ||
398 | case CONST_INT: | |
212bc5fa AO |
399 | { |
400 | rtx low, high; | |
401 | split_double (x, &low, &high); | |
402 | fprintf (file, "%ld", (long)INTVAL (high)); | |
403 | break; | |
404 | } | |
405 | ||
38c37a0e | 406 | default: |
dc759020 | 407 | gcc_unreachable (); |
38c37a0e JL |
408 | } |
409 | break; | |
410 | ||
411 | case 'A': | |
412 | fputc ('(', file); | |
f3f63737 | 413 | if (REG_P (XEXP (x, 0))) |
a556fd39 | 414 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx)); |
38c37a0e JL |
415 | else |
416 | output_address (XEXP (x, 0)); | |
417 | fputc (')', file); | |
418 | break; | |
419 | ||
6fafc523 | 420 | case 'N': |
dc759020 | 421 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
a58be199 AO |
422 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); |
423 | break; | |
424 | ||
425 | case 'U': | |
dc759020 | 426 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
a58be199 | 427 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); |
6fafc523 JL |
428 | break; |
429 | ||
576e5acc JL |
430 | /* For shift counts. The hardware ignores the upper bits of |
431 | any immediate, but the assembler will flag an out of range | |
432 | shift count as an error. So we mask off the high bits | |
433 | of the immediate here. */ | |
434 | case 'S': | |
f3f63737 | 435 | if (CONST_INT_P (x)) |
576e5acc | 436 | { |
a58be199 | 437 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
576e5acc JL |
438 | break; |
439 | } | |
440 | /* FALL THROUGH */ | |
441 | ||
11bb1f11 JL |
442 | default: |
443 | switch (GET_CODE (x)) | |
444 | { | |
445 | case MEM: | |
446 | fputc ('(', file); | |
447 | output_address (XEXP (x, 0)); | |
448 | fputc (')', file); | |
449 | break; | |
450 | ||
38c37a0e JL |
451 | case PLUS: |
452 | output_address (x); | |
453 | break; | |
454 | ||
11bb1f11 JL |
455 | case REG: |
456 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
457 | break; | |
458 | ||
459 | case SUBREG: | |
ddef6bc7 | 460 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
11bb1f11 JL |
461 | break; |
462 | ||
38c37a0e JL |
463 | /* This will only be single precision.... */ |
464 | case CONST_DOUBLE: | |
465 | { | |
466 | unsigned long val; | |
467 | REAL_VALUE_TYPE rv; | |
468 | ||
469 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
470 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
cf31fafa | 471 | fprintf (file, "0x%lx", val); |
38c37a0e JL |
472 | break; |
473 | } | |
474 | ||
11bb1f11 JL |
475 | case CONST_INT: |
476 | case SYMBOL_REF: | |
477 | case CONST: | |
478 | case LABEL_REF: | |
479 | case CODE_LABEL: | |
d1776069 | 480 | case UNSPEC: |
e7ab5593 | 481 | mn10300_print_operand_address (file, x); |
11bb1f11 JL |
482 | break; |
483 | default: | |
dc759020 | 484 | gcc_unreachable (); |
11bb1f11 JL |
485 | } |
486 | break; | |
487 | } | |
488 | } | |
489 | ||
490 | /* Output assembly language output for the address ADDR to FILE. */ | |
491 | ||
492 | void | |
e7ab5593 | 493 | mn10300_print_operand_address (FILE *file, rtx addr) |
11bb1f11 JL |
494 | { |
495 | switch (GET_CODE (addr)) | |
496 | { | |
705ac34f | 497 | case POST_INC: |
e7ab5593 | 498 | mn10300_print_operand_address (file, XEXP (addr, 0)); |
705ac34f JL |
499 | fputc ('+', file); |
500 | break; | |
11bb1f11 | 501 | case REG: |
e7ab5593 | 502 | mn10300_print_operand (file, addr, 0); |
11bb1f11 JL |
503 | break; |
504 | case PLUS: | |
505 | { | |
506 | rtx base, index; | |
507 | if (REG_P (XEXP (addr, 0)) | |
508 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
509 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
510 | else if (REG_P (XEXP (addr, 1)) | |
511 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
512 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
513 | else | |
dc759020 | 514 | gcc_unreachable (); |
e7ab5593 | 515 | mn10300_print_operand (file, index, 0); |
11bb1f11 | 516 | fputc (',', file); |
e7ab5593 | 517 | mn10300_print_operand (file, base, 0);; |
11bb1f11 JL |
518 | break; |
519 | } | |
520 | case SYMBOL_REF: | |
521 | output_addr_const (file, addr); | |
522 | break; | |
523 | default: | |
524 | output_addr_const (file, addr); | |
525 | break; | |
526 | } | |
527 | } | |
528 | ||
535bd17c AS |
529 | /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. |
530 | ||
531 | Used for PIC-specific UNSPECs. */ | |
532 | ||
533 | static bool | |
534 | mn10300_asm_output_addr_const_extra (FILE *file, rtx x) | |
535 | { | |
536 | if (GET_CODE (x) == UNSPEC) | |
537 | { | |
538 | switch (XINT (x, 1)) | |
539 | { | |
540 | case UNSPEC_INT_LABEL: | |
541 | asm_fprintf (file, ".%LLIL" HOST_WIDE_INT_PRINT_DEC, | |
542 | INTVAL (XVECEXP (x, 0, 0))); | |
543 | break; | |
544 | case UNSPEC_PIC: | |
545 | /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ | |
546 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
547 | break; | |
548 | case UNSPEC_GOT: | |
549 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
550 | fputs ("@GOT", file); | |
551 | break; | |
552 | case UNSPEC_GOTOFF: | |
553 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
554 | fputs ("@GOTOFF", file); | |
555 | break; | |
556 | case UNSPEC_PLT: | |
557 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
558 | fputs ("@PLT", file); | |
559 | break; | |
560 | case UNSPEC_GOTSYM_OFF: | |
561 | assemble_name (file, GOT_SYMBOL_NAME); | |
562 | fputs ("-(", file); | |
563 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
564 | fputs ("-.)", file); | |
565 | break; | |
566 | default: | |
567 | return false; | |
568 | } | |
569 | return true; | |
570 | } | |
571 | else | |
572 | return false; | |
573 | } | |
574 | ||
18e9d2f9 AO |
575 | /* Count the number of FP registers that have to be saved. */ |
576 | static int | |
f1777882 | 577 | fp_regs_to_save (void) |
18e9d2f9 AO |
578 | { |
579 | int i, n = 0; | |
580 | ||
581 | if (! TARGET_AM33_2) | |
582 | return 0; | |
583 | ||
584 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 585 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
18e9d2f9 AO |
586 | ++n; |
587 | ||
588 | return n; | |
589 | } | |
590 | ||
f6cd7c62 RS |
591 | /* Print a set of registers in the format required by "movm" and "ret". |
592 | Register K is saved if bit K of MASK is set. The data and address | |
593 | registers can be stored individually, but the extended registers cannot. | |
9f5ed61a | 594 | We assume that the mask already takes that into account. For instance, |
8596d0a1 | 595 | bits 14 to 17 must have the same value. */ |
f6cd7c62 RS |
596 | |
597 | void | |
f1777882 | 598 | mn10300_print_reg_list (FILE *file, int mask) |
f6cd7c62 RS |
599 | { |
600 | int need_comma; | |
601 | int i; | |
602 | ||
603 | need_comma = 0; | |
604 | fputc ('[', file); | |
605 | ||
606 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
607 | if ((mask & (1 << i)) != 0) | |
608 | { | |
609 | if (need_comma) | |
610 | fputc (',', file); | |
611 | fputs (reg_names [i], file); | |
612 | need_comma = 1; | |
613 | } | |
614 | ||
615 | if ((mask & 0x3c000) != 0) | |
616 | { | |
dc759020 | 617 | gcc_assert ((mask & 0x3c000) == 0x3c000); |
f6cd7c62 RS |
618 | if (need_comma) |
619 | fputc (',', file); | |
620 | fputs ("exreg1", file); | |
621 | need_comma = 1; | |
622 | } | |
623 | ||
624 | fputc (']', file); | |
625 | } | |
626 | ||
38c37a0e | 627 | int |
e7ab5593 | 628 | mn10300_can_use_return_insn (void) |
38c37a0e | 629 | { |
460f4b9d | 630 | /* size includes the fixed stack space needed for function calls. */ |
38173d38 | 631 | int size = get_frame_size () + crtl->outgoing_args_size; |
460f4b9d JL |
632 | |
633 | /* And space for the return pointer. */ | |
38173d38 | 634 | size += crtl->outgoing_args_size ? 4 : 0; |
38c37a0e JL |
635 | |
636 | return (reload_completed | |
637 | && size == 0 | |
6fb5fa3c DB |
638 | && !df_regs_ever_live_p (2) |
639 | && !df_regs_ever_live_p (3) | |
640 | && !df_regs_ever_live_p (6) | |
641 | && !df_regs_ever_live_p (7) | |
642 | && !df_regs_ever_live_p (14) | |
643 | && !df_regs_ever_live_p (15) | |
644 | && !df_regs_ever_live_p (16) | |
645 | && !df_regs_ever_live_p (17) | |
18e9d2f9 | 646 | && fp_regs_to_save () == 0 |
38c37a0e JL |
647 | && !frame_pointer_needed); |
648 | } | |
649 | ||
f6cd7c62 RS |
650 | /* Returns the set of live, callee-saved registers as a bitmask. The |
651 | callee-saved extended registers cannot be stored individually, so | |
8596d0a1 | 652 | all of them will be included in the mask if any one of them is used. */ |
f6cd7c62 RS |
653 | |
654 | int | |
f1777882 | 655 | mn10300_get_live_callee_saved_regs (void) |
f6cd7c62 RS |
656 | { |
657 | int mask; | |
658 | int i; | |
659 | ||
660 | mask = 0; | |
18e9d2f9 | 661 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
9d54866d | 662 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
f6cd7c62 RS |
663 | mask |= (1 << i); |
664 | if ((mask & 0x3c000) != 0) | |
665 | mask |= 0x3c000; | |
666 | ||
667 | return mask; | |
668 | } | |
669 | ||
2720cc47 NC |
670 | static rtx |
671 | F (rtx r) | |
672 | { | |
673 | RTX_FRAME_RELATED_P (r) = 1; | |
674 | return r; | |
675 | } | |
676 | ||
f6cd7c62 RS |
677 | /* Generate an instruction that pushes several registers onto the stack. |
678 | Register K will be saved if bit K in MASK is set. The function does | |
679 | nothing if MASK is zero. | |
680 | ||
681 | To be compatible with the "movm" instruction, the lowest-numbered | |
682 | register must be stored in the lowest slot. If MASK is the set | |
683 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
684 | instruction will have the form: | |
685 | ||
686 | (parallel | |
687 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
688 | (set (mem:SI (plus:SI (reg:SI 9) | |
689 | (const_int -1*4))) | |
690 | (reg:SI RN)) | |
691 | ... | |
692 | (set (mem:SI (plus:SI (reg:SI 9) | |
693 | (const_int -N*4))) | |
694 | (reg:SI R1))) */ | |
695 | ||
cc909bba RH |
696 | static void |
697 | mn10300_gen_multiple_store (unsigned int mask) | |
f6cd7c62 | 698 | { |
cc909bba RH |
699 | /* The order in which registers are stored, from SP-4 through SP-N*4. */ |
700 | static const unsigned int store_order[8] = { | |
701 | /* e2, e3: never saved */ | |
702 | FIRST_EXTENDED_REGNUM + 4, | |
703 | FIRST_EXTENDED_REGNUM + 5, | |
704 | FIRST_EXTENDED_REGNUM + 6, | |
705 | FIRST_EXTENDED_REGNUM + 7, | |
706 | /* e0, e1, mdrq, mcrh, mcrl, mcvf: never saved. */ | |
707 | FIRST_DATA_REGNUM + 2, | |
708 | FIRST_DATA_REGNUM + 3, | |
709 | FIRST_ADDRESS_REGNUM + 2, | |
710 | FIRST_ADDRESS_REGNUM + 3, | |
711 | /* d0, d1, a0, a1, mdr, lir, lar: never saved. */ | |
712 | }; | |
713 | ||
714 | rtx x, elts[9]; | |
715 | unsigned int i; | |
716 | int count; | |
717 | ||
718 | if (mask == 0) | |
719 | return; | |
720 | ||
721 | for (i = count = 0; i < ARRAY_SIZE(store_order); ++i) | |
f6cd7c62 | 722 | { |
cc909bba RH |
723 | unsigned regno = store_order[i]; |
724 | ||
725 | if (((mask >> regno) & 1) == 0) | |
726 | continue; | |
f6cd7c62 | 727 | |
cc909bba RH |
728 | ++count; |
729 | x = plus_constant (stack_pointer_rtx, count * -4); | |
730 | x = gen_frame_mem (SImode, x); | |
731 | x = gen_rtx_SET (VOIDmode, x, gen_rtx_REG (SImode, regno)); | |
732 | elts[count] = F(x); | |
733 | ||
734 | /* Remove the register from the mask so that... */ | |
735 | mask &= ~(1u << regno); | |
f6cd7c62 | 736 | } |
cc909bba RH |
737 | |
738 | /* ... we can make sure that we didn't try to use a register | |
739 | not listed in the store order. */ | |
740 | gcc_assert (mask == 0); | |
741 | ||
742 | /* Create the instruction that updates the stack pointer. */ | |
743 | x = plus_constant (stack_pointer_rtx, count * -4); | |
744 | x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x); | |
745 | elts[0] = F(x); | |
746 | ||
747 | /* We need one PARALLEL element to update the stack pointer and | |
748 | an additional element for each register that is stored. */ | |
749 | x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (count + 1, elts)); | |
750 | F (emit_insn (x)); | |
f6cd7c62 RS |
751 | } |
752 | ||
11bb1f11 | 753 | void |
e7ab5593 | 754 | mn10300_expand_prologue (void) |
11bb1f11 | 755 | { |
036182e7 | 756 | HOST_WIDE_INT size; |
3dbc43d1 | 757 | |
3dbc43d1 | 758 | /* SIZE includes the fixed stack space needed for function calls. */ |
38173d38 JH |
759 | size = get_frame_size () + crtl->outgoing_args_size; |
760 | size += (crtl->outgoing_args_size ? 4 : 0); | |
11bb1f11 | 761 | |
8596d0a1 | 762 | /* If we use any of the callee-saved registers, save them now. */ |
f6cd7c62 | 763 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); |
777fbf09 | 764 | |
18e9d2f9 AO |
765 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
766 | { | |
767 | int num_regs_to_save = fp_regs_to_save (), i; | |
768 | HOST_WIDE_INT xsize; | |
e7ab5593 NC |
769 | enum |
770 | { | |
771 | save_sp_merge, | |
772 | save_sp_no_merge, | |
773 | save_sp_partial_merge, | |
774 | save_a0_merge, | |
775 | save_a0_no_merge | |
776 | } strategy; | |
18e9d2f9 AO |
777 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; |
778 | rtx reg; | |
18e9d2f9 AO |
779 | |
780 | /* We have several different strategies to save FP registers. | |
781 | We can store them using SP offsets, which is beneficial if | |
782 | there are just a few registers to save, or we can use `a0' in | |
783 | post-increment mode (`a0' is the only call-clobbered address | |
784 | register that is never used to pass information to a | |
785 | function). Furthermore, if we don't need a frame pointer, we | |
786 | can merge the two SP adds into a single one, but this isn't | |
787 | always beneficial; sometimes we can just split the two adds | |
788 | so that we don't exceed a 16-bit constant size. The code | |
789 | below will select which strategy to use, so as to generate | |
790 | smallest code. Ties are broken in favor or shorter sequences | |
791 | (in terms of number of instructions). */ | |
792 | ||
793 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
794 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
795 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
796 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
f4a88680 JR |
797 | |
798 | /* We add 0 * (S) in two places to promote to the type of S, | |
799 | so that all arms of the conditional have the same type. */ | |
18e9d2f9 | 800 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ |
f4a88680 | 801 | (((S) >= (L)) ? 0 * (S) + (SIZE1) * (N) \ |
18e9d2f9 AO |
802 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ |
803 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
f4a88680 | 804 | : 0 * (S) + (ELSE)) |
18e9d2f9 AO |
805 | #define SIZE_FMOV_SP_(S,N) \ |
806 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
807 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
808 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
809 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
810 | ||
811 | /* Consider alternative save_sp_merge only if we don't need the | |
4375e090 | 812 | frame pointer and size is nonzero. */ |
18e9d2f9 AO |
813 | if (! frame_pointer_needed && size) |
814 | { | |
815 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
816 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
817 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
818 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
819 | ||
820 | if (this_strategy_size < strategy_size) | |
821 | { | |
822 | strategy = save_sp_merge; | |
823 | strategy_size = this_strategy_size; | |
824 | } | |
825 | } | |
826 | ||
827 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
828 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
829 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
830 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
831 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
832 | if (size) | |
833 | { | |
834 | /* Insn: add -size, sp. */ | |
835 | this_strategy_size += SIZE_ADD_SP (-size); | |
836 | } | |
837 | ||
838 | if (this_strategy_size < strategy_size) | |
839 | { | |
840 | strategy = save_sp_no_merge; | |
841 | strategy_size = this_strategy_size; | |
842 | } | |
843 | ||
844 | /* Consider alternative save_sp_partial_merge only if we don't | |
845 | need a frame pointer and size is reasonably large. */ | |
846 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
847 | { | |
848 | /* Insn: add -128, sp. */ | |
849 | this_strategy_size = SIZE_ADD_SP (-128); | |
850 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
851 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
852 | num_regs_to_save); | |
853 | if (size) | |
854 | { | |
855 | /* Insn: add 128-size, sp. */ | |
856 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
857 | } | |
858 | ||
859 | if (this_strategy_size < strategy_size) | |
860 | { | |
861 | strategy = save_sp_partial_merge; | |
862 | strategy_size = this_strategy_size; | |
863 | } | |
864 | } | |
865 | ||
866 | /* Consider alternative save_a0_merge only if we don't need a | |
4375e090 | 867 | frame pointer, size is nonzero and the user hasn't |
18e9d2f9 AO |
868 | changed the calling conventions of a0. */ |
869 | if (! frame_pointer_needed && size | |
9d54866d | 870 | && call_really_used_regs [FIRST_ADDRESS_REGNUM] |
18e9d2f9 AO |
871 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
872 | { | |
873 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
874 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
875 | /* Insn: mov sp, a0. */ | |
876 | this_strategy_size++; | |
877 | if (size) | |
878 | { | |
879 | /* Insn: add size, a0. */ | |
880 | this_strategy_size += SIZE_ADD_AX (size); | |
881 | } | |
882 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
883 | this_strategy_size += 3 * num_regs_to_save; | |
884 | ||
885 | if (this_strategy_size < strategy_size) | |
886 | { | |
887 | strategy = save_a0_merge; | |
888 | strategy_size = this_strategy_size; | |
889 | } | |
890 | } | |
891 | ||
892 | /* Consider alternative save_a0_no_merge if the user hasn't | |
8596d0a1 | 893 | changed the calling conventions of a0. */ |
9d54866d | 894 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM] |
18e9d2f9 AO |
895 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
896 | { | |
897 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
898 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
899 | /* Insn: mov sp, a0. */ | |
900 | this_strategy_size++; | |
901 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
902 | this_strategy_size += 3 * num_regs_to_save; | |
903 | if (size) | |
904 | { | |
905 | /* Insn: add -size, sp. */ | |
906 | this_strategy_size += SIZE_ADD_SP (-size); | |
907 | } | |
908 | ||
909 | if (this_strategy_size < strategy_size) | |
910 | { | |
911 | strategy = save_a0_no_merge; | |
912 | strategy_size = this_strategy_size; | |
913 | } | |
914 | } | |
915 | ||
916 | /* Emit the initial SP add, common to all strategies. */ | |
917 | switch (strategy) | |
918 | { | |
919 | case save_sp_no_merge: | |
920 | case save_a0_no_merge: | |
2720cc47 NC |
921 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
922 | stack_pointer_rtx, | |
923 | GEN_INT (-4 * num_regs_to_save)))); | |
18e9d2f9 AO |
924 | xsize = 0; |
925 | break; | |
926 | ||
927 | case save_sp_partial_merge: | |
2720cc47 NC |
928 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
929 | stack_pointer_rtx, | |
930 | GEN_INT (-128)))); | |
18e9d2f9 AO |
931 | xsize = 128 - 4 * num_regs_to_save; |
932 | size -= xsize; | |
933 | break; | |
934 | ||
935 | case save_sp_merge: | |
936 | case save_a0_merge: | |
2720cc47 NC |
937 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
938 | stack_pointer_rtx, | |
939 | GEN_INT (-(size + 4 * num_regs_to_save))))); | |
18e9d2f9 | 940 | /* We'll have to adjust FP register saves according to the |
8596d0a1 | 941 | frame size. */ |
18e9d2f9 AO |
942 | xsize = size; |
943 | /* Since we've already created the stack frame, don't do it | |
8596d0a1 | 944 | again at the end of the function. */ |
18e9d2f9 AO |
945 | size = 0; |
946 | break; | |
947 | ||
948 | default: | |
dc759020 | 949 | gcc_unreachable (); |
18e9d2f9 | 950 | } |
5abc5de9 | 951 | |
18e9d2f9 AO |
952 | /* Now prepare register a0, if we have decided to use it. */ |
953 | switch (strategy) | |
954 | { | |
955 | case save_sp_merge: | |
956 | case save_sp_no_merge: | |
957 | case save_sp_partial_merge: | |
958 | reg = 0; | |
959 | break; | |
960 | ||
961 | case save_a0_merge: | |
962 | case save_a0_no_merge: | |
963 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
2720cc47 | 964 | F (emit_insn (gen_movsi (reg, stack_pointer_rtx))); |
18e9d2f9 | 965 | if (xsize) |
2720cc47 | 966 | F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)))); |
18e9d2f9 AO |
967 | reg = gen_rtx_POST_INC (SImode, reg); |
968 | break; | |
5abc5de9 | 969 | |
18e9d2f9 | 970 | default: |
dc759020 | 971 | gcc_unreachable (); |
18e9d2f9 | 972 | } |
5abc5de9 | 973 | |
18e9d2f9 AO |
974 | /* Now actually save the FP registers. */ |
975 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 976 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
18e9d2f9 AO |
977 | { |
978 | rtx addr; | |
979 | ||
980 | if (reg) | |
981 | addr = reg; | |
982 | else | |
983 | { | |
984 | /* If we aren't using `a0', use an SP offset. */ | |
985 | if (xsize) | |
986 | { | |
987 | addr = gen_rtx_PLUS (SImode, | |
988 | stack_pointer_rtx, | |
989 | GEN_INT (xsize)); | |
990 | } | |
991 | else | |
992 | addr = stack_pointer_rtx; | |
5abc5de9 | 993 | |
18e9d2f9 AO |
994 | xsize += 4; |
995 | } | |
996 | ||
2720cc47 NC |
997 | F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr), |
998 | gen_rtx_REG (SFmode, i)))); | |
18e9d2f9 AO |
999 | } |
1000 | } | |
1001 | ||
777fbf09 | 1002 | /* Now put the frame pointer into the frame pointer register. */ |
11bb1f11 | 1003 | if (frame_pointer_needed) |
2720cc47 | 1004 | F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx)); |
11bb1f11 | 1005 | |
777fbf09 | 1006 | /* Allocate stack for this frame. */ |
11bb1f11 | 1007 | if (size) |
2720cc47 NC |
1008 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
1009 | stack_pointer_rtx, | |
1010 | GEN_INT (-size)))); | |
1011 | ||
6fb5fa3c DB |
1012 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
1013 | emit_insn (gen_GOTaddr2picreg ()); | |
11bb1f11 JL |
1014 | } |
1015 | ||
1016 | void | |
e7ab5593 | 1017 | mn10300_expand_epilogue (void) |
11bb1f11 | 1018 | { |
036182e7 | 1019 | HOST_WIDE_INT size; |
3dbc43d1 | 1020 | |
3dbc43d1 | 1021 | /* SIZE includes the fixed stack space needed for function calls. */ |
38173d38 JH |
1022 | size = get_frame_size () + crtl->outgoing_args_size; |
1023 | size += (crtl->outgoing_args_size ? 4 : 0); | |
4af476d7 | 1024 | |
18e9d2f9 AO |
1025 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
1026 | { | |
1027 | int num_regs_to_save = fp_regs_to_save (), i; | |
1028 | rtx reg = 0; | |
1029 | ||
1030 | /* We have several options to restore FP registers. We could | |
1031 | load them from SP offsets, but, if there are enough FP | |
1032 | registers to restore, we win if we use a post-increment | |
1033 | addressing mode. */ | |
1034 | ||
1035 | /* If we have a frame pointer, it's the best option, because we | |
1036 | already know it has the value we want. */ | |
1037 | if (frame_pointer_needed) | |
1038 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
1039 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
1040 | it's never used for return values. But only do so if it's | |
1041 | smaller than using SP offsets. */ | |
1042 | else | |
1043 | { | |
1044 | enum { restore_sp_post_adjust, | |
1045 | restore_sp_pre_adjust, | |
1046 | restore_sp_partial_adjust, | |
1047 | restore_a1 } strategy; | |
1048 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
1049 | ||
1050 | /* Consider using sp offsets before adjusting sp. */ | |
1051 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1052 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
1053 | /* If size is too large, we'll have to adjust SP with an | |
1054 | add. */ | |
1055 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1056 | { | |
1057 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
1058 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
1059 | } | |
1060 | /* If we don't have to restore any non-FP registers, | |
1061 | we'll be able to save one byte by using rets. */ | |
1062 | if (! REG_SAVE_BYTES) | |
1063 | this_strategy_size--; | |
1064 | ||
1065 | if (this_strategy_size < strategy_size) | |
1066 | { | |
1067 | strategy = restore_sp_post_adjust; | |
1068 | strategy_size = this_strategy_size; | |
1069 | } | |
1070 | ||
1071 | /* Consider using sp offsets after adjusting sp. */ | |
1072 | /* Insn: add size, sp. */ | |
1073 | this_strategy_size = SIZE_ADD_SP (size); | |
1074 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1075 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
1076 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1077 | save area, so, no savings. */ |
18e9d2f9 AO |
1078 | |
1079 | if (this_strategy_size < strategy_size) | |
1080 | { | |
1081 | strategy = restore_sp_pre_adjust; | |
1082 | strategy_size = this_strategy_size; | |
1083 | } | |
1084 | ||
1085 | /* Consider using sp offsets after partially adjusting sp. | |
1086 | When size is close to 32Kb, we may be able to adjust SP | |
1087 | with an imm16 add instruction while still using fmov | |
1088 | (d8,sp). */ | |
1089 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1090 | { | |
1091 | /* Insn: add size + 4 * num_regs_to_save | |
1092 | + REG_SAVE_BYTES - 252,sp. */ | |
1093 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save | |
1094 | + REG_SAVE_BYTES - 252); | |
1095 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ | |
1096 | this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES | |
1097 | - 4 * num_regs_to_save, | |
1098 | num_regs_to_save); | |
1099 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1100 | save area, so, no savings. */ |
18e9d2f9 AO |
1101 | |
1102 | if (this_strategy_size < strategy_size) | |
1103 | { | |
1104 | strategy = restore_sp_partial_adjust; | |
1105 | strategy_size = this_strategy_size; | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | /* Consider using a1 in post-increment mode, as long as the | |
1110 | user hasn't changed the calling conventions of a1. */ | |
9d54866d | 1111 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1] |
18e9d2f9 AO |
1112 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) |
1113 | { | |
1114 | /* Insn: mov sp,a1. */ | |
1115 | this_strategy_size = 1; | |
1116 | if (size) | |
1117 | { | |
1118 | /* Insn: add size,a1. */ | |
1119 | this_strategy_size += SIZE_ADD_AX (size); | |
1120 | } | |
1121 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1122 | this_strategy_size += 3 * num_regs_to_save; | |
1123 | /* If size is large enough, we may be able to save a | |
1124 | couple of bytes. */ | |
1125 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1126 | { | |
1127 | /* Insn: mov a1,sp. */ | |
1128 | this_strategy_size += 2; | |
1129 | } | |
1130 | /* If we don't have to restore any non-FP registers, | |
1131 | we'll be able to save one byte by using rets. */ | |
1132 | if (! REG_SAVE_BYTES) | |
1133 | this_strategy_size--; | |
1134 | ||
1135 | if (this_strategy_size < strategy_size) | |
1136 | { | |
1137 | strategy = restore_a1; | |
1138 | strategy_size = this_strategy_size; | |
1139 | } | |
1140 | } | |
1141 | ||
1142 | switch (strategy) | |
1143 | { | |
1144 | case restore_sp_post_adjust: | |
1145 | break; | |
1146 | ||
1147 | case restore_sp_pre_adjust: | |
1148 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1149 | stack_pointer_rtx, | |
1150 | GEN_INT (size))); | |
1151 | size = 0; | |
1152 | break; | |
1153 | ||
1154 | case restore_sp_partial_adjust: | |
1155 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1156 | stack_pointer_rtx, | |
1157 | GEN_INT (size + 4 * num_regs_to_save | |
1158 | + REG_SAVE_BYTES - 252))); | |
1159 | size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save; | |
1160 | break; | |
5abc5de9 | 1161 | |
18e9d2f9 AO |
1162 | case restore_a1: |
1163 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1164 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1165 | if (size) | |
1166 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1167 | break; | |
1168 | ||
1169 | default: | |
dc759020 | 1170 | gcc_unreachable (); |
18e9d2f9 AO |
1171 | } |
1172 | } | |
1173 | ||
1174 | /* Adjust the selected register, if any, for post-increment. */ | |
1175 | if (reg) | |
1176 | reg = gen_rtx_POST_INC (SImode, reg); | |
1177 | ||
1178 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 1179 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
18e9d2f9 AO |
1180 | { |
1181 | rtx addr; | |
5abc5de9 | 1182 | |
18e9d2f9 AO |
1183 | if (reg) |
1184 | addr = reg; | |
1185 | else if (size) | |
1186 | { | |
1187 | /* If we aren't using a post-increment register, use an | |
8596d0a1 | 1188 | SP offset. */ |
18e9d2f9 AO |
1189 | addr = gen_rtx_PLUS (SImode, |
1190 | stack_pointer_rtx, | |
1191 | GEN_INT (size)); | |
1192 | } | |
1193 | else | |
1194 | addr = stack_pointer_rtx; | |
1195 | ||
1196 | size += 4; | |
1197 | ||
2720cc47 NC |
1198 | emit_insn (gen_movsf (gen_rtx_REG (SFmode, i), |
1199 | gen_rtx_MEM (SFmode, addr))); | |
18e9d2f9 AO |
1200 | } |
1201 | ||
1202 | /* If we were using the restore_a1 strategy and the number of | |
1203 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1204 | to `sp', to avoid having to use `add' to adjust it. */ | |
1205 | if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255) | |
1206 | { | |
1207 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1208 | size = 0; | |
1209 | } | |
1210 | } | |
1211 | ||
5d29a95f JL |
1212 | /* Maybe cut back the stack, except for the register save area. |
1213 | ||
1214 | If the frame pointer exists, then use the frame pointer to | |
1215 | cut back the stack. | |
1216 | ||
1217 | If the stack size + register save area is more than 255 bytes, | |
1218 | then the stack must be cut back here since the size + register | |
5abc5de9 | 1219 | save size is too big for a ret/retf instruction. |
5d29a95f JL |
1220 | |
1221 | Else leave it alone, it will be cut back as part of the | |
1222 | ret/retf instruction, or there wasn't any stack to begin with. | |
1223 | ||
dab66575 | 1224 | Under no circumstances should the register save area be |
5d29a95f JL |
1225 | deallocated here, that would leave a window where an interrupt |
1226 | could occur and trash the register save area. */ | |
11bb1f11 JL |
1227 | if (frame_pointer_needed) |
1228 | { | |
11bb1f11 | 1229 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
4246e0c5 JL |
1230 | size = 0; |
1231 | } | |
ed6089d6 | 1232 | else if (size + REG_SAVE_BYTES > 255) |
4246e0c5 JL |
1233 | { |
1234 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1235 | stack_pointer_rtx, | |
1236 | GEN_INT (size))); | |
1237 | size = 0; | |
11bb1f11 | 1238 | } |
11bb1f11 | 1239 | |
ed6089d6 | 1240 | /* Adjust the stack and restore callee-saved registers, if any. */ |
6fb5fa3c DB |
1241 | if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1242 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1243 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1244 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
777fbf09 | 1245 | || frame_pointer_needed) |
ed6089d6 AO |
1246 | emit_jump_insn (gen_return_internal_regs |
1247 | (GEN_INT (size + REG_SAVE_BYTES))); | |
777fbf09 | 1248 | else |
ed6089d6 | 1249 | emit_jump_insn (gen_return_internal ()); |
11bb1f11 JL |
1250 | } |
1251 | ||
05713b80 | 1252 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
f6cd7c62 RS |
1253 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1254 | parallel. If OP is a multiple store, return a mask indicating which | |
1255 | registers it saves. Return 0 otherwise. */ | |
1256 | ||
1257 | int | |
e7ab5593 NC |
1258 | mn10300_store_multiple_operation (rtx op, |
1259 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
f6cd7c62 RS |
1260 | { |
1261 | int count; | |
1262 | int mask; | |
1263 | int i; | |
1264 | unsigned int last; | |
1265 | rtx elt; | |
1266 | ||
1267 | count = XVECLEN (op, 0); | |
1268 | if (count < 2) | |
1269 | return 0; | |
1270 | ||
1271 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1272 | elt = XVECEXP (op, 0, 0); | |
1273 | if (GET_CODE (elt) != SET | |
e7ab5593 | 1274 | || (! REG_P (SET_DEST (elt))) |
f6cd7c62 RS |
1275 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM |
1276 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1277 | return 0; | |
1278 | ||
1279 | /* Check that A is the stack pointer and B is the expected stack size. | |
1280 | For OP to match, each subsequent instruction should push a word onto | |
1281 | the stack. We therefore expect the first instruction to create | |
8596d0a1 | 1282 | COUNT-1 stack slots. */ |
f6cd7c62 | 1283 | elt = SET_SRC (elt); |
e7ab5593 | 1284 | if ((! REG_P (XEXP (elt, 0))) |
f6cd7c62 | 1285 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM |
e7ab5593 | 1286 | || (! CONST_INT_P (XEXP (elt, 1))) |
f6cd7c62 RS |
1287 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) |
1288 | return 0; | |
1289 | ||
f6cd7c62 RS |
1290 | mask = 0; |
1291 | for (i = 1; i < count; i++) | |
1292 | { | |
cc909bba RH |
1293 | /* Check that element i is a (set (mem M) R). */ |
1294 | /* ??? Validate the register order a-la mn10300_gen_multiple_store. | |
1295 | Remember: the ordering is *not* monotonic. */ | |
f6cd7c62 RS |
1296 | elt = XVECEXP (op, 0, i); |
1297 | if (GET_CODE (elt) != SET | |
e7ab5593 | 1298 | || (! MEM_P (SET_DEST (elt))) |
cc909bba | 1299 | || (! REG_P (SET_SRC (elt)))) |
f6cd7c62 RS |
1300 | return 0; |
1301 | ||
cc909bba | 1302 | /* Remember which registers are to be saved. */ |
f6cd7c62 RS |
1303 | last = REGNO (SET_SRC (elt)); |
1304 | mask |= (1 << last); | |
1305 | ||
1306 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1307 | elt = XEXP (SET_DEST (elt), 0); | |
1308 | if (GET_CODE (elt) != PLUS | |
e7ab5593 | 1309 | || (! REG_P (XEXP (elt, 0))) |
f6cd7c62 | 1310 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM |
e7ab5593 | 1311 | || (! CONST_INT_P (XEXP (elt, 1))) |
f6cd7c62 RS |
1312 | || INTVAL (XEXP (elt, 1)) != -i * 4) |
1313 | return 0; | |
1314 | } | |
1315 | ||
8596d0a1 | 1316 | /* All or none of the callee-saved extended registers must be in the set. */ |
f6cd7c62 RS |
1317 | if ((mask & 0x3c000) != 0 |
1318 | && (mask & 0x3c000) != 0x3c000) | |
1319 | return 0; | |
1320 | ||
1321 | return mask; | |
1322 | } | |
1323 | ||
f2831cc9 AS |
1324 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. */ |
1325 | ||
1326 | static reg_class_t | |
1327 | mn10300_preferred_reload_class (rtx x, reg_class_t rclass) | |
1328 | { | |
1329 | if (x == stack_pointer_rtx && rclass != SP_REGS) | |
1330 | return ADDRESS_OR_EXTENDED_REGS; | |
1331 | else if (MEM_P (x) | |
1332 | || (REG_P (x) | |
1333 | && !HARD_REGISTER_P (x)) | |
1334 | || (GET_CODE (x) == SUBREG | |
1335 | && REG_P (SUBREG_REG (x)) | |
1336 | && !HARD_REGISTER_P (SUBREG_REG (x)))) | |
1337 | return LIMIT_RELOAD_CLASS (GET_MODE (x), rclass); | |
1338 | else | |
1339 | return rclass; | |
1340 | } | |
1341 | ||
1342 | /* Implement TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */ | |
1343 | ||
1344 | static reg_class_t | |
1345 | mn10300_preferred_output_reload_class (rtx x, reg_class_t rclass) | |
1346 | { | |
1347 | if (x == stack_pointer_rtx && rclass != SP_REGS) | |
1348 | return ADDRESS_OR_EXTENDED_REGS; | |
1349 | ||
1350 | return rclass; | |
1351 | } | |
1352 | ||
11bb1f11 | 1353 | /* What (if any) secondary registers are needed to move IN with mode |
0a2aaacc | 1354 | MODE into a register in register class RCLASS. |
11bb1f11 JL |
1355 | |
1356 | We might be able to simplify this. */ | |
e7ab5593 | 1357 | |
11bb1f11 | 1358 | enum reg_class |
0a2aaacc | 1359 | mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode, |
3c4774e0 | 1360 | rtx in) |
11bb1f11 | 1361 | { |
6528281d JL |
1362 | rtx inner = in; |
1363 | ||
1364 | /* Strip off any SUBREG expressions from IN. Basically we want | |
1365 | to know if IN is a pseudo or (subreg (pseudo)) as those can | |
1366 | turn into MEMs during reload. */ | |
1367 | while (GET_CODE (inner) == SUBREG) | |
1368 | inner = SUBREG_REG (inner); | |
1369 | ||
11bb1f11 JL |
1370 | /* Memory loads less than a full word wide can't have an |
1371 | address or stack pointer destination. They must use | |
1372 | a data register as an intermediate register. */ | |
f3f63737 NC |
1373 | if ((MEM_P (in) |
1374 | || (REG_P (inner) | |
6528281d | 1375 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER)) |
11bb1f11 | 1376 | && (mode == QImode || mode == HImode) |
0a2aaacc KG |
1377 | && (rclass == ADDRESS_REGS || rclass == SP_REGS |
1378 | || rclass == SP_OR_ADDRESS_REGS)) | |
4d1a91c2 | 1379 | { |
705ac34f JL |
1380 | if (TARGET_AM33) |
1381 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
1382 | return DATA_REGS; |
1383 | } | |
11bb1f11 JL |
1384 | |
1385 | /* We can't directly load sp + const_int into a data register; | |
1386 | we must use an address register as an intermediate. */ | |
0a2aaacc KG |
1387 | if (rclass != SP_REGS |
1388 | && rclass != ADDRESS_REGS | |
1389 | && rclass != SP_OR_ADDRESS_REGS | |
1390 | && rclass != SP_OR_EXTENDED_REGS | |
1391 | && rclass != ADDRESS_OR_EXTENDED_REGS | |
1392 | && rclass != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
11bb1f11 JL |
1393 | && (in == stack_pointer_rtx |
1394 | || (GET_CODE (in) == PLUS | |
777fbf09 JL |
1395 | && (XEXP (in, 0) == stack_pointer_rtx |
1396 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
11bb1f11 JL |
1397 | return ADDRESS_REGS; |
1398 | ||
6528281d JL |
1399 | if (TARGET_AM33_2 |
1400 | && rclass == FP_REGS) | |
18e9d2f9 | 1401 | { |
6528281d JL |
1402 | /* We can't load directly into an FP register from a |
1403 | constant address. */ | |
f3f63737 | 1404 | if (MEM_P (in) |
6528281d | 1405 | && CONSTANT_ADDRESS_P (XEXP (in, 0))) |
4af476d7 | 1406 | return DATA_OR_EXTENDED_REGS; |
6528281d JL |
1407 | |
1408 | /* Handle case were a pseudo may not get a hard register | |
1409 | but has an equivalent memory location defined. */ | |
f3f63737 | 1410 | if (REG_P (inner) |
6528281d JL |
1411 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER |
1412 | && reg_equiv_mem [REGNO (inner)] | |
1413 | && CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0))) | |
4af476d7 | 1414 | return DATA_OR_EXTENDED_REGS; |
18e9d2f9 AO |
1415 | } |
1416 | ||
777fbf09 JL |
1417 | /* Otherwise assume no secondary reloads are needed. */ |
1418 | return NO_REGS; | |
1419 | } | |
1420 | ||
1421 | int | |
e7ab5593 | 1422 | mn10300_initial_offset (int from, int to) |
777fbf09 | 1423 | { |
3dbc43d1 JL |
1424 | /* The difference between the argument pointer and the frame pointer |
1425 | is the size of the callee register save area. */ | |
777fbf09 | 1426 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
11bb1f11 | 1427 | { |
6fb5fa3c DB |
1428 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1429 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1430 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1431 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
18e9d2f9 | 1432 | || fp_regs_to_save () |
777fbf09 | 1433 | || frame_pointer_needed) |
18e9d2f9 AO |
1434 | return REG_SAVE_BYTES |
1435 | + 4 * fp_regs_to_save (); | |
777fbf09 | 1436 | else |
22ef4e9b | 1437 | return 0; |
11bb1f11 JL |
1438 | } |
1439 | ||
3dbc43d1 JL |
1440 | /* The difference between the argument pointer and the stack pointer is |
1441 | the sum of the size of this function's frame, the callee register save | |
1442 | area, and the fixed stack space needed for function calls (if any). */ | |
777fbf09 JL |
1443 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
1444 | { | |
6fb5fa3c DB |
1445 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1446 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1447 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1448 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
18e9d2f9 | 1449 | || fp_regs_to_save () |
777fbf09 | 1450 | || frame_pointer_needed) |
4d1a91c2 | 1451 | return (get_frame_size () + REG_SAVE_BYTES |
18e9d2f9 | 1452 | + 4 * fp_regs_to_save () |
38173d38 JH |
1453 | + (crtl->outgoing_args_size |
1454 | ? crtl->outgoing_args_size + 4 : 0)); | |
777fbf09 | 1455 | else |
460f4b9d | 1456 | return (get_frame_size () |
38173d38 JH |
1457 | + (crtl->outgoing_args_size |
1458 | ? crtl->outgoing_args_size + 4 : 0)); | |
777fbf09 | 1459 | } |
11bb1f11 | 1460 | |
3dbc43d1 JL |
1461 | /* The difference between the frame pointer and stack pointer is the sum |
1462 | of the size of this function's frame and the fixed stack space needed | |
1463 | for function calls (if any). */ | |
777fbf09 | 1464 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
460f4b9d | 1465 | return (get_frame_size () |
38173d38 JH |
1466 | + (crtl->outgoing_args_size |
1467 | ? crtl->outgoing_args_size + 4 : 0)); | |
777fbf09 | 1468 | |
dc759020 | 1469 | gcc_unreachable (); |
11bb1f11 | 1470 | } |
22ef4e9b | 1471 | |
bd5bd7ac KH |
1472 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
1473 | ||
9024ea92 | 1474 | static bool |
586de218 | 1475 | mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
9024ea92 KH |
1476 | { |
1477 | /* Return values > 8 bytes in length in memory. */ | |
b1eb8119 DD |
1478 | return (int_size_in_bytes (type) > 8 |
1479 | || int_size_in_bytes (type) == 0 | |
1480 | || TYPE_MODE (type) == BLKmode); | |
9024ea92 KH |
1481 | } |
1482 | ||
22ef4e9b JL |
1483 | /* Flush the argument registers to the stack for a stdarg function; |
1484 | return the new argument pointer. */ | |
9024ea92 | 1485 | static rtx |
f1777882 | 1486 | mn10300_builtin_saveregs (void) |
22ef4e9b | 1487 | { |
fc2acc87 | 1488 | rtx offset, mem; |
22ef4e9b | 1489 | tree fntype = TREE_TYPE (current_function_decl); |
f38958e8 | 1490 | int argadj = ((!stdarg_p (fntype)) |
22ef4e9b | 1491 | ? UNITS_PER_WORD : 0); |
4862826d | 1492 | alias_set_type set = get_varargs_alias_set (); |
22ef4e9b JL |
1493 | |
1494 | if (argadj) | |
38173d38 | 1495 | offset = plus_constant (crtl->args.arg_offset_rtx, argadj); |
22ef4e9b | 1496 | else |
38173d38 | 1497 | offset = crtl->args.arg_offset_rtx; |
22ef4e9b | 1498 | |
38173d38 | 1499 | mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer); |
ba4828e0 | 1500 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1501 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1502 | ||
1503 | mem = gen_rtx_MEM (SImode, | |
38173d38 | 1504 | plus_constant (crtl->args.internal_arg_pointer, 4)); |
ba4828e0 | 1505 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1506 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1507 | ||
22ef4e9b | 1508 | return copy_to_reg (expand_binop (Pmode, add_optab, |
38173d38 | 1509 | crtl->args.internal_arg_pointer, |
22ef4e9b JL |
1510 | offset, 0, 0, OPTAB_LIB_WIDEN)); |
1511 | } | |
1512 | ||
d7bd8aeb | 1513 | static void |
f1777882 | 1514 | mn10300_va_start (tree valist, rtx nextarg) |
fc2acc87 | 1515 | { |
6c535c69 | 1516 | nextarg = expand_builtin_saveregs (); |
e5faf155 | 1517 | std_expand_builtin_va_start (valist, nextarg); |
fc2acc87 RH |
1518 | } |
1519 | ||
8cd5a4e0 RH |
1520 | /* Return true when a parameter should be passed by reference. */ |
1521 | ||
1522 | static bool | |
1523 | mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
586de218 | 1524 | enum machine_mode mode, const_tree type, |
8cd5a4e0 RH |
1525 | bool named ATTRIBUTE_UNUSED) |
1526 | { | |
1527 | unsigned HOST_WIDE_INT size; | |
1528 | ||
1529 | if (type) | |
1530 | size = int_size_in_bytes (type); | |
1531 | else | |
1532 | size = GET_MODE_SIZE (mode); | |
1533 | ||
b1eb8119 | 1534 | return (size > 8 || size == 0); |
8cd5a4e0 RH |
1535 | } |
1536 | ||
22ef4e9b | 1537 | /* Return an RTX to represent where a value with mode MODE will be returned |
990dc016 | 1538 | from a function. If the result is NULL_RTX, the argument is pushed. */ |
22ef4e9b | 1539 | |
ce236858 | 1540 | static rtx |
e7ab5593 | 1541 | mn10300_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
ce236858 | 1542 | const_tree type, bool named ATTRIBUTE_UNUSED) |
22ef4e9b | 1543 | { |
990dc016 | 1544 | rtx result = NULL_RTX; |
f4a88680 | 1545 | int size; |
22ef4e9b JL |
1546 | |
1547 | /* We only support using 2 data registers as argument registers. */ | |
1548 | int nregs = 2; | |
1549 | ||
1550 | /* Figure out the size of the object to be passed. */ | |
1551 | if (mode == BLKmode) | |
1552 | size = int_size_in_bytes (type); | |
1553 | else | |
1554 | size = GET_MODE_SIZE (mode); | |
1555 | ||
22ef4e9b JL |
1556 | cum->nbytes = (cum->nbytes + 3) & ~3; |
1557 | ||
1558 | /* Don't pass this arg via a register if all the argument registers | |
1559 | are used up. */ | |
1560 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
990dc016 | 1561 | return result; |
22ef4e9b JL |
1562 | |
1563 | /* Don't pass this arg via a register if it would be split between | |
1564 | registers and memory. */ | |
1565 | if (type == NULL_TREE | |
1566 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
990dc016 | 1567 | return result; |
22ef4e9b JL |
1568 | |
1569 | switch (cum->nbytes / UNITS_PER_WORD) | |
1570 | { | |
1571 | case 0: | |
990dc016 | 1572 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM); |
22ef4e9b JL |
1573 | break; |
1574 | case 1: | |
990dc016 | 1575 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1); |
22ef4e9b JL |
1576 | break; |
1577 | default: | |
990dc016 | 1578 | break; |
22ef4e9b JL |
1579 | } |
1580 | ||
1581 | return result; | |
1582 | } | |
1583 | ||
ce236858 NF |
1584 | /* Update the data in CUM to advance over an argument |
1585 | of mode MODE and data type TYPE. | |
1586 | (TYPE is null for libcalls where that information may not be available.) */ | |
1587 | ||
1588 | static void | |
1589 | mn10300_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1590 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
1591 | { | |
1592 | cum->nbytes += (mode != BLKmode | |
1593 | ? (GET_MODE_SIZE (mode) + 3) & ~3 | |
1594 | : (int_size_in_bytes (type) + 3) & ~3); | |
1595 | } | |
1596 | ||
78a52f11 RH |
1597 | /* Return the number of bytes of registers to use for an argument passed |
1598 | partially in registers and partially in memory. */ | |
22ef4e9b | 1599 | |
78a52f11 RH |
1600 | static int |
1601 | mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1602 | tree type, bool named ATTRIBUTE_UNUSED) | |
22ef4e9b | 1603 | { |
f4a88680 | 1604 | int size; |
22ef4e9b JL |
1605 | |
1606 | /* We only support using 2 data registers as argument registers. */ | |
1607 | int nregs = 2; | |
1608 | ||
1609 | /* Figure out the size of the object to be passed. */ | |
1610 | if (mode == BLKmode) | |
1611 | size = int_size_in_bytes (type); | |
1612 | else | |
1613 | size = GET_MODE_SIZE (mode); | |
1614 | ||
22ef4e9b JL |
1615 | cum->nbytes = (cum->nbytes + 3) & ~3; |
1616 | ||
1617 | /* Don't pass this arg via a register if all the argument registers | |
1618 | are used up. */ | |
1619 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1620 | return 0; | |
1621 | ||
1622 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1623 | return 0; | |
1624 | ||
1625 | /* Don't pass this arg via a register if it would be split between | |
1626 | registers and memory. */ | |
1627 | if (type == NULL_TREE | |
1628 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1629 | return 0; | |
1630 | ||
78a52f11 | 1631 | return nregs * UNITS_PER_WORD - cum->nbytes; |
22ef4e9b JL |
1632 | } |
1633 | ||
b1eb8119 DD |
1634 | /* Return the location of the function's value. This will be either |
1635 | $d0 for integer functions, $a0 for pointers, or a PARALLEL of both | |
1636 | $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that | |
1637 | we only return the PARALLEL for outgoing values; we do not want | |
1638 | callers relying on this extra copy. */ | |
1639 | ||
34732b0a AS |
1640 | static rtx |
1641 | mn10300_function_value (const_tree valtype, | |
1642 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
1643 | bool outgoing) | |
b1eb8119 DD |
1644 | { |
1645 | rtx rv; | |
1646 | enum machine_mode mode = TYPE_MODE (valtype); | |
1647 | ||
1648 | if (! POINTER_TYPE_P (valtype)) | |
1649 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1650 | else if (! TARGET_PTR_A0D0 || ! outgoing | |
e3b5732b | 1651 | || cfun->returns_struct) |
b1eb8119 DD |
1652 | return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM); |
1653 | ||
1654 | rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2)); | |
1655 | XVECEXP (rv, 0, 0) | |
1656 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1657 | gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM), | |
1658 | GEN_INT (0)); | |
5abc5de9 | 1659 | |
b1eb8119 DD |
1660 | XVECEXP (rv, 0, 1) |
1661 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1662 | gen_rtx_REG (mode, FIRST_DATA_REGNUM), | |
1663 | GEN_INT (0)); | |
1664 | return rv; | |
1665 | } | |
1666 | ||
34732b0a AS |
1667 | /* Implements TARGET_LIBCALL_VALUE. */ |
1668 | ||
1669 | static rtx | |
1670 | mn10300_libcall_value (enum machine_mode mode, | |
1671 | const_rtx fun ATTRIBUTE_UNUSED) | |
1672 | { | |
1673 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1674 | } | |
1675 | ||
1676 | /* Implements FUNCTION_VALUE_REGNO_P. */ | |
1677 | ||
1678 | bool | |
1679 | mn10300_function_value_regno_p (const unsigned int regno) | |
1680 | { | |
1681 | return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM); | |
1682 | } | |
1683 | ||
4af476d7 NC |
1684 | /* Output a compare insn. */ |
1685 | ||
1943c2c1 | 1686 | const char * |
4af476d7 | 1687 | mn10300_output_cmp (rtx operand, rtx insn) |
22ef4e9b | 1688 | { |
22ef4e9b JL |
1689 | rtx temp; |
1690 | int past_call = 0; | |
1691 | ||
1692 | /* We can save a byte if we can find a register which has the value | |
1693 | zero in it. */ | |
1694 | temp = PREV_INSN (insn); | |
74452ac3 | 1695 | while (optimize && temp) |
22ef4e9b JL |
1696 | { |
1697 | rtx set; | |
1698 | ||
1699 | /* We allow the search to go through call insns. We record | |
1700 | the fact that we've past a CALL_INSN and reject matches which | |
1701 | use call clobbered registers. */ | |
e7ab5593 NC |
1702 | if (LABEL_P (temp) |
1703 | || JUMP_P (temp) | |
22ef4e9b JL |
1704 | || GET_CODE (temp) == BARRIER) |
1705 | break; | |
1706 | ||
e7ab5593 | 1707 | if (CALL_P (temp)) |
22ef4e9b JL |
1708 | past_call = 1; |
1709 | ||
1710 | if (GET_CODE (temp) == NOTE) | |
1711 | { | |
1712 | temp = PREV_INSN (temp); | |
1713 | continue; | |
1714 | } | |
1715 | ||
8596d0a1 | 1716 | /* It must be an insn, see if it is a simple set. */ |
22ef4e9b JL |
1717 | set = single_set (temp); |
1718 | if (!set) | |
1719 | { | |
1720 | temp = PREV_INSN (temp); | |
1721 | continue; | |
1722 | } | |
1723 | ||
1724 | /* Are we setting a data register to zero (this does not win for | |
5abc5de9 | 1725 | address registers)? |
22ef4e9b JL |
1726 | |
1727 | If it's a call clobbered register, have we past a call? | |
1728 | ||
1729 | Make sure the register we find isn't the same as ourself; | |
4d1a91c2 JL |
1730 | the mn10300 can't encode that. |
1731 | ||
1732 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1733 | so the code to detect calls here isn't doing anything useful. */ | |
22ef4e9b JL |
1734 | if (REG_P (SET_DEST (set)) |
1735 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1736 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
74452ac3 JL |
1737 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1738 | == REGNO_REG_CLASS (REGNO (operand))) | |
705ac34f JL |
1739 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1740 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
5abc5de9 | 1741 | && (!past_call |
9d54866d | 1742 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
705ac34f JL |
1743 | { |
1744 | rtx xoperands[2]; | |
1745 | xoperands[0] = operand; | |
1746 | xoperands[1] = SET_DEST (set); | |
1747 | ||
1748 | output_asm_insn ("cmp %1,%0", xoperands); | |
1749 | return ""; | |
1750 | } | |
1751 | ||
1752 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1753 | && REG_P (SET_DEST (set)) | |
1754 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1755 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1756 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1757 | != REGNO_REG_CLASS (REGNO (operand))) | |
1758 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
22ef4e9b | 1759 | && REGNO (SET_DEST (set)) != REGNO (operand) |
5abc5de9 | 1760 | && (!past_call |
9d54866d | 1761 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
22ef4e9b JL |
1762 | { |
1763 | rtx xoperands[2]; | |
1764 | xoperands[0] = operand; | |
1765 | xoperands[1] = SET_DEST (set); | |
1766 | ||
1767 | output_asm_insn ("cmp %1,%0", xoperands); | |
1768 | return ""; | |
1769 | } | |
1770 | temp = PREV_INSN (temp); | |
1771 | } | |
1772 | return "cmp 0,%0"; | |
1773 | } | |
460f4b9d | 1774 | |
e9ad4573 JL |
1775 | /* Return 1 if X contains a symbolic expression. We know these |
1776 | expressions will have one of a few well defined forms, so | |
1777 | we need only check those forms. */ | |
e7ab5593 | 1778 | |
e9ad4573 | 1779 | int |
e7ab5593 NC |
1780 | mn10300_symbolic_operand (rtx op, |
1781 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
e9ad4573 JL |
1782 | { |
1783 | switch (GET_CODE (op)) | |
1784 | { | |
1785 | case SYMBOL_REF: | |
1786 | case LABEL_REF: | |
1787 | return 1; | |
1788 | case CONST: | |
1789 | op = XEXP (op, 0); | |
1790 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1791 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
f3f63737 | 1792 | && CONST_INT_P (XEXP (op, 1))); |
e9ad4573 JL |
1793 | default: |
1794 | return 0; | |
1795 | } | |
1796 | } | |
1797 | ||
1798 | /* Try machine dependent ways of modifying an illegitimate address | |
1799 | to be legitimate. If we find one, return the new valid address. | |
1800 | This macro is used in only one place: `memory_address' in explow.c. | |
1801 | ||
1802 | OLDX is the address as it was before break_out_memory_refs was called. | |
1803 | In some cases it is useful to look at this to decide what needs to be done. | |
1804 | ||
e9ad4573 JL |
1805 | Normally it is always safe for this macro to do nothing. It exists to |
1806 | recognize opportunities to optimize the output. | |
1807 | ||
1808 | But on a few ports with segmented architectures and indexed addressing | |
1809 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
e7ab5593 | 1810 | |
4af476d7 | 1811 | static rtx |
506d7b68 PB |
1812 | mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1813 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
e9ad4573 | 1814 | { |
e7ab5593 NC |
1815 | if (flag_pic && ! mn10300_legitimate_pic_operand_p (x)) |
1816 | x = mn10300_legitimize_pic_address (oldx, NULL_RTX); | |
d1776069 | 1817 | |
e9ad4573 JL |
1818 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1819 | special handling to avoid creating an indexed memory address | |
1820 | with x-100000 as the base. */ | |
1821 | if (GET_CODE (x) == PLUS | |
e7ab5593 | 1822 | && mn10300_symbolic_operand (XEXP (x, 1), VOIDmode)) |
e9ad4573 JL |
1823 | { |
1824 | /* Ugly. We modify things here so that the address offset specified | |
1825 | by the index expression is computed first, then added to x to form | |
1826 | the entire address. */ | |
1827 | ||
69bc71fa | 1828 | rtx regx1, regy1, regy2, y; |
e9ad4573 JL |
1829 | |
1830 | /* Strip off any CONST. */ | |
1831 | y = XEXP (x, 1); | |
1832 | if (GET_CODE (y) == CONST) | |
1833 | y = XEXP (y, 0); | |
1834 | ||
bf4219f0 JL |
1835 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1836 | { | |
1837 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1838 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1839 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1840 | regx1 = force_reg (Pmode, | |
e7ab5593 NC |
1841 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, |
1842 | regy2)); | |
c5c76735 | 1843 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
bf4219f0 | 1844 | } |
e9ad4573 | 1845 | } |
371036e0 | 1846 | return x; |
e9ad4573 | 1847 | } |
460ad325 | 1848 | |
d1776069 | 1849 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
8596d0a1 | 1850 | @GOTOFF in `reg'. */ |
e7ab5593 | 1851 | |
d1776069 | 1852 | rtx |
e7ab5593 | 1853 | mn10300_legitimize_pic_address (rtx orig, rtx reg) |
d1776069 | 1854 | { |
53855940 RH |
1855 | rtx x; |
1856 | ||
d1776069 AO |
1857 | if (GET_CODE (orig) == LABEL_REF |
1858 | || (GET_CODE (orig) == SYMBOL_REF | |
1859 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1860 | || ! MN10300_GLOBAL_P (orig)))) | |
1861 | { | |
53855940 | 1862 | if (reg == NULL) |
d1776069 AO |
1863 | reg = gen_reg_rtx (Pmode); |
1864 | ||
53855940 RH |
1865 | x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOTOFF); |
1866 | x = gen_rtx_CONST (SImode, x); | |
1867 | emit_move_insn (reg, x); | |
1868 | ||
1869 | x = emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx)); | |
d1776069 AO |
1870 | } |
1871 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1872 | { | |
53855940 | 1873 | if (reg == NULL) |
d1776069 AO |
1874 | reg = gen_reg_rtx (Pmode); |
1875 | ||
53855940 RH |
1876 | x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOT); |
1877 | x = gen_rtx_CONST (SImode, x); | |
1878 | x = gen_rtx_PLUS (SImode, pic_offset_table_rtx, x); | |
1879 | x = gen_const_mem (SImode, x); | |
1880 | ||
1881 | x = emit_move_insn (reg, x); | |
d1776069 | 1882 | } |
53855940 RH |
1883 | else |
1884 | return orig; | |
1885 | ||
1886 | set_unique_reg_note (x, REG_EQUAL, orig); | |
1887 | return reg; | |
d1776069 AO |
1888 | } |
1889 | ||
1890 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
4375e090 | 1891 | isn't protected by a PIC unspec; nonzero otherwise. */ |
e7ab5593 | 1892 | |
d1776069 | 1893 | int |
e7ab5593 | 1894 | mn10300_legitimate_pic_operand_p (rtx x) |
d1776069 | 1895 | { |
e7ab5593 NC |
1896 | const char *fmt; |
1897 | int i; | |
d1776069 AO |
1898 | |
1899 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1900 | return 0; | |
1901 | ||
1902 | if (GET_CODE (x) == UNSPEC | |
1903 | && (XINT (x, 1) == UNSPEC_PIC | |
1904 | || XINT (x, 1) == UNSPEC_GOT | |
1905 | || XINT (x, 1) == UNSPEC_GOTOFF | |
d4e2d7d2 RS |
1906 | || XINT (x, 1) == UNSPEC_PLT |
1907 | || XINT (x, 1) == UNSPEC_GOTSYM_OFF)) | |
d1776069 AO |
1908 | return 1; |
1909 | ||
d1776069 AO |
1910 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
1911 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1912 | { | |
1913 | if (fmt[i] == 'E') | |
1914 | { | |
4af476d7 | 1915 | int j; |
d1776069 AO |
1916 | |
1917 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
e7ab5593 | 1918 | if (! mn10300_legitimate_pic_operand_p (XVECEXP (x, i, j))) |
d1776069 AO |
1919 | return 0; |
1920 | } | |
e7ab5593 NC |
1921 | else if (fmt[i] == 'e' |
1922 | && ! mn10300_legitimate_pic_operand_p (XEXP (x, i))) | |
d1776069 AO |
1923 | return 0; |
1924 | } | |
1925 | ||
1926 | return 1; | |
1927 | } | |
1928 | ||
e733134f | 1929 | /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is |
c6c3dba9 PB |
1930 | legitimate, and FALSE otherwise. |
1931 | ||
1932 | On the mn10300, the value in the address register must be | |
1933 | in the same memory space/segment as the effective address. | |
1934 | ||
1935 | This is problematical for reload since it does not understand | |
1936 | that base+index != index+base in a memory reference. | |
1937 | ||
1938 | Note it is still possible to use reg+reg addressing modes, | |
1939 | it's just much more difficult. For a discussion of a possible | |
1940 | workaround and solution, see the comments in pa.c before the | |
1941 | function record_unscaled_index_insn_codes. */ | |
1942 | ||
4af476d7 | 1943 | static bool |
c6c3dba9 | 1944 | mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) |
e733134f AO |
1945 | { |
1946 | if (CONSTANT_ADDRESS_P (x) | |
e7ab5593 | 1947 | && (! flag_pic || mn10300_legitimate_pic_operand_p (x))) |
e733134f AO |
1948 | return TRUE; |
1949 | ||
1950 | if (RTX_OK_FOR_BASE_P (x, strict)) | |
1951 | return TRUE; | |
1952 | ||
1953 | if (TARGET_AM33 | |
1954 | && GET_CODE (x) == POST_INC | |
1955 | && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict) | |
1956 | && (mode == SImode || mode == SFmode || mode == HImode)) | |
1957 | return TRUE; | |
1958 | ||
1959 | if (GET_CODE (x) == PLUS) | |
1960 | { | |
1961 | rtx base = 0, index = 0; | |
1962 | ||
1963 | if (REG_P (XEXP (x, 0)) | |
1964 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict)) | |
1965 | { | |
1966 | base = XEXP (x, 0); | |
1967 | index = XEXP (x, 1); | |
1968 | } | |
1969 | ||
1970 | if (REG_P (XEXP (x, 1)) | |
1971 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict)) | |
1972 | { | |
1973 | base = XEXP (x, 1); | |
1974 | index = XEXP (x, 0); | |
1975 | } | |
1976 | ||
1977 | if (base != 0 && index != 0) | |
1978 | { | |
f3f63737 | 1979 | if (CONST_INT_P (index)) |
e733134f AO |
1980 | return TRUE; |
1981 | if (GET_CODE (index) == CONST | |
5542b23d | 1982 | && GET_CODE (XEXP (index, 0)) != PLUS |
e733134f | 1983 | && (! flag_pic |
e7ab5593 | 1984 | || (mn10300_legitimate_pic_operand_p (index) |
4af476d7 | 1985 | && GET_MODE_SIZE (mode) == 4))) |
e733134f AO |
1986 | return TRUE; |
1987 | } | |
1988 | } | |
1989 | ||
1990 | return FALSE; | |
1991 | } | |
1992 | ||
4af476d7 NC |
1993 | /* Used by LEGITIMATE_CONSTANT_P(). Returns TRUE if X is a valid |
1994 | constant. Note that some "constants" aren't valid, such as TLS | |
1995 | symbols and unconverted GOT-based references, so we eliminate | |
1996 | those here. */ | |
1997 | ||
1998 | bool | |
1999 | mn10300_legitimate_constant_p (rtx x) | |
2000 | { | |
2001 | switch (GET_CODE (x)) | |
2002 | { | |
2003 | case CONST: | |
2004 | x = XEXP (x, 0); | |
2005 | ||
2006 | if (GET_CODE (x) == PLUS) | |
2007 | { | |
e7ab5593 | 2008 | if (! CONST_INT_P (XEXP (x, 1))) |
4af476d7 NC |
2009 | return false; |
2010 | x = XEXP (x, 0); | |
2011 | } | |
2012 | ||
2013 | /* Only some unspecs are valid as "constants". */ | |
2014 | if (GET_CODE (x) == UNSPEC) | |
2015 | { | |
4af476d7 NC |
2016 | switch (XINT (x, 1)) |
2017 | { | |
2018 | case UNSPEC_INT_LABEL: | |
2019 | case UNSPEC_PIC: | |
2020 | case UNSPEC_GOT: | |
2021 | case UNSPEC_GOTOFF: | |
2022 | case UNSPEC_PLT: | |
2023 | return true; | |
2024 | default: | |
2025 | return false; | |
2026 | } | |
2027 | } | |
2028 | ||
2029 | /* We must have drilled down to a symbol. */ | |
e7ab5593 | 2030 | if (! mn10300_symbolic_operand (x, Pmode)) |
4af476d7 NC |
2031 | return false; |
2032 | break; | |
2033 | ||
2034 | default: | |
2035 | break; | |
2036 | } | |
2037 | ||
2038 | return true; | |
2039 | } | |
2040 | ||
126b1483 RH |
2041 | /* Undo pic address legitimization for the benefit of debug info. */ |
2042 | ||
2043 | static rtx | |
2044 | mn10300_delegitimize_address (rtx orig_x) | |
2045 | { | |
2046 | rtx x = orig_x, ret, addend = NULL; | |
2047 | bool need_mem; | |
2048 | ||
2049 | if (MEM_P (x)) | |
2050 | x = XEXP (x, 0); | |
2051 | if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode) | |
2052 | return orig_x; | |
2053 | ||
2054 | if (XEXP (x, 0) == pic_offset_table_rtx) | |
2055 | ; | |
2056 | /* With the REG+REG addressing of AM33, var-tracking can re-assemble | |
2057 | some odd-looking "addresses" that were never valid in the first place. | |
2058 | We need to look harder to avoid warnings being emitted. */ | |
2059 | else if (GET_CODE (XEXP (x, 0)) == PLUS) | |
2060 | { | |
2061 | rtx x0 = XEXP (x, 0); | |
2062 | rtx x00 = XEXP (x0, 0); | |
2063 | rtx x01 = XEXP (x0, 1); | |
2064 | ||
2065 | if (x00 == pic_offset_table_rtx) | |
2066 | addend = x01; | |
2067 | else if (x01 == pic_offset_table_rtx) | |
2068 | addend = x00; | |
2069 | else | |
2070 | return orig_x; | |
2071 | ||
2072 | } | |
2073 | else | |
2074 | return orig_x; | |
2075 | x = XEXP (x, 1); | |
2076 | ||
2077 | if (GET_CODE (x) != CONST) | |
2078 | return orig_x; | |
2079 | x = XEXP (x, 0); | |
2080 | if (GET_CODE (x) != UNSPEC) | |
2081 | return orig_x; | |
2082 | ||
2083 | ret = XVECEXP (x, 0, 0); | |
2084 | if (XINT (x, 1) == UNSPEC_GOTOFF) | |
2085 | need_mem = false; | |
2086 | else if (XINT (x, 1) == UNSPEC_GOT) | |
2087 | need_mem = true; | |
2088 | else | |
2089 | return orig_x; | |
2090 | ||
2091 | gcc_assert (GET_CODE (ret) == SYMBOL_REF); | |
2092 | if (need_mem != MEM_P (orig_x)) | |
2093 | return orig_x; | |
2094 | if (need_mem && addend) | |
2095 | return orig_x; | |
2096 | if (addend) | |
2097 | ret = gen_rtx_PLUS (Pmode, addend, ret); | |
2098 | return ret; | |
2099 | } | |
2100 | ||
72d6e3c5 RH |
2101 | /* For addresses, costs are relative to "MOV (Rm),Rn". For AM33 this is |
2102 | the 3-byte fully general instruction; for MN103 this is the 2-byte form | |
2103 | with an address register. */ | |
2104 | ||
dcefdf67 | 2105 | static int |
72d6e3c5 | 2106 | mn10300_address_cost (rtx x, bool speed) |
460ad325 | 2107 | { |
72d6e3c5 RH |
2108 | HOST_WIDE_INT i; |
2109 | rtx base, index; | |
2110 | ||
460ad325 AO |
2111 | switch (GET_CODE (x)) |
2112 | { | |
72d6e3c5 RH |
2113 | case CONST: |
2114 | case SYMBOL_REF: | |
2115 | case LABEL_REF: | |
2116 | /* We assume all of these require a 32-bit constant, even though | |
2117 | some symbol and label references can be relaxed. */ | |
2118 | return speed ? 1 : 4; | |
2119 | ||
460ad325 | 2120 | case REG: |
72d6e3c5 RH |
2121 | case SUBREG: |
2122 | case POST_INC: | |
2123 | return 0; | |
2124 | ||
2125 | case POST_MODIFY: | |
2126 | /* Assume any symbolic offset is a 32-bit constant. */ | |
2127 | i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678); | |
2128 | if (IN_RANGE (i, -128, 127)) | |
2129 | return speed ? 0 : 1; | |
2130 | if (speed) | |
2131 | return 1; | |
2132 | if (IN_RANGE (i, -0x800000, 0x7fffff)) | |
2133 | return 3; | |
2134 | return 4; | |
2135 | ||
2136 | case PLUS: | |
2137 | base = XEXP (x, 0); | |
2138 | index = XEXP (x, 1); | |
2139 | if (register_operand (index, SImode)) | |
460ad325 | 2140 | { |
72d6e3c5 RH |
2141 | /* Attempt to minimize the number of registers in the address. |
2142 | This is similar to what other ports do. */ | |
2143 | if (register_operand (base, SImode)) | |
2144 | return 1; | |
460ad325 | 2145 | |
72d6e3c5 RH |
2146 | base = XEXP (x, 1); |
2147 | index = XEXP (x, 0); | |
2148 | } | |
460ad325 | 2149 | |
72d6e3c5 RH |
2150 | /* Assume any symbolic offset is a 32-bit constant. */ |
2151 | i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678); | |
2152 | if (IN_RANGE (i, -128, 127)) | |
2153 | return speed ? 0 : 1; | |
2154 | if (IN_RANGE (i, -32768, 32767)) | |
2155 | return speed ? 0 : 2; | |
2156 | return speed ? 2 : 6; | |
460ad325 | 2157 | |
72d6e3c5 RH |
2158 | default: |
2159 | return rtx_cost (x, MEM, speed); | |
2160 | } | |
2161 | } | |
460ad325 | 2162 | |
72d6e3c5 | 2163 | /* Implement the TARGET_REGISTER_MOVE_COST hook. |
460ad325 | 2164 | |
72d6e3c5 RH |
2165 | Recall that the base value of 2 is required by assumptions elsewhere |
2166 | in the body of the compiler, and that cost 2 is special-cased as an | |
2167 | early exit from reload meaning no work is required. */ | |
460ad325 | 2168 | |
72d6e3c5 RH |
2169 | static int |
2170 | mn10300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
2171 | reg_class_t ifrom, reg_class_t ito) | |
2172 | { | |
2173 | enum reg_class from = (enum reg_class) ifrom; | |
2174 | enum reg_class to = (enum reg_class) ito; | |
2175 | enum reg_class scratch, test; | |
2176 | ||
2177 | /* Simplify the following code by unifying the fp register classes. */ | |
2178 | if (to == FP_ACC_REGS) | |
2179 | to = FP_REGS; | |
2180 | if (from == FP_ACC_REGS) | |
2181 | from = FP_REGS; | |
2182 | ||
2183 | /* Diagnose invalid moves by costing them as two moves. */ | |
2184 | ||
2185 | scratch = NO_REGS; | |
2186 | test = from; | |
2187 | if (to == SP_REGS) | |
2188 | scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS); | |
2189 | else if (to == FP_REGS && to != from) | |
2190 | scratch = GENERAL_REGS; | |
2191 | else | |
2192 | { | |
2193 | test = to; | |
2194 | if (from == SP_REGS) | |
2195 | scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS); | |
2196 | else if (from == FP_REGS && to != from) | |
2197 | scratch = GENERAL_REGS; | |
2198 | } | |
2199 | if (scratch != NO_REGS && !reg_class_subset_p (test, scratch)) | |
2200 | return (mn10300_register_move_cost (VOIDmode, from, scratch) | |
2201 | + mn10300_register_move_cost (VOIDmode, scratch, to)); | |
460ad325 | 2202 | |
72d6e3c5 | 2203 | /* From here on, all we need consider are legal combinations. */ |
460ad325 | 2204 | |
72d6e3c5 RH |
2205 | if (optimize_size) |
2206 | { | |
2207 | /* The scale here is bytes * 2. */ | |
460ad325 | 2208 | |
72d6e3c5 RH |
2209 | if (from == to && (to == ADDRESS_REGS || to == DATA_REGS)) |
2210 | return 2; | |
460ad325 | 2211 | |
72d6e3c5 RH |
2212 | if (from == SP_REGS) |
2213 | return (to == ADDRESS_REGS ? 2 : 6); | |
2214 | ||
2215 | /* For MN103, all remaining legal moves are two bytes. */ | |
2216 | if (TARGET_AM33) | |
2217 | return 4; | |
2218 | ||
2219 | if (to == SP_REGS) | |
2220 | return (from == ADDRESS_REGS ? 4 : 6); | |
2221 | ||
2222 | if ((from == ADDRESS_REGS || from == DATA_REGS) | |
2223 | && (to == ADDRESS_REGS || to == DATA_REGS)) | |
2224 | return 4; | |
2225 | ||
2226 | if (to == EXTENDED_REGS) | |
2227 | return (to == from ? 6 : 4); | |
460ad325 | 2228 | |
72d6e3c5 RH |
2229 | /* What's left are SP_REGS, FP_REGS, or combinations of the above. */ |
2230 | return 6; | |
2231 | } | |
2232 | else | |
2233 | { | |
2234 | /* The scale here is cycles * 2. */ | |
2235 | ||
2236 | if (to == FP_REGS) | |
2237 | return 8; | |
2238 | if (from == FP_REGS) | |
2239 | return 4; | |
2240 | ||
2241 | /* All legal moves between integral registers are single cycle. */ | |
2242 | return 2; | |
460ad325 AO |
2243 | } |
2244 | } | |
3c50106f | 2245 | |
72d6e3c5 RH |
2246 | /* Implement the TARGET_MEMORY_MOVE_COST hook. |
2247 | ||
2248 | Given lack of the form of the address, this must be speed-relative, | |
2249 | though we should never be less expensive than a size-relative register | |
2250 | move cost above. This is not a problem. */ | |
2251 | ||
dcefdf67 | 2252 | static int |
72d6e3c5 RH |
2253 | mn10300_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, |
2254 | reg_class_t iclass, bool in ATTRIBUTE_UNUSED) | |
dcefdf67 | 2255 | { |
72d6e3c5 RH |
2256 | enum reg_class rclass = (enum reg_class) iclass; |
2257 | ||
2258 | if (rclass == FP_REGS) | |
2259 | return 8; | |
2260 | return 6; | |
dcefdf67 RH |
2261 | } |
2262 | ||
72d6e3c5 RH |
2263 | /* Implement the TARGET_RTX_COSTS hook. |
2264 | ||
2265 | Speed-relative costs are relative to COSTS_N_INSNS, which is intended | |
2266 | to represent cycles. Size-relative costs are in bytes. */ | |
2267 | ||
3c50106f | 2268 | static bool |
72d6e3c5 | 2269 | mn10300_rtx_costs (rtx x, int code, int outer_code, int *ptotal, bool speed) |
3c50106f | 2270 | { |
72d6e3c5 RH |
2271 | /* This value is used for SYMBOL_REF etc where we want to pretend |
2272 | we have a full 32-bit constant. */ | |
2273 | HOST_WIDE_INT i = 0x12345678; | |
2274 | int total; | |
2275 | ||
3c50106f RH |
2276 | switch (code) |
2277 | { | |
2278 | case CONST_INT: | |
72d6e3c5 RH |
2279 | i = INTVAL (x); |
2280 | do_int_costs: | |
2281 | if (speed) | |
2282 | { | |
2283 | if (outer_code == SET) | |
2284 | { | |
2285 | /* 16-bit integer loads have latency 1, 32-bit loads 2. */ | |
2286 | if (IN_RANGE (i, -32768, 32767)) | |
2287 | total = COSTS_N_INSNS (1); | |
2288 | else | |
2289 | total = COSTS_N_INSNS (2); | |
2290 | } | |
2291 | else | |
2292 | { | |
2293 | /* 16-bit integer operands don't affect latency; | |
2294 | 24-bit and 32-bit operands add a cycle. */ | |
2295 | if (IN_RANGE (i, -32768, 32767)) | |
2296 | total = 0; | |
2297 | else | |
2298 | total = COSTS_N_INSNS (1); | |
2299 | } | |
2300 | } | |
3c50106f | 2301 | else |
72d6e3c5 RH |
2302 | { |
2303 | if (outer_code == SET) | |
2304 | { | |
2305 | if (i == 0) | |
2306 | total = 1; | |
2307 | else if (IN_RANGE (i, -128, 127)) | |
2308 | total = 2; | |
2309 | else if (IN_RANGE (i, -32768, 32767)) | |
2310 | total = 3; | |
2311 | else | |
2312 | total = 6; | |
2313 | } | |
2314 | else | |
2315 | { | |
2316 | /* Reference here is ADD An,Dn, vs ADD imm,Dn. */ | |
2317 | if (IN_RANGE (i, -128, 127)) | |
2318 | total = 0; | |
2319 | else if (IN_RANGE (i, -32768, 32767)) | |
2320 | total = 2; | |
2321 | else if (TARGET_AM33 && IN_RANGE (i, -0x01000000, 0x00ffffff)) | |
2322 | total = 3; | |
2323 | else | |
2324 | total = 4; | |
2325 | } | |
2326 | } | |
2327 | goto alldone; | |
3c50106f RH |
2328 | |
2329 | case CONST: | |
2330 | case LABEL_REF: | |
2331 | case SYMBOL_REF: | |
3c50106f | 2332 | case CONST_DOUBLE: |
72d6e3c5 RH |
2333 | /* We assume all of these require a 32-bit constant, even though |
2334 | some symbol and label references can be relaxed. */ | |
2335 | goto do_int_costs; | |
f90b7a5a | 2336 | |
72d6e3c5 RH |
2337 | case UNSPEC: |
2338 | switch (XINT (x, 1)) | |
2339 | { | |
2340 | case UNSPEC_PIC: | |
2341 | case UNSPEC_GOT: | |
2342 | case UNSPEC_GOTOFF: | |
2343 | case UNSPEC_PLT: | |
2344 | case UNSPEC_GOTSYM_OFF: | |
2345 | /* The PIC unspecs also resolve to a 32-bit constant. */ | |
2346 | goto do_int_costs; | |
3c50106f | 2347 | |
72d6e3c5 RH |
2348 | default: |
2349 | /* Assume any non-listed unspec is some sort of arithmetic. */ | |
2350 | goto do_arith_costs; | |
2351 | } | |
fe7496dd | 2352 | |
72d6e3c5 RH |
2353 | case PLUS: |
2354 | /* Notice the size difference of INC and INC4. */ | |
2355 | if (!speed && outer_code == SET && CONST_INT_P (XEXP (x, 1))) | |
2356 | { | |
2357 | i = INTVAL (XEXP (x, 1)); | |
2358 | if (i == 1 || i == 4) | |
2359 | { | |
2360 | total = 1 + rtx_cost (XEXP (x, 0), PLUS, speed); | |
2361 | goto alldone; | |
2362 | } | |
2363 | } | |
2364 | goto do_arith_costs; | |
2365 | ||
2366 | case MINUS: | |
2367 | case AND: | |
2368 | case IOR: | |
2369 | case XOR: | |
2370 | case NOT: | |
2371 | case NEG: | |
2372 | case ZERO_EXTEND: | |
2373 | case SIGN_EXTEND: | |
2374 | case COMPARE: | |
2375 | case BSWAP: | |
2376 | case CLZ: | |
2377 | do_arith_costs: | |
2378 | total = (speed ? COSTS_N_INSNS (1) : 2); | |
2379 | break; | |
fe7496dd | 2380 | |
72d6e3c5 RH |
2381 | case ASHIFT: |
2382 | /* Notice the size difference of ASL2 and variants. */ | |
2383 | if (!speed && CONST_INT_P (XEXP (x, 1))) | |
2384 | switch (INTVAL (XEXP (x, 1))) | |
2385 | { | |
2386 | case 1: | |
2387 | case 2: | |
2388 | total = 1; | |
2389 | goto alldone; | |
2390 | case 3: | |
2391 | case 4: | |
2392 | total = 2; | |
2393 | goto alldone; | |
2394 | } | |
2395 | /* FALLTHRU */ | |
fe7496dd | 2396 | |
72d6e3c5 RH |
2397 | case ASHIFTRT: |
2398 | case LSHIFTRT: | |
2399 | total = (speed ? COSTS_N_INSNS (1) : 3); | |
2400 | goto alldone; | |
fe7496dd | 2401 | |
72d6e3c5 RH |
2402 | case MULT: |
2403 | total = (speed ? COSTS_N_INSNS (3) : 2); | |
fe7496dd | 2404 | break; |
5abc5de9 | 2405 | |
72d6e3c5 RH |
2406 | case DIV: |
2407 | case UDIV: | |
2408 | case MOD: | |
2409 | case UMOD: | |
2410 | total = (speed ? COSTS_N_INSNS (39) | |
2411 | /* Include space to load+retrieve MDR. */ | |
2412 | : code == MOD || code == UMOD ? 6 : 4); | |
fe7496dd | 2413 | break; |
5abc5de9 | 2414 | |
72d6e3c5 RH |
2415 | case MEM: |
2416 | total = mn10300_address_cost (XEXP (x, 0), speed); | |
2417 | if (speed) | |
2418 | total = COSTS_N_INSNS (2 + total); | |
2419 | goto alldone; | |
2420 | ||
fe7496dd | 2421 | default: |
72d6e3c5 RH |
2422 | /* Probably not implemented. Assume external call. */ |
2423 | total = (speed ? COSTS_N_INSNS (10) : 7); | |
2424 | break; | |
fe7496dd AO |
2425 | } |
2426 | ||
72d6e3c5 RH |
2427 | *ptotal = total; |
2428 | return false; | |
2429 | ||
2430 | alldone: | |
2431 | *ptotal = total; | |
2432 | return true; | |
fe7496dd | 2433 | } |
72d6e3c5 | 2434 | |
d1776069 AO |
2435 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2436 | may access it using GOTOFF instead of GOT. */ | |
2437 | ||
2438 | static void | |
3bc5e4ef | 2439 | mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED) |
d1776069 AO |
2440 | { |
2441 | rtx symbol; | |
2442 | ||
e7ab5593 | 2443 | if (! MEM_P (rtl)) |
d1776069 AO |
2444 | return; |
2445 | symbol = XEXP (rtl, 0); | |
2446 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2447 | return; | |
2448 | ||
2449 | if (flag_pic) | |
2450 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2451 | } | |
e6ff3083 AS |
2452 | |
2453 | /* Dispatch tables on the mn10300 are extremely expensive in terms of code | |
2454 | and readonly data size. So we crank up the case threshold value to | |
2455 | encourage a series of if/else comparisons to implement many small switch | |
2456 | statements. In theory, this value could be increased much more if we | |
2457 | were solely optimizing for space, but we keep it "reasonable" to avoid | |
2458 | serious code efficiency lossage. */ | |
2459 | ||
4af476d7 NC |
2460 | static unsigned int |
2461 | mn10300_case_values_threshold (void) | |
e6ff3083 AS |
2462 | { |
2463 | return 6; | |
2464 | } | |
bdeb5f0c | 2465 | |
bdeb5f0c RH |
2466 | /* Worker function for TARGET_TRAMPOLINE_INIT. */ |
2467 | ||
2468 | static void | |
2469 | mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2470 | { | |
d6a3e264 RH |
2471 | rtx mem, disp, fnaddr = XEXP (DECL_RTL (fndecl), 0); |
2472 | ||
2473 | /* This is a strict alignment target, which means that we play | |
2474 | some games to make sure that the locations at which we need | |
2475 | to store <chain> and <disp> wind up at aligned addresses. | |
2476 | ||
2477 | 0x28 0x00 add 0,d0 | |
2478 | 0xfc 0xdd mov chain,a1 | |
2479 | <chain> | |
2480 | 0xf8 0xed 0x00 btst 0,d1 | |
2481 | 0xdc jmp fnaddr | |
2482 | <disp> | |
2483 | ||
2484 | Note that the two extra insns are effectively nops; they | |
2485 | clobber the flags but do not affect the contents of D0 or D1. */ | |
bdeb5f0c | 2486 | |
d6a3e264 RH |
2487 | disp = expand_binop (SImode, sub_optab, fnaddr, |
2488 | plus_constant (XEXP (m_tramp, 0), 11), | |
2489 | NULL_RTX, 1, OPTAB_DIRECT); | |
bdeb5f0c | 2490 | |
d6a3e264 RH |
2491 | mem = adjust_address (m_tramp, SImode, 0); |
2492 | emit_move_insn (mem, gen_int_mode (0xddfc0028, SImode)); | |
2493 | mem = adjust_address (m_tramp, SImode, 4); | |
bdeb5f0c | 2494 | emit_move_insn (mem, chain_value); |
d6a3e264 RH |
2495 | mem = adjust_address (m_tramp, SImode, 8); |
2496 | emit_move_insn (mem, gen_int_mode (0xdc00edf8, SImode)); | |
2497 | mem = adjust_address (m_tramp, SImode, 12); | |
2498 | emit_move_insn (mem, disp); | |
bdeb5f0c | 2499 | } |
990dc016 NC |
2500 | |
2501 | /* Output the assembler code for a C++ thunk function. | |
2502 | THUNK_DECL is the declaration for the thunk function itself, FUNCTION | |
2503 | is the decl for the target function. DELTA is an immediate constant | |
2504 | offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero | |
2505 | the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be | |
2506 | additionally added to THIS. Finally jump to the entry point of | |
2507 | FUNCTION. */ | |
2508 | ||
2509 | static void | |
2510 | mn10300_asm_output_mi_thunk (FILE * file, | |
2511 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2512 | HOST_WIDE_INT delta, | |
2513 | HOST_WIDE_INT vcall_offset, | |
2514 | tree function) | |
2515 | { | |
2516 | const char * _this; | |
2517 | ||
2518 | /* Get the register holding the THIS parameter. Handle the case | |
2519 | where there is a hidden first argument for a returned structure. */ | |
2520 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
2521 | _this = reg_names [FIRST_ARGUMENT_REGNUM + 1]; | |
2522 | else | |
2523 | _this = reg_names [FIRST_ARGUMENT_REGNUM]; | |
2524 | ||
2525 | fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START); | |
2526 | ||
2527 | if (delta) | |
2528 | fprintf (file, "\tadd %d, %s\n", (int) delta, _this); | |
2529 | ||
2530 | if (vcall_offset) | |
2531 | { | |
2532 | const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1]; | |
2533 | ||
2534 | fprintf (file, "\tmov %s, %s\n", _this, scratch); | |
2535 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2536 | fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch); | |
2537 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2538 | fprintf (file, "\tadd %s, %s\n", scratch, _this); | |
2539 | } | |
2540 | ||
2541 | fputs ("\tjmp ", file); | |
2542 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2543 | putc ('\n', file); | |
2544 | } | |
2545 | ||
2546 | /* Return true if mn10300_output_mi_thunk would be able to output the | |
2547 | assembler code for the thunk function specified by the arguments | |
2548 | it is passed, and false otherwise. */ | |
2549 | ||
2550 | static bool | |
2551 | mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2552 | HOST_WIDE_INT delta ATTRIBUTE_UNUSED, | |
2553 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2554 | const_tree function ATTRIBUTE_UNUSED) | |
2555 | { | |
2556 | return true; | |
2557 | } | |
4af476d7 NC |
2558 | |
2559 | bool | |
2560 | mn10300_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) | |
2561 | { | |
2562 | if (REGNO_REG_CLASS (regno) == FP_REGS | |
2563 | || REGNO_REG_CLASS (regno) == FP_ACC_REGS) | |
2564 | /* Do not store integer values in FP registers. */ | |
2565 | return GET_MODE_CLASS (mode) == MODE_FLOAT && ((regno & 1) == 0); | |
2566 | ||
2567 | if (((regno) & 1) == 0 || GET_MODE_SIZE (mode) == 4) | |
2568 | return true; | |
2569 | ||
2570 | if (REGNO_REG_CLASS (regno) == DATA_REGS | |
2571 | || (TARGET_AM33 && REGNO_REG_CLASS (regno) == ADDRESS_REGS) | |
2572 | || REGNO_REG_CLASS (regno) == EXTENDED_REGS) | |
2573 | return GET_MODE_SIZE (mode) <= 4; | |
2574 | ||
2575 | return false; | |
2576 | } | |
2577 | ||
2578 | bool | |
2579 | mn10300_modes_tieable (enum machine_mode mode1, enum machine_mode mode2) | |
2580 | { | |
2581 | if (GET_MODE_CLASS (mode1) == MODE_FLOAT | |
2582 | && GET_MODE_CLASS (mode2) != MODE_FLOAT) | |
2583 | return false; | |
2584 | ||
2585 | if (GET_MODE_CLASS (mode2) == MODE_FLOAT | |
2586 | && GET_MODE_CLASS (mode1) != MODE_FLOAT) | |
2587 | return false; | |
2588 | ||
2589 | if (TARGET_AM33 | |
2590 | || mode1 == mode2 | |
2591 | || (GET_MODE_SIZE (mode1) <= 4 && GET_MODE_SIZE (mode2) <= 4)) | |
2592 | return true; | |
2593 | ||
2594 | return false; | |
2595 | } | |
2596 | ||
2597 | enum machine_mode | |
2598 | mn10300_select_cc_mode (rtx x) | |
2599 | { | |
2600 | return (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) ? CC_FLOATmode : CCmode; | |
2601 | } | |
f3f63737 NC |
2602 | |
2603 | static inline bool | |
2604 | is_load_insn (rtx insn) | |
2605 | { | |
2606 | if (GET_CODE (PATTERN (insn)) != SET) | |
2607 | return false; | |
2608 | ||
2609 | return MEM_P (SET_SRC (PATTERN (insn))); | |
2610 | } | |
2611 | ||
2612 | static inline bool | |
2613 | is_store_insn (rtx insn) | |
2614 | { | |
2615 | if (GET_CODE (PATTERN (insn)) != SET) | |
2616 | return false; | |
2617 | ||
2618 | return MEM_P (SET_DEST (PATTERN (insn))); | |
2619 | } | |
2620 | ||
2621 | /* Update scheduling costs for situations that cannot be | |
2622 | described using the attributes and DFA machinery. | |
2623 | DEP is the insn being scheduled. | |
2624 | INSN is the previous insn. | |
2625 | COST is the current cycle cost for DEP. */ | |
2626 | ||
2627 | static int | |
2628 | mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost) | |
2629 | { | |
2630 | int timings = get_attr_timings (insn); | |
2631 | ||
2632 | if (!TARGET_AM33) | |
2633 | return 1; | |
2634 | ||
2635 | if (GET_CODE (insn) == PARALLEL) | |
2636 | insn = XVECEXP (insn, 0, 0); | |
2637 | ||
2638 | if (GET_CODE (dep) == PARALLEL) | |
2639 | dep = XVECEXP (dep, 0, 0); | |
2640 | ||
2641 | /* For the AM34 a load instruction that follows a | |
2642 | store instruction incurs an extra cycle of delay. */ | |
2643 | if (mn10300_tune_cpu == PROCESSOR_AM34 | |
2644 | && is_load_insn (dep) | |
2645 | && is_store_insn (insn)) | |
2646 | cost += 1; | |
2647 | ||
2648 | /* For the AM34 a non-store, non-branch FPU insn that follows | |
2649 | another FPU insn incurs a one cycle throughput increase. */ | |
2650 | else if (mn10300_tune_cpu == PROCESSOR_AM34 | |
2651 | && ! is_store_insn (insn) | |
2652 | && ! JUMP_P (insn) | |
2653 | && GET_CODE (PATTERN (dep)) == SET | |
2654 | && GET_CODE (PATTERN (insn)) == SET | |
2655 | && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) == MODE_FLOAT | |
2656 | && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT) | |
2657 | cost += 1; | |
2658 | ||
2659 | /* Resolve the conflict described in section 1-7-4 of | |
2660 | Chapter 3 of the MN103E Series Instruction Manual | |
2661 | where it says: | |
2662 | ||
2663 | "When the preceeding instruction is a CPU load or | |
2664 | store instruction, a following FPU instruction | |
2665 | cannot be executed until the CPU completes the | |
2666 | latency period even though there are no register | |
2667 | or flag dependencies between them." */ | |
2668 | ||
2669 | /* Only the AM33-2 (and later) CPUs have FPU instructions. */ | |
2670 | if (! TARGET_AM33_2) | |
2671 | return cost; | |
2672 | ||
2673 | /* If a data dependence already exists then the cost is correct. */ | |
2674 | if (REG_NOTE_KIND (link) == 0) | |
2675 | return cost; | |
2676 | ||
2677 | /* Check that the instruction about to scheduled is an FPU instruction. */ | |
2678 | if (GET_CODE (PATTERN (dep)) != SET) | |
2679 | return cost; | |
2680 | ||
2681 | if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) != MODE_FLOAT) | |
2682 | return cost; | |
2683 | ||
2684 | /* Now check to see if the previous instruction is a load or store. */ | |
2685 | if (! is_load_insn (insn) && ! is_store_insn (insn)) | |
2686 | return cost; | |
2687 | ||
2688 | /* XXX: Verify: The text of 1-7-4 implies that the restriction | |
2689 | only applies when an INTEGER load/store preceeds an FPU | |
2690 | instruction, but is this true ? For now we assume that it is. */ | |
2691 | if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT) | |
2692 | return cost; | |
2693 | ||
2694 | /* Extract the latency value from the timings attribute. */ | |
2695 | return timings < 100 ? (timings % 10) : (timings % 100); | |
2696 | } | |
5efd84c5 NF |
2697 | |
2698 | static void | |
2699 | mn10300_conditional_register_usage (void) | |
2700 | { | |
2701 | unsigned int i; | |
2702 | ||
2703 | if (!TARGET_AM33) | |
2704 | { | |
2705 | for (i = FIRST_EXTENDED_REGNUM; | |
2706 | i <= LAST_EXTENDED_REGNUM; i++) | |
2707 | fixed_regs[i] = call_used_regs[i] = 1; | |
2708 | } | |
2709 | if (!TARGET_AM33_2) | |
2710 | { | |
2711 | for (i = FIRST_FP_REGNUM; | |
2712 | i <= LAST_FP_REGNUM; i++) | |
2713 | fixed_regs[i] = call_used_regs[i] = 1; | |
2714 | } | |
2715 | if (flag_pic) | |
2716 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = | |
2717 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
2718 | } | |
a49b692a RH |
2719 | |
2720 | /* Worker function for TARGET_MD_ASM_CLOBBERS. | |
2721 | We do this in the mn10300 backend to maintain source compatibility | |
2722 | with the old cc0-based compiler. */ | |
2723 | ||
2724 | static tree | |
2725 | mn10300_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED, | |
2726 | tree inputs ATTRIBUTE_UNUSED, | |
2727 | tree clobbers) | |
2728 | { | |
2729 | clobbers = tree_cons (NULL_TREE, build_string (5, "EPSW"), | |
2730 | clobbers); | |
2731 | return clobbers; | |
2732 | } | |
4af476d7 | 2733 | \f |
e7ab5593 NC |
2734 | /* Initialize the GCC target structure. */ |
2735 | ||
2736 | #undef TARGET_EXCEPT_UNWIND_INFO | |
2737 | #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info | |
2738 | ||
2739 | #undef TARGET_ASM_ALIGNED_HI_OP | |
2740 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
2741 | ||
2742 | #undef TARGET_LEGITIMIZE_ADDRESS | |
2743 | #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address | |
2744 | ||
72d6e3c5 RH |
2745 | #undef TARGET_ADDRESS_COST |
2746 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
2747 | #undef TARGET_REGISTER_MOVE_COST | |
2748 | #define TARGET_REGISTER_MOVE_COST mn10300_register_move_cost | |
2749 | #undef TARGET_MEMORY_MOVE_COST | |
2750 | #define TARGET_MEMORY_MOVE_COST mn10300_memory_move_cost | |
e7ab5593 NC |
2751 | #undef TARGET_RTX_COSTS |
2752 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
e7ab5593 NC |
2753 | |
2754 | #undef TARGET_ASM_FILE_START | |
2755 | #define TARGET_ASM_FILE_START mn10300_file_start | |
2756 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
2757 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
2758 | ||
535bd17c AS |
2759 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
2760 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA mn10300_asm_output_addr_const_extra | |
2761 | ||
e7ab5593 NC |
2762 | #undef TARGET_DEFAULT_TARGET_FLAGS |
2763 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0 | |
2764 | #undef TARGET_HANDLE_OPTION | |
2765 | #define TARGET_HANDLE_OPTION mn10300_handle_option | |
2766 | #undef TARGET_OPTION_OVERRIDE | |
2767 | #define TARGET_OPTION_OVERRIDE mn10300_option_override | |
3020190e JM |
2768 | #undef TARGET_OPTION_OPTIMIZATION_TABLE |
2769 | #define TARGET_OPTION_OPTIMIZATION_TABLE mn10300_option_optimization_table | |
e7ab5593 NC |
2770 | |
2771 | #undef TARGET_ENCODE_SECTION_INFO | |
2772 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
2773 | ||
2774 | #undef TARGET_PROMOTE_PROTOTYPES | |
2775 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
2776 | #undef TARGET_RETURN_IN_MEMORY | |
2777 | #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory | |
2778 | #undef TARGET_PASS_BY_REFERENCE | |
2779 | #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference | |
2780 | #undef TARGET_CALLEE_COPIES | |
2781 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
2782 | #undef TARGET_ARG_PARTIAL_BYTES | |
2783 | #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes | |
ce236858 NF |
2784 | #undef TARGET_FUNCTION_ARG |
2785 | #define TARGET_FUNCTION_ARG mn10300_function_arg | |
2786 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
2787 | #define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance | |
e7ab5593 NC |
2788 | |
2789 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
2790 | #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs | |
2791 | #undef TARGET_EXPAND_BUILTIN_VA_START | |
2792 | #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start | |
2793 | ||
2794 | #undef TARGET_CASE_VALUES_THRESHOLD | |
2795 | #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold | |
2796 | ||
2797 | #undef TARGET_LEGITIMATE_ADDRESS_P | |
2798 | #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p | |
126b1483 RH |
2799 | #undef TARGET_DELEGITIMIZE_ADDRESS |
2800 | #define TARGET_DELEGITIMIZE_ADDRESS mn10300_delegitimize_address | |
e7ab5593 | 2801 | |
f2831cc9 AS |
2802 | #undef TARGET_PREFERRED_RELOAD_CLASS |
2803 | #define TARGET_PREFERRED_RELOAD_CLASS mn10300_preferred_reload_class | |
2804 | #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS | |
2805 | #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS mn10300_preferred_output_reload_class | |
2806 | ||
e7ab5593 NC |
2807 | #undef TARGET_TRAMPOLINE_INIT |
2808 | #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init | |
2809 | ||
2810 | #undef TARGET_FUNCTION_VALUE | |
2811 | #define TARGET_FUNCTION_VALUE mn10300_function_value | |
2812 | #undef TARGET_LIBCALL_VALUE | |
2813 | #define TARGET_LIBCALL_VALUE mn10300_libcall_value | |
2814 | ||
2815 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
2816 | #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk | |
2817 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
2818 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk | |
2819 | ||
f3f63737 NC |
2820 | #undef TARGET_SCHED_ADJUST_COST |
2821 | #define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost | |
2822 | ||
5efd84c5 NF |
2823 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
2824 | #define TARGET_CONDITIONAL_REGISTER_USAGE mn10300_conditional_register_usage | |
2825 | ||
a49b692a RH |
2826 | #undef TARGET_MD_ASM_CLOBBERS |
2827 | #define TARGET_MD_ASM_CLOBBERS mn10300_md_asm_clobbers | |
2828 | ||
e7ab5593 | 2829 | struct gcc_target targetm = TARGET_INITIALIZER; |