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11bb1f11 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
6fb5fa3c | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, |
c75c517d | 3 | 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. |
11bb1f11 JL |
4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
e7ab5593 | 6 | This file is part of GCC. |
11bb1f11 | 7 | |
e7ab5593 NC |
8 | GCC is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
11bb1f11 | 12 | |
e7ab5593 NC |
13 | GCC is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
11bb1f11 | 17 | |
e7ab5593 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
11bb1f11 | 21 | |
11bb1f11 | 22 | #include "config.h" |
c5c76735 | 23 | #include "system.h" |
4977bab6 ZW |
24 | #include "coretypes.h" |
25 | #include "tm.h" | |
11bb1f11 | 26 | #include "rtl.h" |
bf6bb899 | 27 | #include "tree.h" |
11bb1f11 JL |
28 | #include "regs.h" |
29 | #include "hard-reg-set.h" | |
11bb1f11 JL |
30 | #include "insn-config.h" |
31 | #include "conditions.h" | |
11bb1f11 JL |
32 | #include "output.h" |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
6528281d | 36 | #include "reload.h" |
11bb1f11 | 37 | #include "expr.h" |
e78d8e51 | 38 | #include "optabs.h" |
bf6bb899 | 39 | #include "function.h" |
11bb1f11 | 40 | #include "obstack.h" |
718f9c0f | 41 | #include "diagnostic-core.h" |
69bc71fa | 42 | #include "tm_p.h" |
672a6f42 NB |
43 | #include "target.h" |
44 | #include "target-def.h" | |
4af476d7 | 45 | #include "df.h" |
11bb1f11 | 46 | |
d1776069 AO |
47 | /* This is used by GOTaddr2picreg to uniquely identify |
48 | UNSPEC_INT_LABELs. */ | |
49 | int mn10300_unspec_int_label_counter; | |
50 | ||
2beef00e AO |
51 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
52 | names are not prefixed by underscores, to tell whether to prefix a | |
53 | label with a plus sign or not, so that the assembler can tell | |
54 | symbol names from register names. */ | |
55 | int mn10300_protect_label; | |
56 | ||
13dd556c RS |
57 | /* The selected processor. */ |
58 | enum processor_type mn10300_processor = PROCESSOR_DEFAULT; | |
59 | ||
f3f63737 NC |
60 | /* Processor type to select for tuning. */ |
61 | static const char * mn10300_tune_string = NULL; | |
62 | ||
63 | /* Selected processor type for tuning. */ | |
64 | enum processor_type mn10300_tune_cpu = PROCESSOR_DEFAULT; | |
65 | ||
4d1a91c2 JL |
66 | /* The size of the callee register save area. Right now we save everything |
67 | on entry since it costs us nothing in code size. It does cost us from a | |
68 | speed standpoint, so we want to optimize this sooner or later. */ | |
e7ab5593 NC |
69 | #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \ |
70 | + 4 * df_regs_ever_live_p (3) \ | |
71 | + 4 * df_regs_ever_live_p (6) \ | |
72 | + 4 * df_regs_ever_live_p (7) \ | |
73 | + 16 * (df_regs_ever_live_p (14) \ | |
74 | || df_regs_ever_live_p (15) \ | |
75 | || df_regs_ever_live_p (16) \ | |
76 | || df_regs_ever_live_p (17))) | |
990dc016 | 77 | |
3020190e JM |
78 | /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ |
79 | static const struct default_options mn10300_option_optimization_table[] = | |
80 | { | |
81 | { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, | |
82 | { OPT_LEVELS_NONE, 0, NULL, 0 } | |
83 | }; | |
672a6f42 | 84 | \f |
13dd556c RS |
85 | /* Implement TARGET_HANDLE_OPTION. */ |
86 | ||
87 | static bool | |
88 | mn10300_handle_option (size_t code, | |
89 | const char *arg ATTRIBUTE_UNUSED, | |
90 | int value) | |
91 | { | |
92 | switch (code) | |
93 | { | |
94 | case OPT_mam33: | |
95 | mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300; | |
96 | return true; | |
f3f63737 | 97 | |
13dd556c RS |
98 | case OPT_mam33_2: |
99 | mn10300_processor = (value | |
100 | ? PROCESSOR_AM33_2 | |
101 | : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT)); | |
102 | return true; | |
f3f63737 NC |
103 | |
104 | case OPT_mam34: | |
105 | mn10300_processor = (value ? PROCESSOR_AM34 : PROCESSOR_DEFAULT); | |
106 | return true; | |
107 | ||
108 | case OPT_mtune_: | |
109 | mn10300_tune_string = arg; | |
110 | return true; | |
111 | ||
13dd556c RS |
112 | default: |
113 | return true; | |
114 | } | |
115 | } | |
116 | ||
c5387660 | 117 | /* Implement TARGET_OPTION_OVERRIDE. */ |
13dd556c | 118 | |
c5387660 JM |
119 | static void |
120 | mn10300_option_override (void) | |
13dd556c RS |
121 | { |
122 | if (TARGET_AM33) | |
123 | target_flags &= ~MASK_MULT_BUG; | |
f3f63737 NC |
124 | else |
125 | { | |
126 | /* Disable scheduling for the MN10300 as we do | |
127 | not have timing information available for it. */ | |
128 | flag_schedule_insns = 0; | |
129 | flag_schedule_insns_after_reload = 0; | |
130 | } | |
131 | ||
132 | if (mn10300_tune_string) | |
133 | { | |
134 | if (strcasecmp (mn10300_tune_string, "mn10300") == 0) | |
135 | mn10300_tune_cpu = PROCESSOR_MN10300; | |
136 | else if (strcasecmp (mn10300_tune_string, "am33") == 0) | |
137 | mn10300_tune_cpu = PROCESSOR_AM33; | |
138 | else if (strcasecmp (mn10300_tune_string, "am33-2") == 0) | |
139 | mn10300_tune_cpu = PROCESSOR_AM33_2; | |
140 | else if (strcasecmp (mn10300_tune_string, "am34") == 0) | |
141 | mn10300_tune_cpu = PROCESSOR_AM34; | |
142 | else | |
143 | error ("-mtune= expects mn10300, am33, am33-2, or am34"); | |
144 | } | |
13dd556c RS |
145 | } |
146 | ||
1bc7c5b6 | 147 | static void |
f1777882 | 148 | mn10300_file_start (void) |
11bb1f11 | 149 | { |
1bc7c5b6 | 150 | default_file_start (); |
705ac34f | 151 | |
18e9d2f9 AO |
152 | if (TARGET_AM33_2) |
153 | fprintf (asm_out_file, "\t.am33_2\n"); | |
154 | else if (TARGET_AM33) | |
1bc7c5b6 | 155 | fprintf (asm_out_file, "\t.am33\n"); |
11bb1f11 JL |
156 | } |
157 | \f | |
11bb1f11 JL |
158 | /* Print operand X using operand code CODE to assembly language output file |
159 | FILE. */ | |
160 | ||
161 | void | |
e7ab5593 | 162 | mn10300_print_operand (FILE *file, rtx x, int code) |
11bb1f11 JL |
163 | { |
164 | switch (code) | |
165 | { | |
166 | case 'b': | |
167 | case 'B': | |
4af476d7 | 168 | if (GET_MODE (XEXP (x, 0)) == CC_FLOATmode) |
18e9d2f9 AO |
169 | { |
170 | switch (code == 'b' ? GET_CODE (x) | |
171 | : reverse_condition_maybe_unordered (GET_CODE (x))) | |
172 | { | |
173 | case NE: | |
174 | fprintf (file, "ne"); | |
175 | break; | |
176 | case EQ: | |
177 | fprintf (file, "eq"); | |
178 | break; | |
179 | case GE: | |
180 | fprintf (file, "ge"); | |
181 | break; | |
182 | case GT: | |
183 | fprintf (file, "gt"); | |
184 | break; | |
185 | case LE: | |
186 | fprintf (file, "le"); | |
187 | break; | |
188 | case LT: | |
189 | fprintf (file, "lt"); | |
190 | break; | |
191 | case ORDERED: | |
192 | fprintf (file, "lge"); | |
193 | break; | |
194 | case UNORDERED: | |
195 | fprintf (file, "uo"); | |
196 | break; | |
197 | case LTGT: | |
198 | fprintf (file, "lg"); | |
199 | break; | |
200 | case UNEQ: | |
201 | fprintf (file, "ue"); | |
202 | break; | |
203 | case UNGE: | |
204 | fprintf (file, "uge"); | |
205 | break; | |
206 | case UNGT: | |
207 | fprintf (file, "ug"); | |
208 | break; | |
209 | case UNLE: | |
210 | fprintf (file, "ule"); | |
211 | break; | |
212 | case UNLT: | |
213 | fprintf (file, "ul"); | |
214 | break; | |
215 | default: | |
dc759020 | 216 | gcc_unreachable (); |
18e9d2f9 AO |
217 | } |
218 | break; | |
219 | } | |
11bb1f11 JL |
220 | /* These are normal and reversed branches. */ |
221 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
222 | { | |
223 | case NE: | |
224 | fprintf (file, "ne"); | |
225 | break; | |
226 | case EQ: | |
227 | fprintf (file, "eq"); | |
228 | break; | |
229 | case GE: | |
230 | fprintf (file, "ge"); | |
231 | break; | |
232 | case GT: | |
233 | fprintf (file, "gt"); | |
234 | break; | |
235 | case LE: | |
236 | fprintf (file, "le"); | |
237 | break; | |
238 | case LT: | |
239 | fprintf (file, "lt"); | |
240 | break; | |
241 | case GEU: | |
242 | fprintf (file, "cc"); | |
243 | break; | |
244 | case GTU: | |
245 | fprintf (file, "hi"); | |
246 | break; | |
247 | case LEU: | |
248 | fprintf (file, "ls"); | |
249 | break; | |
250 | case LTU: | |
251 | fprintf (file, "cs"); | |
252 | break; | |
253 | default: | |
dc759020 | 254 | gcc_unreachable (); |
11bb1f11 JL |
255 | } |
256 | break; | |
257 | case 'C': | |
258 | /* This is used for the operand to a call instruction; | |
259 | if it's a REG, enclose it in parens, else output | |
260 | the operand normally. */ | |
e7ab5593 | 261 | if (REG_P (x)) |
11bb1f11 JL |
262 | { |
263 | fputc ('(', file); | |
e7ab5593 | 264 | mn10300_print_operand (file, x, 0); |
11bb1f11 JL |
265 | fputc (')', file); |
266 | } | |
267 | else | |
e7ab5593 | 268 | mn10300_print_operand (file, x, 0); |
11bb1f11 | 269 | break; |
5abc5de9 | 270 | |
18e9d2f9 AO |
271 | case 'D': |
272 | switch (GET_CODE (x)) | |
273 | { | |
274 | case MEM: | |
275 | fputc ('(', file); | |
276 | output_address (XEXP (x, 0)); | |
277 | fputc (')', file); | |
278 | break; | |
279 | ||
280 | case REG: | |
281 | fprintf (file, "fd%d", REGNO (x) - 18); | |
282 | break; | |
283 | ||
284 | default: | |
dc759020 | 285 | gcc_unreachable (); |
18e9d2f9 AO |
286 | } |
287 | break; | |
288 | ||
38c37a0e JL |
289 | /* These are the least significant word in a 64bit value. */ |
290 | case 'L': | |
291 | switch (GET_CODE (x)) | |
292 | { | |
293 | case MEM: | |
294 | fputc ('(', file); | |
295 | output_address (XEXP (x, 0)); | |
296 | fputc (')', file); | |
297 | break; | |
298 | ||
299 | case REG: | |
300 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
301 | break; | |
302 | ||
303 | case SUBREG: | |
ddef6bc7 | 304 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
38c37a0e JL |
305 | break; |
306 | ||
307 | case CONST_DOUBLE: | |
308 | { | |
309 | long val[2]; | |
310 | REAL_VALUE_TYPE rv; | |
311 | ||
312 | switch (GET_MODE (x)) | |
313 | { | |
314 | case DFmode: | |
315 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
316 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 317 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
318 | break;; |
319 | case SFmode: | |
320 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
321 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
cf31fafa | 322 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
323 | break;; |
324 | case VOIDmode: | |
325 | case DImode: | |
e7ab5593 NC |
326 | mn10300_print_operand_address (file, |
327 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
38c37a0e | 328 | break; |
69bc71fa KG |
329 | default: |
330 | break; | |
38c37a0e JL |
331 | } |
332 | break; | |
333 | } | |
334 | ||
335 | case CONST_INT: | |
212bc5fa AO |
336 | { |
337 | rtx low, high; | |
338 | split_double (x, &low, &high); | |
339 | fprintf (file, "%ld", (long)INTVAL (low)); | |
340 | break; | |
341 | } | |
38c37a0e JL |
342 | |
343 | default: | |
dc759020 | 344 | gcc_unreachable (); |
38c37a0e JL |
345 | } |
346 | break; | |
347 | ||
348 | /* Similarly, but for the most significant word. */ | |
349 | case 'H': | |
350 | switch (GET_CODE (x)) | |
351 | { | |
352 | case MEM: | |
353 | fputc ('(', file); | |
b72f00af | 354 | x = adjust_address (x, SImode, 4); |
38c37a0e JL |
355 | output_address (XEXP (x, 0)); |
356 | fputc (')', file); | |
357 | break; | |
358 | ||
359 | case REG: | |
360 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
361 | break; | |
362 | ||
363 | case SUBREG: | |
ddef6bc7 | 364 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
38c37a0e JL |
365 | break; |
366 | ||
367 | case CONST_DOUBLE: | |
368 | { | |
369 | long val[2]; | |
370 | REAL_VALUE_TYPE rv; | |
371 | ||
372 | switch (GET_MODE (x)) | |
373 | { | |
374 | case DFmode: | |
375 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
376 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 377 | fprintf (file, "0x%lx", val[1]); |
38c37a0e JL |
378 | break;; |
379 | case SFmode: | |
dc759020 | 380 | gcc_unreachable (); |
38c37a0e JL |
381 | case VOIDmode: |
382 | case DImode: | |
e7ab5593 NC |
383 | mn10300_print_operand_address (file, |
384 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
38c37a0e | 385 | break; |
69bc71fa KG |
386 | default: |
387 | break; | |
38c37a0e JL |
388 | } |
389 | break; | |
390 | } | |
391 | ||
392 | case CONST_INT: | |
212bc5fa AO |
393 | { |
394 | rtx low, high; | |
395 | split_double (x, &low, &high); | |
396 | fprintf (file, "%ld", (long)INTVAL (high)); | |
397 | break; | |
398 | } | |
399 | ||
38c37a0e | 400 | default: |
dc759020 | 401 | gcc_unreachable (); |
38c37a0e JL |
402 | } |
403 | break; | |
404 | ||
405 | case 'A': | |
406 | fputc ('(', file); | |
f3f63737 | 407 | if (REG_P (XEXP (x, 0))) |
a556fd39 | 408 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx)); |
38c37a0e JL |
409 | else |
410 | output_address (XEXP (x, 0)); | |
411 | fputc (')', file); | |
412 | break; | |
413 | ||
6fafc523 | 414 | case 'N': |
dc759020 | 415 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
a58be199 AO |
416 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); |
417 | break; | |
418 | ||
419 | case 'U': | |
dc759020 | 420 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
a58be199 | 421 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); |
6fafc523 JL |
422 | break; |
423 | ||
576e5acc JL |
424 | /* For shift counts. The hardware ignores the upper bits of |
425 | any immediate, but the assembler will flag an out of range | |
426 | shift count as an error. So we mask off the high bits | |
427 | of the immediate here. */ | |
428 | case 'S': | |
f3f63737 | 429 | if (CONST_INT_P (x)) |
576e5acc | 430 | { |
a58be199 | 431 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
576e5acc JL |
432 | break; |
433 | } | |
434 | /* FALL THROUGH */ | |
435 | ||
11bb1f11 JL |
436 | default: |
437 | switch (GET_CODE (x)) | |
438 | { | |
439 | case MEM: | |
440 | fputc ('(', file); | |
441 | output_address (XEXP (x, 0)); | |
442 | fputc (')', file); | |
443 | break; | |
444 | ||
38c37a0e JL |
445 | case PLUS: |
446 | output_address (x); | |
447 | break; | |
448 | ||
11bb1f11 JL |
449 | case REG: |
450 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
451 | break; | |
452 | ||
453 | case SUBREG: | |
ddef6bc7 | 454 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
11bb1f11 JL |
455 | break; |
456 | ||
38c37a0e JL |
457 | /* This will only be single precision.... */ |
458 | case CONST_DOUBLE: | |
459 | { | |
460 | unsigned long val; | |
461 | REAL_VALUE_TYPE rv; | |
462 | ||
463 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
464 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
cf31fafa | 465 | fprintf (file, "0x%lx", val); |
38c37a0e JL |
466 | break; |
467 | } | |
468 | ||
11bb1f11 JL |
469 | case CONST_INT: |
470 | case SYMBOL_REF: | |
471 | case CONST: | |
472 | case LABEL_REF: | |
473 | case CODE_LABEL: | |
d1776069 | 474 | case UNSPEC: |
e7ab5593 | 475 | mn10300_print_operand_address (file, x); |
11bb1f11 JL |
476 | break; |
477 | default: | |
dc759020 | 478 | gcc_unreachable (); |
11bb1f11 JL |
479 | } |
480 | break; | |
481 | } | |
482 | } | |
483 | ||
484 | /* Output assembly language output for the address ADDR to FILE. */ | |
485 | ||
486 | void | |
e7ab5593 | 487 | mn10300_print_operand_address (FILE *file, rtx addr) |
11bb1f11 JL |
488 | { |
489 | switch (GET_CODE (addr)) | |
490 | { | |
705ac34f | 491 | case POST_INC: |
e7ab5593 | 492 | mn10300_print_operand_address (file, XEXP (addr, 0)); |
705ac34f JL |
493 | fputc ('+', file); |
494 | break; | |
11bb1f11 | 495 | case REG: |
e7ab5593 | 496 | mn10300_print_operand (file, addr, 0); |
11bb1f11 JL |
497 | break; |
498 | case PLUS: | |
499 | { | |
500 | rtx base, index; | |
501 | if (REG_P (XEXP (addr, 0)) | |
502 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
503 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
504 | else if (REG_P (XEXP (addr, 1)) | |
505 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
506 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
507 | else | |
dc759020 | 508 | gcc_unreachable (); |
e7ab5593 | 509 | mn10300_print_operand (file, index, 0); |
11bb1f11 | 510 | fputc (',', file); |
e7ab5593 | 511 | mn10300_print_operand (file, base, 0);; |
11bb1f11 JL |
512 | break; |
513 | } | |
514 | case SYMBOL_REF: | |
515 | output_addr_const (file, addr); | |
516 | break; | |
517 | default: | |
518 | output_addr_const (file, addr); | |
519 | break; | |
520 | } | |
521 | } | |
522 | ||
535bd17c AS |
523 | /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. |
524 | ||
525 | Used for PIC-specific UNSPECs. */ | |
526 | ||
527 | static bool | |
528 | mn10300_asm_output_addr_const_extra (FILE *file, rtx x) | |
529 | { | |
530 | if (GET_CODE (x) == UNSPEC) | |
531 | { | |
532 | switch (XINT (x, 1)) | |
533 | { | |
534 | case UNSPEC_INT_LABEL: | |
535 | asm_fprintf (file, ".%LLIL" HOST_WIDE_INT_PRINT_DEC, | |
536 | INTVAL (XVECEXP (x, 0, 0))); | |
537 | break; | |
538 | case UNSPEC_PIC: | |
539 | /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ | |
540 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
541 | break; | |
542 | case UNSPEC_GOT: | |
543 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
544 | fputs ("@GOT", file); | |
545 | break; | |
546 | case UNSPEC_GOTOFF: | |
547 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
548 | fputs ("@GOTOFF", file); | |
549 | break; | |
550 | case UNSPEC_PLT: | |
551 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
552 | fputs ("@PLT", file); | |
553 | break; | |
554 | case UNSPEC_GOTSYM_OFF: | |
555 | assemble_name (file, GOT_SYMBOL_NAME); | |
556 | fputs ("-(", file); | |
557 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
558 | fputs ("-.)", file); | |
559 | break; | |
560 | default: | |
561 | return false; | |
562 | } | |
563 | return true; | |
564 | } | |
565 | else | |
566 | return false; | |
567 | } | |
568 | ||
18e9d2f9 AO |
569 | /* Count the number of FP registers that have to be saved. */ |
570 | static int | |
f1777882 | 571 | fp_regs_to_save (void) |
18e9d2f9 AO |
572 | { |
573 | int i, n = 0; | |
574 | ||
575 | if (! TARGET_AM33_2) | |
576 | return 0; | |
577 | ||
578 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 579 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
18e9d2f9 AO |
580 | ++n; |
581 | ||
582 | return n; | |
583 | } | |
584 | ||
f6cd7c62 RS |
585 | /* Print a set of registers in the format required by "movm" and "ret". |
586 | Register K is saved if bit K of MASK is set. The data and address | |
587 | registers can be stored individually, but the extended registers cannot. | |
9f5ed61a | 588 | We assume that the mask already takes that into account. For instance, |
8596d0a1 | 589 | bits 14 to 17 must have the same value. */ |
f6cd7c62 RS |
590 | |
591 | void | |
f1777882 | 592 | mn10300_print_reg_list (FILE *file, int mask) |
f6cd7c62 RS |
593 | { |
594 | int need_comma; | |
595 | int i; | |
596 | ||
597 | need_comma = 0; | |
598 | fputc ('[', file); | |
599 | ||
600 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
601 | if ((mask & (1 << i)) != 0) | |
602 | { | |
603 | if (need_comma) | |
604 | fputc (',', file); | |
605 | fputs (reg_names [i], file); | |
606 | need_comma = 1; | |
607 | } | |
608 | ||
609 | if ((mask & 0x3c000) != 0) | |
610 | { | |
dc759020 | 611 | gcc_assert ((mask & 0x3c000) == 0x3c000); |
f6cd7c62 RS |
612 | if (need_comma) |
613 | fputc (',', file); | |
614 | fputs ("exreg1", file); | |
615 | need_comma = 1; | |
616 | } | |
617 | ||
618 | fputc (']', file); | |
619 | } | |
620 | ||
38c37a0e | 621 | int |
e7ab5593 | 622 | mn10300_can_use_return_insn (void) |
38c37a0e | 623 | { |
460f4b9d | 624 | /* size includes the fixed stack space needed for function calls. */ |
38173d38 | 625 | int size = get_frame_size () + crtl->outgoing_args_size; |
460f4b9d JL |
626 | |
627 | /* And space for the return pointer. */ | |
38173d38 | 628 | size += crtl->outgoing_args_size ? 4 : 0; |
38c37a0e JL |
629 | |
630 | return (reload_completed | |
631 | && size == 0 | |
6fb5fa3c DB |
632 | && !df_regs_ever_live_p (2) |
633 | && !df_regs_ever_live_p (3) | |
634 | && !df_regs_ever_live_p (6) | |
635 | && !df_regs_ever_live_p (7) | |
636 | && !df_regs_ever_live_p (14) | |
637 | && !df_regs_ever_live_p (15) | |
638 | && !df_regs_ever_live_p (16) | |
639 | && !df_regs_ever_live_p (17) | |
18e9d2f9 | 640 | && fp_regs_to_save () == 0 |
38c37a0e JL |
641 | && !frame_pointer_needed); |
642 | } | |
643 | ||
f6cd7c62 RS |
644 | /* Returns the set of live, callee-saved registers as a bitmask. The |
645 | callee-saved extended registers cannot be stored individually, so | |
8596d0a1 | 646 | all of them will be included in the mask if any one of them is used. */ |
f6cd7c62 RS |
647 | |
648 | int | |
f1777882 | 649 | mn10300_get_live_callee_saved_regs (void) |
f6cd7c62 RS |
650 | { |
651 | int mask; | |
652 | int i; | |
653 | ||
654 | mask = 0; | |
18e9d2f9 | 655 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
9d54866d | 656 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
f6cd7c62 RS |
657 | mask |= (1 << i); |
658 | if ((mask & 0x3c000) != 0) | |
659 | mask |= 0x3c000; | |
660 | ||
661 | return mask; | |
662 | } | |
663 | ||
2720cc47 NC |
664 | static rtx |
665 | F (rtx r) | |
666 | { | |
667 | RTX_FRAME_RELATED_P (r) = 1; | |
668 | return r; | |
669 | } | |
670 | ||
f6cd7c62 RS |
671 | /* Generate an instruction that pushes several registers onto the stack. |
672 | Register K will be saved if bit K in MASK is set. The function does | |
673 | nothing if MASK is zero. | |
674 | ||
675 | To be compatible with the "movm" instruction, the lowest-numbered | |
676 | register must be stored in the lowest slot. If MASK is the set | |
677 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
678 | instruction will have the form: | |
679 | ||
680 | (parallel | |
681 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
682 | (set (mem:SI (plus:SI (reg:SI 9) | |
683 | (const_int -1*4))) | |
684 | (reg:SI RN)) | |
685 | ... | |
686 | (set (mem:SI (plus:SI (reg:SI 9) | |
687 | (const_int -N*4))) | |
688 | (reg:SI R1))) */ | |
689 | ||
cc909bba RH |
690 | static void |
691 | mn10300_gen_multiple_store (unsigned int mask) | |
f6cd7c62 | 692 | { |
cc909bba RH |
693 | /* The order in which registers are stored, from SP-4 through SP-N*4. */ |
694 | static const unsigned int store_order[8] = { | |
695 | /* e2, e3: never saved */ | |
696 | FIRST_EXTENDED_REGNUM + 4, | |
697 | FIRST_EXTENDED_REGNUM + 5, | |
698 | FIRST_EXTENDED_REGNUM + 6, | |
699 | FIRST_EXTENDED_REGNUM + 7, | |
700 | /* e0, e1, mdrq, mcrh, mcrl, mcvf: never saved. */ | |
701 | FIRST_DATA_REGNUM + 2, | |
702 | FIRST_DATA_REGNUM + 3, | |
703 | FIRST_ADDRESS_REGNUM + 2, | |
704 | FIRST_ADDRESS_REGNUM + 3, | |
705 | /* d0, d1, a0, a1, mdr, lir, lar: never saved. */ | |
706 | }; | |
707 | ||
708 | rtx x, elts[9]; | |
709 | unsigned int i; | |
710 | int count; | |
711 | ||
712 | if (mask == 0) | |
713 | return; | |
714 | ||
715 | for (i = count = 0; i < ARRAY_SIZE(store_order); ++i) | |
f6cd7c62 | 716 | { |
cc909bba RH |
717 | unsigned regno = store_order[i]; |
718 | ||
719 | if (((mask >> regno) & 1) == 0) | |
720 | continue; | |
f6cd7c62 | 721 | |
cc909bba RH |
722 | ++count; |
723 | x = plus_constant (stack_pointer_rtx, count * -4); | |
724 | x = gen_frame_mem (SImode, x); | |
725 | x = gen_rtx_SET (VOIDmode, x, gen_rtx_REG (SImode, regno)); | |
726 | elts[count] = F(x); | |
727 | ||
728 | /* Remove the register from the mask so that... */ | |
729 | mask &= ~(1u << regno); | |
f6cd7c62 | 730 | } |
cc909bba RH |
731 | |
732 | /* ... we can make sure that we didn't try to use a register | |
733 | not listed in the store order. */ | |
734 | gcc_assert (mask == 0); | |
735 | ||
736 | /* Create the instruction that updates the stack pointer. */ | |
737 | x = plus_constant (stack_pointer_rtx, count * -4); | |
738 | x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x); | |
739 | elts[0] = F(x); | |
740 | ||
741 | /* We need one PARALLEL element to update the stack pointer and | |
742 | an additional element for each register that is stored. */ | |
743 | x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (count + 1, elts)); | |
744 | F (emit_insn (x)); | |
f6cd7c62 RS |
745 | } |
746 | ||
11bb1f11 | 747 | void |
e7ab5593 | 748 | mn10300_expand_prologue (void) |
11bb1f11 | 749 | { |
036182e7 | 750 | HOST_WIDE_INT size; |
3dbc43d1 | 751 | |
3dbc43d1 | 752 | /* SIZE includes the fixed stack space needed for function calls. */ |
38173d38 JH |
753 | size = get_frame_size () + crtl->outgoing_args_size; |
754 | size += (crtl->outgoing_args_size ? 4 : 0); | |
11bb1f11 | 755 | |
8596d0a1 | 756 | /* If we use any of the callee-saved registers, save them now. */ |
f6cd7c62 | 757 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); |
777fbf09 | 758 | |
18e9d2f9 AO |
759 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
760 | { | |
761 | int num_regs_to_save = fp_regs_to_save (), i; | |
762 | HOST_WIDE_INT xsize; | |
e7ab5593 NC |
763 | enum |
764 | { | |
765 | save_sp_merge, | |
766 | save_sp_no_merge, | |
767 | save_sp_partial_merge, | |
768 | save_a0_merge, | |
769 | save_a0_no_merge | |
770 | } strategy; | |
18e9d2f9 AO |
771 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; |
772 | rtx reg; | |
18e9d2f9 AO |
773 | |
774 | /* We have several different strategies to save FP registers. | |
775 | We can store them using SP offsets, which is beneficial if | |
776 | there are just a few registers to save, or we can use `a0' in | |
777 | post-increment mode (`a0' is the only call-clobbered address | |
778 | register that is never used to pass information to a | |
779 | function). Furthermore, if we don't need a frame pointer, we | |
780 | can merge the two SP adds into a single one, but this isn't | |
781 | always beneficial; sometimes we can just split the two adds | |
782 | so that we don't exceed a 16-bit constant size. The code | |
783 | below will select which strategy to use, so as to generate | |
784 | smallest code. Ties are broken in favor or shorter sequences | |
785 | (in terms of number of instructions). */ | |
786 | ||
787 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
788 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
789 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
790 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
f4a88680 JR |
791 | |
792 | /* We add 0 * (S) in two places to promote to the type of S, | |
793 | so that all arms of the conditional have the same type. */ | |
18e9d2f9 | 794 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ |
f4a88680 | 795 | (((S) >= (L)) ? 0 * (S) + (SIZE1) * (N) \ |
18e9d2f9 AO |
796 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ |
797 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
f4a88680 | 798 | : 0 * (S) + (ELSE)) |
18e9d2f9 AO |
799 | #define SIZE_FMOV_SP_(S,N) \ |
800 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
801 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
802 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
803 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
804 | ||
805 | /* Consider alternative save_sp_merge only if we don't need the | |
4375e090 | 806 | frame pointer and size is nonzero. */ |
18e9d2f9 AO |
807 | if (! frame_pointer_needed && size) |
808 | { | |
809 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
810 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
811 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
812 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
813 | ||
814 | if (this_strategy_size < strategy_size) | |
815 | { | |
816 | strategy = save_sp_merge; | |
817 | strategy_size = this_strategy_size; | |
818 | } | |
819 | } | |
820 | ||
821 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
822 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
823 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
824 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
825 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
826 | if (size) | |
827 | { | |
828 | /* Insn: add -size, sp. */ | |
829 | this_strategy_size += SIZE_ADD_SP (-size); | |
830 | } | |
831 | ||
832 | if (this_strategy_size < strategy_size) | |
833 | { | |
834 | strategy = save_sp_no_merge; | |
835 | strategy_size = this_strategy_size; | |
836 | } | |
837 | ||
838 | /* Consider alternative save_sp_partial_merge only if we don't | |
839 | need a frame pointer and size is reasonably large. */ | |
840 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
841 | { | |
842 | /* Insn: add -128, sp. */ | |
843 | this_strategy_size = SIZE_ADD_SP (-128); | |
844 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
845 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
846 | num_regs_to_save); | |
847 | if (size) | |
848 | { | |
849 | /* Insn: add 128-size, sp. */ | |
850 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
851 | } | |
852 | ||
853 | if (this_strategy_size < strategy_size) | |
854 | { | |
855 | strategy = save_sp_partial_merge; | |
856 | strategy_size = this_strategy_size; | |
857 | } | |
858 | } | |
859 | ||
860 | /* Consider alternative save_a0_merge only if we don't need a | |
4375e090 | 861 | frame pointer, size is nonzero and the user hasn't |
18e9d2f9 AO |
862 | changed the calling conventions of a0. */ |
863 | if (! frame_pointer_needed && size | |
9d54866d | 864 | && call_really_used_regs [FIRST_ADDRESS_REGNUM] |
18e9d2f9 AO |
865 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
866 | { | |
867 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
868 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
869 | /* Insn: mov sp, a0. */ | |
870 | this_strategy_size++; | |
871 | if (size) | |
872 | { | |
873 | /* Insn: add size, a0. */ | |
874 | this_strategy_size += SIZE_ADD_AX (size); | |
875 | } | |
876 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
877 | this_strategy_size += 3 * num_regs_to_save; | |
878 | ||
879 | if (this_strategy_size < strategy_size) | |
880 | { | |
881 | strategy = save_a0_merge; | |
882 | strategy_size = this_strategy_size; | |
883 | } | |
884 | } | |
885 | ||
886 | /* Consider alternative save_a0_no_merge if the user hasn't | |
8596d0a1 | 887 | changed the calling conventions of a0. */ |
9d54866d | 888 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM] |
18e9d2f9 AO |
889 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
890 | { | |
891 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
892 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
893 | /* Insn: mov sp, a0. */ | |
894 | this_strategy_size++; | |
895 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
896 | this_strategy_size += 3 * num_regs_to_save; | |
897 | if (size) | |
898 | { | |
899 | /* Insn: add -size, sp. */ | |
900 | this_strategy_size += SIZE_ADD_SP (-size); | |
901 | } | |
902 | ||
903 | if (this_strategy_size < strategy_size) | |
904 | { | |
905 | strategy = save_a0_no_merge; | |
906 | strategy_size = this_strategy_size; | |
907 | } | |
908 | } | |
909 | ||
910 | /* Emit the initial SP add, common to all strategies. */ | |
911 | switch (strategy) | |
912 | { | |
913 | case save_sp_no_merge: | |
914 | case save_a0_no_merge: | |
2720cc47 NC |
915 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
916 | stack_pointer_rtx, | |
917 | GEN_INT (-4 * num_regs_to_save)))); | |
18e9d2f9 AO |
918 | xsize = 0; |
919 | break; | |
920 | ||
921 | case save_sp_partial_merge: | |
2720cc47 NC |
922 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
923 | stack_pointer_rtx, | |
924 | GEN_INT (-128)))); | |
18e9d2f9 AO |
925 | xsize = 128 - 4 * num_regs_to_save; |
926 | size -= xsize; | |
927 | break; | |
928 | ||
929 | case save_sp_merge: | |
930 | case save_a0_merge: | |
2720cc47 NC |
931 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
932 | stack_pointer_rtx, | |
933 | GEN_INT (-(size + 4 * num_regs_to_save))))); | |
18e9d2f9 | 934 | /* We'll have to adjust FP register saves according to the |
8596d0a1 | 935 | frame size. */ |
18e9d2f9 AO |
936 | xsize = size; |
937 | /* Since we've already created the stack frame, don't do it | |
8596d0a1 | 938 | again at the end of the function. */ |
18e9d2f9 AO |
939 | size = 0; |
940 | break; | |
941 | ||
942 | default: | |
dc759020 | 943 | gcc_unreachable (); |
18e9d2f9 | 944 | } |
5abc5de9 | 945 | |
18e9d2f9 AO |
946 | /* Now prepare register a0, if we have decided to use it. */ |
947 | switch (strategy) | |
948 | { | |
949 | case save_sp_merge: | |
950 | case save_sp_no_merge: | |
951 | case save_sp_partial_merge: | |
952 | reg = 0; | |
953 | break; | |
954 | ||
955 | case save_a0_merge: | |
956 | case save_a0_no_merge: | |
957 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
2720cc47 | 958 | F (emit_insn (gen_movsi (reg, stack_pointer_rtx))); |
18e9d2f9 | 959 | if (xsize) |
2720cc47 | 960 | F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)))); |
18e9d2f9 AO |
961 | reg = gen_rtx_POST_INC (SImode, reg); |
962 | break; | |
5abc5de9 | 963 | |
18e9d2f9 | 964 | default: |
dc759020 | 965 | gcc_unreachable (); |
18e9d2f9 | 966 | } |
5abc5de9 | 967 | |
18e9d2f9 AO |
968 | /* Now actually save the FP registers. */ |
969 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 970 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
18e9d2f9 AO |
971 | { |
972 | rtx addr; | |
973 | ||
974 | if (reg) | |
975 | addr = reg; | |
976 | else | |
977 | { | |
978 | /* If we aren't using `a0', use an SP offset. */ | |
979 | if (xsize) | |
980 | { | |
981 | addr = gen_rtx_PLUS (SImode, | |
982 | stack_pointer_rtx, | |
983 | GEN_INT (xsize)); | |
984 | } | |
985 | else | |
986 | addr = stack_pointer_rtx; | |
5abc5de9 | 987 | |
18e9d2f9 AO |
988 | xsize += 4; |
989 | } | |
990 | ||
2720cc47 NC |
991 | F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr), |
992 | gen_rtx_REG (SFmode, i)))); | |
18e9d2f9 AO |
993 | } |
994 | } | |
995 | ||
777fbf09 | 996 | /* Now put the frame pointer into the frame pointer register. */ |
11bb1f11 | 997 | if (frame_pointer_needed) |
2720cc47 | 998 | F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx)); |
11bb1f11 | 999 | |
777fbf09 | 1000 | /* Allocate stack for this frame. */ |
11bb1f11 | 1001 | if (size) |
2720cc47 NC |
1002 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
1003 | stack_pointer_rtx, | |
1004 | GEN_INT (-size)))); | |
1005 | ||
6fb5fa3c DB |
1006 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
1007 | emit_insn (gen_GOTaddr2picreg ()); | |
11bb1f11 JL |
1008 | } |
1009 | ||
1010 | void | |
e7ab5593 | 1011 | mn10300_expand_epilogue (void) |
11bb1f11 | 1012 | { |
036182e7 | 1013 | HOST_WIDE_INT size; |
3dbc43d1 | 1014 | |
3dbc43d1 | 1015 | /* SIZE includes the fixed stack space needed for function calls. */ |
38173d38 JH |
1016 | size = get_frame_size () + crtl->outgoing_args_size; |
1017 | size += (crtl->outgoing_args_size ? 4 : 0); | |
4af476d7 | 1018 | |
18e9d2f9 AO |
1019 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
1020 | { | |
1021 | int num_regs_to_save = fp_regs_to_save (), i; | |
1022 | rtx reg = 0; | |
1023 | ||
1024 | /* We have several options to restore FP registers. We could | |
1025 | load them from SP offsets, but, if there are enough FP | |
1026 | registers to restore, we win if we use a post-increment | |
1027 | addressing mode. */ | |
1028 | ||
1029 | /* If we have a frame pointer, it's the best option, because we | |
1030 | already know it has the value we want. */ | |
1031 | if (frame_pointer_needed) | |
1032 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
1033 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
1034 | it's never used for return values. But only do so if it's | |
1035 | smaller than using SP offsets. */ | |
1036 | else | |
1037 | { | |
1038 | enum { restore_sp_post_adjust, | |
1039 | restore_sp_pre_adjust, | |
1040 | restore_sp_partial_adjust, | |
1041 | restore_a1 } strategy; | |
1042 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
1043 | ||
1044 | /* Consider using sp offsets before adjusting sp. */ | |
1045 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1046 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
1047 | /* If size is too large, we'll have to adjust SP with an | |
1048 | add. */ | |
1049 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1050 | { | |
1051 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
1052 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
1053 | } | |
1054 | /* If we don't have to restore any non-FP registers, | |
1055 | we'll be able to save one byte by using rets. */ | |
1056 | if (! REG_SAVE_BYTES) | |
1057 | this_strategy_size--; | |
1058 | ||
1059 | if (this_strategy_size < strategy_size) | |
1060 | { | |
1061 | strategy = restore_sp_post_adjust; | |
1062 | strategy_size = this_strategy_size; | |
1063 | } | |
1064 | ||
1065 | /* Consider using sp offsets after adjusting sp. */ | |
1066 | /* Insn: add size, sp. */ | |
1067 | this_strategy_size = SIZE_ADD_SP (size); | |
1068 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
1069 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
1070 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1071 | save area, so, no savings. */ |
18e9d2f9 AO |
1072 | |
1073 | if (this_strategy_size < strategy_size) | |
1074 | { | |
1075 | strategy = restore_sp_pre_adjust; | |
1076 | strategy_size = this_strategy_size; | |
1077 | } | |
1078 | ||
1079 | /* Consider using sp offsets after partially adjusting sp. | |
1080 | When size is close to 32Kb, we may be able to adjust SP | |
1081 | with an imm16 add instruction while still using fmov | |
1082 | (d8,sp). */ | |
1083 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1084 | { | |
1085 | /* Insn: add size + 4 * num_regs_to_save | |
1086 | + REG_SAVE_BYTES - 252,sp. */ | |
1087 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save | |
1088 | + REG_SAVE_BYTES - 252); | |
1089 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ | |
1090 | this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES | |
1091 | - 4 * num_regs_to_save, | |
1092 | num_regs_to_save); | |
1093 | /* We're going to use ret to release the FP registers | |
8596d0a1 | 1094 | save area, so, no savings. */ |
18e9d2f9 AO |
1095 | |
1096 | if (this_strategy_size < strategy_size) | |
1097 | { | |
1098 | strategy = restore_sp_partial_adjust; | |
1099 | strategy_size = this_strategy_size; | |
1100 | } | |
1101 | } | |
1102 | ||
1103 | /* Consider using a1 in post-increment mode, as long as the | |
1104 | user hasn't changed the calling conventions of a1. */ | |
9d54866d | 1105 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1] |
18e9d2f9 AO |
1106 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) |
1107 | { | |
1108 | /* Insn: mov sp,a1. */ | |
1109 | this_strategy_size = 1; | |
1110 | if (size) | |
1111 | { | |
1112 | /* Insn: add size,a1. */ | |
1113 | this_strategy_size += SIZE_ADD_AX (size); | |
1114 | } | |
1115 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1116 | this_strategy_size += 3 * num_regs_to_save; | |
1117 | /* If size is large enough, we may be able to save a | |
1118 | couple of bytes. */ | |
1119 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1120 | { | |
1121 | /* Insn: mov a1,sp. */ | |
1122 | this_strategy_size += 2; | |
1123 | } | |
1124 | /* If we don't have to restore any non-FP registers, | |
1125 | we'll be able to save one byte by using rets. */ | |
1126 | if (! REG_SAVE_BYTES) | |
1127 | this_strategy_size--; | |
1128 | ||
1129 | if (this_strategy_size < strategy_size) | |
1130 | { | |
1131 | strategy = restore_a1; | |
1132 | strategy_size = this_strategy_size; | |
1133 | } | |
1134 | } | |
1135 | ||
1136 | switch (strategy) | |
1137 | { | |
1138 | case restore_sp_post_adjust: | |
1139 | break; | |
1140 | ||
1141 | case restore_sp_pre_adjust: | |
1142 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1143 | stack_pointer_rtx, | |
1144 | GEN_INT (size))); | |
1145 | size = 0; | |
1146 | break; | |
1147 | ||
1148 | case restore_sp_partial_adjust: | |
1149 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1150 | stack_pointer_rtx, | |
1151 | GEN_INT (size + 4 * num_regs_to_save | |
1152 | + REG_SAVE_BYTES - 252))); | |
1153 | size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save; | |
1154 | break; | |
5abc5de9 | 1155 | |
18e9d2f9 AO |
1156 | case restore_a1: |
1157 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1158 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1159 | if (size) | |
1160 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1161 | break; | |
1162 | ||
1163 | default: | |
dc759020 | 1164 | gcc_unreachable (); |
18e9d2f9 AO |
1165 | } |
1166 | } | |
1167 | ||
1168 | /* Adjust the selected register, if any, for post-increment. */ | |
1169 | if (reg) | |
1170 | reg = gen_rtx_POST_INC (SImode, reg); | |
1171 | ||
1172 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
9d54866d | 1173 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
18e9d2f9 AO |
1174 | { |
1175 | rtx addr; | |
5abc5de9 | 1176 | |
18e9d2f9 AO |
1177 | if (reg) |
1178 | addr = reg; | |
1179 | else if (size) | |
1180 | { | |
1181 | /* If we aren't using a post-increment register, use an | |
8596d0a1 | 1182 | SP offset. */ |
18e9d2f9 AO |
1183 | addr = gen_rtx_PLUS (SImode, |
1184 | stack_pointer_rtx, | |
1185 | GEN_INT (size)); | |
1186 | } | |
1187 | else | |
1188 | addr = stack_pointer_rtx; | |
1189 | ||
1190 | size += 4; | |
1191 | ||
2720cc47 NC |
1192 | emit_insn (gen_movsf (gen_rtx_REG (SFmode, i), |
1193 | gen_rtx_MEM (SFmode, addr))); | |
18e9d2f9 AO |
1194 | } |
1195 | ||
1196 | /* If we were using the restore_a1 strategy and the number of | |
1197 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1198 | to `sp', to avoid having to use `add' to adjust it. */ | |
1199 | if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255) | |
1200 | { | |
1201 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1202 | size = 0; | |
1203 | } | |
1204 | } | |
1205 | ||
5d29a95f JL |
1206 | /* Maybe cut back the stack, except for the register save area. |
1207 | ||
1208 | If the frame pointer exists, then use the frame pointer to | |
1209 | cut back the stack. | |
1210 | ||
1211 | If the stack size + register save area is more than 255 bytes, | |
1212 | then the stack must be cut back here since the size + register | |
5abc5de9 | 1213 | save size is too big for a ret/retf instruction. |
5d29a95f JL |
1214 | |
1215 | Else leave it alone, it will be cut back as part of the | |
1216 | ret/retf instruction, or there wasn't any stack to begin with. | |
1217 | ||
dab66575 | 1218 | Under no circumstances should the register save area be |
5d29a95f JL |
1219 | deallocated here, that would leave a window where an interrupt |
1220 | could occur and trash the register save area. */ | |
11bb1f11 JL |
1221 | if (frame_pointer_needed) |
1222 | { | |
11bb1f11 | 1223 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
4246e0c5 JL |
1224 | size = 0; |
1225 | } | |
ed6089d6 | 1226 | else if (size + REG_SAVE_BYTES > 255) |
4246e0c5 JL |
1227 | { |
1228 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1229 | stack_pointer_rtx, | |
1230 | GEN_INT (size))); | |
1231 | size = 0; | |
11bb1f11 | 1232 | } |
11bb1f11 | 1233 | |
ed6089d6 | 1234 | /* Adjust the stack and restore callee-saved registers, if any. */ |
6fb5fa3c DB |
1235 | if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1236 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1237 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1238 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
777fbf09 | 1239 | || frame_pointer_needed) |
ed6089d6 AO |
1240 | emit_jump_insn (gen_return_internal_regs |
1241 | (GEN_INT (size + REG_SAVE_BYTES))); | |
777fbf09 | 1242 | else |
ed6089d6 | 1243 | emit_jump_insn (gen_return_internal ()); |
11bb1f11 JL |
1244 | } |
1245 | ||
05713b80 | 1246 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
f6cd7c62 RS |
1247 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1248 | parallel. If OP is a multiple store, return a mask indicating which | |
1249 | registers it saves. Return 0 otherwise. */ | |
1250 | ||
1251 | int | |
e7ab5593 NC |
1252 | mn10300_store_multiple_operation (rtx op, |
1253 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
f6cd7c62 RS |
1254 | { |
1255 | int count; | |
1256 | int mask; | |
1257 | int i; | |
1258 | unsigned int last; | |
1259 | rtx elt; | |
1260 | ||
1261 | count = XVECLEN (op, 0); | |
1262 | if (count < 2) | |
1263 | return 0; | |
1264 | ||
1265 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1266 | elt = XVECEXP (op, 0, 0); | |
1267 | if (GET_CODE (elt) != SET | |
e7ab5593 | 1268 | || (! REG_P (SET_DEST (elt))) |
f6cd7c62 RS |
1269 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM |
1270 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1271 | return 0; | |
1272 | ||
1273 | /* Check that A is the stack pointer and B is the expected stack size. | |
1274 | For OP to match, each subsequent instruction should push a word onto | |
1275 | the stack. We therefore expect the first instruction to create | |
8596d0a1 | 1276 | COUNT-1 stack slots. */ |
f6cd7c62 | 1277 | elt = SET_SRC (elt); |
e7ab5593 | 1278 | if ((! REG_P (XEXP (elt, 0))) |
f6cd7c62 | 1279 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM |
e7ab5593 | 1280 | || (! CONST_INT_P (XEXP (elt, 1))) |
f6cd7c62 RS |
1281 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) |
1282 | return 0; | |
1283 | ||
f6cd7c62 RS |
1284 | mask = 0; |
1285 | for (i = 1; i < count; i++) | |
1286 | { | |
cc909bba RH |
1287 | /* Check that element i is a (set (mem M) R). */ |
1288 | /* ??? Validate the register order a-la mn10300_gen_multiple_store. | |
1289 | Remember: the ordering is *not* monotonic. */ | |
f6cd7c62 RS |
1290 | elt = XVECEXP (op, 0, i); |
1291 | if (GET_CODE (elt) != SET | |
e7ab5593 | 1292 | || (! MEM_P (SET_DEST (elt))) |
cc909bba | 1293 | || (! REG_P (SET_SRC (elt)))) |
f6cd7c62 RS |
1294 | return 0; |
1295 | ||
cc909bba | 1296 | /* Remember which registers are to be saved. */ |
f6cd7c62 RS |
1297 | last = REGNO (SET_SRC (elt)); |
1298 | mask |= (1 << last); | |
1299 | ||
1300 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1301 | elt = XEXP (SET_DEST (elt), 0); | |
1302 | if (GET_CODE (elt) != PLUS | |
e7ab5593 | 1303 | || (! REG_P (XEXP (elt, 0))) |
f6cd7c62 | 1304 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM |
e7ab5593 | 1305 | || (! CONST_INT_P (XEXP (elt, 1))) |
f6cd7c62 RS |
1306 | || INTVAL (XEXP (elt, 1)) != -i * 4) |
1307 | return 0; | |
1308 | } | |
1309 | ||
8596d0a1 | 1310 | /* All or none of the callee-saved extended registers must be in the set. */ |
f6cd7c62 RS |
1311 | if ((mask & 0x3c000) != 0 |
1312 | && (mask & 0x3c000) != 0x3c000) | |
1313 | return 0; | |
1314 | ||
1315 | return mask; | |
1316 | } | |
1317 | ||
f2831cc9 AS |
1318 | /* Implement TARGET_PREFERRED_RELOAD_CLASS. */ |
1319 | ||
1320 | static reg_class_t | |
1321 | mn10300_preferred_reload_class (rtx x, reg_class_t rclass) | |
1322 | { | |
1323 | if (x == stack_pointer_rtx && rclass != SP_REGS) | |
1324 | return ADDRESS_OR_EXTENDED_REGS; | |
1325 | else if (MEM_P (x) | |
1326 | || (REG_P (x) | |
1327 | && !HARD_REGISTER_P (x)) | |
1328 | || (GET_CODE (x) == SUBREG | |
1329 | && REG_P (SUBREG_REG (x)) | |
1330 | && !HARD_REGISTER_P (SUBREG_REG (x)))) | |
1331 | return LIMIT_RELOAD_CLASS (GET_MODE (x), rclass); | |
1332 | else | |
1333 | return rclass; | |
1334 | } | |
1335 | ||
1336 | /* Implement TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */ | |
1337 | ||
1338 | static reg_class_t | |
1339 | mn10300_preferred_output_reload_class (rtx x, reg_class_t rclass) | |
1340 | { | |
1341 | if (x == stack_pointer_rtx && rclass != SP_REGS) | |
1342 | return ADDRESS_OR_EXTENDED_REGS; | |
1343 | ||
1344 | return rclass; | |
1345 | } | |
1346 | ||
11bb1f11 | 1347 | /* What (if any) secondary registers are needed to move IN with mode |
0a2aaacc | 1348 | MODE into a register in register class RCLASS. |
11bb1f11 JL |
1349 | |
1350 | We might be able to simplify this. */ | |
e7ab5593 | 1351 | |
11bb1f11 | 1352 | enum reg_class |
0a2aaacc | 1353 | mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode, |
3c4774e0 | 1354 | rtx in) |
11bb1f11 | 1355 | { |
6528281d JL |
1356 | rtx inner = in; |
1357 | ||
1358 | /* Strip off any SUBREG expressions from IN. Basically we want | |
1359 | to know if IN is a pseudo or (subreg (pseudo)) as those can | |
1360 | turn into MEMs during reload. */ | |
1361 | while (GET_CODE (inner) == SUBREG) | |
1362 | inner = SUBREG_REG (inner); | |
1363 | ||
11bb1f11 JL |
1364 | /* Memory loads less than a full word wide can't have an |
1365 | address or stack pointer destination. They must use | |
1366 | a data register as an intermediate register. */ | |
f3f63737 NC |
1367 | if ((MEM_P (in) |
1368 | || (REG_P (inner) | |
6528281d | 1369 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER)) |
11bb1f11 | 1370 | && (mode == QImode || mode == HImode) |
0a2aaacc KG |
1371 | && (rclass == ADDRESS_REGS || rclass == SP_REGS |
1372 | || rclass == SP_OR_ADDRESS_REGS)) | |
4d1a91c2 | 1373 | { |
705ac34f JL |
1374 | if (TARGET_AM33) |
1375 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
1376 | return DATA_REGS; |
1377 | } | |
11bb1f11 JL |
1378 | |
1379 | /* We can't directly load sp + const_int into a data register; | |
1380 | we must use an address register as an intermediate. */ | |
0a2aaacc KG |
1381 | if (rclass != SP_REGS |
1382 | && rclass != ADDRESS_REGS | |
1383 | && rclass != SP_OR_ADDRESS_REGS | |
1384 | && rclass != SP_OR_EXTENDED_REGS | |
1385 | && rclass != ADDRESS_OR_EXTENDED_REGS | |
1386 | && rclass != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
11bb1f11 JL |
1387 | && (in == stack_pointer_rtx |
1388 | || (GET_CODE (in) == PLUS | |
777fbf09 JL |
1389 | && (XEXP (in, 0) == stack_pointer_rtx |
1390 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
11bb1f11 JL |
1391 | return ADDRESS_REGS; |
1392 | ||
6528281d JL |
1393 | if (TARGET_AM33_2 |
1394 | && rclass == FP_REGS) | |
18e9d2f9 | 1395 | { |
6528281d JL |
1396 | /* We can't load directly into an FP register from a |
1397 | constant address. */ | |
f3f63737 | 1398 | if (MEM_P (in) |
6528281d | 1399 | && CONSTANT_ADDRESS_P (XEXP (in, 0))) |
4af476d7 | 1400 | return DATA_OR_EXTENDED_REGS; |
6528281d JL |
1401 | |
1402 | /* Handle case were a pseudo may not get a hard register | |
1403 | but has an equivalent memory location defined. */ | |
f3f63737 | 1404 | if (REG_P (inner) |
6528281d JL |
1405 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER |
1406 | && reg_equiv_mem [REGNO (inner)] | |
1407 | && CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0))) | |
4af476d7 | 1408 | return DATA_OR_EXTENDED_REGS; |
18e9d2f9 AO |
1409 | } |
1410 | ||
777fbf09 JL |
1411 | /* Otherwise assume no secondary reloads are needed. */ |
1412 | return NO_REGS; | |
1413 | } | |
1414 | ||
1415 | int | |
e7ab5593 | 1416 | mn10300_initial_offset (int from, int to) |
777fbf09 | 1417 | { |
3dbc43d1 JL |
1418 | /* The difference between the argument pointer and the frame pointer |
1419 | is the size of the callee register save area. */ | |
777fbf09 | 1420 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
11bb1f11 | 1421 | { |
6fb5fa3c DB |
1422 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1423 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1424 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1425 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
18e9d2f9 | 1426 | || fp_regs_to_save () |
777fbf09 | 1427 | || frame_pointer_needed) |
18e9d2f9 AO |
1428 | return REG_SAVE_BYTES |
1429 | + 4 * fp_regs_to_save (); | |
777fbf09 | 1430 | else |
22ef4e9b | 1431 | return 0; |
11bb1f11 JL |
1432 | } |
1433 | ||
3dbc43d1 JL |
1434 | /* The difference between the argument pointer and the stack pointer is |
1435 | the sum of the size of this function's frame, the callee register save | |
1436 | area, and the fixed stack space needed for function calls (if any). */ | |
777fbf09 JL |
1437 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
1438 | { | |
6fb5fa3c DB |
1439 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1440 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1441 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1442 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
18e9d2f9 | 1443 | || fp_regs_to_save () |
777fbf09 | 1444 | || frame_pointer_needed) |
4d1a91c2 | 1445 | return (get_frame_size () + REG_SAVE_BYTES |
18e9d2f9 | 1446 | + 4 * fp_regs_to_save () |
38173d38 JH |
1447 | + (crtl->outgoing_args_size |
1448 | ? crtl->outgoing_args_size + 4 : 0)); | |
777fbf09 | 1449 | else |
460f4b9d | 1450 | return (get_frame_size () |
38173d38 JH |
1451 | + (crtl->outgoing_args_size |
1452 | ? crtl->outgoing_args_size + 4 : 0)); | |
777fbf09 | 1453 | } |
11bb1f11 | 1454 | |
3dbc43d1 JL |
1455 | /* The difference between the frame pointer and stack pointer is the sum |
1456 | of the size of this function's frame and the fixed stack space needed | |
1457 | for function calls (if any). */ | |
777fbf09 | 1458 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
460f4b9d | 1459 | return (get_frame_size () |
38173d38 JH |
1460 | + (crtl->outgoing_args_size |
1461 | ? crtl->outgoing_args_size + 4 : 0)); | |
777fbf09 | 1462 | |
dc759020 | 1463 | gcc_unreachable (); |
11bb1f11 | 1464 | } |
22ef4e9b | 1465 | |
bd5bd7ac KH |
1466 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
1467 | ||
9024ea92 | 1468 | static bool |
586de218 | 1469 | mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
9024ea92 KH |
1470 | { |
1471 | /* Return values > 8 bytes in length in memory. */ | |
b1eb8119 DD |
1472 | return (int_size_in_bytes (type) > 8 |
1473 | || int_size_in_bytes (type) == 0 | |
1474 | || TYPE_MODE (type) == BLKmode); | |
9024ea92 KH |
1475 | } |
1476 | ||
22ef4e9b JL |
1477 | /* Flush the argument registers to the stack for a stdarg function; |
1478 | return the new argument pointer. */ | |
9024ea92 | 1479 | static rtx |
f1777882 | 1480 | mn10300_builtin_saveregs (void) |
22ef4e9b | 1481 | { |
fc2acc87 | 1482 | rtx offset, mem; |
22ef4e9b | 1483 | tree fntype = TREE_TYPE (current_function_decl); |
f38958e8 | 1484 | int argadj = ((!stdarg_p (fntype)) |
22ef4e9b | 1485 | ? UNITS_PER_WORD : 0); |
4862826d | 1486 | alias_set_type set = get_varargs_alias_set (); |
22ef4e9b JL |
1487 | |
1488 | if (argadj) | |
38173d38 | 1489 | offset = plus_constant (crtl->args.arg_offset_rtx, argadj); |
22ef4e9b | 1490 | else |
38173d38 | 1491 | offset = crtl->args.arg_offset_rtx; |
22ef4e9b | 1492 | |
38173d38 | 1493 | mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer); |
ba4828e0 | 1494 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1495 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1496 | ||
1497 | mem = gen_rtx_MEM (SImode, | |
38173d38 | 1498 | plus_constant (crtl->args.internal_arg_pointer, 4)); |
ba4828e0 | 1499 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
1500 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1501 | ||
22ef4e9b | 1502 | return copy_to_reg (expand_binop (Pmode, add_optab, |
38173d38 | 1503 | crtl->args.internal_arg_pointer, |
22ef4e9b JL |
1504 | offset, 0, 0, OPTAB_LIB_WIDEN)); |
1505 | } | |
1506 | ||
d7bd8aeb | 1507 | static void |
f1777882 | 1508 | mn10300_va_start (tree valist, rtx nextarg) |
fc2acc87 | 1509 | { |
6c535c69 | 1510 | nextarg = expand_builtin_saveregs (); |
e5faf155 | 1511 | std_expand_builtin_va_start (valist, nextarg); |
fc2acc87 RH |
1512 | } |
1513 | ||
8cd5a4e0 RH |
1514 | /* Return true when a parameter should be passed by reference. */ |
1515 | ||
1516 | static bool | |
1517 | mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
586de218 | 1518 | enum machine_mode mode, const_tree type, |
8cd5a4e0 RH |
1519 | bool named ATTRIBUTE_UNUSED) |
1520 | { | |
1521 | unsigned HOST_WIDE_INT size; | |
1522 | ||
1523 | if (type) | |
1524 | size = int_size_in_bytes (type); | |
1525 | else | |
1526 | size = GET_MODE_SIZE (mode); | |
1527 | ||
b1eb8119 | 1528 | return (size > 8 || size == 0); |
8cd5a4e0 RH |
1529 | } |
1530 | ||
22ef4e9b | 1531 | /* Return an RTX to represent where a value with mode MODE will be returned |
990dc016 | 1532 | from a function. If the result is NULL_RTX, the argument is pushed. */ |
22ef4e9b | 1533 | |
ce236858 | 1534 | static rtx |
e7ab5593 | 1535 | mn10300_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
ce236858 | 1536 | const_tree type, bool named ATTRIBUTE_UNUSED) |
22ef4e9b | 1537 | { |
990dc016 | 1538 | rtx result = NULL_RTX; |
f4a88680 | 1539 | int size; |
22ef4e9b JL |
1540 | |
1541 | /* We only support using 2 data registers as argument registers. */ | |
1542 | int nregs = 2; | |
1543 | ||
1544 | /* Figure out the size of the object to be passed. */ | |
1545 | if (mode == BLKmode) | |
1546 | size = int_size_in_bytes (type); | |
1547 | else | |
1548 | size = GET_MODE_SIZE (mode); | |
1549 | ||
22ef4e9b JL |
1550 | cum->nbytes = (cum->nbytes + 3) & ~3; |
1551 | ||
1552 | /* Don't pass this arg via a register if all the argument registers | |
1553 | are used up. */ | |
1554 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
990dc016 | 1555 | return result; |
22ef4e9b JL |
1556 | |
1557 | /* Don't pass this arg via a register if it would be split between | |
1558 | registers and memory. */ | |
1559 | if (type == NULL_TREE | |
1560 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
990dc016 | 1561 | return result; |
22ef4e9b JL |
1562 | |
1563 | switch (cum->nbytes / UNITS_PER_WORD) | |
1564 | { | |
1565 | case 0: | |
990dc016 | 1566 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM); |
22ef4e9b JL |
1567 | break; |
1568 | case 1: | |
990dc016 | 1569 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1); |
22ef4e9b JL |
1570 | break; |
1571 | default: | |
990dc016 | 1572 | break; |
22ef4e9b JL |
1573 | } |
1574 | ||
1575 | return result; | |
1576 | } | |
1577 | ||
ce236858 NF |
1578 | /* Update the data in CUM to advance over an argument |
1579 | of mode MODE and data type TYPE. | |
1580 | (TYPE is null for libcalls where that information may not be available.) */ | |
1581 | ||
1582 | static void | |
1583 | mn10300_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1584 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
1585 | { | |
1586 | cum->nbytes += (mode != BLKmode | |
1587 | ? (GET_MODE_SIZE (mode) + 3) & ~3 | |
1588 | : (int_size_in_bytes (type) + 3) & ~3); | |
1589 | } | |
1590 | ||
78a52f11 RH |
1591 | /* Return the number of bytes of registers to use for an argument passed |
1592 | partially in registers and partially in memory. */ | |
22ef4e9b | 1593 | |
78a52f11 RH |
1594 | static int |
1595 | mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1596 | tree type, bool named ATTRIBUTE_UNUSED) | |
22ef4e9b | 1597 | { |
f4a88680 | 1598 | int size; |
22ef4e9b JL |
1599 | |
1600 | /* We only support using 2 data registers as argument registers. */ | |
1601 | int nregs = 2; | |
1602 | ||
1603 | /* Figure out the size of the object to be passed. */ | |
1604 | if (mode == BLKmode) | |
1605 | size = int_size_in_bytes (type); | |
1606 | else | |
1607 | size = GET_MODE_SIZE (mode); | |
1608 | ||
22ef4e9b JL |
1609 | cum->nbytes = (cum->nbytes + 3) & ~3; |
1610 | ||
1611 | /* Don't pass this arg via a register if all the argument registers | |
1612 | are used up. */ | |
1613 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1614 | return 0; | |
1615 | ||
1616 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1617 | return 0; | |
1618 | ||
1619 | /* Don't pass this arg via a register if it would be split between | |
1620 | registers and memory. */ | |
1621 | if (type == NULL_TREE | |
1622 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1623 | return 0; | |
1624 | ||
78a52f11 | 1625 | return nregs * UNITS_PER_WORD - cum->nbytes; |
22ef4e9b JL |
1626 | } |
1627 | ||
b1eb8119 DD |
1628 | /* Return the location of the function's value. This will be either |
1629 | $d0 for integer functions, $a0 for pointers, or a PARALLEL of both | |
1630 | $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that | |
1631 | we only return the PARALLEL for outgoing values; we do not want | |
1632 | callers relying on this extra copy. */ | |
1633 | ||
34732b0a AS |
1634 | static rtx |
1635 | mn10300_function_value (const_tree valtype, | |
1636 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
1637 | bool outgoing) | |
b1eb8119 DD |
1638 | { |
1639 | rtx rv; | |
1640 | enum machine_mode mode = TYPE_MODE (valtype); | |
1641 | ||
1642 | if (! POINTER_TYPE_P (valtype)) | |
1643 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1644 | else if (! TARGET_PTR_A0D0 || ! outgoing | |
e3b5732b | 1645 | || cfun->returns_struct) |
b1eb8119 DD |
1646 | return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM); |
1647 | ||
1648 | rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2)); | |
1649 | XVECEXP (rv, 0, 0) | |
1650 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1651 | gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM), | |
1652 | GEN_INT (0)); | |
5abc5de9 | 1653 | |
b1eb8119 DD |
1654 | XVECEXP (rv, 0, 1) |
1655 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1656 | gen_rtx_REG (mode, FIRST_DATA_REGNUM), | |
1657 | GEN_INT (0)); | |
1658 | return rv; | |
1659 | } | |
1660 | ||
34732b0a AS |
1661 | /* Implements TARGET_LIBCALL_VALUE. */ |
1662 | ||
1663 | static rtx | |
1664 | mn10300_libcall_value (enum machine_mode mode, | |
1665 | const_rtx fun ATTRIBUTE_UNUSED) | |
1666 | { | |
1667 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1668 | } | |
1669 | ||
1670 | /* Implements FUNCTION_VALUE_REGNO_P. */ | |
1671 | ||
1672 | bool | |
1673 | mn10300_function_value_regno_p (const unsigned int regno) | |
1674 | { | |
1675 | return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM); | |
1676 | } | |
1677 | ||
4af476d7 NC |
1678 | /* Output a compare insn. */ |
1679 | ||
1943c2c1 | 1680 | const char * |
4af476d7 | 1681 | mn10300_output_cmp (rtx operand, rtx insn) |
22ef4e9b | 1682 | { |
22ef4e9b JL |
1683 | rtx temp; |
1684 | int past_call = 0; | |
1685 | ||
1686 | /* We can save a byte if we can find a register which has the value | |
1687 | zero in it. */ | |
1688 | temp = PREV_INSN (insn); | |
74452ac3 | 1689 | while (optimize && temp) |
22ef4e9b JL |
1690 | { |
1691 | rtx set; | |
1692 | ||
1693 | /* We allow the search to go through call insns. We record | |
1694 | the fact that we've past a CALL_INSN and reject matches which | |
1695 | use call clobbered registers. */ | |
e7ab5593 NC |
1696 | if (LABEL_P (temp) |
1697 | || JUMP_P (temp) | |
22ef4e9b JL |
1698 | || GET_CODE (temp) == BARRIER) |
1699 | break; | |
1700 | ||
e7ab5593 | 1701 | if (CALL_P (temp)) |
22ef4e9b JL |
1702 | past_call = 1; |
1703 | ||
1704 | if (GET_CODE (temp) == NOTE) | |
1705 | { | |
1706 | temp = PREV_INSN (temp); | |
1707 | continue; | |
1708 | } | |
1709 | ||
8596d0a1 | 1710 | /* It must be an insn, see if it is a simple set. */ |
22ef4e9b JL |
1711 | set = single_set (temp); |
1712 | if (!set) | |
1713 | { | |
1714 | temp = PREV_INSN (temp); | |
1715 | continue; | |
1716 | } | |
1717 | ||
1718 | /* Are we setting a data register to zero (this does not win for | |
5abc5de9 | 1719 | address registers)? |
22ef4e9b JL |
1720 | |
1721 | If it's a call clobbered register, have we past a call? | |
1722 | ||
1723 | Make sure the register we find isn't the same as ourself; | |
4d1a91c2 JL |
1724 | the mn10300 can't encode that. |
1725 | ||
1726 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1727 | so the code to detect calls here isn't doing anything useful. */ | |
22ef4e9b JL |
1728 | if (REG_P (SET_DEST (set)) |
1729 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1730 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
74452ac3 JL |
1731 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1732 | == REGNO_REG_CLASS (REGNO (operand))) | |
705ac34f JL |
1733 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1734 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
5abc5de9 | 1735 | && (!past_call |
9d54866d | 1736 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
705ac34f JL |
1737 | { |
1738 | rtx xoperands[2]; | |
1739 | xoperands[0] = operand; | |
1740 | xoperands[1] = SET_DEST (set); | |
1741 | ||
1742 | output_asm_insn ("cmp %1,%0", xoperands); | |
1743 | return ""; | |
1744 | } | |
1745 | ||
1746 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1747 | && REG_P (SET_DEST (set)) | |
1748 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1749 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1750 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1751 | != REGNO_REG_CLASS (REGNO (operand))) | |
1752 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
22ef4e9b | 1753 | && REGNO (SET_DEST (set)) != REGNO (operand) |
5abc5de9 | 1754 | && (!past_call |
9d54866d | 1755 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
22ef4e9b JL |
1756 | { |
1757 | rtx xoperands[2]; | |
1758 | xoperands[0] = operand; | |
1759 | xoperands[1] = SET_DEST (set); | |
1760 | ||
1761 | output_asm_insn ("cmp %1,%0", xoperands); | |
1762 | return ""; | |
1763 | } | |
1764 | temp = PREV_INSN (temp); | |
1765 | } | |
1766 | return "cmp 0,%0"; | |
1767 | } | |
460f4b9d | 1768 | |
e9ad4573 JL |
1769 | /* Return 1 if X contains a symbolic expression. We know these |
1770 | expressions will have one of a few well defined forms, so | |
1771 | we need only check those forms. */ | |
e7ab5593 | 1772 | |
e9ad4573 | 1773 | int |
e7ab5593 NC |
1774 | mn10300_symbolic_operand (rtx op, |
1775 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
e9ad4573 JL |
1776 | { |
1777 | switch (GET_CODE (op)) | |
1778 | { | |
1779 | case SYMBOL_REF: | |
1780 | case LABEL_REF: | |
1781 | return 1; | |
1782 | case CONST: | |
1783 | op = XEXP (op, 0); | |
1784 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1785 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
f3f63737 | 1786 | && CONST_INT_P (XEXP (op, 1))); |
e9ad4573 JL |
1787 | default: |
1788 | return 0; | |
1789 | } | |
1790 | } | |
1791 | ||
1792 | /* Try machine dependent ways of modifying an illegitimate address | |
1793 | to be legitimate. If we find one, return the new valid address. | |
1794 | This macro is used in only one place: `memory_address' in explow.c. | |
1795 | ||
1796 | OLDX is the address as it was before break_out_memory_refs was called. | |
1797 | In some cases it is useful to look at this to decide what needs to be done. | |
1798 | ||
e9ad4573 JL |
1799 | Normally it is always safe for this macro to do nothing. It exists to |
1800 | recognize opportunities to optimize the output. | |
1801 | ||
1802 | But on a few ports with segmented architectures and indexed addressing | |
1803 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
e7ab5593 | 1804 | |
4af476d7 | 1805 | static rtx |
506d7b68 PB |
1806 | mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1807 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
e9ad4573 | 1808 | { |
e7ab5593 NC |
1809 | if (flag_pic && ! mn10300_legitimate_pic_operand_p (x)) |
1810 | x = mn10300_legitimize_pic_address (oldx, NULL_RTX); | |
d1776069 | 1811 | |
e9ad4573 JL |
1812 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1813 | special handling to avoid creating an indexed memory address | |
1814 | with x-100000 as the base. */ | |
1815 | if (GET_CODE (x) == PLUS | |
e7ab5593 | 1816 | && mn10300_symbolic_operand (XEXP (x, 1), VOIDmode)) |
e9ad4573 JL |
1817 | { |
1818 | /* Ugly. We modify things here so that the address offset specified | |
1819 | by the index expression is computed first, then added to x to form | |
1820 | the entire address. */ | |
1821 | ||
69bc71fa | 1822 | rtx regx1, regy1, regy2, y; |
e9ad4573 JL |
1823 | |
1824 | /* Strip off any CONST. */ | |
1825 | y = XEXP (x, 1); | |
1826 | if (GET_CODE (y) == CONST) | |
1827 | y = XEXP (y, 0); | |
1828 | ||
bf4219f0 JL |
1829 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1830 | { | |
1831 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1832 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1833 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1834 | regx1 = force_reg (Pmode, | |
e7ab5593 NC |
1835 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, |
1836 | regy2)); | |
c5c76735 | 1837 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
bf4219f0 | 1838 | } |
e9ad4573 | 1839 | } |
371036e0 | 1840 | return x; |
e9ad4573 | 1841 | } |
460ad325 | 1842 | |
d1776069 | 1843 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
8596d0a1 | 1844 | @GOTOFF in `reg'. */ |
e7ab5593 | 1845 | |
d1776069 | 1846 | rtx |
e7ab5593 | 1847 | mn10300_legitimize_pic_address (rtx orig, rtx reg) |
d1776069 | 1848 | { |
53855940 RH |
1849 | rtx x; |
1850 | ||
d1776069 AO |
1851 | if (GET_CODE (orig) == LABEL_REF |
1852 | || (GET_CODE (orig) == SYMBOL_REF | |
1853 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1854 | || ! MN10300_GLOBAL_P (orig)))) | |
1855 | { | |
53855940 | 1856 | if (reg == NULL) |
d1776069 AO |
1857 | reg = gen_reg_rtx (Pmode); |
1858 | ||
53855940 RH |
1859 | x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOTOFF); |
1860 | x = gen_rtx_CONST (SImode, x); | |
1861 | emit_move_insn (reg, x); | |
1862 | ||
1863 | x = emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx)); | |
d1776069 AO |
1864 | } |
1865 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1866 | { | |
53855940 | 1867 | if (reg == NULL) |
d1776069 AO |
1868 | reg = gen_reg_rtx (Pmode); |
1869 | ||
53855940 RH |
1870 | x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOT); |
1871 | x = gen_rtx_CONST (SImode, x); | |
1872 | x = gen_rtx_PLUS (SImode, pic_offset_table_rtx, x); | |
1873 | x = gen_const_mem (SImode, x); | |
1874 | ||
1875 | x = emit_move_insn (reg, x); | |
d1776069 | 1876 | } |
53855940 RH |
1877 | else |
1878 | return orig; | |
1879 | ||
1880 | set_unique_reg_note (x, REG_EQUAL, orig); | |
1881 | return reg; | |
d1776069 AO |
1882 | } |
1883 | ||
1884 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
4375e090 | 1885 | isn't protected by a PIC unspec; nonzero otherwise. */ |
e7ab5593 | 1886 | |
d1776069 | 1887 | int |
e7ab5593 | 1888 | mn10300_legitimate_pic_operand_p (rtx x) |
d1776069 | 1889 | { |
e7ab5593 NC |
1890 | const char *fmt; |
1891 | int i; | |
d1776069 AO |
1892 | |
1893 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1894 | return 0; | |
1895 | ||
1896 | if (GET_CODE (x) == UNSPEC | |
1897 | && (XINT (x, 1) == UNSPEC_PIC | |
1898 | || XINT (x, 1) == UNSPEC_GOT | |
1899 | || XINT (x, 1) == UNSPEC_GOTOFF | |
d4e2d7d2 RS |
1900 | || XINT (x, 1) == UNSPEC_PLT |
1901 | || XINT (x, 1) == UNSPEC_GOTSYM_OFF)) | |
d1776069 AO |
1902 | return 1; |
1903 | ||
d1776069 AO |
1904 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
1905 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1906 | { | |
1907 | if (fmt[i] == 'E') | |
1908 | { | |
4af476d7 | 1909 | int j; |
d1776069 AO |
1910 | |
1911 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
e7ab5593 | 1912 | if (! mn10300_legitimate_pic_operand_p (XVECEXP (x, i, j))) |
d1776069 AO |
1913 | return 0; |
1914 | } | |
e7ab5593 NC |
1915 | else if (fmt[i] == 'e' |
1916 | && ! mn10300_legitimate_pic_operand_p (XEXP (x, i))) | |
d1776069 AO |
1917 | return 0; |
1918 | } | |
1919 | ||
1920 | return 1; | |
1921 | } | |
1922 | ||
e733134f | 1923 | /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is |
c6c3dba9 PB |
1924 | legitimate, and FALSE otherwise. |
1925 | ||
1926 | On the mn10300, the value in the address register must be | |
1927 | in the same memory space/segment as the effective address. | |
1928 | ||
1929 | This is problematical for reload since it does not understand | |
1930 | that base+index != index+base in a memory reference. | |
1931 | ||
1932 | Note it is still possible to use reg+reg addressing modes, | |
1933 | it's just much more difficult. For a discussion of a possible | |
1934 | workaround and solution, see the comments in pa.c before the | |
1935 | function record_unscaled_index_insn_codes. */ | |
1936 | ||
4af476d7 | 1937 | static bool |
c6c3dba9 | 1938 | mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) |
e733134f AO |
1939 | { |
1940 | if (CONSTANT_ADDRESS_P (x) | |
e7ab5593 | 1941 | && (! flag_pic || mn10300_legitimate_pic_operand_p (x))) |
e733134f AO |
1942 | return TRUE; |
1943 | ||
1944 | if (RTX_OK_FOR_BASE_P (x, strict)) | |
1945 | return TRUE; | |
1946 | ||
1947 | if (TARGET_AM33 | |
1948 | && GET_CODE (x) == POST_INC | |
1949 | && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict) | |
1950 | && (mode == SImode || mode == SFmode || mode == HImode)) | |
1951 | return TRUE; | |
1952 | ||
1953 | if (GET_CODE (x) == PLUS) | |
1954 | { | |
1955 | rtx base = 0, index = 0; | |
1956 | ||
1957 | if (REG_P (XEXP (x, 0)) | |
1958 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict)) | |
1959 | { | |
1960 | base = XEXP (x, 0); | |
1961 | index = XEXP (x, 1); | |
1962 | } | |
1963 | ||
1964 | if (REG_P (XEXP (x, 1)) | |
1965 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict)) | |
1966 | { | |
1967 | base = XEXP (x, 1); | |
1968 | index = XEXP (x, 0); | |
1969 | } | |
1970 | ||
1971 | if (base != 0 && index != 0) | |
1972 | { | |
f3f63737 | 1973 | if (CONST_INT_P (index)) |
e733134f AO |
1974 | return TRUE; |
1975 | if (GET_CODE (index) == CONST | |
5542b23d | 1976 | && GET_CODE (XEXP (index, 0)) != PLUS |
e733134f | 1977 | && (! flag_pic |
e7ab5593 | 1978 | || (mn10300_legitimate_pic_operand_p (index) |
4af476d7 | 1979 | && GET_MODE_SIZE (mode) == 4))) |
e733134f AO |
1980 | return TRUE; |
1981 | } | |
1982 | } | |
1983 | ||
1984 | return FALSE; | |
1985 | } | |
1986 | ||
4af476d7 NC |
1987 | /* Used by LEGITIMATE_CONSTANT_P(). Returns TRUE if X is a valid |
1988 | constant. Note that some "constants" aren't valid, such as TLS | |
1989 | symbols and unconverted GOT-based references, so we eliminate | |
1990 | those here. */ | |
1991 | ||
1992 | bool | |
1993 | mn10300_legitimate_constant_p (rtx x) | |
1994 | { | |
1995 | switch (GET_CODE (x)) | |
1996 | { | |
1997 | case CONST: | |
1998 | x = XEXP (x, 0); | |
1999 | ||
2000 | if (GET_CODE (x) == PLUS) | |
2001 | { | |
e7ab5593 | 2002 | if (! CONST_INT_P (XEXP (x, 1))) |
4af476d7 NC |
2003 | return false; |
2004 | x = XEXP (x, 0); | |
2005 | } | |
2006 | ||
2007 | /* Only some unspecs are valid as "constants". */ | |
2008 | if (GET_CODE (x) == UNSPEC) | |
2009 | { | |
4af476d7 NC |
2010 | switch (XINT (x, 1)) |
2011 | { | |
2012 | case UNSPEC_INT_LABEL: | |
2013 | case UNSPEC_PIC: | |
2014 | case UNSPEC_GOT: | |
2015 | case UNSPEC_GOTOFF: | |
2016 | case UNSPEC_PLT: | |
2017 | return true; | |
2018 | default: | |
2019 | return false; | |
2020 | } | |
2021 | } | |
2022 | ||
2023 | /* We must have drilled down to a symbol. */ | |
e7ab5593 | 2024 | if (! mn10300_symbolic_operand (x, Pmode)) |
4af476d7 NC |
2025 | return false; |
2026 | break; | |
2027 | ||
2028 | default: | |
2029 | break; | |
2030 | } | |
2031 | ||
2032 | return true; | |
2033 | } | |
2034 | ||
72d6e3c5 RH |
2035 | /* For addresses, costs are relative to "MOV (Rm),Rn". For AM33 this is |
2036 | the 3-byte fully general instruction; for MN103 this is the 2-byte form | |
2037 | with an address register. */ | |
2038 | ||
dcefdf67 | 2039 | static int |
72d6e3c5 | 2040 | mn10300_address_cost (rtx x, bool speed) |
460ad325 | 2041 | { |
72d6e3c5 RH |
2042 | HOST_WIDE_INT i; |
2043 | rtx base, index; | |
2044 | ||
460ad325 AO |
2045 | switch (GET_CODE (x)) |
2046 | { | |
72d6e3c5 RH |
2047 | case CONST: |
2048 | case SYMBOL_REF: | |
2049 | case LABEL_REF: | |
2050 | /* We assume all of these require a 32-bit constant, even though | |
2051 | some symbol and label references can be relaxed. */ | |
2052 | return speed ? 1 : 4; | |
2053 | ||
460ad325 | 2054 | case REG: |
72d6e3c5 RH |
2055 | case SUBREG: |
2056 | case POST_INC: | |
2057 | return 0; | |
2058 | ||
2059 | case POST_MODIFY: | |
2060 | /* Assume any symbolic offset is a 32-bit constant. */ | |
2061 | i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678); | |
2062 | if (IN_RANGE (i, -128, 127)) | |
2063 | return speed ? 0 : 1; | |
2064 | if (speed) | |
2065 | return 1; | |
2066 | if (IN_RANGE (i, -0x800000, 0x7fffff)) | |
2067 | return 3; | |
2068 | return 4; | |
2069 | ||
2070 | case PLUS: | |
2071 | base = XEXP (x, 0); | |
2072 | index = XEXP (x, 1); | |
2073 | if (register_operand (index, SImode)) | |
460ad325 | 2074 | { |
72d6e3c5 RH |
2075 | /* Attempt to minimize the number of registers in the address. |
2076 | This is similar to what other ports do. */ | |
2077 | if (register_operand (base, SImode)) | |
2078 | return 1; | |
460ad325 | 2079 | |
72d6e3c5 RH |
2080 | base = XEXP (x, 1); |
2081 | index = XEXP (x, 0); | |
2082 | } | |
460ad325 | 2083 | |
72d6e3c5 RH |
2084 | /* Assume any symbolic offset is a 32-bit constant. */ |
2085 | i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678); | |
2086 | if (IN_RANGE (i, -128, 127)) | |
2087 | return speed ? 0 : 1; | |
2088 | if (IN_RANGE (i, -32768, 32767)) | |
2089 | return speed ? 0 : 2; | |
2090 | return speed ? 2 : 6; | |
460ad325 | 2091 | |
72d6e3c5 RH |
2092 | default: |
2093 | return rtx_cost (x, MEM, speed); | |
2094 | } | |
2095 | } | |
460ad325 | 2096 | |
72d6e3c5 | 2097 | /* Implement the TARGET_REGISTER_MOVE_COST hook. |
460ad325 | 2098 | |
72d6e3c5 RH |
2099 | Recall that the base value of 2 is required by assumptions elsewhere |
2100 | in the body of the compiler, and that cost 2 is special-cased as an | |
2101 | early exit from reload meaning no work is required. */ | |
460ad325 | 2102 | |
72d6e3c5 RH |
2103 | static int |
2104 | mn10300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
2105 | reg_class_t ifrom, reg_class_t ito) | |
2106 | { | |
2107 | enum reg_class from = (enum reg_class) ifrom; | |
2108 | enum reg_class to = (enum reg_class) ito; | |
2109 | enum reg_class scratch, test; | |
2110 | ||
2111 | /* Simplify the following code by unifying the fp register classes. */ | |
2112 | if (to == FP_ACC_REGS) | |
2113 | to = FP_REGS; | |
2114 | if (from == FP_ACC_REGS) | |
2115 | from = FP_REGS; | |
2116 | ||
2117 | /* Diagnose invalid moves by costing them as two moves. */ | |
2118 | ||
2119 | scratch = NO_REGS; | |
2120 | test = from; | |
2121 | if (to == SP_REGS) | |
2122 | scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS); | |
2123 | else if (to == FP_REGS && to != from) | |
2124 | scratch = GENERAL_REGS; | |
2125 | else | |
2126 | { | |
2127 | test = to; | |
2128 | if (from == SP_REGS) | |
2129 | scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS); | |
2130 | else if (from == FP_REGS && to != from) | |
2131 | scratch = GENERAL_REGS; | |
2132 | } | |
2133 | if (scratch != NO_REGS && !reg_class_subset_p (test, scratch)) | |
2134 | return (mn10300_register_move_cost (VOIDmode, from, scratch) | |
2135 | + mn10300_register_move_cost (VOIDmode, scratch, to)); | |
460ad325 | 2136 | |
72d6e3c5 | 2137 | /* From here on, all we need consider are legal combinations. */ |
460ad325 | 2138 | |
72d6e3c5 RH |
2139 | if (optimize_size) |
2140 | { | |
2141 | /* The scale here is bytes * 2. */ | |
460ad325 | 2142 | |
72d6e3c5 RH |
2143 | if (from == to && (to == ADDRESS_REGS || to == DATA_REGS)) |
2144 | return 2; | |
460ad325 | 2145 | |
72d6e3c5 RH |
2146 | if (from == SP_REGS) |
2147 | return (to == ADDRESS_REGS ? 2 : 6); | |
2148 | ||
2149 | /* For MN103, all remaining legal moves are two bytes. */ | |
2150 | if (TARGET_AM33) | |
2151 | return 4; | |
2152 | ||
2153 | if (to == SP_REGS) | |
2154 | return (from == ADDRESS_REGS ? 4 : 6); | |
2155 | ||
2156 | if ((from == ADDRESS_REGS || from == DATA_REGS) | |
2157 | && (to == ADDRESS_REGS || to == DATA_REGS)) | |
2158 | return 4; | |
2159 | ||
2160 | if (to == EXTENDED_REGS) | |
2161 | return (to == from ? 6 : 4); | |
460ad325 | 2162 | |
72d6e3c5 RH |
2163 | /* What's left are SP_REGS, FP_REGS, or combinations of the above. */ |
2164 | return 6; | |
2165 | } | |
2166 | else | |
2167 | { | |
2168 | /* The scale here is cycles * 2. */ | |
2169 | ||
2170 | if (to == FP_REGS) | |
2171 | return 8; | |
2172 | if (from == FP_REGS) | |
2173 | return 4; | |
2174 | ||
2175 | /* All legal moves between integral registers are single cycle. */ | |
2176 | return 2; | |
460ad325 AO |
2177 | } |
2178 | } | |
3c50106f | 2179 | |
72d6e3c5 RH |
2180 | /* Implement the TARGET_MEMORY_MOVE_COST hook. |
2181 | ||
2182 | Given lack of the form of the address, this must be speed-relative, | |
2183 | though we should never be less expensive than a size-relative register | |
2184 | move cost above. This is not a problem. */ | |
2185 | ||
dcefdf67 | 2186 | static int |
72d6e3c5 RH |
2187 | mn10300_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, |
2188 | reg_class_t iclass, bool in ATTRIBUTE_UNUSED) | |
dcefdf67 | 2189 | { |
72d6e3c5 RH |
2190 | enum reg_class rclass = (enum reg_class) iclass; |
2191 | ||
2192 | if (rclass == FP_REGS) | |
2193 | return 8; | |
2194 | return 6; | |
dcefdf67 RH |
2195 | } |
2196 | ||
72d6e3c5 RH |
2197 | /* Implement the TARGET_RTX_COSTS hook. |
2198 | ||
2199 | Speed-relative costs are relative to COSTS_N_INSNS, which is intended | |
2200 | to represent cycles. Size-relative costs are in bytes. */ | |
2201 | ||
3c50106f | 2202 | static bool |
72d6e3c5 | 2203 | mn10300_rtx_costs (rtx x, int code, int outer_code, int *ptotal, bool speed) |
3c50106f | 2204 | { |
72d6e3c5 RH |
2205 | /* This value is used for SYMBOL_REF etc where we want to pretend |
2206 | we have a full 32-bit constant. */ | |
2207 | HOST_WIDE_INT i = 0x12345678; | |
2208 | int total; | |
2209 | ||
3c50106f RH |
2210 | switch (code) |
2211 | { | |
2212 | case CONST_INT: | |
72d6e3c5 RH |
2213 | i = INTVAL (x); |
2214 | do_int_costs: | |
2215 | if (speed) | |
2216 | { | |
2217 | if (outer_code == SET) | |
2218 | { | |
2219 | /* 16-bit integer loads have latency 1, 32-bit loads 2. */ | |
2220 | if (IN_RANGE (i, -32768, 32767)) | |
2221 | total = COSTS_N_INSNS (1); | |
2222 | else | |
2223 | total = COSTS_N_INSNS (2); | |
2224 | } | |
2225 | else | |
2226 | { | |
2227 | /* 16-bit integer operands don't affect latency; | |
2228 | 24-bit and 32-bit operands add a cycle. */ | |
2229 | if (IN_RANGE (i, -32768, 32767)) | |
2230 | total = 0; | |
2231 | else | |
2232 | total = COSTS_N_INSNS (1); | |
2233 | } | |
2234 | } | |
3c50106f | 2235 | else |
72d6e3c5 RH |
2236 | { |
2237 | if (outer_code == SET) | |
2238 | { | |
2239 | if (i == 0) | |
2240 | total = 1; | |
2241 | else if (IN_RANGE (i, -128, 127)) | |
2242 | total = 2; | |
2243 | else if (IN_RANGE (i, -32768, 32767)) | |
2244 | total = 3; | |
2245 | else | |
2246 | total = 6; | |
2247 | } | |
2248 | else | |
2249 | { | |
2250 | /* Reference here is ADD An,Dn, vs ADD imm,Dn. */ | |
2251 | if (IN_RANGE (i, -128, 127)) | |
2252 | total = 0; | |
2253 | else if (IN_RANGE (i, -32768, 32767)) | |
2254 | total = 2; | |
2255 | else if (TARGET_AM33 && IN_RANGE (i, -0x01000000, 0x00ffffff)) | |
2256 | total = 3; | |
2257 | else | |
2258 | total = 4; | |
2259 | } | |
2260 | } | |
2261 | goto alldone; | |
3c50106f RH |
2262 | |
2263 | case CONST: | |
2264 | case LABEL_REF: | |
2265 | case SYMBOL_REF: | |
3c50106f | 2266 | case CONST_DOUBLE: |
72d6e3c5 RH |
2267 | /* We assume all of these require a 32-bit constant, even though |
2268 | some symbol and label references can be relaxed. */ | |
2269 | goto do_int_costs; | |
f90b7a5a | 2270 | |
72d6e3c5 RH |
2271 | case UNSPEC: |
2272 | switch (XINT (x, 1)) | |
2273 | { | |
2274 | case UNSPEC_PIC: | |
2275 | case UNSPEC_GOT: | |
2276 | case UNSPEC_GOTOFF: | |
2277 | case UNSPEC_PLT: | |
2278 | case UNSPEC_GOTSYM_OFF: | |
2279 | /* The PIC unspecs also resolve to a 32-bit constant. */ | |
2280 | goto do_int_costs; | |
3c50106f | 2281 | |
72d6e3c5 RH |
2282 | default: |
2283 | /* Assume any non-listed unspec is some sort of arithmetic. */ | |
2284 | goto do_arith_costs; | |
2285 | } | |
fe7496dd | 2286 | |
72d6e3c5 RH |
2287 | case PLUS: |
2288 | /* Notice the size difference of INC and INC4. */ | |
2289 | if (!speed && outer_code == SET && CONST_INT_P (XEXP (x, 1))) | |
2290 | { | |
2291 | i = INTVAL (XEXP (x, 1)); | |
2292 | if (i == 1 || i == 4) | |
2293 | { | |
2294 | total = 1 + rtx_cost (XEXP (x, 0), PLUS, speed); | |
2295 | goto alldone; | |
2296 | } | |
2297 | } | |
2298 | goto do_arith_costs; | |
2299 | ||
2300 | case MINUS: | |
2301 | case AND: | |
2302 | case IOR: | |
2303 | case XOR: | |
2304 | case NOT: | |
2305 | case NEG: | |
2306 | case ZERO_EXTEND: | |
2307 | case SIGN_EXTEND: | |
2308 | case COMPARE: | |
2309 | case BSWAP: | |
2310 | case CLZ: | |
2311 | do_arith_costs: | |
2312 | total = (speed ? COSTS_N_INSNS (1) : 2); | |
2313 | break; | |
fe7496dd | 2314 | |
72d6e3c5 RH |
2315 | case ASHIFT: |
2316 | /* Notice the size difference of ASL2 and variants. */ | |
2317 | if (!speed && CONST_INT_P (XEXP (x, 1))) | |
2318 | switch (INTVAL (XEXP (x, 1))) | |
2319 | { | |
2320 | case 1: | |
2321 | case 2: | |
2322 | total = 1; | |
2323 | goto alldone; | |
2324 | case 3: | |
2325 | case 4: | |
2326 | total = 2; | |
2327 | goto alldone; | |
2328 | } | |
2329 | /* FALLTHRU */ | |
fe7496dd | 2330 | |
72d6e3c5 RH |
2331 | case ASHIFTRT: |
2332 | case LSHIFTRT: | |
2333 | total = (speed ? COSTS_N_INSNS (1) : 3); | |
2334 | goto alldone; | |
fe7496dd | 2335 | |
72d6e3c5 RH |
2336 | case MULT: |
2337 | total = (speed ? COSTS_N_INSNS (3) : 2); | |
fe7496dd | 2338 | break; |
5abc5de9 | 2339 | |
72d6e3c5 RH |
2340 | case DIV: |
2341 | case UDIV: | |
2342 | case MOD: | |
2343 | case UMOD: | |
2344 | total = (speed ? COSTS_N_INSNS (39) | |
2345 | /* Include space to load+retrieve MDR. */ | |
2346 | : code == MOD || code == UMOD ? 6 : 4); | |
fe7496dd | 2347 | break; |
5abc5de9 | 2348 | |
72d6e3c5 RH |
2349 | case MEM: |
2350 | total = mn10300_address_cost (XEXP (x, 0), speed); | |
2351 | if (speed) | |
2352 | total = COSTS_N_INSNS (2 + total); | |
2353 | goto alldone; | |
2354 | ||
fe7496dd | 2355 | default: |
72d6e3c5 RH |
2356 | /* Probably not implemented. Assume external call. */ |
2357 | total = (speed ? COSTS_N_INSNS (10) : 7); | |
2358 | break; | |
fe7496dd AO |
2359 | } |
2360 | ||
72d6e3c5 RH |
2361 | *ptotal = total; |
2362 | return false; | |
2363 | ||
2364 | alldone: | |
2365 | *ptotal = total; | |
2366 | return true; | |
fe7496dd | 2367 | } |
72d6e3c5 | 2368 | |
d1776069 AO |
2369 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2370 | may access it using GOTOFF instead of GOT. */ | |
2371 | ||
2372 | static void | |
3bc5e4ef | 2373 | mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED) |
d1776069 AO |
2374 | { |
2375 | rtx symbol; | |
2376 | ||
e7ab5593 | 2377 | if (! MEM_P (rtl)) |
d1776069 AO |
2378 | return; |
2379 | symbol = XEXP (rtl, 0); | |
2380 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2381 | return; | |
2382 | ||
2383 | if (flag_pic) | |
2384 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2385 | } | |
e6ff3083 AS |
2386 | |
2387 | /* Dispatch tables on the mn10300 are extremely expensive in terms of code | |
2388 | and readonly data size. So we crank up the case threshold value to | |
2389 | encourage a series of if/else comparisons to implement many small switch | |
2390 | statements. In theory, this value could be increased much more if we | |
2391 | were solely optimizing for space, but we keep it "reasonable" to avoid | |
2392 | serious code efficiency lossage. */ | |
2393 | ||
4af476d7 NC |
2394 | static unsigned int |
2395 | mn10300_case_values_threshold (void) | |
e6ff3083 AS |
2396 | { |
2397 | return 6; | |
2398 | } | |
bdeb5f0c | 2399 | |
bdeb5f0c RH |
2400 | /* Worker function for TARGET_TRAMPOLINE_INIT. */ |
2401 | ||
2402 | static void | |
2403 | mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2404 | { | |
d6a3e264 RH |
2405 | rtx mem, disp, fnaddr = XEXP (DECL_RTL (fndecl), 0); |
2406 | ||
2407 | /* This is a strict alignment target, which means that we play | |
2408 | some games to make sure that the locations at which we need | |
2409 | to store <chain> and <disp> wind up at aligned addresses. | |
2410 | ||
2411 | 0x28 0x00 add 0,d0 | |
2412 | 0xfc 0xdd mov chain,a1 | |
2413 | <chain> | |
2414 | 0xf8 0xed 0x00 btst 0,d1 | |
2415 | 0xdc jmp fnaddr | |
2416 | <disp> | |
2417 | ||
2418 | Note that the two extra insns are effectively nops; they | |
2419 | clobber the flags but do not affect the contents of D0 or D1. */ | |
bdeb5f0c | 2420 | |
d6a3e264 RH |
2421 | disp = expand_binop (SImode, sub_optab, fnaddr, |
2422 | plus_constant (XEXP (m_tramp, 0), 11), | |
2423 | NULL_RTX, 1, OPTAB_DIRECT); | |
bdeb5f0c | 2424 | |
d6a3e264 RH |
2425 | mem = adjust_address (m_tramp, SImode, 0); |
2426 | emit_move_insn (mem, gen_int_mode (0xddfc0028, SImode)); | |
2427 | mem = adjust_address (m_tramp, SImode, 4); | |
bdeb5f0c | 2428 | emit_move_insn (mem, chain_value); |
d6a3e264 RH |
2429 | mem = adjust_address (m_tramp, SImode, 8); |
2430 | emit_move_insn (mem, gen_int_mode (0xdc00edf8, SImode)); | |
2431 | mem = adjust_address (m_tramp, SImode, 12); | |
2432 | emit_move_insn (mem, disp); | |
bdeb5f0c | 2433 | } |
990dc016 NC |
2434 | |
2435 | /* Output the assembler code for a C++ thunk function. | |
2436 | THUNK_DECL is the declaration for the thunk function itself, FUNCTION | |
2437 | is the decl for the target function. DELTA is an immediate constant | |
2438 | offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero | |
2439 | the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be | |
2440 | additionally added to THIS. Finally jump to the entry point of | |
2441 | FUNCTION. */ | |
2442 | ||
2443 | static void | |
2444 | mn10300_asm_output_mi_thunk (FILE * file, | |
2445 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2446 | HOST_WIDE_INT delta, | |
2447 | HOST_WIDE_INT vcall_offset, | |
2448 | tree function) | |
2449 | { | |
2450 | const char * _this; | |
2451 | ||
2452 | /* Get the register holding the THIS parameter. Handle the case | |
2453 | where there is a hidden first argument for a returned structure. */ | |
2454 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
2455 | _this = reg_names [FIRST_ARGUMENT_REGNUM + 1]; | |
2456 | else | |
2457 | _this = reg_names [FIRST_ARGUMENT_REGNUM]; | |
2458 | ||
2459 | fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START); | |
2460 | ||
2461 | if (delta) | |
2462 | fprintf (file, "\tadd %d, %s\n", (int) delta, _this); | |
2463 | ||
2464 | if (vcall_offset) | |
2465 | { | |
2466 | const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1]; | |
2467 | ||
2468 | fprintf (file, "\tmov %s, %s\n", _this, scratch); | |
2469 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2470 | fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch); | |
2471 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2472 | fprintf (file, "\tadd %s, %s\n", scratch, _this); | |
2473 | } | |
2474 | ||
2475 | fputs ("\tjmp ", file); | |
2476 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2477 | putc ('\n', file); | |
2478 | } | |
2479 | ||
2480 | /* Return true if mn10300_output_mi_thunk would be able to output the | |
2481 | assembler code for the thunk function specified by the arguments | |
2482 | it is passed, and false otherwise. */ | |
2483 | ||
2484 | static bool | |
2485 | mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2486 | HOST_WIDE_INT delta ATTRIBUTE_UNUSED, | |
2487 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2488 | const_tree function ATTRIBUTE_UNUSED) | |
2489 | { | |
2490 | return true; | |
2491 | } | |
4af476d7 NC |
2492 | |
2493 | bool | |
2494 | mn10300_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) | |
2495 | { | |
2496 | if (REGNO_REG_CLASS (regno) == FP_REGS | |
2497 | || REGNO_REG_CLASS (regno) == FP_ACC_REGS) | |
2498 | /* Do not store integer values in FP registers. */ | |
2499 | return GET_MODE_CLASS (mode) == MODE_FLOAT && ((regno & 1) == 0); | |
2500 | ||
2501 | if (((regno) & 1) == 0 || GET_MODE_SIZE (mode) == 4) | |
2502 | return true; | |
2503 | ||
2504 | if (REGNO_REG_CLASS (regno) == DATA_REGS | |
2505 | || (TARGET_AM33 && REGNO_REG_CLASS (regno) == ADDRESS_REGS) | |
2506 | || REGNO_REG_CLASS (regno) == EXTENDED_REGS) | |
2507 | return GET_MODE_SIZE (mode) <= 4; | |
2508 | ||
2509 | return false; | |
2510 | } | |
2511 | ||
2512 | bool | |
2513 | mn10300_modes_tieable (enum machine_mode mode1, enum machine_mode mode2) | |
2514 | { | |
2515 | if (GET_MODE_CLASS (mode1) == MODE_FLOAT | |
2516 | && GET_MODE_CLASS (mode2) != MODE_FLOAT) | |
2517 | return false; | |
2518 | ||
2519 | if (GET_MODE_CLASS (mode2) == MODE_FLOAT | |
2520 | && GET_MODE_CLASS (mode1) != MODE_FLOAT) | |
2521 | return false; | |
2522 | ||
2523 | if (TARGET_AM33 | |
2524 | || mode1 == mode2 | |
2525 | || (GET_MODE_SIZE (mode1) <= 4 && GET_MODE_SIZE (mode2) <= 4)) | |
2526 | return true; | |
2527 | ||
2528 | return false; | |
2529 | } | |
2530 | ||
2531 | enum machine_mode | |
2532 | mn10300_select_cc_mode (rtx x) | |
2533 | { | |
2534 | return (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) ? CC_FLOATmode : CCmode; | |
2535 | } | |
f3f63737 NC |
2536 | |
2537 | static inline bool | |
2538 | is_load_insn (rtx insn) | |
2539 | { | |
2540 | if (GET_CODE (PATTERN (insn)) != SET) | |
2541 | return false; | |
2542 | ||
2543 | return MEM_P (SET_SRC (PATTERN (insn))); | |
2544 | } | |
2545 | ||
2546 | static inline bool | |
2547 | is_store_insn (rtx insn) | |
2548 | { | |
2549 | if (GET_CODE (PATTERN (insn)) != SET) | |
2550 | return false; | |
2551 | ||
2552 | return MEM_P (SET_DEST (PATTERN (insn))); | |
2553 | } | |
2554 | ||
2555 | /* Update scheduling costs for situations that cannot be | |
2556 | described using the attributes and DFA machinery. | |
2557 | DEP is the insn being scheduled. | |
2558 | INSN is the previous insn. | |
2559 | COST is the current cycle cost for DEP. */ | |
2560 | ||
2561 | static int | |
2562 | mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost) | |
2563 | { | |
2564 | int timings = get_attr_timings (insn); | |
2565 | ||
2566 | if (!TARGET_AM33) | |
2567 | return 1; | |
2568 | ||
2569 | if (GET_CODE (insn) == PARALLEL) | |
2570 | insn = XVECEXP (insn, 0, 0); | |
2571 | ||
2572 | if (GET_CODE (dep) == PARALLEL) | |
2573 | dep = XVECEXP (dep, 0, 0); | |
2574 | ||
2575 | /* For the AM34 a load instruction that follows a | |
2576 | store instruction incurs an extra cycle of delay. */ | |
2577 | if (mn10300_tune_cpu == PROCESSOR_AM34 | |
2578 | && is_load_insn (dep) | |
2579 | && is_store_insn (insn)) | |
2580 | cost += 1; | |
2581 | ||
2582 | /* For the AM34 a non-store, non-branch FPU insn that follows | |
2583 | another FPU insn incurs a one cycle throughput increase. */ | |
2584 | else if (mn10300_tune_cpu == PROCESSOR_AM34 | |
2585 | && ! is_store_insn (insn) | |
2586 | && ! JUMP_P (insn) | |
2587 | && GET_CODE (PATTERN (dep)) == SET | |
2588 | && GET_CODE (PATTERN (insn)) == SET | |
2589 | && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) == MODE_FLOAT | |
2590 | && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT) | |
2591 | cost += 1; | |
2592 | ||
2593 | /* Resolve the conflict described in section 1-7-4 of | |
2594 | Chapter 3 of the MN103E Series Instruction Manual | |
2595 | where it says: | |
2596 | ||
2597 | "When the preceeding instruction is a CPU load or | |
2598 | store instruction, a following FPU instruction | |
2599 | cannot be executed until the CPU completes the | |
2600 | latency period even though there are no register | |
2601 | or flag dependencies between them." */ | |
2602 | ||
2603 | /* Only the AM33-2 (and later) CPUs have FPU instructions. */ | |
2604 | if (! TARGET_AM33_2) | |
2605 | return cost; | |
2606 | ||
2607 | /* If a data dependence already exists then the cost is correct. */ | |
2608 | if (REG_NOTE_KIND (link) == 0) | |
2609 | return cost; | |
2610 | ||
2611 | /* Check that the instruction about to scheduled is an FPU instruction. */ | |
2612 | if (GET_CODE (PATTERN (dep)) != SET) | |
2613 | return cost; | |
2614 | ||
2615 | if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) != MODE_FLOAT) | |
2616 | return cost; | |
2617 | ||
2618 | /* Now check to see if the previous instruction is a load or store. */ | |
2619 | if (! is_load_insn (insn) && ! is_store_insn (insn)) | |
2620 | return cost; | |
2621 | ||
2622 | /* XXX: Verify: The text of 1-7-4 implies that the restriction | |
2623 | only applies when an INTEGER load/store preceeds an FPU | |
2624 | instruction, but is this true ? For now we assume that it is. */ | |
2625 | if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT) | |
2626 | return cost; | |
2627 | ||
2628 | /* Extract the latency value from the timings attribute. */ | |
2629 | return timings < 100 ? (timings % 10) : (timings % 100); | |
2630 | } | |
5efd84c5 NF |
2631 | |
2632 | static void | |
2633 | mn10300_conditional_register_usage (void) | |
2634 | { | |
2635 | unsigned int i; | |
2636 | ||
2637 | if (!TARGET_AM33) | |
2638 | { | |
2639 | for (i = FIRST_EXTENDED_REGNUM; | |
2640 | i <= LAST_EXTENDED_REGNUM; i++) | |
2641 | fixed_regs[i] = call_used_regs[i] = 1; | |
2642 | } | |
2643 | if (!TARGET_AM33_2) | |
2644 | { | |
2645 | for (i = FIRST_FP_REGNUM; | |
2646 | i <= LAST_FP_REGNUM; i++) | |
2647 | fixed_regs[i] = call_used_regs[i] = 1; | |
2648 | } | |
2649 | if (flag_pic) | |
2650 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = | |
2651 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
2652 | } | |
4af476d7 | 2653 | \f |
e7ab5593 NC |
2654 | /* Initialize the GCC target structure. */ |
2655 | ||
2656 | #undef TARGET_EXCEPT_UNWIND_INFO | |
2657 | #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info | |
2658 | ||
2659 | #undef TARGET_ASM_ALIGNED_HI_OP | |
2660 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
2661 | ||
2662 | #undef TARGET_LEGITIMIZE_ADDRESS | |
2663 | #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address | |
2664 | ||
72d6e3c5 RH |
2665 | #undef TARGET_ADDRESS_COST |
2666 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
2667 | #undef TARGET_REGISTER_MOVE_COST | |
2668 | #define TARGET_REGISTER_MOVE_COST mn10300_register_move_cost | |
2669 | #undef TARGET_MEMORY_MOVE_COST | |
2670 | #define TARGET_MEMORY_MOVE_COST mn10300_memory_move_cost | |
e7ab5593 NC |
2671 | #undef TARGET_RTX_COSTS |
2672 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
e7ab5593 NC |
2673 | |
2674 | #undef TARGET_ASM_FILE_START | |
2675 | #define TARGET_ASM_FILE_START mn10300_file_start | |
2676 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
2677 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
2678 | ||
535bd17c AS |
2679 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
2680 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA mn10300_asm_output_addr_const_extra | |
2681 | ||
e7ab5593 NC |
2682 | #undef TARGET_DEFAULT_TARGET_FLAGS |
2683 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0 | |
2684 | #undef TARGET_HANDLE_OPTION | |
2685 | #define TARGET_HANDLE_OPTION mn10300_handle_option | |
2686 | #undef TARGET_OPTION_OVERRIDE | |
2687 | #define TARGET_OPTION_OVERRIDE mn10300_option_override | |
3020190e JM |
2688 | #undef TARGET_OPTION_OPTIMIZATION_TABLE |
2689 | #define TARGET_OPTION_OPTIMIZATION_TABLE mn10300_option_optimization_table | |
e7ab5593 NC |
2690 | |
2691 | #undef TARGET_ENCODE_SECTION_INFO | |
2692 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
2693 | ||
2694 | #undef TARGET_PROMOTE_PROTOTYPES | |
2695 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
2696 | #undef TARGET_RETURN_IN_MEMORY | |
2697 | #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory | |
2698 | #undef TARGET_PASS_BY_REFERENCE | |
2699 | #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference | |
2700 | #undef TARGET_CALLEE_COPIES | |
2701 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
2702 | #undef TARGET_ARG_PARTIAL_BYTES | |
2703 | #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes | |
ce236858 NF |
2704 | #undef TARGET_FUNCTION_ARG |
2705 | #define TARGET_FUNCTION_ARG mn10300_function_arg | |
2706 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
2707 | #define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance | |
e7ab5593 NC |
2708 | |
2709 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
2710 | #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs | |
2711 | #undef TARGET_EXPAND_BUILTIN_VA_START | |
2712 | #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start | |
2713 | ||
2714 | #undef TARGET_CASE_VALUES_THRESHOLD | |
2715 | #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold | |
2716 | ||
2717 | #undef TARGET_LEGITIMATE_ADDRESS_P | |
2718 | #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p | |
2719 | ||
f2831cc9 AS |
2720 | #undef TARGET_PREFERRED_RELOAD_CLASS |
2721 | #define TARGET_PREFERRED_RELOAD_CLASS mn10300_preferred_reload_class | |
2722 | #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS | |
2723 | #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS mn10300_preferred_output_reload_class | |
2724 | ||
e7ab5593 NC |
2725 | #undef TARGET_TRAMPOLINE_INIT |
2726 | #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init | |
2727 | ||
2728 | #undef TARGET_FUNCTION_VALUE | |
2729 | #define TARGET_FUNCTION_VALUE mn10300_function_value | |
2730 | #undef TARGET_LIBCALL_VALUE | |
2731 | #define TARGET_LIBCALL_VALUE mn10300_libcall_value | |
2732 | ||
2733 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
2734 | #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk | |
2735 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
2736 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk | |
2737 | ||
f3f63737 NC |
2738 | #undef TARGET_SCHED_ADJUST_COST |
2739 | #define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost | |
2740 | ||
5efd84c5 NF |
2741 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
2742 | #define TARGET_CONDITIONAL_REGISTER_USAGE mn10300_conditional_register_usage | |
2743 | ||
e7ab5593 | 2744 | struct gcc_target targetm = TARGET_INITIALIZER; |