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29a404f9 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
3072d30e | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, |
7cf0dbf3 | 3 | 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. |
29a404f9 | 4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
3626e955 | 6 | This file is part of GCC. |
29a404f9 | 7 | |
3626e955 | 8 | GCC is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
29a404f9 | 12 | |
3626e955 | 13 | GCC is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
29a404f9 | 17 | |
3626e955 | 18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
29a404f9 | 21 | |
29a404f9 | 22 | #include "config.h" |
7014838c | 23 | #include "system.h" |
805e22b2 | 24 | #include "coretypes.h" |
25 | #include "tm.h" | |
29a404f9 | 26 | #include "rtl.h" |
4faf81b8 | 27 | #include "tree.h" |
29a404f9 | 28 | #include "regs.h" |
29 | #include "hard-reg-set.h" | |
29a404f9 | 30 | #include "insn-config.h" |
31 | #include "conditions.h" | |
29a404f9 | 32 | #include "output.h" |
33 | #include "insn-attr.h" | |
34 | #include "flags.h" | |
35 | #include "recog.h" | |
8b8be022 | 36 | #include "reload.h" |
29a404f9 | 37 | #include "expr.h" |
d8fc4d0b | 38 | #include "optabs.h" |
4faf81b8 | 39 | #include "function.h" |
29a404f9 | 40 | #include "obstack.h" |
0b205f4c | 41 | #include "diagnostic-core.h" |
59086782 | 42 | #include "toplev.h" |
43 | #include "tm_p.h" | |
a767736d | 44 | #include "target.h" |
45 | #include "target-def.h" | |
5574dbdd | 46 | #include "df.h" |
29a404f9 | 47 | |
b87a151a | 48 | /* This is used by GOTaddr2picreg to uniquely identify |
49 | UNSPEC_INT_LABELs. */ | |
50 | int mn10300_unspec_int_label_counter; | |
51 | ||
1acdfc69 | 52 | /* This is used in the am33_2.0-linux-gnu port, in which global symbol |
53 | names are not prefixed by underscores, to tell whether to prefix a | |
54 | label with a plus sign or not, so that the assembler can tell | |
55 | symbol names from register names. */ | |
56 | int mn10300_protect_label; | |
57 | ||
8c2c40c5 | 58 | /* The selected processor. */ |
59 | enum processor_type mn10300_processor = PROCESSOR_DEFAULT; | |
60 | ||
8ecf154e | 61 | /* The size of the callee register save area. Right now we save everything |
62 | on entry since it costs us nothing in code size. It does cost us from a | |
63 | speed standpoint, so we want to optimize this sooner or later. */ | |
3626e955 | 64 | #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \ |
65 | + 4 * df_regs_ever_live_p (3) \ | |
66 | + 4 * df_regs_ever_live_p (6) \ | |
67 | + 4 * df_regs_ever_live_p (7) \ | |
68 | + 16 * (df_regs_ever_live_p (14) \ | |
69 | || df_regs_ever_live_p (15) \ | |
70 | || df_regs_ever_live_p (16) \ | |
71 | || df_regs_ever_live_p (17))) | |
e92d3ba8 | 72 | |
3626e955 | 73 | static int mn10300_address_cost (rtx, bool); |
c17f64cc | 74 | |
75 | /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ | |
76 | static const struct default_options mn10300_option_optimization_table[] = | |
77 | { | |
78 | { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, | |
79 | { OPT_LEVELS_NONE, 0, NULL, 0 } | |
80 | }; | |
a767736d | 81 | \f |
8c2c40c5 | 82 | /* Implement TARGET_HANDLE_OPTION. */ |
83 | ||
84 | static bool | |
85 | mn10300_handle_option (size_t code, | |
86 | const char *arg ATTRIBUTE_UNUSED, | |
87 | int value) | |
88 | { | |
89 | switch (code) | |
90 | { | |
91 | case OPT_mam33: | |
92 | mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300; | |
93 | return true; | |
94 | case OPT_mam33_2: | |
95 | mn10300_processor = (value | |
96 | ? PROCESSOR_AM33_2 | |
97 | : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT)); | |
98 | return true; | |
99 | default: | |
100 | return true; | |
101 | } | |
102 | } | |
103 | ||
4c834714 | 104 | /* Implement TARGET_OPTION_OVERRIDE. */ |
8c2c40c5 | 105 | |
4c834714 | 106 | static void |
107 | mn10300_option_override (void) | |
8c2c40c5 | 108 | { |
109 | if (TARGET_AM33) | |
110 | target_flags &= ~MASK_MULT_BUG; | |
111 | } | |
112 | ||
92c473b8 | 113 | static void |
3285410a | 114 | mn10300_file_start (void) |
29a404f9 | 115 | { |
92c473b8 | 116 | default_file_start (); |
911517ac | 117 | |
b166356e | 118 | if (TARGET_AM33_2) |
119 | fprintf (asm_out_file, "\t.am33_2\n"); | |
120 | else if (TARGET_AM33) | |
92c473b8 | 121 | fprintf (asm_out_file, "\t.am33\n"); |
29a404f9 | 122 | } |
123 | \f | |
29a404f9 | 124 | /* Print operand X using operand code CODE to assembly language output file |
125 | FILE. */ | |
126 | ||
127 | void | |
3626e955 | 128 | mn10300_print_operand (FILE *file, rtx x, int code) |
29a404f9 | 129 | { |
130 | switch (code) | |
131 | { | |
132 | case 'b': | |
133 | case 'B': | |
5574dbdd | 134 | if (GET_MODE (XEXP (x, 0)) == CC_FLOATmode) |
b166356e | 135 | { |
136 | switch (code == 'b' ? GET_CODE (x) | |
137 | : reverse_condition_maybe_unordered (GET_CODE (x))) | |
138 | { | |
139 | case NE: | |
140 | fprintf (file, "ne"); | |
141 | break; | |
142 | case EQ: | |
143 | fprintf (file, "eq"); | |
144 | break; | |
145 | case GE: | |
146 | fprintf (file, "ge"); | |
147 | break; | |
148 | case GT: | |
149 | fprintf (file, "gt"); | |
150 | break; | |
151 | case LE: | |
152 | fprintf (file, "le"); | |
153 | break; | |
154 | case LT: | |
155 | fprintf (file, "lt"); | |
156 | break; | |
157 | case ORDERED: | |
158 | fprintf (file, "lge"); | |
159 | break; | |
160 | case UNORDERED: | |
161 | fprintf (file, "uo"); | |
162 | break; | |
163 | case LTGT: | |
164 | fprintf (file, "lg"); | |
165 | break; | |
166 | case UNEQ: | |
167 | fprintf (file, "ue"); | |
168 | break; | |
169 | case UNGE: | |
170 | fprintf (file, "uge"); | |
171 | break; | |
172 | case UNGT: | |
173 | fprintf (file, "ug"); | |
174 | break; | |
175 | case UNLE: | |
176 | fprintf (file, "ule"); | |
177 | break; | |
178 | case UNLT: | |
179 | fprintf (file, "ul"); | |
180 | break; | |
181 | default: | |
cf41bb03 | 182 | gcc_unreachable (); |
b166356e | 183 | } |
184 | break; | |
185 | } | |
29a404f9 | 186 | /* These are normal and reversed branches. */ |
187 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
188 | { | |
189 | case NE: | |
190 | fprintf (file, "ne"); | |
191 | break; | |
192 | case EQ: | |
193 | fprintf (file, "eq"); | |
194 | break; | |
195 | case GE: | |
196 | fprintf (file, "ge"); | |
197 | break; | |
198 | case GT: | |
199 | fprintf (file, "gt"); | |
200 | break; | |
201 | case LE: | |
202 | fprintf (file, "le"); | |
203 | break; | |
204 | case LT: | |
205 | fprintf (file, "lt"); | |
206 | break; | |
207 | case GEU: | |
208 | fprintf (file, "cc"); | |
209 | break; | |
210 | case GTU: | |
211 | fprintf (file, "hi"); | |
212 | break; | |
213 | case LEU: | |
214 | fprintf (file, "ls"); | |
215 | break; | |
216 | case LTU: | |
217 | fprintf (file, "cs"); | |
218 | break; | |
219 | default: | |
cf41bb03 | 220 | gcc_unreachable (); |
29a404f9 | 221 | } |
222 | break; | |
223 | case 'C': | |
224 | /* This is used for the operand to a call instruction; | |
225 | if it's a REG, enclose it in parens, else output | |
226 | the operand normally. */ | |
3626e955 | 227 | if (REG_P (x)) |
29a404f9 | 228 | { |
229 | fputc ('(', file); | |
3626e955 | 230 | mn10300_print_operand (file, x, 0); |
29a404f9 | 231 | fputc (')', file); |
232 | } | |
233 | else | |
3626e955 | 234 | mn10300_print_operand (file, x, 0); |
29a404f9 | 235 | break; |
fb16c776 | 236 | |
b166356e | 237 | case 'D': |
238 | switch (GET_CODE (x)) | |
239 | { | |
240 | case MEM: | |
241 | fputc ('(', file); | |
242 | output_address (XEXP (x, 0)); | |
243 | fputc (')', file); | |
244 | break; | |
245 | ||
246 | case REG: | |
247 | fprintf (file, "fd%d", REGNO (x) - 18); | |
248 | break; | |
249 | ||
250 | default: | |
cf41bb03 | 251 | gcc_unreachable (); |
b166356e | 252 | } |
253 | break; | |
254 | ||
6ce19398 | 255 | /* These are the least significant word in a 64bit value. */ |
256 | case 'L': | |
257 | switch (GET_CODE (x)) | |
258 | { | |
259 | case MEM: | |
260 | fputc ('(', file); | |
261 | output_address (XEXP (x, 0)); | |
262 | fputc (')', file); | |
263 | break; | |
264 | ||
265 | case REG: | |
266 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
267 | break; | |
268 | ||
269 | case SUBREG: | |
701e46d0 | 270 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
6ce19398 | 271 | break; |
272 | ||
273 | case CONST_DOUBLE: | |
274 | { | |
275 | long val[2]; | |
276 | REAL_VALUE_TYPE rv; | |
277 | ||
278 | switch (GET_MODE (x)) | |
279 | { | |
280 | case DFmode: | |
281 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
282 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 283 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 284 | break;; |
285 | case SFmode: | |
286 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
287 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
ad3c0f03 | 288 | fprintf (file, "0x%lx", val[0]); |
6ce19398 | 289 | break;; |
290 | case VOIDmode: | |
291 | case DImode: | |
3626e955 | 292 | mn10300_print_operand_address (file, |
293 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
6ce19398 | 294 | break; |
59086782 | 295 | default: |
296 | break; | |
6ce19398 | 297 | } |
298 | break; | |
299 | } | |
300 | ||
301 | case CONST_INT: | |
964d057c | 302 | { |
303 | rtx low, high; | |
304 | split_double (x, &low, &high); | |
305 | fprintf (file, "%ld", (long)INTVAL (low)); | |
306 | break; | |
307 | } | |
6ce19398 | 308 | |
309 | default: | |
cf41bb03 | 310 | gcc_unreachable (); |
6ce19398 | 311 | } |
312 | break; | |
313 | ||
314 | /* Similarly, but for the most significant word. */ | |
315 | case 'H': | |
316 | switch (GET_CODE (x)) | |
317 | { | |
318 | case MEM: | |
319 | fputc ('(', file); | |
eafc6604 | 320 | x = adjust_address (x, SImode, 4); |
6ce19398 | 321 | output_address (XEXP (x, 0)); |
322 | fputc (')', file); | |
323 | break; | |
324 | ||
325 | case REG: | |
326 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
327 | break; | |
328 | ||
329 | case SUBREG: | |
701e46d0 | 330 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
6ce19398 | 331 | break; |
332 | ||
333 | case CONST_DOUBLE: | |
334 | { | |
335 | long val[2]; | |
336 | REAL_VALUE_TYPE rv; | |
337 | ||
338 | switch (GET_MODE (x)) | |
339 | { | |
340 | case DFmode: | |
341 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
342 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
ad3c0f03 | 343 | fprintf (file, "0x%lx", val[1]); |
6ce19398 | 344 | break;; |
345 | case SFmode: | |
cf41bb03 | 346 | gcc_unreachable (); |
6ce19398 | 347 | case VOIDmode: |
348 | case DImode: | |
3626e955 | 349 | mn10300_print_operand_address (file, |
350 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
6ce19398 | 351 | break; |
59086782 | 352 | default: |
353 | break; | |
6ce19398 | 354 | } |
355 | break; | |
356 | } | |
357 | ||
358 | case CONST_INT: | |
964d057c | 359 | { |
360 | rtx low, high; | |
361 | split_double (x, &low, &high); | |
362 | fprintf (file, "%ld", (long)INTVAL (high)); | |
363 | break; | |
364 | } | |
365 | ||
6ce19398 | 366 | default: |
cf41bb03 | 367 | gcc_unreachable (); |
6ce19398 | 368 | } |
369 | break; | |
370 | ||
371 | case 'A': | |
372 | fputc ('(', file); | |
3626e955 | 373 | if (REG_P ((XEXP (x, 0)))) |
bcd9bd66 | 374 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx)); |
6ce19398 | 375 | else |
376 | output_address (XEXP (x, 0)); | |
377 | fputc (')', file); | |
378 | break; | |
379 | ||
167fa942 | 380 | case 'N': |
cf41bb03 | 381 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
058f71f0 | 382 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); |
383 | break; | |
384 | ||
385 | case 'U': | |
cf41bb03 | 386 | gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255); |
058f71f0 | 387 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); |
167fa942 | 388 | break; |
389 | ||
63e678f2 | 390 | /* For shift counts. The hardware ignores the upper bits of |
391 | any immediate, but the assembler will flag an out of range | |
392 | shift count as an error. So we mask off the high bits | |
393 | of the immediate here. */ | |
394 | case 'S': | |
3626e955 | 395 | if (CONST_INT_P ((x))) |
63e678f2 | 396 | { |
058f71f0 | 397 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
63e678f2 | 398 | break; |
399 | } | |
400 | /* FALL THROUGH */ | |
401 | ||
29a404f9 | 402 | default: |
403 | switch (GET_CODE (x)) | |
404 | { | |
405 | case MEM: | |
406 | fputc ('(', file); | |
407 | output_address (XEXP (x, 0)); | |
408 | fputc (')', file); | |
409 | break; | |
410 | ||
6ce19398 | 411 | case PLUS: |
412 | output_address (x); | |
413 | break; | |
414 | ||
29a404f9 | 415 | case REG: |
416 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
417 | break; | |
418 | ||
419 | case SUBREG: | |
701e46d0 | 420 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
29a404f9 | 421 | break; |
422 | ||
6ce19398 | 423 | /* This will only be single precision.... */ |
424 | case CONST_DOUBLE: | |
425 | { | |
426 | unsigned long val; | |
427 | REAL_VALUE_TYPE rv; | |
428 | ||
429 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
430 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
ad3c0f03 | 431 | fprintf (file, "0x%lx", val); |
6ce19398 | 432 | break; |
433 | } | |
434 | ||
29a404f9 | 435 | case CONST_INT: |
436 | case SYMBOL_REF: | |
437 | case CONST: | |
438 | case LABEL_REF: | |
439 | case CODE_LABEL: | |
b87a151a | 440 | case UNSPEC: |
3626e955 | 441 | mn10300_print_operand_address (file, x); |
29a404f9 | 442 | break; |
443 | default: | |
cf41bb03 | 444 | gcc_unreachable (); |
29a404f9 | 445 | } |
446 | break; | |
447 | } | |
448 | } | |
449 | ||
450 | /* Output assembly language output for the address ADDR to FILE. */ | |
451 | ||
452 | void | |
3626e955 | 453 | mn10300_print_operand_address (FILE *file, rtx addr) |
29a404f9 | 454 | { |
455 | switch (GET_CODE (addr)) | |
456 | { | |
911517ac | 457 | case POST_INC: |
3626e955 | 458 | mn10300_print_operand_address (file, XEXP (addr, 0)); |
911517ac | 459 | fputc ('+', file); |
460 | break; | |
29a404f9 | 461 | case REG: |
3626e955 | 462 | mn10300_print_operand (file, addr, 0); |
29a404f9 | 463 | break; |
464 | case PLUS: | |
465 | { | |
466 | rtx base, index; | |
467 | if (REG_P (XEXP (addr, 0)) | |
468 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
469 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
470 | else if (REG_P (XEXP (addr, 1)) | |
471 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
472 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
473 | else | |
cf41bb03 | 474 | gcc_unreachable (); |
3626e955 | 475 | mn10300_print_operand (file, index, 0); |
29a404f9 | 476 | fputc (',', file); |
3626e955 | 477 | mn10300_print_operand (file, base, 0);; |
29a404f9 | 478 | break; |
479 | } | |
480 | case SYMBOL_REF: | |
481 | output_addr_const (file, addr); | |
482 | break; | |
483 | default: | |
484 | output_addr_const (file, addr); | |
485 | break; | |
486 | } | |
487 | } | |
488 | ||
b166356e | 489 | /* Count the number of FP registers that have to be saved. */ |
490 | static int | |
3285410a | 491 | fp_regs_to_save (void) |
b166356e | 492 | { |
493 | int i, n = 0; | |
494 | ||
495 | if (! TARGET_AM33_2) | |
496 | return 0; | |
497 | ||
498 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
d37e81ec | 499 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
b166356e | 500 | ++n; |
501 | ||
502 | return n; | |
503 | } | |
504 | ||
4caa3669 | 505 | /* Print a set of registers in the format required by "movm" and "ret". |
506 | Register K is saved if bit K of MASK is set. The data and address | |
507 | registers can be stored individually, but the extended registers cannot. | |
f2b32076 | 508 | We assume that the mask already takes that into account. For instance, |
09e5ce26 | 509 | bits 14 to 17 must have the same value. */ |
4caa3669 | 510 | |
511 | void | |
3285410a | 512 | mn10300_print_reg_list (FILE *file, int mask) |
4caa3669 | 513 | { |
514 | int need_comma; | |
515 | int i; | |
516 | ||
517 | need_comma = 0; | |
518 | fputc ('[', file); | |
519 | ||
520 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
521 | if ((mask & (1 << i)) != 0) | |
522 | { | |
523 | if (need_comma) | |
524 | fputc (',', file); | |
525 | fputs (reg_names [i], file); | |
526 | need_comma = 1; | |
527 | } | |
528 | ||
529 | if ((mask & 0x3c000) != 0) | |
530 | { | |
cf41bb03 | 531 | gcc_assert ((mask & 0x3c000) == 0x3c000); |
4caa3669 | 532 | if (need_comma) |
533 | fputc (',', file); | |
534 | fputs ("exreg1", file); | |
535 | need_comma = 1; | |
536 | } | |
537 | ||
538 | fputc (']', file); | |
539 | } | |
540 | ||
6ce19398 | 541 | int |
3626e955 | 542 | mn10300_can_use_return_insn (void) |
6ce19398 | 543 | { |
36ed4406 | 544 | /* size includes the fixed stack space needed for function calls. */ |
abe32cce | 545 | int size = get_frame_size () + crtl->outgoing_args_size; |
36ed4406 | 546 | |
547 | /* And space for the return pointer. */ | |
abe32cce | 548 | size += crtl->outgoing_args_size ? 4 : 0; |
6ce19398 | 549 | |
550 | return (reload_completed | |
551 | && size == 0 | |
3072d30e | 552 | && !df_regs_ever_live_p (2) |
553 | && !df_regs_ever_live_p (3) | |
554 | && !df_regs_ever_live_p (6) | |
555 | && !df_regs_ever_live_p (7) | |
556 | && !df_regs_ever_live_p (14) | |
557 | && !df_regs_ever_live_p (15) | |
558 | && !df_regs_ever_live_p (16) | |
559 | && !df_regs_ever_live_p (17) | |
b166356e | 560 | && fp_regs_to_save () == 0 |
6ce19398 | 561 | && !frame_pointer_needed); |
562 | } | |
563 | ||
4caa3669 | 564 | /* Returns the set of live, callee-saved registers as a bitmask. The |
565 | callee-saved extended registers cannot be stored individually, so | |
09e5ce26 | 566 | all of them will be included in the mask if any one of them is used. */ |
4caa3669 | 567 | |
568 | int | |
3285410a | 569 | mn10300_get_live_callee_saved_regs (void) |
4caa3669 | 570 | { |
571 | int mask; | |
572 | int i; | |
573 | ||
574 | mask = 0; | |
b166356e | 575 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
d37e81ec | 576 | if (df_regs_ever_live_p (i) && ! call_really_used_regs[i]) |
4caa3669 | 577 | mask |= (1 << i); |
578 | if ((mask & 0x3c000) != 0) | |
579 | mask |= 0x3c000; | |
580 | ||
581 | return mask; | |
582 | } | |
583 | ||
5f2853dd | 584 | static rtx |
585 | F (rtx r) | |
586 | { | |
587 | RTX_FRAME_RELATED_P (r) = 1; | |
588 | return r; | |
589 | } | |
590 | ||
4caa3669 | 591 | /* Generate an instruction that pushes several registers onto the stack. |
592 | Register K will be saved if bit K in MASK is set. The function does | |
593 | nothing if MASK is zero. | |
594 | ||
595 | To be compatible with the "movm" instruction, the lowest-numbered | |
596 | register must be stored in the lowest slot. If MASK is the set | |
597 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
598 | instruction will have the form: | |
599 | ||
600 | (parallel | |
601 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
602 | (set (mem:SI (plus:SI (reg:SI 9) | |
603 | (const_int -1*4))) | |
604 | (reg:SI RN)) | |
605 | ... | |
606 | (set (mem:SI (plus:SI (reg:SI 9) | |
607 | (const_int -N*4))) | |
608 | (reg:SI R1))) */ | |
609 | ||
610 | void | |
3285410a | 611 | mn10300_gen_multiple_store (int mask) |
4caa3669 | 612 | { |
613 | if (mask != 0) | |
614 | { | |
615 | int i; | |
616 | int count; | |
617 | rtx par; | |
618 | int pari; | |
619 | ||
09e5ce26 | 620 | /* Count how many registers need to be saved. */ |
4caa3669 | 621 | count = 0; |
b166356e | 622 | for (i = 0; i <= LAST_EXTENDED_REGNUM; i++) |
4caa3669 | 623 | if ((mask & (1 << i)) != 0) |
624 | count += 1; | |
625 | ||
626 | /* We need one PARALLEL element to update the stack pointer and | |
09e5ce26 | 627 | an additional element for each register that is stored. */ |
4caa3669 | 628 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
629 | ||
09e5ce26 | 630 | /* Create the instruction that updates the stack pointer. */ |
4caa3669 | 631 | XVECEXP (par, 0, 0) |
5f2853dd | 632 | = F (gen_rtx_SET (SImode, |
633 | stack_pointer_rtx, | |
634 | gen_rtx_PLUS (SImode, | |
635 | stack_pointer_rtx, | |
636 | GEN_INT (-count * 4)))); | |
4caa3669 | 637 | |
09e5ce26 | 638 | /* Create each store. */ |
4caa3669 | 639 | pari = 1; |
b166356e | 640 | for (i = LAST_EXTENDED_REGNUM; i >= 0; i--) |
4caa3669 | 641 | if ((mask & (1 << i)) != 0) |
642 | { | |
643 | rtx address = gen_rtx_PLUS (SImode, | |
644 | stack_pointer_rtx, | |
645 | GEN_INT (-pari * 4)); | |
646 | XVECEXP(par, 0, pari) | |
5f2853dd | 647 | = F (gen_rtx_SET (VOIDmode, |
648 | gen_rtx_MEM (SImode, address), | |
649 | gen_rtx_REG (SImode, i))); | |
4caa3669 | 650 | pari += 1; |
651 | } | |
652 | ||
5f2853dd | 653 | F (emit_insn (par)); |
4caa3669 | 654 | } |
655 | } | |
656 | ||
29a404f9 | 657 | void |
3626e955 | 658 | mn10300_expand_prologue (void) |
29a404f9 | 659 | { |
e3f95b40 | 660 | HOST_WIDE_INT size; |
f1899bff | 661 | |
f1899bff | 662 | /* SIZE includes the fixed stack space needed for function calls. */ |
abe32cce | 663 | size = get_frame_size () + crtl->outgoing_args_size; |
664 | size += (crtl->outgoing_args_size ? 4 : 0); | |
29a404f9 | 665 | |
09e5ce26 | 666 | /* If we use any of the callee-saved registers, save them now. */ |
4caa3669 | 667 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); |
48cb86e3 | 668 | |
b166356e | 669 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
670 | { | |
671 | int num_regs_to_save = fp_regs_to_save (), i; | |
672 | HOST_WIDE_INT xsize; | |
3626e955 | 673 | enum |
674 | { | |
675 | save_sp_merge, | |
676 | save_sp_no_merge, | |
677 | save_sp_partial_merge, | |
678 | save_a0_merge, | |
679 | save_a0_no_merge | |
680 | } strategy; | |
b166356e | 681 | unsigned int strategy_size = (unsigned)-1, this_strategy_size; |
682 | rtx reg; | |
b166356e | 683 | |
684 | /* We have several different strategies to save FP registers. | |
685 | We can store them using SP offsets, which is beneficial if | |
686 | there are just a few registers to save, or we can use `a0' in | |
687 | post-increment mode (`a0' is the only call-clobbered address | |
688 | register that is never used to pass information to a | |
689 | function). Furthermore, if we don't need a frame pointer, we | |
690 | can merge the two SP adds into a single one, but this isn't | |
691 | always beneficial; sometimes we can just split the two adds | |
692 | so that we don't exceed a 16-bit constant size. The code | |
693 | below will select which strategy to use, so as to generate | |
694 | smallest code. Ties are broken in favor or shorter sequences | |
695 | (in terms of number of instructions). */ | |
696 | ||
697 | #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
698 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2) | |
699 | #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \ | |
700 | : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3) | |
701 | #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \ | |
702 | (((S) >= (L)) ? (SIZE1) * (N) \ | |
703 | : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \ | |
704 | + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \ | |
705 | : (ELSE)) | |
706 | #define SIZE_FMOV_SP_(S,N) \ | |
707 | (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \ | |
708 | SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \ | |
709 | (S) ? 4 * (N) : 3 + 4 * ((N) - 1)))) | |
710 | #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N))) | |
711 | ||
712 | /* Consider alternative save_sp_merge only if we don't need the | |
fa483857 | 713 | frame pointer and size is nonzero. */ |
b166356e | 714 | if (! frame_pointer_needed && size) |
715 | { | |
716 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
717 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
718 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
719 | this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save); | |
720 | ||
721 | if (this_strategy_size < strategy_size) | |
722 | { | |
723 | strategy = save_sp_merge; | |
724 | strategy_size = this_strategy_size; | |
725 | } | |
726 | } | |
727 | ||
728 | /* Consider alternative save_sp_no_merge unconditionally. */ | |
729 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
730 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
731 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
732 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
733 | if (size) | |
734 | { | |
735 | /* Insn: add -size, sp. */ | |
736 | this_strategy_size += SIZE_ADD_SP (-size); | |
737 | } | |
738 | ||
739 | if (this_strategy_size < strategy_size) | |
740 | { | |
741 | strategy = save_sp_no_merge; | |
742 | strategy_size = this_strategy_size; | |
743 | } | |
744 | ||
745 | /* Consider alternative save_sp_partial_merge only if we don't | |
746 | need a frame pointer and size is reasonably large. */ | |
747 | if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128) | |
748 | { | |
749 | /* Insn: add -128, sp. */ | |
750 | this_strategy_size = SIZE_ADD_SP (-128); | |
751 | /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */ | |
752 | this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save, | |
753 | num_regs_to_save); | |
754 | if (size) | |
755 | { | |
756 | /* Insn: add 128-size, sp. */ | |
757 | this_strategy_size += SIZE_ADD_SP (128 - size); | |
758 | } | |
759 | ||
760 | if (this_strategy_size < strategy_size) | |
761 | { | |
762 | strategy = save_sp_partial_merge; | |
763 | strategy_size = this_strategy_size; | |
764 | } | |
765 | } | |
766 | ||
767 | /* Consider alternative save_a0_merge only if we don't need a | |
fa483857 | 768 | frame pointer, size is nonzero and the user hasn't |
b166356e | 769 | changed the calling conventions of a0. */ |
770 | if (! frame_pointer_needed && size | |
d37e81ec | 771 | && call_really_used_regs [FIRST_ADDRESS_REGNUM] |
b166356e | 772 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
773 | { | |
774 | /* Insn: add -(size + 4 * num_regs_to_save), sp. */ | |
775 | this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save)); | |
776 | /* Insn: mov sp, a0. */ | |
777 | this_strategy_size++; | |
778 | if (size) | |
779 | { | |
780 | /* Insn: add size, a0. */ | |
781 | this_strategy_size += SIZE_ADD_AX (size); | |
782 | } | |
783 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
784 | this_strategy_size += 3 * num_regs_to_save; | |
785 | ||
786 | if (this_strategy_size < strategy_size) | |
787 | { | |
788 | strategy = save_a0_merge; | |
789 | strategy_size = this_strategy_size; | |
790 | } | |
791 | } | |
792 | ||
793 | /* Consider alternative save_a0_no_merge if the user hasn't | |
09e5ce26 | 794 | changed the calling conventions of a0. */ |
d37e81ec | 795 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM] |
b166356e | 796 | && ! fixed_regs[FIRST_ADDRESS_REGNUM]) |
797 | { | |
798 | /* Insn: add -4 * num_regs_to_save, sp. */ | |
799 | this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save); | |
800 | /* Insn: mov sp, a0. */ | |
801 | this_strategy_size++; | |
802 | /* Insn: fmov fs#, (a0+), for each fs# to be saved. */ | |
803 | this_strategy_size += 3 * num_regs_to_save; | |
804 | if (size) | |
805 | { | |
806 | /* Insn: add -size, sp. */ | |
807 | this_strategy_size += SIZE_ADD_SP (-size); | |
808 | } | |
809 | ||
810 | if (this_strategy_size < strategy_size) | |
811 | { | |
812 | strategy = save_a0_no_merge; | |
813 | strategy_size = this_strategy_size; | |
814 | } | |
815 | } | |
816 | ||
817 | /* Emit the initial SP add, common to all strategies. */ | |
818 | switch (strategy) | |
819 | { | |
820 | case save_sp_no_merge: | |
821 | case save_a0_no_merge: | |
5f2853dd | 822 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
823 | stack_pointer_rtx, | |
824 | GEN_INT (-4 * num_regs_to_save)))); | |
b166356e | 825 | xsize = 0; |
826 | break; | |
827 | ||
828 | case save_sp_partial_merge: | |
5f2853dd | 829 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
830 | stack_pointer_rtx, | |
831 | GEN_INT (-128)))); | |
b166356e | 832 | xsize = 128 - 4 * num_regs_to_save; |
833 | size -= xsize; | |
834 | break; | |
835 | ||
836 | case save_sp_merge: | |
837 | case save_a0_merge: | |
5f2853dd | 838 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
839 | stack_pointer_rtx, | |
840 | GEN_INT (-(size + 4 * num_regs_to_save))))); | |
b166356e | 841 | /* We'll have to adjust FP register saves according to the |
09e5ce26 | 842 | frame size. */ |
b166356e | 843 | xsize = size; |
844 | /* Since we've already created the stack frame, don't do it | |
09e5ce26 | 845 | again at the end of the function. */ |
b166356e | 846 | size = 0; |
847 | break; | |
848 | ||
849 | default: | |
cf41bb03 | 850 | gcc_unreachable (); |
b166356e | 851 | } |
fb16c776 | 852 | |
b166356e | 853 | /* Now prepare register a0, if we have decided to use it. */ |
854 | switch (strategy) | |
855 | { | |
856 | case save_sp_merge: | |
857 | case save_sp_no_merge: | |
858 | case save_sp_partial_merge: | |
859 | reg = 0; | |
860 | break; | |
861 | ||
862 | case save_a0_merge: | |
863 | case save_a0_no_merge: | |
864 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM); | |
5f2853dd | 865 | F (emit_insn (gen_movsi (reg, stack_pointer_rtx))); |
b166356e | 866 | if (xsize) |
5f2853dd | 867 | F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)))); |
b166356e | 868 | reg = gen_rtx_POST_INC (SImode, reg); |
869 | break; | |
fb16c776 | 870 | |
b166356e | 871 | default: |
cf41bb03 | 872 | gcc_unreachable (); |
b166356e | 873 | } |
fb16c776 | 874 | |
b166356e | 875 | /* Now actually save the FP registers. */ |
876 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
d37e81ec | 877 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
b166356e | 878 | { |
879 | rtx addr; | |
880 | ||
881 | if (reg) | |
882 | addr = reg; | |
883 | else | |
884 | { | |
885 | /* If we aren't using `a0', use an SP offset. */ | |
886 | if (xsize) | |
887 | { | |
888 | addr = gen_rtx_PLUS (SImode, | |
889 | stack_pointer_rtx, | |
890 | GEN_INT (xsize)); | |
891 | } | |
892 | else | |
893 | addr = stack_pointer_rtx; | |
fb16c776 | 894 | |
b166356e | 895 | xsize += 4; |
896 | } | |
897 | ||
5f2853dd | 898 | F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr), |
899 | gen_rtx_REG (SFmode, i)))); | |
b166356e | 900 | } |
901 | } | |
902 | ||
48cb86e3 | 903 | /* Now put the frame pointer into the frame pointer register. */ |
29a404f9 | 904 | if (frame_pointer_needed) |
5f2853dd | 905 | F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx)); |
29a404f9 | 906 | |
48cb86e3 | 907 | /* Allocate stack for this frame. */ |
29a404f9 | 908 | if (size) |
5f2853dd | 909 | F (emit_insn (gen_addsi3 (stack_pointer_rtx, |
910 | stack_pointer_rtx, | |
911 | GEN_INT (-size)))); | |
912 | ||
3072d30e | 913 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
914 | emit_insn (gen_GOTaddr2picreg ()); | |
29a404f9 | 915 | } |
916 | ||
917 | void | |
3626e955 | 918 | mn10300_expand_epilogue (void) |
29a404f9 | 919 | { |
e3f95b40 | 920 | HOST_WIDE_INT size; |
f1899bff | 921 | |
f1899bff | 922 | /* SIZE includes the fixed stack space needed for function calls. */ |
abe32cce | 923 | size = get_frame_size () + crtl->outgoing_args_size; |
924 | size += (crtl->outgoing_args_size ? 4 : 0); | |
5574dbdd | 925 | |
b166356e | 926 | if (TARGET_AM33_2 && fp_regs_to_save ()) |
927 | { | |
928 | int num_regs_to_save = fp_regs_to_save (), i; | |
929 | rtx reg = 0; | |
930 | ||
931 | /* We have several options to restore FP registers. We could | |
932 | load them from SP offsets, but, if there are enough FP | |
933 | registers to restore, we win if we use a post-increment | |
934 | addressing mode. */ | |
935 | ||
936 | /* If we have a frame pointer, it's the best option, because we | |
937 | already know it has the value we want. */ | |
938 | if (frame_pointer_needed) | |
939 | reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM); | |
940 | /* Otherwise, we may use `a1', since it's call-clobbered and | |
941 | it's never used for return values. But only do so if it's | |
942 | smaller than using SP offsets. */ | |
943 | else | |
944 | { | |
945 | enum { restore_sp_post_adjust, | |
946 | restore_sp_pre_adjust, | |
947 | restore_sp_partial_adjust, | |
948 | restore_a1 } strategy; | |
949 | unsigned int this_strategy_size, strategy_size = (unsigned)-1; | |
950 | ||
951 | /* Consider using sp offsets before adjusting sp. */ | |
952 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
953 | this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save); | |
954 | /* If size is too large, we'll have to adjust SP with an | |
955 | add. */ | |
956 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
957 | { | |
958 | /* Insn: add size + 4 * num_regs_to_save, sp. */ | |
959 | this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save); | |
960 | } | |
961 | /* If we don't have to restore any non-FP registers, | |
962 | we'll be able to save one byte by using rets. */ | |
963 | if (! REG_SAVE_BYTES) | |
964 | this_strategy_size--; | |
965 | ||
966 | if (this_strategy_size < strategy_size) | |
967 | { | |
968 | strategy = restore_sp_post_adjust; | |
969 | strategy_size = this_strategy_size; | |
970 | } | |
971 | ||
972 | /* Consider using sp offsets after adjusting sp. */ | |
973 | /* Insn: add size, sp. */ | |
974 | this_strategy_size = SIZE_ADD_SP (size); | |
975 | /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */ | |
976 | this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save); | |
977 | /* We're going to use ret to release the FP registers | |
09e5ce26 | 978 | save area, so, no savings. */ |
b166356e | 979 | |
980 | if (this_strategy_size < strategy_size) | |
981 | { | |
982 | strategy = restore_sp_pre_adjust; | |
983 | strategy_size = this_strategy_size; | |
984 | } | |
985 | ||
986 | /* Consider using sp offsets after partially adjusting sp. | |
987 | When size is close to 32Kb, we may be able to adjust SP | |
988 | with an imm16 add instruction while still using fmov | |
989 | (d8,sp). */ | |
990 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
991 | { | |
992 | /* Insn: add size + 4 * num_regs_to_save | |
993 | + REG_SAVE_BYTES - 252,sp. */ | |
994 | this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save | |
995 | + REG_SAVE_BYTES - 252); | |
996 | /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */ | |
997 | this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES | |
998 | - 4 * num_regs_to_save, | |
999 | num_regs_to_save); | |
1000 | /* We're going to use ret to release the FP registers | |
09e5ce26 | 1001 | save area, so, no savings. */ |
b166356e | 1002 | |
1003 | if (this_strategy_size < strategy_size) | |
1004 | { | |
1005 | strategy = restore_sp_partial_adjust; | |
1006 | strategy_size = this_strategy_size; | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | /* Consider using a1 in post-increment mode, as long as the | |
1011 | user hasn't changed the calling conventions of a1. */ | |
d37e81ec | 1012 | if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1] |
b166356e | 1013 | && ! fixed_regs[FIRST_ADDRESS_REGNUM+1]) |
1014 | { | |
1015 | /* Insn: mov sp,a1. */ | |
1016 | this_strategy_size = 1; | |
1017 | if (size) | |
1018 | { | |
1019 | /* Insn: add size,a1. */ | |
1020 | this_strategy_size += SIZE_ADD_AX (size); | |
1021 | } | |
1022 | /* Insn: fmov (a1+),fs#, for each fs# to be restored. */ | |
1023 | this_strategy_size += 3 * num_regs_to_save; | |
1024 | /* If size is large enough, we may be able to save a | |
1025 | couple of bytes. */ | |
1026 | if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255) | |
1027 | { | |
1028 | /* Insn: mov a1,sp. */ | |
1029 | this_strategy_size += 2; | |
1030 | } | |
1031 | /* If we don't have to restore any non-FP registers, | |
1032 | we'll be able to save one byte by using rets. */ | |
1033 | if (! REG_SAVE_BYTES) | |
1034 | this_strategy_size--; | |
1035 | ||
1036 | if (this_strategy_size < strategy_size) | |
1037 | { | |
1038 | strategy = restore_a1; | |
1039 | strategy_size = this_strategy_size; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | switch (strategy) | |
1044 | { | |
1045 | case restore_sp_post_adjust: | |
1046 | break; | |
1047 | ||
1048 | case restore_sp_pre_adjust: | |
1049 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1050 | stack_pointer_rtx, | |
1051 | GEN_INT (size))); | |
1052 | size = 0; | |
1053 | break; | |
1054 | ||
1055 | case restore_sp_partial_adjust: | |
1056 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1057 | stack_pointer_rtx, | |
1058 | GEN_INT (size + 4 * num_regs_to_save | |
1059 | + REG_SAVE_BYTES - 252))); | |
1060 | size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save; | |
1061 | break; | |
fb16c776 | 1062 | |
b166356e | 1063 | case restore_a1: |
1064 | reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1); | |
1065 | emit_insn (gen_movsi (reg, stack_pointer_rtx)); | |
1066 | if (size) | |
1067 | emit_insn (gen_addsi3 (reg, reg, GEN_INT (size))); | |
1068 | break; | |
1069 | ||
1070 | default: | |
cf41bb03 | 1071 | gcc_unreachable (); |
b166356e | 1072 | } |
1073 | } | |
1074 | ||
1075 | /* Adjust the selected register, if any, for post-increment. */ | |
1076 | if (reg) | |
1077 | reg = gen_rtx_POST_INC (SImode, reg); | |
1078 | ||
1079 | for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i) | |
d37e81ec | 1080 | if (df_regs_ever_live_p (i) && ! call_really_used_regs [i]) |
b166356e | 1081 | { |
1082 | rtx addr; | |
fb16c776 | 1083 | |
b166356e | 1084 | if (reg) |
1085 | addr = reg; | |
1086 | else if (size) | |
1087 | { | |
1088 | /* If we aren't using a post-increment register, use an | |
09e5ce26 | 1089 | SP offset. */ |
b166356e | 1090 | addr = gen_rtx_PLUS (SImode, |
1091 | stack_pointer_rtx, | |
1092 | GEN_INT (size)); | |
1093 | } | |
1094 | else | |
1095 | addr = stack_pointer_rtx; | |
1096 | ||
1097 | size += 4; | |
1098 | ||
5f2853dd | 1099 | emit_insn (gen_movsf (gen_rtx_REG (SFmode, i), |
1100 | gen_rtx_MEM (SFmode, addr))); | |
b166356e | 1101 | } |
1102 | ||
1103 | /* If we were using the restore_a1 strategy and the number of | |
1104 | bytes to be released won't fit in the `ret' byte, copy `a1' | |
1105 | to `sp', to avoid having to use `add' to adjust it. */ | |
1106 | if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255) | |
1107 | { | |
1108 | emit_move_insn (stack_pointer_rtx, XEXP (reg, 0)); | |
1109 | size = 0; | |
1110 | } | |
1111 | } | |
1112 | ||
461cabcc | 1113 | /* Maybe cut back the stack, except for the register save area. |
1114 | ||
1115 | If the frame pointer exists, then use the frame pointer to | |
1116 | cut back the stack. | |
1117 | ||
1118 | If the stack size + register save area is more than 255 bytes, | |
1119 | then the stack must be cut back here since the size + register | |
fb16c776 | 1120 | save size is too big for a ret/retf instruction. |
461cabcc | 1121 | |
1122 | Else leave it alone, it will be cut back as part of the | |
1123 | ret/retf instruction, or there wasn't any stack to begin with. | |
1124 | ||
dfd1079d | 1125 | Under no circumstances should the register save area be |
461cabcc | 1126 | deallocated here, that would leave a window where an interrupt |
1127 | could occur and trash the register save area. */ | |
29a404f9 | 1128 | if (frame_pointer_needed) |
1129 | { | |
29a404f9 | 1130 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
b21218d6 | 1131 | size = 0; |
1132 | } | |
55daf463 | 1133 | else if (size + REG_SAVE_BYTES > 255) |
b21218d6 | 1134 | { |
1135 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
1136 | stack_pointer_rtx, | |
1137 | GEN_INT (size))); | |
1138 | size = 0; | |
29a404f9 | 1139 | } |
29a404f9 | 1140 | |
55daf463 | 1141 | /* Adjust the stack and restore callee-saved registers, if any. */ |
3072d30e | 1142 | if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1143 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1144 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1145 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
48cb86e3 | 1146 | || frame_pointer_needed) |
55daf463 | 1147 | emit_jump_insn (gen_return_internal_regs |
1148 | (GEN_INT (size + REG_SAVE_BYTES))); | |
48cb86e3 | 1149 | else |
55daf463 | 1150 | emit_jump_insn (gen_return_internal ()); |
29a404f9 | 1151 | } |
1152 | ||
a2f10574 | 1153 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
4caa3669 | 1154 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
1155 | parallel. If OP is a multiple store, return a mask indicating which | |
1156 | registers it saves. Return 0 otherwise. */ | |
1157 | ||
1158 | int | |
3626e955 | 1159 | mn10300_store_multiple_operation (rtx op, |
1160 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
4caa3669 | 1161 | { |
1162 | int count; | |
1163 | int mask; | |
1164 | int i; | |
1165 | unsigned int last; | |
1166 | rtx elt; | |
1167 | ||
1168 | count = XVECLEN (op, 0); | |
1169 | if (count < 2) | |
1170 | return 0; | |
1171 | ||
1172 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
1173 | elt = XVECEXP (op, 0, 0); | |
1174 | if (GET_CODE (elt) != SET | |
3626e955 | 1175 | || (! REG_P (SET_DEST (elt))) |
4caa3669 | 1176 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM |
1177 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
1178 | return 0; | |
1179 | ||
1180 | /* Check that A is the stack pointer and B is the expected stack size. | |
1181 | For OP to match, each subsequent instruction should push a word onto | |
1182 | the stack. We therefore expect the first instruction to create | |
09e5ce26 | 1183 | COUNT-1 stack slots. */ |
4caa3669 | 1184 | elt = SET_SRC (elt); |
3626e955 | 1185 | if ((! REG_P (XEXP (elt, 0))) |
4caa3669 | 1186 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM |
3626e955 | 1187 | || (! CONST_INT_P (XEXP (elt, 1))) |
4caa3669 | 1188 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) |
1189 | return 0; | |
1190 | ||
1191 | /* Now go through the rest of the vector elements. They must be | |
1192 | ordered so that the first instruction stores the highest-numbered | |
1193 | register to the highest stack slot and that subsequent instructions | |
1194 | store a lower-numbered register to the slot below. | |
1195 | ||
1196 | LAST keeps track of the smallest-numbered register stored so far. | |
09e5ce26 | 1197 | MASK is the set of stored registers. */ |
b166356e | 1198 | last = LAST_EXTENDED_REGNUM + 1; |
4caa3669 | 1199 | mask = 0; |
1200 | for (i = 1; i < count; i++) | |
1201 | { | |
09e5ce26 | 1202 | /* Check that element i is a (set (mem M) R) and that R is valid. */ |
4caa3669 | 1203 | elt = XVECEXP (op, 0, i); |
1204 | if (GET_CODE (elt) != SET | |
3626e955 | 1205 | || (! MEM_P (SET_DEST (elt))) |
1206 | || (! REG_P (SET_SRC (elt))) | |
4caa3669 | 1207 | || REGNO (SET_SRC (elt)) >= last) |
1208 | return 0; | |
1209 | ||
1210 | /* R was OK, so provisionally add it to MASK. We return 0 in any | |
09e5ce26 | 1211 | case if the rest of the instruction has a flaw. */ |
4caa3669 | 1212 | last = REGNO (SET_SRC (elt)); |
1213 | mask |= (1 << last); | |
1214 | ||
1215 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
1216 | elt = XEXP (SET_DEST (elt), 0); | |
1217 | if (GET_CODE (elt) != PLUS | |
3626e955 | 1218 | || (! REG_P (XEXP (elt, 0))) |
4caa3669 | 1219 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM |
3626e955 | 1220 | || (! CONST_INT_P (XEXP (elt, 1))) |
4caa3669 | 1221 | || INTVAL (XEXP (elt, 1)) != -i * 4) |
1222 | return 0; | |
1223 | } | |
1224 | ||
09e5ce26 | 1225 | /* All or none of the callee-saved extended registers must be in the set. */ |
4caa3669 | 1226 | if ((mask & 0x3c000) != 0 |
1227 | && (mask & 0x3c000) != 0x3c000) | |
1228 | return 0; | |
1229 | ||
1230 | return mask; | |
1231 | } | |
1232 | ||
29a404f9 | 1233 | /* What (if any) secondary registers are needed to move IN with mode |
8deb3959 | 1234 | MODE into a register in register class RCLASS. |
29a404f9 | 1235 | |
1236 | We might be able to simplify this. */ | |
3626e955 | 1237 | |
29a404f9 | 1238 | enum reg_class |
8deb3959 | 1239 | mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode, |
51149d85 | 1240 | rtx in) |
29a404f9 | 1241 | { |
8b8be022 | 1242 | rtx inner = in; |
1243 | ||
1244 | /* Strip off any SUBREG expressions from IN. Basically we want | |
1245 | to know if IN is a pseudo or (subreg (pseudo)) as those can | |
1246 | turn into MEMs during reload. */ | |
1247 | while (GET_CODE (inner) == SUBREG) | |
1248 | inner = SUBREG_REG (inner); | |
1249 | ||
29a404f9 | 1250 | /* Memory loads less than a full word wide can't have an |
1251 | address or stack pointer destination. They must use | |
1252 | a data register as an intermediate register. */ | |
3626e955 | 1253 | if ((MEM_P ((in)) |
1254 | || (REG_P ((inner)) | |
8b8be022 | 1255 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER)) |
29a404f9 | 1256 | && (mode == QImode || mode == HImode) |
8deb3959 | 1257 | && (rclass == ADDRESS_REGS || rclass == SP_REGS |
1258 | || rclass == SP_OR_ADDRESS_REGS)) | |
8ecf154e | 1259 | { |
911517ac | 1260 | if (TARGET_AM33) |
1261 | return DATA_OR_EXTENDED_REGS; | |
8ecf154e | 1262 | return DATA_REGS; |
1263 | } | |
29a404f9 | 1264 | |
1265 | /* We can't directly load sp + const_int into a data register; | |
1266 | we must use an address register as an intermediate. */ | |
8deb3959 | 1267 | if (rclass != SP_REGS |
1268 | && rclass != ADDRESS_REGS | |
1269 | && rclass != SP_OR_ADDRESS_REGS | |
1270 | && rclass != SP_OR_EXTENDED_REGS | |
1271 | && rclass != ADDRESS_OR_EXTENDED_REGS | |
1272 | && rclass != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
29a404f9 | 1273 | && (in == stack_pointer_rtx |
1274 | || (GET_CODE (in) == PLUS | |
48cb86e3 | 1275 | && (XEXP (in, 0) == stack_pointer_rtx |
1276 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
29a404f9 | 1277 | return ADDRESS_REGS; |
1278 | ||
8b8be022 | 1279 | if (TARGET_AM33_2 |
1280 | && rclass == FP_REGS) | |
b166356e | 1281 | { |
8b8be022 | 1282 | /* We can't load directly into an FP register from a |
1283 | constant address. */ | |
3626e955 | 1284 | if (MEM_P ((in)) |
8b8be022 | 1285 | && CONSTANT_ADDRESS_P (XEXP (in, 0))) |
5574dbdd | 1286 | return DATA_OR_EXTENDED_REGS; |
8b8be022 | 1287 | |
1288 | /* Handle case were a pseudo may not get a hard register | |
1289 | but has an equivalent memory location defined. */ | |
3626e955 | 1290 | if (REG_P ((inner)) |
8b8be022 | 1291 | && REGNO (inner) >= FIRST_PSEUDO_REGISTER |
1292 | && reg_equiv_mem [REGNO (inner)] | |
1293 | && CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0))) | |
5574dbdd | 1294 | return DATA_OR_EXTENDED_REGS; |
b166356e | 1295 | } |
1296 | ||
48cb86e3 | 1297 | /* Otherwise assume no secondary reloads are needed. */ |
1298 | return NO_REGS; | |
1299 | } | |
1300 | ||
1301 | int | |
3626e955 | 1302 | mn10300_initial_offset (int from, int to) |
48cb86e3 | 1303 | { |
f1899bff | 1304 | /* The difference between the argument pointer and the frame pointer |
1305 | is the size of the callee register save area. */ | |
48cb86e3 | 1306 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
29a404f9 | 1307 | { |
3072d30e | 1308 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1309 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1310 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1311 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
b166356e | 1312 | || fp_regs_to_save () |
48cb86e3 | 1313 | || frame_pointer_needed) |
b166356e | 1314 | return REG_SAVE_BYTES |
1315 | + 4 * fp_regs_to_save (); | |
48cb86e3 | 1316 | else |
bb4959a8 | 1317 | return 0; |
29a404f9 | 1318 | } |
1319 | ||
f1899bff | 1320 | /* The difference between the argument pointer and the stack pointer is |
1321 | the sum of the size of this function's frame, the callee register save | |
1322 | area, and the fixed stack space needed for function calls (if any). */ | |
48cb86e3 | 1323 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
1324 | { | |
3072d30e | 1325 | if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3) |
1326 | || df_regs_ever_live_p (6) || df_regs_ever_live_p (7) | |
1327 | || df_regs_ever_live_p (14) || df_regs_ever_live_p (15) | |
1328 | || df_regs_ever_live_p (16) || df_regs_ever_live_p (17) | |
b166356e | 1329 | || fp_regs_to_save () |
48cb86e3 | 1330 | || frame_pointer_needed) |
8ecf154e | 1331 | return (get_frame_size () + REG_SAVE_BYTES |
b166356e | 1332 | + 4 * fp_regs_to_save () |
abe32cce | 1333 | + (crtl->outgoing_args_size |
1334 | ? crtl->outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1335 | else |
36ed4406 | 1336 | return (get_frame_size () |
abe32cce | 1337 | + (crtl->outgoing_args_size |
1338 | ? crtl->outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1339 | } |
29a404f9 | 1340 | |
f1899bff | 1341 | /* The difference between the frame pointer and stack pointer is the sum |
1342 | of the size of this function's frame and the fixed stack space needed | |
1343 | for function calls (if any). */ | |
48cb86e3 | 1344 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
36ed4406 | 1345 | return (get_frame_size () |
abe32cce | 1346 | + (crtl->outgoing_args_size |
1347 | ? crtl->outgoing_args_size + 4 : 0)); | |
48cb86e3 | 1348 | |
cf41bb03 | 1349 | gcc_unreachable (); |
29a404f9 | 1350 | } |
bb4959a8 | 1351 | |
6644435d | 1352 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
1353 | ||
f2d49d02 | 1354 | static bool |
fb80456a | 1355 | mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
f2d49d02 | 1356 | { |
1357 | /* Return values > 8 bytes in length in memory. */ | |
00b1da0e | 1358 | return (int_size_in_bytes (type) > 8 |
1359 | || int_size_in_bytes (type) == 0 | |
1360 | || TYPE_MODE (type) == BLKmode); | |
f2d49d02 | 1361 | } |
1362 | ||
bb4959a8 | 1363 | /* Flush the argument registers to the stack for a stdarg function; |
1364 | return the new argument pointer. */ | |
f2d49d02 | 1365 | static rtx |
3285410a | 1366 | mn10300_builtin_saveregs (void) |
bb4959a8 | 1367 | { |
ed554036 | 1368 | rtx offset, mem; |
bb4959a8 | 1369 | tree fntype = TREE_TYPE (current_function_decl); |
257d99c3 | 1370 | int argadj = ((!stdarg_p (fntype)) |
bb4959a8 | 1371 | ? UNITS_PER_WORD : 0); |
32c2fdea | 1372 | alias_set_type set = get_varargs_alias_set (); |
bb4959a8 | 1373 | |
1374 | if (argadj) | |
abe32cce | 1375 | offset = plus_constant (crtl->args.arg_offset_rtx, argadj); |
bb4959a8 | 1376 | else |
abe32cce | 1377 | offset = crtl->args.arg_offset_rtx; |
bb4959a8 | 1378 | |
abe32cce | 1379 | mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer); |
ab6ab77e | 1380 | set_mem_alias_set (mem, set); |
ed554036 | 1381 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
1382 | ||
1383 | mem = gen_rtx_MEM (SImode, | |
abe32cce | 1384 | plus_constant (crtl->args.internal_arg_pointer, 4)); |
ab6ab77e | 1385 | set_mem_alias_set (mem, set); |
ed554036 | 1386 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
1387 | ||
bb4959a8 | 1388 | return copy_to_reg (expand_binop (Pmode, add_optab, |
abe32cce | 1389 | crtl->args.internal_arg_pointer, |
bb4959a8 | 1390 | offset, 0, 0, OPTAB_LIB_WIDEN)); |
1391 | } | |
1392 | ||
8a58ed0a | 1393 | static void |
3285410a | 1394 | mn10300_va_start (tree valist, rtx nextarg) |
ed554036 | 1395 | { |
7ccc713a | 1396 | nextarg = expand_builtin_saveregs (); |
7df226a2 | 1397 | std_expand_builtin_va_start (valist, nextarg); |
ed554036 | 1398 | } |
1399 | ||
b981d932 | 1400 | /* Return true when a parameter should be passed by reference. */ |
1401 | ||
1402 | static bool | |
1403 | mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
fb80456a | 1404 | enum machine_mode mode, const_tree type, |
b981d932 | 1405 | bool named ATTRIBUTE_UNUSED) |
1406 | { | |
1407 | unsigned HOST_WIDE_INT size; | |
1408 | ||
1409 | if (type) | |
1410 | size = int_size_in_bytes (type); | |
1411 | else | |
1412 | size = GET_MODE_SIZE (mode); | |
1413 | ||
00b1da0e | 1414 | return (size > 8 || size == 0); |
b981d932 | 1415 | } |
1416 | ||
bb4959a8 | 1417 | /* Return an RTX to represent where a value with mode MODE will be returned |
e92d3ba8 | 1418 | from a function. If the result is NULL_RTX, the argument is pushed. */ |
bb4959a8 | 1419 | |
dc67179a | 1420 | static rtx |
3626e955 | 1421 | mn10300_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
dc67179a | 1422 | const_tree type, bool named ATTRIBUTE_UNUSED) |
bb4959a8 | 1423 | { |
e92d3ba8 | 1424 | rtx result = NULL_RTX; |
bb4959a8 | 1425 | int size, align; |
1426 | ||
1427 | /* We only support using 2 data registers as argument registers. */ | |
1428 | int nregs = 2; | |
1429 | ||
1430 | /* Figure out the size of the object to be passed. */ | |
1431 | if (mode == BLKmode) | |
1432 | size = int_size_in_bytes (type); | |
1433 | else | |
1434 | size = GET_MODE_SIZE (mode); | |
1435 | ||
1436 | /* Figure out the alignment of the object to be passed. */ | |
1437 | align = size; | |
1438 | ||
1439 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1440 | ||
1441 | /* Don't pass this arg via a register if all the argument registers | |
1442 | are used up. */ | |
1443 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
e92d3ba8 | 1444 | return result; |
bb4959a8 | 1445 | |
1446 | /* Don't pass this arg via a register if it would be split between | |
1447 | registers and memory. */ | |
1448 | if (type == NULL_TREE | |
1449 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
e92d3ba8 | 1450 | return result; |
bb4959a8 | 1451 | |
1452 | switch (cum->nbytes / UNITS_PER_WORD) | |
1453 | { | |
1454 | case 0: | |
e92d3ba8 | 1455 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM); |
bb4959a8 | 1456 | break; |
1457 | case 1: | |
e92d3ba8 | 1458 | result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1); |
bb4959a8 | 1459 | break; |
1460 | default: | |
e92d3ba8 | 1461 | break; |
bb4959a8 | 1462 | } |
1463 | ||
1464 | return result; | |
1465 | } | |
1466 | ||
dc67179a | 1467 | /* Update the data in CUM to advance over an argument |
1468 | of mode MODE and data type TYPE. | |
1469 | (TYPE is null for libcalls where that information may not be available.) */ | |
1470 | ||
1471 | static void | |
1472 | mn10300_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1473 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
1474 | { | |
1475 | cum->nbytes += (mode != BLKmode | |
1476 | ? (GET_MODE_SIZE (mode) + 3) & ~3 | |
1477 | : (int_size_in_bytes (type) + 3) & ~3); | |
1478 | } | |
1479 | ||
f054eb3c | 1480 | /* Return the number of bytes of registers to use for an argument passed |
1481 | partially in registers and partially in memory. */ | |
bb4959a8 | 1482 | |
f054eb3c | 1483 | static int |
1484 | mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
1485 | tree type, bool named ATTRIBUTE_UNUSED) | |
bb4959a8 | 1486 | { |
1487 | int size, align; | |
1488 | ||
1489 | /* We only support using 2 data registers as argument registers. */ | |
1490 | int nregs = 2; | |
1491 | ||
1492 | /* Figure out the size of the object to be passed. */ | |
1493 | if (mode == BLKmode) | |
1494 | size = int_size_in_bytes (type); | |
1495 | else | |
1496 | size = GET_MODE_SIZE (mode); | |
1497 | ||
1498 | /* Figure out the alignment of the object to be passed. */ | |
1499 | align = size; | |
1500 | ||
1501 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1502 | ||
1503 | /* Don't pass this arg via a register if all the argument registers | |
1504 | are used up. */ | |
1505 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1506 | return 0; | |
1507 | ||
1508 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1509 | return 0; | |
1510 | ||
1511 | /* Don't pass this arg via a register if it would be split between | |
1512 | registers and memory. */ | |
1513 | if (type == NULL_TREE | |
1514 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1515 | return 0; | |
1516 | ||
f054eb3c | 1517 | return nregs * UNITS_PER_WORD - cum->nbytes; |
bb4959a8 | 1518 | } |
1519 | ||
00b1da0e | 1520 | /* Return the location of the function's value. This will be either |
1521 | $d0 for integer functions, $a0 for pointers, or a PARALLEL of both | |
1522 | $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that | |
1523 | we only return the PARALLEL for outgoing values; we do not want | |
1524 | callers relying on this extra copy. */ | |
1525 | ||
b6713ba6 | 1526 | static rtx |
1527 | mn10300_function_value (const_tree valtype, | |
1528 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
1529 | bool outgoing) | |
00b1da0e | 1530 | { |
1531 | rtx rv; | |
1532 | enum machine_mode mode = TYPE_MODE (valtype); | |
1533 | ||
1534 | if (! POINTER_TYPE_P (valtype)) | |
1535 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1536 | else if (! TARGET_PTR_A0D0 || ! outgoing | |
18d50ae6 | 1537 | || cfun->returns_struct) |
00b1da0e | 1538 | return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM); |
1539 | ||
1540 | rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2)); | |
1541 | XVECEXP (rv, 0, 0) | |
1542 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1543 | gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM), | |
1544 | GEN_INT (0)); | |
fb16c776 | 1545 | |
00b1da0e | 1546 | XVECEXP (rv, 0, 1) |
1547 | = gen_rtx_EXPR_LIST (VOIDmode, | |
1548 | gen_rtx_REG (mode, FIRST_DATA_REGNUM), | |
1549 | GEN_INT (0)); | |
1550 | return rv; | |
1551 | } | |
1552 | ||
b6713ba6 | 1553 | /* Implements TARGET_LIBCALL_VALUE. */ |
1554 | ||
1555 | static rtx | |
1556 | mn10300_libcall_value (enum machine_mode mode, | |
1557 | const_rtx fun ATTRIBUTE_UNUSED) | |
1558 | { | |
1559 | return gen_rtx_REG (mode, FIRST_DATA_REGNUM); | |
1560 | } | |
1561 | ||
1562 | /* Implements FUNCTION_VALUE_REGNO_P. */ | |
1563 | ||
1564 | bool | |
1565 | mn10300_function_value_regno_p (const unsigned int regno) | |
1566 | { | |
1567 | return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM); | |
1568 | } | |
1569 | ||
5574dbdd | 1570 | /* Output a compare insn. */ |
1571 | ||
feb9af9f | 1572 | const char * |
5574dbdd | 1573 | mn10300_output_cmp (rtx operand, rtx insn) |
bb4959a8 | 1574 | { |
bb4959a8 | 1575 | rtx temp; |
1576 | int past_call = 0; | |
1577 | ||
1578 | /* We can save a byte if we can find a register which has the value | |
1579 | zero in it. */ | |
1580 | temp = PREV_INSN (insn); | |
6e90c6cd | 1581 | while (optimize && temp) |
bb4959a8 | 1582 | { |
1583 | rtx set; | |
1584 | ||
1585 | /* We allow the search to go through call insns. We record | |
1586 | the fact that we've past a CALL_INSN and reject matches which | |
1587 | use call clobbered registers. */ | |
3626e955 | 1588 | if (LABEL_P (temp) |
1589 | || JUMP_P (temp) | |
bb4959a8 | 1590 | || GET_CODE (temp) == BARRIER) |
1591 | break; | |
1592 | ||
3626e955 | 1593 | if (CALL_P (temp)) |
bb4959a8 | 1594 | past_call = 1; |
1595 | ||
1596 | if (GET_CODE (temp) == NOTE) | |
1597 | { | |
1598 | temp = PREV_INSN (temp); | |
1599 | continue; | |
1600 | } | |
1601 | ||
09e5ce26 | 1602 | /* It must be an insn, see if it is a simple set. */ |
bb4959a8 | 1603 | set = single_set (temp); |
1604 | if (!set) | |
1605 | { | |
1606 | temp = PREV_INSN (temp); | |
1607 | continue; | |
1608 | } | |
1609 | ||
1610 | /* Are we setting a data register to zero (this does not win for | |
fb16c776 | 1611 | address registers)? |
bb4959a8 | 1612 | |
1613 | If it's a call clobbered register, have we past a call? | |
1614 | ||
1615 | Make sure the register we find isn't the same as ourself; | |
8ecf154e | 1616 | the mn10300 can't encode that. |
1617 | ||
1618 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1619 | so the code to detect calls here isn't doing anything useful. */ | |
bb4959a8 | 1620 | if (REG_P (SET_DEST (set)) |
1621 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1622 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
6e90c6cd | 1623 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1624 | == REGNO_REG_CLASS (REGNO (operand))) | |
911517ac | 1625 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1626 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
fb16c776 | 1627 | && (!past_call |
d37e81ec | 1628 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
911517ac | 1629 | { |
1630 | rtx xoperands[2]; | |
1631 | xoperands[0] = operand; | |
1632 | xoperands[1] = SET_DEST (set); | |
1633 | ||
1634 | output_asm_insn ("cmp %1,%0", xoperands); | |
1635 | return ""; | |
1636 | } | |
1637 | ||
1638 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1639 | && REG_P (SET_DEST (set)) | |
1640 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1641 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1642 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1643 | != REGNO_REG_CLASS (REGNO (operand))) | |
1644 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
bb4959a8 | 1645 | && REGNO (SET_DEST (set)) != REGNO (operand) |
fb16c776 | 1646 | && (!past_call |
d37e81ec | 1647 | || ! call_really_used_regs [REGNO (SET_DEST (set))])) |
bb4959a8 | 1648 | { |
1649 | rtx xoperands[2]; | |
1650 | xoperands[0] = operand; | |
1651 | xoperands[1] = SET_DEST (set); | |
1652 | ||
1653 | output_asm_insn ("cmp %1,%0", xoperands); | |
1654 | return ""; | |
1655 | } | |
1656 | temp = PREV_INSN (temp); | |
1657 | } | |
1658 | return "cmp 0,%0"; | |
1659 | } | |
36ed4406 | 1660 | |
9d3b5b5e | 1661 | /* Similarly, but when using a zero_extract pattern for a btst where |
1662 | the source operand might end up in memory. */ | |
1663 | int | |
3626e955 | 1664 | mn10300_mask_ok_for_mem_btst (int len, int bit) |
9d3b5b5e | 1665 | { |
805e22b2 | 1666 | unsigned int mask = 0; |
9d3b5b5e | 1667 | |
1668 | while (len > 0) | |
1669 | { | |
1670 | mask |= (1 << bit); | |
1671 | bit++; | |
1672 | len--; | |
1673 | } | |
1674 | ||
1675 | /* MASK must bit into an 8bit value. */ | |
1676 | return (((mask & 0xff) == mask) | |
1677 | || ((mask & 0xff00) == mask) | |
1678 | || ((mask & 0xff0000) == mask) | |
1679 | || ((mask & 0xff000000) == mask)); | |
1680 | } | |
1681 | ||
c4cd8f6a | 1682 | /* Return 1 if X contains a symbolic expression. We know these |
1683 | expressions will have one of a few well defined forms, so | |
1684 | we need only check those forms. */ | |
3626e955 | 1685 | |
c4cd8f6a | 1686 | int |
3626e955 | 1687 | mn10300_symbolic_operand (rtx op, |
1688 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
c4cd8f6a | 1689 | { |
1690 | switch (GET_CODE (op)) | |
1691 | { | |
1692 | case SYMBOL_REF: | |
1693 | case LABEL_REF: | |
1694 | return 1; | |
1695 | case CONST: | |
1696 | op = XEXP (op, 0); | |
1697 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1698 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
3626e955 | 1699 | && CONST_INT_P ((XEXP (op, 1)))); |
c4cd8f6a | 1700 | default: |
1701 | return 0; | |
1702 | } | |
1703 | } | |
1704 | ||
1705 | /* Try machine dependent ways of modifying an illegitimate address | |
1706 | to be legitimate. If we find one, return the new valid address. | |
1707 | This macro is used in only one place: `memory_address' in explow.c. | |
1708 | ||
1709 | OLDX is the address as it was before break_out_memory_refs was called. | |
1710 | In some cases it is useful to look at this to decide what needs to be done. | |
1711 | ||
c4cd8f6a | 1712 | Normally it is always safe for this macro to do nothing. It exists to |
1713 | recognize opportunities to optimize the output. | |
1714 | ||
1715 | But on a few ports with segmented architectures and indexed addressing | |
1716 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
3626e955 | 1717 | |
5574dbdd | 1718 | static rtx |
41e3a0c7 | 1719 | mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1720 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
c4cd8f6a | 1721 | { |
3626e955 | 1722 | if (flag_pic && ! mn10300_legitimate_pic_operand_p (x)) |
1723 | x = mn10300_legitimize_pic_address (oldx, NULL_RTX); | |
b87a151a | 1724 | |
c4cd8f6a | 1725 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
1726 | special handling to avoid creating an indexed memory address | |
1727 | with x-100000 as the base. */ | |
1728 | if (GET_CODE (x) == PLUS | |
3626e955 | 1729 | && mn10300_symbolic_operand (XEXP (x, 1), VOIDmode)) |
c4cd8f6a | 1730 | { |
1731 | /* Ugly. We modify things here so that the address offset specified | |
1732 | by the index expression is computed first, then added to x to form | |
1733 | the entire address. */ | |
1734 | ||
59086782 | 1735 | rtx regx1, regy1, regy2, y; |
c4cd8f6a | 1736 | |
1737 | /* Strip off any CONST. */ | |
1738 | y = XEXP (x, 1); | |
1739 | if (GET_CODE (y) == CONST) | |
1740 | y = XEXP (y, 0); | |
1741 | ||
c927a8ab | 1742 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1743 | { | |
1744 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1745 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1746 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1747 | regx1 = force_reg (Pmode, | |
3626e955 | 1748 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, |
1749 | regy2)); | |
7014838c | 1750 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
c927a8ab | 1751 | } |
c4cd8f6a | 1752 | } |
11b4605c | 1753 | return x; |
c4cd8f6a | 1754 | } |
e2aead91 | 1755 | |
b87a151a | 1756 | /* Convert a non-PIC address in `orig' to a PIC address using @GOT or |
09e5ce26 | 1757 | @GOTOFF in `reg'. */ |
3626e955 | 1758 | |
b87a151a | 1759 | rtx |
3626e955 | 1760 | mn10300_legitimize_pic_address (rtx orig, rtx reg) |
b87a151a | 1761 | { |
1762 | if (GET_CODE (orig) == LABEL_REF | |
1763 | || (GET_CODE (orig) == SYMBOL_REF | |
1764 | && (CONSTANT_POOL_ADDRESS_P (orig) | |
1765 | || ! MN10300_GLOBAL_P (orig)))) | |
1766 | { | |
1767 | if (reg == 0) | |
1768 | reg = gen_reg_rtx (Pmode); | |
1769 | ||
1770 | emit_insn (gen_symGOTOFF2reg (reg, orig)); | |
1771 | return reg; | |
1772 | } | |
1773 | else if (GET_CODE (orig) == SYMBOL_REF) | |
1774 | { | |
1775 | if (reg == 0) | |
1776 | reg = gen_reg_rtx (Pmode); | |
1777 | ||
1778 | emit_insn (gen_symGOT2reg (reg, orig)); | |
1779 | return reg; | |
1780 | } | |
1781 | return orig; | |
1782 | } | |
1783 | ||
1784 | /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol | |
fa483857 | 1785 | isn't protected by a PIC unspec; nonzero otherwise. */ |
3626e955 | 1786 | |
b87a151a | 1787 | int |
3626e955 | 1788 | mn10300_legitimate_pic_operand_p (rtx x) |
b87a151a | 1789 | { |
3626e955 | 1790 | const char *fmt; |
1791 | int i; | |
b87a151a | 1792 | |
1793 | if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) | |
1794 | return 0; | |
1795 | ||
1796 | if (GET_CODE (x) == UNSPEC | |
1797 | && (XINT (x, 1) == UNSPEC_PIC | |
1798 | || XINT (x, 1) == UNSPEC_GOT | |
1799 | || XINT (x, 1) == UNSPEC_GOTOFF | |
b6e3379c | 1800 | || XINT (x, 1) == UNSPEC_PLT |
1801 | || XINT (x, 1) == UNSPEC_GOTSYM_OFF)) | |
b87a151a | 1802 | return 1; |
1803 | ||
b87a151a | 1804 | fmt = GET_RTX_FORMAT (GET_CODE (x)); |
1805 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
1806 | { | |
1807 | if (fmt[i] == 'E') | |
1808 | { | |
5574dbdd | 1809 | int j; |
b87a151a | 1810 | |
1811 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
3626e955 | 1812 | if (! mn10300_legitimate_pic_operand_p (XVECEXP (x, i, j))) |
b87a151a | 1813 | return 0; |
1814 | } | |
3626e955 | 1815 | else if (fmt[i] == 'e' |
1816 | && ! mn10300_legitimate_pic_operand_p (XEXP (x, i))) | |
b87a151a | 1817 | return 0; |
1818 | } | |
1819 | ||
1820 | return 1; | |
1821 | } | |
1822 | ||
5411aa8c | 1823 | /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is |
fd50b071 | 1824 | legitimate, and FALSE otherwise. |
1825 | ||
1826 | On the mn10300, the value in the address register must be | |
1827 | in the same memory space/segment as the effective address. | |
1828 | ||
1829 | This is problematical for reload since it does not understand | |
1830 | that base+index != index+base in a memory reference. | |
1831 | ||
1832 | Note it is still possible to use reg+reg addressing modes, | |
1833 | it's just much more difficult. For a discussion of a possible | |
1834 | workaround and solution, see the comments in pa.c before the | |
1835 | function record_unscaled_index_insn_codes. */ | |
1836 | ||
5574dbdd | 1837 | static bool |
fd50b071 | 1838 | mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) |
5411aa8c | 1839 | { |
1840 | if (CONSTANT_ADDRESS_P (x) | |
3626e955 | 1841 | && (! flag_pic || mn10300_legitimate_pic_operand_p (x))) |
5411aa8c | 1842 | return TRUE; |
1843 | ||
1844 | if (RTX_OK_FOR_BASE_P (x, strict)) | |
1845 | return TRUE; | |
1846 | ||
1847 | if (TARGET_AM33 | |
1848 | && GET_CODE (x) == POST_INC | |
1849 | && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict) | |
1850 | && (mode == SImode || mode == SFmode || mode == HImode)) | |
1851 | return TRUE; | |
1852 | ||
1853 | if (GET_CODE (x) == PLUS) | |
1854 | { | |
1855 | rtx base = 0, index = 0; | |
1856 | ||
1857 | if (REG_P (XEXP (x, 0)) | |
1858 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict)) | |
1859 | { | |
1860 | base = XEXP (x, 0); | |
1861 | index = XEXP (x, 1); | |
1862 | } | |
1863 | ||
1864 | if (REG_P (XEXP (x, 1)) | |
1865 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict)) | |
1866 | { | |
1867 | base = XEXP (x, 1); | |
1868 | index = XEXP (x, 0); | |
1869 | } | |
1870 | ||
1871 | if (base != 0 && index != 0) | |
1872 | { | |
3626e955 | 1873 | if (CONST_INT_P ((index))) |
5411aa8c | 1874 | return TRUE; |
1875 | if (GET_CODE (index) == CONST | |
9247cc1c | 1876 | && GET_CODE (XEXP (index, 0)) != PLUS |
5411aa8c | 1877 | && (! flag_pic |
3626e955 | 1878 | || (mn10300_legitimate_pic_operand_p (index) |
5574dbdd | 1879 | && GET_MODE_SIZE (mode) == 4))) |
5411aa8c | 1880 | return TRUE; |
1881 | } | |
1882 | } | |
1883 | ||
1884 | return FALSE; | |
1885 | } | |
1886 | ||
5574dbdd | 1887 | /* Used by LEGITIMATE_CONSTANT_P(). Returns TRUE if X is a valid |
1888 | constant. Note that some "constants" aren't valid, such as TLS | |
1889 | symbols and unconverted GOT-based references, so we eliminate | |
1890 | those here. */ | |
1891 | ||
1892 | bool | |
1893 | mn10300_legitimate_constant_p (rtx x) | |
1894 | { | |
1895 | switch (GET_CODE (x)) | |
1896 | { | |
1897 | case CONST: | |
1898 | x = XEXP (x, 0); | |
1899 | ||
1900 | if (GET_CODE (x) == PLUS) | |
1901 | { | |
3626e955 | 1902 | if (! CONST_INT_P (XEXP (x, 1))) |
5574dbdd | 1903 | return false; |
1904 | x = XEXP (x, 0); | |
1905 | } | |
1906 | ||
1907 | /* Only some unspecs are valid as "constants". */ | |
1908 | if (GET_CODE (x) == UNSPEC) | |
1909 | { | |
1910 | rtx sym = XVECEXP (x, 0, 0); | |
1911 | switch (XINT (x, 1)) | |
1912 | { | |
1913 | case UNSPEC_INT_LABEL: | |
1914 | case UNSPEC_PIC: | |
1915 | case UNSPEC_GOT: | |
1916 | case UNSPEC_GOTOFF: | |
1917 | case UNSPEC_PLT: | |
1918 | return true; | |
1919 | default: | |
1920 | return false; | |
1921 | } | |
1922 | } | |
1923 | ||
1924 | /* We must have drilled down to a symbol. */ | |
3626e955 | 1925 | if (! mn10300_symbolic_operand (x, Pmode)) |
5574dbdd | 1926 | return false; |
1927 | break; | |
1928 | ||
1929 | default: | |
1930 | break; | |
1931 | } | |
1932 | ||
1933 | return true; | |
1934 | } | |
1935 | ||
ec0457a8 | 1936 | static int |
db65aa2c | 1937 | mn10300_address_cost_1 (rtx x, int *unsig) |
e2aead91 | 1938 | { |
e2aead91 | 1939 | switch (GET_CODE (x)) |
1940 | { | |
1941 | case REG: | |
1942 | switch (REGNO_REG_CLASS (REGNO (x))) | |
1943 | { | |
1944 | case SP_REGS: | |
1945 | *unsig = 1; | |
1946 | return 0; | |
1947 | ||
1948 | case ADDRESS_REGS: | |
1949 | return 1; | |
1950 | ||
1951 | case DATA_REGS: | |
1952 | case EXTENDED_REGS: | |
b166356e | 1953 | case FP_REGS: |
e2aead91 | 1954 | return 3; |
1955 | ||
1956 | case NO_REGS: | |
1957 | return 5; | |
1958 | ||
1959 | default: | |
cf41bb03 | 1960 | gcc_unreachable (); |
e2aead91 | 1961 | } |
1962 | ||
1963 | case PLUS: | |
1964 | case MINUS: | |
cbe23f2f | 1965 | case ASHIFT: |
1966 | case AND: | |
e2aead91 | 1967 | case IOR: |
ec0457a8 | 1968 | return (mn10300_address_cost_1 (XEXP (x, 0), unsig) |
1969 | + mn10300_address_cost_1 (XEXP (x, 1), unsig)); | |
e2aead91 | 1970 | |
1971 | case EXPR_LIST: | |
1972 | case SUBREG: | |
1973 | case MEM: | |
db65aa2c | 1974 | return mn10300_address_cost (XEXP (x, 0), !optimize_size); |
e2aead91 | 1975 | |
1976 | case ZERO_EXTEND: | |
1977 | *unsig = 1; | |
ec0457a8 | 1978 | return mn10300_address_cost_1 (XEXP (x, 0), unsig); |
e2aead91 | 1979 | |
1980 | case CONST_INT: | |
1981 | if (INTVAL (x) == 0) | |
1982 | return 0; | |
1983 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
1984 | return 1; | |
1985 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
1986 | return 3; | |
1987 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
1988 | return 5; | |
1989 | return 7; | |
1990 | ||
1991 | case CONST: | |
1992 | case SYMBOL_REF: | |
cbe23f2f | 1993 | case LABEL_REF: |
e2aead91 | 1994 | return 8; |
1995 | ||
e2aead91 | 1996 | default: |
cf41bb03 | 1997 | gcc_unreachable (); |
e2aead91 | 1998 | |
1999 | } | |
2000 | } | |
fab7adbf | 2001 | |
ec0457a8 | 2002 | static int |
f529eb25 | 2003 | mn10300_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED) |
ec0457a8 | 2004 | { |
2005 | int s = 0; | |
2006 | return mn10300_address_cost_1 (x, &s); | |
2007 | } | |
2008 | ||
fab7adbf | 2009 | static bool |
3626e955 | 2010 | mn10300_rtx_costs (rtx x, int code, int outer_code, int *total, |
2011 | bool speed ATTRIBUTE_UNUSED) | |
fab7adbf | 2012 | { |
2013 | switch (code) | |
2014 | { | |
2015 | case CONST_INT: | |
2016 | /* Zeros are extremely cheap. */ | |
74f4459c | 2017 | if (INTVAL (x) == 0 && (outer_code == SET || outer_code == COMPARE)) |
fab7adbf | 2018 | *total = 0; |
2019 | /* If it fits in 8 bits, then it's still relatively cheap. */ | |
2020 | else if (INT_8_BITS (INTVAL (x))) | |
2021 | *total = 1; | |
2022 | /* This is the "base" cost, includes constants where either the | |
2023 | upper or lower 16bits are all zeros. */ | |
2024 | else if (INT_16_BITS (INTVAL (x)) | |
2025 | || (INTVAL (x) & 0xffff) == 0 | |
2026 | || (INTVAL (x) & 0xffff0000) == 0) | |
2027 | *total = 2; | |
2028 | else | |
2029 | *total = 4; | |
2030 | return true; | |
2031 | ||
2032 | case CONST: | |
2033 | case LABEL_REF: | |
2034 | case SYMBOL_REF: | |
2035 | /* These are more costly than a CONST_INT, but we can relax them, | |
2036 | so they're less costly than a CONST_DOUBLE. */ | |
2037 | *total = 6; | |
2038 | return true; | |
2039 | ||
2040 | case CONST_DOUBLE: | |
2041 | /* We don't optimize CONST_DOUBLEs well nor do we relax them well, | |
2042 | so their cost is very high. */ | |
2043 | *total = 8; | |
2044 | return true; | |
2045 | ||
74f4459c | 2046 | case ZERO_EXTRACT: |
2047 | /* This is cheap, we can use btst. */ | |
2048 | if (outer_code == COMPARE) | |
2049 | *total = 0; | |
2050 | return false; | |
2051 | ||
fab7adbf | 2052 | /* ??? This probably needs more work. */ |
2053 | case MOD: | |
2054 | case DIV: | |
2055 | case MULT: | |
2056 | *total = 8; | |
2057 | return true; | |
2058 | ||
2059 | default: | |
2060 | return false; | |
2061 | } | |
2062 | } | |
8935d57c | 2063 | |
2064 | /* Check whether a constant used to initialize a DImode or DFmode can | |
2065 | use a clr instruction. The code here must be kept in sync with | |
2066 | movdf and movdi. */ | |
2067 | ||
2068 | bool | |
3285410a | 2069 | mn10300_wide_const_load_uses_clr (rtx operands[2]) |
8935d57c | 2070 | { |
5f2853dd | 2071 | long val[2] = {0, 0}; |
8935d57c | 2072 | |
3626e955 | 2073 | if (! REG_P (operands[0]) |
8935d57c | 2074 | || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS) |
2075 | return false; | |
2076 | ||
2077 | switch (GET_CODE (operands[1])) | |
2078 | { | |
2079 | case CONST_INT: | |
2080 | { | |
2081 | rtx low, high; | |
2082 | split_double (operands[1], &low, &high); | |
2083 | val[0] = INTVAL (low); | |
2084 | val[1] = INTVAL (high); | |
2085 | } | |
2086 | break; | |
fb16c776 | 2087 | |
8935d57c | 2088 | case CONST_DOUBLE: |
2089 | if (GET_MODE (operands[1]) == DFmode) | |
2090 | { | |
2091 | REAL_VALUE_TYPE rv; | |
2092 | ||
2093 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
2094 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
2095 | } | |
2096 | else if (GET_MODE (operands[1]) == VOIDmode | |
2097 | || GET_MODE (operands[1]) == DImode) | |
2098 | { | |
2099 | val[0] = CONST_DOUBLE_LOW (operands[1]); | |
2100 | val[1] = CONST_DOUBLE_HIGH (operands[1]); | |
2101 | } | |
2102 | break; | |
fb16c776 | 2103 | |
8935d57c | 2104 | default: |
2105 | return false; | |
2106 | } | |
2107 | ||
2108 | return val[0] == 0 || val[1] == 0; | |
2109 | } | |
b87a151a | 2110 | /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we |
2111 | may access it using GOTOFF instead of GOT. */ | |
2112 | ||
2113 | static void | |
48ed5fc2 | 2114 | mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED) |
b87a151a | 2115 | { |
2116 | rtx symbol; | |
2117 | ||
3626e955 | 2118 | if (! MEM_P (rtl)) |
b87a151a | 2119 | return; |
2120 | symbol = XEXP (rtl, 0); | |
2121 | if (GET_CODE (symbol) != SYMBOL_REF) | |
2122 | return; | |
2123 | ||
2124 | if (flag_pic) | |
2125 | SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl); | |
2126 | } | |
906bb5c3 | 2127 | |
2128 | /* Dispatch tables on the mn10300 are extremely expensive in terms of code | |
2129 | and readonly data size. So we crank up the case threshold value to | |
2130 | encourage a series of if/else comparisons to implement many small switch | |
2131 | statements. In theory, this value could be increased much more if we | |
2132 | were solely optimizing for space, but we keep it "reasonable" to avoid | |
2133 | serious code efficiency lossage. */ | |
2134 | ||
5574dbdd | 2135 | static unsigned int |
2136 | mn10300_case_values_threshold (void) | |
906bb5c3 | 2137 | { |
2138 | return 6; | |
2139 | } | |
3e16f982 | 2140 | |
2141 | /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE. */ | |
2142 | ||
2143 | static void | |
2144 | mn10300_asm_trampoline_template (FILE *f) | |
2145 | { | |
2146 | fprintf (f, "\tadd -4,sp\n"); | |
2147 | fprintf (f, "\t.long 0x0004fffa\n"); | |
2148 | fprintf (f, "\tmov (0,sp),a0\n"); | |
2149 | fprintf (f, "\tadd 4,sp\n"); | |
2150 | fprintf (f, "\tmov (13,a0),a1\n"); | |
2151 | fprintf (f, "\tmov (17,a0),a0\n"); | |
2152 | fprintf (f, "\tjmp (a0)\n"); | |
2153 | fprintf (f, "\t.long 0\n"); | |
2154 | fprintf (f, "\t.long 0\n"); | |
2155 | } | |
2156 | ||
2157 | /* Worker function for TARGET_TRAMPOLINE_INIT. */ | |
2158 | ||
2159 | static void | |
2160 | mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2161 | { | |
2162 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
2163 | rtx mem; | |
2164 | ||
2165 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
2166 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
2167 | ||
2168 | mem = adjust_address (m_tramp, SImode, 0x14); | |
2169 | emit_move_insn (mem, chain_value); | |
2170 | mem = adjust_address (m_tramp, SImode, 0x18); | |
2171 | emit_move_insn (mem, fnaddr); | |
2172 | } | |
e92d3ba8 | 2173 | |
2174 | /* Output the assembler code for a C++ thunk function. | |
2175 | THUNK_DECL is the declaration for the thunk function itself, FUNCTION | |
2176 | is the decl for the target function. DELTA is an immediate constant | |
2177 | offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero | |
2178 | the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be | |
2179 | additionally added to THIS. Finally jump to the entry point of | |
2180 | FUNCTION. */ | |
2181 | ||
2182 | static void | |
2183 | mn10300_asm_output_mi_thunk (FILE * file, | |
2184 | tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2185 | HOST_WIDE_INT delta, | |
2186 | HOST_WIDE_INT vcall_offset, | |
2187 | tree function) | |
2188 | { | |
2189 | const char * _this; | |
2190 | ||
2191 | /* Get the register holding the THIS parameter. Handle the case | |
2192 | where there is a hidden first argument for a returned structure. */ | |
2193 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
2194 | _this = reg_names [FIRST_ARGUMENT_REGNUM + 1]; | |
2195 | else | |
2196 | _this = reg_names [FIRST_ARGUMENT_REGNUM]; | |
2197 | ||
2198 | fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START); | |
2199 | ||
2200 | if (delta) | |
2201 | fprintf (file, "\tadd %d, %s\n", (int) delta, _this); | |
2202 | ||
2203 | if (vcall_offset) | |
2204 | { | |
2205 | const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1]; | |
2206 | ||
2207 | fprintf (file, "\tmov %s, %s\n", _this, scratch); | |
2208 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2209 | fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch); | |
2210 | fprintf (file, "\tmov (%s), %s\n", scratch, scratch); | |
2211 | fprintf (file, "\tadd %s, %s\n", scratch, _this); | |
2212 | } | |
2213 | ||
2214 | fputs ("\tjmp ", file); | |
2215 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2216 | putc ('\n', file); | |
2217 | } | |
2218 | ||
2219 | /* Return true if mn10300_output_mi_thunk would be able to output the | |
2220 | assembler code for the thunk function specified by the arguments | |
2221 | it is passed, and false otherwise. */ | |
2222 | ||
2223 | static bool | |
2224 | mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, | |
2225 | HOST_WIDE_INT delta ATTRIBUTE_UNUSED, | |
2226 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2227 | const_tree function ATTRIBUTE_UNUSED) | |
2228 | { | |
2229 | return true; | |
2230 | } | |
5574dbdd | 2231 | |
2232 | bool | |
2233 | mn10300_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) | |
2234 | { | |
2235 | if (REGNO_REG_CLASS (regno) == FP_REGS | |
2236 | || REGNO_REG_CLASS (regno) == FP_ACC_REGS) | |
2237 | /* Do not store integer values in FP registers. */ | |
2238 | return GET_MODE_CLASS (mode) == MODE_FLOAT && ((regno & 1) == 0); | |
2239 | ||
2240 | if (((regno) & 1) == 0 || GET_MODE_SIZE (mode) == 4) | |
2241 | return true; | |
2242 | ||
2243 | if (REGNO_REG_CLASS (regno) == DATA_REGS | |
2244 | || (TARGET_AM33 && REGNO_REG_CLASS (regno) == ADDRESS_REGS) | |
2245 | || REGNO_REG_CLASS (regno) == EXTENDED_REGS) | |
2246 | return GET_MODE_SIZE (mode) <= 4; | |
2247 | ||
2248 | return false; | |
2249 | } | |
2250 | ||
2251 | bool | |
2252 | mn10300_modes_tieable (enum machine_mode mode1, enum machine_mode mode2) | |
2253 | { | |
2254 | if (GET_MODE_CLASS (mode1) == MODE_FLOAT | |
2255 | && GET_MODE_CLASS (mode2) != MODE_FLOAT) | |
2256 | return false; | |
2257 | ||
2258 | if (GET_MODE_CLASS (mode2) == MODE_FLOAT | |
2259 | && GET_MODE_CLASS (mode1) != MODE_FLOAT) | |
2260 | return false; | |
2261 | ||
2262 | if (TARGET_AM33 | |
2263 | || mode1 == mode2 | |
2264 | || (GET_MODE_SIZE (mode1) <= 4 && GET_MODE_SIZE (mode2) <= 4)) | |
2265 | return true; | |
2266 | ||
2267 | return false; | |
2268 | } | |
2269 | ||
2270 | enum machine_mode | |
2271 | mn10300_select_cc_mode (rtx x) | |
2272 | { | |
2273 | return (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) ? CC_FLOATmode : CCmode; | |
2274 | } | |
2275 | \f | |
3626e955 | 2276 | /* Initialize the GCC target structure. */ |
2277 | ||
2278 | #undef TARGET_EXCEPT_UNWIND_INFO | |
2279 | #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info | |
2280 | ||
2281 | #undef TARGET_ASM_ALIGNED_HI_OP | |
2282 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
2283 | ||
2284 | #undef TARGET_LEGITIMIZE_ADDRESS | |
2285 | #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address | |
2286 | ||
2287 | #undef TARGET_RTX_COSTS | |
2288 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
2289 | #undef TARGET_ADDRESS_COST | |
2290 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
2291 | ||
2292 | #undef TARGET_ASM_FILE_START | |
2293 | #define TARGET_ASM_FILE_START mn10300_file_start | |
2294 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
2295 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
2296 | ||
2297 | #undef TARGET_DEFAULT_TARGET_FLAGS | |
2298 | #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0 | |
2299 | #undef TARGET_HANDLE_OPTION | |
2300 | #define TARGET_HANDLE_OPTION mn10300_handle_option | |
2301 | #undef TARGET_OPTION_OVERRIDE | |
2302 | #define TARGET_OPTION_OVERRIDE mn10300_option_override | |
c17f64cc | 2303 | #undef TARGET_OPTION_OPTIMIZATION_TABLE |
2304 | #define TARGET_OPTION_OPTIMIZATION_TABLE mn10300_option_optimization_table | |
3626e955 | 2305 | |
2306 | #undef TARGET_ENCODE_SECTION_INFO | |
2307 | #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info | |
2308 | ||
2309 | #undef TARGET_PROMOTE_PROTOTYPES | |
2310 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
2311 | #undef TARGET_RETURN_IN_MEMORY | |
2312 | #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory | |
2313 | #undef TARGET_PASS_BY_REFERENCE | |
2314 | #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference | |
2315 | #undef TARGET_CALLEE_COPIES | |
2316 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
2317 | #undef TARGET_ARG_PARTIAL_BYTES | |
2318 | #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes | |
dc67179a | 2319 | #undef TARGET_FUNCTION_ARG |
2320 | #define TARGET_FUNCTION_ARG mn10300_function_arg | |
2321 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
2322 | #define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance | |
3626e955 | 2323 | |
2324 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
2325 | #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs | |
2326 | #undef TARGET_EXPAND_BUILTIN_VA_START | |
2327 | #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start | |
2328 | ||
2329 | #undef TARGET_CASE_VALUES_THRESHOLD | |
2330 | #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold | |
2331 | ||
2332 | #undef TARGET_LEGITIMATE_ADDRESS_P | |
2333 | #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p | |
2334 | ||
2335 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE | |
2336 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE mn10300_asm_trampoline_template | |
2337 | #undef TARGET_TRAMPOLINE_INIT | |
2338 | #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init | |
2339 | ||
2340 | #undef TARGET_FUNCTION_VALUE | |
2341 | #define TARGET_FUNCTION_VALUE mn10300_function_value | |
2342 | #undef TARGET_LIBCALL_VALUE | |
2343 | #define TARGET_LIBCALL_VALUE mn10300_libcall_value | |
2344 | ||
2345 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
2346 | #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk | |
2347 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
2348 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk | |
2349 | ||
2350 | struct gcc_target targetm = TARGET_INITIALIZER; |