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11bb1f11 | 1 | /* Subroutines for insn-output.c for Matsushita MN10300 series |
a58be199 | 2 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
92547f12 | 3 | Free Software Foundation, Inc. |
11bb1f11 JL |
4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
11bb1f11 | 23 | #include "config.h" |
c5c76735 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
11bb1f11 | 27 | #include "rtl.h" |
bf6bb899 | 28 | #include "tree.h" |
11bb1f11 JL |
29 | #include "regs.h" |
30 | #include "hard-reg-set.h" | |
31 | #include "real.h" | |
32 | #include "insn-config.h" | |
33 | #include "conditions.h" | |
11bb1f11 JL |
34 | #include "output.h" |
35 | #include "insn-attr.h" | |
36 | #include "flags.h" | |
37 | #include "recog.h" | |
38 | #include "expr.h" | |
e78d8e51 | 39 | #include "optabs.h" |
bf6bb899 | 40 | #include "function.h" |
11bb1f11 | 41 | #include "obstack.h" |
69bc71fa KG |
42 | #include "toplev.h" |
43 | #include "tm_p.h" | |
672a6f42 NB |
44 | #include "target.h" |
45 | #include "target-def.h" | |
11bb1f11 | 46 | |
4d1a91c2 JL |
47 | /* The size of the callee register save area. Right now we save everything |
48 | on entry since it costs us nothing in code size. It does cost us from a | |
49 | speed standpoint, so we want to optimize this sooner or later. */ | |
980d0e81 JL |
50 | #define REG_SAVE_BYTES (4 * regs_ever_live[2] \ |
51 | + 4 * regs_ever_live[3] \ | |
705ac34f JL |
52 | + 4 * regs_ever_live[6] \ |
53 | + 4 * regs_ever_live[7] \ | |
54 | + 16 * (regs_ever_live[14] || regs_ever_live[15] \ | |
55 | || regs_ever_live[16] || regs_ever_live[17])) | |
3c50106f RH |
56 | |
57 | ||
dcefdf67 RH |
58 | static int mn10300_address_cost_1 PARAMS ((rtx, int *)); |
59 | static int mn10300_address_cost PARAMS ((rtx)); | |
3c50106f RH |
60 | static bool mn10300_rtx_costs PARAMS ((rtx, int, int, int *)); |
61 | ||
672a6f42 NB |
62 | \f |
63 | /* Initialize the GCC target structure. */ | |
301d03af RS |
64 | #undef TARGET_ASM_ALIGNED_HI_OP |
65 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
4d1a91c2 | 66 | |
3c50106f RH |
67 | #undef TARGET_RTX_COSTS |
68 | #define TARGET_RTX_COSTS mn10300_rtx_costs | |
dcefdf67 RH |
69 | #undef TARGET_ADDRESS_COST |
70 | #define TARGET_ADDRESS_COST mn10300_address_cost | |
3c50106f | 71 | |
f6897b10 | 72 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 73 | \f |
11bb1f11 JL |
74 | void |
75 | asm_file_start (file) | |
76 | FILE *file; | |
77 | { | |
78 | fprintf (file, "#\tGCC For the Matsushita MN10300\n"); | |
79 | if (optimize) | |
80 | fprintf (file, "# -O%d\n", optimize); | |
81 | else | |
82 | fprintf (file, "\n\n"); | |
705ac34f JL |
83 | |
84 | if (TARGET_AM33) | |
85 | fprintf (file, "\t.am33\n"); | |
11bb1f11 JL |
86 | output_file_directive (file, main_input_filename); |
87 | } | |
88 | \f | |
89 | ||
11bb1f11 JL |
90 | /* Print operand X using operand code CODE to assembly language output file |
91 | FILE. */ | |
92 | ||
93 | void | |
94 | print_operand (file, x, code) | |
95 | FILE *file; | |
96 | rtx x; | |
97 | int code; | |
98 | { | |
99 | switch (code) | |
100 | { | |
101 | case 'b': | |
102 | case 'B': | |
103 | /* These are normal and reversed branches. */ | |
104 | switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x))) | |
105 | { | |
106 | case NE: | |
107 | fprintf (file, "ne"); | |
108 | break; | |
109 | case EQ: | |
110 | fprintf (file, "eq"); | |
111 | break; | |
112 | case GE: | |
113 | fprintf (file, "ge"); | |
114 | break; | |
115 | case GT: | |
116 | fprintf (file, "gt"); | |
117 | break; | |
118 | case LE: | |
119 | fprintf (file, "le"); | |
120 | break; | |
121 | case LT: | |
122 | fprintf (file, "lt"); | |
123 | break; | |
124 | case GEU: | |
125 | fprintf (file, "cc"); | |
126 | break; | |
127 | case GTU: | |
128 | fprintf (file, "hi"); | |
129 | break; | |
130 | case LEU: | |
131 | fprintf (file, "ls"); | |
132 | break; | |
133 | case LTU: | |
134 | fprintf (file, "cs"); | |
135 | break; | |
136 | default: | |
137 | abort (); | |
138 | } | |
139 | break; | |
140 | case 'C': | |
141 | /* This is used for the operand to a call instruction; | |
142 | if it's a REG, enclose it in parens, else output | |
143 | the operand normally. */ | |
144 | if (GET_CODE (x) == REG) | |
145 | { | |
146 | fputc ('(', file); | |
147 | print_operand (file, x, 0); | |
148 | fputc (')', file); | |
149 | } | |
150 | else | |
151 | print_operand (file, x, 0); | |
152 | break; | |
153 | ||
38c37a0e JL |
154 | /* These are the least significant word in a 64bit value. */ |
155 | case 'L': | |
156 | switch (GET_CODE (x)) | |
157 | { | |
158 | case MEM: | |
159 | fputc ('(', file); | |
160 | output_address (XEXP (x, 0)); | |
161 | fputc (')', file); | |
162 | break; | |
163 | ||
164 | case REG: | |
165 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
166 | break; | |
167 | ||
168 | case SUBREG: | |
ddef6bc7 | 169 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
38c37a0e JL |
170 | break; |
171 | ||
172 | case CONST_DOUBLE: | |
173 | { | |
174 | long val[2]; | |
175 | REAL_VALUE_TYPE rv; | |
176 | ||
177 | switch (GET_MODE (x)) | |
178 | { | |
179 | case DFmode: | |
180 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
181 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 182 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
183 | break;; |
184 | case SFmode: | |
185 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
186 | REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]); | |
cf31fafa | 187 | fprintf (file, "0x%lx", val[0]); |
38c37a0e JL |
188 | break;; |
189 | case VOIDmode: | |
190 | case DImode: | |
191 | print_operand_address (file, | |
192 | GEN_INT (CONST_DOUBLE_LOW (x))); | |
193 | break; | |
69bc71fa KG |
194 | default: |
195 | break; | |
38c37a0e JL |
196 | } |
197 | break; | |
198 | } | |
199 | ||
200 | case CONST_INT: | |
212bc5fa AO |
201 | { |
202 | rtx low, high; | |
203 | split_double (x, &low, &high); | |
204 | fprintf (file, "%ld", (long)INTVAL (low)); | |
205 | break; | |
206 | } | |
38c37a0e JL |
207 | |
208 | default: | |
209 | abort (); | |
210 | } | |
211 | break; | |
212 | ||
213 | /* Similarly, but for the most significant word. */ | |
214 | case 'H': | |
215 | switch (GET_CODE (x)) | |
216 | { | |
217 | case MEM: | |
218 | fputc ('(', file); | |
b72f00af | 219 | x = adjust_address (x, SImode, 4); |
38c37a0e JL |
220 | output_address (XEXP (x, 0)); |
221 | fputc (')', file); | |
222 | break; | |
223 | ||
224 | case REG: | |
225 | fprintf (file, "%s", reg_names[REGNO (x) + 1]); | |
226 | break; | |
227 | ||
228 | case SUBREG: | |
ddef6bc7 | 229 | fprintf (file, "%s", reg_names[subreg_regno (x) + 1]); |
38c37a0e JL |
230 | break; |
231 | ||
232 | case CONST_DOUBLE: | |
233 | { | |
234 | long val[2]; | |
235 | REAL_VALUE_TYPE rv; | |
236 | ||
237 | switch (GET_MODE (x)) | |
238 | { | |
239 | case DFmode: | |
240 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
241 | REAL_VALUE_TO_TARGET_DOUBLE (rv, val); | |
cf31fafa | 242 | fprintf (file, "0x%lx", val[1]); |
38c37a0e JL |
243 | break;; |
244 | case SFmode: | |
245 | abort (); | |
246 | case VOIDmode: | |
247 | case DImode: | |
248 | print_operand_address (file, | |
249 | GEN_INT (CONST_DOUBLE_HIGH (x))); | |
250 | break; | |
69bc71fa KG |
251 | default: |
252 | break; | |
38c37a0e JL |
253 | } |
254 | break; | |
255 | } | |
256 | ||
257 | case CONST_INT: | |
212bc5fa AO |
258 | { |
259 | rtx low, high; | |
260 | split_double (x, &low, &high); | |
261 | fprintf (file, "%ld", (long)INTVAL (high)); | |
262 | break; | |
263 | } | |
264 | ||
38c37a0e JL |
265 | default: |
266 | abort (); | |
267 | } | |
268 | break; | |
269 | ||
270 | case 'A': | |
271 | fputc ('(', file); | |
272 | if (GET_CODE (XEXP (x, 0)) == REG) | |
c5c76735 | 273 | output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0))); |
38c37a0e JL |
274 | else |
275 | output_address (XEXP (x, 0)); | |
276 | fputc (')', file); | |
277 | break; | |
278 | ||
6fafc523 | 279 | case 'N': |
a58be199 AO |
280 | if (INTVAL (x) < -128 || INTVAL (x) > 255) |
281 | abort (); | |
282 | fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff)); | |
283 | break; | |
284 | ||
285 | case 'U': | |
286 | if (INTVAL (x) < -128 || INTVAL (x) > 255) | |
287 | abort (); | |
288 | fprintf (file, "%d", (int)(INTVAL (x) & 0xff)); | |
6fafc523 JL |
289 | break; |
290 | ||
576e5acc JL |
291 | /* For shift counts. The hardware ignores the upper bits of |
292 | any immediate, but the assembler will flag an out of range | |
293 | shift count as an error. So we mask off the high bits | |
294 | of the immediate here. */ | |
295 | case 'S': | |
296 | if (GET_CODE (x) == CONST_INT) | |
297 | { | |
a58be199 | 298 | fprintf (file, "%d", (int)(INTVAL (x) & 0x1f)); |
576e5acc JL |
299 | break; |
300 | } | |
301 | /* FALL THROUGH */ | |
302 | ||
11bb1f11 JL |
303 | default: |
304 | switch (GET_CODE (x)) | |
305 | { | |
306 | case MEM: | |
307 | fputc ('(', file); | |
308 | output_address (XEXP (x, 0)); | |
309 | fputc (')', file); | |
310 | break; | |
311 | ||
38c37a0e JL |
312 | case PLUS: |
313 | output_address (x); | |
314 | break; | |
315 | ||
11bb1f11 JL |
316 | case REG: |
317 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
318 | break; | |
319 | ||
320 | case SUBREG: | |
ddef6bc7 | 321 | fprintf (file, "%s", reg_names[subreg_regno (x)]); |
11bb1f11 JL |
322 | break; |
323 | ||
38c37a0e JL |
324 | /* This will only be single precision.... */ |
325 | case CONST_DOUBLE: | |
326 | { | |
327 | unsigned long val; | |
328 | REAL_VALUE_TYPE rv; | |
329 | ||
330 | REAL_VALUE_FROM_CONST_DOUBLE (rv, x); | |
331 | REAL_VALUE_TO_TARGET_SINGLE (rv, val); | |
cf31fafa | 332 | fprintf (file, "0x%lx", val); |
38c37a0e JL |
333 | break; |
334 | } | |
335 | ||
11bb1f11 JL |
336 | case CONST_INT: |
337 | case SYMBOL_REF: | |
338 | case CONST: | |
339 | case LABEL_REF: | |
340 | case CODE_LABEL: | |
341 | print_operand_address (file, x); | |
342 | break; | |
343 | default: | |
344 | abort (); | |
345 | } | |
346 | break; | |
347 | } | |
348 | } | |
349 | ||
350 | /* Output assembly language output for the address ADDR to FILE. */ | |
351 | ||
352 | void | |
353 | print_operand_address (file, addr) | |
354 | FILE *file; | |
355 | rtx addr; | |
356 | { | |
357 | switch (GET_CODE (addr)) | |
358 | { | |
705ac34f JL |
359 | case POST_INC: |
360 | print_operand_address (file, XEXP (addr, 0)); | |
361 | fputc ('+', file); | |
362 | break; | |
11bb1f11 | 363 | case REG: |
79e4122c | 364 | print_operand (file, addr, 0); |
11bb1f11 JL |
365 | break; |
366 | case PLUS: | |
367 | { | |
368 | rtx base, index; | |
369 | if (REG_P (XEXP (addr, 0)) | |
370 | && REG_OK_FOR_BASE_P (XEXP (addr, 0))) | |
371 | base = XEXP (addr, 0), index = XEXP (addr, 1); | |
372 | else if (REG_P (XEXP (addr, 1)) | |
373 | && REG_OK_FOR_BASE_P (XEXP (addr, 1))) | |
374 | base = XEXP (addr, 1), index = XEXP (addr, 0); | |
375 | else | |
376 | abort (); | |
377 | print_operand (file, index, 0); | |
378 | fputc (',', file); | |
379 | print_operand (file, base, 0);; | |
380 | break; | |
381 | } | |
382 | case SYMBOL_REF: | |
383 | output_addr_const (file, addr); | |
384 | break; | |
385 | default: | |
386 | output_addr_const (file, addr); | |
387 | break; | |
388 | } | |
389 | } | |
390 | ||
f6cd7c62 RS |
391 | /* Print a set of registers in the format required by "movm" and "ret". |
392 | Register K is saved if bit K of MASK is set. The data and address | |
393 | registers can be stored individually, but the extended registers cannot. | |
394 | We assume that the mask alread takes that into account. For instance, | |
395 | bits 14 to 17 must have the same value. */ | |
396 | ||
397 | void | |
398 | mn10300_print_reg_list (file, mask) | |
399 | FILE *file; | |
400 | int mask; | |
401 | { | |
402 | int need_comma; | |
403 | int i; | |
404 | ||
405 | need_comma = 0; | |
406 | fputc ('[', file); | |
407 | ||
408 | for (i = 0; i < FIRST_EXTENDED_REGNUM; i++) | |
409 | if ((mask & (1 << i)) != 0) | |
410 | { | |
411 | if (need_comma) | |
412 | fputc (',', file); | |
413 | fputs (reg_names [i], file); | |
414 | need_comma = 1; | |
415 | } | |
416 | ||
417 | if ((mask & 0x3c000) != 0) | |
418 | { | |
419 | if ((mask & 0x3c000) != 0x3c000) | |
420 | abort(); | |
421 | if (need_comma) | |
422 | fputc (',', file); | |
423 | fputs ("exreg1", file); | |
424 | need_comma = 1; | |
425 | } | |
426 | ||
427 | fputc (']', file); | |
428 | } | |
429 | ||
38c37a0e JL |
430 | int |
431 | can_use_return_insn () | |
432 | { | |
460f4b9d JL |
433 | /* size includes the fixed stack space needed for function calls. */ |
434 | int size = get_frame_size () + current_function_outgoing_args_size; | |
435 | ||
436 | /* And space for the return pointer. */ | |
437 | size += current_function_outgoing_args_size ? 4 : 0; | |
38c37a0e JL |
438 | |
439 | return (reload_completed | |
440 | && size == 0 | |
441 | && !regs_ever_live[2] | |
442 | && !regs_ever_live[3] | |
443 | && !regs_ever_live[6] | |
444 | && !regs_ever_live[7] | |
705ac34f JL |
445 | && !regs_ever_live[14] |
446 | && !regs_ever_live[15] | |
447 | && !regs_ever_live[16] | |
448 | && !regs_ever_live[17] | |
38c37a0e JL |
449 | && !frame_pointer_needed); |
450 | } | |
451 | ||
f6cd7c62 RS |
452 | /* Returns the set of live, callee-saved registers as a bitmask. The |
453 | callee-saved extended registers cannot be stored individually, so | |
454 | all of them will be included in the mask if any one of them is used. */ | |
455 | ||
456 | int | |
457 | mn10300_get_live_callee_saved_regs () | |
458 | { | |
459 | int mask; | |
460 | int i; | |
461 | ||
462 | mask = 0; | |
463 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
464 | if (regs_ever_live[i] && ! call_used_regs[i]) | |
465 | mask |= (1 << i); | |
466 | if ((mask & 0x3c000) != 0) | |
467 | mask |= 0x3c000; | |
468 | ||
469 | return mask; | |
470 | } | |
471 | ||
472 | /* Generate an instruction that pushes several registers onto the stack. | |
473 | Register K will be saved if bit K in MASK is set. The function does | |
474 | nothing if MASK is zero. | |
475 | ||
476 | To be compatible with the "movm" instruction, the lowest-numbered | |
477 | register must be stored in the lowest slot. If MASK is the set | |
478 | { R1,...,RN }, where R1...RN are ordered least first, the generated | |
479 | instruction will have the form: | |
480 | ||
481 | (parallel | |
482 | (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4))) | |
483 | (set (mem:SI (plus:SI (reg:SI 9) | |
484 | (const_int -1*4))) | |
485 | (reg:SI RN)) | |
486 | ... | |
487 | (set (mem:SI (plus:SI (reg:SI 9) | |
488 | (const_int -N*4))) | |
489 | (reg:SI R1))) */ | |
490 | ||
491 | void | |
492 | mn10300_gen_multiple_store (mask) | |
493 | int mask; | |
494 | { | |
495 | if (mask != 0) | |
496 | { | |
497 | int i; | |
498 | int count; | |
499 | rtx par; | |
500 | int pari; | |
501 | ||
502 | /* Count how many registers need to be saved. */ | |
503 | count = 0; | |
504 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
505 | if ((mask & (1 << i)) != 0) | |
506 | count += 1; | |
507 | ||
508 | /* We need one PARALLEL element to update the stack pointer and | |
509 | an additional element for each register that is stored. */ | |
510 | par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); | |
511 | ||
512 | /* Create the instruction that updates the stack pointer. */ | |
513 | XVECEXP (par, 0, 0) | |
514 | = gen_rtx_SET (SImode, | |
515 | stack_pointer_rtx, | |
516 | gen_rtx_PLUS (SImode, | |
517 | stack_pointer_rtx, | |
518 | GEN_INT (-count * 4))); | |
519 | ||
520 | /* Create each store. */ | |
521 | pari = 1; | |
522 | for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) | |
523 | if ((mask & (1 << i)) != 0) | |
524 | { | |
525 | rtx address = gen_rtx_PLUS (SImode, | |
526 | stack_pointer_rtx, | |
527 | GEN_INT (-pari * 4)); | |
528 | XVECEXP(par, 0, pari) | |
529 | = gen_rtx_SET (VOIDmode, | |
530 | gen_rtx_MEM (SImode, address), | |
531 | gen_rtx_REG (SImode, i)); | |
532 | pari += 1; | |
533 | } | |
534 | ||
535 | par = emit_insn (par); | |
536 | RTX_FRAME_RELATED_P (par) = 1; | |
537 | } | |
538 | } | |
539 | ||
11bb1f11 JL |
540 | void |
541 | expand_prologue () | |
542 | { | |
036182e7 | 543 | HOST_WIDE_INT size; |
3dbc43d1 | 544 | |
3dbc43d1 | 545 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
546 | size = get_frame_size () + current_function_outgoing_args_size; |
547 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 548 | |
f6cd7c62 RS |
549 | /* If we use any of the callee-saved registers, save them now. */ |
550 | mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ()); | |
777fbf09 JL |
551 | |
552 | /* Now put the frame pointer into the frame pointer register. */ | |
11bb1f11 | 553 | if (frame_pointer_needed) |
6e86170d | 554 | emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); |
11bb1f11 | 555 | |
777fbf09 | 556 | /* Allocate stack for this frame. */ |
11bb1f11 JL |
557 | if (size) |
558 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
559 | stack_pointer_rtx, | |
560 | GEN_INT (-size))); | |
561 | } | |
562 | ||
563 | void | |
564 | expand_epilogue () | |
565 | { | |
036182e7 | 566 | HOST_WIDE_INT size; |
3dbc43d1 | 567 | |
3dbc43d1 | 568 | /* SIZE includes the fixed stack space needed for function calls. */ |
460f4b9d JL |
569 | size = get_frame_size () + current_function_outgoing_args_size; |
570 | size += (current_function_outgoing_args_size ? 4 : 0); | |
11bb1f11 | 571 | |
5d29a95f JL |
572 | /* Maybe cut back the stack, except for the register save area. |
573 | ||
574 | If the frame pointer exists, then use the frame pointer to | |
575 | cut back the stack. | |
576 | ||
577 | If the stack size + register save area is more than 255 bytes, | |
578 | then the stack must be cut back here since the size + register | |
579 | save size is too big for a ret/retf instruction. | |
580 | ||
581 | Else leave it alone, it will be cut back as part of the | |
582 | ret/retf instruction, or there wasn't any stack to begin with. | |
583 | ||
584 | Under no circumstanes should the register save area be | |
585 | deallocated here, that would leave a window where an interrupt | |
586 | could occur and trash the register save area. */ | |
11bb1f11 JL |
587 | if (frame_pointer_needed) |
588 | { | |
11bb1f11 | 589 | emit_move_insn (stack_pointer_rtx, frame_pointer_rtx); |
4246e0c5 JL |
590 | size = 0; |
591 | } | |
ed6089d6 | 592 | else if (size + REG_SAVE_BYTES > 255) |
4246e0c5 JL |
593 | { |
594 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
595 | stack_pointer_rtx, | |
596 | GEN_INT (size))); | |
597 | size = 0; | |
11bb1f11 | 598 | } |
11bb1f11 | 599 | |
ed6089d6 AO |
600 | /* Adjust the stack and restore callee-saved registers, if any. */ |
601 | if (size || regs_ever_live[2] || regs_ever_live[3] | |
777fbf09 | 602 | || regs_ever_live[6] || regs_ever_live[7] |
705ac34f JL |
603 | || regs_ever_live[14] || regs_ever_live[15] |
604 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 | 605 | || frame_pointer_needed) |
ed6089d6 AO |
606 | emit_jump_insn (gen_return_internal_regs |
607 | (GEN_INT (size + REG_SAVE_BYTES))); | |
777fbf09 | 608 | else |
ed6089d6 | 609 | emit_jump_insn (gen_return_internal ()); |
11bb1f11 JL |
610 | } |
611 | ||
612 | /* Update the condition code from the insn. */ | |
613 | ||
614 | void | |
615 | notice_update_cc (body, insn) | |
616 | rtx body; | |
617 | rtx insn; | |
618 | { | |
11bb1f11 JL |
619 | switch (get_attr_cc (insn)) |
620 | { | |
621 | case CC_NONE: | |
622 | /* Insn does not affect CC at all. */ | |
623 | break; | |
624 | ||
625 | case CC_NONE_0HIT: | |
626 | /* Insn does not change CC, but the 0'th operand has been changed. */ | |
627 | if (cc_status.value1 != 0 | |
1ccbefce | 628 | && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) |
11bb1f11 JL |
629 | cc_status.value1 = 0; |
630 | break; | |
631 | ||
d116300b | 632 | case CC_SET_ZN: |
1ccbefce | 633 | /* Insn sets the Z,N flags of CC to recog_data.operand[0]. |
d116300b | 634 | V,C are unusable. */ |
11bb1f11 | 635 | CC_STATUS_INIT; |
d116300b | 636 | cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE; |
1ccbefce | 637 | cc_status.value1 = recog_data.operand[0]; |
11bb1f11 JL |
638 | break; |
639 | ||
d116300b | 640 | case CC_SET_ZNV: |
1ccbefce | 641 | /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. |
d116300b | 642 | C is unusable. */ |
82c6faa8 | 643 | CC_STATUS_INIT; |
d116300b | 644 | cc_status.flags |= CC_NO_CARRY; |
1ccbefce | 645 | cc_status.value1 = recog_data.operand[0]; |
82c6faa8 JL |
646 | break; |
647 | ||
11bb1f11 JL |
648 | case CC_COMPARE: |
649 | /* The insn is a compare instruction. */ | |
650 | CC_STATUS_INIT; | |
651 | cc_status.value1 = SET_SRC (body); | |
652 | break; | |
653 | ||
3b800f71 JL |
654 | case CC_INVERT: |
655 | /* The insn is a compare instruction. */ | |
656 | CC_STATUS_INIT; | |
657 | cc_status.value1 = SET_SRC (body); | |
658 | cc_status.flags |= CC_INVERTED; | |
659 | break; | |
660 | ||
11bb1f11 JL |
661 | case CC_CLOBBER: |
662 | /* Insn doesn't leave CC in a usable state. */ | |
663 | CC_STATUS_INIT; | |
664 | break; | |
82c6faa8 JL |
665 | |
666 | default: | |
667 | abort (); | |
11bb1f11 | 668 | } |
11bb1f11 JL |
669 | } |
670 | ||
05713b80 | 671 | /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store(). |
f6cd7c62 RS |
672 | This function is for MATCH_PARALLEL and so assumes OP is known to be |
673 | parallel. If OP is a multiple store, return a mask indicating which | |
674 | registers it saves. Return 0 otherwise. */ | |
675 | ||
676 | int | |
677 | store_multiple_operation (op, mode) | |
678 | rtx op; | |
679 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
680 | { | |
681 | int count; | |
682 | int mask; | |
683 | int i; | |
684 | unsigned int last; | |
685 | rtx elt; | |
686 | ||
687 | count = XVECLEN (op, 0); | |
688 | if (count < 2) | |
689 | return 0; | |
690 | ||
691 | /* Check that first instruction has the form (set (sp) (plus A B)) */ | |
692 | elt = XVECEXP (op, 0, 0); | |
693 | if (GET_CODE (elt) != SET | |
694 | || GET_CODE (SET_DEST (elt)) != REG | |
695 | || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM | |
696 | || GET_CODE (SET_SRC (elt)) != PLUS) | |
697 | return 0; | |
698 | ||
699 | /* Check that A is the stack pointer and B is the expected stack size. | |
700 | For OP to match, each subsequent instruction should push a word onto | |
701 | the stack. We therefore expect the first instruction to create | |
702 | COUNT-1 stack slots. */ | |
703 | elt = SET_SRC (elt); | |
704 | if (GET_CODE (XEXP (elt, 0)) != REG | |
705 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
706 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
707 | || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4) | |
708 | return 0; | |
709 | ||
710 | /* Now go through the rest of the vector elements. They must be | |
711 | ordered so that the first instruction stores the highest-numbered | |
712 | register to the highest stack slot and that subsequent instructions | |
713 | store a lower-numbered register to the slot below. | |
714 | ||
715 | LAST keeps track of the smallest-numbered register stored so far. | |
716 | MASK is the set of stored registers. */ | |
717 | last = FIRST_PSEUDO_REGISTER; | |
718 | mask = 0; | |
719 | for (i = 1; i < count; i++) | |
720 | { | |
721 | /* Check that element i is a (set (mem M) R) and that R is valid. */ | |
722 | elt = XVECEXP (op, 0, i); | |
723 | if (GET_CODE (elt) != SET | |
724 | || GET_CODE (SET_DEST (elt)) != MEM | |
725 | || GET_CODE (SET_SRC (elt)) != REG | |
726 | || REGNO (SET_SRC (elt)) >= last) | |
727 | return 0; | |
728 | ||
729 | /* R was OK, so provisionally add it to MASK. We return 0 in any | |
730 | case if the rest of the instruction has a flaw. */ | |
731 | last = REGNO (SET_SRC (elt)); | |
732 | mask |= (1 << last); | |
733 | ||
734 | /* Check that M has the form (plus (sp) (const_int -I*4)) */ | |
735 | elt = XEXP (SET_DEST (elt), 0); | |
736 | if (GET_CODE (elt) != PLUS | |
737 | || GET_CODE (XEXP (elt, 0)) != REG | |
738 | || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM | |
739 | || GET_CODE (XEXP (elt, 1)) != CONST_INT | |
740 | || INTVAL (XEXP (elt, 1)) != -i * 4) | |
741 | return 0; | |
742 | } | |
743 | ||
744 | /* All or none of the callee-saved extended registers must be in the set. */ | |
745 | if ((mask & 0x3c000) != 0 | |
746 | && (mask & 0x3c000) != 0x3c000) | |
747 | return 0; | |
748 | ||
749 | return mask; | |
750 | } | |
751 | ||
11bb1f11 JL |
752 | /* Return true if OP is a valid call operand. */ |
753 | ||
754 | int | |
755 | call_address_operand (op, mode) | |
756 | rtx op; | |
69bc71fa | 757 | enum machine_mode mode ATTRIBUTE_UNUSED; |
11bb1f11 JL |
758 | { |
759 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG); | |
760 | } | |
761 | ||
762 | /* What (if any) secondary registers are needed to move IN with mode | |
8493cfcb | 763 | MODE into a register in register class CLASS. |
11bb1f11 JL |
764 | |
765 | We might be able to simplify this. */ | |
766 | enum reg_class | |
767 | secondary_reload_class (class, mode, in) | |
768 | enum reg_class class; | |
769 | enum machine_mode mode; | |
770 | rtx in; | |
771 | { | |
11bb1f11 JL |
772 | /* Memory loads less than a full word wide can't have an |
773 | address or stack pointer destination. They must use | |
774 | a data register as an intermediate register. */ | |
15c09738 AH |
775 | if ((GET_CODE (in) == MEM |
776 | || (GET_CODE (in) == REG | |
777 | && REGNO (in) >= FIRST_PSEUDO_REGISTER) | |
778 | || (GET_CODE (in) == SUBREG | |
779 | && GET_CODE (SUBREG_REG (in)) == REG | |
780 | && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER)) | |
11bb1f11 | 781 | && (mode == QImode || mode == HImode) |
15c09738 | 782 | && (class == ADDRESS_REGS || class == SP_REGS |
842a0788 | 783 | || class == SP_OR_ADDRESS_REGS)) |
4d1a91c2 | 784 | { |
705ac34f JL |
785 | if (TARGET_AM33) |
786 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
787 | return DATA_REGS; |
788 | } | |
11bb1f11 JL |
789 | |
790 | /* We can't directly load sp + const_int into a data register; | |
791 | we must use an address register as an intermediate. */ | |
777fbf09 JL |
792 | if (class != SP_REGS |
793 | && class != ADDRESS_REGS | |
794 | && class != SP_OR_ADDRESS_REGS | |
705ac34f JL |
795 | && class != SP_OR_EXTENDED_REGS |
796 | && class != ADDRESS_OR_EXTENDED_REGS | |
797 | && class != SP_OR_ADDRESS_OR_EXTENDED_REGS | |
11bb1f11 JL |
798 | && (in == stack_pointer_rtx |
799 | || (GET_CODE (in) == PLUS | |
777fbf09 JL |
800 | && (XEXP (in, 0) == stack_pointer_rtx |
801 | || XEXP (in, 1) == stack_pointer_rtx)))) | |
11bb1f11 JL |
802 | return ADDRESS_REGS; |
803 | ||
4c742813 JL |
804 | if (GET_CODE (in) == PLUS |
805 | && (XEXP (in, 0) == stack_pointer_rtx | |
806 | || XEXP (in, 1) == stack_pointer_rtx)) | |
4d1a91c2 | 807 | { |
705ac34f JL |
808 | if (TARGET_AM33) |
809 | return DATA_OR_EXTENDED_REGS; | |
4d1a91c2 JL |
810 | return DATA_REGS; |
811 | } | |
4c742813 | 812 | |
777fbf09 JL |
813 | /* Otherwise assume no secondary reloads are needed. */ |
814 | return NO_REGS; | |
815 | } | |
816 | ||
817 | int | |
818 | initial_offset (from, to) | |
819 | int from, to; | |
820 | { | |
3dbc43d1 JL |
821 | /* The difference between the argument pointer and the frame pointer |
822 | is the size of the callee register save area. */ | |
777fbf09 | 823 | if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) |
11bb1f11 | 824 | { |
777fbf09 JL |
825 | if (regs_ever_live[2] || regs_ever_live[3] |
826 | || regs_ever_live[6] || regs_ever_live[7] | |
705ac34f JL |
827 | || regs_ever_live[14] || regs_ever_live[15] |
828 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 | 829 | || frame_pointer_needed) |
4d1a91c2 | 830 | return REG_SAVE_BYTES; |
777fbf09 | 831 | else |
22ef4e9b | 832 | return 0; |
11bb1f11 JL |
833 | } |
834 | ||
3dbc43d1 JL |
835 | /* The difference between the argument pointer and the stack pointer is |
836 | the sum of the size of this function's frame, the callee register save | |
837 | area, and the fixed stack space needed for function calls (if any). */ | |
777fbf09 JL |
838 | if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
839 | { | |
840 | if (regs_ever_live[2] || regs_ever_live[3] | |
841 | || regs_ever_live[6] || regs_ever_live[7] | |
705ac34f JL |
842 | || regs_ever_live[14] || regs_ever_live[15] |
843 | || regs_ever_live[16] || regs_ever_live[17] | |
777fbf09 | 844 | || frame_pointer_needed) |
4d1a91c2 | 845 | return (get_frame_size () + REG_SAVE_BYTES |
460f4b9d JL |
846 | + (current_function_outgoing_args_size |
847 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 | 848 | else |
460f4b9d JL |
849 | return (get_frame_size () |
850 | + (current_function_outgoing_args_size | |
851 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 | 852 | } |
11bb1f11 | 853 | |
3dbc43d1 JL |
854 | /* The difference between the frame pointer and stack pointer is the sum |
855 | of the size of this function's frame and the fixed stack space needed | |
856 | for function calls (if any). */ | |
777fbf09 | 857 | if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM) |
460f4b9d JL |
858 | return (get_frame_size () |
859 | + (current_function_outgoing_args_size | |
860 | ? current_function_outgoing_args_size + 4 : 0)); | |
777fbf09 JL |
861 | |
862 | abort (); | |
11bb1f11 | 863 | } |
22ef4e9b JL |
864 | |
865 | /* Flush the argument registers to the stack for a stdarg function; | |
866 | return the new argument pointer. */ | |
867 | rtx | |
648d2ffc | 868 | mn10300_builtin_saveregs () |
22ef4e9b | 869 | { |
fc2acc87 | 870 | rtx offset, mem; |
22ef4e9b JL |
871 | tree fntype = TREE_TYPE (current_function_decl); |
872 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
873 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
874 | != void_type_node))) | |
875 | ? UNITS_PER_WORD : 0); | |
fc2acc87 | 876 | int set = get_varargs_alias_set (); |
22ef4e9b JL |
877 | |
878 | if (argadj) | |
879 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
880 | else | |
881 | offset = current_function_arg_offset_rtx; | |
882 | ||
fc2acc87 | 883 | mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer); |
ba4828e0 | 884 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
885 | emit_move_insn (mem, gen_rtx_REG (SImode, 0)); |
886 | ||
887 | mem = gen_rtx_MEM (SImode, | |
888 | plus_constant (current_function_internal_arg_pointer, 4)); | |
ba4828e0 | 889 | set_mem_alias_set (mem, set); |
fc2acc87 RH |
890 | emit_move_insn (mem, gen_rtx_REG (SImode, 1)); |
891 | ||
22ef4e9b JL |
892 | return copy_to_reg (expand_binop (Pmode, add_optab, |
893 | current_function_internal_arg_pointer, | |
894 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
895 | } | |
896 | ||
fc2acc87 | 897 | void |
e5faf155 | 898 | mn10300_va_start (valist, nextarg) |
fc2acc87 RH |
899 | tree valist; |
900 | rtx nextarg; | |
901 | { | |
6c535c69 | 902 | nextarg = expand_builtin_saveregs (); |
e5faf155 | 903 | std_expand_builtin_va_start (valist, nextarg); |
fc2acc87 RH |
904 | } |
905 | ||
906 | rtx | |
907 | mn10300_va_arg (valist, type) | |
908 | tree valist, type; | |
909 | { | |
910 | HOST_WIDE_INT align, rsize; | |
911 | tree t, ptr, pptr; | |
912 | ||
913 | /* Compute the rounded size of the type. */ | |
914 | align = PARM_BOUNDARY / BITS_PER_UNIT; | |
915 | rsize = (((int_size_in_bytes (type) + align - 1) / align) * align); | |
916 | ||
917 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
918 | build_int_2 ((rsize > 8 ? 4 : rsize), 0)); | |
919 | TREE_SIDE_EFFECTS (t) = 1; | |
920 | ||
921 | ptr = build_pointer_type (type); | |
922 | ||
923 | /* "Large" types are passed by reference. */ | |
924 | if (rsize > 8) | |
925 | { | |
926 | pptr = build_pointer_type (ptr); | |
927 | t = build1 (NOP_EXPR, pptr, t); | |
928 | TREE_SIDE_EFFECTS (t) = 1; | |
929 | ||
930 | t = build1 (INDIRECT_REF, ptr, t); | |
931 | TREE_SIDE_EFFECTS (t) = 1; | |
932 | } | |
933 | else | |
934 | { | |
935 | t = build1 (NOP_EXPR, ptr, t); | |
936 | TREE_SIDE_EFFECTS (t) = 1; | |
937 | } | |
938 | ||
939 | /* Calculate! */ | |
940 | return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL); | |
941 | } | |
942 | ||
22ef4e9b JL |
943 | /* Return an RTX to represent where a value with mode MODE will be returned |
944 | from a function. If the result is 0, the argument is pushed. */ | |
945 | ||
946 | rtx | |
947 | function_arg (cum, mode, type, named) | |
948 | CUMULATIVE_ARGS *cum; | |
949 | enum machine_mode mode; | |
950 | tree type; | |
69bc71fa | 951 | int named ATTRIBUTE_UNUSED; |
22ef4e9b JL |
952 | { |
953 | rtx result = 0; | |
954 | int size, align; | |
955 | ||
956 | /* We only support using 2 data registers as argument registers. */ | |
957 | int nregs = 2; | |
958 | ||
959 | /* Figure out the size of the object to be passed. */ | |
960 | if (mode == BLKmode) | |
961 | size = int_size_in_bytes (type); | |
962 | else | |
963 | size = GET_MODE_SIZE (mode); | |
964 | ||
965 | /* Figure out the alignment of the object to be passed. */ | |
966 | align = size; | |
967 | ||
968 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
969 | ||
970 | /* Don't pass this arg via a register if all the argument registers | |
971 | are used up. */ | |
972 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
973 | return 0; | |
974 | ||
975 | /* Don't pass this arg via a register if it would be split between | |
976 | registers and memory. */ | |
977 | if (type == NULL_TREE | |
978 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
979 | return 0; | |
980 | ||
981 | switch (cum->nbytes / UNITS_PER_WORD) | |
982 | { | |
983 | case 0: | |
c5c76735 | 984 | result = gen_rtx_REG (mode, 0); |
22ef4e9b JL |
985 | break; |
986 | case 1: | |
c5c76735 | 987 | result = gen_rtx_REG (mode, 1); |
22ef4e9b JL |
988 | break; |
989 | default: | |
990 | result = 0; | |
991 | } | |
992 | ||
993 | return result; | |
994 | } | |
995 | ||
996 | /* Return the number of registers to use for an argument passed partially | |
997 | in registers and partially in memory. */ | |
998 | ||
999 | int | |
1000 | function_arg_partial_nregs (cum, mode, type, named) | |
1001 | CUMULATIVE_ARGS *cum; | |
1002 | enum machine_mode mode; | |
1003 | tree type; | |
69bc71fa | 1004 | int named ATTRIBUTE_UNUSED; |
22ef4e9b JL |
1005 | { |
1006 | int size, align; | |
1007 | ||
1008 | /* We only support using 2 data registers as argument registers. */ | |
1009 | int nregs = 2; | |
1010 | ||
1011 | /* Figure out the size of the object to be passed. */ | |
1012 | if (mode == BLKmode) | |
1013 | size = int_size_in_bytes (type); | |
1014 | else | |
1015 | size = GET_MODE_SIZE (mode); | |
1016 | ||
1017 | /* Figure out the alignment of the object to be passed. */ | |
1018 | align = size; | |
1019 | ||
1020 | cum->nbytes = (cum->nbytes + 3) & ~3; | |
1021 | ||
1022 | /* Don't pass this arg via a register if all the argument registers | |
1023 | are used up. */ | |
1024 | if (cum->nbytes > nregs * UNITS_PER_WORD) | |
1025 | return 0; | |
1026 | ||
1027 | if (cum->nbytes + size <= nregs * UNITS_PER_WORD) | |
1028 | return 0; | |
1029 | ||
1030 | /* Don't pass this arg via a register if it would be split between | |
1031 | registers and memory. */ | |
1032 | if (type == NULL_TREE | |
1033 | && cum->nbytes + size > nregs * UNITS_PER_WORD) | |
1034 | return 0; | |
1035 | ||
1036 | return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD; | |
1037 | } | |
1038 | ||
1039 | /* Output a tst insn. */ | |
1943c2c1 | 1040 | const char * |
22ef4e9b JL |
1041 | output_tst (operand, insn) |
1042 | rtx operand, insn; | |
1043 | { | |
22ef4e9b JL |
1044 | rtx temp; |
1045 | int past_call = 0; | |
1046 | ||
1047 | /* We can save a byte if we can find a register which has the value | |
1048 | zero in it. */ | |
1049 | temp = PREV_INSN (insn); | |
74452ac3 | 1050 | while (optimize && temp) |
22ef4e9b JL |
1051 | { |
1052 | rtx set; | |
1053 | ||
1054 | /* We allow the search to go through call insns. We record | |
1055 | the fact that we've past a CALL_INSN and reject matches which | |
1056 | use call clobbered registers. */ | |
1057 | if (GET_CODE (temp) == CODE_LABEL | |
1058 | || GET_CODE (temp) == JUMP_INSN | |
1059 | || GET_CODE (temp) == BARRIER) | |
1060 | break; | |
1061 | ||
1062 | if (GET_CODE (temp) == CALL_INSN) | |
1063 | past_call = 1; | |
1064 | ||
1065 | if (GET_CODE (temp) == NOTE) | |
1066 | { | |
1067 | temp = PREV_INSN (temp); | |
1068 | continue; | |
1069 | } | |
1070 | ||
1071 | /* It must be an insn, see if it is a simple set. */ | |
1072 | set = single_set (temp); | |
1073 | if (!set) | |
1074 | { | |
1075 | temp = PREV_INSN (temp); | |
1076 | continue; | |
1077 | } | |
1078 | ||
1079 | /* Are we setting a data register to zero (this does not win for | |
1080 | address registers)? | |
1081 | ||
1082 | If it's a call clobbered register, have we past a call? | |
1083 | ||
1084 | Make sure the register we find isn't the same as ourself; | |
4d1a91c2 JL |
1085 | the mn10300 can't encode that. |
1086 | ||
1087 | ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN | |
1088 | so the code to detect calls here isn't doing anything useful. */ | |
22ef4e9b JL |
1089 | if (REG_P (SET_DEST (set)) |
1090 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1091 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
74452ac3 JL |
1092 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) |
1093 | == REGNO_REG_CLASS (REGNO (operand))) | |
705ac34f JL |
1094 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS |
1095 | && REGNO (SET_DEST (set)) != REGNO (operand) | |
1096 | && (!past_call | |
1097 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1098 | { | |
1099 | rtx xoperands[2]; | |
1100 | xoperands[0] = operand; | |
1101 | xoperands[1] = SET_DEST (set); | |
1102 | ||
1103 | output_asm_insn ("cmp %1,%0", xoperands); | |
1104 | return ""; | |
1105 | } | |
1106 | ||
1107 | if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS | |
1108 | && REG_P (SET_DEST (set)) | |
1109 | && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set))) | |
1110 | && !reg_set_between_p (SET_DEST (set), temp, insn) | |
1111 | && (REGNO_REG_CLASS (REGNO (SET_DEST (set))) | |
1112 | != REGNO_REG_CLASS (REGNO (operand))) | |
1113 | && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS | |
22ef4e9b JL |
1114 | && REGNO (SET_DEST (set)) != REGNO (operand) |
1115 | && (!past_call | |
1116 | || !call_used_regs[REGNO (SET_DEST (set))])) | |
1117 | { | |
1118 | rtx xoperands[2]; | |
1119 | xoperands[0] = operand; | |
1120 | xoperands[1] = SET_DEST (set); | |
1121 | ||
1122 | output_asm_insn ("cmp %1,%0", xoperands); | |
1123 | return ""; | |
1124 | } | |
1125 | temp = PREV_INSN (temp); | |
1126 | } | |
1127 | return "cmp 0,%0"; | |
1128 | } | |
460f4b9d JL |
1129 | |
1130 | int | |
1131 | impossible_plus_operand (op, mode) | |
1132 | rtx op; | |
69bc71fa | 1133 | enum machine_mode mode ATTRIBUTE_UNUSED; |
460f4b9d | 1134 | { |
460f4b9d JL |
1135 | if (GET_CODE (op) != PLUS) |
1136 | return 0; | |
1137 | ||
4c742813 JL |
1138 | if (XEXP (op, 0) == stack_pointer_rtx |
1139 | || XEXP (op, 1) == stack_pointer_rtx) | |
460f4b9d JL |
1140 | return 1; |
1141 | ||
460f4b9d JL |
1142 | return 0; |
1143 | } | |
e9ad4573 | 1144 | |
f8912297 JL |
1145 | /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used |
1146 | for the btst insn which may examine memory or a register (the memory | |
1147 | variant only allows an unsigned 8 bit integer). */ | |
1148 | int | |
1149 | const_8bit_operand (op, mode) | |
1150 | register rtx op; | |
69bc71fa | 1151 | enum machine_mode mode ATTRIBUTE_UNUSED; |
f8912297 JL |
1152 | { |
1153 | return (GET_CODE (op) == CONST_INT | |
1154 | && INTVAL (op) >= 0 | |
1155 | && INTVAL (op) < 256); | |
1156 | } | |
1157 | ||
1158 | /* Similarly, but when using a zero_extract pattern for a btst where | |
1159 | the source operand might end up in memory. */ | |
1160 | int | |
1161 | mask_ok_for_mem_btst (len, bit) | |
1162 | int len; | |
1163 | int bit; | |
1164 | { | |
4977bab6 | 1165 | unsigned int mask = 0; |
f8912297 JL |
1166 | |
1167 | while (len > 0) | |
1168 | { | |
1169 | mask |= (1 << bit); | |
1170 | bit++; | |
1171 | len--; | |
1172 | } | |
1173 | ||
1174 | /* MASK must bit into an 8bit value. */ | |
1175 | return (((mask & 0xff) == mask) | |
1176 | || ((mask & 0xff00) == mask) | |
1177 | || ((mask & 0xff0000) == mask) | |
1178 | || ((mask & 0xff000000) == mask)); | |
1179 | } | |
1180 | ||
e9ad4573 JL |
1181 | /* Return 1 if X contains a symbolic expression. We know these |
1182 | expressions will have one of a few well defined forms, so | |
1183 | we need only check those forms. */ | |
1184 | int | |
1185 | symbolic_operand (op, mode) | |
1186 | register rtx op; | |
69bc71fa | 1187 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e9ad4573 JL |
1188 | { |
1189 | switch (GET_CODE (op)) | |
1190 | { | |
1191 | case SYMBOL_REF: | |
1192 | case LABEL_REF: | |
1193 | return 1; | |
1194 | case CONST: | |
1195 | op = XEXP (op, 0); | |
1196 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
1197 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
1198 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
1199 | default: | |
1200 | return 0; | |
1201 | } | |
1202 | } | |
1203 | ||
1204 | /* Try machine dependent ways of modifying an illegitimate address | |
1205 | to be legitimate. If we find one, return the new valid address. | |
1206 | This macro is used in only one place: `memory_address' in explow.c. | |
1207 | ||
1208 | OLDX is the address as it was before break_out_memory_refs was called. | |
1209 | In some cases it is useful to look at this to decide what needs to be done. | |
1210 | ||
1211 | MODE and WIN are passed so that this macro can use | |
1212 | GO_IF_LEGITIMATE_ADDRESS. | |
1213 | ||
1214 | Normally it is always safe for this macro to do nothing. It exists to | |
1215 | recognize opportunities to optimize the output. | |
1216 | ||
1217 | But on a few ports with segmented architectures and indexed addressing | |
1218 | (mn10300, hppa) it is used to rewrite certain problematical addresses. */ | |
1219 | rtx | |
1220 | legitimize_address (x, oldx, mode) | |
1221 | rtx x; | |
69bc71fa KG |
1222 | rtx oldx ATTRIBUTE_UNUSED; |
1223 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
e9ad4573 JL |
1224 | { |
1225 | /* Uh-oh. We might have an address for x[n-100000]. This needs | |
1226 | special handling to avoid creating an indexed memory address | |
1227 | with x-100000 as the base. */ | |
1228 | if (GET_CODE (x) == PLUS | |
1229 | && symbolic_operand (XEXP (x, 1), VOIDmode)) | |
1230 | { | |
1231 | /* Ugly. We modify things here so that the address offset specified | |
1232 | by the index expression is computed first, then added to x to form | |
1233 | the entire address. */ | |
1234 | ||
69bc71fa | 1235 | rtx regx1, regy1, regy2, y; |
e9ad4573 JL |
1236 | |
1237 | /* Strip off any CONST. */ | |
1238 | y = XEXP (x, 1); | |
1239 | if (GET_CODE (y) == CONST) | |
1240 | y = XEXP (y, 0); | |
1241 | ||
bf4219f0 JL |
1242 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1243 | { | |
1244 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1245 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1246 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1247 | regx1 = force_reg (Pmode, | |
1248 | gen_rtx (GET_CODE (y), Pmode, regx1, regy2)); | |
c5c76735 | 1249 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); |
bf4219f0 | 1250 | } |
e9ad4573 | 1251 | } |
371036e0 | 1252 | return x; |
e9ad4573 | 1253 | } |
460ad325 | 1254 | |
dcefdf67 RH |
1255 | static int |
1256 | mn10300_address_cost_1 (x, unsig) | |
460ad325 AO |
1257 | rtx x; |
1258 | int *unsig; | |
1259 | { | |
460ad325 AO |
1260 | switch (GET_CODE (x)) |
1261 | { | |
1262 | case REG: | |
1263 | switch (REGNO_REG_CLASS (REGNO (x))) | |
1264 | { | |
1265 | case SP_REGS: | |
1266 | *unsig = 1; | |
1267 | return 0; | |
1268 | ||
1269 | case ADDRESS_REGS: | |
1270 | return 1; | |
1271 | ||
1272 | case DATA_REGS: | |
1273 | case EXTENDED_REGS: | |
1274 | return 3; | |
1275 | ||
1276 | case NO_REGS: | |
1277 | return 5; | |
1278 | ||
1279 | default: | |
1280 | abort (); | |
1281 | } | |
1282 | ||
1283 | case PLUS: | |
1284 | case MINUS: | |
d82704fb AO |
1285 | case ASHIFT: |
1286 | case AND: | |
460ad325 | 1287 | case IOR: |
dcefdf67 RH |
1288 | return (mn10300_address_cost_1 (XEXP (x, 0), unsig) |
1289 | + mn10300_address_cost_1 (XEXP (x, 1), unsig)); | |
460ad325 AO |
1290 | |
1291 | case EXPR_LIST: | |
1292 | case SUBREG: | |
1293 | case MEM: | |
dcefdf67 | 1294 | return mn10300_address_cost (XEXP (x, 0)); |
460ad325 AO |
1295 | |
1296 | case ZERO_EXTEND: | |
1297 | *unsig = 1; | |
dcefdf67 | 1298 | return mn10300_address_cost_1 (XEXP (x, 0), unsig); |
460ad325 AO |
1299 | |
1300 | case CONST_INT: | |
1301 | if (INTVAL (x) == 0) | |
1302 | return 0; | |
1303 | if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100) | |
1304 | return 1; | |
1305 | if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000) | |
1306 | return 3; | |
1307 | if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000) | |
1308 | return 5; | |
1309 | return 7; | |
1310 | ||
1311 | case CONST: | |
1312 | case SYMBOL_REF: | |
d82704fb | 1313 | case LABEL_REF: |
460ad325 AO |
1314 | return 8; |
1315 | ||
1316 | case ADDRESSOF: | |
1317 | switch (GET_CODE (XEXP (x, 0))) | |
1318 | { | |
1319 | case MEM: | |
dcefdf67 | 1320 | return mn10300_address_cost (XEXP (x, 0)); |
460ad325 AO |
1321 | |
1322 | case REG: | |
1323 | return 1; | |
1324 | ||
1325 | default: | |
1326 | abort (); | |
1327 | } | |
1328 | ||
1329 | default: | |
1330 | abort (); | |
1331 | ||
1332 | } | |
1333 | } | |
3c50106f | 1334 | |
dcefdf67 RH |
1335 | static int |
1336 | mn10300_address_cost (x) | |
1337 | rtx x; | |
1338 | { | |
1339 | int s = 0; | |
1340 | return mn10300_address_cost_1 (x, &s); | |
1341 | } | |
1342 | ||
3c50106f RH |
1343 | static bool |
1344 | mn10300_rtx_costs (x, code, outer_code, total) | |
1345 | rtx x; | |
1346 | int code, outer_code; | |
1347 | int *total; | |
1348 | { | |
1349 | switch (code) | |
1350 | { | |
1351 | case CONST_INT: | |
1352 | /* Zeros are extremely cheap. */ | |
1353 | if (INTVAL (x) == 0 && outer_code == SET) | |
1354 | *total = 0; | |
1355 | /* If it fits in 8 bits, then it's still relatively cheap. */ | |
1356 | else if (INT_8_BITS (INTVAL (x))) | |
1357 | *total = 1; | |
1358 | /* This is the "base" cost, includes constants where either the | |
1359 | upper or lower 16bits are all zeros. */ | |
1360 | else if (INT_16_BITS (INTVAL (x)) | |
1361 | || (INTVAL (x) & 0xffff) == 0 | |
1362 | || (INTVAL (x) & 0xffff0000) == 0) | |
1363 | *total = 2; | |
1364 | else | |
1365 | *total = 4; | |
1366 | return true; | |
1367 | ||
1368 | case CONST: | |
1369 | case LABEL_REF: | |
1370 | case SYMBOL_REF: | |
1371 | /* These are more costly than a CONST_INT, but we can relax them, | |
1372 | so they're less costly than a CONST_DOUBLE. */ | |
1373 | *total = 6; | |
1374 | return true; | |
1375 | ||
1376 | case CONST_DOUBLE: | |
1377 | /* We don't optimize CONST_DOUBLEs well nor do we relax them well, | |
1378 | so their cost is very high. */ | |
1379 | *total = 8; | |
1380 | return true; | |
1381 | ||
1382 | /* ??? This probably needs more work. */ | |
1383 | case MOD: | |
1384 | case DIV: | |
1385 | case MULT: | |
1386 | *total = 8; | |
1387 | return true; | |
1388 | ||
1389 | default: | |
1390 | return false; | |
1391 | } | |
1392 | } |