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cf011243 AO |
1 | /* Definitions of target machine for GNU compiler. |
2 | Matsushita MN10300 series | |
2f83c7d6 | 3 | Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, |
cd8d8754 | 4 | 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. |
11bb1f11 JL |
5 | Contributed by Jeff Law (law@cygnus.com). |
6 | ||
e7ab5593 | 7 | This file is part of GCC. |
11bb1f11 | 8 | |
e7ab5593 NC |
9 | GCC is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
11bb1f11 | 13 | |
e7ab5593 NC |
14 | GCC is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
11bb1f11 | 18 | |
e7ab5593 NC |
19 | You should have received a copy of the GNU General Public License |
20 | along with GCC; see the file COPYING3. If not see | |
21 | <http://www.gnu.org/licenses/>. */ | |
11bb1f11 JL |
22 | |
23 | #undef ASM_SPEC | |
11bb1f11 JL |
24 | #undef LIB_SPEC |
25 | #undef ENDFILE_SPEC | |
e7ab5593 | 26 | #undef LINK_SPEC |
2ea10770 | 27 | #define LINK_SPEC "%{mrelax:--relax}" |
e7ab5593 | 28 | #undef STARTFILE_SPEC |
dff55dbc | 29 | #define STARTFILE_SPEC "%{!mno-crt0:%{!shared:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}" |
11bb1f11 JL |
30 | |
31 | /* Names to predefine in the preprocessor for this target machine. */ | |
32 | ||
cc956ba2 NB |
33 | #define TARGET_CPU_CPP_BUILTINS() \ |
34 | do \ | |
35 | { \ | |
36 | builtin_define ("__mn10300__"); \ | |
37 | builtin_define ("__MN10300__"); \ | |
816e93eb NC |
38 | builtin_assert ("cpu=mn10300"); \ |
39 | builtin_assert ("machine=mn10300"); \ | |
e7ab5593 | 40 | \ |
f3f63737 NC |
41 | if (TARGET_AM34) \ |
42 | { \ | |
43 | builtin_define ("__AM33__=4"); \ | |
44 | builtin_define ("__AM34__"); \ | |
45 | } \ | |
46 | else if (TARGET_AM33_2) \ | |
e7ab5593 NC |
47 | { \ |
48 | builtin_define ("__AM33__=2"); \ | |
49 | builtin_define ("__AM33_2__"); \ | |
50 | } \ | |
51 | else if (TARGET_AM33) \ | |
52 | builtin_define ("__AM33__=1"); \ | |
298362c8 NC |
53 | \ |
54 | builtin_define (TARGET_ALLOW_LIW ? \ | |
55 | "__LIW__" : "__NO_LIW__");\ | |
56 | \ | |
cc956ba2 NB |
57 | } \ |
58 | while (0) | |
11bb1f11 | 59 | |
cd8d8754 JM |
60 | #ifndef MN10300_OPTS_H |
61 | #include "config/mn10300/mn10300-opts.h" | |
62 | #endif | |
11bb1f11 | 63 | |
f3f63737 | 64 | extern enum processor_type mn10300_tune_cpu; |
d1776069 | 65 | |
13dd556c | 66 | #define TARGET_AM33 (mn10300_processor >= PROCESSOR_AM33) |
f3f63737 NC |
67 | #define TARGET_AM33_2 (mn10300_processor >= PROCESSOR_AM33_2) |
68 | #define TARGET_AM34 (mn10300_processor >= PROCESSOR_AM34) | |
13dd556c RS |
69 | |
70 | #ifndef PROCESSOR_DEFAULT | |
71 | #define PROCESSOR_DEFAULT PROCESSOR_MN10300 | |
11bb1f11 JL |
72 | #endif |
73 | ||
11bb1f11 JL |
74 | \f |
75 | /* Target machine storage layout */ | |
76 | ||
77 | /* Define this if most significant bit is lowest numbered | |
78 | in instructions that operate on numbered bit-fields. | |
79 | This is not true on the Matsushita MN1003. */ | |
80 | #define BITS_BIG_ENDIAN 0 | |
81 | ||
82 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
83 | /* This is not true on the Matsushita MN10300. */ | |
84 | #define BYTES_BIG_ENDIAN 0 | |
85 | ||
86 | /* Define this if most significant word of a multiword number is lowest | |
87 | numbered. | |
88 | This is not true on the Matsushita MN10300. */ | |
89 | #define WORDS_BIG_ENDIAN 0 | |
90 | ||
11bb1f11 JL |
91 | /* Width of a word, in units (bytes). */ |
92 | #define UNITS_PER_WORD 4 | |
93 | ||
11bb1f11 JL |
94 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
95 | #define PARM_BOUNDARY 32 | |
96 | ||
85f65093 | 97 | /* The stack goes in 32-bit lumps. */ |
11bb1f11 JL |
98 | #define STACK_BOUNDARY 32 |
99 | ||
100 | /* Allocation boundary (in *bits*) for the code of a function. | |
101 | 8 is the minimum boundary; it's unclear if bigger alignments | |
102 | would improve performance. */ | |
103 | #define FUNCTION_BOUNDARY 8 | |
104 | ||
8596d0a1 | 105 | /* No data type wants to be aligned rounder than this. */ |
11bb1f11 JL |
106 | #define BIGGEST_ALIGNMENT 32 |
107 | ||
108 | /* Alignment of field after `int : 0' in a structure. */ | |
e7ab5593 | 109 | #define EMPTY_FIELD_BOUNDARY 32 |
11bb1f11 JL |
110 | |
111 | /* Define this if move instructions will actually fail to work | |
112 | when given unaligned data. */ | |
113 | #define STRICT_ALIGNMENT 1 | |
114 | ||
115 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
116 | #define DEFAULT_SIGNED_CHAR 0 | |
6b9b8b34 JM |
117 | |
118 | #undef SIZE_TYPE | |
119 | #define SIZE_TYPE "unsigned int" | |
120 | ||
121 | #undef PTRDIFF_TYPE | |
122 | #define PTRDIFF_TYPE "int" | |
123 | ||
124 | #undef WCHAR_TYPE | |
125 | #define WCHAR_TYPE "long int" | |
126 | ||
127 | #undef WCHAR_TYPE_SIZE | |
128 | #define WCHAR_TYPE_SIZE BITS_PER_WORD | |
11bb1f11 JL |
129 | \f |
130 | /* Standard register usage. */ | |
131 | ||
132 | /* Number of actual hardware registers. | |
133 | The hardware registers are assigned numbers for the compiler | |
134 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
135 | ||
136 | All registers that the compiler knows about must be given numbers, | |
137 | even those that are not normally considered general registers. */ | |
138 | ||
4af476d7 NC |
139 | #define FIRST_PSEUDO_REGISTER 52 |
140 | ||
141 | /* Specify machine-specific register numbers. The commented out entries | |
142 | are defined in mn10300.md. */ | |
143 | #define FIRST_DATA_REGNUM 0 | |
144 | #define LAST_DATA_REGNUM 3 | |
145 | #define FIRST_ADDRESS_REGNUM 4 | |
146 | /* #define PIC_REG 6 */ | |
147 | #define LAST_ADDRESS_REGNUM 8 | |
148 | /* #define SP_REG 9 */ | |
a47944e2 | 149 | #define FIRST_EXTENDED_REGNUM 10 |
4af476d7 NC |
150 | #define LAST_EXTENDED_REGNUM 17 |
151 | #define FIRST_FP_REGNUM 18 | |
152 | #define LAST_FP_REGNUM 49 | |
c25a21f5 | 153 | /* #define MDR_REG 50 */ |
4af476d7 NC |
154 | /* #define CC_REG 51 */ |
155 | #define FIRST_ARGUMENT_REGNUM 0 | |
a47944e2 AO |
156 | |
157 | /* Specify the registers used for certain standard purposes. | |
158 | The values of these macros are register numbers. */ | |
159 | ||
160 | /* Register to use for pushing function arguments. */ | |
4af476d7 | 161 | #define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1) |
a47944e2 AO |
162 | |
163 | /* Base register for access to local variables of the function. */ | |
4af476d7 | 164 | #define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM - 1) |
a47944e2 AO |
165 | |
166 | /* Base register for access to arguments of the function. This | |
167 | is a fake register and will be eliminated into either the frame | |
168 | pointer or stack pointer. */ | |
169 | #define ARG_POINTER_REGNUM LAST_ADDRESS_REGNUM | |
170 | ||
171 | /* Register in which static-chain is passed to a function. */ | |
4af476d7 | 172 | #define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1) |
a47944e2 | 173 | |
11bb1f11 JL |
174 | /* 1 for registers that have pervasive standard uses |
175 | and are not available for the register allocator. */ | |
176 | ||
177 | #define FIXED_REGISTERS \ | |
c25a21f5 RH |
178 | { 0, 0, 0, 0, /* data regs */ \ |
179 | 0, 0, 0, 0, /* addr regs */ \ | |
180 | 1, /* arg reg */ \ | |
181 | 1, /* sp reg */ \ | |
182 | 0, 0, 0, 0, 0, 0, 0, 0, /* extended regs */ \ | |
183 | 0, 0, /* fp regs (18-19) */ \ | |
184 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \ | |
185 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (30-39) */ \ | |
186 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (40-49) */ \ | |
187 | 0, /* mdr reg */ \ | |
188 | 1 /* cc reg */ \ | |
18e9d2f9 | 189 | } |
11bb1f11 JL |
190 | |
191 | /* 1 for registers not available across function calls. | |
192 | These must include the FIXED_REGISTERS and also any | |
193 | registers that can be used without being saved. | |
194 | The latter must include the registers where values are returned | |
195 | and the register where structure-value addresses are passed. | |
196 | Aside from that, you can include as many other registers as you | |
197 | like. */ | |
198 | ||
199 | #define CALL_USED_REGISTERS \ | |
c25a21f5 RH |
200 | { 1, 1, 0, 0, /* data regs */ \ |
201 | 1, 1, 0, 0, /* addr regs */ \ | |
202 | 1, /* arg reg */ \ | |
203 | 1, /* sp reg */ \ | |
204 | 1, 1, 1, 1, 0, 0, 0, 0, /* extended regs */ \ | |
205 | 1, 1, /* fp regs (18-19) */ \ | |
206 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \ | |
207 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, /* fp regs (30-39) */ \ | |
208 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* fp regs (40-49) */ \ | |
209 | 1, /* mdr reg */ \ | |
210 | 1 /* cc reg */ \ | |
18e9d2f9 | 211 | } |
11bb1f11 | 212 | |
9d54866d NC |
213 | /* Note: The definition of CALL_REALLY_USED_REGISTERS is not |
214 | redundant. It is needed when compiling in PIC mode because | |
215 | the a2 register becomes fixed (and hence must be marked as | |
216 | call_used) but in order to preserve the ABI it is not marked | |
217 | as call_really_used. */ | |
218 | #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS | |
219 | ||
11bb1f11 | 220 | #define REG_ALLOC_ORDER \ |
18e9d2f9 AO |
221 | { 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9 \ |
222 | , 42, 43, 44, 45, 46, 47, 48, 49, 34, 35, 36, 37, 38, 39, 40, 41 \ | |
c25a21f5 | 223 | , 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 50, 51 \ |
18e9d2f9 | 224 | } |
705ac34f | 225 | |
11bb1f11 JL |
226 | /* Return number of consecutive hard regs needed starting at reg REGNO |
227 | to hold something of mode MODE. | |
228 | ||
229 | This is ordinarily the length in words of a value of mode MODE | |
230 | but can be less for certain modes in special long registers. */ | |
231 | ||
232 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
233 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
234 | ||
235 | /* Value is 1 if hard register REGNO can hold a value of machine-mode | |
236 | MODE. */ | |
11bb1f11 | 237 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
4af476d7 | 238 | mn10300_hard_regno_mode_ok ((REGNO), (MODE)) |
11bb1f11 JL |
239 | |
240 | /* Value is 1 if it is a good idea to tie two pseudo registers | |
241 | when one has mode MODE1 and one has mode MODE2. | |
242 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
243 | for any hard reg, then this must be 0 for correct output. */ | |
244 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
4af476d7 | 245 | mn10300_modes_tieable ((MODE1), (MODE2)) |
11bb1f11 | 246 | |
4246e0c5 JL |
247 | /* 4 data, and effectively 3 address registers is small as far as I'm |
248 | concerned. */ | |
42db504c | 249 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true |
11bb1f11 JL |
250 | \f |
251 | /* Define the classes of registers for register constraints in the | |
252 | machine description. Also define ranges of constants. | |
253 | ||
254 | One of the classes must always be named ALL_REGS and include all hard regs. | |
255 | If there is more than one class, another class must be named NO_REGS | |
256 | and contain no registers. | |
257 | ||
258 | The name GENERAL_REGS must be the name of a class (or an alias for | |
259 | another name such as ALL_REGS). This is the class of registers | |
260 | that is allowed by "g" or "r" in a register constraint. | |
261 | Also, registers outside this class are allocated only when | |
262 | instructions express preferences for them. | |
263 | ||
264 | The classes must be numbered in nondecreasing order; that is, | |
265 | a larger-numbered class must never be contained completely | |
266 | in a smaller-numbered class. | |
267 | ||
268 | For any two classes, it is very desirable that there be another | |
269 | class that represents their union. */ | |
5abc5de9 | 270 | |
e7ab5593 NC |
271 | enum reg_class |
272 | { | |
36846b26 | 273 | NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, SP_OR_ADDRESS_REGS, |
c25a21f5 | 274 | EXTENDED_REGS, FP_REGS, FP_ACC_REGS, CC_REGS, MDR_REGS, |
36846b26 | 275 | GENERAL_REGS, SP_OR_GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES |
11bb1f11 JL |
276 | }; |
277 | ||
278 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
279 | ||
8596d0a1 | 280 | /* Give names of register classes as strings for dump file. */ |
11bb1f11 | 281 | |
c25a21f5 | 282 | #define REG_CLASS_NAMES \ |
36846b26 | 283 | { "NO_REGS", "DATA_REGS", "ADDRESS_REGS", "SP_REGS", "SP_OR_ADDRESS_REGS", \ |
c25a21f5 RH |
284 | "EXTENDED_REGS", "FP_REGS", "FP_ACC_REGS", "CC_REGS", "MDR_REGS", \ |
285 | "GENERAL_REGS", "SP_OR_GENERAL_REGS", "ALL_REGS", "LIM_REGS" \ | |
e7ab5593 | 286 | } |
11bb1f11 JL |
287 | |
288 | /* Define which registers fit in which classes. | |
289 | This is an initializer for a vector of HARD_REG_SET | |
290 | of length N_REG_CLASSES. */ | |
291 | ||
4af476d7 | 292 | #define REG_CLASS_CONTENTS \ |
f3f63737 | 293 | { { 0, 0 }, /* No regs */ \ |
4af476d7 NC |
294 | { 0x0000000f, 0 }, /* DATA_REGS */ \ |
295 | { 0x000001f0, 0 }, /* ADDRESS_REGS */ \ | |
296 | { 0x00000200, 0 }, /* SP_REGS */ \ | |
4af476d7 NC |
297 | { 0x000003f0, 0 }, /* SP_OR_ADDRESS_REGS */ \ |
298 | { 0x0003fc00, 0 }, /* EXTENDED_REGS */ \ | |
4af476d7 NC |
299 | { 0xfffc0000, 0x3ffff },/* FP_REGS */ \ |
300 | { 0x03fc0000, 0 }, /* FP_ACC_REGS */ \ | |
301 | { 0x00000000, 0x80000 },/* CC_REGS */ \ | |
c25a21f5 | 302 | { 0x00000000, 0x40000 },/* MDR_REGS */ \ |
4af476d7 | 303 | { 0x0003fdff, 0 }, /* GENERAL_REGS */ \ |
36846b26 | 304 | { 0x0003ffff, 0 }, /* SP_OR_GENERAL_REGS */ \ |
f3f63737 | 305 | { 0xffffffff, 0xfffff } /* ALL_REGS */ \ |
11bb1f11 JL |
306 | } |
307 | ||
308 | /* The same information, inverted: | |
309 | Return the class number of the smallest class containing | |
310 | reg number REGNO. This could be a conditional expression | |
311 | or could index an array. */ | |
312 | ||
e7ab5593 NC |
313 | #define REGNO_REG_CLASS(REGNO) \ |
314 | ((REGNO) <= LAST_DATA_REGNUM ? DATA_REGS : \ | |
315 | (REGNO) <= LAST_ADDRESS_REGNUM ? ADDRESS_REGS : \ | |
316 | (REGNO) == STACK_POINTER_REGNUM ? SP_REGS : \ | |
a47944e2 | 317 | (REGNO) <= LAST_EXTENDED_REGNUM ? EXTENDED_REGS : \ |
e7ab5593 | 318 | (REGNO) <= LAST_FP_REGNUM ? FP_REGS : \ |
c25a21f5 | 319 | (REGNO) == MDR_REG ? MDR_REGS : \ |
e7ab5593 | 320 | (REGNO) == CC_REG ? CC_REGS : \ |
7f13af23 | 321 | NO_REGS) |
11bb1f11 JL |
322 | |
323 | /* The class value for index registers, and the one for base regs. */ | |
36846b26 RH |
324 | #define INDEX_REG_CLASS \ |
325 | (TARGET_AM33 ? GENERAL_REGS : DATA_REGS) | |
326 | #define BASE_REG_CLASS \ | |
327 | (TARGET_AM33 ? SP_OR_GENERAL_REGS : SP_OR_ADDRESS_REGS) | |
11bb1f11 | 328 | |
11bb1f11 JL |
329 | /* Macros to check register numbers against specific register classes. */ |
330 | ||
a204fec0 AO |
331 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
332 | and check its validity for a certain class. | |
333 | We have two alternate definitions for each of them. | |
334 | The usual definition accepts all pseudo regs; the other rejects | |
335 | them unless they have been allocated suitable hard regs. | |
336 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
337 | ||
338 | Most source files want to accept pseudo regs in the hope that | |
339 | they will get allocated to the class that the insn wants them to be in. | |
340 | Source files for reload pass need to be strict. | |
341 | After reload, it makes no difference, since pseudo regs have | |
342 | been eliminated by then. */ | |
343 | ||
11bb1f11 JL |
344 | /* These assume that REGNO is a hard or pseudo reg number. |
345 | They give nonzero only if REGNO is a hard reg of the suitable class | |
346 | or a pseudo reg currently allocated to a suitable hard reg. | |
347 | Since they use reg_renumber, they are safe only once reg_renumber | |
348 | has been allocated, which happens in local-alloc.c. */ | |
a204fec0 AO |
349 | |
350 | #ifndef REG_OK_STRICT | |
e733134f | 351 | # define REG_STRICT 0 |
a204fec0 | 352 | #else |
e733134f | 353 | # define REG_STRICT 1 |
a204fec0 AO |
354 | #endif |
355 | ||
e733134f | 356 | #define REGNO_DATA_P(regno, strict) \ |
36846b26 | 357 | mn10300_regno_in_class_p (regno, DATA_REGS, strict) |
e733134f | 358 | #define REGNO_ADDRESS_P(regno, strict) \ |
36846b26 | 359 | mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict) |
e733134f | 360 | #define REGNO_EXTENDED_P(regno, strict) \ |
36846b26 RH |
361 | mn10300_regno_in_class_p (regno, EXTENDED_REGS, strict) |
362 | #define REGNO_GENERAL_P(regno, strict) \ | |
363 | mn10300_regno_in_class_p (regno, GENERAL_REGS, strict) | |
e733134f AO |
364 | |
365 | #define REGNO_STRICT_OK_FOR_BASE_P(regno, strict) \ | |
36846b26 | 366 | mn10300_regno_in_class_p (regno, BASE_REG_CLASS, strict) |
11bb1f11 | 367 | #define REGNO_OK_FOR_BASE_P(regno) \ |
e733134f AO |
368 | (REGNO_STRICT_OK_FOR_BASE_P ((regno), REG_STRICT)) |
369 | #define REG_OK_FOR_BASE_P(X) \ | |
370 | (REGNO_OK_FOR_BASE_P (REGNO (X))) | |
11bb1f11 | 371 | |
e733134f | 372 | #define REGNO_STRICT_OK_FOR_BIT_BASE_P(regno, strict) \ |
36846b26 | 373 | mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict) |
4d1a91c2 | 374 | #define REGNO_OK_FOR_BIT_BASE_P(regno) \ |
e733134f AO |
375 | (REGNO_STRICT_OK_FOR_BIT_BASE_P ((regno), REG_STRICT)) |
376 | #define REG_OK_FOR_BIT_BASE_P(X) \ | |
377 | (REGNO_OK_FOR_BIT_BASE_P (REGNO (X))) | |
4d1a91c2 | 378 | |
e733134f | 379 | #define REGNO_STRICT_OK_FOR_INDEX_P(regno, strict) \ |
36846b26 | 380 | mn10300_regno_in_class_p (regno, INDEX_REG_CLASS, strict) |
11bb1f11 | 381 | #define REGNO_OK_FOR_INDEX_P(regno) \ |
e733134f AO |
382 | (REGNO_STRICT_OK_FOR_INDEX_P ((regno), REG_STRICT)) |
383 | #define REG_OK_FOR_INDEX_P(X) \ | |
384 | (REGNO_OK_FOR_INDEX_P (REGNO (X))) | |
11bb1f11 | 385 | |
11bb1f11 | 386 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ |
705ac34f | 387 | (!TARGET_AM33 && (MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS) |
11bb1f11 | 388 | |
11bb1f11 JL |
389 | /* Return the maximum number of consecutive registers |
390 | needed to represent mode MODE in a register of class CLASS. */ | |
391 | ||
392 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
393 | ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
394 | ||
18e9d2f9 AO |
395 | /* A class that contains registers which the compiler must always |
396 | access in a mode that is the same size as the mode in which it | |
397 | loaded the register. */ | |
398 | #define CLASS_CANNOT_CHANGE_SIZE FP_REGS | |
399 | ||
5abc5de9 | 400 | /* Return 1 if VALUE is in the range specified. */ |
11bb1f11 JL |
401 | |
402 | #define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100) | |
403 | #define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000) | |
404 | ||
11bb1f11 JL |
405 | \f |
406 | /* Stack layout; function entry, exit and calling. */ | |
407 | ||
408 | /* Define this if pushing a word on the stack | |
409 | makes the stack pointer a smaller address. */ | |
410 | ||
411 | #define STACK_GROWS_DOWNWARD | |
412 | ||
a4d05547 | 413 | /* Define this to nonzero if the nominal address of the stack frame |
11bb1f11 JL |
414 | is at the high-address end of the local variables; |
415 | that is, each additional local variable allocated | |
416 | goes at a more negative offset in the frame. */ | |
417 | ||
f62c8a5c | 418 | #define FRAME_GROWS_DOWNWARD 1 |
11bb1f11 JL |
419 | |
420 | /* Offset within stack frame to start allocating local variables at. | |
421 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
422 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
423 | of the first local allocated. */ | |
424 | ||
6e86170d | 425 | #define STARTING_FRAME_OFFSET 0 |
11bb1f11 JL |
426 | |
427 | /* Offset of first parameter from the argument pointer register value. */ | |
428 | /* Is equal to the size of the saved fp + pc, even if an fp isn't | |
429 | saved since the value is used before we know. */ | |
430 | ||
22ef4e9b | 431 | #define FIRST_PARM_OFFSET(FNDECL) 4 |
11bb1f11 | 432 | |
c157b3f0 RH |
433 | /* But the CFA is at the arg pointer directly, not at the first argument. */ |
434 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
435 | ||
777fbf09 JL |
436 | #define ELIMINABLE_REGS \ |
437 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
438 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
439 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} | |
440 | ||
777fbf09 | 441 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
e7ab5593 | 442 | OFFSET = mn10300_initial_offset (FROM, TO) |
11bb1f11 | 443 | |
22ef4e9b JL |
444 | /* We use d0/d1 for passing parameters, so allocate 8 bytes of space |
445 | for a register flushback area. */ | |
446 | #define REG_PARM_STACK_SPACE(DECL) 8 | |
81464b2c | 447 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
f73ad30e | 448 | #define ACCUMULATE_OUTGOING_ARGS 1 |
e7ab5593 | 449 | |
3dbc43d1 JL |
450 | /* So we can allocate space for return pointers once for the function |
451 | instead of around every call. */ | |
452 | #define STACK_POINTER_OFFSET 4 | |
6e86170d | 453 | |
11bb1f11 | 454 | /* 1 if N is a possible register number for function argument passing. |
990dc016 | 455 | On the MN10300, d0 and d1 are used in this way. */ |
11bb1f11 | 456 | |
653958e8 | 457 | #define FUNCTION_ARG_REGNO_P(N) ((N) <= 1) |
22ef4e9b | 458 | |
11bb1f11 JL |
459 | \f |
460 | /* Define a data type for recording info about an argument list | |
461 | during the scan of that argument list. This data type should | |
462 | hold all necessary information about the function itself | |
463 | and about the args processed so far, enough to enable macros | |
464 | such as FUNCTION_ARG to determine where the next arg should go. | |
465 | ||
466 | On the MN10300, this is a single integer, which is a number of bytes | |
467 | of arguments scanned so far. */ | |
468 | ||
22ef4e9b | 469 | #define CUMULATIVE_ARGS struct cum_arg |
e7ab5593 NC |
470 | |
471 | struct cum_arg | |
472 | { | |
473 | int nbytes; | |
474 | }; | |
11bb1f11 JL |
475 | |
476 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
477 | for a call to a function whose data type is FNTYPE. | |
478 | For a library call, FNTYPE is 0. | |
479 | ||
480 | On the MN10300, the offset starts at 0. */ | |
481 | ||
0f6937fe | 482 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
22ef4e9b | 483 | ((CUM).nbytes = 0) |
11bb1f11 | 484 | |
34732b0a | 485 | #define FUNCTION_VALUE_REGNO_P(N) mn10300_function_value_regno_p (N) |
11bb1f11 | 486 | |
11bb1f11 | 487 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
11bb1f11 JL |
488 | |
489 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
490 | the stack pointer does not matter. The value is tested only in | |
491 | functions that have frame pointers. | |
492 | No definition is equivalent to always zero. */ | |
493 | ||
494 | #define EXIT_IGNORE_STACK 1 | |
495 | ||
496 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
497 | for profiling a function entry. */ | |
498 | ||
499 | #define FUNCTION_PROFILER(FILE, LABELNO) ; | |
500 | ||
11bb1f11 JL |
501 | /* Length in units of the trampoline for entering a nested function. */ |
502 | ||
d6a3e264 RH |
503 | #define TRAMPOLINE_SIZE 16 |
504 | #define TRAMPOLINE_ALIGNMENT 32 | |
11bb1f11 | 505 | |
74452ac3 JL |
506 | /* A C expression whose value is RTL representing the value of the return |
507 | address for the frame COUNT steps up from the current frame. | |
508 | ||
509 | On the mn10300, the return address is not at a constant location | |
510 | due to the frame layout. Luckily, it is at a constant offset from | |
511 | the argument pointer, so we define RETURN_ADDR_RTX to return a | |
512 | MEM using arg_pointer_rtx. Reload will replace arg_pointer_rtx | |
513 | with a reference to the stack/frame pointer + an appropriate offset. */ | |
514 | ||
515 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
516 | ((COUNT == 0) \ | |
c5c76735 | 517 | ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ |
74452ac3 | 518 | : (rtx) 0) |
2720cc47 | 519 | |
885fe07c RH |
520 | /* The return address is saved both in the stack and in MDR. Using |
521 | the stack location is handiest for what unwinding needs. */ | |
522 | #define INCOMING_RETURN_ADDR_RTX \ | |
523 | gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) | |
11bb1f11 | 524 | \f |
11bb1f11 JL |
525 | /* Maximum number of registers that can appear in a valid memory address. */ |
526 | ||
527 | #define MAX_REGS_PER_ADDRESS 2 | |
528 | ||
11bb1f11 | 529 | \f |
36846b26 RH |
530 | /* We have post-increments. */ |
531 | #define HAVE_POST_INCREMENT TARGET_AM33 | |
532 | #define HAVE_POST_MODIFY_DISP TARGET_AM33 | |
533 | ||
534 | /* ... But we don't want to use them for block moves. Small offsets are | |
535 | just as effective, at least for inline block move sizes, and appears | |
536 | to produce cleaner code. */ | |
537 | #define USE_LOAD_POST_INCREMENT(M) 0 | |
538 | #define USE_STORE_POST_INCREMENT(M) 0 | |
705ac34f | 539 | |
11bb1f11 | 540 | /* Accept either REG or SUBREG where a register is valid. */ |
5abc5de9 | 541 | |
e733134f AO |
542 | #define RTX_OK_FOR_BASE_P(X, strict) \ |
543 | ((REG_P (X) && REGNO_STRICT_OK_FOR_BASE_P (REGNO (X), \ | |
544 | (strict))) \ | |
11bb1f11 | 545 | || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \ |
e733134f AO |
546 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (SUBREG_REG (X)), \ |
547 | (strict)))) | |
11bb1f11 | 548 | |
36846b26 RH |
549 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \ |
550 | do { \ | |
551 | rtx new_x = mn10300_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \ | |
552 | if (new_x) \ | |
553 | { \ | |
554 | X = new_x; \ | |
555 | goto WIN; \ | |
556 | } \ | |
557 | } while (0) | |
11bb1f11 | 558 | \f |
11bb1f11 | 559 | |
d1776069 AO |
560 | /* Zero if this needs fixing up to become PIC. */ |
561 | ||
e7ab5593 NC |
562 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
563 | mn10300_legitimate_pic_operand_p (X) | |
d1776069 AO |
564 | |
565 | /* Register to hold the addressing base for | |
566 | position independent code access to data items. */ | |
567 | #define PIC_OFFSET_TABLE_REGNUM PIC_REG | |
568 | ||
569 | /* The name of the pseudo-symbol representing the Global Offset Table. */ | |
570 | #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" | |
571 | ||
572 | #define SYMBOLIC_CONST_P(X) \ | |
573 | ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ | |
574 | && ! LEGITIMATE_PIC_OPERAND_P (X)) | |
575 | ||
576 | /* Non-global SYMBOL_REFs have SYMBOL_REF_FLAG enabled. */ | |
577 | #define MN10300_GLOBAL_P(X) (! SYMBOL_REF_FLAG (X)) | |
11bb1f11 | 578 | \f |
bad41521 | 579 | #define SELECT_CC_MODE(OP, X, Y) mn10300_select_cc_mode (OP, X, Y) |
4af476d7 NC |
580 | #define REVERSIBLE_CC_MODE(MODE) 0 |
581 | \f | |
11bb1f11 JL |
582 | /* Nonzero if access to memory by bytes or half words is no faster |
583 | than accessing full words. */ | |
584 | #define SLOW_BYTE_ACCESS 1 | |
585 | ||
22ef4e9b JL |
586 | #define NO_FUNCTION_CSE |
587 | ||
11bb1f11 JL |
588 | /* According expr.c, a value of around 6 should minimize code size, and |
589 | for the MN10300 series, that's our primary concern. */ | |
e04ad03d | 590 | #define MOVE_RATIO(speed) 6 |
11bb1f11 JL |
591 | |
592 | #define TEXT_SECTION_ASM_OP "\t.section .text" | |
593 | #define DATA_SECTION_ASM_OP "\t.section .data" | |
e7ab5593 | 594 | #define BSS_SECTION_ASM_OP "\t.section .bss" |
11bb1f11 | 595 | |
11bb1f11 JL |
596 | #define ASM_COMMENT_START "#" |
597 | ||
598 | /* Output to assembler file text saying following lines | |
599 | may contain character constants, extra white space, comments, etc. */ | |
600 | ||
601 | #define ASM_APP_ON "#APP\n" | |
602 | ||
603 | /* Output to assembler file text saying following lines | |
604 | no longer contain unusual constructs. */ | |
605 | ||
606 | #define ASM_APP_OFF "#NO_APP\n" | |
607 | ||
33561817 NC |
608 | #undef USER_LABEL_PREFIX |
609 | #define USER_LABEL_PREFIX "_" | |
610 | ||
11bb1f11 JL |
611 | /* This says how to output the assembler to define a global |
612 | uninitialized but not common symbol. | |
613 | Try to use asm_output_bss to implement this macro. */ | |
614 | ||
f7620587 JL |
615 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ |
616 | asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) | |
11bb1f11 | 617 | |
506a61b1 KG |
618 | /* Globalizing directive for a label. */ |
619 | #define GLOBAL_ASM_OP "\t.global " | |
11bb1f11 JL |
620 | |
621 | /* This is how to output a reference to a user-level label named NAME. | |
622 | `assemble_name' uses this. */ | |
623 | ||
e7ab5593 | 624 | #undef ASM_OUTPUT_LABELREF |
772c5265 | 625 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
33561817 | 626 | asm_fprintf (FILE, "%U%s", (*targetm.strip_name_encoding) (NAME)) |
11bb1f11 | 627 | |
11bb1f11 JL |
628 | /* This is how we tell the assembler that two symbols have the same value. */ |
629 | ||
630 | #define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \ | |
e7ab5593 NC |
631 | do \ |
632 | { \ | |
633 | assemble_name (FILE, NAME1); \ | |
634 | fputs (" = ", FILE); \ | |
635 | assemble_name (FILE, NAME2); \ | |
636 | fputc ('\n', FILE); \ | |
637 | } \ | |
638 | while (0) | |
11bb1f11 JL |
639 | |
640 | /* How to refer to registers in assembler output. | |
641 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
642 | ||
4af476d7 NC |
643 | #define REGISTER_NAMES \ |
644 | { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp", \ | |
645 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" \ | |
646 | , "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" \ | |
647 | , "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15" \ | |
648 | , "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23" \ | |
649 | , "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31" \ | |
650 | , "mdr", "EPSW" \ | |
a46ef285 AO |
651 | } |
652 | ||
4af476d7 NC |
653 | #define ADDITIONAL_REGISTER_NAMES \ |
654 | { {"r8", 4}, {"r9", 5}, {"r10", 6}, {"r11", 7}, \ | |
655 | {"r12", 0}, {"r13", 1}, {"r14", 2}, {"r15", 3}, \ | |
656 | {"e0", 10}, {"e1", 11}, {"e2", 12}, {"e3", 13}, \ | |
657 | {"e4", 14}, {"e5", 15}, {"e6", 16}, {"e7", 17} \ | |
658 | , {"fd0", 18}, {"fd2", 20}, {"fd4", 22}, {"fd6", 24} \ | |
659 | , {"fd8", 26}, {"fd10", 28}, {"fd12", 30}, {"fd14", 32} \ | |
660 | , {"fd16", 34}, {"fd18", 36}, {"fd20", 38}, {"fd22", 40} \ | |
661 | , {"fd24", 42}, {"fd26", 44}, {"fd28", 46}, {"fd30", 48} \ | |
662 | , {"cc", CC_REG} \ | |
a46ef285 | 663 | } |
11bb1f11 JL |
664 | |
665 | /* Print an instruction operand X on file FILE. | |
666 | look in mn10300.c for details */ | |
667 | ||
e7ab5593 NC |
668 | #define PRINT_OPERAND(FILE, X, CODE) \ |
669 | mn10300_print_operand (FILE, X, CODE) | |
11bb1f11 JL |
670 | |
671 | /* Print a memory operand whose address is X, on file FILE. | |
672 | This uses a function in output-vax.c. */ | |
673 | ||
e7ab5593 NC |
674 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ |
675 | mn10300_print_operand_address (FILE, ADDR) | |
11bb1f11 | 676 | |
11bb1f11 JL |
677 | /* This is how to output an element of a case-vector that is absolute. */ |
678 | ||
679 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
761c70aa | 680 | fprintf (FILE, "\t%s .L%d\n", ".long", VALUE) |
11bb1f11 JL |
681 | |
682 | /* This is how to output an element of a case-vector that is relative. */ | |
683 | ||
33f7f353 | 684 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
11bb1f11 JL |
685 | fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL) |
686 | ||
687 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
688 | if ((LOG) != 0) \ | |
689 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
690 | ||
956d6950 | 691 | /* We don't have to worry about dbx compatibility for the mn10300. */ |
11bb1f11 JL |
692 | #define DEFAULT_GDB_EXTENSIONS 1 |
693 | ||
5c68706c | 694 | /* Use dwarf2 debugging info by default. */ |
2720cc47 | 695 | #undef PREFERRED_DEBUGGING_TYPE |
5c68706c | 696 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG |
2720cc47 | 697 | #define DWARF2_DEBUGGING_INFO 1 |
5c68706c AO |
698 | #define DWARF2_ASM_LINE_DEBUG_INFO 1 |
699 | ||
11bb1f11 JL |
700 | /* Specify the machine mode that this machine uses |
701 | for the index in the tablejump instruction. */ | |
702 | #define CASE_VECTOR_MODE Pmode | |
703 | ||
11bb1f11 JL |
704 | /* Define if operations between registers always perform the operation |
705 | on the full register even if a narrower mode is specified. */ | |
706 | #define WORD_REGISTER_OPERATIONS | |
707 | ||
708 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
709 | ||
11bb1f11 JL |
710 | /* This flag, if defined, says the same insns that convert to a signed fixnum |
711 | also convert validly to an unsigned one. */ | |
712 | #define FIXUNS_TRUNC_LIKE_FIX_TRUNC | |
713 | ||
11bb1f11 JL |
714 | /* Max number of bytes we can move from memory to memory |
715 | in one reasonably fast instruction. */ | |
716 | #define MOVE_MAX 4 | |
717 | ||
718 | /* Define if shifts truncate the shift count | |
719 | which implies one can omit a sign-extension or zero-extension | |
720 | of a shift count. */ | |
721 | #define SHIFT_COUNT_TRUNCATED 1 | |
722 | ||
723 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
724 | is done just by pretending it is already truncated. */ | |
725 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
726 | ||
11bb1f11 JL |
727 | /* Specify the machine mode that pointers have. |
728 | After generation of rtl, the compiler makes no further distinction | |
729 | between pointers and any other objects of this machine mode. */ | |
730 | #define Pmode SImode | |
731 | ||
732 | /* A function address in a call instruction | |
733 | is a byte address (for indexing purposes) | |
734 | so give the MEM rtx a byte's mode. */ | |
735 | #define FUNCTION_MODE QImode | |
736 | ||
737 | /* The assembler op to get a word. */ | |
738 | ||
739 | #define FILE_ASM_OP "\t.file\n" | |
740 |