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cf011243 AO |
1 | /* Definitions of target machine for GNU compiler. |
2 | Matsushita MN10300 series | |
aeee4812 | 3 | Copyright (C) 1996-2023 Free Software Foundation, Inc. |
11bb1f11 JL |
4 | Contributed by Jeff Law (law@cygnus.com). |
5 | ||
e7ab5593 | 6 | This file is part of GCC. |
11bb1f11 | 7 | |
e7ab5593 NC |
8 | GCC is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
11bb1f11 | 12 | |
e7ab5593 NC |
13 | GCC is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
11bb1f11 | 17 | |
e7ab5593 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
11bb1f11 JL |
21 | |
22 | #undef ASM_SPEC | |
11bb1f11 JL |
23 | #undef LIB_SPEC |
24 | #undef ENDFILE_SPEC | |
e7ab5593 | 25 | #undef LINK_SPEC |
4a68b724 | 26 | #define LINK_SPEC "%{mrelax:%{!r:--relax}}" |
e7ab5593 | 27 | #undef STARTFILE_SPEC |
dff55dbc | 28 | #define STARTFILE_SPEC "%{!mno-crt0:%{!shared:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}" |
11bb1f11 JL |
29 | |
30 | /* Names to predefine in the preprocessor for this target machine. */ | |
31 | ||
cc956ba2 NB |
32 | #define TARGET_CPU_CPP_BUILTINS() \ |
33 | do \ | |
34 | { \ | |
35 | builtin_define ("__mn10300__"); \ | |
36 | builtin_define ("__MN10300__"); \ | |
816e93eb NC |
37 | builtin_assert ("cpu=mn10300"); \ |
38 | builtin_assert ("machine=mn10300"); \ | |
e7ab5593 | 39 | \ |
f3f63737 NC |
40 | if (TARGET_AM34) \ |
41 | { \ | |
42 | builtin_define ("__AM33__=4"); \ | |
43 | builtin_define ("__AM34__"); \ | |
44 | } \ | |
45 | else if (TARGET_AM33_2) \ | |
e7ab5593 NC |
46 | { \ |
47 | builtin_define ("__AM33__=2"); \ | |
48 | builtin_define ("__AM33_2__"); \ | |
49 | } \ | |
50 | else if (TARGET_AM33) \ | |
51 | builtin_define ("__AM33__=1"); \ | |
298362c8 NC |
52 | \ |
53 | builtin_define (TARGET_ALLOW_LIW ? \ | |
54 | "__LIW__" : "__NO_LIW__");\ | |
55 | \ | |
662c03f4 NC |
56 | builtin_define (TARGET_ALLOW_SETLB ? \ |
57 | "__SETLB__" : "__NO_SETLB__");\ | |
cc956ba2 NB |
58 | } \ |
59 | while (0) | |
11bb1f11 | 60 | |
cd8d8754 JM |
61 | #ifndef MN10300_OPTS_H |
62 | #include "config/mn10300/mn10300-opts.h" | |
63 | #endif | |
11bb1f11 | 64 | |
f3f63737 | 65 | extern enum processor_type mn10300_tune_cpu; |
d1776069 | 66 | |
13dd556c | 67 | #define TARGET_AM33 (mn10300_processor >= PROCESSOR_AM33) |
f3f63737 NC |
68 | #define TARGET_AM33_2 (mn10300_processor >= PROCESSOR_AM33_2) |
69 | #define TARGET_AM34 (mn10300_processor >= PROCESSOR_AM34) | |
13dd556c RS |
70 | |
71 | #ifndef PROCESSOR_DEFAULT | |
72 | #define PROCESSOR_DEFAULT PROCESSOR_MN10300 | |
11bb1f11 JL |
73 | #endif |
74 | ||
11bb1f11 JL |
75 | \f |
76 | /* Target machine storage layout */ | |
77 | ||
78 | /* Define this if most significant bit is lowest numbered | |
79 | in instructions that operate on numbered bit-fields. | |
80 | This is not true on the Matsushita MN1003. */ | |
81 | #define BITS_BIG_ENDIAN 0 | |
82 | ||
83 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
84 | /* This is not true on the Matsushita MN10300. */ | |
85 | #define BYTES_BIG_ENDIAN 0 | |
86 | ||
87 | /* Define this if most significant word of a multiword number is lowest | |
88 | numbered. | |
89 | This is not true on the Matsushita MN10300. */ | |
90 | #define WORDS_BIG_ENDIAN 0 | |
91 | ||
11bb1f11 JL |
92 | /* Width of a word, in units (bytes). */ |
93 | #define UNITS_PER_WORD 4 | |
94 | ||
11bb1f11 JL |
95 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
96 | #define PARM_BOUNDARY 32 | |
97 | ||
85f65093 | 98 | /* The stack goes in 32-bit lumps. */ |
11bb1f11 JL |
99 | #define STACK_BOUNDARY 32 |
100 | ||
101 | /* Allocation boundary (in *bits*) for the code of a function. | |
102 | 8 is the minimum boundary; it's unclear if bigger alignments | |
103 | would improve performance. */ | |
104 | #define FUNCTION_BOUNDARY 8 | |
105 | ||
8596d0a1 | 106 | /* No data type wants to be aligned rounder than this. */ |
11bb1f11 JL |
107 | #define BIGGEST_ALIGNMENT 32 |
108 | ||
109 | /* Alignment of field after `int : 0' in a structure. */ | |
e7ab5593 | 110 | #define EMPTY_FIELD_BOUNDARY 32 |
11bb1f11 JL |
111 | |
112 | /* Define this if move instructions will actually fail to work | |
113 | when given unaligned data. */ | |
114 | #define STRICT_ALIGNMENT 1 | |
115 | ||
116 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
117 | #define DEFAULT_SIGNED_CHAR 0 | |
6b9b8b34 JM |
118 | |
119 | #undef SIZE_TYPE | |
120 | #define SIZE_TYPE "unsigned int" | |
121 | ||
122 | #undef PTRDIFF_TYPE | |
123 | #define PTRDIFF_TYPE "int" | |
124 | ||
125 | #undef WCHAR_TYPE | |
126 | #define WCHAR_TYPE "long int" | |
127 | ||
128 | #undef WCHAR_TYPE_SIZE | |
129 | #define WCHAR_TYPE_SIZE BITS_PER_WORD | |
11bb1f11 JL |
130 | \f |
131 | /* Standard register usage. */ | |
132 | ||
133 | /* Number of actual hardware registers. | |
134 | The hardware registers are assigned numbers for the compiler | |
135 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
136 | ||
137 | All registers that the compiler knows about must be given numbers, | |
138 | even those that are not normally considered general registers. */ | |
139 | ||
4af476d7 NC |
140 | #define FIRST_PSEUDO_REGISTER 52 |
141 | ||
142 | /* Specify machine-specific register numbers. The commented out entries | |
143 | are defined in mn10300.md. */ | |
144 | #define FIRST_DATA_REGNUM 0 | |
145 | #define LAST_DATA_REGNUM 3 | |
146 | #define FIRST_ADDRESS_REGNUM 4 | |
147 | /* #define PIC_REG 6 */ | |
148 | #define LAST_ADDRESS_REGNUM 8 | |
149 | /* #define SP_REG 9 */ | |
a47944e2 | 150 | #define FIRST_EXTENDED_REGNUM 10 |
4af476d7 NC |
151 | #define LAST_EXTENDED_REGNUM 17 |
152 | #define FIRST_FP_REGNUM 18 | |
153 | #define LAST_FP_REGNUM 49 | |
c25a21f5 | 154 | /* #define MDR_REG 50 */ |
4af476d7 NC |
155 | /* #define CC_REG 51 */ |
156 | #define FIRST_ARGUMENT_REGNUM 0 | |
a47944e2 AO |
157 | |
158 | /* Specify the registers used for certain standard purposes. | |
159 | The values of these macros are register numbers. */ | |
160 | ||
161 | /* Register to use for pushing function arguments. */ | |
4af476d7 | 162 | #define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1) |
a47944e2 AO |
163 | |
164 | /* Base register for access to local variables of the function. */ | |
4af476d7 | 165 | #define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM - 1) |
a47944e2 AO |
166 | |
167 | /* Base register for access to arguments of the function. This | |
168 | is a fake register and will be eliminated into either the frame | |
169 | pointer or stack pointer. */ | |
170 | #define ARG_POINTER_REGNUM LAST_ADDRESS_REGNUM | |
171 | ||
172 | /* Register in which static-chain is passed to a function. */ | |
4af476d7 | 173 | #define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1) |
a47944e2 | 174 | |
11bb1f11 JL |
175 | /* 1 for registers that have pervasive standard uses |
176 | and are not available for the register allocator. */ | |
177 | ||
178 | #define FIXED_REGISTERS \ | |
c25a21f5 RH |
179 | { 0, 0, 0, 0, /* data regs */ \ |
180 | 0, 0, 0, 0, /* addr regs */ \ | |
181 | 1, /* arg reg */ \ | |
182 | 1, /* sp reg */ \ | |
183 | 0, 0, 0, 0, 0, 0, 0, 0, /* extended regs */ \ | |
184 | 0, 0, /* fp regs (18-19) */ \ | |
185 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \ | |
186 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (30-39) */ \ | |
187 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (40-49) */ \ | |
188 | 0, /* mdr reg */ \ | |
189 | 1 /* cc reg */ \ | |
18e9d2f9 | 190 | } |
11bb1f11 JL |
191 | |
192 | /* 1 for registers not available across function calls. | |
193 | These must include the FIXED_REGISTERS and also any | |
194 | registers that can be used without being saved. | |
195 | The latter must include the registers where values are returned | |
196 | and the register where structure-value addresses are passed. | |
197 | Aside from that, you can include as many other registers as you | |
198 | like. */ | |
199 | ||
d7fb4c31 | 200 | #define CALL_REALLY_USED_REGISTERS \ |
c25a21f5 RH |
201 | { 1, 1, 0, 0, /* data regs */ \ |
202 | 1, 1, 0, 0, /* addr regs */ \ | |
203 | 1, /* arg reg */ \ | |
204 | 1, /* sp reg */ \ | |
205 | 1, 1, 1, 1, 0, 0, 0, 0, /* extended regs */ \ | |
206 | 1, 1, /* fp regs (18-19) */ \ | |
207 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \ | |
208 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, /* fp regs (30-39) */ \ | |
209 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* fp regs (40-49) */ \ | |
210 | 1, /* mdr reg */ \ | |
211 | 1 /* cc reg */ \ | |
18e9d2f9 | 212 | } |
11bb1f11 JL |
213 | |
214 | #define REG_ALLOC_ORDER \ | |
18e9d2f9 AO |
215 | { 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9 \ |
216 | , 42, 43, 44, 45, 46, 47, 48, 49, 34, 35, 36, 37, 38, 39, 40, 41 \ | |
c25a21f5 | 217 | , 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 50, 51 \ |
18e9d2f9 | 218 | } |
705ac34f | 219 | |
4246e0c5 JL |
220 | /* 4 data, and effectively 3 address registers is small as far as I'm |
221 | concerned. */ | |
42db504c | 222 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true |
11bb1f11 JL |
223 | \f |
224 | /* Define the classes of registers for register constraints in the | |
225 | machine description. Also define ranges of constants. | |
226 | ||
227 | One of the classes must always be named ALL_REGS and include all hard regs. | |
228 | If there is more than one class, another class must be named NO_REGS | |
229 | and contain no registers. | |
230 | ||
231 | The name GENERAL_REGS must be the name of a class (or an alias for | |
232 | another name such as ALL_REGS). This is the class of registers | |
233 | that is allowed by "g" or "r" in a register constraint. | |
234 | Also, registers outside this class are allocated only when | |
235 | instructions express preferences for them. | |
236 | ||
237 | The classes must be numbered in nondecreasing order; that is, | |
238 | a larger-numbered class must never be contained completely | |
239 | in a smaller-numbered class. | |
240 | ||
241 | For any two classes, it is very desirable that there be another | |
242 | class that represents their union. */ | |
5abc5de9 | 243 | |
e7ab5593 NC |
244 | enum reg_class |
245 | { | |
36846b26 | 246 | NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, SP_OR_ADDRESS_REGS, |
c25a21f5 | 247 | EXTENDED_REGS, FP_REGS, FP_ACC_REGS, CC_REGS, MDR_REGS, |
36846b26 | 248 | GENERAL_REGS, SP_OR_GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES |
11bb1f11 JL |
249 | }; |
250 | ||
251 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
252 | ||
8596d0a1 | 253 | /* Give names of register classes as strings for dump file. */ |
11bb1f11 | 254 | |
c25a21f5 | 255 | #define REG_CLASS_NAMES \ |
36846b26 | 256 | { "NO_REGS", "DATA_REGS", "ADDRESS_REGS", "SP_REGS", "SP_OR_ADDRESS_REGS", \ |
c25a21f5 RH |
257 | "EXTENDED_REGS", "FP_REGS", "FP_ACC_REGS", "CC_REGS", "MDR_REGS", \ |
258 | "GENERAL_REGS", "SP_OR_GENERAL_REGS", "ALL_REGS", "LIM_REGS" \ | |
e7ab5593 | 259 | } |
11bb1f11 JL |
260 | |
261 | /* Define which registers fit in which classes. | |
262 | This is an initializer for a vector of HARD_REG_SET | |
263 | of length N_REG_CLASSES. */ | |
264 | ||
4af476d7 | 265 | #define REG_CLASS_CONTENTS \ |
f3f63737 | 266 | { { 0, 0 }, /* No regs */ \ |
4af476d7 NC |
267 | { 0x0000000f, 0 }, /* DATA_REGS */ \ |
268 | { 0x000001f0, 0 }, /* ADDRESS_REGS */ \ | |
269 | { 0x00000200, 0 }, /* SP_REGS */ \ | |
4af476d7 NC |
270 | { 0x000003f0, 0 }, /* SP_OR_ADDRESS_REGS */ \ |
271 | { 0x0003fc00, 0 }, /* EXTENDED_REGS */ \ | |
4af476d7 NC |
272 | { 0xfffc0000, 0x3ffff },/* FP_REGS */ \ |
273 | { 0x03fc0000, 0 }, /* FP_ACC_REGS */ \ | |
274 | { 0x00000000, 0x80000 },/* CC_REGS */ \ | |
c25a21f5 | 275 | { 0x00000000, 0x40000 },/* MDR_REGS */ \ |
4af476d7 | 276 | { 0x0003fdff, 0 }, /* GENERAL_REGS */ \ |
36846b26 | 277 | { 0x0003ffff, 0 }, /* SP_OR_GENERAL_REGS */ \ |
f3f63737 | 278 | { 0xffffffff, 0xfffff } /* ALL_REGS */ \ |
11bb1f11 JL |
279 | } |
280 | ||
281 | /* The same information, inverted: | |
282 | Return the class number of the smallest class containing | |
283 | reg number REGNO. This could be a conditional expression | |
284 | or could index an array. */ | |
285 | ||
e7ab5593 NC |
286 | #define REGNO_REG_CLASS(REGNO) \ |
287 | ((REGNO) <= LAST_DATA_REGNUM ? DATA_REGS : \ | |
288 | (REGNO) <= LAST_ADDRESS_REGNUM ? ADDRESS_REGS : \ | |
289 | (REGNO) == STACK_POINTER_REGNUM ? SP_REGS : \ | |
a47944e2 | 290 | (REGNO) <= LAST_EXTENDED_REGNUM ? EXTENDED_REGS : \ |
e7ab5593 | 291 | (REGNO) <= LAST_FP_REGNUM ? FP_REGS : \ |
c25a21f5 | 292 | (REGNO) == MDR_REG ? MDR_REGS : \ |
e7ab5593 | 293 | (REGNO) == CC_REG ? CC_REGS : \ |
7f13af23 | 294 | NO_REGS) |
11bb1f11 JL |
295 | |
296 | /* The class value for index registers, and the one for base regs. */ | |
36846b26 RH |
297 | #define INDEX_REG_CLASS \ |
298 | (TARGET_AM33 ? GENERAL_REGS : DATA_REGS) | |
299 | #define BASE_REG_CLASS \ | |
300 | (TARGET_AM33 ? SP_OR_GENERAL_REGS : SP_OR_ADDRESS_REGS) | |
11bb1f11 | 301 | |
11bb1f11 JL |
302 | /* Macros to check register numbers against specific register classes. */ |
303 | ||
a204fec0 AO |
304 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx |
305 | and check its validity for a certain class. | |
306 | We have two alternate definitions for each of them. | |
307 | The usual definition accepts all pseudo regs; the other rejects | |
308 | them unless they have been allocated suitable hard regs. | |
309 | The symbol REG_OK_STRICT causes the latter definition to be used. | |
310 | ||
311 | Most source files want to accept pseudo regs in the hope that | |
312 | they will get allocated to the class that the insn wants them to be in. | |
313 | Source files for reload pass need to be strict. | |
314 | After reload, it makes no difference, since pseudo regs have | |
315 | been eliminated by then. */ | |
316 | ||
11bb1f11 JL |
317 | /* These assume that REGNO is a hard or pseudo reg number. |
318 | They give nonzero only if REGNO is a hard reg of the suitable class | |
319 | or a pseudo reg currently allocated to a suitable hard reg. | |
320 | Since they use reg_renumber, they are safe only once reg_renumber | |
e53b6e56 | 321 | has been allocated, which happens in reginfo.cc during register |
aeb9f7cf | 322 | allocation. */ |
a204fec0 AO |
323 | |
324 | #ifndef REG_OK_STRICT | |
e733134f | 325 | # define REG_STRICT 0 |
a204fec0 | 326 | #else |
e733134f | 327 | # define REG_STRICT 1 |
a204fec0 AO |
328 | #endif |
329 | ||
e733134f | 330 | #define REGNO_DATA_P(regno, strict) \ |
36846b26 | 331 | mn10300_regno_in_class_p (regno, DATA_REGS, strict) |
e733134f | 332 | #define REGNO_ADDRESS_P(regno, strict) \ |
36846b26 | 333 | mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict) |
e733134f | 334 | #define REGNO_EXTENDED_P(regno, strict) \ |
36846b26 RH |
335 | mn10300_regno_in_class_p (regno, EXTENDED_REGS, strict) |
336 | #define REGNO_GENERAL_P(regno, strict) \ | |
337 | mn10300_regno_in_class_p (regno, GENERAL_REGS, strict) | |
e733134f AO |
338 | |
339 | #define REGNO_STRICT_OK_FOR_BASE_P(regno, strict) \ | |
36846b26 | 340 | mn10300_regno_in_class_p (regno, BASE_REG_CLASS, strict) |
11bb1f11 | 341 | #define REGNO_OK_FOR_BASE_P(regno) \ |
e733134f AO |
342 | (REGNO_STRICT_OK_FOR_BASE_P ((regno), REG_STRICT)) |
343 | #define REG_OK_FOR_BASE_P(X) \ | |
344 | (REGNO_OK_FOR_BASE_P (REGNO (X))) | |
11bb1f11 | 345 | |
e733134f | 346 | #define REGNO_STRICT_OK_FOR_BIT_BASE_P(regno, strict) \ |
36846b26 | 347 | mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict) |
4d1a91c2 | 348 | #define REGNO_OK_FOR_BIT_BASE_P(regno) \ |
e733134f AO |
349 | (REGNO_STRICT_OK_FOR_BIT_BASE_P ((regno), REG_STRICT)) |
350 | #define REG_OK_FOR_BIT_BASE_P(X) \ | |
351 | (REGNO_OK_FOR_BIT_BASE_P (REGNO (X))) | |
4d1a91c2 | 352 | |
e733134f | 353 | #define REGNO_STRICT_OK_FOR_INDEX_P(regno, strict) \ |
36846b26 | 354 | mn10300_regno_in_class_p (regno, INDEX_REG_CLASS, strict) |
11bb1f11 | 355 | #define REGNO_OK_FOR_INDEX_P(regno) \ |
e733134f AO |
356 | (REGNO_STRICT_OK_FOR_INDEX_P ((regno), REG_STRICT)) |
357 | #define REG_OK_FOR_INDEX_P(X) \ | |
358 | (REGNO_OK_FOR_INDEX_P (REGNO (X))) | |
11bb1f11 | 359 | |
11bb1f11 | 360 | #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ |
705ac34f | 361 | (!TARGET_AM33 && (MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS) |
11bb1f11 | 362 | |
18e9d2f9 AO |
363 | /* A class that contains registers which the compiler must always |
364 | access in a mode that is the same size as the mode in which it | |
365 | loaded the register. */ | |
366 | #define CLASS_CANNOT_CHANGE_SIZE FP_REGS | |
367 | ||
5abc5de9 | 368 | /* Return 1 if VALUE is in the range specified. */ |
11bb1f11 JL |
369 | |
370 | #define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100) | |
371 | #define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000) | |
372 | ||
11bb1f11 JL |
373 | \f |
374 | /* Stack layout; function entry, exit and calling. */ | |
375 | ||
376 | /* Define this if pushing a word on the stack | |
377 | makes the stack pointer a smaller address. */ | |
378 | ||
62f9f30b | 379 | #define STACK_GROWS_DOWNWARD 1 |
11bb1f11 | 380 | |
a4d05547 | 381 | /* Define this to nonzero if the nominal address of the stack frame |
11bb1f11 JL |
382 | is at the high-address end of the local variables; |
383 | that is, each additional local variable allocated | |
384 | goes at a more negative offset in the frame. */ | |
385 | ||
f62c8a5c | 386 | #define FRAME_GROWS_DOWNWARD 1 |
11bb1f11 | 387 | |
11bb1f11 JL |
388 | /* Offset of first parameter from the argument pointer register value. */ |
389 | /* Is equal to the size of the saved fp + pc, even if an fp isn't | |
390 | saved since the value is used before we know. */ | |
391 | ||
22ef4e9b | 392 | #define FIRST_PARM_OFFSET(FNDECL) 4 |
11bb1f11 | 393 | |
c157b3f0 RH |
394 | /* But the CFA is at the arg pointer directly, not at the first argument. */ |
395 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
396 | ||
777fbf09 JL |
397 | #define ELIMINABLE_REGS \ |
398 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
399 | { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ | |
400 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} | |
401 | ||
777fbf09 | 402 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
e7ab5593 | 403 | OFFSET = mn10300_initial_offset (FROM, TO) |
11bb1f11 | 404 | |
22ef4e9b JL |
405 | /* We use d0/d1 for passing parameters, so allocate 8 bytes of space |
406 | for a register flushback area. */ | |
407 | #define REG_PARM_STACK_SPACE(DECL) 8 | |
81464b2c | 408 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
f73ad30e | 409 | #define ACCUMULATE_OUTGOING_ARGS 1 |
e7ab5593 | 410 | |
3dbc43d1 JL |
411 | /* So we can allocate space for return pointers once for the function |
412 | instead of around every call. */ | |
413 | #define STACK_POINTER_OFFSET 4 | |
6e86170d | 414 | |
11bb1f11 | 415 | /* 1 if N is a possible register number for function argument passing. |
990dc016 | 416 | On the MN10300, d0 and d1 are used in this way. */ |
11bb1f11 | 417 | |
653958e8 | 418 | #define FUNCTION_ARG_REGNO_P(N) ((N) <= 1) |
22ef4e9b | 419 | |
11bb1f11 JL |
420 | \f |
421 | /* Define a data type for recording info about an argument list | |
422 | during the scan of that argument list. This data type should | |
423 | hold all necessary information about the function itself | |
424 | and about the args processed so far, enough to enable macros | |
425 | such as FUNCTION_ARG to determine where the next arg should go. | |
426 | ||
427 | On the MN10300, this is a single integer, which is a number of bytes | |
428 | of arguments scanned so far. */ | |
429 | ||
22ef4e9b | 430 | #define CUMULATIVE_ARGS struct cum_arg |
e7ab5593 NC |
431 | |
432 | struct cum_arg | |
433 | { | |
434 | int nbytes; | |
435 | }; | |
11bb1f11 JL |
436 | |
437 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
438 | for a call to a function whose data type is FNTYPE. | |
439 | For a library call, FNTYPE is 0. | |
440 | ||
441 | On the MN10300, the offset starts at 0. */ | |
442 | ||
0f6937fe | 443 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
22ef4e9b | 444 | ((CUM).nbytes = 0) |
11bb1f11 | 445 | |
34732b0a | 446 | #define FUNCTION_VALUE_REGNO_P(N) mn10300_function_value_regno_p (N) |
11bb1f11 | 447 | |
11bb1f11 | 448 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
11bb1f11 JL |
449 | |
450 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
451 | the stack pointer does not matter. The value is tested only in | |
452 | functions that have frame pointers. | |
453 | No definition is equivalent to always zero. */ | |
454 | ||
455 | #define EXIT_IGNORE_STACK 1 | |
456 | ||
457 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
458 | for profiling a function entry. */ | |
459 | ||
460 | #define FUNCTION_PROFILER(FILE, LABELNO) ; | |
461 | ||
11bb1f11 JL |
462 | /* Length in units of the trampoline for entering a nested function. */ |
463 | ||
d6a3e264 RH |
464 | #define TRAMPOLINE_SIZE 16 |
465 | #define TRAMPOLINE_ALIGNMENT 32 | |
11bb1f11 | 466 | |
74452ac3 JL |
467 | /* A C expression whose value is RTL representing the value of the return |
468 | address for the frame COUNT steps up from the current frame. | |
469 | ||
470 | On the mn10300, the return address is not at a constant location | |
471 | due to the frame layout. Luckily, it is at a constant offset from | |
472 | the argument pointer, so we define RETURN_ADDR_RTX to return a | |
473 | MEM using arg_pointer_rtx. Reload will replace arg_pointer_rtx | |
474 | with a reference to the stack/frame pointer + an appropriate offset. */ | |
475 | ||
476 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
477 | ((COUNT == 0) \ | |
c5c76735 | 478 | ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \ |
74452ac3 | 479 | : (rtx) 0) |
2720cc47 | 480 | |
885fe07c RH |
481 | /* The return address is saved both in the stack and in MDR. Using |
482 | the stack location is handiest for what unwinding needs. */ | |
483 | #define INCOMING_RETURN_ADDR_RTX \ | |
240930c4 | 484 | gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)) |
11bb1f11 | 485 | \f |
11bb1f11 JL |
486 | /* Maximum number of registers that can appear in a valid memory address. */ |
487 | ||
488 | #define MAX_REGS_PER_ADDRESS 2 | |
489 | ||
11bb1f11 | 490 | \f |
36846b26 RH |
491 | /* We have post-increments. */ |
492 | #define HAVE_POST_INCREMENT TARGET_AM33 | |
493 | #define HAVE_POST_MODIFY_DISP TARGET_AM33 | |
494 | ||
495 | /* ... But we don't want to use them for block moves. Small offsets are | |
496 | just as effective, at least for inline block move sizes, and appears | |
497 | to produce cleaner code. */ | |
498 | #define USE_LOAD_POST_INCREMENT(M) 0 | |
499 | #define USE_STORE_POST_INCREMENT(M) 0 | |
705ac34f | 500 | |
11bb1f11 | 501 | /* Accept either REG or SUBREG where a register is valid. */ |
5abc5de9 | 502 | |
e733134f AO |
503 | #define RTX_OK_FOR_BASE_P(X, strict) \ |
504 | ((REG_P (X) && REGNO_STRICT_OK_FOR_BASE_P (REGNO (X), \ | |
505 | (strict))) \ | |
11bb1f11 | 506 | || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \ |
e733134f AO |
507 | && REGNO_STRICT_OK_FOR_BASE_P (REGNO (SUBREG_REG (X)), \ |
508 | (strict)))) | |
11bb1f11 | 509 | |
36846b26 RH |
510 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \ |
511 | do { \ | |
512 | rtx new_x = mn10300_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \ | |
513 | if (new_x) \ | |
514 | { \ | |
515 | X = new_x; \ | |
516 | goto WIN; \ | |
517 | } \ | |
518 | } while (0) | |
11bb1f11 | 519 | \f |
11bb1f11 | 520 | |
d1776069 AO |
521 | /* Zero if this needs fixing up to become PIC. */ |
522 | ||
e7ab5593 NC |
523 | #define LEGITIMATE_PIC_OPERAND_P(X) \ |
524 | mn10300_legitimate_pic_operand_p (X) | |
d1776069 AO |
525 | |
526 | /* Register to hold the addressing base for | |
527 | position independent code access to data items. */ | |
528 | #define PIC_OFFSET_TABLE_REGNUM PIC_REG | |
529 | ||
530 | /* The name of the pseudo-symbol representing the Global Offset Table. */ | |
531 | #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" | |
532 | ||
533 | #define SYMBOLIC_CONST_P(X) \ | |
534 | ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ | |
535 | && ! LEGITIMATE_PIC_OPERAND_P (X)) | |
536 | ||
537 | /* Non-global SYMBOL_REFs have SYMBOL_REF_FLAG enabled. */ | |
538 | #define MN10300_GLOBAL_P(X) (! SYMBOL_REF_FLAG (X)) | |
11bb1f11 | 539 | \f |
bad41521 | 540 | #define SELECT_CC_MODE(OP, X, Y) mn10300_select_cc_mode (OP, X, Y) |
4af476d7 NC |
541 | #define REVERSIBLE_CC_MODE(MODE) 0 |
542 | \f | |
11bb1f11 JL |
543 | /* Nonzero if access to memory by bytes or half words is no faster |
544 | than accessing full words. */ | |
545 | #define SLOW_BYTE_ACCESS 1 | |
546 | ||
1e8552c2 | 547 | #define NO_FUNCTION_CSE 1 |
22ef4e9b | 548 | |
e53b6e56 | 549 | /* According expr.cc, a value of around 6 should minimize code size, and |
11bb1f11 | 550 | for the MN10300 series, that's our primary concern. */ |
e04ad03d | 551 | #define MOVE_RATIO(speed) 6 |
11bb1f11 JL |
552 | |
553 | #define TEXT_SECTION_ASM_OP "\t.section .text" | |
554 | #define DATA_SECTION_ASM_OP "\t.section .data" | |
e7ab5593 | 555 | #define BSS_SECTION_ASM_OP "\t.section .bss" |
11bb1f11 | 556 | |
11bb1f11 JL |
557 | #define ASM_COMMENT_START "#" |
558 | ||
559 | /* Output to assembler file text saying following lines | |
560 | may contain character constants, extra white space, comments, etc. */ | |
561 | ||
562 | #define ASM_APP_ON "#APP\n" | |
563 | ||
564 | /* Output to assembler file text saying following lines | |
565 | no longer contain unusual constructs. */ | |
566 | ||
567 | #define ASM_APP_OFF "#NO_APP\n" | |
568 | ||
33561817 NC |
569 | #undef USER_LABEL_PREFIX |
570 | #define USER_LABEL_PREFIX "_" | |
571 | ||
11bb1f11 JL |
572 | /* This says how to output the assembler to define a global |
573 | uninitialized but not common symbol. | |
574 | Try to use asm_output_bss to implement this macro. */ | |
575 | ||
f7620587 JL |
576 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ |
577 | asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) | |
11bb1f11 | 578 | |
506a61b1 KG |
579 | /* Globalizing directive for a label. */ |
580 | #define GLOBAL_ASM_OP "\t.global " | |
11bb1f11 JL |
581 | |
582 | /* This is how to output a reference to a user-level label named NAME. | |
583 | `assemble_name' uses this. */ | |
584 | ||
e7ab5593 | 585 | #undef ASM_OUTPUT_LABELREF |
772c5265 | 586 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ |
33561817 | 587 | asm_fprintf (FILE, "%U%s", (*targetm.strip_name_encoding) (NAME)) |
11bb1f11 | 588 | |
11bb1f11 JL |
589 | /* This is how we tell the assembler that two symbols have the same value. */ |
590 | ||
591 | #define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \ | |
e7ab5593 NC |
592 | do \ |
593 | { \ | |
594 | assemble_name (FILE, NAME1); \ | |
595 | fputs (" = ", FILE); \ | |
596 | assemble_name (FILE, NAME2); \ | |
597 | fputc ('\n', FILE); \ | |
598 | } \ | |
599 | while (0) | |
11bb1f11 JL |
600 | |
601 | /* How to refer to registers in assembler output. | |
602 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
603 | ||
4af476d7 NC |
604 | #define REGISTER_NAMES \ |
605 | { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp", \ | |
606 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" \ | |
607 | , "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" \ | |
608 | , "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15" \ | |
609 | , "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23" \ | |
610 | , "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31" \ | |
611 | , "mdr", "EPSW" \ | |
a46ef285 AO |
612 | } |
613 | ||
4af476d7 NC |
614 | #define ADDITIONAL_REGISTER_NAMES \ |
615 | { {"r8", 4}, {"r9", 5}, {"r10", 6}, {"r11", 7}, \ | |
616 | {"r12", 0}, {"r13", 1}, {"r14", 2}, {"r15", 3}, \ | |
617 | {"e0", 10}, {"e1", 11}, {"e2", 12}, {"e3", 13}, \ | |
618 | {"e4", 14}, {"e5", 15}, {"e6", 16}, {"e7", 17} \ | |
619 | , {"fd0", 18}, {"fd2", 20}, {"fd4", 22}, {"fd6", 24} \ | |
620 | , {"fd8", 26}, {"fd10", 28}, {"fd12", 30}, {"fd14", 32} \ | |
621 | , {"fd16", 34}, {"fd18", 36}, {"fd20", 38}, {"fd22", 40} \ | |
622 | , {"fd24", 42}, {"fd26", 44}, {"fd28", 46}, {"fd30", 48} \ | |
623 | , {"cc", CC_REG} \ | |
a46ef285 | 624 | } |
11bb1f11 JL |
625 | |
626 | /* Print an instruction operand X on file FILE. | |
e53b6e56 | 627 | look in mn10300.cc for details */ |
11bb1f11 | 628 | |
e7ab5593 NC |
629 | #define PRINT_OPERAND(FILE, X, CODE) \ |
630 | mn10300_print_operand (FILE, X, CODE) | |
11bb1f11 JL |
631 | |
632 | /* Print a memory operand whose address is X, on file FILE. | |
633 | This uses a function in output-vax.c. */ | |
634 | ||
e7ab5593 NC |
635 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ |
636 | mn10300_print_operand_address (FILE, ADDR) | |
11bb1f11 | 637 | |
11bb1f11 JL |
638 | /* This is how to output an element of a case-vector that is absolute. */ |
639 | ||
640 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
761c70aa | 641 | fprintf (FILE, "\t%s .L%d\n", ".long", VALUE) |
11bb1f11 JL |
642 | |
643 | /* This is how to output an element of a case-vector that is relative. */ | |
644 | ||
33f7f353 | 645 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
11bb1f11 JL |
646 | fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL) |
647 | ||
648 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
649 | if ((LOG) != 0) \ | |
650 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
651 | ||
5c68706c | 652 | /* Use dwarf2 debugging info by default. */ |
2720cc47 | 653 | #undef PREFERRED_DEBUGGING_TYPE |
5c68706c | 654 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG |
2720cc47 | 655 | #define DWARF2_DEBUGGING_INFO 1 |
5c68706c AO |
656 | #define DWARF2_ASM_LINE_DEBUG_INFO 1 |
657 | ||
11bb1f11 JL |
658 | /* Specify the machine mode that this machine uses |
659 | for the index in the tablejump instruction. */ | |
660 | #define CASE_VECTOR_MODE Pmode | |
661 | ||
11bb1f11 JL |
662 | /* Define if operations between registers always perform the operation |
663 | on the full register even if a narrower mode is specified. */ | |
9e11bfef | 664 | #define WORD_REGISTER_OPERATIONS 1 |
11bb1f11 JL |
665 | |
666 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
667 | ||
11bb1f11 JL |
668 | /* Max number of bytes we can move from memory to memory |
669 | in one reasonably fast instruction. */ | |
670 | #define MOVE_MAX 4 | |
671 | ||
672 | /* Define if shifts truncate the shift count | |
673 | which implies one can omit a sign-extension or zero-extension | |
674 | of a shift count. */ | |
675 | #define SHIFT_COUNT_TRUNCATED 1 | |
676 | ||
11bb1f11 JL |
677 | /* Specify the machine mode that pointers have. |
678 | After generation of rtl, the compiler makes no further distinction | |
679 | between pointers and any other objects of this machine mode. */ | |
680 | #define Pmode SImode | |
681 | ||
682 | /* A function address in a call instruction | |
683 | is a byte address (for indexing purposes) | |
684 | so give the MEM rtx a byte's mode. */ | |
685 | #define FUNCTION_MODE QImode | |
686 | ||
687 | /* The assembler op to get a word. */ | |
688 | ||
689 | #define FILE_ASM_OP "\t.file\n" | |
690 |