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9304f876 | 1 | ;; Constraint definitions of Andes NDS32 cpu for GNU compiler |
cbe34bb5 | 2 | ;; Copyright (C) 2012-2017 Free Software Foundation, Inc. |
9304f876 CJW |
3 | ;; Contributed by Andes Technology Corporation. |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ;; Check 16.8.7 Defining Machine-Specific Constraints for detail. | |
22 | ||
23 | ;; NO contrains can be prefixed with: E F V X g i m n o p r s | |
24 | ;; Machine-dependent integer: I J K L M N O P | |
25 | ;; Machine-dependent floating: G H | |
26 | ||
27 | ||
28 | (define_register_constraint "w" "(TARGET_ISA_V3 || TARGET_ISA_V3M) ? LOW_REGS : NO_REGS" | |
29 | "LOW register class $r0 ~ $r7 constraint for V3/V3M ISA") | |
30 | ||
31 | (define_register_constraint "l" "LOW_REGS" | |
32 | "LOW register class $r0 ~ $r7") | |
33 | ||
34 | (define_register_constraint "d" "MIDDLE_REGS" | |
35 | "MIDDLE register class $r0 ~ $r11, $r16 ~ $r19") | |
36 | ||
37 | (define_register_constraint "h" "HIGH_REGS" | |
38 | "HIGH register class $r12 ~ $r14, $r20 ~ $r31") | |
39 | ||
40 | ||
41 | (define_register_constraint "t" "R15_TA_REG" | |
42 | "Temporary Assist register $ta (i.e. $r15)") | |
43 | ||
44 | (define_register_constraint "k" "STACK_REG" | |
45 | "Stack register $sp") | |
46 | ||
47 | ||
48 | (define_constraint "Iu03" | |
49 | "Unsigned immediate 3-bit value" | |
50 | (and (match_code "const_int") | |
51 | (match_test "ival < (1 << 3) && ival >= 0"))) | |
52 | ||
53 | (define_constraint "In03" | |
54 | "Negative immediate 3-bit value in the range of -7 to 0" | |
55 | (and (match_code "const_int") | |
56 | (match_test "IN_RANGE (ival, -7, 0)"))) | |
57 | ||
58 | (define_constraint "Iu04" | |
59 | "Unsigned immediate 4-bit value" | |
60 | (and (match_code "const_int") | |
61 | (match_test "ival < (1 << 4) && ival >= 0"))) | |
62 | ||
63 | (define_constraint "Is05" | |
64 | "Signed immediate 5-bit value" | |
65 | (and (match_code "const_int") | |
66 | (match_test "ival < (1 << 4) && ival >= -(1 << 4)"))) | |
67 | ||
68 | (define_constraint "Iu05" | |
69 | "Unsigned immediate 5-bit value" | |
70 | (and (match_code "const_int") | |
71 | (match_test "ival < (1 << 5) && ival >= 0"))) | |
72 | ||
73 | (define_constraint "In05" | |
74 | "Negative immediate 5-bit value in the range of -31 to 0" | |
75 | (and (match_code "const_int") | |
76 | (match_test "IN_RANGE (ival, -31, 0)"))) | |
77 | ||
78 | ;; Ip05 is special and dedicated for v3 movpi45 instruction. | |
79 | ;; movpi45 has imm5u field but the range is 16 ~ 47. | |
80 | (define_constraint "Ip05" | |
81 | "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47" | |
82 | (and (match_code "const_int") | |
83 | (match_test "ival < ((1 << 5) + 16) | |
84 | && ival >= (0 + 16) | |
85 | && (TARGET_ISA_V3 || TARGET_ISA_V3M)"))) | |
86 | ||
87 | (define_constraint "Iu06" | |
88 | "Unsigned immediate 6-bit value constraint for addri36.sp instruction" | |
89 | (and (match_code "const_int") | |
90 | (match_test "ival < (1 << 6) | |
91 | && ival >= 0 | |
92 | && (ival % 4 == 0) | |
93 | && (TARGET_ISA_V3 || TARGET_ISA_V3M)"))) | |
94 | ||
95 | (define_constraint "Iu08" | |
96 | "Unsigned immediate 8-bit value" | |
97 | (and (match_code "const_int") | |
98 | (match_test "ival < (1 << 8) && ival >= 0"))) | |
99 | ||
100 | (define_constraint "Iu09" | |
101 | "Unsigned immediate 9-bit value" | |
102 | (and (match_code "const_int") | |
103 | (match_test "ival < (1 << 9) && ival >= 0"))) | |
104 | ||
105 | ||
106 | (define_constraint "Is10" | |
107 | "Signed immediate 10-bit value" | |
108 | (and (match_code "const_int") | |
109 | (match_test "ival < (1 << 9) && ival >= -(1 << 9)"))) | |
110 | ||
111 | (define_constraint "Is11" | |
112 | "Signed immediate 11-bit value" | |
113 | (and (match_code "const_int") | |
114 | (match_test "ival < (1 << 10) && ival >= -(1 << 10)"))) | |
115 | ||
116 | ||
117 | (define_constraint "Is15" | |
118 | "Signed immediate 15-bit value" | |
119 | (and (match_code "const_int") | |
120 | (match_test "ival < (1 << 14) && ival >= -(1 << 14)"))) | |
121 | ||
122 | (define_constraint "Iu15" | |
123 | "Unsigned immediate 15-bit value" | |
124 | (and (match_code "const_int") | |
125 | (match_test "ival < (1 << 15) && ival >= 0"))) | |
126 | ||
127 | ||
128 | ;; Ic15 is special and dedicated for performance extension | |
129 | ;; 'bclr' (single-bit-clear) instruction. | |
130 | ;; It is used in andsi3 pattern and recognized for the immediate | |
131 | ;; which is NOT in the range of imm15u but OK for 'bclr' instruction. | |
132 | ;; (If the immediate value IS in the range of imm15u, | |
133 | ;; we can directly use 'andi' instruction.) | |
134 | (define_constraint "Ic15" | |
135 | "A constant which is not in the range of imm15u but ok for bclr instruction" | |
136 | (and (match_code "const_int") | |
137 | (match_test "(ival & 0xffff8000) && nds32_can_use_bclr_p (ival)"))) | |
138 | ||
139 | ;; Ie15 is special and dedicated for performance extension | |
140 | ;; 'bset' (single-bit-set) instruction. | |
141 | ;; It is used in iorsi3 pattern and recognized for the immediate | |
142 | ;; which is NOT in the range of imm15u but OK for 'bset' instruction. | |
143 | ;; (If the immediate value IS in the range of imm15u, | |
144 | ;; we can directly use 'ori' instruction.) | |
145 | (define_constraint "Ie15" | |
146 | "A constant which is not in the range of imm15u but ok for bset instruction" | |
147 | (and (match_code "const_int") | |
148 | (match_test "(ival & 0xffff8000) && nds32_can_use_bset_p (ival)"))) | |
149 | ||
150 | ;; It15 is special and dedicated for performance extension | |
151 | ;; 'btgl' (single-bit-toggle) instruction. | |
152 | ;; It is used in xorsi3 pattern and recognized for the immediate | |
153 | ;; which is NOT in the range of imm15u but OK for 'btgl' instruction. | |
154 | ;; (If the immediate value IS in the range of imm15u, | |
155 | ;; we can directly use 'xori' instruction.) | |
156 | (define_constraint "It15" | |
157 | "A constant which is not in the range of imm15u but ok for btgl instruction" | |
158 | (and (match_code "const_int") | |
159 | (match_test "(ival & 0xffff8000) && nds32_can_use_btgl_p (ival)"))) | |
160 | ||
161 | ||
162 | ;; Ii15 is special and dedicated for v3 isa | |
163 | ;; 'bitci' (bit-clear-immediate) instruction. | |
164 | ;; It is used in andsi3 pattern and recognized for the immediate whose | |
165 | ;; (~ival) value is in the range of imm15u and OK for 'bitci' instruction. | |
166 | ;; For example, 'andi $r0,$r0,0xfffffffc' can be presented | |
167 | ; with 'bitci $r0,$r0,3'. | |
168 | (define_constraint "Ii15" | |
169 | "A constant whose compliment value is in the range of imm15u | |
170 | and ok for bitci instruction" | |
171 | (and (match_code "const_int") | |
172 | (match_test "nds32_can_use_bitci_p (ival)"))) | |
173 | ||
174 | ||
175 | (define_constraint "Is16" | |
176 | "Signed immediate 16-bit value" | |
177 | (and (match_code "const_int") | |
178 | (match_test "ival < (1 << 15) && ival >= -(1 << 15)"))) | |
179 | ||
180 | (define_constraint "Is17" | |
181 | "Signed immediate 17-bit value" | |
182 | (and (match_code "const_int") | |
183 | (match_test "ival < (1 << 16) && ival >= -(1 << 16)"))) | |
184 | ||
185 | ||
186 | (define_constraint "Is19" | |
187 | "Signed immediate 19-bit value" | |
188 | (and (match_code "const_int") | |
189 | (match_test "ival < (1 << 18) && ival >= -(1 << 18)"))) | |
190 | ||
191 | ||
192 | (define_constraint "Is20" | |
193 | "Signed immediate 20-bit value" | |
194 | (and (match_code "const_int") | |
195 | (match_test "ival < (1 << 19) && ival >= -(1 << 19)"))) | |
196 | ||
197 | ||
198 | (define_constraint "Ihig" | |
199 | "The immediate value that can be simply set high 20-bit" | |
200 | (and (match_code "const_int") | |
201 | (match_test "(ival != 0) && ((ival & 0xfff) == 0)"))) | |
202 | ||
203 | (define_constraint "Izeb" | |
204 | "The immediate value 0xff" | |
205 | (and (match_code "const_int") | |
206 | (match_test "(ival == 0xff)"))) | |
207 | ||
208 | (define_constraint "Izeh" | |
209 | "The immediate value 0xffff" | |
210 | (and (match_code "const_int") | |
211 | (match_test "(ival == 0xffff)"))) | |
212 | ||
213 | (define_constraint "Ixls" | |
214 | "The immediate value 0x01" | |
215 | (and (match_code "const_int") | |
216 | (match_test "TARGET_PERF_EXT && (ival == 0x1)"))) | |
217 | ||
218 | (define_constraint "Ix11" | |
219 | "The immediate value 0x7ff" | |
220 | (and (match_code "const_int") | |
221 | (match_test "TARGET_PERF_EXT && (ival == 0x7ff)"))) | |
222 | ||
223 | (define_constraint "Ibms" | |
224 | "The immediate value with power of 2" | |
225 | (and (match_code "const_int") | |
226 | (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M) | |
227 | && (IN_RANGE (exact_log2 (ival), 0, 7))"))) | |
228 | ||
229 | (define_constraint "Ifex" | |
230 | "The immediate value with power of 2 minus 1" | |
231 | (and (match_code "const_int") | |
232 | (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M) | |
233 | && (IN_RANGE (exact_log2 (ival + 1), 1, 8))"))) | |
234 | ||
235 | ||
236 | (define_memory_constraint "U33" | |
237 | "Memory constraint for 333 format" | |
238 | (and (match_code "mem") | |
239 | (match_test "nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U"))) | |
240 | ||
241 | (define_memory_constraint "U45" | |
242 | "Memory constraint for 45 format" | |
243 | (and (match_code "mem") | |
244 | (match_test "(nds32_mem_format (op) == ADDRESS_REG) | |
245 | && (GET_MODE (op) == SImode)"))) | |
246 | ||
247 | (define_memory_constraint "U37" | |
248 | "Memory constraint for 37 format" | |
249 | (and (match_code "mem") | |
250 | (match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U | |
251 | || nds32_mem_format (op) == ADDRESS_FP_IMM7U) | |
252 | && (GET_MODE (op) == SImode)"))) | |
253 | ||
254 | ;; ------------------------------------------------------------------------ |