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9304f876 1;; Intrinsic patterns description of Andes NDS32 cpu for GNU compiler
23a5b65a 2;; Copyright (C) 2012-2014 Free Software Foundation, Inc.
9304f876
CJW
3;; Contributed by Andes Technology Corporation.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15;; License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; ------------------------------------------------------------------------
22
23;; Register Transfer.
24
25(define_insn "unspec_volatile_mfsr"
26 [(set (match_operand:SI 0 "register_operand" "=r")
27 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MFSR))]
28 ""
29 "mfsr\t%0, %V1"
30 [(set_attr "type" "misc")
31 (set_attr "length" "4")]
32)
33
34(define_insn "unspec_volatile_mfusr"
35 [(set (match_operand:SI 0 "register_operand" "=r")
36 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MFUSR))]
37 ""
38 "mfusr\t%0, %V1"
39 [(set_attr "type" "misc")
40 (set_attr "length" "4")]
41)
42
43(define_insn "unspec_volatile_mtsr"
44 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
45 (match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MTSR)]
46 ""
47 "mtsr\t%0, %V1"
48 [(set_attr "type" "misc")
49 (set_attr "length" "4")]
50)
51
52(define_insn "unspec_volatile_mtusr"
53 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
54 (match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MTUSR)]
55 ""
56 "mtusr\t%0, %V1"
57 [(set_attr "type" "misc")
58 (set_attr "length" "4")]
59)
60
61;; ------------------------------------------------------------------------
62
63;; Interrupt Instructions.
64
65(define_insn "unspec_volatile_setgie_en"
66 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETGIE_EN)]
67 ""
68 "setgie.e"
69 [(set_attr "type" "misc")]
70)
71
72(define_insn "unspec_volatile_setgie_dis"
73 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETGIE_DIS)]
74 ""
75 "setgie.d"
76 [(set_attr "type" "misc")]
77)
78
79;; ------------------------------------------------------------------------
80
81;; Cache Synchronization Instructions
82
83(define_insn "unspec_volatile_isync"
84 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_ISYNC)]
85 ""
86 "isync\t%0"
87 [(set_attr "type" "misc")]
88)
89
90(define_insn "unspec_volatile_isb"
91 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_ISB)]
92 ""
93 "isb"
94 [(set_attr "type" "misc")]
95)
96
97;; ------------------------------------------------------------------------