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9304f876 1;; Intrinsic patterns description of Andes NDS32 cpu for GNU compiler
85ec4feb 2;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
9304f876
CJW		 3;; Contributed by Andes Technology Corporation.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15;; License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; ------------------------------------------------------------------------
22
23;; Register Transfer.
24
25(define_insn "unspec_volatile_mfsr"
26 [(set (match_operand:SI 0 "register_operand" "=r")
27 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MFSR))]
28 ""
29 "mfsr\t%0, %V1"
30 [(set_attr "type" "misc")
31 (set_attr "length" "4")]
32)
33
34(define_insn "unspec_volatile_mfusr"
35 [(set (match_operand:SI 0 "register_operand" "=r")
36 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MFUSR))]
37 ""
38 "mfusr\t%0, %V1"
39 [(set_attr "type" "misc")
40 (set_attr "length" "4")]
41)
42
154e3ea6
MC		 43(define_expand "mtsr_isb"
44 [(set (match_operand:SI 0 "register_operand" "")
45 (match_operand:SI 1 "immediate_operand" ""))]
46 ""
47{
48 emit_insn (gen_unspec_volatile_mtsr (operands[0], operands[1]));
49 emit_insn (gen_unspec_volatile_isb());
50 DONE;
51})
52
53(define_expand "mtsr_dsb"
54 [(set (match_operand:SI 0 "register_operand" "")
55 (match_operand:SI 1 "immediate_operand" ""))]
56 ""
57{
58 emit_insn (gen_unspec_volatile_mtsr (operands[0], operands[1]));
59 emit_insn (gen_unspec_dsb());
60 DONE;
61})
62
9304f876
CJW		 63(define_insn "unspec_volatile_mtsr"
64 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
65 (match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MTSR)]
66 ""
67 "mtsr\t%0, %V1"
68 [(set_attr "type" "misc")
69 (set_attr "length" "4")]
70)
71
72(define_insn "unspec_volatile_mtusr"
73 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
74 (match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_MTUSR)]
75 ""
76 "mtusr\t%0, %V1"
77 [(set_attr "type" "misc")
78 (set_attr "length" "4")]
79)
80
0bb4423d
MC		 81;; FPU Register Transfer.
82
83(define_insn "unspec_fcpynsd"
84 [(set (match_operand:DF 0 "register_operand" "=f")
85 (unspec:DF [(match_operand:DF 1 "register_operand" "f")
86 (match_operand:DF 2 "register_operand" "f")] UNSPEC_FCPYNSD))]
87 ""
88 "fcpynsd\t%0, %1, %2"
89 [(set_attr "type" "misc")
90 (set_attr "length" "4")]
91)
92
93(define_insn "unspec_fcpynss"
94 [(set (match_operand:SF 0 "register_operand" "=f")
95 (unspec:SF [(match_operand:SF 1 "register_operand" "f")
96 (match_operand:SF 2 "register_operand" "f")] UNSPEC_FCPYNSS))]
97 ""
98 "fcpynss\t%0, %1, %2"
99 [(set_attr "type" "misc")
100 (set_attr "length" "4")]
101)
102
103(define_insn "unspec_fcpysd"
104 [(set (match_operand:DF 0 "register_operand" "=f")
105 (unspec:DF [(match_operand:DF 1 "register_operand" "f")
106 (match_operand:DF 2 "register_operand" "f")] UNSPEC_FCPYSD))]
107 ""
108 "fcpysd\t%0, %1, %2"
109 [(set_attr "type" "misc")
110 (set_attr "length" "4")]
111)
112
113(define_insn "unspec_fcpyss"
114 [(set (match_operand:SF 0 "register_operand" "=f")
115 (unspec:SF [(match_operand:SF 1 "register_operand" "f")
116 (match_operand:SF 2 "register_operand" "f")] UNSPEC_FCPYSS))]
117 ""
118 "fcpyss\t%0, %1, %2"
119 [(set_attr "type" "misc")
120 (set_attr "length" "4")]
121)
122
123(define_insn "unspec_fmfcsr"
124 [(set (match_operand:SI 0 "register_operand" "=r")
125 (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_FMFCSR))]
126 ""
127 "fmfcsr\t%0"
128 [(set_attr "type" "misc")
129 (set_attr "length" "4")]
130)
131
132(define_insn "unspec_fmtcsr"
133 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_FMTCSR)]
134 ""
135 "fmtcsr\t%0"
136 [(set_attr "type" "misc")
137 (set_attr "length" "4")]
138)
139
140(define_insn "unspec_fmfcfg"
141 [(set (match_operand:SI 0 "register_operand" "=r")
142 (unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_FMFCFG))]
143 ""
144 "fmfcfg\t%0"
145 [(set_attr "type" "misc")
146 (set_attr "length" "4")]
147)
148
9304f876
CJW		 149;; ------------------------------------------------------------------------
150
151;; Interrupt Instructions.
152
153(define_insn "unspec_volatile_setgie_en"
154 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETGIE_EN)]
155 ""
156 "setgie.e"
157 [(set_attr "type" "misc")]
158)
159
160(define_insn "unspec_volatile_setgie_dis"
161 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETGIE_DIS)]
162 ""
163 "setgie.d"
164 [(set_attr "type" "misc")]
165)
166
167;; ------------------------------------------------------------------------
168
169;; Cache Synchronization Instructions
170
171(define_insn "unspec_volatile_isync"
172 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_ISYNC)]
173 ""
174 "isync\t%0"
175 [(set_attr "type" "misc")]
176)
177
178(define_insn "unspec_volatile_isb"
179 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_ISB)]
180 ""
181 "isb"
182 [(set_attr "type" "misc")]
183)
184
154e3ea6
MC		 185(define_insn "unspec_dsb"
186 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_DSB)]
187 ""
188 "dsb"
189 [(set_attr "type" "misc")]
190)
191
192(define_insn "unspec_msync"
193 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_MSYNC)]
194 ""
195 "msync\t%0"
196 [(set_attr "type" "misc")]
197)
198
199(define_insn "unspec_msync_all"
200 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_MSYNC_ALL)]
201 ""
202 "msync\tall"
203 [(set_attr "type" "misc")]
204)
205
206(define_insn "unspec_msync_store"
207 [(unspec_volatile [(const_int 0)] UNSPEC_VOLATILE_MSYNC_STORE)]
208 ""
209 "msync\tstore"
210 [(set_attr "type" "misc")]
211)
212
213;; Load and Store
214
215(define_insn "unspec_volatile_llw"
216 [(set (match_operand:SI 0 "register_operand" "=r")
217 (unspec_volatile:SI [(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
218 (match_operand:SI 2 "register_operand" "r")))] UNSPEC_VOLATILE_LLW))]
219 ""
220 "llw\t%0, [%1 + %2]"
221 [(set_attr "length" "4")]
222)
223
224(define_insn "unspec_lwup"
225 [(set (match_operand:SI 0 "register_operand" "=r")
226 (unspec_volatile:SI [(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
227 (match_operand:SI 2 "register_operand" "r")))] UNSPEC_LWUP))]
228 ""
229 "lwup\t%0, [%1 + %2]"
230 [(set_attr "length" "4")]
231)
232
233(define_insn "unspec_lbup"
234 [(set (match_operand:SI 0 "register_operand" "=r")
235 (unspec_volatile:SI [(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
236 (match_operand:SI 2 "register_operand" "r")))] UNSPEC_LBUP))]
237 ""
238 "lbup\t%0, [%1 + %2]"
239 [(set_attr "length" "4")]
240)
241
242(define_insn "unspec_volatile_scw"
243 [(set (match_operand:SI 0 "register_operand" "=r")
244 (unspec_volatile:SI [(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
245 (match_operand:SI 2 "register_operand" "r")))
246 (match_operand:SI 3 "register_operand" "0")] UNSPEC_VOLATILE_SCW))]
247 ""
248 "scw\t%0, [%1 + %2]"
249 [(set_attr "length" "4")]
250)
251
252(define_insn "unspec_swup"
253 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
254 (match_operand:SI 1 "register_operand" "r")))
255 (unspec:SI [(match_operand:SI 2 "register_operand" "r")] UNSPEC_SWUP))]
256 ""
257 "swup\t%2, [%0 + %1]"
258 [(set_attr "length" "4")]
259)
260
261(define_insn "unspec_sbup"
262 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
263 (match_operand:SI 1 "register_operand" "r")))
264 (unspec:SI [(match_operand:SI 2 "register_operand" "r")] UNSPEC_SBUP))]
265 ""
266 "sbup\t%2, [%0 + %1]"
267 [(set_attr "length" "4")]
268)
f1a0afe2
MC		 269
270;; CCTL
271
272(define_insn "cctl_l1d_invalall"
273 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_CCTL_L1D_INVALALL)]
274 ""
275 "cctl\tL1D_INVALALL"
276 [(set_attr "type" "mmu")]
277)
278
279(define_insn "cctl_l1d_wball_alvl"
280 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_CCTL_L1D_WBALL_ALVL)]
281 ""
282 "cctl\tL1D_WBALL, alevel"
283 [(set_attr "type" "mmu")]
284)
285
286(define_insn "cctl_l1d_wball_one_lvl"
287 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_CCTL_L1D_WBALL_ONE_LVL)]
288 ""
289 "cctl\tL1D_WBALL, 1level"
290 [(set_attr "type" "mmu")]
291)
292
293(define_insn "cctl_idx_read"
294 [(set (match_operand:SI 0 "register_operand" "=r")
295 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")
296 (match_operand:SI 2 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_IDX_READ))]
297 ""
298 "cctl\t%0, %2, %X1"
299 [(set_attr "type" "mmu")]
300)
301
302(define_insn "cctl_idx_write"
303 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
304 (match_operand:SI 1 "register_operand" "r")
305 (match_operand:SI 2 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_IDX_WRITE)]
306 ""
307 "cctl\t%1, %2, %W0"
308 [(set_attr "type" "mmu")]
309)
310
311(define_insn "cctl_va_wbinval_l1"
312 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
313 (match_operand:SI 1 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_VA_WBINVAL_L1)]
314 ""
315 "cctl\t%1, %U0, 1level"
316 [(set_attr "type" "mmu")]
317)
318
319(define_insn "cctl_va_wbinval_la"
320 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
321 (match_operand:SI 1 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_VA_WBINVAL_LA)]
322 ""
323 "cctl\t%1, %U0, alevel"
324 [(set_attr "type" "mmu")]
325)
326
327(define_insn "cctl_idx_wbinval"
328 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
329 (match_operand:SI 1 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_IDX_WBINVAL)]
330 ""
331 "cctl\t%1, %T0"
332 [(set_attr "type" "mmu")]
333)
334
335(define_insn "cctl_va_lck"
336 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")
337 (match_operand:SI 1 "register_operand" "r")] UNSPEC_VOLATILE_CCTL_VA_LCK)]
338 ""
339 "cctl\t%1, %R0"
340 [(set_attr "type" "mmu")]
341)
2feae6cd
MC		 342
343
344;; Performance Extension
345
346(define_expand "unspec_ave"
347 [(match_operand:SI 0 "register_operand" "")
348 (match_operand:SI 1 "register_operand" "")
349 (match_operand:SI 2 "register_operand" "")]
350 ""
351{
352 emit_insn (gen_ave (operands[0], operands[1], operands[2]));
353 DONE;
354})
355
356(define_expand "unspec_bclr"
357 [(match_operand:SI 0 "register_operand" "")
358 (match_operand:SI 1 "register_operand" "")
359 (match_operand:SI 2 "immediate_operand" "")]
360 ""
361{
362 unsigned HOST_WIDE_INT val = ~(1u << UINTVAL (operands[2]));
363 emit_insn (gen_andsi3 (operands[0], operands[1], gen_int_mode (val, SImode)));
364 DONE;
365})
366
367(define_expand "unspec_bset"
368 [(match_operand:SI 0 "register_operand" "")
369 (match_operand:SI 1 "register_operand" "")
370 (match_operand:SI 2 "immediate_operand" "")]
371 ""
372{
373 unsigned HOST_WIDE_INT val = 1u << UINTVAL (operands[2]);
374 emit_insn (gen_iorsi3 (operands[0], operands[1], gen_int_mode (val, SImode)));
375 DONE;
376})
377
378(define_expand "unspec_btgl"
379 [(match_operand:SI 0 "register_operand" "")
380 (match_operand:SI 1 "register_operand" "")
381 (match_operand:SI 2 "immediate_operand" "")]
382 ""
383{
384 unsigned HOST_WIDE_INT val = 1u << UINTVAL (operands[2]);
385 emit_insn (gen_xorsi3 (operands[0], operands[1], gen_int_mode (val, SImode)));
386 DONE;
387})
388
389(define_expand "unspec_btst"
390 [(match_operand:SI 0 "register_operand" "")
391 (match_operand:SI 1 "register_operand" "")
392 (match_operand:SI 2 "immediate_operand" "")]
393 ""
394{
395 emit_insn (gen_btst (operands[0], operands[1], operands[2]));
396 DONE;
397})
398
399(define_insn "unspec_clip"
400 [(set (match_operand:SI 0 "register_operand" "=r")
401 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
402 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIP))]
403 ""
404 "clip\t%0, %1, %2"
405 [(set_attr "type" "alu")
406 (set_attr "length" "4")]
407)
408
409(define_insn "unspec_clips"
410 [(set (match_operand:SI 0 "register_operand" "=r")
411 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
412 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIPS))]
413 ""
414 "clips\t%0, %1, %2"
415 [(set_attr "type" "alu")
416 (set_attr "length" "4")]
417)
418
419(define_insn "unspec_clo"
420 [(set (match_operand:SI 0 "register_operand" "=r")
421 (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_CLO))]
422 ""
423 "clo\t%0, %1"
424 [(set_attr "type" "alu")
425 (set_attr "length" "4")]
426)
427
428(define_insn "unspec_ssabssi2"
429 [(set (match_operand:SI 0 "register_operand" "=r")
430 (ss_abs:SI (match_operand:SI 1 "register_operand" "r")))]
431 ""
432 "abs\t%0, %1"
433 [(set_attr "type" "alu")
434 (set_attr "length" "4")]
435)
436
437;; Performance extension 2
438
439(define_insn "unspec_pbsad"
440 [(set (match_operand:SI 0 "register_operand" "=r")
441 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
442 (match_operand:SI 2 "register_operand" "r")] UNSPEC_PBSAD))]
443 ""
444 "pbsad\t%0, %1, %2"
445 [(set_attr "type" "pbsad")
446 (set_attr "length" "4")]
447)
448
449(define_insn "unspec_pbsada"
450 [(set (match_operand:SI 0 "register_operand" "=r")
451 (unspec:SI [(match_operand:SI 1 "register_operand" "0")
452 (match_operand:SI 2 "register_operand" "r")
453 (match_operand:SI 3 "register_operand" "r")] UNSPEC_PBSADA))]
454 ""
455 "pbsada\t%0, %2, %3"
456 [(set_attr "type" "pbsada")
457 (set_attr "length" "4")]
458)
459
460(define_expand "bse"
461 [(match_operand:SI 0 "register_operand" "")
462 (match_operand:SI 1 "register_operand" "")
463 (match_operand:SI 2 "register_operand" "")]
464 ""
465 {
466 rtx temp0 = gen_reg_rtx (SImode);
467 rtx temp2 = gen_reg_rtx (SImode);
468
469 emit_move_insn (temp0, gen_rtx_MEM (Pmode, operands[0]));
470 emit_move_insn (temp2, gen_rtx_MEM (Pmode, operands[2]));
471 emit_insn (gen_unspec_bse (temp0, operands[1], temp2, temp0, temp2));
472 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp0);
473 emit_move_insn (gen_rtx_MEM (Pmode, operands[2]), temp2);
474 DONE;
475 }
476)
477
478(define_insn "unspec_bse"
479 [(set (match_operand:SI 0 "register_operand" "=r")
480 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
481 (match_operand:SI 2 "register_operand" "r")
482 (match_operand:SI 3 "register_operand" "0")] UNSPEC_BSE))
483 (set (match_operand:SI 4 "register_operand" "=2")
484 (unspec:SI [(match_dup 1)
485 (match_dup 2)
486 (match_dup 0)] UNSPEC_BSE_2))]
487 ""
488 "bse\t%0, %1, %2"
489 [(set_attr "type" "alu")
490 (set_attr "length" "4")]
491)
492
493(define_expand "bsp"
494 [(match_operand:SI 0 "register_operand" "")
495 (match_operand:SI 1 "register_operand" "")
496 (match_operand:SI 2 "register_operand" "")]
497 ""
498 {
499 rtx temp0 = gen_reg_rtx (SImode);
500 rtx temp2 = gen_reg_rtx (SImode);
501
502 emit_move_insn (temp0, gen_rtx_MEM (Pmode, operands[0]));
503 emit_move_insn (temp2, gen_rtx_MEM (Pmode, operands[2]));
504 emit_insn (gen_unspec_bsp (temp0, operands[1], temp2, temp0, temp2));
505 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp0);
506 emit_move_insn (gen_rtx_MEM (Pmode, operands[2]), temp2);
507 DONE;
508 }
509)
510
511(define_insn "unspec_bsp"
512 [(set (match_operand:SI 0 "register_operand" "=r")
513 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
514 (match_operand:SI 2 "register_operand" "r")
515 (match_operand:SI 3 "register_operand" "0")] UNSPEC_BSP))
516 (set (match_operand:SI 4 "register_operand" "=2")
517 (unspec:SI [(match_dup 1)
518 (match_dup 2)
519 (match_dup 0)] UNSPEC_BSP_2))]
520 ""
521 "bsp\t%0, %1, %2"
522 [(set_attr "type" "alu")
523 (set_attr "length" "4")]
524)
525
3999578c
MC		 526;; String Extension
527
528(define_insn "unspec_ffb"
529 [(set (match_operand:SI 0 "register_operand" "=r, r")
530 (unspec:SI [(match_operand:SI 1 "register_operand" "r, r")
531 (match_operand:SI 2 "nonmemory_operand" "Iu08, r")] UNSPEC_FFB))]
532 ""
533 "@
534 ffbi\t%0, %1, %2
535 ffb\t%0, %1, %2"
536 [(set_attr "type" "alu")
537 (set_attr "length" "4")]
538)
539
540(define_insn "unspec_ffmism"
541 [(set (match_operand:SI 0 "register_operand" "=r")
542 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
543 (match_operand:SI 2 "register_operand" "r")] UNSPEC_FFMISM))]
544 ""
545 "ffmism\t%0, %1, %2"
546 [(set_attr "type" "alu")
547 (set_attr "length" "4")]
548)
549
550(define_insn "unspec_flmism"
551 [(set (match_operand:SI 0 "register_operand" "=r")
552 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
553 (match_operand:SI 2 "register_operand" "r")] UNSPEC_FLMISM))]
554 ""
555 "flmism\t%0, %1, %2"
556 [(set_attr "type" "alu")
557 (set_attr "length" "4")]
558)
559
2feae6cd
MC		 560;; System
561
562(define_insn "unspec_sva"
563 [(set (match_operand:SI 0 "register_operand" "=r")
564 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
565 (match_operand:SI 2 "register_operand" "r")] UNSPEC_SVA))]
566 ""
567 "sva\t%0, %1, %2"
568 [(set_attr "type" "alu")
569 (set_attr "length" "4")]
570)
571
572(define_insn "unspec_svs"
573 [(set (match_operand:SI 0 "register_operand" "=r")
574 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
575 (match_operand:SI 2 "register_operand" "r")] UNSPEC_SVS))]
576 ""
577 "svs\t%0, %1, %2"
578 [(set_attr "type" "alu")
579 (set_attr "length" "4")]
580)
581
582(define_insn "unspec_jr_itoff"
583 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_JR_ITOFF)]
584 ""
585 "jr.itoff\t%0"
586 [(set_attr "type" "misc")]
587)
588
589(define_insn "unspec_jr_toff"
590 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_JR_TOFF)]
591 ""
592 "jr.toff\t%0"
593 [(set_attr "type" "branch")]
594)
595
596(define_insn "unspec_jral_iton"
597 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_JRAL_ITON)]
598 ""
599 "jral.iton\t%0"
600 [(set_attr "type" "branch")]
601)
602
603(define_insn "unspec_jral_ton"
604 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_JRAL_TON)]
605 ""
606 "jral.ton\t%0"
607 [(set_attr "type" "branch")]
608)
609
610(define_insn "unspec_ret_itoff"
611 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_RET_ITOFF)]
612 ""
613 "ret.itoff\t%0"
614 [(set_attr "type" "branch")]
615)
616
617(define_insn "unspec_ret_toff"
618 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_VOLATILE_RET_TOFF)]
619 ""
620 "ret.toff\t%0"
621 [(set_attr "type" "branch")]
622)
623
624(define_insn "unspec_standby_no_wake_grant"
625 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_STANDBY_NO_WAKE_GRANT)]
626 ""
627 "standby\tno_wake_grant"
628 [(set_attr "type" "misc")]
629)
630
631(define_insn "unspec_standby_wake_grant"
632 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_STANDBY_WAKE_GRANT)]
633 ""
634 "standby\twake_grant"
635 [(set_attr "type" "misc")]
636)
637
638(define_insn "unspec_standby_wait_done"
639 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_STANDBY_WAKE_DONE)]
640 ""
641 "standby\twait_done"
642 [(set_attr "type" "misc")]
643)
644
645(define_insn "unspec_teqz"
646 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
647 (match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_TEQZ)]
648 ""
649 "teqz\t%0, %1"
650 [(set_attr "type" "misc")]
651)
652
653(define_insn "unspec_tnez"
654 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
655 (match_operand:SI 1 "immediate_operand" "i")] UNSPEC_VOLATILE_TNEZ)]
656 ""
657 "tnez\t%0, %1"
658 [(set_attr "type" "misc")]
659)
660
661(define_insn "unspec_trap"
662 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_TRAP)]
663 ""
664 "trap\t%0"
665 [(set_attr "type" "misc")]
666)
667
668(define_insn "unspec_setend_big"
669 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETEND_BIG)]
670 ""
671 "setend.b"
672 [(set_attr "type" "misc")]
673)
674
675(define_insn "unspec_setend_little"
676 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_SETEND_LITTLE)]
677 ""
678 "setend.l"
679 [(set_attr "type" "misc")]
680)
681
682(define_insn "unspec_break"
683 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_BREAK)]
684 ""
685 "break\t%0"
686 [(set_attr "type" "misc")]
687)
688
689(define_insn "unspec_syscall"
690 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_SYSCALL)]
691 ""
692 "syscall\t%0"
693 [(set_attr "type" "misc")]
694)
695
696(define_insn "unspec_nop"
697 [(unspec_volatile:SI [(const_int 0)] UNSPEC_VOLATILE_NOP)]
698 ""
699 "nop"
700 [(set_attr "type" "misc")]
701)
702
703(define_expand "unspec_get_current_sp"
704 [(match_operand:SI 0 "register_operand" "")]
705 ""
706{
707 emit_move_insn (operands[0], gen_rtx_REG (SImode, SP_REGNUM));
708 DONE;
709})
710
711(define_expand "unspec_set_current_sp"
712 [(match_operand:SI 0 "register_operand" "")]
713 ""
714{
715 emit_move_insn (gen_rtx_REG (SImode, SP_REGNUM), operands[0]);
716 DONE;
717})
718
719(define_expand "unspec_return_address"
720 [(match_operand:SI 0 "register_operand" "")]
721 ""
722{
723 emit_move_insn (operands[0], gen_rtx_REG (SImode, LP_REGNUM));
724 DONE;
725})
726
727;; Swap
728
729(define_insn "unspec_wsbh"
730 [(set (match_operand:SI 0 "register_operand" "=r")
731 (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_WSBH))]
732 ""
733 "wsbh\t%0, %1"
734 [(set_attr "type" "alu")
735 (set_attr "length" "4")]
736)
e576ddb5
KC		 737;;Unaligned Load/Store
738
739(define_expand "unaligned_load_hw"
740 [(set (match_operand:HI 0 "register_operand" "")
741 (unspec:HI [(mem:HI (match_operand:SI 1 "register_operand" ""))] UNSPEC_UALOAD_HW))]
742 ""
743{
744 operands[0] = simplify_gen_subreg (SImode, operands[0],
745 GET_MODE (operands[0]), 0);
746 if (TARGET_ISA_V3M)
747 {
748 nds32_expand_unaligned_load (operands, HImode);
749 }
750 else
751 {
752 emit_insn (gen_unaligned_load_w (operands[0],
753 gen_rtx_MEM (SImode, operands[1])));
754
755 if (WORDS_BIG_ENDIAN)
756 emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT(16)));
757 else
758 emit_insn (gen_andsi3 (operands[0], operands[0], GEN_INT (0xffff)));
759 }
760
761 DONE;
762})
763
764(define_expand "unaligned_loadsi"
765 [(set (match_operand:SI 0 "register_operand" "=r")
766 (unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_W))]
767 ""
768{
769 if (TARGET_ISA_V3M)
770 nds32_expand_unaligned_load (operands, SImode);
771 else
772 emit_insn (gen_unaligned_load_w (operands[0],
773 gen_rtx_MEM (SImode, (operands[1]))));
774 DONE;
775})
776
777(define_insn "unaligned_load_w"
778 [(set (match_operand:SI 0 "register_operand" "= r")
779 (unspec:SI [(match_operand:SI 1 "nds32_lmw_smw_base_operand" " Umw")] UNSPEC_UALOAD_W))]
780 ""
781{
782 return nds32_output_lmw_single_word (operands);
783}
784 [(set_attr "type" "load")
785 (set_attr "length" "4")]
786)
787
788(define_expand "unaligned_loaddi"
789 [(set (match_operand:DI 0 "register_operand" "=r")
790 (unspec:DI [(mem:DI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_DW))]
791 ""
792{
793 if (TARGET_ISA_V3M)
794 {
795 nds32_expand_unaligned_load (operands, DImode);
796 }
797 else
798 emit_insn (gen_unaligned_load_dw (operands[0], operands[1]));
799 DONE;
800})
801
802(define_insn "unaligned_load_dw"
803 [(set (match_operand:DI 0 "register_operand" "=r")
804 (unspec:DI [(mem:DI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_DW))]
805 ""
806{
807 rtx otherops[3];
808 otherops[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
809 otherops[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
810 otherops[2] = operands[1];
811
812 output_asm_insn ("lmw.bi\t%0, [%2], %1, 0", otherops);
813 return "";
814}
815 [(set_attr "type" "load")
816 (set_attr "length" "4")]
817)
818
819(define_expand "unaligned_store_hw"
820 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
821 (unspec:HI [(match_operand:HI 1 "register_operand" "")] UNSPEC_UASTORE_HW))]
822 ""
823{
824 operands[1] = simplify_gen_subreg (SImode, operands[1],
825 GET_MODE (operands[1]), 0);
826 nds32_expand_unaligned_store (operands, HImode);
827 DONE;
828})
829
830(define_expand "unaligned_storesi"
831 [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
832 (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_UASTORE_W))]
833 ""
834{
835 if (TARGET_ISA_V3M)
836 nds32_expand_unaligned_store (operands, SImode);
837 else
838 emit_insn (gen_unaligned_store_w (gen_rtx_MEM (SImode, operands[0]),
839 operands[1]));
840 DONE;
841})
842
843(define_insn "unaligned_store_w"
844 [(set (match_operand:SI 0 "nds32_lmw_smw_base_operand" "=Umw")
845 (unspec:SI [(match_operand:SI 1 "register_operand" " r")] UNSPEC_UASTORE_W))]
846 ""
847{
848 return nds32_output_smw_single_word (operands);
849}
850 [(set_attr "type" "store")
851 (set_attr "length" "4")]
852)
853
854(define_expand "unaligned_storedi"
855 [(set (mem:DI (match_operand:SI 0 "register_operand" "r"))
856 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_UASTORE_DW))]
857 ""
858{
859 if (TARGET_ISA_V3M)
860 nds32_expand_unaligned_store (operands, DImode);
861 else
862 emit_insn (gen_unaligned_store_dw (operands[0], operands[1]));
863 DONE;
864})
865
866(define_insn "unaligned_store_dw"
867 [(set (mem:DI (match_operand:SI 0 "register_operand" "r"))
868 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_UASTORE_DW))]
869 ""
870{
871 rtx otherops[3];
872 otherops[0] = gen_rtx_REG (SImode, REGNO (operands[1]));
873 otherops[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
874 otherops[2] = operands[0];
875
876 output_asm_insn ("smw.bi\t%0, [%2], %1, 0", otherops);
877 return "";
878}
879 [(set_attr "type" "store")
880 (set_attr "length" "4")]
881)
882
9304f876 883;; ------------------------------------------------------------------------
Mirror of https://gcc.gnu.org/git/gcc.git