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1 | ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler |
2 | ;; Copyright (C) 2012-2018 Free Software Foundation, Inc. | |
3 | ;; Contributed by Andes Technology Corporation. | |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ||
22 | ;; ------------------------------------------------------------------------ | |
23 | ;; Define N9 2R1W pipeline settings. | |
24 | ;; ------------------------------------------------------------------------ | |
25 | ||
26 | (define_automaton "nds32_n9_2r1w_machine") | |
27 | ||
28 | ;; ------------------------------------------------------------------------ | |
29 | ;; Pipeline Stages | |
30 | ;; ------------------------------------------------------------------------ | |
31 | ;; IF - Instruction Fetch | |
32 | ;; II - Instruction Issue / Instruction Decode | |
33 | ;; EX - Instruction Execution | |
34 | ;; MM - Memory Execution | |
35 | ;; WB - Instruction Retire / Result Write-Back | |
36 | ||
37 | (define_cpu_unit "n9_2r1w_ii" "nds32_n9_2r1w_machine") | |
38 | (define_cpu_unit "n9_2r1w_ex" "nds32_n9_2r1w_machine") | |
39 | (define_cpu_unit "n9_2r1w_mm" "nds32_n9_2r1w_machine") | |
40 | (define_cpu_unit "n9_2r1w_wb" "nds32_n9_2r1w_machine") | |
41 | ||
42 | (define_insn_reservation "nds_n9_2r1w_unknown" 1 | |
43 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
44 | (and (eq_attr "type" "unknown") | |
45 | (eq_attr "pipeline_model" "n9"))) | |
46 | "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb") | |
47 | ||
48 | (define_insn_reservation "nds_n9_2r1w_misc" 1 | |
49 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
50 | (and (eq_attr "type" "misc") | |
51 | (eq_attr "pipeline_model" "n9"))) | |
52 | "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb") | |
53 | ||
54 | (define_insn_reservation "nds_n9_2r1w_mmu" 1 | |
55 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
56 | (and (eq_attr "type" "mmu") | |
57 | (eq_attr "pipeline_model" "n9"))) | |
58 | "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb") | |
59 | ||
60 | (define_insn_reservation "nds_n9_2r1w_alu" 1 | |
61 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
62 | (and (eq_attr "type" "alu") | |
63 | (eq_attr "pipeline_model" "n9"))) | |
64 | "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb") | |
65 | ||
66 | (define_insn_reservation "nds_n9_2r1w_alu_shift" 1 | |
67 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
68 | (and (eq_attr "type" "alu_shift") | |
69 | (eq_attr "pipeline_model" "n9"))) | |
70 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
71 | ||
72 | (define_insn_reservation "nds_n9_2r1w_pbsad" 1 | |
73 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
74 | (and (eq_attr "type" "pbsad") | |
75 | (eq_attr "pipeline_model" "n9"))) | |
76 | "n9_2r1w_ii, n9_2r1w_ex*3, n9_2r1w_mm, n9_2r1w_wb") | |
77 | ||
78 | (define_insn_reservation "nds_n9_2r1w_pbsada" 1 | |
79 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
80 | (and (eq_attr "type" "pbsada") | |
81 | (eq_attr "pipeline_model" "n9"))) | |
82 | "n9_2r1w_ii, n9_2r1w_ex*3, n9_2r1w_mm, n9_2r1w_wb") | |
83 | ||
84 | (define_insn_reservation "nds_n9_2r1w_load" 1 | |
85 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
86 | (and (match_test "nds32::load_single_p (insn)") | |
87 | (eq_attr "pipeline_model" "n9"))) | |
88 | "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb") | |
89 | ||
90 | (define_insn_reservation "nds_n9_2r1w_store" 1 | |
91 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
92 | (and (match_test "nds32::store_single_p (insn)") | |
93 | (eq_attr "pipeline_model" "n9"))) | |
94 | "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb") | |
95 | ||
96 | (define_insn_reservation "nds_n9_2r1w_load_multiple_1" 1 | |
97 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
98 | (and (eq_attr "pipeline_model" "n9") | |
99 | (and (eq_attr "type" "load_multiple") | |
100 | (eq_attr "combo" "1")))) | |
101 | "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb") | |
102 | ||
103 | (define_insn_reservation "nds_n9_2r1w_load_multiple_2" 1 | |
104 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
105 | (and (eq_attr "pipeline_model" "n9") | |
106 | (ior (and (eq_attr "type" "load_multiple") | |
107 | (eq_attr "combo" "2")) | |
108 | (match_test "nds32::load_double_p (insn)")))) | |
109 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
110 | ||
111 | (define_insn_reservation "nds_n9_2r1w_load_multiple_3" 1 | |
112 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
113 | (and (eq_attr "pipeline_model" "n9") | |
114 | (and (eq_attr "type" "load_multiple") | |
115 | (eq_attr "combo" "3")))) | |
116 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
117 | ||
118 | (define_insn_reservation "nds_n9_2r1w_load_multiple_4" 1 | |
119 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
120 | (and (eq_attr "pipeline_model" "n9") | |
121 | (and (eq_attr "type" "load_multiple") | |
122 | (eq_attr "combo" "4")))) | |
123 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
124 | ||
125 | (define_insn_reservation "nds_n9_2r1w_load_multiple_5" 1 | |
126 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
127 | (and (eq_attr "pipeline_model" "n9") | |
128 | (and (eq_attr "type" "load_multiple") | |
129 | (eq_attr "combo" "5")))) | |
130 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*2, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
131 | ||
132 | (define_insn_reservation "nds_n9_2r1w_load_multiple_6" 1 | |
133 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
134 | (and (eq_attr "pipeline_model" "n9") | |
135 | (and (eq_attr "type" "load_multiple") | |
136 | (eq_attr "combo" "6")))) | |
137 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*3, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
138 | ||
139 | (define_insn_reservation "nds_n9_2r1w_load_multiple_7" 1 | |
140 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
141 | (and (eq_attr "pipeline_model" "n9") | |
142 | (and (eq_attr "type" "load_multiple") | |
143 | (eq_attr "combo" "7")))) | |
144 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*4, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
145 | ||
146 | (define_insn_reservation "nds_n9_2r1w_load_multiple_8" 1 | |
147 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
148 | (and (eq_attr "pipeline_model" "n9") | |
149 | (and (eq_attr "type" "load_multiple") | |
150 | (eq_attr "combo" "8")))) | |
151 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*5, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
152 | ||
153 | (define_insn_reservation "nds_n9_2r1w_load_multiple_12" 1 | |
154 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
155 | (and (eq_attr "pipeline_model" "n9") | |
156 | (and (eq_attr "type" "load_multiple") | |
157 | (eq_attr "combo" "12")))) | |
158 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*9, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
159 | ||
160 | (define_insn_reservation "nds_n9_2r1w_store_multiple_1" 1 | |
161 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
162 | (and (eq_attr "pipeline_model" "n9") | |
163 | (and (eq_attr "type" "store_multiple") | |
164 | (eq_attr "combo" "1")))) | |
165 | "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb") | |
166 | ||
167 | (define_insn_reservation "nds_n9_2r1w_store_multiple_2" 1 | |
168 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
169 | (and (eq_attr "pipeline_model" "n9") | |
170 | (ior (and (eq_attr "type" "store_multiple") | |
171 | (eq_attr "combo" "2")) | |
172 | (match_test "nds32::store_double_p (insn)")))) | |
173 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
174 | ||
175 | (define_insn_reservation "nds_n9_2r1w_store_multiple_3" 1 | |
176 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
177 | (and (eq_attr "pipeline_model" "n9") | |
178 | (and (eq_attr "type" "store_multiple") | |
179 | (eq_attr "combo" "3")))) | |
180 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
181 | ||
182 | (define_insn_reservation "nds_n9_2r1w_store_multiple_4" 1 | |
183 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
184 | (and (eq_attr "pipeline_model" "n9") | |
185 | (and (eq_attr "type" "store_multiple") | |
186 | (eq_attr "combo" "4")))) | |
187 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
188 | ||
189 | (define_insn_reservation "nds_n9_2r1w_store_multiple_5" 1 | |
190 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
191 | (and (eq_attr "pipeline_model" "n9") | |
192 | (and (eq_attr "type" "store_multiple") | |
193 | (eq_attr "combo" "5")))) | |
194 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*2, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
195 | ||
196 | (define_insn_reservation "nds_n9_2r1w_store_multiple_6" 1 | |
197 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
198 | (and (eq_attr "pipeline_model" "n9") | |
199 | (and (eq_attr "type" "store_multiple") | |
200 | (eq_attr "combo" "6")))) | |
201 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*3, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
202 | ||
203 | (define_insn_reservation "nds_n9_2r1w_store_multiple_7" 1 | |
204 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
205 | (and (eq_attr "pipeline_model" "n9") | |
206 | (and (eq_attr "type" "store_multiple") | |
207 | (eq_attr "combo" "7")))) | |
208 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*4, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
209 | ||
210 | (define_insn_reservation "nds_n9_2r1w_store_multiple_8" 1 | |
211 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
212 | (and (eq_attr "pipeline_model" "n9") | |
213 | (and (eq_attr "type" "store_multiple") | |
214 | (eq_attr "combo" "8")))) | |
215 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*5, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
216 | ||
217 | (define_insn_reservation "nds_n9_2r1w_store_multiple_12" 1 | |
218 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
219 | (and (eq_attr "pipeline_model" "n9") | |
220 | (and (eq_attr "type" "store_multiple") | |
221 | (eq_attr "combo" "12")))) | |
222 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*9, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
223 | ||
224 | (define_insn_reservation "nds_n9_2r1w_mul_fast" 1 | |
225 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config != MUL_TYPE_SLOW") | |
226 | (and (eq_attr "type" "mul") | |
227 | (eq_attr "pipeline_model" "n9"))) | |
228 | "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb") | |
229 | ||
230 | (define_insn_reservation "nds_n9_2r1w_mul_slow" 1 | |
231 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config == MUL_TYPE_SLOW") | |
232 | (and (eq_attr "type" "mul") | |
233 | (eq_attr "pipeline_model" "n9"))) | |
234 | "n9_2r1w_ii, n9_2r1w_ex*17, n9_2r1w_mm, n9_2r1w_wb") | |
235 | ||
236 | (define_insn_reservation "nds_n9_2r1w_mac_fast" 1 | |
237 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config != MUL_TYPE_SLOW") | |
238 | (and (eq_attr "type" "mac") | |
239 | (eq_attr "pipeline_model" "n9"))) | |
240 | "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
241 | ||
242 | (define_insn_reservation "nds_n9_2r1w_mac_slow" 1 | |
243 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config == MUL_TYPE_SLOW") | |
244 | (and (eq_attr "type" "mac") | |
245 | (eq_attr "pipeline_model" "n9"))) | |
246 | "n9_2r1w_ii, (n9_2r1w_ii+n9_2r1w_ex)*17, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
247 | ||
248 | (define_insn_reservation "nds_n9_2r1w_div" 1 | |
249 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
250 | (and (eq_attr "type" "div") | |
251 | (eq_attr "pipeline_model" "n9"))) | |
252 | "n9_2r1w_ii, (n9_2r1w_ii+n9_2r1w_ex)*34, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb") | |
253 | ||
254 | (define_insn_reservation "nds_n9_2r1w_branch" 1 | |
255 | (and (match_test "nds32_register_ports_config == REG_PORT_2R1W") | |
256 | (and (eq_attr "type" "branch") | |
257 | (eq_attr "pipeline_model" "n9"))) | |
258 | "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb") | |
259 | ||
260 | ;; ------------------------------------------------------------------------ | |
261 | ;; Comment Notations and Bypass Rules | |
262 | ;; ------------------------------------------------------------------------ | |
263 | ;; Producers (LHS) | |
264 | ;; LD_!bi | |
265 | ;; Load data from the memory (without updating the base register) and | |
266 | ;; produce the loaded data. The result is ready at MM. Because the register | |
267 | ;; port is 2R1W, two micro-operations are required if the base register | |
268 | ;; should be updated. In this case, the base register is updated by the | |
269 | ;; second micro-operation, and the updated result is ready at EX. | |
270 | ;; LMW(N, M) | |
271 | ;; There are N micro-operations within an instruction that loads multiple | |
272 | ;; words. The result produced by the M-th micro-operation is sent to | |
273 | ;; consumers. The result is ready at MM. If the base register should be | |
274 | ;; updated, an extra micro-operation is apppended to the end of the | |
275 | ;; sequence, and the result is ready at EX. | |
276 | ;; MUL, MAC | |
277 | ;; Compute data in the multiply-adder and produce the data. The result | |
278 | ;; is ready at MM. | |
279 | ;; DIV | |
280 | ;; Compute data in the divider and produce the data. The result is ready | |
281 | ;; at MM. | |
282 | ;; | |
283 | ;; Consumers (RHS) | |
284 | ;; ALU, PBSAD, PBSADA_RaRb, MUL, MAC, DIV, MMU | |
285 | ;; Require operands at EX. | |
286 | ;; ALU_SHIFT_Rb | |
287 | ;; An ALU-SHIFT instruction consists of a shift micro-operation followed | |
288 | ;; by an arithmetic micro-operation. The operand Rb is used by the first | |
289 | ;; micro-operation, and there are some latencies if data dependency occurs. | |
290 | ;; MOVD44_E | |
291 | ;; A double-word move instruction needs two micro-operations because the | |
292 | ;; reigster ports is 2R1W. The first micro-operation writes an even number | |
293 | ;; register, and the second micro-operation writes an odd number register. | |
294 | ;; Each input operand is required at EX for each micro-operation. MOVD44_E | |
295 | ;; stands for the first micro-operation. | |
296 | ;; MAC_RaRb, M2R | |
297 | ;; MAC instructions do multiplication at EX and do accumulation at MM, but | |
298 | ;; MAC instructions which operate on general purpose registers always | |
299 | ;; require operands at EX because MM stage cannot be forwarded in 2R1W mode. | |
300 | ;; ADDR_IN | |
301 | ;; If an instruction requires an address as its input operand, the address | |
302 | ;; is required at EX. | |
303 | ;; ST_bi | |
304 | ;; A post-increment store instruction requires its data at EX because MM | |
305 | ;; cannot be forwarded in 2R1W mode. | |
306 | ;; ST_!bi_RI | |
307 | ;; A store instruction with an immediate offset requires its data at EX | |
308 | ;; because MM cannot be forwarded in 2R1W mode. If the offset field is a | |
309 | ;; register (ST_!bi_RR), the instruction will be separated into two micro- | |
310 | ;; operations, and the second one requires the input operand at EX in order | |
311 | ;; to store it to the memory. | |
312 | ;; SMW(N, M) | |
313 | ;; There are N micro-operations within an instruction that stores multiple | |
314 | ;; words. Each M-th micro-operation requires its data at MM. | |
315 | ;; BR | |
316 | ;; If a branch instruction is conditional, its input data is required at EX. | |
317 | ||
318 | ;; LD_!bi, MUL, MAC | |
319 | ;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44_E, MUL, MAC_RaRb, M2R, DIV, ADDR_IN_!bi, ADDR_IN_bi_Ra, ST_bi, ST_!bi_RI, BR, MMU | |
320 | (define_bypass 2 | |
321 | "nds_n9_2r1w_load,\ | |
322 | nds_n9_2r1w_mul_fast, nds_n9_2r1w_mul_slow,\ | |
323 | nds_n9_2r1w_mac_fast, nds_n9_2r1w_mac_slow" | |
324 | "nds_n9_2r1w_alu, nds_n9_2r1w_alu_shift,\ | |
325 | nds_n9_2r1w_pbsad, nds_n9_2r1w_pbsada,\ | |
326 | nds_n9_2r1w_mul_fast, nds_n9_2r1w_mul_slow,\ | |
327 | nds_n9_2r1w_mac_fast, nds_n9_2r1w_mac_slow,\ | |
328 | nds_n9_2r1w_branch,\ | |
329 | nds_n9_2r1w_div,\ | |
330 | nds_n9_2r1w_load,nds_n9_2r1w_store,\ | |
331 | nds_n9_2r1w_load_multiple_1,nds_n9_2r1w_load_multiple_2, nds_n9_2r1w_load_multiple_3,\ | |
332 | nds_n9_2r1w_load_multiple_4,nds_n9_2r1w_load_multiple_5, nds_n9_2r1w_load_multiple_6,\ | |
333 | nds_n9_2r1w_load_multiple_7,nds_n9_2r1w_load_multiple_8, nds_n9_2r1w_load_multiple_12,\ | |
334 | nds_n9_2r1w_store_multiple_1,nds_n9_2r1w_store_multiple_2, nds_n9_2r1w_store_multiple_3,\ | |
335 | nds_n9_2r1w_store_multiple_4,nds_n9_2r1w_store_multiple_5, nds_n9_2r1w_store_multiple_6,\ | |
336 | nds_n9_2r1w_store_multiple_7,nds_n9_2r1w_store_multiple_8, nds_n9_2r1w_store_multiple_12,\ | |
337 | nds_n9_2r1w_mmu" | |
338 | "nds32_n9_2r1w_mm_to_ex_p" | |
339 | ) | |
340 | ||
341 | ;; LMW(N, N) | |
342 | ;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44_E, MUL, MAC_RaRb, M2R, DIV, ADDR_IN_!bi, ADDR_IN_bi_Ra, ST_bi, ST_!bi_RI, BR, MMU | |
343 | (define_bypass 2 | |
344 | "nds_n9_2r1w_load_multiple_1,nds_n9_2r1w_load_multiple_2, nds_n9_2r1w_load_multiple_3,\ | |
345 | nds_n9_2r1w_load_multiple_4,nds_n9_2r1w_load_multiple_5, nds_n9_2r1w_load_multiple_6,\ | |
346 | nds_n9_2r1w_load_multiple_7,nds_n9_2r1w_load_multiple_8, nds_n9_2r1w_load_multiple_12" | |
347 | "nds_n9_2r1w_alu, nds_n9_2r1w_alu_shift,\ | |
348 | nds_n9_2r1w_pbsad, nds_n9_2r1w_pbsada,\ | |
349 | nds_n9_2r1w_mul_fast, nds_n9_2r1w_mul_slow,\ | |
350 | nds_n9_2r1w_mac_fast, nds_n9_2r1w_mac_slow,\ | |
351 | nds_n9_2r1w_branch,\ | |
352 | nds_n9_2r1w_div,\ | |
353 | nds_n9_2r1w_load,nds_n9_2r1w_store,\ | |
354 | nds_n9_2r1w_load_multiple_1,nds_n9_2r1w_load_multiple_2, nds_n9_2r1w_load_multiple_3,\ | |
355 | nds_n9_2r1w_load_multiple_4,nds_n9_2r1w_load_multiple_5, nds_n9_2r1w_load_multiple_6,\ | |
356 | nds_n9_2r1w_load_multiple_7,nds_n9_2r1w_load_multiple_8, nds_n9_2r1w_load_multiple_12,\ | |
357 | nds_n9_2r1w_store_multiple_1,nds_n9_2r1w_store_multiple_2, nds_n9_2r1w_store_multiple_3,\ | |
358 | nds_n9_2r1w_store_multiple_4,nds_n9_2r1w_store_multiple_5, nds_n9_2r1w_store_multiple_6,\ | |
359 | nds_n9_2r1w_store_multiple_7,nds_n9_2r1w_store_multiple_8, nds_n9_2r1w_store_multiple_12,\ | |
360 | nds_n9_2r1w_mmu" | |
361 | "nds32_n9_last_load_to_ex_p" | |
362 | ) |