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9304f876 | 1 | /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler |
85ec4feb | 2 | Copyright (C) 2012-2018 Free Software Foundation, Inc. |
9304f876 CJW |
3 | Contributed by Andes Technology Corporation. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 3, or (at your | |
10 | option) any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
19ac960a | 21 | /* ------------------------------------------------------------------------ */ |
9304f876 | 22 | |
8fcc61f8 RS |
23 | #define IN_TARGET_CODE 1 |
24 | ||
9304f876 CJW |
25 | #include "config.h" |
26 | #include "system.h" | |
27 | #include "coretypes.h" | |
c7131fb2 | 28 | #include "backend.h" |
e11c4407 | 29 | #include "target.h" |
c7131fb2 | 30 | #include "rtl.h" |
e11c4407 | 31 | #include "tree.h" |
c4d8d050 | 32 | #include "tree-pass.h" |
314e6352 ML |
33 | #include "stringpool.h" |
34 | #include "attribs.h" | |
c7131fb2 | 35 | #include "df.h" |
4d0cdd0c | 36 | #include "memmodel.h" |
e11c4407 AM |
37 | #include "tm_p.h" |
38 | #include "optabs.h" /* For GEN_FCN. */ | |
39 | #include "regs.h" | |
40 | #include "emit-rtl.h" | |
41 | #include "recog.h" | |
42 | #include "diagnostic-core.h" | |
d8a2d370 DN |
43 | #include "stor-layout.h" |
44 | #include "varasm.h" | |
45 | #include "calls.h" | |
9304f876 | 46 | #include "output.h" |
36566b39 | 47 | #include "explow.h" |
9304f876 | 48 | #include "expr.h" |
9304f876 | 49 | #include "tm-constrs.h" |
9b2b7279 | 50 | #include "builtins.h" |
72b7e5e1 | 51 | #include "cpplib.h" |
c4d8d050 | 52 | #include "context.h" |
9304f876 | 53 | |
994c5d85 | 54 | /* This file should be included last. */ |
d58627a0 RS |
55 | #include "target-def.h" |
56 | ||
9304f876 CJW |
57 | /* ------------------------------------------------------------------------ */ |
58 | ||
59 | /* This file is divided into five parts: | |
60 | ||
61 | PART 1: Auxiliary static variable definitions and | |
62 | target hook static variable definitions. | |
63 | ||
64 | PART 2: Auxiliary static function definitions. | |
65 | ||
66 | PART 3: Implement target hook stuff definitions. | |
67 | ||
68 | PART 4: Implemet extern function definitions, | |
69 | the prototype is in nds32-protos.h. | |
70 | ||
71 | PART 5: Initialize target hook structure and definitions. */ | |
72 | ||
73 | /* ------------------------------------------------------------------------ */ | |
74 | ||
75 | /* PART 1: Auxiliary static variable definitions and | |
76 | target hook static variable definitions. */ | |
77 | ||
9304f876 CJW |
78 | /* Define intrinsic register names. |
79 | Please refer to nds32_intrinsic.h file, the index is corresponding to | |
80 | 'enum nds32_intrinsic_registers' data type values. | |
81 | NOTE that the base value starting from 1024. */ | |
82 | static const char * const nds32_intrinsic_register_names[] = | |
83 | { | |
2095a9d5 MC |
84 | "$CPU_VER", |
85 | "$ICM_CFG", | |
86 | "$DCM_CFG", | |
87 | "$MMU_CFG", | |
88 | "$MSC_CFG", | |
89 | "$MSC_CFG2", | |
90 | "$CORE_ID", | |
91 | "$FUCOP_EXIST", | |
92 | ||
93 | "$PSW", | |
94 | "$IPSW", | |
95 | "$P_IPSW", | |
96 | "$IVB", | |
97 | "$EVA", | |
98 | "$P_EVA", | |
99 | "$ITYPE", | |
100 | "$P_ITYPE", | |
101 | ||
102 | "$MERR", | |
103 | "$IPC", | |
104 | "$P_IPC", | |
105 | "$OIPC", | |
106 | "$P_P0", | |
107 | "$P_P1", | |
108 | ||
109 | "$INT_MASK", | |
110 | "$INT_MASK2", | |
111 | "$INT_MASK3", | |
112 | "$INT_PEND", | |
113 | "$INT_PEND2", | |
114 | "$INT_PEND3", | |
115 | "$SP_USR", | |
116 | "$SP_PRIV", | |
117 | "$INT_PRI", | |
118 | "$INT_PRI2", | |
119 | "$INT_PRI3", | |
120 | "$INT_PRI4", | |
121 | "$INT_CTRL", | |
122 | "$INT_TRIGGER", | |
123 | "$INT_TRIGGER2", | |
124 | "$INT_GPR_PUSH_DIS", | |
125 | ||
126 | "$MMU_CTL", | |
127 | "$L1_PPTB", | |
128 | "$TLB_VPN", | |
129 | "$TLB_DATA", | |
130 | "$TLB_MISC", | |
131 | "$VLPT_IDX", | |
132 | "$ILMB", | |
133 | "$DLMB", | |
134 | ||
135 | "$CACHE_CTL", | |
136 | "$HSMP_SADDR", | |
137 | "$HSMP_EADDR", | |
138 | "$SDZ_CTL", | |
139 | "$N12MISC_CTL", | |
140 | "$MISC_CTL", | |
141 | "$ECC_MISC", | |
142 | ||
143 | "$BPC0", | |
144 | "$BPC1", | |
145 | "$BPC2", | |
146 | "$BPC3", | |
147 | "$BPC4", | |
148 | "$BPC5", | |
149 | "$BPC6", | |
150 | "$BPC7", | |
151 | ||
152 | "$BPA0", | |
153 | "$BPA1", | |
154 | "$BPA2", | |
155 | "$BPA3", | |
156 | "$BPA4", | |
157 | "$BPA5", | |
158 | "$BPA6", | |
159 | "$BPA7", | |
160 | ||
161 | "$BPAM0", | |
162 | "$BPAM1", | |
163 | "$BPAM2", | |
164 | "$BPAM3", | |
165 | "$BPAM4", | |
166 | "$BPAM5", | |
167 | "$BPAM6", | |
168 | "$BPAM7", | |
169 | ||
170 | "$BPV0", | |
171 | "$BPV1", | |
172 | "$BPV2", | |
173 | "$BPV3", | |
174 | "$BPV4", | |
175 | "$BPV5", | |
176 | "$BPV6", | |
177 | "$BPV7", | |
178 | ||
179 | "$BPCID0", | |
180 | "$BPCID1", | |
181 | "$BPCID2", | |
182 | "$BPCID3", | |
183 | "$BPCID4", | |
184 | "$BPCID5", | |
185 | "$BPCID6", | |
186 | "$BPCID7", | |
187 | ||
188 | "$EDM_CFG", | |
189 | "$EDMSW", | |
190 | "$EDM_CTL", | |
191 | "$EDM_DTR", | |
192 | "$BPMTC", | |
193 | "$DIMBR", | |
194 | ||
195 | "$TECR0", | |
196 | "$TECR1", | |
197 | "$PFMC0", | |
198 | "$PFMC1", | |
199 | "$PFMC2", | |
200 | "$PFM_CTL", | |
201 | "$PFT_CTL", | |
202 | "$HSP_CTL", | |
203 | "$SP_BOUND", | |
204 | "$SP_BOUND_PRIV", | |
205 | "$SP_BASE", | |
206 | "$SP_BASE_PRIV", | |
207 | "$FUCOP_CTL", | |
208 | "$PRUSR_ACC_CTL", | |
209 | ||
210 | "$DMA_CFG", | |
211 | "$DMA_GCSW", | |
212 | "$DMA_CHNSEL", | |
213 | "$DMA_ACT", | |
214 | "$DMA_SETUP", | |
215 | "$DMA_ISADDR", | |
216 | "$DMA_ESADDR", | |
217 | "$DMA_TCNT", | |
218 | "$DMA_STATUS", | |
219 | "$DMA_2DSET", | |
220 | "$DMA_2DSCTL", | |
221 | "$DMA_RCNT", | |
222 | "$DMA_HSTATUS", | |
223 | ||
224 | "$PC", | |
225 | "$SP_USR1", | |
226 | "$SP_USR2", | |
227 | "$SP_USR3", | |
228 | "$SP_PRIV1", | |
229 | "$SP_PRIV2", | |
230 | "$SP_PRIV3", | |
231 | "$BG_REGION", | |
232 | "$SFCR", | |
233 | "$SIGN", | |
234 | "$ISIGN", | |
235 | "$P_ISIGN", | |
236 | "$IFC_LP", | |
237 | "$ITB" | |
9304f876 CJW |
238 | }; |
239 | ||
f1a0afe2 MC |
240 | /* Define instrinsic cctl names. */ |
241 | static const char * const nds32_cctl_names[] = | |
242 | { | |
243 | "L1D_VA_FILLCK", | |
244 | "L1D_VA_ULCK", | |
245 | "L1I_VA_FILLCK", | |
246 | "L1I_VA_ULCK", | |
247 | ||
248 | "L1D_IX_WBINVAL", | |
249 | "L1D_IX_INVAL", | |
250 | "L1D_IX_WB", | |
251 | "L1I_IX_INVAL", | |
252 | ||
253 | "L1D_VA_INVAL", | |
254 | "L1D_VA_WB", | |
255 | "L1D_VA_WBINVAL", | |
256 | "L1I_VA_INVAL", | |
257 | ||
258 | "L1D_IX_RTAG", | |
259 | "L1D_IX_RWD", | |
260 | "L1I_IX_RTAG", | |
261 | "L1I_IX_RWD", | |
262 | ||
263 | "L1D_IX_WTAG", | |
264 | "L1D_IX_WWD", | |
265 | "L1I_IX_WTAG", | |
266 | "L1I_IX_WWD" | |
267 | }; | |
5e6ae0cc | 268 | |
57aaf0cc MC |
269 | static const char * const nds32_dpref_names[] = |
270 | { | |
271 | "SRD", | |
272 | "MRD", | |
273 | "SWR", | |
274 | "MWR", | |
275 | "PTE", | |
276 | "CLWR" | |
277 | }; | |
278 | ||
5e6ae0cc CJW |
279 | /* Defining register allocation order for performance. |
280 | We want to allocate callee-saved registers after others. | |
281 | It may be used by nds32_adjust_reg_alloc_order(). */ | |
282 | static const int nds32_reg_alloc_order_for_speed[] = | |
283 | { | |
284 | 0, 1, 2, 3, 4, 5, 16, 17, | |
285 | 18, 19, 20, 21, 22, 23, 24, 25, | |
286 | 26, 27, 6, 7, 8, 9, 10, 11, | |
287 | 12, 13, 14, 15 | |
288 | }; | |
289 | ||
9304f876 CJW |
290 | /* Defining target-specific uses of __attribute__. */ |
291 | static const struct attribute_spec nds32_attribute_table[] = | |
292 | { | |
293 | /* Syntax: { name, min_len, max_len, decl_required, type_required, | |
4849deb1 JJ |
294 | function_type_required, affects_type_identity, handler, |
295 | exclude } */ | |
9304f876 CJW |
296 | |
297 | /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */ | |
4849deb1 | 298 | { "interrupt", 1, 64, false, false, false, false, NULL, NULL }, |
9304f876 | 299 | /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */ |
4849deb1 | 300 | { "exception", 1, 8, false, false, false, false, NULL, NULL }, |
9304f876 | 301 | /* Argument is user's interrupt numbers. The vector number is always 0. */ |
4849deb1 | 302 | { "reset", 1, 1, false, false, false, false, NULL, NULL }, |
9304f876 CJW |
303 | |
304 | /* The attributes describing isr nested type. */ | |
4849deb1 JJ |
305 | { "nested", 0, 0, false, false, false, false, NULL, NULL }, |
306 | { "not_nested", 0, 0, false, false, false, false, NULL, NULL }, | |
307 | { "nested_ready", 0, 0, false, false, false, false, NULL, NULL }, | |
9304f876 CJW |
308 | |
309 | /* The attributes describing isr register save scheme. */ | |
4849deb1 JJ |
310 | { "save_all", 0, 0, false, false, false, false, NULL, NULL }, |
311 | { "partial_save", 0, 0, false, false, false, false, NULL, NULL }, | |
9304f876 CJW |
312 | |
313 | /* The attributes used by reset attribute. */ | |
4849deb1 JJ |
314 | { "nmi", 1, 1, false, false, false, false, NULL, NULL }, |
315 | { "warm", 1, 1, false, false, false, false, NULL, NULL }, | |
9304f876 CJW |
316 | |
317 | /* The attribute telling no prologue/epilogue. */ | |
4849deb1 | 318 | { "naked", 0, 0, false, false, false, false, NULL, NULL }, |
9304f876 | 319 | |
85a98076 KLC |
320 | /* The attribute is used to tell this function to be ROM patch. */ |
321 | { "indirect_call",0, 0, false, false, false, false, NULL, NULL }, | |
322 | ||
54c537e6 CJW |
323 | /* FOR BACKWARD COMPATIBILITY, |
324 | this attribute also tells no prologue/epilogue. */ | |
325 | { "no_prologue", 0, 0, false, false, false, false, NULL, NULL }, | |
326 | ||
9304f876 | 327 | /* The last attribute spec is set to be NULL. */ |
4849deb1 | 328 | { NULL, 0, 0, false, false, false, false, NULL, NULL } |
9304f876 CJW |
329 | }; |
330 | ||
331 | ||
332 | /* ------------------------------------------------------------------------ */ | |
333 | ||
334 | /* PART 2: Auxiliary static function definitions. */ | |
335 | ||
336 | /* Function to save and restore machine-specific function data. */ | |
337 | static struct machine_function * | |
338 | nds32_init_machine_status (void) | |
339 | { | |
340 | struct machine_function *machine; | |
766090c2 | 341 | machine = ggc_cleared_alloc<machine_function> (); |
9304f876 | 342 | |
ca3a4a55 CJW |
343 | /* Initially assume this function does not use __builtin_eh_return. */ |
344 | machine->use_eh_return_p = 0; | |
345 | ||
9304f876 CJW |
346 | /* Initially assume this function needs prologue/epilogue. */ |
347 | machine->naked_p = 0; | |
348 | ||
349 | /* Initially assume this function does NOT use fp_as_gp optimization. */ | |
350 | machine->fp_as_gp_p = 0; | |
351 | ||
5f2a98c3 CJW |
352 | /* Initially this function is not under strictly aligned situation. */ |
353 | machine->strict_aligned_p = 0; | |
354 | ||
54c537e6 CJW |
355 | /* Initially this function has no naked and no_prologue attributes. */ |
356 | machine->attr_naked_p = 0; | |
357 | machine->attr_no_prologue_p = 0; | |
358 | ||
9304f876 CJW |
359 | return machine; |
360 | } | |
361 | ||
362 | /* Function to compute stack frame size and | |
363 | store into cfun->machine structure. */ | |
364 | static void | |
365 | nds32_compute_stack_frame (void) | |
366 | { | |
367 | int r; | |
368 | int block_size; | |
a6c7e777 | 369 | bool v3pushpop_p; |
9304f876 CJW |
370 | |
371 | /* Because nds32_compute_stack_frame() will be called from different place, | |
372 | everytime we enter this function, we have to assume this function | |
373 | needs prologue/epilogue. */ | |
374 | cfun->machine->naked_p = 0; | |
375 | ||
54c537e6 CJW |
376 | /* We need to mark whether this function has naked and no_prologue |
377 | attribute so that we can distinguish the difference if users applies | |
378 | -mret-in-naked-func option. */ | |
379 | cfun->machine->attr_naked_p | |
380 | = lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) | |
381 | ? 1 : 0; | |
382 | cfun->machine->attr_no_prologue_p | |
383 | = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) | |
384 | ? 1 : 0; | |
ca3a4a55 CJW |
385 | |
386 | /* If __builtin_eh_return is used, we better have frame pointer needed | |
387 | so that we can easily locate the stack slot of return address. */ | |
388 | if (crtl->calls_eh_return) | |
389 | { | |
390 | frame_pointer_needed = 1; | |
391 | ||
392 | /* We need to mark eh data registers that need to be saved | |
393 | in the stack. */ | |
394 | cfun->machine->eh_return_data_first_regno = EH_RETURN_DATA_REGNO (0); | |
395 | for (r = 0; EH_RETURN_DATA_REGNO (r) != INVALID_REGNUM; r++) | |
396 | cfun->machine->eh_return_data_last_regno = r; | |
397 | ||
398 | cfun->machine->eh_return_data_regs_size | |
399 | = 4 * (cfun->machine->eh_return_data_last_regno | |
400 | - cfun->machine->eh_return_data_first_regno | |
401 | + 1); | |
402 | cfun->machine->use_eh_return_p = 1; | |
403 | } | |
404 | else | |
405 | { | |
406 | /* Assigning SP_REGNUM to eh_first_regno and eh_last_regno means we | |
407 | do not need to handle __builtin_eh_return case in this function. */ | |
408 | cfun->machine->eh_return_data_first_regno = SP_REGNUM; | |
409 | cfun->machine->eh_return_data_last_regno = SP_REGNUM; | |
410 | ||
411 | cfun->machine->eh_return_data_regs_size = 0; | |
412 | cfun->machine->use_eh_return_p = 0; | |
413 | } | |
414 | ||
9304f876 | 415 | /* Get variadic arguments size to prepare pretend arguments and |
35da54a6 CJW |
416 | we will push them into stack at prologue by ourself. */ |
417 | cfun->machine->va_args_size = crtl->args.pretend_args_size; | |
418 | if (cfun->machine->va_args_size != 0) | |
419 | { | |
420 | cfun->machine->va_args_first_regno | |
8a498f99 CJW |
421 | = NDS32_GPR_ARG_FIRST_REGNUM |
422 | + NDS32_MAX_GPR_REGS_FOR_ARGS | |
423 | - (crtl->args.pretend_args_size / UNITS_PER_WORD); | |
35da54a6 | 424 | cfun->machine->va_args_last_regno |
8a498f99 | 425 | = NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS - 1; |
35da54a6 CJW |
426 | } |
427 | else | |
428 | { | |
429 | cfun->machine->va_args_first_regno = SP_REGNUM; | |
430 | cfun->machine->va_args_last_regno = SP_REGNUM; | |
431 | } | |
432 | ||
433 | /* Important: We need to make sure that varargs area is 8-byte alignment. */ | |
434 | block_size = cfun->machine->va_args_size; | |
435 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) | |
436 | { | |
437 | cfun->machine->va_args_area_padding_bytes | |
438 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; | |
439 | } | |
9304f876 CJW |
440 | |
441 | /* Get local variables, incoming variables, and temporary variables size. | |
442 | Note that we need to make sure it is 8-byte alignment because | |
443 | there may be no padding bytes if we are using LRA. */ | |
444 | cfun->machine->local_size = NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ()); | |
445 | ||
446 | /* Get outgoing arguments size. */ | |
447 | cfun->machine->out_args_size = crtl->outgoing_args_size; | |
448 | ||
449 | /* If $fp value is required to be saved on stack, it needs 4 bytes space. | |
450 | Check whether $fp is ever live. */ | |
451 | cfun->machine->fp_size = (df_regs_ever_live_p (FP_REGNUM)) ? 4 : 0; | |
452 | ||
453 | /* If $gp value is required to be saved on stack, it needs 4 bytes space. | |
454 | Check whether we are using PIC code genration. */ | |
b26fa4f9 KLC |
455 | cfun->machine->gp_size = |
456 | (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ? 4 : 0; | |
9304f876 CJW |
457 | |
458 | /* If $lp value is required to be saved on stack, it needs 4 bytes space. | |
459 | Check whether $lp is ever live. */ | |
13116651 CJW |
460 | cfun->machine->lp_size |
461 | = (flag_always_save_lp || df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0; | |
9304f876 CJW |
462 | |
463 | /* Initially there is no padding bytes. */ | |
c457f751 | 464 | cfun->machine->callee_saved_area_gpr_padding_bytes = 0; |
9304f876 CJW |
465 | |
466 | /* Calculate the bytes of saving callee-saved registers on stack. */ | |
c457f751 CJW |
467 | cfun->machine->callee_saved_gpr_regs_size = 0; |
468 | cfun->machine->callee_saved_first_gpr_regno = SP_REGNUM; | |
469 | cfun->machine->callee_saved_last_gpr_regno = SP_REGNUM; | |
e2286268 MC |
470 | cfun->machine->callee_saved_fpr_regs_size = 0; |
471 | cfun->machine->callee_saved_first_fpr_regno = SP_REGNUM; | |
472 | cfun->machine->callee_saved_last_fpr_regno = SP_REGNUM; | |
473 | ||
9304f876 CJW |
474 | /* Currently, there is no need to check $r28~$r31 |
475 | because we will save them in another way. */ | |
476 | for (r = 0; r < 28; r++) | |
477 | { | |
478 | if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) | |
479 | { | |
480 | /* Mark the first required callee-saved register | |
481 | (only need to set it once). | |
482 | If first regno == SP_REGNUM, we can tell that | |
483 | it is the first time to be here. */ | |
c457f751 CJW |
484 | if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) |
485 | cfun->machine->callee_saved_first_gpr_regno = r; | |
9304f876 | 486 | /* Mark the last required callee-saved register. */ |
c457f751 | 487 | cfun->machine->callee_saved_last_gpr_regno = r; |
9304f876 CJW |
488 | } |
489 | } | |
490 | ||
e2286268 MC |
491 | /* Recording fpu callee-saved register. */ |
492 | if (TARGET_HARD_FLOAT) | |
493 | { | |
494 | for (r = NDS32_FIRST_FPR_REGNUM; r < NDS32_LAST_FPR_REGNUM; r++) | |
495 | { | |
496 | if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) | |
497 | { | |
498 | /* Mark the first required callee-saved register. */ | |
499 | if (cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM) | |
500 | { | |
501 | /* Make first callee-saved number is even, | |
502 | bacause we use doubleword access, and this way | |
503 | promise 8-byte alignemt. */ | |
504 | if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (r)) | |
505 | cfun->machine->callee_saved_first_fpr_regno = r - 1; | |
506 | else | |
507 | cfun->machine->callee_saved_first_fpr_regno = r; | |
508 | } | |
509 | cfun->machine->callee_saved_last_fpr_regno = r; | |
510 | } | |
511 | } | |
512 | ||
513 | /* Make last callee-saved register number is odd, | |
514 | we hope callee-saved register is even. */ | |
515 | int last_fpr = cfun->machine->callee_saved_last_fpr_regno; | |
516 | if (NDS32_FPR_REGNO_OK_FOR_DOUBLE (last_fpr)) | |
517 | cfun->machine->callee_saved_last_fpr_regno++; | |
518 | } | |
519 | ||
9304f876 | 520 | /* Check if this function can omit prologue/epilogue code fragment. |
54c537e6 | 521 | If there is 'no_prologue'/'naked' attribute in this function, |
9304f876 CJW |
522 | we can set 'naked_p' flag to indicate that |
523 | we do not have to generate prologue/epilogue. | |
524 | Or, if all the following conditions succeed, | |
525 | we can set this function 'naked_p' as well: | |
526 | condition 1: first_regno == last_regno == SP_REGNUM, | |
8a498f99 CJW |
527 | which means we do not have to save |
528 | any callee-saved registers. | |
9304f876 | 529 | condition 2: Both $lp and $fp are NOT live in this function, |
8a498f99 CJW |
530 | which means we do not need to save them and there |
531 | is no outgoing size. | |
9304f876 | 532 | condition 3: There is no local_size, which means |
8a498f99 | 533 | we do not need to adjust $sp. */ |
54c537e6 CJW |
534 | if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) |
535 | || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) | |
c457f751 CJW |
536 | || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM |
537 | && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM | |
e2286268 MC |
538 | && cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM |
539 | && cfun->machine->callee_saved_last_fpr_regno == SP_REGNUM | |
9304f876 CJW |
540 | && !df_regs_ever_live_p (FP_REGNUM) |
541 | && !df_regs_ever_live_p (LP_REGNUM) | |
b26fa4f9 KLC |
542 | && cfun->machine->local_size == 0 |
543 | && !flag_pic)) | |
9304f876 | 544 | { |
2da1e7c0 | 545 | /* Set this function 'naked_p' and other functions can check this flag. |
8a498f99 CJW |
546 | Note that in nds32 port, the 'naked_p = 1' JUST means there is no |
547 | callee-saved, local size, and outgoing size. | |
548 | The varargs space and ret instruction may still present in | |
549 | the prologue/epilogue expanding. */ | |
9304f876 CJW |
550 | cfun->machine->naked_p = 1; |
551 | ||
552 | /* No need to save $fp, $gp, and $lp. | |
8a498f99 CJW |
553 | We should set these value to be zero |
554 | so that nds32_initial_elimination_offset() can work properly. */ | |
9304f876 CJW |
555 | cfun->machine->fp_size = 0; |
556 | cfun->machine->gp_size = 0; | |
557 | cfun->machine->lp_size = 0; | |
558 | ||
559 | /* If stack usage computation is required, | |
8a498f99 | 560 | we need to provide the static stack size. */ |
9304f876 CJW |
561 | if (flag_stack_usage_info) |
562 | current_function_static_stack_size = 0; | |
563 | ||
564 | /* No need to do following adjustment, return immediately. */ | |
565 | return; | |
566 | } | |
567 | ||
a6c7e777 MC |
568 | v3pushpop_p = NDS32_V3PUSH_AVAILABLE_P; |
569 | ||
9304f876 CJW |
570 | /* Adjustment for v3push instructions: |
571 | If we are using v3push (push25/pop25) instructions, | |
572 | we need to make sure Rb is $r6 and Re is | |
573 | located on $r6, $r8, $r10, or $r14. | |
574 | Some results above will be discarded and recomputed. | |
2da1e7c0 CJW |
575 | Note that it is only available under V3/V3M ISA and we |
576 | DO NOT setup following stuff for isr or variadic function. */ | |
a6c7e777 | 577 | if (v3pushpop_p) |
9304f876 CJW |
578 | { |
579 | /* Recompute: | |
8a498f99 CJW |
580 | cfun->machine->fp_size |
581 | cfun->machine->gp_size | |
582 | cfun->machine->lp_size | |
583 | cfun->machine->callee_saved_first_gpr_regno | |
584 | cfun->machine->callee_saved_last_gpr_regno */ | |
9304f876 CJW |
585 | |
586 | /* For v3push instructions, $fp, $gp, and $lp are always saved. */ | |
587 | cfun->machine->fp_size = 4; | |
588 | cfun->machine->gp_size = 4; | |
589 | cfun->machine->lp_size = 4; | |
590 | ||
591 | /* Remember to set Rb = $r6. */ | |
c457f751 | 592 | cfun->machine->callee_saved_first_gpr_regno = 6; |
9304f876 | 593 | |
c457f751 | 594 | if (cfun->machine->callee_saved_last_gpr_regno <= 6) |
9304f876 CJW |
595 | { |
596 | /* Re = $r6 */ | |
c457f751 | 597 | cfun->machine->callee_saved_last_gpr_regno = 6; |
9304f876 | 598 | } |
c457f751 | 599 | else if (cfun->machine->callee_saved_last_gpr_regno <= 8) |
9304f876 CJW |
600 | { |
601 | /* Re = $r8 */ | |
c457f751 | 602 | cfun->machine->callee_saved_last_gpr_regno = 8; |
9304f876 | 603 | } |
c457f751 | 604 | else if (cfun->machine->callee_saved_last_gpr_regno <= 10) |
9304f876 CJW |
605 | { |
606 | /* Re = $r10 */ | |
c457f751 | 607 | cfun->machine->callee_saved_last_gpr_regno = 10; |
9304f876 | 608 | } |
c457f751 | 609 | else if (cfun->machine->callee_saved_last_gpr_regno <= 14) |
9304f876 CJW |
610 | { |
611 | /* Re = $r14 */ | |
c457f751 | 612 | cfun->machine->callee_saved_last_gpr_regno = 14; |
9304f876 | 613 | } |
c457f751 | 614 | else if (cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM) |
9304f876 CJW |
615 | { |
616 | /* If last_regno is SP_REGNUM, which means | |
617 | it is never changed, so set it to Re = $r6. */ | |
c457f751 | 618 | cfun->machine->callee_saved_last_gpr_regno = 6; |
9304f876 CJW |
619 | } |
620 | else | |
621 | { | |
622 | /* The program flow should not go here. */ | |
623 | gcc_unreachable (); | |
624 | } | |
625 | } | |
626 | ||
a6c7e777 MC |
627 | int sp_adjust = cfun->machine->local_size |
628 | + cfun->machine->out_args_size | |
e2286268 MC |
629 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
630 | + cfun->machine->callee_saved_fpr_regs_size; | |
a6c7e777 MC |
631 | |
632 | if (!v3pushpop_p | |
633 | && sp_adjust == 0 | |
634 | && !frame_pointer_needed) | |
635 | { | |
636 | block_size = cfun->machine->fp_size | |
637 | + cfun->machine->gp_size | |
361292be CJW |
638 | + cfun->machine->lp_size; |
639 | ||
640 | if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) | |
641 | block_size += (4 * (cfun->machine->callee_saved_last_gpr_regno | |
642 | - cfun->machine->callee_saved_first_gpr_regno | |
643 | + 1)); | |
a6c7e777 MC |
644 | |
645 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) | |
646 | { | |
647 | /* $r14 is last callee save register. */ | |
648 | if (cfun->machine->callee_saved_last_gpr_regno | |
649 | < NDS32_LAST_CALLEE_SAVE_GPR_REGNUM) | |
650 | { | |
651 | cfun->machine->callee_saved_last_gpr_regno++; | |
652 | } | |
653 | else if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) | |
654 | { | |
655 | cfun->machine->callee_saved_first_gpr_regno | |
656 | = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; | |
657 | cfun->machine->callee_saved_last_gpr_regno | |
658 | = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; | |
659 | } | |
660 | } | |
661 | } | |
662 | ||
8a498f99 CJW |
663 | /* We have correctly set callee_saved_first_gpr_regno |
664 | and callee_saved_last_gpr_regno. | |
665 | Initially, the callee_saved_gpr_regs_size is supposed to be 0. | |
666 | As long as callee_saved_last_gpr_regno is not SP_REGNUM, | |
667 | we can update callee_saved_gpr_regs_size with new size. */ | |
c457f751 | 668 | if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) |
9304f876 CJW |
669 | { |
670 | /* Compute pushed size of callee-saved registers. */ | |
c457f751 CJW |
671 | cfun->machine->callee_saved_gpr_regs_size |
672 | = 4 * (cfun->machine->callee_saved_last_gpr_regno | |
673 | - cfun->machine->callee_saved_first_gpr_regno | |
9304f876 CJW |
674 | + 1); |
675 | } | |
676 | ||
e2286268 MC |
677 | if (TARGET_HARD_FLOAT) |
678 | { | |
679 | /* Compute size of callee svaed floating-point registers. */ | |
680 | if (cfun->machine->callee_saved_last_fpr_regno != SP_REGNUM) | |
681 | { | |
682 | cfun->machine->callee_saved_fpr_regs_size | |
683 | = 4 * (cfun->machine->callee_saved_last_fpr_regno | |
684 | - cfun->machine->callee_saved_first_fpr_regno | |
685 | + 1); | |
686 | } | |
687 | } | |
688 | ||
9304f876 | 689 | /* Important: We need to make sure that |
8a498f99 CJW |
690 | (fp_size + gp_size + lp_size + callee_saved_gpr_regs_size) |
691 | is 8-byte alignment. | |
692 | If it is not, calculate the padding bytes. */ | |
35da54a6 | 693 | block_size = cfun->machine->fp_size |
9304f876 CJW |
694 | + cfun->machine->gp_size |
695 | + cfun->machine->lp_size | |
c457f751 | 696 | + cfun->machine->callee_saved_gpr_regs_size; |
9304f876 CJW |
697 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) |
698 | { | |
c457f751 | 699 | cfun->machine->callee_saved_area_gpr_padding_bytes |
9304f876 CJW |
700 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; |
701 | } | |
702 | ||
703 | /* If stack usage computation is required, | |
704 | we need to provide the static stack size. */ | |
705 | if (flag_stack_usage_info) | |
706 | { | |
707 | current_function_static_stack_size | |
708 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) | |
709 | + cfun->machine->local_size | |
710 | + cfun->machine->out_args_size; | |
711 | } | |
712 | } | |
713 | ||
714 | /* Function to create a parallel rtx pattern | |
715 | which presents stack push multiple behavior. | |
716 | The overall concept are: | |
717 | "push registers to memory", | |
718 | "adjust stack pointer". */ | |
4e9a2848 | 719 | static void |
a6c7e777 MC |
720 | nds32_emit_stack_push_multiple (unsigned Rb, unsigned Re, |
721 | bool save_fp_p, bool save_gp_p, bool save_lp_p, | |
722 | bool vaarg_p) | |
9304f876 | 723 | { |
a6c7e777 | 724 | unsigned regno; |
9304f876 CJW |
725 | int extra_count; |
726 | int num_use_regs; | |
727 | int par_index; | |
728 | int offset; | |
729 | ||
730 | rtx reg; | |
731 | rtx mem; | |
732 | rtx push_rtx; | |
733 | rtx adjust_sp_rtx; | |
734 | rtx parallel_insn; | |
47e0e7d2 | 735 | rtx dwarf; |
9304f876 CJW |
736 | |
737 | /* We need to provide a customized rtx which contains | |
738 | necessary information for data analysis, | |
739 | so we create a parallel rtx like this: | |
740 | (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) | |
8a498f99 CJW |
741 | (reg:SI Rb)) |
742 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) | |
743 | (reg:SI Rb+1)) | |
744 | ... | |
745 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) | |
746 | (reg:SI Re)) | |
747 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) | |
748 | (reg:SI FP_REGNUM)) | |
749 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) | |
750 | (reg:SI GP_REGNUM)) | |
751 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) | |
752 | (reg:SI LP_REGNUM)) | |
753 | (set (reg:SI SP_REGNUM) | |
754 | (plus (reg:SI SP_REGNUM) (const_int -32)))]) */ | |
9304f876 CJW |
755 | |
756 | /* Calculate the number of registers that will be pushed. */ | |
757 | extra_count = 0; | |
a6c7e777 | 758 | if (save_fp_p) |
9304f876 | 759 | extra_count++; |
a6c7e777 | 760 | if (save_gp_p) |
9304f876 | 761 | extra_count++; |
a6c7e777 | 762 | if (save_lp_p) |
9304f876 CJW |
763 | extra_count++; |
764 | /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ | |
a6c7e777 | 765 | if (Rb == SP_REGNUM && Re == SP_REGNUM) |
9304f876 CJW |
766 | num_use_regs = extra_count; |
767 | else | |
a6c7e777 | 768 | num_use_regs = Re - Rb + 1 + extra_count; |
9304f876 CJW |
769 | |
770 | /* In addition to used registers, | |
771 | we need one more space for (set sp sp-x) rtx. */ | |
772 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
773 | rtvec_alloc (num_use_regs + 1)); | |
774 | par_index = 0; | |
775 | ||
776 | /* Initialize offset and start to create push behavior. */ | |
777 | offset = -(num_use_regs * 4); | |
778 | ||
779 | /* Create (set mem regX) from Rb, Rb+1 up to Re. */ | |
a6c7e777 | 780 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
781 | { |
782 | /* Rb and Re may be SP_REGNUM. | |
8a498f99 | 783 | We need to break this loop immediately. */ |
9304f876 | 784 | if (regno == SP_REGNUM) |
4e9a2848 | 785 | break; |
9304f876 CJW |
786 | |
787 | reg = gen_rtx_REG (SImode, regno); | |
788 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
789 | stack_pointer_rtx, | |
790 | offset)); | |
f7df4a84 | 791 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
792 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
793 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
794 | offset = offset + 4; | |
795 | par_index++; | |
796 | } | |
797 | ||
798 | /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */ | |
a6c7e777 | 799 | if (save_fp_p) |
9304f876 CJW |
800 | { |
801 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
802 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
803 | stack_pointer_rtx, | |
804 | offset)); | |
f7df4a84 | 805 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
806 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
807 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
808 | offset = offset + 4; | |
809 | par_index++; | |
810 | } | |
a6c7e777 | 811 | if (save_gp_p) |
9304f876 CJW |
812 | { |
813 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
814 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
815 | stack_pointer_rtx, | |
816 | offset)); | |
f7df4a84 | 817 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
818 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
819 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
820 | offset = offset + 4; | |
821 | par_index++; | |
822 | } | |
a6c7e777 | 823 | if (save_lp_p) |
9304f876 CJW |
824 | { |
825 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
826 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
827 | stack_pointer_rtx, | |
828 | offset)); | |
f7df4a84 | 829 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
830 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
831 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
832 | offset = offset + 4; | |
833 | par_index++; | |
834 | } | |
835 | ||
836 | /* Create (set sp sp-x). */ | |
837 | ||
838 | /* We need to re-calculate the offset value again for adjustment. */ | |
839 | offset = -(num_use_regs * 4); | |
840 | adjust_sp_rtx | |
f7df4a84 | 841 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
842 | plus_constant (Pmode, stack_pointer_rtx, offset)); |
843 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
844 | RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; | |
845 | ||
4e9a2848 CJW |
846 | parallel_insn = emit_insn (parallel_insn); |
847 | ||
848 | /* The insn rtx 'parallel_insn' will change frame layout. | |
849 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
850 | generate CFI (Call Frame Information) stuff. */ | |
851 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
47e0e7d2 CJW |
852 | |
853 | /* Don't use GCC's logic for CFI info if we are generate a push for VAARG | |
854 | since we will not restore those register at epilogue. */ | |
855 | if (vaarg_p) | |
856 | { | |
857 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, | |
858 | copy_rtx (adjust_sp_rtx), NULL_RTX); | |
859 | REG_NOTES (parallel_insn) = dwarf; | |
860 | } | |
9304f876 CJW |
861 | } |
862 | ||
863 | /* Function to create a parallel rtx pattern | |
864 | which presents stack pop multiple behavior. | |
865 | The overall concept are: | |
866 | "pop registers from memory", | |
867 | "adjust stack pointer". */ | |
4e9a2848 | 868 | static void |
a6c7e777 MC |
869 | nds32_emit_stack_pop_multiple (unsigned Rb, unsigned Re, |
870 | bool save_fp_p, bool save_gp_p, bool save_lp_p) | |
9304f876 | 871 | { |
a6c7e777 | 872 | unsigned regno; |
9304f876 CJW |
873 | int extra_count; |
874 | int num_use_regs; | |
875 | int par_index; | |
876 | int offset; | |
877 | ||
878 | rtx reg; | |
879 | rtx mem; | |
880 | rtx pop_rtx; | |
881 | rtx adjust_sp_rtx; | |
882 | rtx parallel_insn; | |
4e9a2848 | 883 | rtx dwarf = NULL_RTX; |
9304f876 CJW |
884 | |
885 | /* We need to provide a customized rtx which contains | |
886 | necessary information for data analysis, | |
887 | so we create a parallel rtx like this: | |
888 | (parallel [(set (reg:SI Rb) | |
8a498f99 CJW |
889 | (mem (reg:SI SP_REGNUM))) |
890 | (set (reg:SI Rb+1) | |
891 | (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) | |
892 | ... | |
893 | (set (reg:SI Re) | |
894 | (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) | |
895 | (set (reg:SI FP_REGNUM) | |
896 | (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) | |
897 | (set (reg:SI GP_REGNUM) | |
898 | (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) | |
899 | (set (reg:SI LP_REGNUM) | |
900 | (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) | |
901 | (set (reg:SI SP_REGNUM) | |
902 | (plus (reg:SI SP_REGNUM) (const_int 32)))]) */ | |
9304f876 CJW |
903 | |
904 | /* Calculate the number of registers that will be poped. */ | |
905 | extra_count = 0; | |
a6c7e777 | 906 | if (save_fp_p) |
9304f876 | 907 | extra_count++; |
a6c7e777 | 908 | if (save_gp_p) |
9304f876 | 909 | extra_count++; |
a6c7e777 | 910 | if (save_lp_p) |
9304f876 CJW |
911 | extra_count++; |
912 | /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ | |
a6c7e777 | 913 | if (Rb == SP_REGNUM && Re == SP_REGNUM) |
9304f876 CJW |
914 | num_use_regs = extra_count; |
915 | else | |
a6c7e777 | 916 | num_use_regs = Re - Rb + 1 + extra_count; |
9304f876 CJW |
917 | |
918 | /* In addition to used registers, | |
919 | we need one more space for (set sp sp+x) rtx. */ | |
920 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
921 | rtvec_alloc (num_use_regs + 1)); | |
922 | par_index = 0; | |
923 | ||
924 | /* Initialize offset and start to create pop behavior. */ | |
925 | offset = 0; | |
926 | ||
927 | /* Create (set regX mem) from Rb, Rb+1 up to Re. */ | |
a6c7e777 | 928 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
929 | { |
930 | /* Rb and Re may be SP_REGNUM. | |
8a498f99 | 931 | We need to break this loop immediately. */ |
9304f876 | 932 | if (regno == SP_REGNUM) |
4e9a2848 | 933 | break; |
9304f876 CJW |
934 | |
935 | reg = gen_rtx_REG (SImode, regno); | |
936 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
937 | stack_pointer_rtx, | |
938 | offset)); | |
f7df4a84 | 939 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
940 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
941 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
942 | offset = offset + 4; | |
943 | par_index++; | |
4e9a2848 CJW |
944 | |
945 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
946 | } |
947 | ||
948 | /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */ | |
a6c7e777 | 949 | if (save_fp_p) |
9304f876 CJW |
950 | { |
951 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
952 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
953 | stack_pointer_rtx, | |
954 | offset)); | |
f7df4a84 | 955 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
956 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
957 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
958 | offset = offset + 4; | |
959 | par_index++; | |
4e9a2848 CJW |
960 | |
961 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 | 962 | } |
a6c7e777 | 963 | if (save_gp_p) |
9304f876 CJW |
964 | { |
965 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
966 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
967 | stack_pointer_rtx, | |
968 | offset)); | |
f7df4a84 | 969 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
970 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
971 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
972 | offset = offset + 4; | |
973 | par_index++; | |
4e9a2848 CJW |
974 | |
975 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 | 976 | } |
a6c7e777 | 977 | if (save_lp_p) |
9304f876 CJW |
978 | { |
979 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
980 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
981 | stack_pointer_rtx, | |
982 | offset)); | |
f7df4a84 | 983 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
984 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
985 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
986 | offset = offset + 4; | |
987 | par_index++; | |
4e9a2848 CJW |
988 | |
989 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
990 | } |
991 | ||
992 | /* Create (set sp sp+x). */ | |
993 | ||
994 | /* The offset value is already in place. No need to re-calculate it. */ | |
995 | adjust_sp_rtx | |
f7df4a84 | 996 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
997 | plus_constant (Pmode, stack_pointer_rtx, offset)); |
998 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
9304f876 | 999 | |
4e9a2848 CJW |
1000 | /* Tell gcc we adjust SP in this insn. */ |
1001 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, copy_rtx (adjust_sp_rtx), dwarf); | |
1002 | ||
1003 | parallel_insn = emit_insn (parallel_insn); | |
1004 | ||
1005 | /* The insn rtx 'parallel_insn' will change frame layout. | |
1006 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1007 | generate CFI (Call Frame Information) stuff. */ | |
1008 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
1009 | ||
1010 | /* Add CFI info by manual. */ | |
1011 | REG_NOTES (parallel_insn) = dwarf; | |
9304f876 CJW |
1012 | } |
1013 | ||
1014 | /* Function to create a parallel rtx pattern | |
1015 | which presents stack v3push behavior. | |
1016 | The overall concept are: | |
1017 | "push registers to memory", | |
1018 | "adjust stack pointer". */ | |
88437f39 | 1019 | static void |
a6c7e777 MC |
1020 | nds32_emit_stack_v3push (unsigned Rb, |
1021 | unsigned Re, | |
1022 | unsigned imm8u) | |
9304f876 | 1023 | { |
a6c7e777 | 1024 | unsigned regno; |
9304f876 CJW |
1025 | int num_use_regs; |
1026 | int par_index; | |
1027 | int offset; | |
1028 | ||
1029 | rtx reg; | |
1030 | rtx mem; | |
1031 | rtx push_rtx; | |
1032 | rtx adjust_sp_rtx; | |
1033 | rtx parallel_insn; | |
1034 | ||
1035 | /* We need to provide a customized rtx which contains | |
1036 | necessary information for data analysis, | |
1037 | so we create a parallel rtx like this: | |
88437f39 | 1038 | (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) |
8a498f99 CJW |
1039 | (reg:SI Rb)) |
1040 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) | |
1041 | (reg:SI Rb+1)) | |
1042 | ... | |
1043 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) | |
1044 | (reg:SI Re)) | |
1045 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) | |
1046 | (reg:SI FP_REGNUM)) | |
1047 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) | |
1048 | (reg:SI GP_REGNUM)) | |
1049 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) | |
1050 | (reg:SI LP_REGNUM)) | |
1051 | (set (reg:SI SP_REGNUM) | |
1052 | (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */ | |
9304f876 CJW |
1053 | |
1054 | /* Calculate the number of registers that will be pushed. | |
1055 | Since $fp, $gp, and $lp is always pushed with v3push instruction, | |
1056 | we need to count these three registers. | |
1057 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1058 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1059 | num_use_regs = Re - Rb + 1 + 3; |
9304f876 CJW |
1060 | |
1061 | /* In addition to used registers, | |
1062 | we need one more space for (set sp sp-x-imm8u) rtx. */ | |
1063 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
1064 | rtvec_alloc (num_use_regs + 1)); | |
1065 | par_index = 0; | |
1066 | ||
1067 | /* Initialize offset and start to create push behavior. */ | |
1068 | offset = -(num_use_regs * 4); | |
1069 | ||
1070 | /* Create (set mem regX) from Rb, Rb+1 up to Re. | |
1071 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1072 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1073 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
1074 | { |
1075 | reg = gen_rtx_REG (SImode, regno); | |
1076 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1077 | stack_pointer_rtx, | |
1078 | offset)); | |
f7df4a84 | 1079 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1080 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1081 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1082 | offset = offset + 4; | |
1083 | par_index++; | |
1084 | } | |
1085 | ||
1086 | /* Create (set mem fp). */ | |
1087 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
1088 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1089 | stack_pointer_rtx, | |
1090 | offset)); | |
f7df4a84 | 1091 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1092 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1093 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1094 | offset = offset + 4; | |
1095 | par_index++; | |
1096 | /* Create (set mem gp). */ | |
1097 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
1098 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1099 | stack_pointer_rtx, | |
1100 | offset)); | |
f7df4a84 | 1101 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1102 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1103 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1104 | offset = offset + 4; | |
1105 | par_index++; | |
1106 | /* Create (set mem lp). */ | |
1107 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
1108 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1109 | stack_pointer_rtx, | |
1110 | offset)); | |
f7df4a84 | 1111 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1112 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1113 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1114 | offset = offset + 4; | |
1115 | par_index++; | |
1116 | ||
1117 | /* Create (set sp sp-x-imm8u). */ | |
1118 | ||
1119 | /* We need to re-calculate the offset value again for adjustment. */ | |
1120 | offset = -(num_use_regs * 4); | |
1121 | adjust_sp_rtx | |
f7df4a84 | 1122 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
1123 | plus_constant (Pmode, |
1124 | stack_pointer_rtx, | |
a6c7e777 | 1125 | offset - imm8u)); |
9304f876 CJW |
1126 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; |
1127 | RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; | |
1128 | ||
88437f39 CJW |
1129 | parallel_insn = emit_insn (parallel_insn); |
1130 | ||
1131 | /* The insn rtx 'parallel_insn' will change frame layout. | |
1132 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1133 | generate CFI (Call Frame Information) stuff. */ | |
1134 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
9304f876 CJW |
1135 | } |
1136 | ||
1137 | /* Function to create a parallel rtx pattern | |
1138 | which presents stack v3pop behavior. | |
1139 | The overall concept are: | |
1140 | "pop registers from memory", | |
1141 | "adjust stack pointer". */ | |
88437f39 | 1142 | static void |
a6c7e777 MC |
1143 | nds32_emit_stack_v3pop (unsigned Rb, |
1144 | unsigned Re, | |
1145 | unsigned imm8u) | |
9304f876 | 1146 | { |
a6c7e777 | 1147 | unsigned regno; |
9304f876 CJW |
1148 | int num_use_regs; |
1149 | int par_index; | |
1150 | int offset; | |
1151 | ||
1152 | rtx reg; | |
1153 | rtx mem; | |
1154 | rtx pop_rtx; | |
1155 | rtx adjust_sp_rtx; | |
1156 | rtx parallel_insn; | |
88437f39 | 1157 | rtx dwarf = NULL_RTX; |
9304f876 CJW |
1158 | |
1159 | /* We need to provide a customized rtx which contains | |
1160 | necessary information for data analysis, | |
1161 | so we create a parallel rtx like this: | |
1162 | (parallel [(set (reg:SI Rb) | |
8a498f99 CJW |
1163 | (mem (reg:SI SP_REGNUM))) |
1164 | (set (reg:SI Rb+1) | |
1165 | (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) | |
1166 | ... | |
1167 | (set (reg:SI Re) | |
1168 | (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) | |
1169 | (set (reg:SI FP_REGNUM) | |
1170 | (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) | |
1171 | (set (reg:SI GP_REGNUM) | |
1172 | (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) | |
1173 | (set (reg:SI LP_REGNUM) | |
1174 | (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) | |
1175 | (set (reg:SI SP_REGNUM) | |
1176 | (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */ | |
9304f876 CJW |
1177 | |
1178 | /* Calculate the number of registers that will be poped. | |
1179 | Since $fp, $gp, and $lp is always poped with v3pop instruction, | |
1180 | we need to count these three registers. | |
1181 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1182 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1183 | num_use_regs = Re - Rb + 1 + 3; |
9304f876 CJW |
1184 | |
1185 | /* In addition to used registers, | |
1186 | we need one more space for (set sp sp+x+imm8u) rtx. */ | |
1187 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
1188 | rtvec_alloc (num_use_regs + 1)); | |
1189 | par_index = 0; | |
1190 | ||
1191 | /* Initialize offset and start to create pop behavior. */ | |
1192 | offset = 0; | |
1193 | ||
1194 | /* Create (set regX mem) from Rb, Rb+1 up to Re. | |
1195 | Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1196 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1197 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
1198 | { |
1199 | reg = gen_rtx_REG (SImode, regno); | |
1200 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1201 | stack_pointer_rtx, | |
1202 | offset)); | |
f7df4a84 | 1203 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1204 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1205 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1206 | offset = offset + 4; | |
1207 | par_index++; | |
88437f39 CJW |
1208 | |
1209 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
1210 | } |
1211 | ||
1212 | /* Create (set fp mem). */ | |
1213 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
1214 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1215 | stack_pointer_rtx, | |
1216 | offset)); | |
f7df4a84 | 1217 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1218 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1219 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1220 | offset = offset + 4; | |
1221 | par_index++; | |
88437f39 CJW |
1222 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
1223 | ||
9304f876 CJW |
1224 | /* Create (set gp mem). */ |
1225 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
1226 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1227 | stack_pointer_rtx, | |
1228 | offset)); | |
f7df4a84 | 1229 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1230 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1231 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1232 | offset = offset + 4; | |
1233 | par_index++; | |
88437f39 CJW |
1234 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
1235 | ||
9304f876 CJW |
1236 | /* Create (set lp mem ). */ |
1237 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
1238 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1239 | stack_pointer_rtx, | |
1240 | offset)); | |
f7df4a84 | 1241 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1242 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1243 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1244 | offset = offset + 4; | |
1245 | par_index++; | |
88437f39 | 1246 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
9304f876 CJW |
1247 | |
1248 | /* Create (set sp sp+x+imm8u). */ | |
1249 | ||
1250 | /* The offset value is already in place. No need to re-calculate it. */ | |
1251 | adjust_sp_rtx | |
f7df4a84 | 1252 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
1253 | plus_constant (Pmode, |
1254 | stack_pointer_rtx, | |
a6c7e777 | 1255 | offset + imm8u)); |
9304f876 | 1256 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; |
9304f876 | 1257 | |
a6c7e777 MC |
1258 | if (frame_pointer_needed) |
1259 | { | |
1260 | /* (expr_list:REG_CFA_DEF_CFA (plus:SI (reg/f:SI $sp) | |
1261 | (const_int 0)) | |
1262 | mean reset frame pointer to $sp and reset to offset 0. */ | |
1263 | rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
1264 | const0_rtx); | |
1265 | dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); | |
1266 | } | |
1267 | else | |
1268 | { | |
1269 | /* Tell gcc we adjust SP in this insn. */ | |
1270 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, | |
1271 | copy_rtx (adjust_sp_rtx), dwarf); | |
1272 | } | |
88437f39 CJW |
1273 | |
1274 | parallel_insn = emit_insn (parallel_insn); | |
1275 | ||
1276 | /* The insn rtx 'parallel_insn' will change frame layout. | |
1277 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1278 | generate CFI (Call Frame Information) stuff. */ | |
1279 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
1280 | ||
1281 | /* Add CFI info by manual. */ | |
1282 | REG_NOTES (parallel_insn) = dwarf; | |
9304f876 CJW |
1283 | } |
1284 | ||
b26fa4f9 KLC |
1285 | static void |
1286 | nds32_emit_load_gp (void) | |
1287 | { | |
1288 | rtx got_symbol, pat; | |
1289 | ||
1290 | /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ | |
1291 | emit_insn (gen_blockage ()); | |
1292 | ||
1293 | got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
1294 | /* sethi $gp, _GLOBAL_OFFSET_TABLE_ -8 */ | |
1295 | pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); | |
1296 | pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-8))); | |
1297 | emit_insn (gen_sethi (pic_offset_table_rtx,pat)); | |
1298 | ||
1299 | /* ori $gp, $gp, _GLOBAL_OFFSET_TABLE_ -4 */ | |
1300 | pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); | |
1301 | pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-4))); | |
1302 | emit_insn (gen_lo_sum (pic_offset_table_rtx, pic_offset_table_rtx, pat)); | |
1303 | ||
1304 | /* add5.pc $gp */ | |
1305 | emit_insn (gen_add_pc (pic_offset_table_rtx, pic_offset_table_rtx)); | |
1306 | ||
1307 | /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ | |
1308 | emit_insn (gen_blockage ()); | |
1309 | } | |
1310 | ||
9304f876 CJW |
1311 | /* Function that may creates more instructions |
1312 | for large value on adjusting stack pointer. | |
1313 | ||
1314 | In nds32 target, 'addi' can be used for stack pointer | |
1315 | adjustment in prologue/epilogue stage. | |
1316 | However, sometimes there are too many local variables so that | |
1317 | the adjustment value is not able to be fit in the 'addi' instruction. | |
1318 | One solution is to move value into a register | |
1319 | and then use 'add' instruction. | |
a6c7e777 MC |
1320 | In practice, we use TA_REGNUM ($r15) to accomplish this purpose. */ |
1321 | static void | |
1322 | nds32_emit_adjust_frame (rtx to_reg, rtx from_reg, int adjust_value) | |
9304f876 | 1323 | { |
9304f876 | 1324 | rtx tmp_reg; |
a6c7e777 MC |
1325 | rtx frame_adjust_insn; |
1326 | rtx adjust_value_rtx = GEN_INT (adjust_value); | |
9304f876 | 1327 | |
a6c7e777 MC |
1328 | if (adjust_value == 0) |
1329 | return; | |
1330 | ||
1331 | if (!satisfies_constraint_Is15 (adjust_value_rtx)) | |
9304f876 CJW |
1332 | { |
1333 | /* The value is not able to fit in single addi instruction. | |
8a498f99 CJW |
1334 | Create more instructions of moving value into a register |
1335 | and then add stack pointer with it. */ | |
9304f876 CJW |
1336 | |
1337 | /* $r15 is going to be temporary register to hold the value. */ | |
1338 | tmp_reg = gen_rtx_REG (SImode, TA_REGNUM); | |
1339 | ||
1340 | /* Create one more instruction to move value | |
8a498f99 | 1341 | into the temporary register. */ |
a6c7e777 | 1342 | emit_move_insn (tmp_reg, adjust_value_rtx); |
9304f876 CJW |
1343 | |
1344 | /* Create new 'add' rtx. */ | |
a6c7e777 MC |
1345 | frame_adjust_insn = gen_addsi3 (to_reg, |
1346 | from_reg, | |
1347 | tmp_reg); | |
9304f876 | 1348 | /* Emit rtx into insn list and receive its transformed insn rtx. */ |
a6c7e777 | 1349 | frame_adjust_insn = emit_insn (frame_adjust_insn); |
9304f876 | 1350 | |
a6c7e777 MC |
1351 | /* Because (tmp_reg <- full_value) may be split into two |
1352 | rtl patterns, we can not set its RTX_FRAME_RELATED_P. | |
1353 | We need to construct another (sp <- sp + full_value) | |
1354 | and then insert it into sp_adjust_insn's reg note to | |
1355 | represent a frame related expression. | |
1356 | GCC knows how to refer it and output debug information. */ | |
9304f876 | 1357 | |
a6c7e777 MC |
1358 | rtx plus_rtx; |
1359 | rtx set_rtx; | |
9304f876 | 1360 | |
a6c7e777 MC |
1361 | plus_rtx = plus_constant (Pmode, from_reg, adjust_value); |
1362 | set_rtx = gen_rtx_SET (to_reg, plus_rtx); | |
1363 | add_reg_note (frame_adjust_insn, REG_FRAME_RELATED_EXPR, set_rtx); | |
9304f876 CJW |
1364 | } |
1365 | else | |
1366 | { | |
a6c7e777 MC |
1367 | /* Generate sp adjustment instruction if and only if sp_adjust != 0. */ |
1368 | frame_adjust_insn = gen_addsi3 (to_reg, | |
1369 | from_reg, | |
1370 | adjust_value_rtx); | |
1371 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
1372 | frame_adjust_insn = emit_insn (frame_adjust_insn); | |
9304f876 | 1373 | } |
a6c7e777 MC |
1374 | |
1375 | /* The insn rtx 'sp_adjust_insn' will change frame layout. | |
1376 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1377 | generate CFI (Call Frame Information) stuff. */ | |
1378 | RTX_FRAME_RELATED_P (frame_adjust_insn) = 1; | |
9304f876 CJW |
1379 | } |
1380 | ||
1381 | /* Return true if MODE/TYPE need double word alignment. */ | |
1382 | static bool | |
ef4bddc2 | 1383 | nds32_needs_double_word_align (machine_mode mode, const_tree type) |
9304f876 CJW |
1384 | { |
1385 | unsigned int align; | |
1386 | ||
634bdae9 CJW |
1387 | /* Pick up the alignment according to the mode or type. */ |
1388 | align = NDS32_MODE_TYPE_ALIGN (mode, type); | |
9304f876 CJW |
1389 | |
1390 | return (align > PARM_BOUNDARY); | |
1391 | } | |
1392 | ||
1393 | /* Return true if FUNC is a naked function. */ | |
2140297c | 1394 | bool |
810f736f | 1395 | nds32_naked_function_p (tree func) |
9304f876 | 1396 | { |
54c537e6 CJW |
1397 | /* FOR BACKWARD COMPATIBILITY, |
1398 | we need to support 'no_prologue' attribute as well. */ | |
1399 | tree t_naked; | |
1400 | tree t_no_prologue; | |
9304f876 CJW |
1401 | |
1402 | if (TREE_CODE (func) != FUNCTION_DECL) | |
1403 | abort (); | |
1404 | ||
54c537e6 CJW |
1405 | /* We have to use lookup_attribute() to check attributes. |
1406 | Because attr_naked_p and attr_no_prologue_p are set in | |
1407 | nds32_compute_stack_frame() and the function has not been | |
1408 | invoked yet. */ | |
1409 | t_naked = lookup_attribute ("naked", DECL_ATTRIBUTES (func)); | |
1410 | t_no_prologue = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (func)); | |
9304f876 | 1411 | |
54c537e6 | 1412 | return ((t_naked != NULL_TREE) || (t_no_prologue != NULL_TREE)); |
9304f876 CJW |
1413 | } |
1414 | ||
c411e9aa SC |
1415 | /* Function that determine whether a load postincrement is a good thing to use |
1416 | for a given mode. */ | |
1417 | bool | |
1418 | nds32_use_load_post_increment (machine_mode mode) | |
1419 | { | |
1420 | return (GET_MODE_SIZE (mode) <= GET_MODE_SIZE(E_DImode)); | |
1421 | } | |
1422 | ||
9304f876 CJW |
1423 | /* Function that check if 'X' is a valid address register. |
1424 | The variable 'STRICT' is very important to | |
1425 | make decision for register number. | |
1426 | ||
1427 | STRICT : true | |
1428 | => We are in reload pass or after reload pass. | |
8a498f99 | 1429 | The register number should be strictly limited in general registers. |
9304f876 CJW |
1430 | |
1431 | STRICT : false | |
1432 | => Before reload pass, we are free to use any register number. */ | |
1433 | static bool | |
1434 | nds32_address_register_rtx_p (rtx x, bool strict) | |
1435 | { | |
1436 | int regno; | |
1437 | ||
1438 | if (GET_CODE (x) != REG) | |
1439 | return false; | |
1440 | ||
1441 | regno = REGNO (x); | |
1442 | ||
1443 | if (strict) | |
1444 | return REGNO_OK_FOR_BASE_P (regno); | |
1445 | else | |
1446 | return true; | |
1447 | } | |
1448 | ||
1449 | /* Function that check if 'INDEX' is valid to be a index rtx for address. | |
1450 | ||
1451 | OUTER_MODE : Machine mode of outer address rtx. | |
8a498f99 | 1452 | INDEX : Check if this rtx is valid to be a index for address. |
9304f876 CJW |
1453 | STRICT : If it is true, we are in reload pass or after reload pass. */ |
1454 | static bool | |
ef4bddc2 | 1455 | nds32_legitimate_index_p (machine_mode outer_mode, |
9304f876 CJW |
1456 | rtx index, |
1457 | bool strict) | |
1458 | { | |
1459 | int regno; | |
1460 | rtx op0; | |
1461 | rtx op1; | |
1462 | ||
1463 | switch (GET_CODE (index)) | |
1464 | { | |
1465 | case REG: | |
1466 | regno = REGNO (index); | |
1467 | /* If we are in reload pass or after reload pass, | |
8a498f99 | 1468 | we need to limit it to general register. */ |
9304f876 CJW |
1469 | if (strict) |
1470 | return REGNO_OK_FOR_INDEX_P (regno); | |
1471 | else | |
1472 | return true; | |
1473 | ||
1474 | case CONST_INT: | |
1475 | /* The alignment of the integer value is determined by 'outer_mode'. */ | |
e2286268 | 1476 | switch (GET_MODE_SIZE (outer_mode)) |
9304f876 | 1477 | { |
e2286268 | 1478 | case 1: |
9304f876 | 1479 | /* Further check if the value is legal for the 'outer_mode'. */ |
e2286268 MC |
1480 | if (satisfies_constraint_Is15 (index)) |
1481 | return true; | |
1482 | break; | |
9304f876 | 1483 | |
e2286268 | 1484 | case 2: |
9304f876 | 1485 | /* Further check if the value is legal for the 'outer_mode'. */ |
e2286268 MC |
1486 | if (satisfies_constraint_Is16 (index)) |
1487 | { | |
5f2a98c3 CJW |
1488 | /* If it is not under strictly aligned situation, |
1489 | we can return true without checking alignment. */ | |
1490 | if (!cfun->machine->strict_aligned_p) | |
1491 | return true; | |
e2286268 | 1492 | /* Make sure address is half word alignment. */ |
5f2a98c3 | 1493 | else if (NDS32_HALF_WORD_ALIGN_P (INTVAL (index))) |
e2286268 MC |
1494 | return true; |
1495 | } | |
1496 | break; | |
9304f876 | 1497 | |
e2286268 | 1498 | case 4: |
9304f876 | 1499 | /* Further check if the value is legal for the 'outer_mode'. */ |
e2286268 MC |
1500 | if (satisfies_constraint_Is17 (index)) |
1501 | { | |
1502 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) | |
1503 | { | |
1504 | if (!satisfies_constraint_Is14 (index)) | |
1505 | return false; | |
1506 | } | |
1507 | ||
5f2a98c3 CJW |
1508 | /* If it is not under strictly aligned situation, |
1509 | we can return true without checking alignment. */ | |
1510 | if (!cfun->machine->strict_aligned_p) | |
1511 | return true; | |
e2286268 | 1512 | /* Make sure address is word alignment. */ |
5f2a98c3 | 1513 | else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) |
e2286268 MC |
1514 | return true; |
1515 | } | |
1516 | break; | |
9304f876 | 1517 | |
e2286268 MC |
1518 | case 8: |
1519 | if (satisfies_constraint_Is17 (gen_int_mode (INTVAL (index) + 4, | |
1520 | SImode))) | |
1521 | { | |
1522 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) | |
1523 | { | |
1524 | if (!satisfies_constraint_Is14 (index)) | |
1525 | return false; | |
1526 | } | |
1527 | ||
5f2a98c3 CJW |
1528 | /* If it is not under strictly aligned situation, |
1529 | we can return true without checking alignment. */ | |
1530 | if (!cfun->machine->strict_aligned_p) | |
1531 | return true; | |
e2286268 MC |
1532 | /* Make sure address is word alignment. |
1533 | Currently we do not have 64-bit load/store yet, | |
1534 | so we will use two 32-bit load/store instructions to do | |
1535 | memory access and they are single word alignment. */ | |
5f2a98c3 | 1536 | else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) |
e2286268 MC |
1537 | return true; |
1538 | } | |
1539 | break; | |
9304f876 | 1540 | |
e2286268 MC |
1541 | default: |
1542 | return false; | |
9304f876 CJW |
1543 | } |
1544 | ||
1545 | return false; | |
1546 | ||
1547 | case MULT: | |
1548 | op0 = XEXP (index, 0); | |
1549 | op1 = XEXP (index, 1); | |
1550 | ||
1551 | if (REG_P (op0) && CONST_INT_P (op1)) | |
1552 | { | |
1553 | int multiplier; | |
1554 | multiplier = INTVAL (op1); | |
1555 | ||
f62a2af5 CJW |
1556 | /* We only allow (mult reg const_int_1), (mult reg const_int_2), |
1557 | (mult reg const_int_4) or (mult reg const_int_8). */ | |
1558 | if (multiplier != 1 && multiplier != 2 | |
1559 | && multiplier != 4 && multiplier != 8) | |
9304f876 CJW |
1560 | return false; |
1561 | ||
1562 | regno = REGNO (op0); | |
1563 | /* Limit it in general registers if we are | |
1564 | in reload pass or after reload pass. */ | |
1565 | if(strict) | |
1566 | return REGNO_OK_FOR_INDEX_P (regno); | |
1567 | else | |
1568 | return true; | |
1569 | } | |
1570 | ||
1571 | return false; | |
1572 | ||
1573 | case ASHIFT: | |
1574 | op0 = XEXP (index, 0); | |
1575 | op1 = XEXP (index, 1); | |
1576 | ||
1577 | if (REG_P (op0) && CONST_INT_P (op1)) | |
1578 | { | |
1579 | int sv; | |
1580 | /* op1 is already the sv value for use to do left shift. */ | |
1581 | sv = INTVAL (op1); | |
1582 | ||
1583 | /* We only allow (ashift reg const_int_0) | |
f62a2af5 CJW |
1584 | or (ashift reg const_int_1) or (ashift reg const_int_2) or |
1585 | (ashift reg const_int_3). */ | |
1586 | if (sv != 0 && sv != 1 && sv !=2 && sv != 3) | |
9304f876 CJW |
1587 | return false; |
1588 | ||
1589 | regno = REGNO (op0); | |
1590 | /* Limit it in general registers if we are | |
1591 | in reload pass or after reload pass. */ | |
1592 | if(strict) | |
1593 | return REGNO_OK_FOR_INDEX_P (regno); | |
1594 | else | |
1595 | return true; | |
1596 | } | |
1597 | ||
1598 | return false; | |
1599 | ||
1600 | default: | |
1601 | return false; | |
1602 | } | |
1603 | } | |
1604 | ||
c4d8d050 CJW |
1605 | static void |
1606 | nds32_register_pass ( | |
1607 | rtl_opt_pass *(*make_pass_func) (gcc::context *), | |
1608 | enum pass_positioning_ops pass_pos, | |
1609 | const char *ref_pass_name) | |
1610 | { | |
1611 | opt_pass *new_opt_pass = make_pass_func (g); | |
1612 | ||
1613 | struct register_pass_info insert_pass = | |
1614 | { | |
1615 | new_opt_pass, /* pass */ | |
1616 | ref_pass_name, /* reference_pass_name */ | |
1617 | 1, /* ref_pass_instance_number */ | |
1618 | pass_pos /* po_op */ | |
1619 | }; | |
1620 | ||
1621 | register_pass (&insert_pass); | |
1622 | } | |
1623 | ||
1624 | /* This function is called from nds32_option_override (). | |
1625 | All new passes should be registered here. */ | |
1626 | static void | |
1627 | nds32_register_passes (void) | |
1628 | { | |
2140297c CJW |
1629 | nds32_register_pass ( |
1630 | make_pass_nds32_fp_as_gp, | |
1631 | PASS_POS_INSERT_BEFORE, | |
1632 | "ira"); | |
1633 | ||
c4d8d050 CJW |
1634 | nds32_register_pass ( |
1635 | make_pass_nds32_relax_opt, | |
1636 | PASS_POS_INSERT_AFTER, | |
1637 | "mach"); | |
1638 | } | |
1639 | ||
9304f876 CJW |
1640 | /* ------------------------------------------------------------------------ */ |
1641 | ||
1642 | /* PART 3: Implement target hook stuff definitions. */ | |
e2286268 MC |
1643 | \f |
1644 | ||
a5876228 CJW |
1645 | /* Computing the Length of an Insn. |
1646 | Modifies the length assigned to instruction INSN. | |
1647 | LEN is the initially computed length of the insn. */ | |
1648 | int | |
1649 | nds32_adjust_insn_length (rtx_insn *insn, int length) | |
1650 | { | |
1651 | int adjust_value = 0; | |
1652 | switch (recog_memoized (insn)) | |
1653 | { | |
1654 | case CODE_FOR_call_internal: | |
1655 | case CODE_FOR_call_value_internal: | |
1656 | { | |
43fa41c1 CJW |
1657 | if (NDS32_ALIGN_P ()) |
1658 | { | |
1659 | rtx_insn *next_insn = next_active_insn (insn); | |
1660 | if (next_insn && get_attr_length (next_insn) != 2) | |
1661 | adjust_value += 2; | |
1662 | } | |
a5876228 CJW |
1663 | /* We need insert a nop after a noretun function call |
1664 | to prevent software breakpoint corrupt the next function. */ | |
1665 | if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
1666 | { | |
1667 | if (TARGET_16_BIT) | |
1668 | adjust_value += 2; | |
1669 | else | |
1670 | adjust_value += 4; | |
1671 | } | |
1672 | } | |
1673 | return length + adjust_value; | |
1674 | ||
1675 | default: | |
1676 | return length; | |
1677 | } | |
1678 | } | |
1679 | ||
5f2a98c3 CJW |
1680 | /* Storage Layout. */ |
1681 | ||
1682 | /* This function will be called just before expansion into rtl. */ | |
1683 | static void | |
1684 | nds32_expand_to_rtl_hook (void) | |
1685 | { | |
1686 | /* We need to set strictly aligned situation. | |
1687 | After that, the memory address checking in nds32_legitimate_address_p() | |
1688 | will take alignment offset into consideration so that it will not create | |
1689 | unaligned [base + offset] access during the rtl optimization. */ | |
1690 | cfun->machine->strict_aligned_p = 1; | |
1691 | } | |
1692 | ||
1693 | \f | |
e2286268 MC |
1694 | /* Register Usage. */ |
1695 | ||
1696 | static void | |
1697 | nds32_conditional_register_usage (void) | |
1698 | { | |
1699 | int regno; | |
1700 | ||
1701 | if (TARGET_HARD_FLOAT) | |
1702 | { | |
1703 | for (regno = NDS32_FIRST_FPR_REGNUM; | |
1704 | regno <= NDS32_LAST_FPR_REGNUM; regno++) | |
1705 | { | |
1706 | fixed_regs[regno] = 0; | |
1707 | if (regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS) | |
1708 | call_used_regs[regno] = 1; | |
1709 | else if (regno >= NDS32_FIRST_FPR_REGNUM + 22 | |
1710 | && regno < NDS32_FIRST_FPR_REGNUM + 48) | |
1711 | call_used_regs[regno] = 1; | |
1712 | else | |
1713 | call_used_regs[regno] = 0; | |
1714 | } | |
1715 | } | |
1716 | else if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
1717 | { | |
1718 | for (regno = NDS32_FIRST_FPR_REGNUM; | |
1719 | regno <= NDS32_LAST_FPR_REGNUM; | |
1720 | regno++) | |
1721 | fixed_regs[regno] = 0; | |
1722 | } | |
1723 | } | |
1724 | ||
9304f876 CJW |
1725 | \f |
1726 | /* Register Classes. */ | |
1727 | ||
1728 | static unsigned char | |
1729 | nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED, | |
ef4bddc2 | 1730 | machine_mode mode) |
9304f876 CJW |
1731 | { |
1732 | /* Return the maximum number of consecutive registers | |
1733 | needed to represent "mode" in a register of "rclass". */ | |
1734 | return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); | |
1735 | } | |
1736 | ||
1737 | static int | |
1738 | nds32_register_priority (int hard_regno) | |
1739 | { | |
1740 | /* Encourage to use r0-r7 for LRA when optimize for size. */ | |
6a5a7ee3 CJW |
1741 | if (optimize_size) |
1742 | { | |
1743 | if (hard_regno < 8) | |
1744 | return 4; | |
1745 | else if (hard_regno < 16) | |
1746 | return 3; | |
1747 | else if (hard_regno < 28) | |
1748 | return 2; | |
1749 | else | |
1750 | return 1; | |
1751 | } | |
1752 | else | |
1753 | { | |
1754 | if (hard_regno > 27) | |
1755 | return 1; | |
1756 | else | |
1757 | return 4; | |
1758 | } | |
9304f876 CJW |
1759 | } |
1760 | ||
e2286268 MC |
1761 | static bool |
1762 | nds32_can_change_mode_class (machine_mode from, | |
1763 | machine_mode to, | |
1764 | reg_class_t rclass) | |
1765 | { | |
1766 | /* Don't spill double-precision register to two singal-precision | |
1767 | registers */ | |
1768 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
1769 | && GET_MODE_SIZE (from) != GET_MODE_SIZE (to)) | |
1770 | { | |
1771 | return !reg_classes_intersect_p (rclass, FP_REGS); | |
1772 | } | |
1773 | ||
1774 | return true; | |
1775 | } | |
1776 | ||
9304f876 CJW |
1777 | \f |
1778 | /* Stack Layout and Calling Conventions. */ | |
1779 | ||
1780 | /* There are three kinds of pointer concepts using in GCC compiler: | |
1781 | ||
1782 | frame pointer: A pointer to the first location of local variables. | |
1783 | stack pointer: A pointer to the top of a stack frame. | |
1784 | argument pointer: A pointer to the incoming arguments. | |
1785 | ||
1786 | In nds32 target calling convention, we are using 8-byte alignment. | |
1787 | Besides, we would like to have each stack frame of a function includes: | |
1788 | ||
1789 | [Block A] | |
1790 | 1. previous hard frame pointer | |
1791 | 2. return address | |
1792 | 3. callee-saved registers | |
1793 | 4. <padding bytes> (we will calculte in nds32_compute_stack_frame() | |
8a498f99 CJW |
1794 | and save it at |
1795 | cfun->machine->callee_saved_area_padding_bytes) | |
9304f876 CJW |
1796 | |
1797 | [Block B] | |
1798 | 1. local variables | |
1799 | 2. spilling location | |
1800 | 3. <padding bytes> (it will be calculated by GCC itself) | |
1801 | 4. incoming arguments | |
1802 | 5. <padding bytes> (it will be calculated by GCC itself) | |
1803 | ||
1804 | [Block C] | |
1805 | 1. <padding bytes> (it will be calculated by GCC itself) | |
1806 | 2. outgoing arguments | |
1807 | ||
1808 | We 'wrap' these blocks together with | |
1809 | hard frame pointer ($r28) and stack pointer ($r31). | |
1810 | By applying the basic frame/stack/argument pointers concept, | |
1811 | the layout of a stack frame shoule be like this: | |
1812 | ||
8a498f99 | 1813 | | | |
9304f876 | 1814 | old stack pointer -> ---- |
8a498f99 CJW |
1815 | | | \ |
1816 | | | saved arguments for | |
1817 | | | vararg functions | |
1818 | | | / | |
9304f876 CJW |
1819 | hard frame pointer -> -- |
1820 | & argument pointer | | \ | |
8a498f99 CJW |
1821 | | | previous hardware frame pointer |
1822 | | | return address | |
1823 | | | callee-saved registers | |
1824 | | | / | |
1825 | frame pointer -> -- | |
1826 | | | \ | |
1827 | | | local variables | |
1828 | | | and incoming arguments | |
1829 | | | / | |
1830 | -- | |
1831 | | | \ | |
1832 | | | outgoing | |
1833 | | | arguments | |
1834 | | | / | |
1835 | stack pointer -> ---- | |
9304f876 CJW |
1836 | |
1837 | $SFP and $AP are used to represent frame pointer and arguments pointer, | |
1838 | which will be both eliminated as hard frame pointer. */ | |
1839 | ||
1840 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
1841 | ||
19ac960a CJW |
1842 | static bool |
1843 | nds32_can_eliminate (const int from_reg, const int to_reg) | |
9304f876 CJW |
1844 | { |
1845 | if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
1846 | return true; | |
1847 | ||
1848 | if (from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) | |
1849 | return true; | |
1850 | ||
1851 | if (from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
1852 | return true; | |
1853 | ||
1854 | if (from_reg == FRAME_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) | |
1855 | return true; | |
1856 | ||
1857 | return false; | |
1858 | } | |
1859 | ||
1860 | /* -- Passing Arguments in Registers. */ | |
1861 | ||
1862 | static rtx | |
ef4bddc2 | 1863 | nds32_function_arg (cumulative_args_t ca, machine_mode mode, |
9304f876 CJW |
1864 | const_tree type, bool named) |
1865 | { | |
7f6cd86b | 1866 | unsigned int regno; |
9304f876 CJW |
1867 | CUMULATIVE_ARGS *cum = get_cumulative_args (ca); |
1868 | ||
1869 | /* The last time this hook is called, | |
1870 | it is called with MODE == VOIDmode. */ | |
1871 | if (mode == VOIDmode) | |
1872 | return NULL_RTX; | |
1873 | ||
7f6cd86b | 1874 | /* For nameless arguments, we need to take care it individually. */ |
9304f876 | 1875 | if (!named) |
9304f876 | 1876 | { |
7f6cd86b | 1877 | /* If we are under hard float abi, we have arguments passed on the |
8a498f99 | 1878 | stack and all situation can be handled by GCC itself. */ |
7f6cd86b CJW |
1879 | if (TARGET_HARD_FLOAT) |
1880 | return NULL_RTX; | |
1881 | ||
1882 | if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) | |
1883 | { | |
1884 | /* If we still have enough registers to pass argument, pick up | |
1885 | next available register number. */ | |
1886 | regno | |
1887 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1888 | return gen_rtx_REG (mode, regno); | |
1889 | } | |
634bdae9 | 1890 | |
9304f876 | 1891 | /* No register available, return NULL_RTX. |
8a498f99 | 1892 | The compiler will use stack to pass argument instead. */ |
9304f876 CJW |
1893 | return NULL_RTX; |
1894 | } | |
7f6cd86b CJW |
1895 | |
1896 | /* The following is to handle named argument. | |
1897 | Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT | |
1898 | are different. */ | |
1899 | if (TARGET_HARD_FLOAT) | |
1900 | { | |
e2286268 MC |
1901 | /* For TARGET_HARD_FLOAT calling convention, we use GPR and FPR |
1902 | to pass argument. We have to further check TYPE and MODE so | |
1903 | that we can determine which kind of register we shall use. */ | |
1904 | ||
1905 | /* Note that we need to pass argument entirely in registers under | |
1906 | hard float abi. */ | |
1907 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1908 | && NDS32_ARG_ENTIRE_IN_FPR_REG_P (cum->fpr_offset, mode, type)) | |
1909 | { | |
1910 | /* Pick up the next available FPR register number. */ | |
1911 | regno | |
1912 | = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type); | |
1913 | return gen_rtx_REG (mode, regno); | |
1914 | } | |
1915 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
1916 | && NDS32_ARG_ENTIRE_IN_GPR_REG_P (cum->gpr_offset, mode, type)) | |
1917 | { | |
1918 | /* Pick up the next available GPR register number. */ | |
1919 | regno | |
1920 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1921 | return gen_rtx_REG (mode, regno); | |
1922 | } | |
7f6cd86b CJW |
1923 | } |
1924 | else | |
1925 | { | |
1926 | /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass | |
8a498f99 CJW |
1927 | argument. Since we allow to pass argument partially in registers, |
1928 | we can just return it if there are still registers available. */ | |
7f6cd86b CJW |
1929 | if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) |
1930 | { | |
1931 | /* Pick up the next available register number. */ | |
1932 | regno | |
1933 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1934 | return gen_rtx_REG (mode, regno); | |
1935 | } | |
1936 | ||
1937 | } | |
1938 | ||
1939 | /* No register available, return NULL_RTX. | |
1940 | The compiler will use stack to pass argument instead. */ | |
1941 | return NULL_RTX; | |
9304f876 CJW |
1942 | } |
1943 | ||
d40f3c40 | 1944 | static bool |
ef4bddc2 | 1945 | nds32_must_pass_in_stack (machine_mode mode, const_tree type) |
d40f3c40 CJW |
1946 | { |
1947 | /* Return true if a type must be passed in memory. | |
1948 | If it is NOT using hard float abi, small aggregates can be | |
1949 | passed in a register even we are calling a variadic function. | |
1950 | So there is no need to take padding into consideration. */ | |
1951 | if (TARGET_HARD_FLOAT) | |
1952 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
1953 | else | |
1954 | return must_pass_in_stack_var_size (mode, type); | |
1955 | } | |
1956 | ||
650fc469 | 1957 | static int |
ef4bddc2 | 1958 | nds32_arg_partial_bytes (cumulative_args_t ca, machine_mode mode, |
650fc469 CJW |
1959 | tree type, bool named ATTRIBUTE_UNUSED) |
1960 | { | |
1961 | /* Returns the number of bytes at the beginning of an argument that | |
1962 | must be put in registers. The value must be zero for arguments that are | |
1963 | passed entirely in registers or that are entirely pushed on the stack. | |
1964 | Besides, TARGET_FUNCTION_ARG for these arguments should return the | |
1965 | first register to be used by the caller for this argument. */ | |
1966 | unsigned int needed_reg_count; | |
1967 | unsigned int remaining_reg_count; | |
1968 | CUMULATIVE_ARGS *cum; | |
1969 | ||
1970 | cum = get_cumulative_args (ca); | |
1971 | ||
1972 | /* Under hard float abi, we better have argument entirely passed in | |
1973 | registers or pushed on the stack so that we can reduce the complexity | |
1974 | of dealing with cum->gpr_offset and cum->fpr_offset. */ | |
1975 | if (TARGET_HARD_FLOAT) | |
1976 | return 0; | |
1977 | ||
1978 | /* If we have already runned out of argument registers, return zero | |
1979 | so that the argument will be entirely pushed on the stack. */ | |
1980 | if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
1981 | >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS) | |
1982 | return 0; | |
1983 | ||
1984 | /* Calculate how many registers do we need for this argument. */ | |
1985 | needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
1986 | ||
1987 | /* Calculate how many argument registers have left for passing argument. | |
1988 | Note that we should count it from next available register number. */ | |
1989 | remaining_reg_count | |
1990 | = NDS32_MAX_GPR_REGS_FOR_ARGS | |
1991 | - (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
8a498f99 | 1992 | - NDS32_GPR_ARG_FIRST_REGNUM); |
650fc469 CJW |
1993 | |
1994 | /* Note that we have to return the nubmer of bytes, not registers count. */ | |
1995 | if (needed_reg_count > remaining_reg_count) | |
1996 | return remaining_reg_count * UNITS_PER_WORD; | |
1997 | ||
1998 | return 0; | |
1999 | } | |
2000 | ||
9304f876 | 2001 | static void |
ef4bddc2 | 2002 | nds32_function_arg_advance (cumulative_args_t ca, machine_mode mode, |
9304f876 CJW |
2003 | const_tree type, bool named) |
2004 | { | |
2005 | CUMULATIVE_ARGS *cum = get_cumulative_args (ca); | |
2006 | ||
9304f876 CJW |
2007 | if (named) |
2008 | { | |
7f6cd86b | 2009 | /* We need to further check TYPE and MODE so that we can determine |
e2286268 | 2010 | which kind of register we shall advance. */ |
7f6cd86b CJW |
2011 | |
2012 | /* Under hard float abi, we may advance FPR registers. */ | |
e2286268 | 2013 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) |
7f6cd86b | 2014 | { |
e2286268 MC |
2015 | cum->fpr_offset |
2016 | = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type) | |
2017 | - NDS32_FPR_ARG_FIRST_REGNUM | |
2018 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
7f6cd86b CJW |
2019 | } |
2020 | else | |
2021 | { | |
2022 | cum->gpr_offset | |
2023 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
2024 | - NDS32_GPR_ARG_FIRST_REGNUM | |
2025 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
2026 | } | |
2027 | } | |
2028 | else | |
2029 | { | |
2030 | /* If this nameless argument is NOT under TARGET_HARD_FLOAT, | |
8a498f99 CJW |
2031 | we can advance next register as well so that caller is |
2032 | able to pass arguments in registers and callee must be | |
2033 | in charge of pushing all of them into stack. */ | |
7f6cd86b CJW |
2034 | if (!TARGET_HARD_FLOAT) |
2035 | { | |
2036 | cum->gpr_offset | |
2037 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
2038 | - NDS32_GPR_ARG_FIRST_REGNUM | |
2039 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
2040 | } | |
9304f876 CJW |
2041 | } |
2042 | } | |
2043 | ||
2044 | static unsigned int | |
ef4bddc2 | 2045 | nds32_function_arg_boundary (machine_mode mode, const_tree type) |
9304f876 CJW |
2046 | { |
2047 | return (nds32_needs_double_word_align (mode, type) | |
2048 | ? NDS32_DOUBLE_WORD_ALIGNMENT | |
2049 | : PARM_BOUNDARY); | |
2050 | } | |
2051 | ||
7c32ef41 MC |
2052 | bool |
2053 | nds32_vector_mode_supported_p (machine_mode mode) | |
2054 | { | |
2055 | if (mode == V4QImode | |
2056 | || mode == V2HImode) | |
2057 | return NDS32_EXT_DSP_P (); | |
2058 | ||
2059 | return false; | |
2060 | } | |
2061 | ||
9304f876 CJW |
2062 | /* -- How Scalar Function Values Are Returned. */ |
2063 | ||
2064 | static rtx | |
2065 | nds32_function_value (const_tree ret_type, | |
2066 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
2067 | bool outgoing ATTRIBUTE_UNUSED) | |
2068 | { | |
ef4bddc2 | 2069 | machine_mode mode; |
9304f876 CJW |
2070 | int unsignedp; |
2071 | ||
2072 | mode = TYPE_MODE (ret_type); | |
2073 | unsignedp = TYPE_UNSIGNED (ret_type); | |
2074 | ||
e2286268 MC |
2075 | if (INTEGRAL_TYPE_P (ret_type)) |
2076 | mode = promote_mode (ret_type, mode, &unsignedp); | |
9304f876 | 2077 | |
e2286268 MC |
2078 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) |
2079 | return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM); | |
2080 | else | |
2081 | return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); | |
9304f876 CJW |
2082 | } |
2083 | ||
2084 | static rtx | |
ef4bddc2 | 2085 | nds32_libcall_value (machine_mode mode, |
9304f876 CJW |
2086 | const_rtx fun ATTRIBUTE_UNUSED) |
2087 | { | |
e2286268 MC |
2088 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) |
2089 | return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM); | |
2090 | ||
9304f876 CJW |
2091 | return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); |
2092 | } | |
2093 | ||
2094 | static bool | |
2095 | nds32_function_value_regno_p (const unsigned int regno) | |
2096 | { | |
e2286268 MC |
2097 | if (regno == NDS32_GPR_RET_FIRST_REGNUM |
2098 | || (TARGET_HARD_FLOAT | |
2099 | && regno == NDS32_FPR_RET_FIRST_REGNUM)) | |
2100 | return true; | |
2101 | ||
2102 | return false; | |
2103 | } | |
2104 | ||
2105 | /* -- How Large Values Are Returned. */ | |
2106 | ||
2107 | static bool | |
2108 | nds32_return_in_memory (const_tree type, | |
2109 | const_tree fntype ATTRIBUTE_UNUSED) | |
2110 | { | |
2111 | /* Note that int_size_in_bytes can return -1 if the size can vary | |
2112 | or is larger than an integer. */ | |
2113 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
2114 | ||
2115 | /* For COMPLEX_TYPE, if the total size cannot be hold within two registers, | |
2116 | the return value is supposed to be in memory. We need to be aware of | |
2117 | that the size may be -1. */ | |
2118 | if (TREE_CODE (type) == COMPLEX_TYPE) | |
2119 | if (size < 0 || size > 2 * UNITS_PER_WORD) | |
2120 | return true; | |
2121 | ||
2122 | /* If it is BLKmode and the total size cannot be hold within two registers, | |
2123 | the return value is supposed to be in memory. We need to be aware of | |
2124 | that the size may be -1. */ | |
2125 | if (TYPE_MODE (type) == BLKmode) | |
2126 | if (size < 0 || size > 2 * UNITS_PER_WORD) | |
2127 | return true; | |
2128 | ||
2129 | /* For other cases, having result in memory is unnecessary. */ | |
2130 | return false; | |
9304f876 CJW |
2131 | } |
2132 | ||
2133 | /* -- Function Entry and Exit. */ | |
2134 | ||
2135 | /* The content produced from this function | |
2136 | will be placed before prologue body. */ | |
2137 | static void | |
42776416 | 2138 | nds32_asm_function_prologue (FILE *file) |
9304f876 CJW |
2139 | { |
2140 | int r; | |
2141 | const char *func_name; | |
2142 | tree attrs; | |
2143 | tree name; | |
2144 | ||
2145 | /* All stack frame information is supposed to be | |
2146 | already computed when expanding prologue. | |
2147 | The result is in cfun->machine. | |
2148 | DO NOT call nds32_compute_stack_frame() here | |
2149 | because it may corrupt the essential information. */ | |
2150 | ||
2151 | fprintf (file, "\t! BEGIN PROLOGUE\n"); | |
2152 | fprintf (file, "\t! fp needed: %d\n", frame_pointer_needed); | |
2153 | fprintf (file, "\t! pretend_args: %d\n", cfun->machine->va_args_size); | |
2154 | fprintf (file, "\t! local_size: %d\n", cfun->machine->local_size); | |
2155 | fprintf (file, "\t! out_args_size: %d\n", cfun->machine->out_args_size); | |
2156 | ||
2157 | /* Use df_regs_ever_live_p() to detect if the register | |
2158 | is ever used in the current function. */ | |
2159 | fprintf (file, "\t! registers ever_live: "); | |
e2286268 | 2160 | for (r = 0; r < 65; r++) |
9304f876 CJW |
2161 | { |
2162 | if (df_regs_ever_live_p (r)) | |
2163 | fprintf (file, "%s, ", reg_names[r]); | |
2164 | } | |
2165 | fputc ('\n', file); | |
2166 | ||
2167 | /* Display the attributes of this function. */ | |
2168 | fprintf (file, "\t! function attributes: "); | |
f2dafb91 CJW |
2169 | /* Get the attributes tree list. |
2170 | Note that GCC builds attributes list with reverse order. */ | |
2171 | attrs = DECL_ATTRIBUTES (current_function_decl); | |
9304f876 CJW |
2172 | |
2173 | /* If there is no any attribute, print out "None". */ | |
2174 | if (!attrs) | |
2175 | fprintf (file, "None"); | |
2176 | ||
2177 | /* If there are some attributes, try if we need to | |
2178 | construct isr vector information. */ | |
2179 | func_name = IDENTIFIER_POINTER (DECL_NAME (current_function_decl)); | |
2180 | nds32_construct_isr_vectors_information (attrs, func_name); | |
2181 | ||
2182 | /* Display all attributes of this function. */ | |
2183 | while (attrs) | |
2184 | { | |
2185 | name = TREE_PURPOSE (attrs); | |
2186 | fprintf (file, "%s ", IDENTIFIER_POINTER (name)); | |
2187 | ||
2188 | /* Pick up the next attribute. */ | |
2189 | attrs = TREE_CHAIN (attrs); | |
2190 | } | |
2191 | fputc ('\n', file); | |
2192 | } | |
2193 | ||
2194 | /* After rtl prologue has been expanded, this function is used. */ | |
2195 | static void | |
2196 | nds32_asm_function_end_prologue (FILE *file) | |
2197 | { | |
2198 | fprintf (file, "\t! END PROLOGUE\n"); | |
9304f876 CJW |
2199 | } |
2200 | ||
2201 | /* Before rtl epilogue has been expanded, this function is used. */ | |
2202 | static void | |
2203 | nds32_asm_function_begin_epilogue (FILE *file) | |
2204 | { | |
9304f876 CJW |
2205 | fprintf (file, "\t! BEGIN EPILOGUE\n"); |
2206 | } | |
2207 | ||
2208 | /* The content produced from this function | |
2209 | will be placed after epilogue body. */ | |
2210 | static void | |
42776416 | 2211 | nds32_asm_function_epilogue (FILE *file) |
9304f876 CJW |
2212 | { |
2213 | fprintf (file, "\t! END EPILOGUE\n"); | |
2214 | } | |
2215 | ||
2216 | static void | |
2217 | nds32_asm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, | |
2218 | HOST_WIDE_INT delta, | |
2219 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2220 | tree function) | |
2221 | { | |
2222 | int this_regno; | |
2223 | ||
2224 | /* Make sure unwind info is emitted for the thunk if needed. */ | |
2225 | final_start_function (emit_barrier (), file, 1); | |
2226 | ||
2227 | this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) | |
2228 | ? 1 | |
2229 | : 0); | |
2230 | ||
b26fa4f9 KLC |
2231 | if (flag_pic) |
2232 | { | |
2233 | fprintf (file, "\tsmw.adm\t$r31, [$r31], $r31, 4\n"); | |
2234 | fprintf (file, "\tsethi\t%s, hi20(_GLOBAL_OFFSET_TABLE_-8)\n", | |
2235 | reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
2236 | fprintf (file, "\tori\t%s, %s, lo12(_GLOBAL_OFFSET_TABLE_-4)\n", | |
2237 | reg_names [PIC_OFFSET_TABLE_REGNUM], | |
2238 | reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
2239 | ||
2240 | if (TARGET_ISA_V3) | |
2241 | fprintf (file, "\tadd5.pc\t$gp\n"); | |
2242 | else | |
2243 | { | |
2244 | fprintf (file, "\tmfusr\t$ta, $pc\n"); | |
2245 | fprintf (file, "\tadd\t%s, $ta, %s\n", | |
2246 | reg_names [PIC_OFFSET_TABLE_REGNUM], | |
2247 | reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
2248 | } | |
2249 | } | |
2250 | ||
9304f876 CJW |
2251 | if (delta != 0) |
2252 | { | |
2253 | if (satisfies_constraint_Is15 (GEN_INT (delta))) | |
2254 | { | |
5af50159 | 2255 | fprintf (file, "\taddi\t$r%d, $r%d, " HOST_WIDE_INT_PRINT_DEC "\n", |
9304f876 CJW |
2256 | this_regno, this_regno, delta); |
2257 | } | |
2258 | else if (satisfies_constraint_Is20 (GEN_INT (delta))) | |
2259 | { | |
5af50159 | 2260 | fprintf (file, "\tmovi\t$ta, " HOST_WIDE_INT_PRINT_DEC "\n", delta); |
9304f876 CJW |
2261 | fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); |
2262 | } | |
2263 | else | |
2264 | { | |
5af50159 KC |
2265 | fprintf (file, |
2266 | "\tsethi\t$ta, hi20(" HOST_WIDE_INT_PRINT_DEC ")\n", | |
2267 | delta); | |
2268 | fprintf (file, | |
2269 | "\tori\t$ta, $ta, lo12(" HOST_WIDE_INT_PRINT_DEC ")\n", | |
2270 | delta); | |
9304f876 CJW |
2271 | fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); |
2272 | } | |
2273 | } | |
2274 | ||
b26fa4f9 KLC |
2275 | if (flag_pic) |
2276 | { | |
2277 | fprintf (file, "\tla\t$ta, "); | |
2278 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2279 | fprintf (file, "@PLT\n"); | |
2280 | fprintf (file, "\t! epilogue\n"); | |
2281 | fprintf (file, "\tlwi.bi\t%s, [%s], 4\n", | |
2282 | reg_names[PIC_OFFSET_TABLE_REGNUM], | |
2283 | reg_names[STACK_POINTER_REGNUM]); | |
2284 | fprintf (file, "\tbr\t$ta\n"); | |
2285 | } | |
2286 | else | |
2287 | { | |
2288 | fprintf (file, "\tb\t"); | |
2289 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2290 | fprintf (file, "\n"); | |
2291 | } | |
9304f876 CJW |
2292 | |
2293 | final_end_function (); | |
2294 | } | |
2295 | ||
2296 | /* -- Permitting tail calls. */ | |
2297 | ||
cc48a87f CJW |
2298 | /* Return true if it is ok to do sibling call optimization. */ |
2299 | static bool | |
2300 | nds32_function_ok_for_sibcall (tree decl, | |
2301 | tree exp ATTRIBUTE_UNUSED) | |
2302 | { | |
2303 | /* The DECL is NULL if it is an indirect call. */ | |
2304 | ||
2305 | /* 1. Do not apply sibling call if -mv3push is enabled, | |
2306 | because pop25 instruction also represents return behavior. | |
2307 | 2. If this function is a variadic function, do not apply sibling call | |
2308 | because the stack layout may be a mess. | |
2309 | 3. We don't want to apply sibling call optimization for indirect | |
2310 | sibcall because the pop behavior in epilogue may pollute the | |
2311 | content of caller-saved regsiter when the register is used for | |
b26fa4f9 KLC |
2312 | indirect sibcall. |
2313 | 4. In pic mode, it may use some registers for PLT call. */ | |
cc48a87f CJW |
2314 | return (!TARGET_V3PUSH |
2315 | && (cfun->machine->va_args_size == 0) | |
b26fa4f9 KLC |
2316 | && decl |
2317 | && !flag_pic); | |
cc48a87f CJW |
2318 | } |
2319 | ||
9304f876 CJW |
2320 | /* Determine whether we need to enable warning for function return check. */ |
2321 | static bool | |
2322 | nds32_warn_func_return (tree decl) | |
2323 | { | |
8a498f99 CJW |
2324 | /* Naked functions are implemented entirely in assembly, including the |
2325 | return sequence, so suppress warnings about this. */ | |
9304f876 CJW |
2326 | return !nds32_naked_function_p (decl); |
2327 | } | |
2328 | ||
2329 | \f | |
2330 | /* Implementing the Varargs Macros. */ | |
2331 | ||
d4a6a4d9 CJW |
2332 | static void |
2333 | nds32_setup_incoming_varargs (cumulative_args_t ca, | |
ef4bddc2 | 2334 | machine_mode mode, |
d4a6a4d9 CJW |
2335 | tree type, |
2336 | int *pretend_args_size, | |
2337 | int second_time ATTRIBUTE_UNUSED) | |
2338 | { | |
2339 | unsigned int total_args_regs; | |
2340 | unsigned int num_of_used_regs; | |
2341 | unsigned int remaining_reg_count; | |
2342 | CUMULATIVE_ARGS *cum; | |
2343 | ||
2344 | /* If we are under hard float abi, we do not need to set *pretend_args_size. | |
2345 | So that all nameless arguments are pushed by caller and all situation | |
2346 | can be handled by GCC itself. */ | |
2347 | if (TARGET_HARD_FLOAT) | |
2348 | return; | |
2349 | ||
2350 | /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers, | |
2351 | counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments. | |
2352 | However, for nameless(anonymous) arguments, we should push them on the | |
2353 | stack so that all the nameless arguments appear to have been passed | |
2354 | consecutively in the memory for accessing. Hence, we need to check and | |
2355 | exclude the registers that are used for named arguments. */ | |
2356 | ||
2357 | cum = get_cumulative_args (ca); | |
2358 | ||
2359 | /* The MODE and TYPE describe the last argument. | |
2360 | We need those information to determine the remaining registers | |
2361 | for varargs. */ | |
2362 | total_args_regs | |
2363 | = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM; | |
2364 | num_of_used_regs | |
2365 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
2366 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
2367 | ||
2368 | remaining_reg_count = total_args_regs - num_of_used_regs; | |
2369 | *pretend_args_size = remaining_reg_count * UNITS_PER_WORD; | |
2370 | ||
2371 | return; | |
2372 | } | |
2373 | ||
9304f876 CJW |
2374 | static bool |
2375 | nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) | |
2376 | { | |
d4a6a4d9 CJW |
2377 | /* If this hook returns true, the named argument of FUNCTION_ARG is always |
2378 | true for named arguments, and false for unnamed arguments. */ | |
9304f876 CJW |
2379 | return true; |
2380 | } | |
2381 | ||
2382 | \f | |
2383 | /* Trampolines for Nested Functions. */ | |
2384 | ||
2385 | static void | |
2386 | nds32_asm_trampoline_template (FILE *f) | |
2387 | { | |
2388 | if (TARGET_REDUCED_REGS) | |
2389 | { | |
2390 | /* Trampoline is not supported on reduced-set registers yet. */ | |
2391 | sorry ("a nested function is not supported for reduced registers"); | |
2392 | } | |
2393 | else | |
2394 | { | |
2395 | asm_fprintf (f, "\t! Trampoline code template\n"); | |
2396 | asm_fprintf (f, "\t! This code fragment will be copied " | |
2397 | "into stack on demand\n"); | |
2398 | ||
2399 | asm_fprintf (f, "\tmfusr\t$r16,$pc\n"); | |
2400 | asm_fprintf (f, "\tlwi\t$r15,[$r16 + 20] " | |
2401 | "! load nested function address\n"); | |
2402 | asm_fprintf (f, "\tlwi\t$r16,[$r16 + 16] " | |
2403 | "! load chain_value\n"); | |
2404 | asm_fprintf (f, "\tjr\t$r15\n"); | |
2405 | } | |
2406 | ||
2407 | /* Preserve space ($pc + 16) for saving chain_value, | |
2408 | nds32_trampoline_init will fill the value in this slot. */ | |
2409 | asm_fprintf (f, "\t! space for saving chain_value\n"); | |
2410 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
2411 | ||
2412 | /* Preserve space ($pc + 20) for saving nested function address, | |
2413 | nds32_trampoline_init will fill the value in this slot. */ | |
2414 | asm_fprintf (f, "\t! space for saving nested function address\n"); | |
2415 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
2416 | } | |
2417 | ||
2418 | /* Emit RTL insns to initialize the variable parts of a trampoline. */ | |
2419 | static void | |
2420 | nds32_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2421 | { | |
2422 | int i; | |
2423 | ||
2424 | /* Nested function address. */ | |
2425 | rtx fnaddr; | |
2426 | /* The memory rtx that is going to | |
2427 | be filled with chain_value. */ | |
2428 | rtx chain_value_mem; | |
2429 | /* The memory rtx that is going to | |
2430 | be filled with nested function address. */ | |
2431 | rtx nested_func_mem; | |
2432 | ||
2433 | /* Start address of trampoline code in stack, for doing cache sync. */ | |
2434 | rtx sync_cache_addr; | |
2435 | /* Temporary register for sync instruction. */ | |
2436 | rtx tmp_reg; | |
2437 | /* Instruction-cache sync instruction, | |
2438 | requesting an argument as starting address. */ | |
2439 | rtx isync_insn; | |
2440 | /* For convenience reason of doing comparison. */ | |
2441 | int tramp_align_in_bytes; | |
2442 | ||
2443 | /* Trampoline is not supported on reduced-set registers yet. */ | |
2444 | if (TARGET_REDUCED_REGS) | |
2445 | sorry ("a nested function is not supported for reduced registers"); | |
2446 | ||
2447 | /* STEP 1: Copy trampoline code template into stack, | |
8a498f99 | 2448 | fill up essential data into stack. */ |
9304f876 CJW |
2449 | |
2450 | /* Extract nested function address rtx. */ | |
2451 | fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
2452 | ||
2453 | /* m_tramp is memory rtx that is going to be filled with trampoline code. | |
2454 | We have nds32_asm_trampoline_template() to emit template pattern. */ | |
2455 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
2456 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
2457 | ||
2458 | /* After copying trampoline code into stack, | |
2459 | fill chain_value into stack. */ | |
2460 | chain_value_mem = adjust_address (m_tramp, SImode, 16); | |
2461 | emit_move_insn (chain_value_mem, chain_value); | |
2462 | /* After copying trampoline code int stack, | |
2463 | fill nested function address into stack. */ | |
2464 | nested_func_mem = adjust_address (m_tramp, SImode, 20); | |
2465 | emit_move_insn (nested_func_mem, fnaddr); | |
2466 | ||
2467 | /* STEP 2: Sync instruction-cache. */ | |
2468 | ||
2469 | /* We have successfully filled trampoline code into stack. | |
2470 | However, in order to execute code in stack correctly, | |
2471 | we must sync instruction cache. */ | |
2472 | sync_cache_addr = XEXP (m_tramp, 0); | |
2473 | tmp_reg = gen_reg_rtx (SImode); | |
2474 | isync_insn = gen_unspec_volatile_isync (tmp_reg); | |
2475 | ||
2476 | /* Because nds32_cache_block_size is in bytes, | |
2477 | we get trampoline alignment in bytes for convenient comparison. */ | |
2478 | tramp_align_in_bytes = TRAMPOLINE_ALIGNMENT / BITS_PER_UNIT; | |
2479 | ||
2480 | if (tramp_align_in_bytes >= nds32_cache_block_size | |
2481 | && (tramp_align_in_bytes % nds32_cache_block_size) == 0) | |
2482 | { | |
2483 | /* Under this condition, the starting address of trampoline | |
8a498f99 CJW |
2484 | must be aligned to the starting address of each cache block |
2485 | and we do not have to worry about cross-boundary issue. */ | |
9304f876 CJW |
2486 | for (i = 0; |
2487 | i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) | |
2488 | / nds32_cache_block_size; | |
2489 | i++) | |
2490 | { | |
2491 | emit_move_insn (tmp_reg, | |
2492 | plus_constant (Pmode, sync_cache_addr, | |
2493 | nds32_cache_block_size * i)); | |
2494 | emit_insn (isync_insn); | |
2495 | } | |
2496 | } | |
2497 | else if (TRAMPOLINE_SIZE > nds32_cache_block_size) | |
2498 | { | |
2499 | /* The starting address of trampoline code | |
8a498f99 CJW |
2500 | may not be aligned to the cache block, |
2501 | so the trampoline code may be across two cache block. | |
2502 | We need to sync the last element, which is 4-byte size, | |
2503 | of trampoline template. */ | |
9304f876 CJW |
2504 | for (i = 0; |
2505 | i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) | |
2506 | / nds32_cache_block_size; | |
2507 | i++) | |
2508 | { | |
2509 | emit_move_insn (tmp_reg, | |
2510 | plus_constant (Pmode, sync_cache_addr, | |
2511 | nds32_cache_block_size * i)); | |
2512 | emit_insn (isync_insn); | |
2513 | } | |
2514 | ||
2515 | /* The last element of trampoline template is 4-byte size. */ | |
2516 | emit_move_insn (tmp_reg, | |
2517 | plus_constant (Pmode, sync_cache_addr, | |
2518 | TRAMPOLINE_SIZE - 4)); | |
2519 | emit_insn (isync_insn); | |
2520 | } | |
2521 | else | |
2522 | { | |
2523 | /* This is the simplest case. | |
8a498f99 CJW |
2524 | Because TRAMPOLINE_SIZE is less than or |
2525 | equal to nds32_cache_block_size, | |
2526 | we can just sync start address and | |
2527 | the last element of trampoline code. */ | |
9304f876 CJW |
2528 | |
2529 | /* Sync starting address of tampoline code. */ | |
2530 | emit_move_insn (tmp_reg, sync_cache_addr); | |
2531 | emit_insn (isync_insn); | |
2532 | /* Sync the last element, which is 4-byte size, | |
8a498f99 | 2533 | of trampoline template. */ |
9304f876 CJW |
2534 | emit_move_insn (tmp_reg, |
2535 | plus_constant (Pmode, sync_cache_addr, | |
2536 | TRAMPOLINE_SIZE - 4)); | |
2537 | emit_insn (isync_insn); | |
2538 | } | |
2539 | ||
2540 | /* Set instruction serialization barrier | |
2541 | to guarantee the correct operations. */ | |
2542 | emit_insn (gen_unspec_volatile_isb ()); | |
2543 | } | |
2544 | ||
2545 | \f | |
2546 | /* Addressing Modes. */ | |
2547 | ||
2548 | static bool | |
ef4bddc2 | 2549 | nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict) |
9304f876 | 2550 | { |
e2286268 MC |
2551 | if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) |
2552 | { | |
2553 | /* When using floating-point instructions, | |
2554 | we don't allow 'addr' to be [symbol_ref], [CONST] pattern. */ | |
2555 | if ((mode == DFmode || mode == SFmode) | |
2556 | && (GET_CODE (x) == SYMBOL_REF | |
2557 | || GET_CODE(x) == CONST)) | |
2558 | return false; | |
2559 | ||
2560 | /* Allow [post_modify] addressing mode, when using FPU instructions. */ | |
2561 | if (GET_CODE (x) == POST_MODIFY | |
2562 | && mode == DFmode) | |
2563 | { | |
2564 | if (GET_CODE (XEXP (x, 0)) == REG | |
2565 | && GET_CODE (XEXP (x, 1)) == PLUS) | |
2566 | { | |
2567 | rtx plus_op = XEXP (x, 1); | |
2568 | rtx op0 = XEXP (plus_op, 0); | |
2569 | rtx op1 = XEXP (plus_op, 1); | |
2570 | ||
2571 | if (nds32_address_register_rtx_p (op0, strict) | |
2572 | && CONST_INT_P (op1)) | |
2573 | { | |
2574 | if (satisfies_constraint_Is14 (op1)) | |
2575 | { | |
5f2a98c3 CJW |
2576 | /* If it is not under strictly aligned situation, |
2577 | we can return true without checking alignment. */ | |
2578 | if (!cfun->machine->strict_aligned_p) | |
2579 | return true; | |
e2286268 MC |
2580 | /* Make sure address is word alignment. |
2581 | Currently we do not have 64-bit load/store yet, | |
2582 | so we will use two 32-bit load/store instructions to do | |
2583 | memory access and they are single word alignment. */ | |
5f2a98c3 | 2584 | else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (op1))) |
e2286268 MC |
2585 | return true; |
2586 | } | |
2587 | } | |
2588 | } | |
2589 | } | |
2590 | } | |
2591 | ||
9304f876 CJW |
2592 | /* For (mem:DI addr) or (mem:DF addr) case, |
2593 | we only allow 'addr' to be [reg], [symbol_ref], | |
8a498f99 | 2594 | [const], or [reg + const_int] pattern. */ |
9304f876 CJW |
2595 | if (mode == DImode || mode == DFmode) |
2596 | { | |
2597 | /* Allow [Reg + const_int] addressing mode. */ | |
2598 | if (GET_CODE (x) == PLUS) | |
2599 | { | |
2600 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict) | |
2601 | && nds32_legitimate_index_p (mode, XEXP (x, 1), strict) | |
2602 | && CONST_INT_P (XEXP (x, 1))) | |
2603 | return true; | |
9304f876 CJW |
2604 | else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) |
2605 | && nds32_legitimate_index_p (mode, XEXP (x, 0), strict) | |
2606 | && CONST_INT_P (XEXP (x, 0))) | |
2607 | return true; | |
2608 | } | |
2609 | ||
e2286268 MC |
2610 | /* Allow [post_inc] and [post_dec] addressing mode. */ |
2611 | if (GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC) | |
2612 | { | |
2613 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) | |
2614 | return true; | |
2615 | } | |
2616 | ||
9304f876 CJW |
2617 | /* Now check [reg], [symbol_ref], and [const]. */ |
2618 | if (GET_CODE (x) != REG | |
2619 | && GET_CODE (x) != SYMBOL_REF | |
2620 | && GET_CODE (x) != CONST) | |
2621 | return false; | |
2622 | } | |
2623 | ||
2624 | /* Check if 'x' is a valid address. */ | |
2625 | switch (GET_CODE (x)) | |
2626 | { | |
2627 | case REG: | |
2628 | /* (mem (reg A)) => [Ra] */ | |
2629 | return nds32_address_register_rtx_p (x, strict); | |
2630 | ||
2631 | case SYMBOL_REF: | |
4855be84 | 2632 | /* (mem (symbol_ref A)) => [symbol_ref] */ |
b26fa4f9 KLC |
2633 | |
2634 | if (flag_pic || SYMBOL_REF_TLS_MODEL (x)) | |
2635 | return false; | |
2636 | ||
85a98076 KLC |
2637 | if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) |
2638 | return false; | |
2639 | ||
4855be84 | 2640 | /* If -mcmodel=large, the 'symbol_ref' is not a valid address |
8a498f99 | 2641 | during or after LRA/reload phase. */ |
4855be84 | 2642 | if (TARGET_CMODEL_LARGE |
9304f876 CJW |
2643 | && (reload_completed |
2644 | || reload_in_progress | |
2645 | || lra_in_progress)) | |
2646 | return false; | |
4855be84 | 2647 | /* If -mcmodel=medium and the symbol references to rodata section, |
8a498f99 CJW |
2648 | the 'symbol_ref' is not a valid address during or after |
2649 | LRA/reload phase. */ | |
4855be84 | 2650 | if (TARGET_CMODEL_MEDIUM |
b26fa4f9 KLC |
2651 | && (NDS32_SYMBOL_REF_RODATA_P (x) |
2652 | || CONSTANT_POOL_ADDRESS_P (x)) | |
9304f876 CJW |
2653 | && (reload_completed |
2654 | || reload_in_progress | |
2655 | || lra_in_progress)) | |
2656 | return false; | |
2657 | ||
4855be84 CJW |
2658 | return true; |
2659 | ||
2660 | case CONST: | |
9304f876 | 2661 | /* (mem (const (...))) |
8a498f99 | 2662 | => [ + const_addr ], where const_addr = symbol_ref + const_int */ |
9304f876 CJW |
2663 | if (GET_CODE (XEXP (x, 0)) == PLUS) |
2664 | { | |
2665 | rtx plus_op = XEXP (x, 0); | |
2666 | ||
2667 | rtx op0 = XEXP (plus_op, 0); | |
2668 | rtx op1 = XEXP (plus_op, 1); | |
2669 | ||
2670 | if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) | |
4855be84 CJW |
2671 | { |
2672 | /* Now we see the [ + const_addr ] pattern, but we need | |
8a498f99 | 2673 | some further checking. */ |
b26fa4f9 KLC |
2674 | |
2675 | if (flag_pic) | |
2676 | return false; | |
2677 | ||
4855be84 | 2678 | /* If -mcmodel=large, the 'const_addr' is not a valid address |
8a498f99 | 2679 | during or after LRA/reload phase. */ |
4855be84 CJW |
2680 | if (TARGET_CMODEL_LARGE |
2681 | && (reload_completed | |
2682 | || reload_in_progress | |
2683 | || lra_in_progress)) | |
2684 | return false; | |
2685 | /* If -mcmodel=medium and the symbol references to rodata section, | |
8a498f99 CJW |
2686 | the 'const_addr' is not a valid address during or after |
2687 | LRA/reload phase. */ | |
4855be84 CJW |
2688 | if (TARGET_CMODEL_MEDIUM |
2689 | && NDS32_SYMBOL_REF_RODATA_P (op0) | |
2690 | && (reload_completed | |
2691 | || reload_in_progress | |
2692 | || lra_in_progress)) | |
2693 | return false; | |
2694 | ||
2695 | /* At this point we can make sure 'const_addr' is a | |
2696 | valid address. */ | |
2697 | return true; | |
2698 | } | |
9304f876 CJW |
2699 | } |
2700 | ||
2701 | return false; | |
2702 | ||
2703 | case POST_MODIFY: | |
2704 | /* (mem (post_modify (reg) (plus (reg) (reg)))) | |
8a498f99 | 2705 | => [Ra], Rb */ |
9304f876 | 2706 | /* (mem (post_modify (reg) (plus (reg) (const_int)))) |
8a498f99 | 2707 | => [Ra], const_int */ |
9304f876 CJW |
2708 | if (GET_CODE (XEXP (x, 0)) == REG |
2709 | && GET_CODE (XEXP (x, 1)) == PLUS) | |
2710 | { | |
2711 | rtx plus_op = XEXP (x, 1); | |
2712 | ||
2713 | rtx op0 = XEXP (plus_op, 0); | |
2714 | rtx op1 = XEXP (plus_op, 1); | |
2715 | ||
2716 | if (nds32_address_register_rtx_p (op0, strict) | |
2717 | && nds32_legitimate_index_p (mode, op1, strict)) | |
2718 | return true; | |
2719 | else | |
2720 | return false; | |
2721 | } | |
2722 | ||
2723 | return false; | |
2724 | ||
2725 | case POST_INC: | |
2726 | case POST_DEC: | |
2727 | /* (mem (post_inc reg)) => [Ra], 1/2/4 */ | |
2728 | /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */ | |
2729 | /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. | |
8a498f99 | 2730 | We only need to deal with register Ra. */ |
9304f876 CJW |
2731 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) |
2732 | return true; | |
2733 | else | |
2734 | return false; | |
2735 | ||
2736 | case PLUS: | |
2737 | /* (mem (plus reg const_int)) | |
8a498f99 | 2738 | => [Ra + imm] */ |
9304f876 | 2739 | /* (mem (plus reg reg)) |
8a498f99 | 2740 | => [Ra + Rb] */ |
9304f876 | 2741 | /* (mem (plus (mult reg const_int) reg)) |
8a498f99 | 2742 | => [Ra + Rb << sv] */ |
9304f876 CJW |
2743 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict) |
2744 | && nds32_legitimate_index_p (mode, XEXP (x, 1), strict)) | |
2745 | return true; | |
2746 | else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) | |
2747 | && nds32_legitimate_index_p (mode, XEXP (x, 0), strict)) | |
2748 | return true; | |
2749 | else | |
2750 | return false; | |
2751 | ||
2752 | case LO_SUM: | |
34425025 | 2753 | /* (mem (lo_sum (reg) (symbol_ref))) */ |
85a98076 | 2754 | /* (mem (lo_sum (reg) (const (plus (symbol_ref) (reg)))) */ |
b26fa4f9 KLC |
2755 | /* TLS case: (mem (lo_sum (reg) (const (unspec symbol_ref X)))) */ |
2756 | /* The LO_SUM is a valid address if and only if we would like to | |
2757 | generate 32-bit full address memory access with any of following | |
2758 | circumstance: | |
2759 | 1. -mcmodel=large. | |
2760 | 2. -mcmodel=medium and the symbol_ref references to rodata. */ | |
85a98076 KLC |
2761 | { |
2762 | rtx sym = NULL_RTX; | |
2763 | ||
b26fa4f9 KLC |
2764 | if (flag_pic) |
2765 | return false; | |
2766 | ||
85a98076 KLC |
2767 | if (!REG_P (XEXP (x, 0))) |
2768 | return false; | |
2769 | ||
2770 | if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
2771 | sym = XEXP (x, 1); | |
2772 | else if (GET_CODE (XEXP (x, 1)) == CONST) | |
2773 | { | |
2774 | rtx plus = XEXP(XEXP (x, 1), 0); | |
2775 | if (GET_CODE (plus) == PLUS) | |
2776 | sym = XEXP (plus, 0); | |
2777 | else if (GET_CODE (plus) == UNSPEC) | |
2778 | sym = XVECEXP (plus, 0, 0); | |
2779 | } | |
2780 | else | |
2781 | return false; | |
2782 | ||
2783 | gcc_assert (GET_CODE (sym) == SYMBOL_REF); | |
2784 | ||
2785 | if (TARGET_ICT_MODEL_LARGE | |
2786 | && nds32_indirect_call_referenced_p (sym)) | |
2787 | return true; | |
2788 | ||
2789 | if (TARGET_CMODEL_LARGE) | |
2790 | return true; | |
2791 | else if (TARGET_CMODEL_MEDIUM | |
2792 | && NDS32_SYMBOL_REF_RODATA_P (sym)) | |
2793 | return true; | |
2794 | else | |
2795 | return false; | |
2796 | } | |
9304f876 CJW |
2797 | |
2798 | default: | |
2799 | return false; | |
2800 | } | |
2801 | } | |
2802 | ||
85a98076 KLC |
2803 | static rtx |
2804 | nds32_legitimize_address (rtx x, | |
2805 | rtx oldx ATTRIBUTE_UNUSED, | |
2806 | machine_mode mode ATTRIBUTE_UNUSED) | |
2807 | { | |
b26fa4f9 KLC |
2808 | if (nds32_tls_referenced_p (x)) |
2809 | x = nds32_legitimize_tls_address (x); | |
2810 | else if (flag_pic && SYMBOLIC_CONST_P (x)) | |
2811 | x = nds32_legitimize_pic_address (x); | |
2812 | else if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) | |
85a98076 KLC |
2813 | x = nds32_legitimize_ict_address (x); |
2814 | ||
2815 | return x; | |
2816 | } | |
2817 | ||
2818 | static bool | |
2819 | nds32_legitimate_constant_p (machine_mode mode, rtx x) | |
2820 | { | |
2821 | switch (GET_CODE (x)) | |
2822 | { | |
2823 | case CONST_DOUBLE: | |
2824 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
2825 | && (mode == DFmode || mode == SFmode)) | |
2826 | return false; | |
2827 | break; | |
2828 | case CONST: | |
2829 | x = XEXP (x, 0); | |
2830 | ||
2831 | if (GET_CODE (x) == PLUS) | |
2832 | { | |
2833 | if (!CONST_INT_P (XEXP (x, 1))) | |
2834 | return false; | |
2835 | x = XEXP (x, 0); | |
2836 | } | |
2837 | ||
2838 | if (GET_CODE (x) == UNSPEC) | |
2839 | { | |
2840 | switch (XINT (x, 1)) | |
2841 | { | |
b26fa4f9 KLC |
2842 | case UNSPEC_GOT: |
2843 | case UNSPEC_GOTOFF: | |
2844 | case UNSPEC_PLT: | |
2845 | case UNSPEC_TLSGD: | |
2846 | case UNSPEC_TLSLD: | |
2847 | case UNSPEC_TLSIE: | |
2848 | case UNSPEC_TLSLE: | |
85a98076 KLC |
2849 | case UNSPEC_ICT: |
2850 | return false; | |
2851 | default: | |
2852 | return true; | |
2853 | } | |
2854 | } | |
2855 | break; | |
b26fa4f9 KLC |
2856 | case SYMBOL_REF: |
2857 | /* TLS symbols need a call to resolve in | |
2858 | precompute_register_parameters. */ | |
2859 | if (SYMBOL_REF_TLS_MODEL (x)) | |
2860 | return false; | |
2861 | break; | |
85a98076 KLC |
2862 | default: |
2863 | return true; | |
2864 | } | |
2865 | ||
2866 | return true; | |
2867 | } | |
2868 | ||
2869 | /* Reorgnize the UNSPEC CONST and return its direct symbol. */ | |
2870 | static rtx | |
2871 | nds32_delegitimize_address (rtx x) | |
2872 | { | |
2873 | x = delegitimize_mem_from_attrs (x); | |
2874 | ||
2875 | if (GET_CODE(x) == CONST) | |
2876 | { | |
2877 | rtx inner = XEXP (x, 0); | |
2878 | ||
2879 | /* Handle for GOTOFF. */ | |
2880 | if (GET_CODE (inner) == PLUS) | |
2881 | inner = XEXP (inner, 0); | |
2882 | ||
2883 | if (GET_CODE (inner) == UNSPEC) | |
2884 | { | |
2885 | switch (XINT (inner, 1)) | |
2886 | { | |
b26fa4f9 KLC |
2887 | case UNSPEC_GOTINIT: |
2888 | case UNSPEC_GOT: | |
2889 | case UNSPEC_GOTOFF: | |
2890 | case UNSPEC_PLT: | |
2891 | case UNSPEC_TLSGD: | |
2892 | case UNSPEC_TLSLD: | |
2893 | case UNSPEC_TLSIE: | |
2894 | case UNSPEC_TLSLE: | |
85a98076 KLC |
2895 | case UNSPEC_ICT: |
2896 | x = XVECEXP (inner, 0, 0); | |
2897 | break; | |
2898 | default: | |
2899 | break; | |
2900 | } | |
2901 | } | |
2902 | } | |
2903 | return x; | |
2904 | } | |
2905 | ||
7c32ef41 MC |
2906 | static machine_mode |
2907 | nds32_vectorize_preferred_simd_mode (scalar_mode mode) | |
2908 | { | |
2909 | if (!NDS32_EXT_DSP_P ()) | |
2910 | return word_mode; | |
2911 | ||
2912 | switch (mode) | |
2913 | { | |
2914 | case E_QImode: | |
2915 | return V4QImode; | |
2916 | case E_HImode: | |
2917 | return V2HImode; | |
2918 | default: | |
2919 | return word_mode; | |
2920 | } | |
2921 | } | |
2922 | ||
85a98076 KLC |
2923 | static bool |
2924 | nds32_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
2925 | { | |
2926 | switch (GET_CODE (x)) | |
2927 | { | |
2928 | case CONST: | |
2929 | return !nds32_legitimate_constant_p (mode, x); | |
2930 | case SYMBOL_REF: | |
2931 | /* All symbols have to be accessed through gp-relative in PIC mode. */ | |
2932 | /* We don't want to force symbol as constant pool in .text section, | |
2933 | because we use the gp-relatived instruction to load in small | |
2934 | or medium model. */ | |
b26fa4f9 KLC |
2935 | if (flag_pic |
2936 | || SYMBOL_REF_TLS_MODEL (x) | |
85a98076 KLC |
2937 | || TARGET_CMODEL_SMALL |
2938 | || TARGET_CMODEL_MEDIUM) | |
2939 | return true; | |
2940 | break; | |
b26fa4f9 KLC |
2941 | case CONST_INT: |
2942 | case CONST_DOUBLE: | |
2943 | if (flag_pic && (lra_in_progress || reload_completed)) | |
2944 | return true; | |
2945 | break; | |
85a98076 KLC |
2946 | default: |
2947 | return false; | |
2948 | } | |
2949 | return false; | |
2950 | } | |
2951 | ||
5b6f2bf3 CJW |
2952 | \f |
2953 | /* Condition Code Status. */ | |
2954 | ||
2955 | /* -- Representation of condition codes using registers. */ | |
2956 | ||
2957 | static void | |
2958 | nds32_canonicalize_comparison (int *code, | |
2959 | rtx *op0 ATTRIBUTE_UNUSED, | |
2960 | rtx *op1, | |
2961 | bool op0_preserve_value ATTRIBUTE_UNUSED) | |
2962 | { | |
2963 | /* When the instruction combination pass tries to combine a comparison insn | |
2964 | with its previous insns, it also transforms the operator in order to | |
2965 | minimize its constant field. For example, it tries to transform a | |
2966 | comparison insn from | |
2967 | (set (reg:SI 54) | |
2968 | (ltu:SI (reg:SI 52) | |
2969 | (const_int 10 [0xa]))) | |
2970 | to | |
2971 | (set (reg:SI 54) | |
2972 | (leu:SI (reg:SI 52) | |
2973 | (const_int 9 [0x9]))) | |
2974 | ||
2975 | However, the nds32 target only provides instructions supporting the LTU | |
2976 | operation directly, and the implementation of the pattern "cbranchsi4" | |
2977 | only expands the LTU form. In order to handle the non-LTU operations | |
2978 | generated from passes other than the RTL expansion pass, we have to | |
2979 | implement this hook to revert those changes. Since we only expand the LTU | |
2980 | operator in the RTL expansion pass, we might only need to handle the LEU | |
2981 | case, unless we find other optimization passes perform more aggressive | |
2982 | transformations. */ | |
2983 | ||
2984 | if (*code == LEU && CONST_INT_P (*op1)) | |
2985 | { | |
2986 | *op1 = gen_int_mode (INTVAL (*op1) + 1, SImode); | |
2987 | *code = LTU; | |
2988 | } | |
2989 | } | |
2990 | ||
9304f876 CJW |
2991 | \f |
2992 | /* Describing Relative Costs of Operations. */ | |
2993 | ||
19ac960a | 2994 | static int |
69e7672a | 2995 | nds32_register_move_cost (machine_mode mode, |
19ac960a CJW |
2996 | reg_class_t from, |
2997 | reg_class_t to) | |
9304f876 | 2998 | { |
69e7672a KC |
2999 | /* In garywolf cpu, FPR to GPR is chaper than other cpu. */ |
3000 | if (TARGET_PIPELINE_GRAYWOLF) | |
3001 | { | |
3002 | if (GET_MODE_SIZE (mode) == 8) | |
3003 | { | |
3004 | /* DPR to GPR. */ | |
3005 | if (from == FP_REGS && to != FP_REGS) | |
3006 | return 3; | |
3007 | /* GPR to DPR. */ | |
3008 | if (from != FP_REGS && to == FP_REGS) | |
3009 | return 2; | |
3010 | } | |
3011 | else | |
3012 | { | |
3013 | if ((from == FP_REGS && to != FP_REGS) | |
3014 | || (from != FP_REGS && to == FP_REGS)) | |
3015 | return 2; | |
3016 | } | |
3017 | } | |
3018 | ||
e2286268 MC |
3019 | if ((from == FP_REGS && to != FP_REGS) |
3020 | || (from != FP_REGS && to == FP_REGS)) | |
69e7672a | 3021 | return 3; |
e2286268 MC |
3022 | else if (from == HIGH_REGS || to == HIGH_REGS) |
3023 | return optimize_size ? 6 : 2; | |
3024 | else | |
3025 | return 2; | |
9304f876 CJW |
3026 | } |
3027 | ||
19ac960a | 3028 | static int |
ef4bddc2 | 3029 | nds32_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
19ac960a CJW |
3030 | reg_class_t rclass ATTRIBUTE_UNUSED, |
3031 | bool in ATTRIBUTE_UNUSED) | |
9304f876 CJW |
3032 | { |
3033 | return 8; | |
3034 | } | |
3035 | ||
3036 | /* This target hook describes the relative costs of RTL expressions. | |
3037 | Return 'true' when all subexpressions of x have been processed. | |
3038 | Return 'false' to sum the costs of sub-rtx, plus cost of this operation. | |
3039 | Refer to gcc/rtlanal.c for more information. */ | |
3040 | static bool | |
3041 | nds32_rtx_costs (rtx x, | |
e548c9df | 3042 | machine_mode mode, |
9304f876 | 3043 | int outer_code, |
89a4b547 | 3044 | int opno, |
9304f876 CJW |
3045 | int *total, |
3046 | bool speed) | |
3047 | { | |
e548c9df | 3048 | return nds32_rtx_costs_impl (x, mode, outer_code, opno, total, speed); |
9304f876 CJW |
3049 | } |
3050 | ||
19ac960a CJW |
3051 | static int |
3052 | nds32_address_cost (rtx address, | |
ef4bddc2 | 3053 | machine_mode mode, |
19ac960a CJW |
3054 | addr_space_t as, |
3055 | bool speed) | |
9304f876 | 3056 | { |
89a4b547 | 3057 | return nds32_address_cost_impl (address, mode, as, speed); |
9304f876 CJW |
3058 | } |
3059 | ||
511a41d7 CJW |
3060 | \f |
3061 | /* Dividing the Output into Sections (Texts, Data, . . . ). */ | |
3062 | ||
3063 | /* If references to a symbol or a constant must be treated differently | |
3064 | depending on something about the variable or function named by the symbol | |
3065 | (such as what section it is in), we use this hook to store flags | |
3066 | in symbol_ref rtx. */ | |
3067 | static void | |
3068 | nds32_encode_section_info (tree decl, rtx rtl, int new_decl_p) | |
3069 | { | |
3070 | default_encode_section_info (decl, rtl, new_decl_p); | |
3071 | ||
3072 | /* For the memory rtx, if it references to rodata section, we can store | |
3073 | NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the | |
3074 | nds32_legitimate_address_p() can determine how to treat such symbol_ref | |
3075 | based on -mcmodel=X and this information. */ | |
3076 | if (MEM_P (rtl) && MEM_READONLY_P (rtl)) | |
3077 | { | |
3078 | rtx addr = XEXP (rtl, 0); | |
3079 | ||
3080 | if (GET_CODE (addr) == SYMBOL_REF) | |
3081 | { | |
3082 | /* For (mem (symbol_ref X)) case. */ | |
3083 | SYMBOL_REF_FLAGS (addr) |= NDS32_SYMBOL_FLAG_RODATA; | |
3084 | } | |
3085 | else if (GET_CODE (addr) == CONST | |
3086 | && GET_CODE (XEXP (addr, 0)) == PLUS) | |
3087 | { | |
3088 | /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */ | |
3089 | rtx plus_op = XEXP (addr, 0); | |
3090 | rtx op0 = XEXP (plus_op, 0); | |
3091 | rtx op1 = XEXP (plus_op, 1); | |
3092 | ||
3093 | if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) | |
3094 | SYMBOL_REF_FLAGS (op0) |= NDS32_SYMBOL_FLAG_RODATA; | |
3095 | } | |
3096 | } | |
3097 | } | |
3098 | ||
9304f876 CJW |
3099 | \f |
3100 | /* Defining the Output Assembler Language. */ | |
3101 | ||
3102 | /* -- The Overall Framework of an Assembler File. */ | |
3103 | ||
3104 | static void | |
3105 | nds32_asm_file_start (void) | |
3106 | { | |
9304f876 CJW |
3107 | default_file_start (); |
3108 | ||
b26fa4f9 KLC |
3109 | if (flag_pic) |
3110 | fprintf (asm_out_file, "\t.pic\n"); | |
3111 | ||
9304f876 CJW |
3112 | /* Tell assembler which ABI we are using. */ |
3113 | fprintf (asm_out_file, "\t! ABI version\n"); | |
e2286268 MC |
3114 | if (TARGET_HARD_FLOAT) |
3115 | fprintf (asm_out_file, "\t.abi_2fp_plus\n"); | |
3116 | else | |
3117 | fprintf (asm_out_file, "\t.abi_2\n"); | |
9304f876 CJW |
3118 | |
3119 | /* Tell assembler that this asm code is generated by compiler. */ | |
3120 | fprintf (asm_out_file, "\t! This asm file is generated by compiler\n"); | |
3121 | fprintf (asm_out_file, "\t.flag\tverbatim\n"); | |
85a98076 KLC |
3122 | |
3123 | if (TARGET_ICT_MODEL_LARGE) | |
3124 | fprintf (asm_out_file, "\t.ict_model\tlarge\n"); | |
3125 | else | |
3126 | fprintf (asm_out_file, "\t.ict_model\tsmall\n"); | |
9304f876 CJW |
3127 | /* Give assembler the size of each vector for interrupt handler. */ |
3128 | fprintf (asm_out_file, "\t! This vector size directive is required " | |
3129 | "for checking inconsistency on interrupt handler\n"); | |
3130 | fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size); | |
3131 | ||
2140297c CJW |
3132 | /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os, |
3133 | the compiler may produce 'la $fp,_FP_BASE_' instruction | |
3134 | at prologue for fp-as-gp optimization. | |
3135 | We should emit weak reference of _FP_BASE_ to avoid undefined reference | |
3136 | in case user does not pass '--relax' option to linker. */ | |
3137 | if (TARGET_FORCE_FP_AS_GP || optimize_size) | |
3138 | { | |
3139 | fprintf (asm_out_file, "\t! This weak reference is required to do " | |
3140 | "fp-as-gp link time optimization\n"); | |
3141 | fprintf (asm_out_file, "\t.weak\t_FP_BASE_\n"); | |
3142 | } | |
3143 | ||
9304f876 CJW |
3144 | fprintf (asm_out_file, "\t! ------------------------------------\n"); |
3145 | ||
3146 | if (TARGET_ISA_V2) | |
3147 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V2"); | |
3148 | if (TARGET_ISA_V3) | |
3149 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3"); | |
3150 | if (TARGET_ISA_V3M) | |
3151 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M"); | |
3152 | ||
dd000841 CJW |
3153 | switch (nds32_cpu_option) |
3154 | { | |
3155 | case CPU_N6: | |
3156 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N6"); | |
3157 | break; | |
3158 | ||
3159 | case CPU_N7: | |
3160 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N7"); | |
3161 | break; | |
3162 | ||
3163 | case CPU_N8: | |
3164 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N8"); | |
3165 | break; | |
3166 | ||
3167 | case CPU_E8: | |
3168 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "E8"); | |
3169 | break; | |
3170 | ||
3171 | case CPU_N9: | |
3172 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N9"); | |
3173 | break; | |
3174 | ||
3175 | case CPU_N10: | |
3176 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N10"); | |
3177 | break; | |
3178 | ||
3179 | case CPU_GRAYWOLF: | |
3180 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "Graywolf"); | |
3181 | break; | |
3182 | ||
3183 | case CPU_N12: | |
3184 | case CPU_N13: | |
3185 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N13"); | |
3186 | break; | |
3187 | ||
3188 | case CPU_SIMPLE: | |
3189 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "SIMPLE"); | |
3190 | break; | |
3191 | ||
3192 | default: | |
3193 | gcc_unreachable (); | |
3194 | } | |
3195 | ||
77b7a1ca CJW |
3196 | if (TARGET_CMODEL_SMALL) |
3197 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "SMALL"); | |
3198 | if (TARGET_CMODEL_MEDIUM) | |
3199 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "MEDIUM"); | |
3200 | if (TARGET_CMODEL_LARGE) | |
3201 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "LARGE"); | |
3202 | ||
9304f876 CJW |
3203 | fprintf (asm_out_file, "\t! Endian setting\t: %s\n", |
3204 | ((TARGET_BIG_ENDIAN) ? "big-endian" | |
3205 | : "little-endian")); | |
e2286268 MC |
3206 | fprintf (asm_out_file, "\t! Use SP floating-point instruction\t: %s\n", |
3207 | ((TARGET_FPU_SINGLE) ? "Yes" | |
3208 | : "No")); | |
3209 | fprintf (asm_out_file, "\t! Use DP floating-point instruction\t: %s\n", | |
3210 | ((TARGET_FPU_DOUBLE) ? "Yes" | |
3211 | : "No")); | |
3212 | fprintf (asm_out_file, "\t! ABI version\t\t: %s\n", | |
3213 | ((TARGET_HARD_FLOAT) ? "ABI2FP+" | |
3214 | : "ABI2")); | |
9304f876 CJW |
3215 | |
3216 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3217 | ||
3218 | fprintf (asm_out_file, "\t! Use conditional move\t\t: %s\n", | |
3219 | ((TARGET_CMOV) ? "Yes" | |
3220 | : "No")); | |
3221 | fprintf (asm_out_file, "\t! Use performance extension\t: %s\n", | |
aa4b851c | 3222 | ((TARGET_EXT_PERF) ? "Yes" |
9304f876 | 3223 | : "No")); |
aa4b851c CJW |
3224 | fprintf (asm_out_file, "\t! Use performance extension 2\t: %s\n", |
3225 | ((TARGET_EXT_PERF2) ? "Yes" | |
3226 | : "No")); | |
3227 | fprintf (asm_out_file, "\t! Use string extension\t\t: %s\n", | |
3228 | ((TARGET_EXT_STRING) ? "Yes" | |
3229 | : "No")); | |
9304f876 CJW |
3230 | |
3231 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3232 | ||
3233 | fprintf (asm_out_file, "\t! V3PUSH instructions\t: %s\n", | |
3234 | ((TARGET_V3PUSH) ? "Yes" | |
3235 | : "No")); | |
3236 | fprintf (asm_out_file, "\t! 16-bit instructions\t: %s\n", | |
3237 | ((TARGET_16_BIT) ? "Yes" | |
3238 | : "No")); | |
9304f876 CJW |
3239 | fprintf (asm_out_file, "\t! Reduced registers set\t: %s\n", |
3240 | ((TARGET_REDUCED_REGS) ? "Yes" | |
3241 | : "No")); | |
3242 | ||
bc8a8810 MC |
3243 | fprintf (asm_out_file, "\t! Support unaligned access\t\t: %s\n", |
3244 | (flag_unaligned_access ? "Yes" | |
3245 | : "No")); | |
3246 | ||
9304f876 CJW |
3247 | fprintf (asm_out_file, "\t! ------------------------------------\n"); |
3248 | ||
3249 | if (optimize_size) | |
3250 | fprintf (asm_out_file, "\t! Optimization level\t: -Os\n"); | |
10c8bd03 CJW |
3251 | else if (optimize_fast) |
3252 | fprintf (asm_out_file, "\t! Optimization level\t: -Ofast\n"); | |
3253 | else if (optimize_debug) | |
3254 | fprintf (asm_out_file, "\t! Optimization level\t: -Og\n"); | |
9304f876 CJW |
3255 | else |
3256 | fprintf (asm_out_file, "\t! Optimization level\t: -O%d\n", optimize); | |
3257 | ||
3258 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3259 | ||
3260 | fprintf (asm_out_file, "\t! Cache block size\t: %d\n", | |
3261 | nds32_cache_block_size); | |
3262 | ||
3263 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3264 | ||
c23a919b | 3265 | nds32_asm_file_start_for_isr (); |
9304f876 CJW |
3266 | } |
3267 | ||
3268 | static void | |
3269 | nds32_asm_file_end (void) | |
3270 | { | |
c23a919b | 3271 | nds32_asm_file_end_for_isr (); |
9304f876 CJW |
3272 | |
3273 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3274 | } | |
3275 | ||
85a98076 KLC |
3276 | static bool |
3277 | nds32_asm_output_addr_const_extra (FILE *file, rtx x) | |
3278 | { | |
3279 | if (GET_CODE (x) == UNSPEC) | |
3280 | { | |
3281 | switch (XINT (x, 1)) | |
3282 | { | |
b26fa4f9 KLC |
3283 | case UNSPEC_GOTINIT: |
3284 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3285 | break; | |
3286 | case UNSPEC_GOTOFF: | |
3287 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3288 | fputs ("@GOTOFF", file); | |
3289 | break; | |
3290 | case UNSPEC_GOT: | |
3291 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3292 | fputs ("@GOT", file); | |
3293 | break; | |
3294 | case UNSPEC_PLT: | |
3295 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3296 | fputs ("@PLT", file); | |
3297 | break; | |
3298 | case UNSPEC_TLSGD: | |
3299 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3300 | fputs ("@TLSDESC", file); | |
3301 | break; | |
3302 | case UNSPEC_TLSLD: | |
3303 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3304 | fputs ("@TLSDESC", file); | |
3305 | break; | |
3306 | case UNSPEC_TLSIE: | |
3307 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3308 | fputs ("@GOTTPOFF", file); | |
3309 | break; | |
3310 | case UNSPEC_TLSLE: | |
3311 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3312 | fputs ("@TPOFF", file); | |
3313 | break; | |
85a98076 KLC |
3314 | case UNSPEC_ICT: |
3315 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3316 | fputs ("@ICT", file); | |
3317 | break; | |
3318 | default: | |
3319 | return false; | |
3320 | } | |
3321 | return true; | |
3322 | } | |
3323 | else | |
3324 | return false; | |
3325 | } | |
3326 | ||
9304f876 CJW |
3327 | /* -- Output and Generation of Labels. */ |
3328 | ||
3329 | static void | |
3330 | nds32_asm_globalize_label (FILE *stream, const char *name) | |
3331 | { | |
3332 | fputs ("\t.global\t", stream); | |
3333 | assemble_name (stream, name); | |
3334 | fputs ("\n", stream); | |
3335 | } | |
3336 | ||
3337 | /* -- Output of Assembler Instructions. */ | |
3338 | ||
3339 | static void | |
3340 | nds32_print_operand (FILE *stream, rtx x, int code) | |
3341 | { | |
bfeb6685 | 3342 | HOST_WIDE_INT op_value = 0; |
a3b13564 KC |
3343 | HOST_WIDE_INT one_position; |
3344 | HOST_WIDE_INT zero_position; | |
e2286268 MC |
3345 | bool pick_lsb_p = false; |
3346 | bool pick_msb_p = false; | |
3347 | int regno; | |
3348 | ||
bfeb6685 CJW |
3349 | if (CONST_INT_P (x)) |
3350 | op_value = INTVAL (x); | |
9304f876 CJW |
3351 | |
3352 | switch (code) | |
3353 | { | |
3354 | case 0 : | |
3355 | /* Do nothing special. */ | |
3356 | break; | |
3357 | ||
a3b13564 KC |
3358 | case 'b': |
3359 | /* Use exact_log2() to search the 0-bit position. */ | |
3360 | gcc_assert (CONST_INT_P (x)); | |
3361 | zero_position = exact_log2 (~UINTVAL (x) & GET_MODE_MASK (SImode)); | |
3362 | gcc_assert (zero_position != -1); | |
3363 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, zero_position); | |
3364 | ||
3365 | /* No need to handle following process, so return immediately. */ | |
3366 | return; | |
3367 | ||
8656bbcf SC |
3368 | case 'e': |
3369 | gcc_assert (MEM_P (x) | |
3370 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3371 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT); | |
3372 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (XEXP (x, 0), 1))); | |
3373 | ||
3374 | /* No need to handle following process, so return immediately. */ | |
3375 | return; | |
7c32ef41 MC |
3376 | |
3377 | case 'v': | |
3378 | gcc_assert (CONST_INT_P (x) | |
3379 | && (INTVAL (x) == 0 | |
3380 | || INTVAL (x) == 8 | |
3381 | || INTVAL (x) == 16 | |
3382 | || INTVAL (x) == 24)); | |
3383 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8); | |
3384 | ||
3385 | /* No need to handle following process, so return immediately. */ | |
3386 | return; | |
3387 | ||
a3b13564 KC |
3388 | case 'B': |
3389 | /* Use exact_log2() to search the 1-bit position. */ | |
3390 | gcc_assert (CONST_INT_P (x)); | |
3391 | one_position = exact_log2 (UINTVAL (x) & GET_MODE_MASK (SImode)); | |
3392 | gcc_assert (one_position != -1); | |
3393 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, one_position); | |
3394 | ||
3395 | /* No need to handle following process, so return immediately. */ | |
3396 | return; | |
3397 | ||
e2286268 MC |
3398 | case 'L': |
3399 | /* X is supposed to be REG rtx. */ | |
3400 | gcc_assert (REG_P (x)); | |
3401 | /* Claim that we are going to pick LSB part of X. */ | |
3402 | pick_lsb_p = true; | |
3403 | break; | |
3404 | ||
3405 | case 'H': | |
3406 | /* X is supposed to be REG rtx. */ | |
3407 | gcc_assert (REG_P (x)); | |
3408 | /* Claim that we are going to pick MSB part of X. */ | |
3409 | pick_msb_p = true; | |
3410 | break; | |
3411 | ||
9304f876 CJW |
3412 | case 'V': |
3413 | /* 'x' is supposed to be CONST_INT, get the value. */ | |
3414 | gcc_assert (CONST_INT_P (x)); | |
9304f876 CJW |
3415 | |
3416 | /* According to the Andes architecture, | |
8a498f99 CJW |
3417 | the system/user register index range is 0 ~ 1023. |
3418 | In order to avoid conflict between user-specified-integer value | |
3419 | and enum-specified-register value, | |
3420 | the 'enum nds32_intrinsic_registers' value | |
3421 | in nds32_intrinsic.h starts from 1024. */ | |
9304f876 CJW |
3422 | if (op_value < 1024 && op_value >= 0) |
3423 | { | |
3424 | /* If user gives integer value directly (0~1023), | |
3425 | we just print out the value. */ | |
5af50159 | 3426 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, op_value); |
9304f876 CJW |
3427 | } |
3428 | else if (op_value < 0 | |
3429 | || op_value >= ((int) ARRAY_SIZE (nds32_intrinsic_register_names) | |
3430 | + 1024)) | |
3431 | { | |
3432 | /* The enum index value for array size is out of range. */ | |
3433 | error ("intrinsic register index is out of range"); | |
3434 | } | |
3435 | else | |
3436 | { | |
3437 | /* If user applies normal way with __NDS32_REG_XXX__ enum data, | |
3438 | we can print out register name. Remember to substract 1024. */ | |
3439 | fprintf (stream, "%s", | |
3440 | nds32_intrinsic_register_names[op_value - 1024]); | |
3441 | } | |
3442 | ||
3443 | /* No need to handle following process, so return immediately. */ | |
3444 | return; | |
3445 | ||
f1a0afe2 MC |
3446 | case 'R': /* cctl valck */ |
3447 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3448 | if (op_value < 0 || op_value > 4) | |
3449 | error ("CCTL intrinsic function subtype out of range!"); | |
3450 | fprintf (stream, "%s", nds32_cctl_names[op_value]); | |
3451 | return; | |
3452 | ||
3453 | case 'T': /* cctl idxwbinv */ | |
3454 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3455 | if (op_value < 0 || op_value > 4) | |
3456 | error ("CCTL intrinsic function subtype out of range!"); | |
3457 | fprintf (stream, "%s", nds32_cctl_names[op_value + 4]); | |
3458 | return; | |
3459 | ||
3460 | case 'U': /* cctl vawbinv */ | |
3461 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3462 | if (op_value < 0 || op_value > 4) | |
3463 | error ("CCTL intrinsic function subtype out of range!"); | |
3464 | fprintf (stream, "%s", nds32_cctl_names[op_value + 8]); | |
3465 | return; | |
3466 | ||
3467 | case 'X': /* cctl idxread */ | |
3468 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3469 | if (op_value < 0 || op_value > 4) | |
3470 | error ("CCTL intrinsic function subtype out of range!"); | |
3471 | fprintf (stream, "%s", nds32_cctl_names[op_value + 12]); | |
3472 | return; | |
3473 | ||
3474 | case 'W': /* cctl idxwitre */ | |
3475 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3476 | if (op_value < 0 || op_value > 4) | |
3477 | error ("CCTL intrinsic function subtype out of range!"); | |
3478 | fprintf (stream, "%s", nds32_cctl_names[op_value + 16]); | |
3479 | return; | |
3480 | ||
57aaf0cc MC |
3481 | case 'Z': /* dpref */ |
3482 | fprintf (stream, "%s", nds32_dpref_names[op_value]); | |
3483 | return; | |
3484 | ||
9304f876 CJW |
3485 | default : |
3486 | /* Unknown flag. */ | |
3487 | output_operand_lossage ("invalid operand output code"); | |
3488 | break; | |
3489 | } | |
3490 | ||
3491 | switch (GET_CODE (x)) | |
3492 | { | |
3493 | case LABEL_REF: | |
85a98076 KLC |
3494 | output_addr_const (stream, x); |
3495 | break; | |
3496 | ||
9304f876 CJW |
3497 | case SYMBOL_REF: |
3498 | output_addr_const (stream, x); | |
85a98076 KLC |
3499 | |
3500 | if (nds32_indirect_call_referenced_p (x)) | |
3501 | fprintf (stream, "@ICT"); | |
3502 | ||
9304f876 CJW |
3503 | break; |
3504 | ||
3505 | case REG: | |
e2286268 MC |
3506 | /* Print a Double-precision register name. */ |
3507 | if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode) | |
3508 | && NDS32_IS_FPR_REGNUM (REGNO (x))) | |
3509 | { | |
3510 | regno = REGNO (x); | |
3511 | if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno)) | |
3512 | { | |
3513 | output_operand_lossage ("invalid operand for code '%c'", code); | |
3514 | break; | |
3515 | } | |
3516 | fprintf (stream, "$fd%d", (regno - NDS32_FIRST_FPR_REGNUM) >> 1); | |
3517 | break; | |
3518 | } | |
3519 | ||
3520 | /* Print LSB or MSB part of register pair if the | |
3521 | constraint modifier 'L' or 'H' is specified. */ | |
3522 | if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode) | |
3523 | && NDS32_IS_GPR_REGNUM (REGNO (x))) | |
3524 | { | |
3525 | if ((pick_lsb_p && WORDS_BIG_ENDIAN) | |
3526 | || (pick_msb_p && !WORDS_BIG_ENDIAN)) | |
3527 | { | |
3528 | /* If we would like to print out LSB register under big-endian, | |
3529 | or print out MSB register under little-endian, we need to | |
3530 | increase register number. */ | |
3531 | regno = REGNO (x); | |
3532 | regno++; | |
3533 | fputs (reg_names[regno], stream); | |
3534 | break; | |
3535 | } | |
3536 | } | |
3537 | ||
9304f876 | 3538 | /* Forbid using static chain register ($r16) |
8a498f99 | 3539 | on reduced-set registers configuration. */ |
9304f876 CJW |
3540 | if (TARGET_REDUCED_REGS |
3541 | && REGNO (x) == STATIC_CHAIN_REGNUM) | |
3542 | sorry ("a nested function is not supported for reduced registers"); | |
3543 | ||
3544 | /* Normal cases, print out register name. */ | |
3545 | fputs (reg_names[REGNO (x)], stream); | |
3546 | break; | |
3547 | ||
3548 | case MEM: | |
cc8ca59e | 3549 | output_address (GET_MODE (x), XEXP (x, 0)); |
9304f876 CJW |
3550 | break; |
3551 | ||
e2286268 MC |
3552 | case HIGH: |
3553 | if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE) | |
3554 | { | |
3555 | const REAL_VALUE_TYPE *rv; | |
3556 | long val; | |
3557 | gcc_assert (GET_MODE (x) == SFmode); | |
3558 | ||
3559 | rv = CONST_DOUBLE_REAL_VALUE (XEXP (x, 0)); | |
3560 | REAL_VALUE_TO_TARGET_SINGLE (*rv, val); | |
3561 | ||
3562 | fprintf (stream, "hi20(0x%lx)", val); | |
3563 | } | |
3564 | else | |
3565 | gcc_unreachable (); | |
3566 | break; | |
3567 | ||
3568 | case CONST_DOUBLE: | |
3569 | const REAL_VALUE_TYPE *rv; | |
3570 | long val; | |
3571 | gcc_assert (GET_MODE (x) == SFmode); | |
3572 | ||
3573 | rv = CONST_DOUBLE_REAL_VALUE (x); | |
3574 | REAL_VALUE_TO_TARGET_SINGLE (*rv, val); | |
3575 | ||
3576 | fprintf (stream, "0x%lx", val); | |
3577 | break; | |
3578 | ||
9304f876 CJW |
3579 | case CODE_LABEL: |
3580 | case CONST_INT: | |
3581 | case CONST: | |
3582 | output_addr_const (stream, x); | |
3583 | break; | |
3584 | ||
7c32ef41 MC |
3585 | case CONST_VECTOR: |
3586 | fprintf (stream, HOST_WIDE_INT_PRINT_HEX, const_vector_to_hwint (x)); | |
3587 | break; | |
3588 | ||
85a98076 KLC |
3589 | case LO_SUM: |
3590 | /* This is a special case for inline assembly using memory address 'p'. | |
3591 | The inline assembly code is expected to use pesudo instruction | |
3592 | for the operand. EX: la */ | |
3593 | output_addr_const (stream, XEXP(x, 1)); | |
3594 | break; | |
3595 | ||
9304f876 CJW |
3596 | default: |
3597 | /* Generally, output_addr_const () is able to handle most cases. | |
8a498f99 CJW |
3598 | We want to see what CODE could appear, |
3599 | so we use gcc_unreachable() to stop it. */ | |
9304f876 CJW |
3600 | debug_rtx (x); |
3601 | gcc_unreachable (); | |
3602 | break; | |
3603 | } | |
3604 | } | |
3605 | ||
3606 | static void | |
85a98076 KLC |
3607 | nds32_print_operand_address (FILE *stream, |
3608 | machine_mode mode ATTRIBUTE_UNUSED, | |
3609 | rtx x) | |
9304f876 CJW |
3610 | { |
3611 | rtx op0, op1; | |
3612 | ||
3613 | switch (GET_CODE (x)) | |
3614 | { | |
3615 | case SYMBOL_REF: | |
3616 | case CONST: | |
3617 | /* [ + symbol_ref] */ | |
3618 | /* [ + const_addr], where const_addr = symbol_ref + const_int */ | |
3619 | fputs ("[ + ", stream); | |
3620 | output_addr_const (stream, x); | |
3621 | fputs ("]", stream); | |
3622 | break; | |
3623 | ||
85a98076 KLC |
3624 | case LO_SUM: |
3625 | /* This is a special case for inline assembly using memory operand 'm'. | |
3626 | The inline assembly code is expected to use pesudo instruction | |
3627 | for the operand. EX: [ls].[bhw] */ | |
3628 | fputs ("[ + ", stream); | |
3629 | op1 = XEXP (x, 1); | |
3630 | output_addr_const (stream, op1); | |
3631 | fputs ("]", stream); | |
3632 | break; | |
3633 | ||
9304f876 CJW |
3634 | case REG: |
3635 | /* Forbid using static chain register ($r16) | |
8a498f99 | 3636 | on reduced-set registers configuration. */ |
9304f876 CJW |
3637 | if (TARGET_REDUCED_REGS |
3638 | && REGNO (x) == STATIC_CHAIN_REGNUM) | |
3639 | sorry ("a nested function is not supported for reduced registers"); | |
3640 | ||
3641 | /* [Ra] */ | |
3642 | fprintf (stream, "[%s]", reg_names[REGNO (x)]); | |
3643 | break; | |
3644 | ||
3645 | case PLUS: | |
3646 | op0 = XEXP (x, 0); | |
3647 | op1 = XEXP (x, 1); | |
3648 | ||
3649 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 3650 | on reduced-set registers configuration. */ |
9304f876 CJW |
3651 | if (TARGET_REDUCED_REGS |
3652 | && REG_P (op0) | |
3653 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
3654 | sorry ("a nested function is not supported for reduced registers"); | |
3655 | /* Checking op1, forbid using static chain register ($r16) | |
8a498f99 | 3656 | on reduced-set registers configuration. */ |
9304f876 CJW |
3657 | if (TARGET_REDUCED_REGS |
3658 | && REG_P (op1) | |
3659 | && REGNO (op1) == STATIC_CHAIN_REGNUM) | |
3660 | sorry ("a nested function is not supported for reduced registers"); | |
3661 | ||
3662 | if (REG_P (op0) && CONST_INT_P (op1)) | |
3663 | { | |
3664 | /* [Ra + imm] */ | |
5af50159 KC |
3665 | fprintf (stream, "[%s + (" HOST_WIDE_INT_PRINT_DEC ")]", |
3666 | reg_names[REGNO (op0)], INTVAL (op1)); | |
9304f876 CJW |
3667 | } |
3668 | else if (REG_P (op0) && REG_P (op1)) | |
3669 | { | |
3670 | /* [Ra + Rb] */ | |
3671 | fprintf (stream, "[%s + %s]", | |
3672 | reg_names[REGNO (op0)], reg_names[REGNO (op1)]); | |
3673 | } | |
3674 | else if (GET_CODE (op0) == MULT && REG_P (op1)) | |
3675 | { | |
3676 | /* [Ra + Rb << sv] | |
3677 | From observation, the pattern looks like: | |
3678 | (plus:SI (mult:SI (reg:SI 58) | |
8a498f99 CJW |
3679 | (const_int 4 [0x4])) |
3680 | (reg/f:SI 57)) */ | |
9304f876 CJW |
3681 | int sv; |
3682 | ||
3683 | /* We need to set sv to output shift value. */ | |
3684 | if (INTVAL (XEXP (op0, 1)) == 1) | |
3685 | sv = 0; | |
3686 | else if (INTVAL (XEXP (op0, 1)) == 2) | |
3687 | sv = 1; | |
3688 | else if (INTVAL (XEXP (op0, 1)) == 4) | |
3689 | sv = 2; | |
f62a2af5 CJW |
3690 | else if (INTVAL (XEXP (op0, 1)) == 8) |
3691 | sv = 3; | |
9304f876 CJW |
3692 | else |
3693 | gcc_unreachable (); | |
3694 | ||
3695 | fprintf (stream, "[%s + %s << %d]", | |
3696 | reg_names[REGNO (op1)], | |
3697 | reg_names[REGNO (XEXP (op0, 0))], | |
3698 | sv); | |
3699 | } | |
7c32ef41 MC |
3700 | else if (GET_CODE (op0) == ASHIFT && REG_P (op1)) |
3701 | { | |
3702 | /* [Ra + Rb << sv] | |
3703 | In normal, ASHIFT can be converted to MULT like above case. | |
3704 | But when the address rtx does not go through canonicalize_address | |
3705 | defined in fwprop, we'll need this case. */ | |
3706 | int sv = INTVAL (XEXP (op0, 1)); | |
3707 | gcc_assert (sv <= 3 && sv >=0); | |
3708 | ||
3709 | fprintf (stream, "[%s + %s << %d]", | |
3710 | reg_names[REGNO (op1)], | |
3711 | reg_names[REGNO (XEXP (op0, 0))], | |
3712 | sv); | |
3713 | } | |
9304f876 CJW |
3714 | else |
3715 | { | |
3716 | /* The control flow is not supposed to be here. */ | |
3717 | debug_rtx (x); | |
3718 | gcc_unreachable (); | |
3719 | } | |
3720 | ||
3721 | break; | |
3722 | ||
3723 | case POST_MODIFY: | |
3724 | /* (post_modify (regA) (plus (regA) (regB))) | |
8a498f99 CJW |
3725 | (post_modify (regA) (plus (regA) (const_int))) |
3726 | We would like to extract | |
3727 | regA and regB (or const_int) from plus rtx. */ | |
9304f876 CJW |
3728 | op0 = XEXP (XEXP (x, 1), 0); |
3729 | op1 = XEXP (XEXP (x, 1), 1); | |
3730 | ||
3731 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 3732 | on reduced-set registers configuration. */ |
9304f876 CJW |
3733 | if (TARGET_REDUCED_REGS |
3734 | && REG_P (op0) | |
3735 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
3736 | sorry ("a nested function is not supported for reduced registers"); | |
3737 | /* Checking op1, forbid using static chain register ($r16) | |
8a498f99 | 3738 | on reduced-set registers configuration. */ |
9304f876 CJW |
3739 | if (TARGET_REDUCED_REGS |
3740 | && REG_P (op1) | |
3741 | && REGNO (op1) == STATIC_CHAIN_REGNUM) | |
3742 | sorry ("a nested function is not supported for reduced registers"); | |
3743 | ||
3744 | if (REG_P (op0) && REG_P (op1)) | |
3745 | { | |
3746 | /* [Ra], Rb */ | |
3747 | fprintf (stream, "[%s], %s", | |
3748 | reg_names[REGNO (op0)], reg_names[REGNO (op1)]); | |
3749 | } | |
3750 | else if (REG_P (op0) && CONST_INT_P (op1)) | |
3751 | { | |
3752 | /* [Ra], imm */ | |
5af50159 KC |
3753 | fprintf (stream, "[%s], " HOST_WIDE_INT_PRINT_DEC, |
3754 | reg_names[REGNO (op0)], INTVAL (op1)); | |
9304f876 CJW |
3755 | } |
3756 | else | |
3757 | { | |
3758 | /* The control flow is not supposed to be here. */ | |
3759 | debug_rtx (x); | |
3760 | gcc_unreachable (); | |
3761 | } | |
3762 | ||
3763 | break; | |
3764 | ||
3765 | case POST_INC: | |
3766 | case POST_DEC: | |
3767 | op0 = XEXP (x, 0); | |
3768 | ||
3769 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 3770 | on reduced-set registers configuration. */ |
9304f876 CJW |
3771 | if (TARGET_REDUCED_REGS |
3772 | && REG_P (op0) | |
3773 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
3774 | sorry ("a nested function is not supported for reduced registers"); | |
3775 | ||
3776 | if (REG_P (op0)) | |
3777 | { | |
3778 | /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4" | |
3779 | The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. | |
3780 | We only need to deal with register Ra. */ | |
3781 | fprintf (stream, "[%s]", reg_names[REGNO (op0)]); | |
3782 | } | |
3783 | else | |
3784 | { | |
3785 | /* The control flow is not supposed to be here. */ | |
3786 | debug_rtx (x); | |
3787 | gcc_unreachable (); | |
3788 | } | |
3789 | ||
3790 | break; | |
3791 | ||
3792 | default : | |
3793 | /* Generally, output_addr_const () is able to handle most cases. | |
8a498f99 CJW |
3794 | We want to see what CODE could appear, |
3795 | so we use gcc_unreachable() to stop it. */ | |
9304f876 CJW |
3796 | debug_rtx (x); |
3797 | gcc_unreachable (); | |
3798 | break; | |
3799 | } | |
3800 | } | |
3801 | ||
e2286268 MC |
3802 | /* -- Assembler Commands for Exception Regions. */ |
3803 | ||
3804 | static rtx | |
3805 | nds32_dwarf_register_span (rtx reg) | |
3806 | { | |
3807 | rtx dwarf_high, dwarf_low; | |
3808 | rtx dwarf_single; | |
3809 | machine_mode mode; | |
3810 | int regno; | |
3811 | ||
3812 | mode = GET_MODE (reg); | |
3813 | regno = REGNO (reg); | |
3814 | ||
3815 | /* We need to adjust dwarf register information for floating-point registers | |
3816 | rather than using default register number mapping. */ | |
3817 | if (regno >= NDS32_FIRST_FPR_REGNUM | |
3818 | && regno <= NDS32_LAST_FPR_REGNUM) | |
3819 | { | |
3820 | if (mode == DFmode || mode == SCmode) | |
3821 | { | |
3822 | /* By default, GCC maps increasing register numbers to increasing | |
3823 | memory locations, but paired FPRs in NDS32 target are always | |
3824 | big-endian, i.e.: | |
3825 | ||
3826 | fd0 : fs0 fs1 | |
3827 | (MSB) (LSB) | |
3828 | ||
3829 | We must return parallel rtx to represent such layout. */ | |
3830 | dwarf_high = gen_rtx_REG (word_mode, regno); | |
3831 | dwarf_low = gen_rtx_REG (word_mode, regno + 1); | |
3832 | return gen_rtx_PARALLEL (VOIDmode, | |
3833 | gen_rtvec (2, dwarf_low, dwarf_high)); | |
3834 | } | |
3835 | else if (mode == DCmode) | |
3836 | { | |
3837 | rtx dwarf_high_re = gen_rtx_REG (word_mode, regno); | |
3838 | rtx dwarf_low_re = gen_rtx_REG (word_mode, regno + 1); | |
3839 | rtx dwarf_high_im = gen_rtx_REG (word_mode, regno); | |
3840 | rtx dwarf_low_im = gen_rtx_REG (word_mode, regno + 1); | |
3841 | return gen_rtx_PARALLEL (VOIDmode, | |
3842 | gen_rtvec (4, dwarf_low_re, dwarf_high_re, | |
3843 | dwarf_high_im, dwarf_low_im)); | |
3844 | } | |
3845 | else if (mode == SFmode || mode == SImode) | |
3846 | { | |
3847 | /* Create new dwarf information with adjusted register number. */ | |
3848 | dwarf_single = gen_rtx_REG (word_mode, regno); | |
3849 | return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, dwarf_single)); | |
3850 | } | |
3851 | else | |
3852 | { | |
3853 | /* We should not be here. */ | |
3854 | gcc_unreachable (); | |
3855 | } | |
3856 | } | |
3857 | ||
3858 | return NULL_RTX; | |
3859 | } | |
3860 | ||
3861 | /* Map internal gcc register numbers to DWARF2 register numbers. */ | |
3862 | ||
3863 | unsigned int | |
3864 | nds32_dbx_register_number (unsigned int regno) | |
3865 | { | |
3866 | /* The nds32 port in GDB maintains a mapping between dwarf register | |
3867 | number and displayed register name. For backward compatibility to | |
3868 | previous toolchain, currently our gdb still has four registers | |
3869 | (d0.l, d0.h, d1.l, and d1.h) between GPR and FPR while compiler | |
3870 | does not count those four registers in its register number table. | |
3871 | So we have to add 4 on its register number and then create new | |
3872 | dwarf information. Hopefully we can discard such workaround | |
3873 | in the future. */ | |
3874 | if (NDS32_IS_FPR_REGNUM (regno)) | |
3875 | return regno + 4; | |
3876 | ||
3877 | return regno; | |
3878 | } | |
3879 | ||
9304f876 CJW |
3880 | \f |
3881 | /* Defining target-specific uses of __attribute__. */ | |
3882 | ||
3883 | /* Add some checking after merging attributes. */ | |
3884 | static tree | |
3885 | nds32_merge_decl_attributes (tree olddecl, tree newdecl) | |
3886 | { | |
3887 | tree combined_attrs; | |
3888 | ||
3889 | /* Create combined attributes. */ | |
3890 | combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl), | |
3891 | DECL_ATTRIBUTES (newdecl)); | |
3892 | ||
59043e75 | 3893 | /* Since newdecl is acutally a duplicate of olddecl, |
9304f876 CJW |
3894 | we can take olddecl for some operations. */ |
3895 | if (TREE_CODE (olddecl) == FUNCTION_DECL) | |
3896 | { | |
3897 | /* Check isr-specific attributes conflict. */ | |
3898 | nds32_check_isr_attrs_conflict (olddecl, combined_attrs); | |
3899 | } | |
3900 | ||
3901 | return combined_attrs; | |
3902 | } | |
3903 | ||
3904 | /* Add some checking when inserting attributes. */ | |
3905 | static void | |
3906 | nds32_insert_attributes (tree decl, tree *attributes) | |
3907 | { | |
85a98076 KLC |
3908 | /* A "indirect_call" function attribute implies "noinline" and "noclone" |
3909 | for elf toolchain to support ROM patch mechanism. */ | |
3910 | if (TREE_CODE (decl) == FUNCTION_DECL | |
3911 | && lookup_attribute ("indirect_call", *attributes) != NULL) | |
3912 | { | |
3913 | tree new_attrs = *attributes; | |
3914 | ||
3915 | if (lookup_attribute ("noinline", new_attrs) == NULL) | |
3916 | new_attrs = tree_cons (get_identifier ("noinline"), NULL, new_attrs); | |
3917 | if (lookup_attribute ("noclone", new_attrs) == NULL) | |
3918 | new_attrs = tree_cons (get_identifier ("noclone"), NULL, new_attrs); | |
3919 | ||
3920 | if (!TREE_PUBLIC (decl)) | |
3921 | error("indirect_call attribute can't apply for static function"); | |
3922 | ||
3923 | *attributes = new_attrs; | |
3924 | } | |
3925 | ||
9304f876 CJW |
3926 | /* For function declaration, we need to check isr-specific attributes: |
3927 | 1. Call nds32_check_isr_attrs_conflict() to check any conflict. | |
3928 | 2. Check valid integer value for interrupt/exception. | |
3929 | 3. Check valid integer value for reset. | |
3930 | 4. Check valid function for nmi/warm. */ | |
3931 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
3932 | { | |
3933 | tree func_attrs; | |
3934 | tree intr, excp, reset; | |
3935 | ||
3936 | /* Pick up function attributes. */ | |
3937 | func_attrs = *attributes; | |
3938 | ||
3939 | /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */ | |
3940 | nds32_check_isr_attrs_conflict (decl, func_attrs); | |
3941 | ||
3942 | /* Now we are starting to check valid id value | |
8a498f99 CJW |
3943 | for interrupt/exception/reset. |
3944 | Note that we ONLY check its validity here. | |
3945 | To construct isr vector information, it is still performed | |
3946 | by nds32_construct_isr_vectors_information(). */ | |
9304f876 CJW |
3947 | intr = lookup_attribute ("interrupt", func_attrs); |
3948 | excp = lookup_attribute ("exception", func_attrs); | |
3949 | reset = lookup_attribute ("reset", func_attrs); | |
3950 | ||
3951 | if (intr || excp) | |
3952 | { | |
3953 | /* Deal with interrupt/exception. */ | |
3954 | tree id_list; | |
3955 | unsigned int lower_bound, upper_bound; | |
3956 | ||
3957 | /* The way to handle interrupt or exception is the same, | |
3958 | we just need to take care of actual vector number. | |
3959 | For interrupt(0..63), the actual vector number is (9..72). | |
3960 | For exception(1..8), the actual vector number is (1..8). */ | |
3961 | lower_bound = (intr) ? (0) : (1); | |
3962 | upper_bound = (intr) ? (63) : (8); | |
3963 | ||
3964 | /* Prepare id list so that we can traverse id value. */ | |
3965 | id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp)); | |
3966 | ||
3967 | /* 2. Check valid integer value for interrupt/exception. */ | |
3968 | while (id_list) | |
3969 | { | |
3970 | tree id; | |
3971 | ||
3972 | /* Pick up each vector id value. */ | |
3973 | id = TREE_VALUE (id_list); | |
3974 | /* Issue error if it is not a valid integer value. */ | |
3975 | if (TREE_CODE (id) != INTEGER_CST | |
8e6cdc90 RS |
3976 | || wi::ltu_p (wi::to_wide (id), lower_bound) |
3977 | || wi::gtu_p (wi::to_wide (id), upper_bound)) | |
9304f876 CJW |
3978 | error ("invalid id value for interrupt/exception attribute"); |
3979 | ||
3980 | /* Advance to next id. */ | |
3981 | id_list = TREE_CHAIN (id_list); | |
3982 | } | |
3983 | } | |
3984 | else if (reset) | |
3985 | { | |
3986 | /* Deal with reset. */ | |
3987 | tree id_list; | |
3988 | tree id; | |
3989 | tree nmi, warm; | |
3990 | unsigned int lower_bound; | |
3991 | unsigned int upper_bound; | |
3992 | ||
3993 | /* Prepare id_list and identify id value so that | |
3994 | we can check if total number of vectors is valid. */ | |
3995 | id_list = TREE_VALUE (reset); | |
3996 | id = TREE_VALUE (id_list); | |
3997 | ||
3998 | /* The maximum numbers for user's interrupt is 64. */ | |
3999 | lower_bound = 0; | |
4000 | upper_bound = 64; | |
4001 | ||
4002 | /* 3. Check valid integer value for reset. */ | |
4003 | if (TREE_CODE (id) != INTEGER_CST | |
8e6cdc90 RS |
4004 | || wi::ltu_p (wi::to_wide (id), lower_bound) |
4005 | || wi::gtu_p (wi::to_wide (id), upper_bound)) | |
9304f876 CJW |
4006 | error ("invalid id value for reset attribute"); |
4007 | ||
4008 | /* 4. Check valid function for nmi/warm. */ | |
4009 | nmi = lookup_attribute ("nmi", func_attrs); | |
4010 | warm = lookup_attribute ("warm", func_attrs); | |
4011 | ||
4012 | if (nmi != NULL_TREE) | |
4013 | { | |
4014 | tree nmi_func_list; | |
4015 | tree nmi_func; | |
4016 | ||
4017 | nmi_func_list = TREE_VALUE (nmi); | |
4018 | nmi_func = TREE_VALUE (nmi_func_list); | |
4019 | ||
4020 | /* Issue error if it is not a valid nmi function. */ | |
4021 | if (TREE_CODE (nmi_func) != IDENTIFIER_NODE) | |
4022 | error ("invalid nmi function for reset attribute"); | |
4023 | } | |
4024 | ||
4025 | if (warm != NULL_TREE) | |
4026 | { | |
4027 | tree warm_func_list; | |
4028 | tree warm_func; | |
4029 | ||
4030 | warm_func_list = TREE_VALUE (warm); | |
4031 | warm_func = TREE_VALUE (warm_func_list); | |
4032 | ||
4033 | /* Issue error if it is not a valid warm function. */ | |
4034 | if (TREE_CODE (warm_func) != IDENTIFIER_NODE) | |
4035 | error ("invalid warm function for reset attribute"); | |
4036 | } | |
4037 | } | |
4038 | else | |
4039 | { | |
4040 | /* No interrupt, exception, or reset attribute is set. */ | |
4041 | return; | |
4042 | } | |
4043 | } | |
4044 | } | |
4045 | ||
4046 | static bool | |
4047 | nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED, | |
4048 | tree pop_target ATTRIBUTE_UNUSED) | |
4049 | { | |
4050 | /* Currently, we do not parse any pragma target by ourself, | |
4051 | so just simply return false. */ | |
4052 | return false; | |
4053 | } | |
4054 | ||
4055 | static void | |
4056 | nds32_option_override (void) | |
4057 | { | |
4058 | /* After all the command options have been parsed, | |
4059 | we shall deal with some flags for changing compiler settings. */ | |
4060 | ||
4061 | /* At first, we check if we have to strictly | |
4062 | set some flags based on ISA family. */ | |
4063 | if (TARGET_ISA_V2) | |
4064 | { | |
4065 | /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */ | |
4066 | target_flags &= ~MASK_V3PUSH; | |
4067 | } | |
4068 | if (TARGET_ISA_V3) | |
4069 | { | |
4070 | /* Under V3 ISA, currently nothing should be strictly set. */ | |
4071 | } | |
4072 | if (TARGET_ISA_V3M) | |
4073 | { | |
4074 | /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */ | |
4075 | target_flags |= MASK_REDUCED_REGS; | |
aa4b851c CJW |
4076 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */ |
4077 | target_flags &= ~MASK_EXT_PERF; | |
4078 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */ | |
4079 | target_flags &= ~MASK_EXT_PERF2; | |
4080 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */ | |
4081 | target_flags &= ~MASK_EXT_STRING; | |
b26fa4f9 KLC |
4082 | |
4083 | if (flag_pic) | |
4084 | error ("not support -fpic option for v3m toolchain"); | |
9304f876 CJW |
4085 | } |
4086 | ||
4087 | /* See if we are using reduced-set registers: | |
4088 | $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31 | |
4089 | If so, we must forbid using $r11~$r14, $r16~$r27. */ | |
4090 | if (TARGET_REDUCED_REGS) | |
4091 | { | |
4092 | int r; | |
4093 | ||
4094 | /* Prevent register allocator from | |
8a498f99 | 4095 | choosing it as doing register allocation. */ |
9304f876 CJW |
4096 | for (r = 11; r <= 14; r++) |
4097 | fixed_regs[r] = call_used_regs[r] = 1; | |
4098 | for (r = 16; r <= 27; r++) | |
4099 | fixed_regs[r] = call_used_regs[r] = 1; | |
4100 | } | |
4101 | ||
2140297c CJW |
4102 | /* See if user explicitly would like to use fp-as-gp optimization. |
4103 | If so, we must prevent $fp from being allocated | |
4104 | during register allocation. */ | |
4105 | if (TARGET_FORCE_FP_AS_GP) | |
4106 | fixed_regs[FP_REGNUM] = call_used_regs[FP_REGNUM] = 1; | |
4107 | ||
9304f876 CJW |
4108 | if (!TARGET_16_BIT) |
4109 | { | |
4110 | /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */ | |
4111 | target_flags &= ~MASK_V3PUSH; | |
4112 | } | |
4113 | ||
e2286268 MC |
4114 | if (TARGET_HARD_FLOAT && !(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) |
4115 | { | |
4116 | if (nds32_arch_option == ARCH_V3S || nds32_arch_option == ARCH_V3F) | |
4117 | error ("Disable FPU ISA, " | |
4118 | "the ABI option must be enable '-mfloat-abi=soft'"); | |
4119 | else | |
4120 | error ("'-mabi=2fp+' option only support when FPU available, " | |
4121 | "must be enable '-mext-fpu-sp' or '-mext-fpu-dp'"); | |
4122 | } | |
4123 | ||
19c93809 | 4124 | nds32_init_rtx_costs (); |
c4d8d050 CJW |
4125 | |
4126 | nds32_register_passes (); | |
9304f876 CJW |
4127 | } |
4128 | ||
4129 | \f | |
4130 | /* Miscellaneous Parameters. */ | |
4131 | ||
823835a9 CJW |
4132 | static rtx_insn * |
4133 | nds32_md_asm_adjust (vec<rtx> &outputs ATTRIBUTE_UNUSED, | |
4134 | vec<rtx> &inputs ATTRIBUTE_UNUSED, | |
4135 | vec<const char *> &constraints ATTRIBUTE_UNUSED, | |
4136 | vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs) | |
4137 | { | |
b28c01ab CJW |
4138 | if (!flag_inline_asm_r15) |
4139 | { | |
4140 | clobbers.safe_push (gen_rtx_REG (SImode, TA_REGNUM)); | |
4141 | SET_HARD_REG_BIT (clobbered_regs, TA_REGNUM); | |
4142 | } | |
823835a9 CJW |
4143 | return NULL; |
4144 | } | |
4145 | ||
9304f876 CJW |
4146 | static void |
4147 | nds32_init_builtins (void) | |
4148 | { | |
aaa44d2d | 4149 | nds32_init_builtins_impl (); |
9304f876 CJW |
4150 | } |
4151 | ||
7a12ea32 MC |
4152 | static tree |
4153 | nds32_builtin_decl (unsigned code, bool initialize_p) | |
4154 | { | |
4155 | /* Implement in nds32-intrinsic.c. */ | |
4156 | return nds32_builtin_decl_impl (code, initialize_p); | |
4157 | } | |
4158 | ||
9304f876 CJW |
4159 | static rtx |
4160 | nds32_expand_builtin (tree exp, | |
4161 | rtx target, | |
aaa44d2d | 4162 | rtx subtarget, |
ef4bddc2 | 4163 | machine_mode mode, |
aaa44d2d | 4164 | int ignore) |
9304f876 | 4165 | { |
aaa44d2d | 4166 | return nds32_expand_builtin_impl (exp, target, subtarget, mode, ignore); |
9304f876 CJW |
4167 | } |
4168 | ||
4169 | ||
4170 | /* ------------------------------------------------------------------------ */ | |
4171 | ||
4172 | /* PART 4: Implemet extern function definitions, | |
4173 | the prototype is in nds32-protos.h. */ | |
72b7e5e1 KC |
4174 | \f |
4175 | /* Run-time Target Specification. */ | |
4176 | ||
4177 | void | |
4178 | nds32_cpu_cpp_builtins(struct cpp_reader *pfile) | |
4179 | { | |
4180 | #define builtin_define(TXT) cpp_define (pfile, TXT) | |
4181 | #define builtin_assert(TXT) cpp_assert (pfile, TXT) | |
4182 | builtin_define ("__nds32__"); | |
4183 | builtin_define ("__NDS32__"); | |
4184 | ||
e2286268 MC |
4185 | if (TARGET_HARD_FLOAT) |
4186 | builtin_define ("__NDS32_ABI_2FP_PLUS__"); | |
4187 | else | |
4188 | builtin_define ("__NDS32_ABI_2__"); | |
4189 | ||
72b7e5e1 KC |
4190 | if (TARGET_ISA_V2) |
4191 | builtin_define ("__NDS32_ISA_V2__"); | |
4192 | if (TARGET_ISA_V3) | |
4193 | builtin_define ("__NDS32_ISA_V3__"); | |
4194 | if (TARGET_ISA_V3M) | |
4195 | builtin_define ("__NDS32_ISA_V3M__"); | |
4196 | ||
e2286268 MC |
4197 | if (TARGET_FPU_SINGLE) |
4198 | builtin_define ("__NDS32_EXT_FPU_SP__"); | |
4199 | if (TARGET_FPU_DOUBLE) | |
4200 | builtin_define ("__NDS32_EXT_FPU_DP__"); | |
4201 | ||
4202 | if (TARGET_EXT_FPU_FMA) | |
4203 | builtin_define ("__NDS32_EXT_FPU_FMA__"); | |
4204 | if (NDS32_EXT_FPU_DOT_E) | |
4205 | builtin_define ("__NDS32_EXT_FPU_DOT_E__"); | |
4206 | if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
4207 | { | |
4208 | switch (nds32_fp_regnum) | |
4209 | { | |
4210 | case 0: | |
4211 | case 4: | |
4212 | builtin_define ("__NDS32_EXT_FPU_CONFIG_0__"); | |
4213 | break; | |
4214 | case 1: | |
4215 | case 5: | |
4216 | builtin_define ("__NDS32_EXT_FPU_CONFIG_1__"); | |
4217 | break; | |
4218 | case 2: | |
4219 | case 6: | |
4220 | builtin_define ("__NDS32_EXT_FPU_CONFIG_2__"); | |
4221 | break; | |
4222 | case 3: | |
4223 | case 7: | |
4224 | builtin_define ("__NDS32_EXT_FPU_CONFIG_3__"); | |
4225 | break; | |
4226 | default: | |
4227 | abort (); | |
4228 | } | |
4229 | } | |
4230 | ||
72b7e5e1 KC |
4231 | if (TARGET_BIG_ENDIAN) |
4232 | builtin_define ("__NDS32_EB__"); | |
4233 | else | |
4234 | builtin_define ("__NDS32_EL__"); | |
4235 | ||
4236 | if (TARGET_REDUCED_REGS) | |
4237 | builtin_define ("__NDS32_REDUCED_REGS__"); | |
4238 | if (TARGET_CMOV) | |
4239 | builtin_define ("__NDS32_CMOV__"); | |
4240 | if (TARGET_EXT_PERF) | |
4241 | builtin_define ("__NDS32_EXT_PERF__"); | |
4242 | if (TARGET_EXT_PERF2) | |
4243 | builtin_define ("__NDS32_EXT_PERF2__"); | |
4244 | if (TARGET_EXT_STRING) | |
4245 | builtin_define ("__NDS32_EXT_STRING__"); | |
4246 | if (TARGET_16_BIT) | |
4247 | builtin_define ("__NDS32_16_BIT__"); | |
4248 | if (TARGET_GP_DIRECT) | |
4249 | builtin_define ("__NDS32_GP_DIRECT__"); | |
ff77f6e8 KC |
4250 | if (TARGET_VH) |
4251 | builtin_define ("__NDS32_VH__"); | |
7c32ef41 MC |
4252 | if (NDS32_EXT_DSP_P ()) |
4253 | builtin_define ("__NDS32_EXT_DSP__"); | |
72b7e5e1 KC |
4254 | |
4255 | if (TARGET_BIG_ENDIAN) | |
4256 | builtin_define ("__big_endian__"); | |
4257 | ||
4258 | builtin_assert ("cpu=nds32"); | |
4259 | builtin_assert ("machine=nds32"); | |
e2286268 MC |
4260 | |
4261 | if (TARGET_HARD_FLOAT) | |
4262 | builtin_define ("__NDS32_ABI_2FP_PLUS"); | |
4263 | else | |
4264 | builtin_define ("__NDS32_ABI_2"); | |
4265 | ||
72b7e5e1 KC |
4266 | #undef builtin_define |
4267 | #undef builtin_assert | |
4268 | } | |
4269 | ||
9304f876 CJW |
4270 | \f |
4271 | /* Defining Data Structures for Per-function Information. */ | |
4272 | ||
4273 | void | |
4274 | nds32_init_expanders (void) | |
4275 | { | |
4276 | /* Arrange to initialize and mark the machine per-function status. */ | |
4277 | init_machine_status = nds32_init_machine_status; | |
4278 | } | |
4279 | ||
4280 | \f | |
4281 | /* Register Usage. */ | |
4282 | ||
5e6ae0cc CJW |
4283 | /* -- Order of Allocation of Registers. */ |
4284 | ||
4285 | void | |
4286 | nds32_adjust_reg_alloc_order (void) | |
4287 | { | |
4288 | const int nds32_reg_alloc_order[] = REG_ALLOC_ORDER; | |
4289 | ||
4290 | /* Copy the default register allocation order, which is designed | |
4291 | to optimize for code size. */ | |
4292 | memcpy(reg_alloc_order, nds32_reg_alloc_order, sizeof (reg_alloc_order)); | |
4293 | ||
4294 | /* Adjust few register allocation order when optimizing for speed. */ | |
4295 | if (!optimize_size) | |
4296 | { | |
4297 | memcpy (reg_alloc_order, nds32_reg_alloc_order_for_speed, | |
4298 | sizeof (nds32_reg_alloc_order_for_speed)); | |
4299 | } | |
4300 | } | |
4301 | ||
9304f876 CJW |
4302 | /* -- How Values Fit in Registers. */ |
4303 | ||
e2286268 MC |
4304 | static unsigned |
4305 | nds32_hard_regno_nregs (unsigned regno ATTRIBUTE_UNUSED, | |
4306 | machine_mode mode) | |
4307 | { | |
4308 | return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); | |
4309 | } | |
4310 | ||
f939c3e6 RS |
4311 | /* Implement TARGET_HARD_REGNO_MODE_OK. */ |
4312 | ||
4313 | static bool | |
4314 | nds32_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
9304f876 | 4315 | { |
e2286268 | 4316 | if (regno > FIRST_PSEUDO_REGISTER) |
f939c3e6 | 4317 | return true; |
9304f876 | 4318 | |
e2286268 MC |
4319 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) && NDS32_IS_FPR_REGNUM (regno)) |
4320 | { | |
4321 | if (NDS32_IS_EXT_FPR_REGNUM(regno)) | |
4322 | return (NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) && (mode == DFmode)); | |
4323 | else if (mode == SFmode || mode == SImode) | |
4324 | return NDS32_FPR_REGNO_OK_FOR_SINGLE (regno); | |
4325 | else if (mode == DFmode) | |
4326 | return NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno); | |
4327 | ||
4328 | return false; | |
4329 | } | |
4330 | ||
4331 | /* Restrict double-word quantities to even register pairs. */ | |
4332 | if (regno <= NDS32_LAST_GPR_REGNUM) | |
4333 | return (targetm.hard_regno_nregs (regno, mode) == 1 | |
4334 | || !((regno) & 1)); | |
4335 | ||
f939c3e6 | 4336 | return false; |
9304f876 CJW |
4337 | } |
4338 | ||
99e1629f RS |
4339 | /* Implement TARGET_MODES_TIEABLE_P. We can use general registers to |
4340 | tie QI/HI/SI modes together. */ | |
4341 | ||
4342 | static bool | |
4343 | nds32_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
4344 | { | |
e2286268 MC |
4345 | if ((GET_MODE_CLASS (mode1) == MODE_INT |
4346 | && GET_MODE_CLASS (mode2) == MODE_INT) | |
4347 | && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD | |
4348 | && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD) | |
4349 | return true; | |
4350 | ||
4351 | if (GET_MODE_SIZE (mode1) == GET_MODE_SIZE (mode2)) | |
4352 | { | |
4353 | if ((TARGET_FPU_SINGLE && !TARGET_FPU_DOUBLE) | |
4354 | && (mode1 == DFmode || mode2 == DFmode)) | |
4355 | return false; | |
4356 | else | |
4357 | return true; | |
4358 | } | |
4359 | ||
4360 | return false; | |
99e1629f | 4361 | } |
9304f876 CJW |
4362 | \f |
4363 | /* Register Classes. */ | |
4364 | ||
4365 | enum reg_class | |
4366 | nds32_regno_reg_class (int regno) | |
4367 | { | |
4368 | /* Refer to nds32.h for more register class details. */ | |
4369 | ||
4370 | if (regno >= 0 && regno <= 7) | |
4371 | return LOW_REGS; | |
4372 | else if (regno >= 8 && regno <= 11) | |
4373 | return MIDDLE_REGS; | |
4374 | else if (regno >= 12 && regno <= 14) | |
4375 | return HIGH_REGS; | |
4376 | else if (regno == 15) | |
4377 | return R15_TA_REG; | |
4378 | else if (regno >= 16 && regno <= 19) | |
4379 | return MIDDLE_REGS; | |
4380 | else if (regno >= 20 && regno <= 31) | |
4381 | return HIGH_REGS; | |
4382 | else if (regno == 32 || regno == 33) | |
e2286268 MC |
4383 | { |
4384 | /* $SFP and $AP is FRAME_REGS in fact, However prevent IRA don't | |
4385 | know how to allocate register for $SFP and $AP, just tell IRA they | |
4386 | are GENERAL_REGS, and ARM do this hack too. */ | |
4387 | return GENERAL_REGS; | |
4388 | } | |
4389 | else if (regno >= 34 && regno <= 97) | |
4390 | return FP_REGS; | |
9304f876 CJW |
4391 | else |
4392 | return NO_REGS; | |
4393 | } | |
4394 | ||
4395 | \f | |
4396 | /* Stack Layout and Calling Conventions. */ | |
4397 | ||
4398 | /* -- Basic Stack Layout. */ | |
4399 | ||
ca3a4a55 CJW |
4400 | rtx |
4401 | nds32_dynamic_chain_address (rtx frameaddr) | |
4402 | { | |
4403 | if (TARGET_V3PUSH) | |
4404 | { | |
4405 | /* If -mv3push is specified, we push $fp, $gp, and $lp into stack. | |
4406 | We can access dynamic chain address from stack by [$fp - 12]. */ | |
4407 | return plus_constant (Pmode, frameaddr, -12); | |
4408 | } | |
4409 | else | |
4410 | { | |
4411 | /* For general case we push $fp and $lp into stack at prologue. | |
4412 | We can access dynamic chain address from stack by [$fp - 8]. */ | |
4413 | return plus_constant (Pmode, frameaddr, -8); | |
4414 | } | |
4415 | } | |
4416 | ||
9304f876 CJW |
4417 | rtx |
4418 | nds32_return_addr_rtx (int count, | |
ca3a4a55 | 4419 | rtx frameaddr) |
9304f876 | 4420 | { |
ca3a4a55 CJW |
4421 | int offset; |
4422 | rtx addr; | |
4423 | ||
9304f876 | 4424 | if (count != 0) |
ca3a4a55 CJW |
4425 | { |
4426 | /* In nds32 ABI design, we can expect that $lp is always available | |
4427 | from stack by [$fp - 4] location. */ | |
4428 | offset = -4; | |
4429 | addr = plus_constant (Pmode, frameaddr, offset); | |
4430 | addr = memory_address (Pmode, addr); | |
4431 | ||
4432 | return gen_rtx_MEM (Pmode, addr); | |
4433 | } | |
9304f876 CJW |
4434 | |
4435 | /* If count == 0, it means we are at current frame, | |
4436 | the return address is $r30 ($lp). */ | |
4437 | return get_hard_reg_initial_val (Pmode, LP_REGNUM); | |
4438 | } | |
4439 | ||
4440 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
4441 | ||
4442 | HOST_WIDE_INT | |
4443 | nds32_initial_elimination_offset (unsigned int from_reg, unsigned int to_reg) | |
4444 | { | |
4445 | HOST_WIDE_INT offset; | |
4446 | ||
4447 | /* Compute and setup stack frame size. | |
4448 | The result will be in cfun->machine. */ | |
4449 | nds32_compute_stack_frame (); | |
4450 | ||
4451 | /* Remember to consider | |
ca3a4a55 CJW |
4452 | cfun->machine->callee_saved_area_gpr_padding_bytes and |
4453 | cfun->machine->eh_return_data_regs_size | |
9304f876 CJW |
4454 | when calculating offset. */ |
4455 | if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
4456 | { | |
4457 | offset = (cfun->machine->fp_size | |
8a498f99 | 4458 | + cfun->machine->gp_size |
9304f876 | 4459 | + cfun->machine->lp_size |
c457f751 CJW |
4460 | + cfun->machine->callee_saved_gpr_regs_size |
4461 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
e2286268 | 4462 | + cfun->machine->callee_saved_fpr_regs_size |
ca3a4a55 | 4463 | + cfun->machine->eh_return_data_regs_size |
9304f876 CJW |
4464 | + cfun->machine->local_size |
4465 | + cfun->machine->out_args_size); | |
4466 | } | |
4467 | else if (from_reg == ARG_POINTER_REGNUM | |
4468 | && to_reg == HARD_FRAME_POINTER_REGNUM) | |
4469 | { | |
4470 | offset = 0; | |
4471 | } | |
4472 | else if (from_reg == FRAME_POINTER_REGNUM | |
4473 | && to_reg == STACK_POINTER_REGNUM) | |
4474 | { | |
4475 | offset = (cfun->machine->local_size + cfun->machine->out_args_size); | |
4476 | } | |
4477 | else if (from_reg == FRAME_POINTER_REGNUM | |
4478 | && to_reg == HARD_FRAME_POINTER_REGNUM) | |
4479 | { | |
4480 | offset = (-1) * (cfun->machine->fp_size | |
4481 | + cfun->machine->gp_size | |
4482 | + cfun->machine->lp_size | |
c457f751 | 4483 | + cfun->machine->callee_saved_gpr_regs_size |
e2286268 | 4484 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
ca3a4a55 CJW |
4485 | + cfun->machine->callee_saved_fpr_regs_size |
4486 | + cfun->machine->eh_return_data_regs_size); | |
9304f876 CJW |
4487 | } |
4488 | else | |
4489 | { | |
4490 | gcc_unreachable (); | |
4491 | } | |
4492 | ||
4493 | return offset; | |
4494 | } | |
4495 | ||
4496 | /* -- Passing Arguments in Registers. */ | |
4497 | ||
4498 | void | |
4499 | nds32_init_cumulative_args (CUMULATIVE_ARGS *cum, | |
4500 | tree fntype ATTRIBUTE_UNUSED, | |
4501 | rtx libname ATTRIBUTE_UNUSED, | |
4502 | tree fndecl ATTRIBUTE_UNUSED, | |
4503 | int n_named_args ATTRIBUTE_UNUSED) | |
4504 | { | |
e2286268 MC |
4505 | /* Initial available registers. The values are offset against |
4506 | NDS32_GPR_ARG_FIRST_REGNUM and NDS32_FPR_ARG_FIRST_REGNUM | |
9304f876 | 4507 | for passing arguments. */ |
9d93cc24 | 4508 | cum->gpr_offset = 0; |
e2286268 | 4509 | cum->fpr_offset = 0; |
9304f876 CJW |
4510 | } |
4511 | ||
4512 | /* -- Function Entry and Exit. */ | |
4513 | ||
4514 | /* Function for normal multiple push prologue. */ | |
4515 | void | |
4516 | nds32_expand_prologue (void) | |
4517 | { | |
4518 | int fp_adjust; | |
4519 | int sp_adjust; | |
a6c7e777 | 4520 | unsigned Rb, Re; |
9304f876 | 4521 | |
9304f876 CJW |
4522 | /* Compute and setup stack frame size. |
4523 | The result will be in cfun->machine. */ | |
4524 | nds32_compute_stack_frame (); | |
4525 | ||
2140297c CJW |
4526 | /* Check frame_pointer_needed again to prevent fp is need after reload. */ |
4527 | if (frame_pointer_needed) | |
4528 | cfun->machine->fp_as_gp_p = false; | |
4529 | ||
557430f1 CJW |
4530 | /* If this is a variadic function, first we need to push argument |
4531 | registers that hold the unnamed argument value. */ | |
4532 | if (cfun->machine->va_args_size != 0) | |
4533 | { | |
a6c7e777 MC |
4534 | Rb = cfun->machine->va_args_first_regno; |
4535 | Re = cfun->machine->va_args_last_regno; | |
4536 | /* No need to push $fp, $gp, or $lp. */ | |
4537 | nds32_emit_stack_push_multiple (Rb, Re, false, false, false, true); | |
557430f1 CJW |
4538 | |
4539 | /* We may also need to adjust stack pointer for padding bytes | |
4540 | because varargs may cause $sp not 8-byte aligned. */ | |
4541 | if (cfun->machine->va_args_area_padding_bytes) | |
4542 | { | |
4543 | /* Generate sp adjustment instruction. */ | |
4544 | sp_adjust = cfun->machine->va_args_area_padding_bytes; | |
557430f1 | 4545 | |
a6c7e777 MC |
4546 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4547 | stack_pointer_rtx, | |
4548 | -1 * sp_adjust); | |
557430f1 CJW |
4549 | } |
4550 | } | |
4551 | ||
9304f876 CJW |
4552 | /* If the function is 'naked', |
4553 | we do not have to generate prologue code fragment. */ | |
b26fa4f9 | 4554 | if (cfun->machine->naked_p && !flag_pic) |
9304f876 CJW |
4555 | return; |
4556 | ||
4557 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
4558 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
4559 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
4560 | |
4561 | /* If $fp, $gp, $lp, and all callee-save registers are NOT required | |
4562 | to be saved, we don't have to create multiple push instruction. | |
4563 | Otherwise, a multiple push instruction is needed. */ | |
a6c7e777 MC |
4564 | if (!(Rb == SP_REGNUM && Re == SP_REGNUM |
4565 | && cfun->machine->fp_size == 0 | |
4566 | && cfun->machine->gp_size == 0 | |
4567 | && cfun->machine->lp_size == 0)) | |
9304f876 CJW |
4568 | { |
4569 | /* Create multiple push instruction rtx. */ | |
a6c7e777 MC |
4570 | nds32_emit_stack_push_multiple ( |
4571 | Rb, Re, | |
4572 | cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size, | |
4573 | false); | |
9304f876 CJW |
4574 | } |
4575 | ||
ca3a4a55 CJW |
4576 | /* Save eh data registers. */ |
4577 | if (cfun->machine->use_eh_return_p) | |
4578 | { | |
4579 | Rb = cfun->machine->eh_return_data_first_regno; | |
4580 | Re = cfun->machine->eh_return_data_last_regno; | |
4581 | ||
4582 | /* No need to push $fp, $gp, or $lp. | |
4583 | Also, this is not variadic arguments push. */ | |
4584 | nds32_emit_stack_push_multiple (Rb, Re, false, false, false, false); | |
4585 | } | |
4586 | ||
9304f876 CJW |
4587 | /* Check frame_pointer_needed to see |
4588 | if we shall emit fp adjustment instruction. */ | |
4589 | if (frame_pointer_needed) | |
4590 | { | |
4591 | /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size) | |
8a498f99 | 4592 | + (4 * callee-saved-registers) |
ca3a4a55 | 4593 | + (4 * exception-handling-data-registers) |
8a498f99 CJW |
4594 | Note: No need to adjust |
4595 | cfun->machine->callee_saved_area_gpr_padding_bytes, | |
4596 | because, at this point, stack pointer is just | |
4597 | at the position after push instruction. */ | |
9304f876 CJW |
4598 | fp_adjust = cfun->machine->fp_size |
4599 | + cfun->machine->gp_size | |
4600 | + cfun->machine->lp_size | |
ca3a4a55 CJW |
4601 | + cfun->machine->callee_saved_gpr_regs_size |
4602 | + cfun->machine->eh_return_data_regs_size; | |
7064dcad | 4603 | |
a6c7e777 MC |
4604 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, |
4605 | stack_pointer_rtx, | |
4606 | fp_adjust); | |
9304f876 CJW |
4607 | } |
4608 | ||
e2286268 MC |
4609 | /* Save fpu registers. */ |
4610 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
4611 | { | |
4612 | /* When $sp moved to bottom of stack, we need to check whether | |
4613 | the range of offset in the FPU instruction. */ | |
4614 | int fpr_offset = cfun->machine->local_size | |
4615 | + cfun->machine->out_args_size | |
4616 | + cfun->machine->callee_saved_fpr_regs_size; | |
4617 | ||
4618 | /* Check FPU instruction offset imm14s. */ | |
4619 | if (!satisfies_constraint_Is14 (GEN_INT (fpr_offset))) | |
4620 | { | |
4621 | int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes | |
4622 | + cfun->machine->callee_saved_fpr_regs_size; | |
4623 | ||
4624 | /* Save fpu registers, need to allocate stack space | |
4625 | for fpu callee registers. And now $sp position | |
4626 | on callee saved fpr registers. */ | |
4627 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4628 | stack_pointer_rtx, | |
4629 | -1 * fpr_space); | |
4630 | ||
4631 | /* Emit fpu store instruction, using [$sp + offset] store | |
4632 | fpu registers. */ | |
4633 | nds32_emit_push_fpr_callee_saved (0); | |
4634 | ||
4635 | /* Adjust $sp = $sp - local_size - out_args_size. */ | |
4636 | sp_adjust = cfun->machine->local_size | |
4637 | + cfun->machine->out_args_size; | |
4638 | ||
4639 | /* Allocate stack space for local size and out args size. */ | |
4640 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4641 | stack_pointer_rtx, | |
4642 | -1 * sp_adjust); | |
4643 | } | |
4644 | else | |
4645 | { | |
4646 | /* Offset range in Is14, so $sp moved to bottom of stack. */ | |
4647 | ||
4648 | /* Adjust $sp = $sp - local_size - out_args_size | |
4649 | - callee_saved_area_gpr_padding_bytes | |
4650 | - callee_saved_fpr_regs_size. */ | |
4651 | sp_adjust = cfun->machine->local_size | |
4652 | + cfun->machine->out_args_size | |
4653 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
4654 | + cfun->machine->callee_saved_fpr_regs_size; | |
4655 | ||
4656 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4657 | stack_pointer_rtx, | |
4658 | -1 * sp_adjust); | |
4659 | ||
4660 | /* Emit fpu store instruction, using [$sp + offset] store | |
4661 | fpu registers. */ | |
4662 | int fpr_position = cfun->machine->out_args_size | |
4663 | + cfun->machine->local_size; | |
4664 | nds32_emit_push_fpr_callee_saved (fpr_position); | |
4665 | } | |
4666 | } | |
4667 | else | |
4668 | { | |
4669 | /* Adjust $sp = $sp - local_size - out_args_size | |
4670 | - callee_saved_area_gpr_padding_bytes. */ | |
4671 | sp_adjust = cfun->machine->local_size | |
4672 | + cfun->machine->out_args_size | |
4673 | + cfun->machine->callee_saved_area_gpr_padding_bytes; | |
4674 | ||
4675 | /* sp_adjust value may be out of range of the addi instruction, | |
4676 | create alternative add behavior with TA_REGNUM if necessary, | |
4677 | using NEGATIVE value to tell that we are decreasing address. */ | |
4678 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4679 | stack_pointer_rtx, | |
4680 | -1 * sp_adjust); | |
4681 | } | |
9304f876 | 4682 | |
b26fa4f9 KLC |
4683 | /* Emit gp setup instructions for -fpic. */ |
4684 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) | |
4685 | nds32_emit_load_gp (); | |
4686 | ||
9304f876 CJW |
4687 | /* Prevent the instruction scheduler from |
4688 | moving instructions across the boundary. */ | |
4689 | emit_insn (gen_blockage ()); | |
4690 | } | |
4691 | ||
4692 | /* Function for normal multiple pop epilogue. */ | |
4693 | void | |
d6529176 | 4694 | nds32_expand_epilogue (bool sibcall_p) |
9304f876 CJW |
4695 | { |
4696 | int sp_adjust; | |
a6c7e777 | 4697 | unsigned Rb, Re; |
9304f876 CJW |
4698 | |
4699 | /* Compute and setup stack frame size. | |
4700 | The result will be in cfun->machine. */ | |
4701 | nds32_compute_stack_frame (); | |
4702 | ||
4703 | /* Prevent the instruction scheduler from | |
4704 | moving instructions across the boundary. */ | |
4705 | emit_insn (gen_blockage ()); | |
4706 | ||
4707 | /* If the function is 'naked', we do not have to generate | |
557430f1 CJW |
4708 | epilogue code fragment BUT 'ret' instruction. |
4709 | However, if this function is also a variadic function, | |
4710 | we need to create adjust stack pointer before 'ret' instruction. */ | |
9304f876 CJW |
4711 | if (cfun->machine->naked_p) |
4712 | { | |
557430f1 | 4713 | /* If this is a variadic function, we do not have to restore argument |
8a498f99 CJW |
4714 | registers but need to adjust stack pointer back to previous stack |
4715 | frame location before return. */ | |
557430f1 CJW |
4716 | if (cfun->machine->va_args_size != 0) |
4717 | { | |
4718 | /* Generate sp adjustment instruction. | |
4719 | We need to consider padding bytes here. */ | |
4720 | sp_adjust = cfun->machine->va_args_size | |
4721 | + cfun->machine->va_args_area_padding_bytes; | |
a6c7e777 MC |
4722 | |
4723 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4724 | stack_pointer_rtx, | |
4725 | sp_adjust); | |
557430f1 CJW |
4726 | } |
4727 | ||
03390cda | 4728 | /* Generate return instruction by using 'return_internal' pattern. |
8a498f99 | 4729 | Make sure this instruction is after gen_blockage(). */ |
d6529176 | 4730 | if (!sibcall_p) |
54c537e6 CJW |
4731 | { |
4732 | /* We need to further check attributes to determine whether | |
4733 | there should be return instruction at epilogue. | |
4734 | If the attribute naked exists but -mno-ret-in-naked-func | |
4735 | is issued, there is NO need to generate return instruction. */ | |
4736 | if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) | |
4737 | return; | |
4738 | ||
4739 | emit_jump_insn (gen_return_internal ()); | |
4740 | } | |
9304f876 CJW |
4741 | return; |
4742 | } | |
4743 | ||
4744 | if (frame_pointer_needed) | |
4745 | { | |
e2286268 MC |
4746 | /* Restore fpu registers. */ |
4747 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
4748 | { | |
4749 | int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes; | |
4750 | ||
4751 | /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) | |
4752 | - (4 * callee-saved-registers) | |
4753 | - (4 * exception-handling-data-registers) | |
4754 | - (4 * callee-saved-gpr-registers padding byte) | |
4755 | - (4 * callee-saved-fpr-registers) | |
4756 | Note: we want to adjust stack pointer | |
4757 | to the position for callee-saved fpr register, | |
4758 | And restore fpu register use .bi instruction to adjust $sp | |
4759 | from callee-saved fpr register to pop instruction. */ | |
4760 | sp_adjust = cfun->machine->fp_size | |
4761 | + cfun->machine->gp_size | |
4762 | + cfun->machine->lp_size | |
4763 | + cfun->machine->callee_saved_gpr_regs_size | |
ca3a4a55 | 4764 | + cfun->machine->eh_return_data_regs_size |
e2286268 MC |
4765 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
4766 | + cfun->machine->callee_saved_fpr_regs_size; | |
557430f1 | 4767 | |
e2286268 MC |
4768 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4769 | hard_frame_pointer_rtx, | |
4770 | -1 * sp_adjust); | |
4771 | ||
4772 | /* Emit fpu load instruction, using .bi instruction | |
4773 | load fpu registers. */ | |
4774 | nds32_emit_pop_fpr_callee_saved (gpr_padding); | |
4775 | } | |
4776 | else | |
4777 | { | |
4778 | /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) | |
4779 | - (4 * callee-saved-registers) | |
4780 | - (4 * exception-handling-data-registers) | |
4781 | Note: No need to adjust | |
4782 | cfun->machine->callee_saved_area_gpr_padding_bytes, | |
4783 | because we want to adjust stack pointer | |
4784 | to the position for pop instruction. */ | |
4785 | sp_adjust = cfun->machine->fp_size | |
4786 | + cfun->machine->gp_size | |
4787 | + cfun->machine->lp_size | |
ca3a4a55 CJW |
4788 | + cfun->machine->callee_saved_gpr_regs_size |
4789 | + cfun->machine->eh_return_data_regs_size; | |
e2286268 MC |
4790 | |
4791 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4792 | hard_frame_pointer_rtx, | |
4793 | -1 * sp_adjust); | |
4794 | } | |
9304f876 CJW |
4795 | } |
4796 | else | |
4797 | { | |
e2286268 MC |
4798 | /* Restore fpu registers. */ |
4799 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
4800 | { | |
4801 | int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes; | |
9304f876 | 4802 | |
e2286268 MC |
4803 | /* Adjust $sp = $sp + local_size + out_args_size. */ |
4804 | sp_adjust = cfun->machine->local_size | |
4805 | + cfun->machine->out_args_size; | |
a6c7e777 | 4806 | |
e2286268 MC |
4807 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4808 | stack_pointer_rtx, | |
4809 | sp_adjust); | |
4810 | ||
4811 | /* Emit fpu load instruction, using .bi instruction | |
4812 | load fpu registers, and adjust $sp from callee-saved fpr register | |
4813 | to callee-saved gpr register. */ | |
4814 | nds32_emit_pop_fpr_callee_saved (gpr_padding); | |
4815 | } | |
4816 | else | |
4817 | { | |
4818 | /* If frame pointer is NOT needed, | |
4819 | we cannot calculate the sp adjustment from frame pointer. | |
4820 | Instead, we calculate the adjustment by local_size, | |
4821 | out_args_size, and callee_saved_area_gpr_padding_bytes. | |
4822 | Notice that such sp adjustment value may be out of range, | |
4823 | so we have to deal with it as well. */ | |
4824 | ||
4825 | /* Adjust $sp = $sp + local_size + out_args_size | |
4826 | + callee_saved_area_gpr_padding_bytes. */ | |
4827 | sp_adjust = cfun->machine->local_size | |
4828 | + cfun->machine->out_args_size | |
4829 | + cfun->machine->callee_saved_area_gpr_padding_bytes; | |
4830 | ||
4831 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4832 | stack_pointer_rtx, | |
4833 | sp_adjust); | |
4834 | } | |
9304f876 CJW |
4835 | } |
4836 | ||
ca3a4a55 CJW |
4837 | /* Restore eh data registers. */ |
4838 | if (cfun->machine->use_eh_return_p) | |
4839 | { | |
4840 | Rb = cfun->machine->eh_return_data_first_regno; | |
4841 | Re = cfun->machine->eh_return_data_last_regno; | |
4842 | ||
4843 | /* No need to pop $fp, $gp, or $lp. */ | |
4844 | nds32_emit_stack_pop_multiple (Rb, Re, false, false, false); | |
4845 | } | |
4846 | ||
9304f876 | 4847 | /* Get callee_first_regno and callee_last_regno. */ |
a6c7e777 MC |
4848 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
4849 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
4850 | |
4851 | /* If $fp, $gp, $lp, and all callee-save registers are NOT required | |
4852 | to be saved, we don't have to create multiple pop instruction. | |
4853 | Otherwise, a multiple pop instruction is needed. */ | |
a6c7e777 MC |
4854 | if (!(Rb == SP_REGNUM && Re == SP_REGNUM |
4855 | && cfun->machine->fp_size == 0 | |
4856 | && cfun->machine->gp_size == 0 | |
4857 | && cfun->machine->lp_size == 0)) | |
9304f876 CJW |
4858 | { |
4859 | /* Create multiple pop instruction rtx. */ | |
a6c7e777 MC |
4860 | nds32_emit_stack_pop_multiple ( |
4861 | Rb, Re, | |
4862 | cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size); | |
9304f876 CJW |
4863 | } |
4864 | ||
557430f1 CJW |
4865 | /* If this is a variadic function, we do not have to restore argument |
4866 | registers but need to adjust stack pointer back to previous stack | |
4867 | frame location before return. */ | |
4868 | if (cfun->machine->va_args_size != 0) | |
4869 | { | |
4870 | /* Generate sp adjustment instruction. | |
8a498f99 | 4871 | We need to consider padding bytes here. */ |
557430f1 CJW |
4872 | sp_adjust = cfun->machine->va_args_size |
4873 | + cfun->machine->va_args_area_padding_bytes; | |
557430f1 | 4874 | |
a6c7e777 MC |
4875 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4876 | stack_pointer_rtx, | |
4877 | sp_adjust); | |
557430f1 CJW |
4878 | } |
4879 | ||
ca3a4a55 CJW |
4880 | /* If this function uses __builtin_eh_return, make stack adjustment |
4881 | for exception handler. */ | |
4882 | if (cfun->machine->use_eh_return_p) | |
4883 | { | |
4884 | /* We need to unwind the stack by the offset computed by | |
4885 | EH_RETURN_STACKADJ_RTX. However, at this point the CFA is | |
4886 | based on SP. Ideally we would update the SP and define the | |
4887 | CFA along the lines of: | |
4888 | ||
4889 | SP = SP + EH_RETURN_STACKADJ_RTX | |
4890 | (regnote CFA = SP - EH_RETURN_STACKADJ_RTX) | |
4891 | ||
4892 | However the dwarf emitter only understands a constant | |
4893 | register offset. | |
4894 | ||
4895 | The solution chosen here is to use the otherwise $ta ($r15) | |
4896 | as a temporary register to hold the current SP value. The | |
4897 | CFA is described using $ta then SP is modified. */ | |
4898 | ||
4899 | rtx ta_reg; | |
4900 | rtx insn; | |
4901 | ||
4902 | ta_reg = gen_rtx_REG (SImode, TA_REGNUM); | |
4903 | ||
4904 | insn = emit_move_insn (ta_reg, stack_pointer_rtx); | |
4905 | add_reg_note (insn, REG_CFA_DEF_CFA, ta_reg); | |
4906 | RTX_FRAME_RELATED_P (insn) = 1; | |
4907 | ||
4908 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
4909 | stack_pointer_rtx, | |
4910 | EH_RETURN_STACKADJ_RTX)); | |
4911 | ||
4912 | /* Ensure the assignment to $ta does not get optimized away. */ | |
4913 | emit_use (ta_reg); | |
4914 | } | |
4915 | ||
03390cda | 4916 | /* Generate return instruction. */ |
d6529176 CJW |
4917 | if (!sibcall_p) |
4918 | emit_jump_insn (gen_return_internal ()); | |
9304f876 CJW |
4919 | } |
4920 | ||
4921 | /* Function for v3push prologue. */ | |
4922 | void | |
4923 | nds32_expand_prologue_v3push (void) | |
4924 | { | |
4925 | int fp_adjust; | |
4926 | int sp_adjust; | |
e2286268 | 4927 | int fpr_space = 0; |
a6c7e777 | 4928 | unsigned Rb, Re; |
9304f876 | 4929 | |
9304f876 CJW |
4930 | /* Compute and setup stack frame size. |
4931 | The result will be in cfun->machine. */ | |
4932 | nds32_compute_stack_frame (); | |
4933 | ||
a6c7e777 MC |
4934 | if (cfun->machine->callee_saved_gpr_regs_size > 0) |
4935 | df_set_regs_ever_live (FP_REGNUM, 1); | |
4936 | ||
2140297c CJW |
4937 | /* Check frame_pointer_needed again to prevent fp is need after reload. */ |
4938 | if (frame_pointer_needed) | |
4939 | cfun->machine->fp_as_gp_p = false; | |
4940 | ||
9304f876 CJW |
4941 | /* If the function is 'naked', |
4942 | we do not have to generate prologue code fragment. */ | |
b26fa4f9 | 4943 | if (cfun->machine->naked_p && !flag_pic) |
9304f876 CJW |
4944 | return; |
4945 | ||
4946 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
4947 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
4948 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
4949 | |
4950 | /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available, | |
4951 | where imm8u has to be 8-byte alignment. */ | |
4952 | sp_adjust = cfun->machine->local_size | |
4953 | + cfun->machine->out_args_size | |
e2286268 MC |
4954 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
4955 | + cfun->machine->callee_saved_fpr_regs_size; | |
9304f876 CJW |
4956 | |
4957 | if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
4958 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)) | |
4959 | { | |
4960 | /* We can use 'push25 Re,imm8u'. */ | |
4961 | ||
88437f39 | 4962 | /* nds32_emit_stack_v3push(last_regno, sp_adjust), |
a6c7e777 MC |
4963 | the pattern 'stack_v3push' is implemented in nds32.md. */ |
4964 | nds32_emit_stack_v3push (Rb, Re, sp_adjust); | |
e2286268 MC |
4965 | |
4966 | /* Save fpu registers. */ | |
4967 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
4968 | { | |
4969 | /* Calculate fpr position. */ | |
4970 | int fpr_position = cfun->machine->local_size | |
4971 | + cfun->machine->out_args_size; | |
4972 | /* Emit fpu store instruction, using [$sp + offset] store | |
4973 | fpu registers. */ | |
4974 | nds32_emit_push_fpr_callee_saved (fpr_position); | |
4975 | } | |
4976 | ||
9304f876 | 4977 | /* Check frame_pointer_needed to see |
8a498f99 | 4978 | if we shall emit fp adjustment instruction. */ |
9304f876 CJW |
4979 | if (frame_pointer_needed) |
4980 | { | |
4981 | /* adjust $fp = $sp + 4 ($fp size) | |
8a498f99 CJW |
4982 | + 4 ($gp size) |
4983 | + 4 ($lp size) | |
4984 | + (4 * n) (callee-saved registers) | |
4985 | + sp_adjust ('push25 Re,imm8u') | |
9304f876 | 4986 | Note: Since we use 'push25 Re,imm8u', |
8a498f99 CJW |
4987 | the position of stack pointer is further |
4988 | changed after push instruction. | |
4989 | Hence, we need to take sp_adjust value | |
4990 | into consideration. */ | |
9304f876 CJW |
4991 | fp_adjust = cfun->machine->fp_size |
4992 | + cfun->machine->gp_size | |
4993 | + cfun->machine->lp_size | |
c457f751 | 4994 | + cfun->machine->callee_saved_gpr_regs_size |
9304f876 | 4995 | + sp_adjust; |
a6c7e777 MC |
4996 | |
4997 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, | |
4998 | stack_pointer_rtx, | |
4999 | fp_adjust); | |
9304f876 CJW |
5000 | } |
5001 | } | |
5002 | else | |
5003 | { | |
e2286268 MC |
5004 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5005 | { | |
5006 | /* Calculate fpr space. */ | |
5007 | fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes | |
5008 | + cfun->machine->callee_saved_fpr_regs_size; | |
5009 | ||
5010 | /* We have to use 'push25 Re, fpr_space', to pre-allocate | |
5011 | callee saved fpr registers space. */ | |
5012 | nds32_emit_stack_v3push (Rb, Re, fpr_space); | |
5013 | nds32_emit_push_fpr_callee_saved (0); | |
5014 | } | |
5015 | else | |
5016 | { | |
5017 | /* We have to use 'push25 Re,0' and | |
5018 | expand one more instruction to adjust $sp later. */ | |
9304f876 | 5019 | |
e2286268 MC |
5020 | /* nds32_emit_stack_v3push(last_regno, sp_adjust), |
5021 | the pattern 'stack_v3push' is implemented in nds32.md. */ | |
5022 | nds32_emit_stack_v3push (Rb, Re, 0); | |
5023 | } | |
9304f876 CJW |
5024 | |
5025 | /* Check frame_pointer_needed to see | |
8a498f99 | 5026 | if we shall emit fp adjustment instruction. */ |
9304f876 CJW |
5027 | if (frame_pointer_needed) |
5028 | { | |
5029 | /* adjust $fp = $sp + 4 ($fp size) | |
8a498f99 CJW |
5030 | + 4 ($gp size) |
5031 | + 4 ($lp size) | |
5032 | + (4 * n) (callee-saved registers) | |
9304f876 | 5033 | Note: Since we use 'push25 Re,0', |
8a498f99 CJW |
5034 | the stack pointer is just at the position |
5035 | after push instruction. | |
5036 | No need to take sp_adjust into consideration. */ | |
9304f876 CJW |
5037 | fp_adjust = cfun->machine->fp_size |
5038 | + cfun->machine->gp_size | |
5039 | + cfun->machine->lp_size | |
c457f751 | 5040 | + cfun->machine->callee_saved_gpr_regs_size; |
a6c7e777 | 5041 | |
e2286268 MC |
5042 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5043 | { | |
5044 | /* We use 'push25 Re, fpr_space', the $sp is | |
5045 | on callee saved fpr position, so need to consider | |
5046 | fpr space. */ | |
5047 | fp_adjust = fp_adjust + fpr_space; | |
5048 | } | |
5049 | ||
a6c7e777 MC |
5050 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, |
5051 | stack_pointer_rtx, | |
5052 | fp_adjust); | |
9304f876 CJW |
5053 | } |
5054 | ||
e2286268 MC |
5055 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5056 | { | |
5057 | /* We use 'push25 Re, fpr_space', | |
5058 | the $sp is on callee saved fpr position, | |
5059 | no need to consider fpr space. */ | |
5060 | sp_adjust = sp_adjust - fpr_space; | |
5061 | } | |
5062 | ||
9304f876 | 5063 | /* Because we use 'push25 Re,0', |
8a498f99 | 5064 | we need to expand one more instruction to adjust $sp. |
8a498f99 | 5065 | using NEGATIVE value to tell that we are decreasing address. */ |
a6c7e777 MC |
5066 | nds32_emit_adjust_frame (stack_pointer_rtx, |
5067 | stack_pointer_rtx, | |
5068 | -1 * sp_adjust); | |
9304f876 CJW |
5069 | } |
5070 | ||
b26fa4f9 KLC |
5071 | /* Emit gp setup instructions for -fpic. */ |
5072 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) | |
5073 | nds32_emit_load_gp (); | |
5074 | ||
9304f876 CJW |
5075 | /* Prevent the instruction scheduler from |
5076 | moving instructions across the boundary. */ | |
5077 | emit_insn (gen_blockage ()); | |
5078 | } | |
5079 | ||
5080 | /* Function for v3pop epilogue. */ | |
5081 | void | |
d6529176 | 5082 | nds32_expand_epilogue_v3pop (bool sibcall_p) |
9304f876 CJW |
5083 | { |
5084 | int sp_adjust; | |
a6c7e777 | 5085 | unsigned Rb, Re; |
9304f876 CJW |
5086 | |
5087 | /* Compute and setup stack frame size. | |
5088 | The result will be in cfun->machine. */ | |
5089 | nds32_compute_stack_frame (); | |
5090 | ||
5091 | /* Prevent the instruction scheduler from | |
5092 | moving instructions across the boundary. */ | |
5093 | emit_insn (gen_blockage ()); | |
5094 | ||
5095 | /* If the function is 'naked', we do not have to generate | |
5096 | epilogue code fragment BUT 'ret' instruction. */ | |
5097 | if (cfun->machine->naked_p) | |
5098 | { | |
03390cda | 5099 | /* Generate return instruction by using 'return_internal' pattern. |
54c537e6 CJW |
5100 | Make sure this instruction is after gen_blockage(). |
5101 | First we need to check this is a function without sibling call. */ | |
d6529176 | 5102 | if (!sibcall_p) |
54c537e6 CJW |
5103 | { |
5104 | /* We need to further check attributes to determine whether | |
5105 | there should be return instruction at epilogue. | |
5106 | If the attribute naked exists but -mno-ret-in-naked-func | |
5107 | is issued, there is NO need to generate return instruction. */ | |
5108 | if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) | |
5109 | return; | |
5110 | ||
5111 | emit_jump_insn (gen_return_internal ()); | |
5112 | } | |
9304f876 CJW |
5113 | return; |
5114 | } | |
5115 | ||
5116 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
5117 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
5118 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
5119 | |
5120 | /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available, | |
5121 | where imm8u has to be 8-byte alignment. */ | |
5122 | sp_adjust = cfun->machine->local_size | |
5123 | + cfun->machine->out_args_size | |
e2286268 MC |
5124 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
5125 | + cfun->machine->callee_saved_fpr_regs_size; | |
9304f876 CJW |
5126 | |
5127 | /* We have to consider alloca issue as well. | |
5128 | If the function does call alloca(), the stack pointer is not fixed. | |
5129 | In that case, we cannot use 'pop25 Re,imm8u' directly. | |
5130 | We have to caculate stack pointer from frame pointer | |
5131 | and then use 'pop25 Re,0'. | |
5132 | Of course, the frame_pointer_needed should be nonzero | |
5133 | if the function calls alloca(). */ | |
5134 | if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
5135 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) | |
5136 | && !cfun->calls_alloca) | |
5137 | { | |
e2286268 MC |
5138 | /* Restore fpu registers. */ |
5139 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
5140 | { | |
5141 | int fpr_position = cfun->machine->local_size | |
5142 | + cfun->machine->out_args_size; | |
5143 | /* Emit fpu load instruction, using [$sp + offset] restore | |
5144 | fpu registers. */ | |
5145 | nds32_emit_v3pop_fpr_callee_saved (fpr_position); | |
5146 | } | |
5147 | ||
9304f876 CJW |
5148 | /* We can use 'pop25 Re,imm8u'. */ |
5149 | ||
88437f39 | 5150 | /* nds32_emit_stack_v3pop(last_regno, sp_adjust), |
a6c7e777 MC |
5151 | the pattern 'stack_v3pop' is implementad in nds32.md. */ |
5152 | nds32_emit_stack_v3pop (Rb, Re, sp_adjust); | |
9304f876 CJW |
5153 | } |
5154 | else | |
5155 | { | |
5156 | /* We have to use 'pop25 Re,0', and prior to it, | |
8a498f99 | 5157 | we must expand one more instruction to adjust $sp. */ |
9304f876 CJW |
5158 | |
5159 | if (frame_pointer_needed) | |
5160 | { | |
5161 | /* adjust $sp = $fp - 4 ($fp size) | |
8a498f99 CJW |
5162 | - 4 ($gp size) |
5163 | - 4 ($lp size) | |
5164 | - (4 * n) (callee-saved registers) | |
9304f876 | 5165 | Note: No need to adjust |
8a498f99 CJW |
5166 | cfun->machine->callee_saved_area_gpr_padding_bytes, |
5167 | because we want to adjust stack pointer | |
5168 | to the position for pop instruction. */ | |
9304f876 CJW |
5169 | sp_adjust = cfun->machine->fp_size |
5170 | + cfun->machine->gp_size | |
5171 | + cfun->machine->lp_size | |
c457f751 | 5172 | + cfun->machine->callee_saved_gpr_regs_size; |
a6c7e777 | 5173 | |
e2286268 MC |
5174 | /* Restore fpu registers. */ |
5175 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
5176 | { | |
5177 | /* Set $sp to callee saved fpr position, we need to restore | |
5178 | fpr registers. */ | |
5179 | sp_adjust = sp_adjust | |
5180 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
5181 | + cfun->machine->callee_saved_fpr_regs_size; | |
5182 | ||
5183 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5184 | hard_frame_pointer_rtx, | |
5185 | -1 * sp_adjust); | |
5186 | ||
5187 | /* Emit fpu load instruction, using [$sp + offset] restore | |
5188 | fpu registers. */ | |
5189 | nds32_emit_v3pop_fpr_callee_saved (0); | |
5190 | } | |
5191 | else | |
5192 | { | |
5193 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5194 | hard_frame_pointer_rtx, | |
5195 | -1 * sp_adjust); | |
5196 | } | |
9304f876 CJW |
5197 | } |
5198 | else | |
5199 | { | |
5200 | /* If frame pointer is NOT needed, | |
5201 | we cannot calculate the sp adjustment from frame pointer. | |
5202 | Instead, we calculate the adjustment by local_size, | |
5203 | out_args_size, and callee_saved_area_padding_bytes. | |
5204 | Notice that such sp adjustment value may be out of range, | |
5205 | so we have to deal with it as well. */ | |
5206 | ||
5207 | /* Adjust $sp = $sp + local_size + out_args_size | |
e2286268 MC |
5208 | + callee_saved_area_gpr_padding_bytes |
5209 | + callee_saved_fpr_regs_size. */ | |
9304f876 CJW |
5210 | sp_adjust = cfun->machine->local_size |
5211 | + cfun->machine->out_args_size | |
e2286268 MC |
5212 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
5213 | + cfun->machine->callee_saved_fpr_regs_size; | |
5214 | ||
5215 | /* Restore fpu registers. */ | |
5216 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
5217 | { | |
5218 | /* Set $sp to callee saved fpr position, we need to restore | |
5219 | fpr registers. */ | |
5220 | sp_adjust = sp_adjust | |
5221 | - cfun->machine->callee_saved_area_gpr_padding_bytes | |
5222 | - cfun->machine->callee_saved_fpr_regs_size; | |
5223 | ||
5224 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5225 | stack_pointer_rtx, | |
5226 | sp_adjust); | |
5227 | ||
5228 | /* Emit fpu load instruction, using [$sp + offset] restore | |
5229 | fpu registers. */ | |
5230 | nds32_emit_v3pop_fpr_callee_saved (0); | |
5231 | } | |
5232 | else | |
5233 | { | |
5234 | /* sp_adjust value may be out of range of the addi instruction, | |
5235 | create alternative add behavior with TA_REGNUM if necessary, | |
5236 | using POSITIVE value to tell that we are increasing | |
5237 | address. */ | |
5238 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5239 | stack_pointer_rtx, | |
5240 | sp_adjust); | |
5241 | } | |
9304f876 CJW |
5242 | } |
5243 | ||
e2286268 MC |
5244 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5245 | { | |
5246 | /* We have fpr need to restore, so $sp is set on callee saved fpr | |
5247 | position. And we use 'pop25 Re, fpr_space' to adjust $sp. */ | |
5248 | int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes | |
5249 | + cfun->machine->callee_saved_fpr_regs_size; | |
5250 | nds32_emit_stack_v3pop (Rb, Re, fpr_space); | |
5251 | } | |
5252 | else | |
5253 | { | |
5254 | /* nds32_emit_stack_v3pop(last_regno, sp_adjust), | |
5255 | the pattern 'stack_v3pop' is implementad in nds32.md. */ | |
5256 | nds32_emit_stack_v3pop (Rb, Re, 0); | |
5257 | } | |
9304f876 | 5258 | } |
aa2642ef CJW |
5259 | /* Generate return instruction. */ |
5260 | emit_jump_insn (gen_pop25return ()); | |
9304f876 CJW |
5261 | } |
5262 | ||
03390cda CJW |
5263 | /* Return nonzero if this function is known to have a null epilogue. |
5264 | This allows the optimizer to omit jumps to jumps if no stack | |
5265 | was created. */ | |
5266 | int | |
5267 | nds32_can_use_return_insn (void) | |
5268 | { | |
e2286268 MC |
5269 | int sp_adjust; |
5270 | ||
03390cda CJW |
5271 | /* Prior to reloading, we can't tell how many registers must be saved. |
5272 | Thus we can not determine whether this function has null epilogue. */ | |
5273 | if (!reload_completed) | |
5274 | return 0; | |
5275 | ||
54c537e6 CJW |
5276 | /* If attribute 'naked' appears but -mno-ret-in-naked-func is used, |
5277 | we cannot use return instruction. */ | |
5278 | if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) | |
5279 | return 0; | |
5280 | ||
e2286268 MC |
5281 | sp_adjust = cfun->machine->local_size |
5282 | + cfun->machine->out_args_size | |
5283 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
5284 | + cfun->machine->callee_saved_fpr_regs_size; | |
5285 | if (!cfun->machine->fp_as_gp_p | |
5286 | && satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
5287 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) | |
5288 | && !cfun->calls_alloca | |
5289 | && NDS32_V3PUSH_AVAILABLE_P | |
5290 | && !(TARGET_HARD_FLOAT | |
5291 | && (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM))) | |
5292 | return 1; | |
5293 | ||
03390cda CJW |
5294 | /* If no stack was created, two conditions must be satisfied: |
5295 | 1. This is a naked function. | |
8a498f99 | 5296 | So there is no callee-saved, local size, or outgoing size. |
03390cda | 5297 | 2. This is NOT a variadic function. |
8a498f99 | 5298 | So there is no pushing arguement registers into the stack. */ |
03390cda CJW |
5299 | return (cfun->machine->naked_p && (cfun->machine->va_args_size == 0)); |
5300 | } | |
5301 | ||
2f1bb3ca SC |
5302 | scalar_int_mode |
5303 | nds32_case_vector_shorten_mode (int min_offset, int max_offset, | |
5304 | rtx body ATTRIBUTE_UNUSED) | |
5305 | { | |
5306 | if (min_offset < 0 || max_offset >= 0x2000) | |
5307 | return SImode; | |
5308 | else | |
5309 | { | |
5310 | /* The jump table maybe need to 2 byte alignment, | |
5311 | so reserved 1 byte for check max_offset. */ | |
5312 | if (max_offset >= 0xff) | |
5313 | return HImode; | |
5314 | else | |
5315 | return QImode; | |
5316 | } | |
5317 | } | |
5318 | ||
9304f876 CJW |
5319 | /* ------------------------------------------------------------------------ */ |
5320 | ||
43fa41c1 CJW |
5321 | /* Return alignment for the label. */ |
5322 | int | |
5323 | nds32_target_alignment (rtx_insn *label) | |
5324 | { | |
5325 | rtx_insn *insn; | |
5326 | ||
5327 | if (!NDS32_ALIGN_P ()) | |
5328 | return 0; | |
5329 | ||
5330 | insn = next_active_insn (label); | |
5331 | ||
5332 | /* Always align to 4 byte when first instruction after label is jump | |
5333 | instruction since length for that might changed, so let's always align | |
5334 | it for make sure we don't lose any perfomance here. */ | |
5335 | if (insn == 0 | |
5336 | || (get_attr_length (insn) == 2 | |
5337 | && !JUMP_P (insn) && !CALL_P (insn))) | |
5338 | return 0; | |
5339 | else | |
5340 | return 2; | |
5341 | } | |
5342 | ||
79498ad8 CJW |
5343 | /* Return alignment for data. */ |
5344 | unsigned int | |
5345 | nds32_data_alignment (tree data, | |
5346 | unsigned int basic_align) | |
5347 | { | |
5348 | if ((basic_align < BITS_PER_WORD) | |
5349 | && (TREE_CODE (data) == ARRAY_TYPE | |
5350 | || TREE_CODE (data) == UNION_TYPE | |
5351 | || TREE_CODE (data) == RECORD_TYPE)) | |
5352 | return BITS_PER_WORD; | |
5353 | else | |
5354 | return basic_align; | |
5355 | } | |
5356 | ||
5357 | /* Return alignment for constant value. */ | |
5358 | static HOST_WIDE_INT | |
5359 | nds32_constant_alignment (const_tree constant, | |
5360 | HOST_WIDE_INT basic_align) | |
5361 | { | |
5362 | /* Make string literal and constant for constructor to word align. */ | |
5363 | if (((TREE_CODE (constant) == STRING_CST | |
5364 | || TREE_CODE (constant) == CONSTRUCTOR | |
5365 | || TREE_CODE (constant) == UNION_TYPE | |
5366 | || TREE_CODE (constant) == RECORD_TYPE | |
5367 | || TREE_CODE (constant) == ARRAY_TYPE) | |
5368 | && basic_align < BITS_PER_WORD)) | |
5369 | return BITS_PER_WORD; | |
5370 | else | |
5371 | return basic_align; | |
5372 | } | |
5373 | ||
5374 | /* Return alignment for local variable. */ | |
5375 | unsigned int | |
5376 | nds32_local_alignment (tree local ATTRIBUTE_UNUSED, | |
5377 | unsigned int basic_align) | |
5378 | { | |
5379 | bool at_least_align_to_word = false; | |
5380 | /* Make local array, struct and union at least align to word for make | |
5381 | sure it can unroll memcpy when initialize by constant. */ | |
5382 | switch (TREE_CODE (local)) | |
5383 | { | |
5384 | case ARRAY_TYPE: | |
5385 | case RECORD_TYPE: | |
5386 | case UNION_TYPE: | |
5387 | at_least_align_to_word = true; | |
5388 | break; | |
5389 | default: | |
5390 | at_least_align_to_word = false; | |
5391 | break; | |
5392 | } | |
5393 | if (at_least_align_to_word | |
5394 | && (basic_align < BITS_PER_WORD)) | |
5395 | return BITS_PER_WORD; | |
5396 | else | |
5397 | return basic_align; | |
5398 | } | |
5399 | ||
e2286268 MC |
5400 | bool |
5401 | nds32_split_double_word_load_store_p(rtx *operands, bool load_p) | |
5402 | { | |
5403 | rtx mem = load_p ? operands[1] : operands[0]; | |
5404 | /* Do split at split2 if -O0 or schedule 2 not enable. */ | |
5405 | if (optimize == 0 || !flag_schedule_insns_after_reload) | |
5406 | return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem); | |
5407 | ||
5408 | /* Split double word load store after copy propgation. */ | |
5409 | if (current_pass == NULL) | |
5410 | return false; | |
5411 | ||
5412 | const char *pass_name = current_pass->name; | |
5413 | if (pass_name && ((strcmp (pass_name, "split4") == 0) | |
5414 | || (strcmp (pass_name, "split5") == 0))) | |
5415 | return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem); | |
5416 | ||
5417 | return false; | |
5418 | } | |
5419 | ||
5420 | static bool | |
5421 | nds32_use_blocks_for_constant_p (machine_mode mode, | |
5422 | const_rtx x ATTRIBUTE_UNUSED) | |
5423 | { | |
5424 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
5425 | && (mode == DFmode || mode == SFmode)) | |
5426 | return true; | |
5427 | else | |
5428 | return false; | |
5429 | } | |
9304f876 | 5430 | |
9304f876 CJW |
5431 | /* ------------------------------------------------------------------------ */ |
5432 | ||
5433 | /* PART 5: Initialize target hook structure and definitions. */ | |
5434 | \f | |
5435 | /* Controlling the Compilation Driver. */ | |
5436 | ||
5437 | \f | |
5438 | /* Run-time Target Specification. */ | |
5439 | ||
5440 | \f | |
5441 | /* Defining Data Structures for Per-function Information. */ | |
5442 | ||
5443 | \f | |
5444 | /* Storage Layout. */ | |
5445 | ||
5446 | #undef TARGET_PROMOTE_FUNCTION_MODE | |
5447 | #define TARGET_PROMOTE_FUNCTION_MODE \ | |
5448 | default_promote_function_mode_always_promote | |
5449 | ||
5f2a98c3 CJW |
5450 | #undef TARGET_EXPAND_TO_RTL_HOOK |
5451 | #define TARGET_EXPAND_TO_RTL_HOOK nds32_expand_to_rtl_hook | |
5452 | ||
79498ad8 CJW |
5453 | #undef TARGET_CONSTANT_ALIGNMENT |
5454 | #define TARGET_CONSTANT_ALIGNMENT nds32_constant_alignment | |
5455 | ||
9304f876 CJW |
5456 | \f |
5457 | /* Layout of Source Language Data Types. */ | |
5458 | ||
5459 | \f | |
5460 | /* Register Usage. */ | |
5461 | ||
5462 | /* -- Basic Characteristics of Registers. */ | |
5463 | ||
e2286268 MC |
5464 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
5465 | #define TARGET_CONDITIONAL_REGISTER_USAGE nds32_conditional_register_usage | |
5466 | ||
9304f876 CJW |
5467 | /* -- Order of Allocation of Registers. */ |
5468 | ||
5469 | /* -- How Values Fit in Registers. */ | |
5470 | ||
e2286268 MC |
5471 | #undef TARGET_HARD_REGNO_NREGS |
5472 | #define TARGET_HARD_REGNO_NREGS nds32_hard_regno_nregs | |
5473 | ||
50256c75 CJW |
5474 | #undef TARGET_HARD_REGNO_MODE_OK |
5475 | #define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok | |
5476 | ||
5477 | #undef TARGET_MODES_TIEABLE_P | |
5478 | #define TARGET_MODES_TIEABLE_P nds32_modes_tieable_p | |
5479 | ||
9304f876 CJW |
5480 | /* -- Handling Leaf Functions. */ |
5481 | ||
5482 | /* -- Registers That Form a Stack. */ | |
5483 | ||
5484 | \f | |
5485 | /* Register Classes. */ | |
5486 | ||
5487 | #undef TARGET_CLASS_MAX_NREGS | |
5488 | #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs | |
5489 | ||
9304f876 CJW |
5490 | #undef TARGET_REGISTER_PRIORITY |
5491 | #define TARGET_REGISTER_PRIORITY nds32_register_priority | |
5492 | ||
e2286268 MC |
5493 | #undef TARGET_CAN_CHANGE_MODE_CLASS |
5494 | #define TARGET_CAN_CHANGE_MODE_CLASS nds32_can_change_mode_class | |
5495 | ||
9304f876 CJW |
5496 | \f |
5497 | /* Obsolete Macros for Defining Constraints. */ | |
5498 | ||
5499 | \f | |
5500 | /* Stack Layout and Calling Conventions. */ | |
5501 | ||
5502 | /* -- Basic Stack Layout. */ | |
5503 | ||
5504 | /* -- Exception Handling Support. */ | |
5505 | ||
5506 | /* -- Specifying How Stack Checking is Done. */ | |
5507 | ||
5508 | /* -- Registers That Address the Stack Frame. */ | |
5509 | ||
5510 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
5511 | ||
5512 | #undef TARGET_CAN_ELIMINATE | |
5513 | #define TARGET_CAN_ELIMINATE nds32_can_eliminate | |
5514 | ||
5515 | /* -- Passing Function Arguments on the Stack. */ | |
5516 | ||
5517 | /* -- Passing Arguments in Registers. */ | |
5518 | ||
5519 | #undef TARGET_FUNCTION_ARG | |
5520 | #define TARGET_FUNCTION_ARG nds32_function_arg | |
5521 | ||
d40f3c40 CJW |
5522 | #undef TARGET_MUST_PASS_IN_STACK |
5523 | #define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack | |
5524 | ||
650fc469 CJW |
5525 | #undef TARGET_ARG_PARTIAL_BYTES |
5526 | #define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes | |
5527 | ||
9304f876 CJW |
5528 | #undef TARGET_FUNCTION_ARG_ADVANCE |
5529 | #define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance | |
5530 | ||
5531 | #undef TARGET_FUNCTION_ARG_BOUNDARY | |
5532 | #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary | |
5533 | ||
7c32ef41 MC |
5534 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
5535 | #define TARGET_VECTOR_MODE_SUPPORTED_P nds32_vector_mode_supported_p | |
5536 | ||
9304f876 CJW |
5537 | /* -- How Scalar Function Values Are Returned. */ |
5538 | ||
5539 | #undef TARGET_FUNCTION_VALUE | |
5540 | #define TARGET_FUNCTION_VALUE nds32_function_value | |
5541 | ||
5542 | #undef TARGET_LIBCALL_VALUE | |
5543 | #define TARGET_LIBCALL_VALUE nds32_libcall_value | |
5544 | ||
5545 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
5546 | #define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p | |
5547 | ||
5548 | /* -- How Large Values Are Returned. */ | |
5549 | ||
e2286268 MC |
5550 | #undef TARGET_RETURN_IN_MEMORY |
5551 | #define TARGET_RETURN_IN_MEMORY nds32_return_in_memory | |
5552 | ||
9304f876 CJW |
5553 | /* -- Caller-Saves Register Allocation. */ |
5554 | ||
5555 | /* -- Function Entry and Exit. */ | |
5556 | ||
5557 | #undef TARGET_ASM_FUNCTION_PROLOGUE | |
5558 | #define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue | |
5559 | ||
5560 | #undef TARGET_ASM_FUNCTION_END_PROLOGUE | |
5561 | #define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue | |
5562 | ||
5563 | #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE | |
5564 | #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue | |
5565 | ||
5566 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
5567 | #define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue | |
5568 | ||
5569 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
5570 | #define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk | |
5571 | ||
5572 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
5573 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
5574 | ||
5575 | /* -- Generating Code for Profiling. */ | |
5576 | ||
5577 | /* -- Permitting tail calls. */ | |
5578 | ||
cc48a87f CJW |
5579 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
5580 | #define TARGET_FUNCTION_OK_FOR_SIBCALL nds32_function_ok_for_sibcall | |
5581 | ||
9304f876 CJW |
5582 | #undef TARGET_WARN_FUNC_RETURN |
5583 | #define TARGET_WARN_FUNC_RETURN nds32_warn_func_return | |
5584 | ||
5585 | /* Stack smashing protection. */ | |
5586 | ||
5587 | \f | |
5588 | /* Implementing the Varargs Macros. */ | |
5589 | ||
d4a6a4d9 CJW |
5590 | #undef TARGET_SETUP_INCOMING_VARARGS |
5591 | #define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs | |
5592 | ||
9304f876 CJW |
5593 | #undef TARGET_STRICT_ARGUMENT_NAMING |
5594 | #define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming | |
5595 | ||
5596 | \f | |
5597 | /* Trampolines for Nested Functions. */ | |
5598 | ||
5599 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE | |
5600 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template | |
5601 | ||
5602 | #undef TARGET_TRAMPOLINE_INIT | |
5603 | #define TARGET_TRAMPOLINE_INIT nds32_trampoline_init | |
5604 | ||
5605 | \f | |
5606 | /* Implicit Calls to Library Routines. */ | |
5607 | ||
5608 | \f | |
5609 | /* Addressing Modes. */ | |
5610 | ||
5611 | #undef TARGET_LEGITIMATE_ADDRESS_P | |
5612 | #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p | |
5613 | ||
85a98076 KLC |
5614 | #undef TARGET_LEGITIMIZE_ADDRESS |
5615 | #define TARGET_LEGITIMIZE_ADDRESS nds32_legitimize_address | |
5616 | ||
5617 | #undef TARGET_LEGITIMATE_CONSTANT_P | |
5618 | #define TARGET_LEGITIMATE_CONSTANT_P nds32_legitimate_constant_p | |
5619 | ||
7c32ef41 MC |
5620 | #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE |
5621 | #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE nds32_vectorize_preferred_simd_mode | |
5622 | ||
85a98076 KLC |
5623 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
5624 | #define TARGET_CANNOT_FORCE_CONST_MEM nds32_cannot_force_const_mem | |
5625 | ||
5626 | #undef TARGET_DELEGITIMIZE_ADDRESS | |
5627 | #define TARGET_DELEGITIMIZE_ADDRESS nds32_delegitimize_address | |
5628 | ||
9304f876 CJW |
5629 | \f |
5630 | /* Anchored Addresses. */ | |
5631 | ||
5632 | \f | |
5633 | /* Condition Code Status. */ | |
5634 | ||
5635 | /* -- Representation of condition codes using (cc0). */ | |
5636 | ||
5637 | /* -- Representation of condition codes using registers. */ | |
5638 | ||
5b6f2bf3 CJW |
5639 | #undef TARGET_CANONICALIZE_COMPARISON |
5640 | #define TARGET_CANONICALIZE_COMPARISON nds32_canonicalize_comparison | |
5641 | ||
9304f876 CJW |
5642 | /* -- Macros to control conditional execution. */ |
5643 | ||
5644 | \f | |
5645 | /* Describing Relative Costs of Operations. */ | |
5646 | ||
5647 | #undef TARGET_REGISTER_MOVE_COST | |
5648 | #define TARGET_REGISTER_MOVE_COST nds32_register_move_cost | |
5649 | ||
5650 | #undef TARGET_MEMORY_MOVE_COST | |
5651 | #define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost | |
5652 | ||
5653 | #undef TARGET_RTX_COSTS | |
5654 | #define TARGET_RTX_COSTS nds32_rtx_costs | |
5655 | ||
5656 | #undef TARGET_ADDRESS_COST | |
5657 | #define TARGET_ADDRESS_COST nds32_address_cost | |
5658 | ||
5659 | \f | |
5660 | /* Adjusting the Instruction Scheduler. */ | |
5661 | ||
5662 | \f | |
5663 | /* Dividing the Output into Sections (Texts, Data, . . . ). */ | |
5664 | ||
511a41d7 CJW |
5665 | #undef TARGET_ENCODE_SECTION_INFO |
5666 | #define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info | |
5667 | ||
9304f876 CJW |
5668 | \f |
5669 | /* Position Independent Code. */ | |
5670 | ||
5671 | \f | |
5672 | /* Defining the Output Assembler Language. */ | |
5673 | ||
5674 | /* -- The Overall Framework of an Assembler File. */ | |
5675 | ||
5676 | #undef TARGET_ASM_FILE_START | |
5677 | #define TARGET_ASM_FILE_START nds32_asm_file_start | |
5678 | #undef TARGET_ASM_FILE_END | |
5679 | #define TARGET_ASM_FILE_END nds32_asm_file_end | |
5680 | ||
5681 | /* -- Output of Data. */ | |
5682 | ||
5683 | #undef TARGET_ASM_ALIGNED_HI_OP | |
5684 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
5685 | ||
5686 | #undef TARGET_ASM_ALIGNED_SI_OP | |
5687 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
5688 | ||
85a98076 KLC |
5689 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
5690 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nds32_asm_output_addr_const_extra | |
5691 | ||
9304f876 CJW |
5692 | /* -- Output of Uninitialized Variables. */ |
5693 | ||
5694 | /* -- Output and Generation of Labels. */ | |
5695 | ||
5696 | #undef TARGET_ASM_GLOBALIZE_LABEL | |
5697 | #define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label | |
5698 | ||
5699 | /* -- How Initialization Functions Are Handled. */ | |
5700 | ||
5701 | /* -- Macros Controlling Initialization Routines. */ | |
5702 | ||
5703 | /* -- Output of Assembler Instructions. */ | |
5704 | ||
5705 | #undef TARGET_PRINT_OPERAND | |
5706 | #define TARGET_PRINT_OPERAND nds32_print_operand | |
5707 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
5708 | #define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address | |
5709 | ||
5710 | /* -- Output of Dispatch Tables. */ | |
5711 | ||
5712 | /* -- Assembler Commands for Exception Regions. */ | |
5713 | ||
e2286268 MC |
5714 | #undef TARGET_DWARF_REGISTER_SPAN |
5715 | #define TARGET_DWARF_REGISTER_SPAN nds32_dwarf_register_span | |
5716 | ||
9304f876 CJW |
5717 | /* -- Assembler Commands for Alignment. */ |
5718 | ||
5719 | \f | |
5720 | /* Controlling Debugging Information Format. */ | |
5721 | ||
5722 | /* -- Macros Affecting All Debugging Formats. */ | |
5723 | ||
5724 | /* -- Specific Options for DBX Output. */ | |
5725 | ||
5726 | /* -- Open-Ended Hooks for DBX Format. */ | |
5727 | ||
5728 | /* -- File Names in DBX Format. */ | |
5729 | ||
180295ed | 5730 | /* -- Macros for DWARF Output. */ |
9304f876 CJW |
5731 | |
5732 | /* -- Macros for VMS Debug Format. */ | |
5733 | ||
5734 | \f | |
5735 | /* Cross Compilation and Floating Point. */ | |
5736 | ||
5737 | \f | |
5738 | /* Mode Switching Instructions. */ | |
5739 | ||
5740 | \f | |
5741 | /* Defining target-specific uses of __attribute__. */ | |
5742 | ||
5743 | #undef TARGET_ATTRIBUTE_TABLE | |
5744 | #define TARGET_ATTRIBUTE_TABLE nds32_attribute_table | |
5745 | ||
5746 | #undef TARGET_MERGE_DECL_ATTRIBUTES | |
5747 | #define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes | |
5748 | ||
5749 | #undef TARGET_INSERT_ATTRIBUTES | |
5750 | #define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes | |
5751 | ||
5752 | #undef TARGET_OPTION_PRAGMA_PARSE | |
5753 | #define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse | |
5754 | ||
5755 | #undef TARGET_OPTION_OVERRIDE | |
5756 | #define TARGET_OPTION_OVERRIDE nds32_option_override | |
5757 | ||
5758 | \f | |
5759 | /* Emulating TLS. */ | |
5760 | ||
5761 | \f | |
5762 | /* Defining coprocessor specifics for MIPS targets. */ | |
5763 | ||
5764 | \f | |
5765 | /* Parameters for Precompiled Header Validity Checking. */ | |
5766 | ||
5767 | \f | |
5768 | /* C++ ABI parameters. */ | |
5769 | ||
5770 | \f | |
5771 | /* Adding support for named address spaces. */ | |
5772 | ||
5773 | \f | |
5774 | /* Miscellaneous Parameters. */ | |
5775 | ||
823835a9 CJW |
5776 | #undef TARGET_MD_ASM_ADJUST |
5777 | #define TARGET_MD_ASM_ADJUST nds32_md_asm_adjust | |
5778 | ||
9304f876 CJW |
5779 | #undef TARGET_INIT_BUILTINS |
5780 | #define TARGET_INIT_BUILTINS nds32_init_builtins | |
5781 | ||
7a12ea32 MC |
5782 | #undef TARGET_BUILTIN_DECL |
5783 | #define TARGET_BUILTIN_DECL nds32_builtin_decl | |
5784 | ||
9304f876 CJW |
5785 | #undef TARGET_EXPAND_BUILTIN |
5786 | #define TARGET_EXPAND_BUILTIN nds32_expand_builtin | |
5787 | ||
e2286268 MC |
5788 | |
5789 | #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P | |
5790 | #define TARGET_USE_BLOCKS_FOR_CONSTANT_P nds32_use_blocks_for_constant_p | |
5791 | ||
9304f876 CJW |
5792 | \f |
5793 | /* ------------------------------------------------------------------------ */ | |
5794 | ||
5795 | /* Initialize the GCC target structure. */ | |
5796 | ||
5797 | struct gcc_target targetm = TARGET_INITIALIZER; | |
5798 | ||
5799 | /* ------------------------------------------------------------------------ */ |