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9304f876 | 1 | /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler |
85ec4feb | 2 | Copyright (C) 2012-2018 Free Software Foundation, Inc. |
9304f876 CJW |
3 | Contributed by Andes Technology Corporation. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 3, or (at your | |
10 | option) any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
19ac960a | 21 | /* ------------------------------------------------------------------------ */ |
9304f876 | 22 | |
8fcc61f8 RS |
23 | #define IN_TARGET_CODE 1 |
24 | ||
9304f876 CJW |
25 | #include "config.h" |
26 | #include "system.h" | |
27 | #include "coretypes.h" | |
c7131fb2 | 28 | #include "backend.h" |
e11c4407 | 29 | #include "target.h" |
c7131fb2 | 30 | #include "rtl.h" |
e11c4407 | 31 | #include "tree.h" |
314e6352 ML |
32 | #include "stringpool.h" |
33 | #include "attribs.h" | |
c7131fb2 | 34 | #include "df.h" |
4d0cdd0c | 35 | #include "memmodel.h" |
e11c4407 AM |
36 | #include "tm_p.h" |
37 | #include "optabs.h" /* For GEN_FCN. */ | |
38 | #include "regs.h" | |
39 | #include "emit-rtl.h" | |
40 | #include "recog.h" | |
41 | #include "diagnostic-core.h" | |
d8a2d370 DN |
42 | #include "stor-layout.h" |
43 | #include "varasm.h" | |
44 | #include "calls.h" | |
9304f876 | 45 | #include "output.h" |
36566b39 | 46 | #include "explow.h" |
9304f876 | 47 | #include "expr.h" |
9304f876 | 48 | #include "tm-constrs.h" |
9b2b7279 | 49 | #include "builtins.h" |
72b7e5e1 | 50 | #include "cpplib.h" |
9304f876 | 51 | |
994c5d85 | 52 | /* This file should be included last. */ |
d58627a0 RS |
53 | #include "target-def.h" |
54 | ||
9304f876 CJW |
55 | /* ------------------------------------------------------------------------ */ |
56 | ||
57 | /* This file is divided into five parts: | |
58 | ||
59 | PART 1: Auxiliary static variable definitions and | |
60 | target hook static variable definitions. | |
61 | ||
62 | PART 2: Auxiliary static function definitions. | |
63 | ||
64 | PART 3: Implement target hook stuff definitions. | |
65 | ||
66 | PART 4: Implemet extern function definitions, | |
67 | the prototype is in nds32-protos.h. | |
68 | ||
69 | PART 5: Initialize target hook structure and definitions. */ | |
70 | ||
71 | /* ------------------------------------------------------------------------ */ | |
72 | ||
73 | /* PART 1: Auxiliary static variable definitions and | |
74 | target hook static variable definitions. */ | |
75 | ||
9304f876 CJW |
76 | /* Define intrinsic register names. |
77 | Please refer to nds32_intrinsic.h file, the index is corresponding to | |
78 | 'enum nds32_intrinsic_registers' data type values. | |
79 | NOTE that the base value starting from 1024. */ | |
80 | static const char * const nds32_intrinsic_register_names[] = | |
81 | { | |
82 | "$PSW", "$IPSW", "$ITYPE", "$IPC" | |
83 | }; | |
84 | ||
85 | /* Defining target-specific uses of __attribute__. */ | |
86 | static const struct attribute_spec nds32_attribute_table[] = | |
87 | { | |
88 | /* Syntax: { name, min_len, max_len, decl_required, type_required, | |
4849deb1 JJ |
89 | function_type_required, affects_type_identity, handler, |
90 | exclude } */ | |
9304f876 CJW |
91 | |
92 | /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */ | |
4849deb1 | 93 | { "interrupt", 1, 64, false, false, false, false, NULL, NULL }, |
9304f876 | 94 | /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */ |
4849deb1 | 95 | { "exception", 1, 8, false, false, false, false, NULL, NULL }, |
9304f876 | 96 | /* Argument is user's interrupt numbers. The vector number is always 0. */ |
4849deb1 | 97 | { "reset", 1, 1, false, false, false, false, NULL, NULL }, |
9304f876 CJW |
98 | |
99 | /* The attributes describing isr nested type. */ | |
4849deb1 JJ |
100 | { "nested", 0, 0, false, false, false, false, NULL, NULL }, |
101 | { "not_nested", 0, 0, false, false, false, false, NULL, NULL }, | |
102 | { "nested_ready", 0, 0, false, false, false, false, NULL, NULL }, | |
9304f876 CJW |
103 | |
104 | /* The attributes describing isr register save scheme. */ | |
4849deb1 JJ |
105 | { "save_all", 0, 0, false, false, false, false, NULL, NULL }, |
106 | { "partial_save", 0, 0, false, false, false, false, NULL, NULL }, | |
9304f876 CJW |
107 | |
108 | /* The attributes used by reset attribute. */ | |
4849deb1 JJ |
109 | { "nmi", 1, 1, false, false, false, false, NULL, NULL }, |
110 | { "warm", 1, 1, false, false, false, false, NULL, NULL }, | |
9304f876 CJW |
111 | |
112 | /* The attribute telling no prologue/epilogue. */ | |
4849deb1 | 113 | { "naked", 0, 0, false, false, false, false, NULL, NULL }, |
9304f876 CJW |
114 | |
115 | /* The last attribute spec is set to be NULL. */ | |
4849deb1 | 116 | { NULL, 0, 0, false, false, false, false, NULL, NULL } |
9304f876 CJW |
117 | }; |
118 | ||
119 | ||
120 | /* ------------------------------------------------------------------------ */ | |
121 | ||
122 | /* PART 2: Auxiliary static function definitions. */ | |
123 | ||
124 | /* Function to save and restore machine-specific function data. */ | |
125 | static struct machine_function * | |
126 | nds32_init_machine_status (void) | |
127 | { | |
128 | struct machine_function *machine; | |
766090c2 | 129 | machine = ggc_cleared_alloc<machine_function> (); |
9304f876 CJW |
130 | |
131 | /* Initially assume this function needs prologue/epilogue. */ | |
132 | machine->naked_p = 0; | |
133 | ||
134 | /* Initially assume this function does NOT use fp_as_gp optimization. */ | |
135 | machine->fp_as_gp_p = 0; | |
136 | ||
137 | return machine; | |
138 | } | |
139 | ||
140 | /* Function to compute stack frame size and | |
141 | store into cfun->machine structure. */ | |
142 | static void | |
143 | nds32_compute_stack_frame (void) | |
144 | { | |
145 | int r; | |
146 | int block_size; | |
a6c7e777 | 147 | bool v3pushpop_p; |
9304f876 CJW |
148 | |
149 | /* Because nds32_compute_stack_frame() will be called from different place, | |
150 | everytime we enter this function, we have to assume this function | |
151 | needs prologue/epilogue. */ | |
152 | cfun->machine->naked_p = 0; | |
153 | ||
154 | /* Get variadic arguments size to prepare pretend arguments and | |
35da54a6 CJW |
155 | we will push them into stack at prologue by ourself. */ |
156 | cfun->machine->va_args_size = crtl->args.pretend_args_size; | |
157 | if (cfun->machine->va_args_size != 0) | |
158 | { | |
159 | cfun->machine->va_args_first_regno | |
8a498f99 CJW |
160 | = NDS32_GPR_ARG_FIRST_REGNUM |
161 | + NDS32_MAX_GPR_REGS_FOR_ARGS | |
162 | - (crtl->args.pretend_args_size / UNITS_PER_WORD); | |
35da54a6 | 163 | cfun->machine->va_args_last_regno |
8a498f99 | 164 | = NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS - 1; |
35da54a6 CJW |
165 | } |
166 | else | |
167 | { | |
168 | cfun->machine->va_args_first_regno = SP_REGNUM; | |
169 | cfun->machine->va_args_last_regno = SP_REGNUM; | |
170 | } | |
171 | ||
172 | /* Important: We need to make sure that varargs area is 8-byte alignment. */ | |
173 | block_size = cfun->machine->va_args_size; | |
174 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) | |
175 | { | |
176 | cfun->machine->va_args_area_padding_bytes | |
177 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; | |
178 | } | |
9304f876 CJW |
179 | |
180 | /* Get local variables, incoming variables, and temporary variables size. | |
181 | Note that we need to make sure it is 8-byte alignment because | |
182 | there may be no padding bytes if we are using LRA. */ | |
183 | cfun->machine->local_size = NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ()); | |
184 | ||
185 | /* Get outgoing arguments size. */ | |
186 | cfun->machine->out_args_size = crtl->outgoing_args_size; | |
187 | ||
188 | /* If $fp value is required to be saved on stack, it needs 4 bytes space. | |
189 | Check whether $fp is ever live. */ | |
190 | cfun->machine->fp_size = (df_regs_ever_live_p (FP_REGNUM)) ? 4 : 0; | |
191 | ||
192 | /* If $gp value is required to be saved on stack, it needs 4 bytes space. | |
193 | Check whether we are using PIC code genration. */ | |
194 | cfun->machine->gp_size = (flag_pic) ? 4 : 0; | |
195 | ||
196 | /* If $lp value is required to be saved on stack, it needs 4 bytes space. | |
197 | Check whether $lp is ever live. */ | |
198 | cfun->machine->lp_size = (df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0; | |
199 | ||
200 | /* Initially there is no padding bytes. */ | |
c457f751 | 201 | cfun->machine->callee_saved_area_gpr_padding_bytes = 0; |
9304f876 CJW |
202 | |
203 | /* Calculate the bytes of saving callee-saved registers on stack. */ | |
c457f751 CJW |
204 | cfun->machine->callee_saved_gpr_regs_size = 0; |
205 | cfun->machine->callee_saved_first_gpr_regno = SP_REGNUM; | |
206 | cfun->machine->callee_saved_last_gpr_regno = SP_REGNUM; | |
9304f876 CJW |
207 | /* Currently, there is no need to check $r28~$r31 |
208 | because we will save them in another way. */ | |
209 | for (r = 0; r < 28; r++) | |
210 | { | |
211 | if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) | |
212 | { | |
213 | /* Mark the first required callee-saved register | |
214 | (only need to set it once). | |
215 | If first regno == SP_REGNUM, we can tell that | |
216 | it is the first time to be here. */ | |
c457f751 CJW |
217 | if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) |
218 | cfun->machine->callee_saved_first_gpr_regno = r; | |
9304f876 | 219 | /* Mark the last required callee-saved register. */ |
c457f751 | 220 | cfun->machine->callee_saved_last_gpr_regno = r; |
9304f876 CJW |
221 | } |
222 | } | |
223 | ||
224 | /* Check if this function can omit prologue/epilogue code fragment. | |
225 | If there is 'naked' attribute in this function, | |
226 | we can set 'naked_p' flag to indicate that | |
227 | we do not have to generate prologue/epilogue. | |
228 | Or, if all the following conditions succeed, | |
229 | we can set this function 'naked_p' as well: | |
230 | condition 1: first_regno == last_regno == SP_REGNUM, | |
8a498f99 CJW |
231 | which means we do not have to save |
232 | any callee-saved registers. | |
9304f876 | 233 | condition 2: Both $lp and $fp are NOT live in this function, |
8a498f99 CJW |
234 | which means we do not need to save them and there |
235 | is no outgoing size. | |
9304f876 | 236 | condition 3: There is no local_size, which means |
8a498f99 | 237 | we do not need to adjust $sp. */ |
9304f876 | 238 | if (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) |
c457f751 CJW |
239 | || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM |
240 | && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM | |
9304f876 CJW |
241 | && !df_regs_ever_live_p (FP_REGNUM) |
242 | && !df_regs_ever_live_p (LP_REGNUM) | |
243 | && cfun->machine->local_size == 0)) | |
244 | { | |
2da1e7c0 | 245 | /* Set this function 'naked_p' and other functions can check this flag. |
8a498f99 CJW |
246 | Note that in nds32 port, the 'naked_p = 1' JUST means there is no |
247 | callee-saved, local size, and outgoing size. | |
248 | The varargs space and ret instruction may still present in | |
249 | the prologue/epilogue expanding. */ | |
9304f876 CJW |
250 | cfun->machine->naked_p = 1; |
251 | ||
252 | /* No need to save $fp, $gp, and $lp. | |
8a498f99 CJW |
253 | We should set these value to be zero |
254 | so that nds32_initial_elimination_offset() can work properly. */ | |
9304f876 CJW |
255 | cfun->machine->fp_size = 0; |
256 | cfun->machine->gp_size = 0; | |
257 | cfun->machine->lp_size = 0; | |
258 | ||
259 | /* If stack usage computation is required, | |
8a498f99 | 260 | we need to provide the static stack size. */ |
9304f876 CJW |
261 | if (flag_stack_usage_info) |
262 | current_function_static_stack_size = 0; | |
263 | ||
264 | /* No need to do following adjustment, return immediately. */ | |
265 | return; | |
266 | } | |
267 | ||
a6c7e777 MC |
268 | v3pushpop_p = NDS32_V3PUSH_AVAILABLE_P; |
269 | ||
9304f876 CJW |
270 | /* Adjustment for v3push instructions: |
271 | If we are using v3push (push25/pop25) instructions, | |
272 | we need to make sure Rb is $r6 and Re is | |
273 | located on $r6, $r8, $r10, or $r14. | |
274 | Some results above will be discarded and recomputed. | |
2da1e7c0 CJW |
275 | Note that it is only available under V3/V3M ISA and we |
276 | DO NOT setup following stuff for isr or variadic function. */ | |
a6c7e777 | 277 | if (v3pushpop_p) |
9304f876 CJW |
278 | { |
279 | /* Recompute: | |
8a498f99 CJW |
280 | cfun->machine->fp_size |
281 | cfun->machine->gp_size | |
282 | cfun->machine->lp_size | |
283 | cfun->machine->callee_saved_first_gpr_regno | |
284 | cfun->machine->callee_saved_last_gpr_regno */ | |
9304f876 CJW |
285 | |
286 | /* For v3push instructions, $fp, $gp, and $lp are always saved. */ | |
287 | cfun->machine->fp_size = 4; | |
288 | cfun->machine->gp_size = 4; | |
289 | cfun->machine->lp_size = 4; | |
290 | ||
291 | /* Remember to set Rb = $r6. */ | |
c457f751 | 292 | cfun->machine->callee_saved_first_gpr_regno = 6; |
9304f876 | 293 | |
c457f751 | 294 | if (cfun->machine->callee_saved_last_gpr_regno <= 6) |
9304f876 CJW |
295 | { |
296 | /* Re = $r6 */ | |
c457f751 | 297 | cfun->machine->callee_saved_last_gpr_regno = 6; |
9304f876 | 298 | } |
c457f751 | 299 | else if (cfun->machine->callee_saved_last_gpr_regno <= 8) |
9304f876 CJW |
300 | { |
301 | /* Re = $r8 */ | |
c457f751 | 302 | cfun->machine->callee_saved_last_gpr_regno = 8; |
9304f876 | 303 | } |
c457f751 | 304 | else if (cfun->machine->callee_saved_last_gpr_regno <= 10) |
9304f876 CJW |
305 | { |
306 | /* Re = $r10 */ | |
c457f751 | 307 | cfun->machine->callee_saved_last_gpr_regno = 10; |
9304f876 | 308 | } |
c457f751 | 309 | else if (cfun->machine->callee_saved_last_gpr_regno <= 14) |
9304f876 CJW |
310 | { |
311 | /* Re = $r14 */ | |
c457f751 | 312 | cfun->machine->callee_saved_last_gpr_regno = 14; |
9304f876 | 313 | } |
c457f751 | 314 | else if (cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM) |
9304f876 CJW |
315 | { |
316 | /* If last_regno is SP_REGNUM, which means | |
317 | it is never changed, so set it to Re = $r6. */ | |
c457f751 | 318 | cfun->machine->callee_saved_last_gpr_regno = 6; |
9304f876 CJW |
319 | } |
320 | else | |
321 | { | |
322 | /* The program flow should not go here. */ | |
323 | gcc_unreachable (); | |
324 | } | |
325 | } | |
326 | ||
a6c7e777 MC |
327 | int sp_adjust = cfun->machine->local_size |
328 | + cfun->machine->out_args_size | |
329 | + cfun->machine->callee_saved_area_gpr_padding_bytes; | |
330 | ||
331 | if (!v3pushpop_p | |
332 | && sp_adjust == 0 | |
333 | && !frame_pointer_needed) | |
334 | { | |
335 | block_size = cfun->machine->fp_size | |
336 | + cfun->machine->gp_size | |
337 | + cfun->machine->lp_size | |
338 | + (4 * (cfun->machine->callee_saved_last_gpr_regno | |
339 | - cfun->machine->callee_saved_first_gpr_regno | |
340 | + 1)); | |
341 | ||
342 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) | |
343 | { | |
344 | /* $r14 is last callee save register. */ | |
345 | if (cfun->machine->callee_saved_last_gpr_regno | |
346 | < NDS32_LAST_CALLEE_SAVE_GPR_REGNUM) | |
347 | { | |
348 | cfun->machine->callee_saved_last_gpr_regno++; | |
349 | } | |
350 | else if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) | |
351 | { | |
352 | cfun->machine->callee_saved_first_gpr_regno | |
353 | = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; | |
354 | cfun->machine->callee_saved_last_gpr_regno | |
355 | = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; | |
356 | } | |
357 | } | |
358 | } | |
359 | ||
8a498f99 CJW |
360 | /* We have correctly set callee_saved_first_gpr_regno |
361 | and callee_saved_last_gpr_regno. | |
362 | Initially, the callee_saved_gpr_regs_size is supposed to be 0. | |
363 | As long as callee_saved_last_gpr_regno is not SP_REGNUM, | |
364 | we can update callee_saved_gpr_regs_size with new size. */ | |
c457f751 | 365 | if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) |
9304f876 CJW |
366 | { |
367 | /* Compute pushed size of callee-saved registers. */ | |
c457f751 CJW |
368 | cfun->machine->callee_saved_gpr_regs_size |
369 | = 4 * (cfun->machine->callee_saved_last_gpr_regno | |
370 | - cfun->machine->callee_saved_first_gpr_regno | |
9304f876 CJW |
371 | + 1); |
372 | } | |
373 | ||
374 | /* Important: We need to make sure that | |
8a498f99 CJW |
375 | (fp_size + gp_size + lp_size + callee_saved_gpr_regs_size) |
376 | is 8-byte alignment. | |
377 | If it is not, calculate the padding bytes. */ | |
35da54a6 | 378 | block_size = cfun->machine->fp_size |
9304f876 CJW |
379 | + cfun->machine->gp_size |
380 | + cfun->machine->lp_size | |
c457f751 | 381 | + cfun->machine->callee_saved_gpr_regs_size; |
9304f876 CJW |
382 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) |
383 | { | |
c457f751 | 384 | cfun->machine->callee_saved_area_gpr_padding_bytes |
9304f876 CJW |
385 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; |
386 | } | |
387 | ||
388 | /* If stack usage computation is required, | |
389 | we need to provide the static stack size. */ | |
390 | if (flag_stack_usage_info) | |
391 | { | |
392 | current_function_static_stack_size | |
393 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) | |
394 | + cfun->machine->local_size | |
395 | + cfun->machine->out_args_size; | |
396 | } | |
397 | } | |
398 | ||
399 | /* Function to create a parallel rtx pattern | |
400 | which presents stack push multiple behavior. | |
401 | The overall concept are: | |
402 | "push registers to memory", | |
403 | "adjust stack pointer". */ | |
4e9a2848 | 404 | static void |
a6c7e777 MC |
405 | nds32_emit_stack_push_multiple (unsigned Rb, unsigned Re, |
406 | bool save_fp_p, bool save_gp_p, bool save_lp_p, | |
407 | bool vaarg_p) | |
9304f876 | 408 | { |
a6c7e777 | 409 | unsigned regno; |
9304f876 CJW |
410 | int extra_count; |
411 | int num_use_regs; | |
412 | int par_index; | |
413 | int offset; | |
414 | ||
415 | rtx reg; | |
416 | rtx mem; | |
417 | rtx push_rtx; | |
418 | rtx adjust_sp_rtx; | |
419 | rtx parallel_insn; | |
47e0e7d2 | 420 | rtx dwarf; |
9304f876 CJW |
421 | |
422 | /* We need to provide a customized rtx which contains | |
423 | necessary information for data analysis, | |
424 | so we create a parallel rtx like this: | |
425 | (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) | |
8a498f99 CJW |
426 | (reg:SI Rb)) |
427 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) | |
428 | (reg:SI Rb+1)) | |
429 | ... | |
430 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) | |
431 | (reg:SI Re)) | |
432 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) | |
433 | (reg:SI FP_REGNUM)) | |
434 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) | |
435 | (reg:SI GP_REGNUM)) | |
436 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) | |
437 | (reg:SI LP_REGNUM)) | |
438 | (set (reg:SI SP_REGNUM) | |
439 | (plus (reg:SI SP_REGNUM) (const_int -32)))]) */ | |
9304f876 CJW |
440 | |
441 | /* Calculate the number of registers that will be pushed. */ | |
442 | extra_count = 0; | |
a6c7e777 | 443 | if (save_fp_p) |
9304f876 | 444 | extra_count++; |
a6c7e777 | 445 | if (save_gp_p) |
9304f876 | 446 | extra_count++; |
a6c7e777 | 447 | if (save_lp_p) |
9304f876 CJW |
448 | extra_count++; |
449 | /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ | |
a6c7e777 | 450 | if (Rb == SP_REGNUM && Re == SP_REGNUM) |
9304f876 CJW |
451 | num_use_regs = extra_count; |
452 | else | |
a6c7e777 | 453 | num_use_regs = Re - Rb + 1 + extra_count; |
9304f876 CJW |
454 | |
455 | /* In addition to used registers, | |
456 | we need one more space for (set sp sp-x) rtx. */ | |
457 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
458 | rtvec_alloc (num_use_regs + 1)); | |
459 | par_index = 0; | |
460 | ||
461 | /* Initialize offset and start to create push behavior. */ | |
462 | offset = -(num_use_regs * 4); | |
463 | ||
464 | /* Create (set mem regX) from Rb, Rb+1 up to Re. */ | |
a6c7e777 | 465 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
466 | { |
467 | /* Rb and Re may be SP_REGNUM. | |
8a498f99 | 468 | We need to break this loop immediately. */ |
9304f876 | 469 | if (regno == SP_REGNUM) |
4e9a2848 | 470 | break; |
9304f876 CJW |
471 | |
472 | reg = gen_rtx_REG (SImode, regno); | |
473 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
474 | stack_pointer_rtx, | |
475 | offset)); | |
f7df4a84 | 476 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
477 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
478 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
479 | offset = offset + 4; | |
480 | par_index++; | |
481 | } | |
482 | ||
483 | /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */ | |
a6c7e777 | 484 | if (save_fp_p) |
9304f876 CJW |
485 | { |
486 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
487 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
488 | stack_pointer_rtx, | |
489 | offset)); | |
f7df4a84 | 490 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
491 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
492 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
493 | offset = offset + 4; | |
494 | par_index++; | |
495 | } | |
a6c7e777 | 496 | if (save_gp_p) |
9304f876 CJW |
497 | { |
498 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
499 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
500 | stack_pointer_rtx, | |
501 | offset)); | |
f7df4a84 | 502 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
503 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
504 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
505 | offset = offset + 4; | |
506 | par_index++; | |
507 | } | |
a6c7e777 | 508 | if (save_lp_p) |
9304f876 CJW |
509 | { |
510 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
511 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
512 | stack_pointer_rtx, | |
513 | offset)); | |
f7df4a84 | 514 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
515 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
516 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
517 | offset = offset + 4; | |
518 | par_index++; | |
519 | } | |
520 | ||
521 | /* Create (set sp sp-x). */ | |
522 | ||
523 | /* We need to re-calculate the offset value again for adjustment. */ | |
524 | offset = -(num_use_regs * 4); | |
525 | adjust_sp_rtx | |
f7df4a84 | 526 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
527 | plus_constant (Pmode, stack_pointer_rtx, offset)); |
528 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
529 | RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; | |
530 | ||
4e9a2848 CJW |
531 | parallel_insn = emit_insn (parallel_insn); |
532 | ||
533 | /* The insn rtx 'parallel_insn' will change frame layout. | |
534 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
535 | generate CFI (Call Frame Information) stuff. */ | |
536 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
47e0e7d2 CJW |
537 | |
538 | /* Don't use GCC's logic for CFI info if we are generate a push for VAARG | |
539 | since we will not restore those register at epilogue. */ | |
540 | if (vaarg_p) | |
541 | { | |
542 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, | |
543 | copy_rtx (adjust_sp_rtx), NULL_RTX); | |
544 | REG_NOTES (parallel_insn) = dwarf; | |
545 | } | |
9304f876 CJW |
546 | } |
547 | ||
548 | /* Function to create a parallel rtx pattern | |
549 | which presents stack pop multiple behavior. | |
550 | The overall concept are: | |
551 | "pop registers from memory", | |
552 | "adjust stack pointer". */ | |
4e9a2848 | 553 | static void |
a6c7e777 MC |
554 | nds32_emit_stack_pop_multiple (unsigned Rb, unsigned Re, |
555 | bool save_fp_p, bool save_gp_p, bool save_lp_p) | |
9304f876 | 556 | { |
a6c7e777 | 557 | unsigned regno; |
9304f876 CJW |
558 | int extra_count; |
559 | int num_use_regs; | |
560 | int par_index; | |
561 | int offset; | |
562 | ||
563 | rtx reg; | |
564 | rtx mem; | |
565 | rtx pop_rtx; | |
566 | rtx adjust_sp_rtx; | |
567 | rtx parallel_insn; | |
4e9a2848 | 568 | rtx dwarf = NULL_RTX; |
9304f876 CJW |
569 | |
570 | /* We need to provide a customized rtx which contains | |
571 | necessary information for data analysis, | |
572 | so we create a parallel rtx like this: | |
573 | (parallel [(set (reg:SI Rb) | |
8a498f99 CJW |
574 | (mem (reg:SI SP_REGNUM))) |
575 | (set (reg:SI Rb+1) | |
576 | (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) | |
577 | ... | |
578 | (set (reg:SI Re) | |
579 | (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) | |
580 | (set (reg:SI FP_REGNUM) | |
581 | (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) | |
582 | (set (reg:SI GP_REGNUM) | |
583 | (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) | |
584 | (set (reg:SI LP_REGNUM) | |
585 | (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) | |
586 | (set (reg:SI SP_REGNUM) | |
587 | (plus (reg:SI SP_REGNUM) (const_int 32)))]) */ | |
9304f876 CJW |
588 | |
589 | /* Calculate the number of registers that will be poped. */ | |
590 | extra_count = 0; | |
a6c7e777 | 591 | if (save_fp_p) |
9304f876 | 592 | extra_count++; |
a6c7e777 | 593 | if (save_gp_p) |
9304f876 | 594 | extra_count++; |
a6c7e777 | 595 | if (save_lp_p) |
9304f876 CJW |
596 | extra_count++; |
597 | /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ | |
a6c7e777 | 598 | if (Rb == SP_REGNUM && Re == SP_REGNUM) |
9304f876 CJW |
599 | num_use_regs = extra_count; |
600 | else | |
a6c7e777 | 601 | num_use_regs = Re - Rb + 1 + extra_count; |
9304f876 CJW |
602 | |
603 | /* In addition to used registers, | |
604 | we need one more space for (set sp sp+x) rtx. */ | |
605 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
606 | rtvec_alloc (num_use_regs + 1)); | |
607 | par_index = 0; | |
608 | ||
609 | /* Initialize offset and start to create pop behavior. */ | |
610 | offset = 0; | |
611 | ||
612 | /* Create (set regX mem) from Rb, Rb+1 up to Re. */ | |
a6c7e777 | 613 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
614 | { |
615 | /* Rb and Re may be SP_REGNUM. | |
8a498f99 | 616 | We need to break this loop immediately. */ |
9304f876 | 617 | if (regno == SP_REGNUM) |
4e9a2848 | 618 | break; |
9304f876 CJW |
619 | |
620 | reg = gen_rtx_REG (SImode, regno); | |
621 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
622 | stack_pointer_rtx, | |
623 | offset)); | |
f7df4a84 | 624 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
625 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
626 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
627 | offset = offset + 4; | |
628 | par_index++; | |
4e9a2848 CJW |
629 | |
630 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
631 | } |
632 | ||
633 | /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */ | |
a6c7e777 | 634 | if (save_fp_p) |
9304f876 CJW |
635 | { |
636 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
637 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
638 | stack_pointer_rtx, | |
639 | offset)); | |
f7df4a84 | 640 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
641 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
642 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
643 | offset = offset + 4; | |
644 | par_index++; | |
4e9a2848 CJW |
645 | |
646 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 | 647 | } |
a6c7e777 | 648 | if (save_gp_p) |
9304f876 CJW |
649 | { |
650 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
651 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
652 | stack_pointer_rtx, | |
653 | offset)); | |
f7df4a84 | 654 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
655 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
656 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
657 | offset = offset + 4; | |
658 | par_index++; | |
4e9a2848 CJW |
659 | |
660 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 | 661 | } |
a6c7e777 | 662 | if (save_lp_p) |
9304f876 CJW |
663 | { |
664 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
665 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
666 | stack_pointer_rtx, | |
667 | offset)); | |
f7df4a84 | 668 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
669 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
670 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
671 | offset = offset + 4; | |
672 | par_index++; | |
4e9a2848 CJW |
673 | |
674 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
675 | } |
676 | ||
677 | /* Create (set sp sp+x). */ | |
678 | ||
679 | /* The offset value is already in place. No need to re-calculate it. */ | |
680 | adjust_sp_rtx | |
f7df4a84 | 681 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
682 | plus_constant (Pmode, stack_pointer_rtx, offset)); |
683 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
9304f876 | 684 | |
4e9a2848 CJW |
685 | /* Tell gcc we adjust SP in this insn. */ |
686 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, copy_rtx (adjust_sp_rtx), dwarf); | |
687 | ||
688 | parallel_insn = emit_insn (parallel_insn); | |
689 | ||
690 | /* The insn rtx 'parallel_insn' will change frame layout. | |
691 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
692 | generate CFI (Call Frame Information) stuff. */ | |
693 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
694 | ||
695 | /* Add CFI info by manual. */ | |
696 | REG_NOTES (parallel_insn) = dwarf; | |
9304f876 CJW |
697 | } |
698 | ||
699 | /* Function to create a parallel rtx pattern | |
700 | which presents stack v3push behavior. | |
701 | The overall concept are: | |
702 | "push registers to memory", | |
703 | "adjust stack pointer". */ | |
88437f39 | 704 | static void |
a6c7e777 MC |
705 | nds32_emit_stack_v3push (unsigned Rb, |
706 | unsigned Re, | |
707 | unsigned imm8u) | |
9304f876 | 708 | { |
a6c7e777 | 709 | unsigned regno; |
9304f876 CJW |
710 | int num_use_regs; |
711 | int par_index; | |
712 | int offset; | |
713 | ||
714 | rtx reg; | |
715 | rtx mem; | |
716 | rtx push_rtx; | |
717 | rtx adjust_sp_rtx; | |
718 | rtx parallel_insn; | |
719 | ||
720 | /* We need to provide a customized rtx which contains | |
721 | necessary information for data analysis, | |
722 | so we create a parallel rtx like this: | |
88437f39 | 723 | (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) |
8a498f99 CJW |
724 | (reg:SI Rb)) |
725 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) | |
726 | (reg:SI Rb+1)) | |
727 | ... | |
728 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) | |
729 | (reg:SI Re)) | |
730 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) | |
731 | (reg:SI FP_REGNUM)) | |
732 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) | |
733 | (reg:SI GP_REGNUM)) | |
734 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) | |
735 | (reg:SI LP_REGNUM)) | |
736 | (set (reg:SI SP_REGNUM) | |
737 | (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */ | |
9304f876 CJW |
738 | |
739 | /* Calculate the number of registers that will be pushed. | |
740 | Since $fp, $gp, and $lp is always pushed with v3push instruction, | |
741 | we need to count these three registers. | |
742 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
743 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 744 | num_use_regs = Re - Rb + 1 + 3; |
9304f876 CJW |
745 | |
746 | /* In addition to used registers, | |
747 | we need one more space for (set sp sp-x-imm8u) rtx. */ | |
748 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
749 | rtvec_alloc (num_use_regs + 1)); | |
750 | par_index = 0; | |
751 | ||
752 | /* Initialize offset and start to create push behavior. */ | |
753 | offset = -(num_use_regs * 4); | |
754 | ||
755 | /* Create (set mem regX) from Rb, Rb+1 up to Re. | |
756 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
757 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 758 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
759 | { |
760 | reg = gen_rtx_REG (SImode, regno); | |
761 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
762 | stack_pointer_rtx, | |
763 | offset)); | |
f7df4a84 | 764 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
765 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
766 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
767 | offset = offset + 4; | |
768 | par_index++; | |
769 | } | |
770 | ||
771 | /* Create (set mem fp). */ | |
772 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
773 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
774 | stack_pointer_rtx, | |
775 | offset)); | |
f7df4a84 | 776 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
777 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
778 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
779 | offset = offset + 4; | |
780 | par_index++; | |
781 | /* Create (set mem gp). */ | |
782 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
783 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
784 | stack_pointer_rtx, | |
785 | offset)); | |
f7df4a84 | 786 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
787 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
788 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
789 | offset = offset + 4; | |
790 | par_index++; | |
791 | /* Create (set mem lp). */ | |
792 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
793 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
794 | stack_pointer_rtx, | |
795 | offset)); | |
f7df4a84 | 796 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
797 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
798 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
799 | offset = offset + 4; | |
800 | par_index++; | |
801 | ||
802 | /* Create (set sp sp-x-imm8u). */ | |
803 | ||
804 | /* We need to re-calculate the offset value again for adjustment. */ | |
805 | offset = -(num_use_regs * 4); | |
806 | adjust_sp_rtx | |
f7df4a84 | 807 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
808 | plus_constant (Pmode, |
809 | stack_pointer_rtx, | |
a6c7e777 | 810 | offset - imm8u)); |
9304f876 CJW |
811 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; |
812 | RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; | |
813 | ||
88437f39 CJW |
814 | parallel_insn = emit_insn (parallel_insn); |
815 | ||
816 | /* The insn rtx 'parallel_insn' will change frame layout. | |
817 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
818 | generate CFI (Call Frame Information) stuff. */ | |
819 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
9304f876 CJW |
820 | } |
821 | ||
822 | /* Function to create a parallel rtx pattern | |
823 | which presents stack v3pop behavior. | |
824 | The overall concept are: | |
825 | "pop registers from memory", | |
826 | "adjust stack pointer". */ | |
88437f39 | 827 | static void |
a6c7e777 MC |
828 | nds32_emit_stack_v3pop (unsigned Rb, |
829 | unsigned Re, | |
830 | unsigned imm8u) | |
9304f876 | 831 | { |
a6c7e777 | 832 | unsigned regno; |
9304f876 CJW |
833 | int num_use_regs; |
834 | int par_index; | |
835 | int offset; | |
836 | ||
837 | rtx reg; | |
838 | rtx mem; | |
839 | rtx pop_rtx; | |
840 | rtx adjust_sp_rtx; | |
841 | rtx parallel_insn; | |
88437f39 | 842 | rtx dwarf = NULL_RTX; |
9304f876 CJW |
843 | |
844 | /* We need to provide a customized rtx which contains | |
845 | necessary information for data analysis, | |
846 | so we create a parallel rtx like this: | |
847 | (parallel [(set (reg:SI Rb) | |
8a498f99 CJW |
848 | (mem (reg:SI SP_REGNUM))) |
849 | (set (reg:SI Rb+1) | |
850 | (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) | |
851 | ... | |
852 | (set (reg:SI Re) | |
853 | (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) | |
854 | (set (reg:SI FP_REGNUM) | |
855 | (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) | |
856 | (set (reg:SI GP_REGNUM) | |
857 | (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) | |
858 | (set (reg:SI LP_REGNUM) | |
859 | (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) | |
860 | (set (reg:SI SP_REGNUM) | |
861 | (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */ | |
9304f876 CJW |
862 | |
863 | /* Calculate the number of registers that will be poped. | |
864 | Since $fp, $gp, and $lp is always poped with v3pop instruction, | |
865 | we need to count these three registers. | |
866 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
867 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 868 | num_use_regs = Re - Rb + 1 + 3; |
9304f876 CJW |
869 | |
870 | /* In addition to used registers, | |
871 | we need one more space for (set sp sp+x+imm8u) rtx. */ | |
872 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
873 | rtvec_alloc (num_use_regs + 1)); | |
874 | par_index = 0; | |
875 | ||
876 | /* Initialize offset and start to create pop behavior. */ | |
877 | offset = 0; | |
878 | ||
879 | /* Create (set regX mem) from Rb, Rb+1 up to Re. | |
880 | Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
881 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 882 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
883 | { |
884 | reg = gen_rtx_REG (SImode, regno); | |
885 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
886 | stack_pointer_rtx, | |
887 | offset)); | |
f7df4a84 | 888 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
889 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
890 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
891 | offset = offset + 4; | |
892 | par_index++; | |
88437f39 CJW |
893 | |
894 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
895 | } |
896 | ||
897 | /* Create (set fp mem). */ | |
898 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
899 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
900 | stack_pointer_rtx, | |
901 | offset)); | |
f7df4a84 | 902 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
903 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
904 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
905 | offset = offset + 4; | |
906 | par_index++; | |
88437f39 CJW |
907 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
908 | ||
9304f876 CJW |
909 | /* Create (set gp mem). */ |
910 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
911 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
912 | stack_pointer_rtx, | |
913 | offset)); | |
f7df4a84 | 914 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
915 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
916 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
917 | offset = offset + 4; | |
918 | par_index++; | |
88437f39 CJW |
919 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
920 | ||
9304f876 CJW |
921 | /* Create (set lp mem ). */ |
922 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
923 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
924 | stack_pointer_rtx, | |
925 | offset)); | |
f7df4a84 | 926 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
927 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
928 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
929 | offset = offset + 4; | |
930 | par_index++; | |
88437f39 | 931 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
9304f876 CJW |
932 | |
933 | /* Create (set sp sp+x+imm8u). */ | |
934 | ||
935 | /* The offset value is already in place. No need to re-calculate it. */ | |
936 | adjust_sp_rtx | |
f7df4a84 | 937 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
938 | plus_constant (Pmode, |
939 | stack_pointer_rtx, | |
a6c7e777 | 940 | offset + imm8u)); |
9304f876 | 941 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; |
9304f876 | 942 | |
a6c7e777 MC |
943 | if (frame_pointer_needed) |
944 | { | |
945 | /* (expr_list:REG_CFA_DEF_CFA (plus:SI (reg/f:SI $sp) | |
946 | (const_int 0)) | |
947 | mean reset frame pointer to $sp and reset to offset 0. */ | |
948 | rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
949 | const0_rtx); | |
950 | dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); | |
951 | } | |
952 | else | |
953 | { | |
954 | /* Tell gcc we adjust SP in this insn. */ | |
955 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, | |
956 | copy_rtx (adjust_sp_rtx), dwarf); | |
957 | } | |
88437f39 CJW |
958 | |
959 | parallel_insn = emit_insn (parallel_insn); | |
960 | ||
961 | /* The insn rtx 'parallel_insn' will change frame layout. | |
962 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
963 | generate CFI (Call Frame Information) stuff. */ | |
964 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
965 | ||
966 | /* Add CFI info by manual. */ | |
967 | REG_NOTES (parallel_insn) = dwarf; | |
9304f876 CJW |
968 | } |
969 | ||
9304f876 CJW |
970 | /* Function that may creates more instructions |
971 | for large value on adjusting stack pointer. | |
972 | ||
973 | In nds32 target, 'addi' can be used for stack pointer | |
974 | adjustment in prologue/epilogue stage. | |
975 | However, sometimes there are too many local variables so that | |
976 | the adjustment value is not able to be fit in the 'addi' instruction. | |
977 | One solution is to move value into a register | |
978 | and then use 'add' instruction. | |
a6c7e777 MC |
979 | In practice, we use TA_REGNUM ($r15) to accomplish this purpose. */ |
980 | static void | |
981 | nds32_emit_adjust_frame (rtx to_reg, rtx from_reg, int adjust_value) | |
9304f876 | 982 | { |
9304f876 | 983 | rtx tmp_reg; |
a6c7e777 MC |
984 | rtx frame_adjust_insn; |
985 | rtx adjust_value_rtx = GEN_INT (adjust_value); | |
9304f876 | 986 | |
a6c7e777 MC |
987 | if (adjust_value == 0) |
988 | return; | |
989 | ||
990 | if (!satisfies_constraint_Is15 (adjust_value_rtx)) | |
9304f876 CJW |
991 | { |
992 | /* The value is not able to fit in single addi instruction. | |
8a498f99 CJW |
993 | Create more instructions of moving value into a register |
994 | and then add stack pointer with it. */ | |
9304f876 CJW |
995 | |
996 | /* $r15 is going to be temporary register to hold the value. */ | |
997 | tmp_reg = gen_rtx_REG (SImode, TA_REGNUM); | |
998 | ||
999 | /* Create one more instruction to move value | |
8a498f99 | 1000 | into the temporary register. */ |
a6c7e777 | 1001 | emit_move_insn (tmp_reg, adjust_value_rtx); |
9304f876 CJW |
1002 | |
1003 | /* Create new 'add' rtx. */ | |
a6c7e777 MC |
1004 | frame_adjust_insn = gen_addsi3 (to_reg, |
1005 | from_reg, | |
1006 | tmp_reg); | |
9304f876 | 1007 | /* Emit rtx into insn list and receive its transformed insn rtx. */ |
a6c7e777 | 1008 | frame_adjust_insn = emit_insn (frame_adjust_insn); |
9304f876 | 1009 | |
a6c7e777 MC |
1010 | /* Because (tmp_reg <- full_value) may be split into two |
1011 | rtl patterns, we can not set its RTX_FRAME_RELATED_P. | |
1012 | We need to construct another (sp <- sp + full_value) | |
1013 | and then insert it into sp_adjust_insn's reg note to | |
1014 | represent a frame related expression. | |
1015 | GCC knows how to refer it and output debug information. */ | |
9304f876 | 1016 | |
a6c7e777 MC |
1017 | rtx plus_rtx; |
1018 | rtx set_rtx; | |
9304f876 | 1019 | |
a6c7e777 MC |
1020 | plus_rtx = plus_constant (Pmode, from_reg, adjust_value); |
1021 | set_rtx = gen_rtx_SET (to_reg, plus_rtx); | |
1022 | add_reg_note (frame_adjust_insn, REG_FRAME_RELATED_EXPR, set_rtx); | |
9304f876 CJW |
1023 | } |
1024 | else | |
1025 | { | |
a6c7e777 MC |
1026 | /* Generate sp adjustment instruction if and only if sp_adjust != 0. */ |
1027 | frame_adjust_insn = gen_addsi3 (to_reg, | |
1028 | from_reg, | |
1029 | adjust_value_rtx); | |
1030 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
1031 | frame_adjust_insn = emit_insn (frame_adjust_insn); | |
9304f876 | 1032 | } |
a6c7e777 MC |
1033 | |
1034 | /* The insn rtx 'sp_adjust_insn' will change frame layout. | |
1035 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1036 | generate CFI (Call Frame Information) stuff. */ | |
1037 | RTX_FRAME_RELATED_P (frame_adjust_insn) = 1; | |
9304f876 CJW |
1038 | } |
1039 | ||
1040 | /* Return true if MODE/TYPE need double word alignment. */ | |
1041 | static bool | |
ef4bddc2 | 1042 | nds32_needs_double_word_align (machine_mode mode, const_tree type) |
9304f876 CJW |
1043 | { |
1044 | unsigned int align; | |
1045 | ||
634bdae9 CJW |
1046 | /* Pick up the alignment according to the mode or type. */ |
1047 | align = NDS32_MODE_TYPE_ALIGN (mode, type); | |
9304f876 CJW |
1048 | |
1049 | return (align > PARM_BOUNDARY); | |
1050 | } | |
1051 | ||
1052 | /* Return true if FUNC is a naked function. */ | |
810f736f CJW |
1053 | static bool |
1054 | nds32_naked_function_p (tree func) | |
9304f876 CJW |
1055 | { |
1056 | tree t; | |
1057 | ||
1058 | if (TREE_CODE (func) != FUNCTION_DECL) | |
1059 | abort (); | |
1060 | ||
1061 | t = lookup_attribute ("naked", DECL_ATTRIBUTES (func)); | |
1062 | ||
1063 | return (t != NULL_TREE); | |
1064 | } | |
1065 | ||
1066 | /* Function that check if 'X' is a valid address register. | |
1067 | The variable 'STRICT' is very important to | |
1068 | make decision for register number. | |
1069 | ||
1070 | STRICT : true | |
1071 | => We are in reload pass or after reload pass. | |
8a498f99 | 1072 | The register number should be strictly limited in general registers. |
9304f876 CJW |
1073 | |
1074 | STRICT : false | |
1075 | => Before reload pass, we are free to use any register number. */ | |
1076 | static bool | |
1077 | nds32_address_register_rtx_p (rtx x, bool strict) | |
1078 | { | |
1079 | int regno; | |
1080 | ||
1081 | if (GET_CODE (x) != REG) | |
1082 | return false; | |
1083 | ||
1084 | regno = REGNO (x); | |
1085 | ||
1086 | if (strict) | |
1087 | return REGNO_OK_FOR_BASE_P (regno); | |
1088 | else | |
1089 | return true; | |
1090 | } | |
1091 | ||
1092 | /* Function that check if 'INDEX' is valid to be a index rtx for address. | |
1093 | ||
1094 | OUTER_MODE : Machine mode of outer address rtx. | |
8a498f99 | 1095 | INDEX : Check if this rtx is valid to be a index for address. |
9304f876 CJW |
1096 | STRICT : If it is true, we are in reload pass or after reload pass. */ |
1097 | static bool | |
ef4bddc2 | 1098 | nds32_legitimate_index_p (machine_mode outer_mode, |
9304f876 CJW |
1099 | rtx index, |
1100 | bool strict) | |
1101 | { | |
1102 | int regno; | |
1103 | rtx op0; | |
1104 | rtx op1; | |
1105 | ||
1106 | switch (GET_CODE (index)) | |
1107 | { | |
1108 | case REG: | |
1109 | regno = REGNO (index); | |
1110 | /* If we are in reload pass or after reload pass, | |
8a498f99 | 1111 | we need to limit it to general register. */ |
9304f876 CJW |
1112 | if (strict) |
1113 | return REGNO_OK_FOR_INDEX_P (regno); | |
1114 | else | |
1115 | return true; | |
1116 | ||
1117 | case CONST_INT: | |
1118 | /* The alignment of the integer value is determined by 'outer_mode'. */ | |
1119 | if (GET_MODE_SIZE (outer_mode) == 1) | |
1120 | { | |
1121 | /* Further check if the value is legal for the 'outer_mode'. */ | |
1122 | if (!satisfies_constraint_Is15 (index)) | |
1123 | return false; | |
1124 | ||
1125 | /* Pass all test, the value is valid, return true. */ | |
1126 | return true; | |
1127 | } | |
1128 | if (GET_MODE_SIZE (outer_mode) == 2 | |
1129 | && NDS32_HALF_WORD_ALIGN_P (INTVAL (index))) | |
1130 | { | |
1131 | /* Further check if the value is legal for the 'outer_mode'. */ | |
1132 | if (!satisfies_constraint_Is16 (index)) | |
1133 | return false; | |
1134 | ||
1135 | /* Pass all test, the value is valid, return true. */ | |
1136 | return true; | |
1137 | } | |
1138 | if (GET_MODE_SIZE (outer_mode) == 4 | |
1139 | && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) | |
1140 | { | |
1141 | /* Further check if the value is legal for the 'outer_mode'. */ | |
1142 | if (!satisfies_constraint_Is17 (index)) | |
1143 | return false; | |
1144 | ||
1145 | /* Pass all test, the value is valid, return true. */ | |
1146 | return true; | |
1147 | } | |
1148 | if (GET_MODE_SIZE (outer_mode) == 8 | |
1149 | && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) | |
1150 | { | |
1151 | /* Further check if the value is legal for the 'outer_mode'. */ | |
1152 | if (!satisfies_constraint_Is17 (gen_int_mode (INTVAL (index) + 4, | |
1153 | SImode))) | |
1154 | return false; | |
1155 | ||
1156 | /* Pass all test, the value is valid, return true. */ | |
1157 | return true; | |
1158 | } | |
1159 | ||
1160 | return false; | |
1161 | ||
1162 | case MULT: | |
1163 | op0 = XEXP (index, 0); | |
1164 | op1 = XEXP (index, 1); | |
1165 | ||
1166 | if (REG_P (op0) && CONST_INT_P (op1)) | |
1167 | { | |
1168 | int multiplier; | |
1169 | multiplier = INTVAL (op1); | |
1170 | ||
1171 | /* We only allow (mult reg const_int_1) | |
1172 | or (mult reg const_int_2) or (mult reg const_int_4). */ | |
1173 | if (multiplier != 1 && multiplier != 2 && multiplier != 4) | |
1174 | return false; | |
1175 | ||
1176 | regno = REGNO (op0); | |
1177 | /* Limit it in general registers if we are | |
1178 | in reload pass or after reload pass. */ | |
1179 | if(strict) | |
1180 | return REGNO_OK_FOR_INDEX_P (regno); | |
1181 | else | |
1182 | return true; | |
1183 | } | |
1184 | ||
1185 | return false; | |
1186 | ||
1187 | case ASHIFT: | |
1188 | op0 = XEXP (index, 0); | |
1189 | op1 = XEXP (index, 1); | |
1190 | ||
1191 | if (REG_P (op0) && CONST_INT_P (op1)) | |
1192 | { | |
1193 | int sv; | |
1194 | /* op1 is already the sv value for use to do left shift. */ | |
1195 | sv = INTVAL (op1); | |
1196 | ||
1197 | /* We only allow (ashift reg const_int_0) | |
1198 | or (ashift reg const_int_1) or (ashift reg const_int_2). */ | |
1199 | if (sv != 0 && sv != 1 && sv !=2) | |
1200 | return false; | |
1201 | ||
1202 | regno = REGNO (op0); | |
1203 | /* Limit it in general registers if we are | |
1204 | in reload pass or after reload pass. */ | |
1205 | if(strict) | |
1206 | return REGNO_OK_FOR_INDEX_P (regno); | |
1207 | else | |
1208 | return true; | |
1209 | } | |
1210 | ||
1211 | return false; | |
1212 | ||
1213 | default: | |
1214 | return false; | |
1215 | } | |
1216 | } | |
1217 | ||
9304f876 CJW |
1218 | /* ------------------------------------------------------------------------ */ |
1219 | ||
1220 | /* PART 3: Implement target hook stuff definitions. */ | |
1221 | \f | |
1222 | /* Register Classes. */ | |
1223 | ||
1224 | static unsigned char | |
1225 | nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED, | |
ef4bddc2 | 1226 | machine_mode mode) |
9304f876 CJW |
1227 | { |
1228 | /* Return the maximum number of consecutive registers | |
1229 | needed to represent "mode" in a register of "rclass". */ | |
1230 | return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); | |
1231 | } | |
1232 | ||
1233 | static int | |
1234 | nds32_register_priority (int hard_regno) | |
1235 | { | |
1236 | /* Encourage to use r0-r7 for LRA when optimize for size. */ | |
1237 | if (optimize_size && hard_regno < 8) | |
1238 | return 4; | |
1239 | return 3; | |
1240 | } | |
1241 | ||
1242 | \f | |
1243 | /* Stack Layout and Calling Conventions. */ | |
1244 | ||
1245 | /* There are three kinds of pointer concepts using in GCC compiler: | |
1246 | ||
1247 | frame pointer: A pointer to the first location of local variables. | |
1248 | stack pointer: A pointer to the top of a stack frame. | |
1249 | argument pointer: A pointer to the incoming arguments. | |
1250 | ||
1251 | In nds32 target calling convention, we are using 8-byte alignment. | |
1252 | Besides, we would like to have each stack frame of a function includes: | |
1253 | ||
1254 | [Block A] | |
1255 | 1. previous hard frame pointer | |
1256 | 2. return address | |
1257 | 3. callee-saved registers | |
1258 | 4. <padding bytes> (we will calculte in nds32_compute_stack_frame() | |
8a498f99 CJW |
1259 | and save it at |
1260 | cfun->machine->callee_saved_area_padding_bytes) | |
9304f876 CJW |
1261 | |
1262 | [Block B] | |
1263 | 1. local variables | |
1264 | 2. spilling location | |
1265 | 3. <padding bytes> (it will be calculated by GCC itself) | |
1266 | 4. incoming arguments | |
1267 | 5. <padding bytes> (it will be calculated by GCC itself) | |
1268 | ||
1269 | [Block C] | |
1270 | 1. <padding bytes> (it will be calculated by GCC itself) | |
1271 | 2. outgoing arguments | |
1272 | ||
1273 | We 'wrap' these blocks together with | |
1274 | hard frame pointer ($r28) and stack pointer ($r31). | |
1275 | By applying the basic frame/stack/argument pointers concept, | |
1276 | the layout of a stack frame shoule be like this: | |
1277 | ||
8a498f99 | 1278 | | | |
9304f876 | 1279 | old stack pointer -> ---- |
8a498f99 CJW |
1280 | | | \ |
1281 | | | saved arguments for | |
1282 | | | vararg functions | |
1283 | | | / | |
9304f876 CJW |
1284 | hard frame pointer -> -- |
1285 | & argument pointer | | \ | |
8a498f99 CJW |
1286 | | | previous hardware frame pointer |
1287 | | | return address | |
1288 | | | callee-saved registers | |
1289 | | | / | |
1290 | frame pointer -> -- | |
1291 | | | \ | |
1292 | | | local variables | |
1293 | | | and incoming arguments | |
1294 | | | / | |
1295 | -- | |
1296 | | | \ | |
1297 | | | outgoing | |
1298 | | | arguments | |
1299 | | | / | |
1300 | stack pointer -> ---- | |
9304f876 CJW |
1301 | |
1302 | $SFP and $AP are used to represent frame pointer and arguments pointer, | |
1303 | which will be both eliminated as hard frame pointer. */ | |
1304 | ||
1305 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
1306 | ||
19ac960a CJW |
1307 | static bool |
1308 | nds32_can_eliminate (const int from_reg, const int to_reg) | |
9304f876 CJW |
1309 | { |
1310 | if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
1311 | return true; | |
1312 | ||
1313 | if (from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) | |
1314 | return true; | |
1315 | ||
1316 | if (from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
1317 | return true; | |
1318 | ||
1319 | if (from_reg == FRAME_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) | |
1320 | return true; | |
1321 | ||
1322 | return false; | |
1323 | } | |
1324 | ||
1325 | /* -- Passing Arguments in Registers. */ | |
1326 | ||
1327 | static rtx | |
ef4bddc2 | 1328 | nds32_function_arg (cumulative_args_t ca, machine_mode mode, |
9304f876 CJW |
1329 | const_tree type, bool named) |
1330 | { | |
7f6cd86b | 1331 | unsigned int regno; |
9304f876 CJW |
1332 | CUMULATIVE_ARGS *cum = get_cumulative_args (ca); |
1333 | ||
1334 | /* The last time this hook is called, | |
1335 | it is called with MODE == VOIDmode. */ | |
1336 | if (mode == VOIDmode) | |
1337 | return NULL_RTX; | |
1338 | ||
7f6cd86b | 1339 | /* For nameless arguments, we need to take care it individually. */ |
9304f876 | 1340 | if (!named) |
9304f876 | 1341 | { |
7f6cd86b | 1342 | /* If we are under hard float abi, we have arguments passed on the |
8a498f99 | 1343 | stack and all situation can be handled by GCC itself. */ |
7f6cd86b CJW |
1344 | if (TARGET_HARD_FLOAT) |
1345 | return NULL_RTX; | |
1346 | ||
1347 | if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) | |
1348 | { | |
1349 | /* If we still have enough registers to pass argument, pick up | |
1350 | next available register number. */ | |
1351 | regno | |
1352 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1353 | return gen_rtx_REG (mode, regno); | |
1354 | } | |
634bdae9 | 1355 | |
9304f876 | 1356 | /* No register available, return NULL_RTX. |
8a498f99 | 1357 | The compiler will use stack to pass argument instead. */ |
9304f876 CJW |
1358 | return NULL_RTX; |
1359 | } | |
7f6cd86b CJW |
1360 | |
1361 | /* The following is to handle named argument. | |
1362 | Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT | |
1363 | are different. */ | |
1364 | if (TARGET_HARD_FLOAT) | |
1365 | { | |
1366 | /* Currently we have not implemented hard float yet. */ | |
1367 | gcc_unreachable (); | |
1368 | } | |
1369 | else | |
1370 | { | |
1371 | /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass | |
8a498f99 CJW |
1372 | argument. Since we allow to pass argument partially in registers, |
1373 | we can just return it if there are still registers available. */ | |
7f6cd86b CJW |
1374 | if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) |
1375 | { | |
1376 | /* Pick up the next available register number. */ | |
1377 | regno | |
1378 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1379 | return gen_rtx_REG (mode, regno); | |
1380 | } | |
1381 | ||
1382 | } | |
1383 | ||
1384 | /* No register available, return NULL_RTX. | |
1385 | The compiler will use stack to pass argument instead. */ | |
1386 | return NULL_RTX; | |
9304f876 CJW |
1387 | } |
1388 | ||
d40f3c40 | 1389 | static bool |
ef4bddc2 | 1390 | nds32_must_pass_in_stack (machine_mode mode, const_tree type) |
d40f3c40 CJW |
1391 | { |
1392 | /* Return true if a type must be passed in memory. | |
1393 | If it is NOT using hard float abi, small aggregates can be | |
1394 | passed in a register even we are calling a variadic function. | |
1395 | So there is no need to take padding into consideration. */ | |
1396 | if (TARGET_HARD_FLOAT) | |
1397 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
1398 | else | |
1399 | return must_pass_in_stack_var_size (mode, type); | |
1400 | } | |
1401 | ||
650fc469 | 1402 | static int |
ef4bddc2 | 1403 | nds32_arg_partial_bytes (cumulative_args_t ca, machine_mode mode, |
650fc469 CJW |
1404 | tree type, bool named ATTRIBUTE_UNUSED) |
1405 | { | |
1406 | /* Returns the number of bytes at the beginning of an argument that | |
1407 | must be put in registers. The value must be zero for arguments that are | |
1408 | passed entirely in registers or that are entirely pushed on the stack. | |
1409 | Besides, TARGET_FUNCTION_ARG for these arguments should return the | |
1410 | first register to be used by the caller for this argument. */ | |
1411 | unsigned int needed_reg_count; | |
1412 | unsigned int remaining_reg_count; | |
1413 | CUMULATIVE_ARGS *cum; | |
1414 | ||
1415 | cum = get_cumulative_args (ca); | |
1416 | ||
1417 | /* Under hard float abi, we better have argument entirely passed in | |
1418 | registers or pushed on the stack so that we can reduce the complexity | |
1419 | of dealing with cum->gpr_offset and cum->fpr_offset. */ | |
1420 | if (TARGET_HARD_FLOAT) | |
1421 | return 0; | |
1422 | ||
1423 | /* If we have already runned out of argument registers, return zero | |
1424 | so that the argument will be entirely pushed on the stack. */ | |
1425 | if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
1426 | >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS) | |
1427 | return 0; | |
1428 | ||
1429 | /* Calculate how many registers do we need for this argument. */ | |
1430 | needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
1431 | ||
1432 | /* Calculate how many argument registers have left for passing argument. | |
1433 | Note that we should count it from next available register number. */ | |
1434 | remaining_reg_count | |
1435 | = NDS32_MAX_GPR_REGS_FOR_ARGS | |
1436 | - (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
8a498f99 | 1437 | - NDS32_GPR_ARG_FIRST_REGNUM); |
650fc469 CJW |
1438 | |
1439 | /* Note that we have to return the nubmer of bytes, not registers count. */ | |
1440 | if (needed_reg_count > remaining_reg_count) | |
1441 | return remaining_reg_count * UNITS_PER_WORD; | |
1442 | ||
1443 | return 0; | |
1444 | } | |
1445 | ||
9304f876 | 1446 | static void |
ef4bddc2 | 1447 | nds32_function_arg_advance (cumulative_args_t ca, machine_mode mode, |
9304f876 CJW |
1448 | const_tree type, bool named) |
1449 | { | |
ef4bddc2 | 1450 | machine_mode sub_mode; |
9304f876 CJW |
1451 | CUMULATIVE_ARGS *cum = get_cumulative_args (ca); |
1452 | ||
9304f876 CJW |
1453 | if (named) |
1454 | { | |
7f6cd86b CJW |
1455 | /* We need to further check TYPE and MODE so that we can determine |
1456 | which kind of register we shall advance. */ | |
1457 | if (type && TREE_CODE (type) == COMPLEX_TYPE) | |
1458 | sub_mode = TYPE_MODE (TREE_TYPE (type)); | |
1459 | else | |
1460 | sub_mode = mode; | |
1461 | ||
1462 | /* Under hard float abi, we may advance FPR registers. */ | |
1463 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (sub_mode) == MODE_FLOAT) | |
1464 | { | |
1465 | /* Currently we have not implemented hard float yet. */ | |
1466 | gcc_unreachable (); | |
1467 | } | |
1468 | else | |
1469 | { | |
1470 | cum->gpr_offset | |
1471 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
1472 | - NDS32_GPR_ARG_FIRST_REGNUM | |
1473 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
1474 | } | |
1475 | } | |
1476 | else | |
1477 | { | |
1478 | /* If this nameless argument is NOT under TARGET_HARD_FLOAT, | |
8a498f99 CJW |
1479 | we can advance next register as well so that caller is |
1480 | able to pass arguments in registers and callee must be | |
1481 | in charge of pushing all of them into stack. */ | |
7f6cd86b CJW |
1482 | if (!TARGET_HARD_FLOAT) |
1483 | { | |
1484 | cum->gpr_offset | |
1485 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
1486 | - NDS32_GPR_ARG_FIRST_REGNUM | |
1487 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
1488 | } | |
9304f876 CJW |
1489 | } |
1490 | } | |
1491 | ||
1492 | static unsigned int | |
ef4bddc2 | 1493 | nds32_function_arg_boundary (machine_mode mode, const_tree type) |
9304f876 CJW |
1494 | { |
1495 | return (nds32_needs_double_word_align (mode, type) | |
1496 | ? NDS32_DOUBLE_WORD_ALIGNMENT | |
1497 | : PARM_BOUNDARY); | |
1498 | } | |
1499 | ||
1500 | /* -- How Scalar Function Values Are Returned. */ | |
1501 | ||
1502 | static rtx | |
1503 | nds32_function_value (const_tree ret_type, | |
1504 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
1505 | bool outgoing ATTRIBUTE_UNUSED) | |
1506 | { | |
ef4bddc2 | 1507 | machine_mode mode; |
9304f876 CJW |
1508 | int unsignedp; |
1509 | ||
1510 | mode = TYPE_MODE (ret_type); | |
1511 | unsignedp = TYPE_UNSIGNED (ret_type); | |
1512 | ||
1513 | mode = promote_mode (ret_type, mode, &unsignedp); | |
1514 | ||
1515 | return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); | |
1516 | } | |
1517 | ||
1518 | static rtx | |
ef4bddc2 | 1519 | nds32_libcall_value (machine_mode mode, |
9304f876 CJW |
1520 | const_rtx fun ATTRIBUTE_UNUSED) |
1521 | { | |
1522 | return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); | |
1523 | } | |
1524 | ||
1525 | static bool | |
1526 | nds32_function_value_regno_p (const unsigned int regno) | |
1527 | { | |
1528 | return (regno == NDS32_GPR_RET_FIRST_REGNUM); | |
1529 | } | |
1530 | ||
1531 | /* -- Function Entry and Exit. */ | |
1532 | ||
1533 | /* The content produced from this function | |
1534 | will be placed before prologue body. */ | |
1535 | static void | |
42776416 | 1536 | nds32_asm_function_prologue (FILE *file) |
9304f876 CJW |
1537 | { |
1538 | int r; | |
1539 | const char *func_name; | |
1540 | tree attrs; | |
1541 | tree name; | |
1542 | ||
1543 | /* All stack frame information is supposed to be | |
1544 | already computed when expanding prologue. | |
1545 | The result is in cfun->machine. | |
1546 | DO NOT call nds32_compute_stack_frame() here | |
1547 | because it may corrupt the essential information. */ | |
1548 | ||
1549 | fprintf (file, "\t! BEGIN PROLOGUE\n"); | |
1550 | fprintf (file, "\t! fp needed: %d\n", frame_pointer_needed); | |
1551 | fprintf (file, "\t! pretend_args: %d\n", cfun->machine->va_args_size); | |
1552 | fprintf (file, "\t! local_size: %d\n", cfun->machine->local_size); | |
1553 | fprintf (file, "\t! out_args_size: %d\n", cfun->machine->out_args_size); | |
1554 | ||
1555 | /* Use df_regs_ever_live_p() to detect if the register | |
1556 | is ever used in the current function. */ | |
1557 | fprintf (file, "\t! registers ever_live: "); | |
1558 | for (r = 0; r < 32; r++) | |
1559 | { | |
1560 | if (df_regs_ever_live_p (r)) | |
1561 | fprintf (file, "%s, ", reg_names[r]); | |
1562 | } | |
1563 | fputc ('\n', file); | |
1564 | ||
1565 | /* Display the attributes of this function. */ | |
1566 | fprintf (file, "\t! function attributes: "); | |
f2dafb91 CJW |
1567 | /* Get the attributes tree list. |
1568 | Note that GCC builds attributes list with reverse order. */ | |
1569 | attrs = DECL_ATTRIBUTES (current_function_decl); | |
9304f876 CJW |
1570 | |
1571 | /* If there is no any attribute, print out "None". */ | |
1572 | if (!attrs) | |
1573 | fprintf (file, "None"); | |
1574 | ||
1575 | /* If there are some attributes, try if we need to | |
1576 | construct isr vector information. */ | |
1577 | func_name = IDENTIFIER_POINTER (DECL_NAME (current_function_decl)); | |
1578 | nds32_construct_isr_vectors_information (attrs, func_name); | |
1579 | ||
1580 | /* Display all attributes of this function. */ | |
1581 | while (attrs) | |
1582 | { | |
1583 | name = TREE_PURPOSE (attrs); | |
1584 | fprintf (file, "%s ", IDENTIFIER_POINTER (name)); | |
1585 | ||
1586 | /* Pick up the next attribute. */ | |
1587 | attrs = TREE_CHAIN (attrs); | |
1588 | } | |
1589 | fputc ('\n', file); | |
1590 | } | |
1591 | ||
1592 | /* After rtl prologue has been expanded, this function is used. */ | |
1593 | static void | |
1594 | nds32_asm_function_end_prologue (FILE *file) | |
1595 | { | |
1596 | fprintf (file, "\t! END PROLOGUE\n"); | |
1597 | ||
1598 | /* If frame pointer is NOT needed and -mfp-as-gp is issued, | |
1599 | we can generate special directive: ".omit_fp_begin" | |
1600 | to guide linker doing fp-as-gp optimization. | |
1601 | However, for a naked function, which means | |
1602 | it should not have prologue/epilogue, | |
1603 | using fp-as-gp still requires saving $fp by push/pop behavior and | |
1604 | there is no benefit to use fp-as-gp on such small function. | |
1605 | So we need to make sure this function is NOT naked as well. */ | |
1606 | if (!frame_pointer_needed | |
1607 | && !cfun->machine->naked_p | |
1608 | && cfun->machine->fp_as_gp_p) | |
1609 | { | |
1610 | fprintf (file, "\t! ----------------------------------------\n"); | |
1611 | fprintf (file, "\t! Guide linker to do " | |
1612 | "link time optimization: fp-as-gp\n"); | |
1613 | fprintf (file, "\t! We add one more instruction to " | |
1614 | "initialize $fp near to $gp location.\n"); | |
1615 | fprintf (file, "\t! If linker fails to use fp-as-gp transformation,\n"); | |
1616 | fprintf (file, "\t! this extra instruction should be " | |
1617 | "eliminated at link stage.\n"); | |
1618 | fprintf (file, "\t.omit_fp_begin\n"); | |
1619 | fprintf (file, "\tla\t$fp,_FP_BASE_\n"); | |
1620 | fprintf (file, "\t! ----------------------------------------\n"); | |
1621 | } | |
1622 | } | |
1623 | ||
1624 | /* Before rtl epilogue has been expanded, this function is used. */ | |
1625 | static void | |
1626 | nds32_asm_function_begin_epilogue (FILE *file) | |
1627 | { | |
1628 | /* If frame pointer is NOT needed and -mfp-as-gp is issued, | |
1629 | we can generate special directive: ".omit_fp_end" | |
1630 | to claim fp-as-gp optimization range. | |
1631 | However, for a naked function, | |
1632 | which means it should not have prologue/epilogue, | |
1633 | using fp-as-gp still requires saving $fp by push/pop behavior and | |
1634 | there is no benefit to use fp-as-gp on such small function. | |
1635 | So we need to make sure this function is NOT naked as well. */ | |
1636 | if (!frame_pointer_needed | |
1637 | && !cfun->machine->naked_p | |
1638 | && cfun->machine->fp_as_gp_p) | |
1639 | { | |
1640 | fprintf (file, "\t! ----------------------------------------\n"); | |
1641 | fprintf (file, "\t! Claim the range of fp-as-gp " | |
1642 | "link time optimization\n"); | |
1643 | fprintf (file, "\t.omit_fp_end\n"); | |
1644 | fprintf (file, "\t! ----------------------------------------\n"); | |
1645 | } | |
1646 | ||
1647 | fprintf (file, "\t! BEGIN EPILOGUE\n"); | |
1648 | } | |
1649 | ||
1650 | /* The content produced from this function | |
1651 | will be placed after epilogue body. */ | |
1652 | static void | |
42776416 | 1653 | nds32_asm_function_epilogue (FILE *file) |
9304f876 CJW |
1654 | { |
1655 | fprintf (file, "\t! END EPILOGUE\n"); | |
1656 | } | |
1657 | ||
1658 | static void | |
1659 | nds32_asm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, | |
1660 | HOST_WIDE_INT delta, | |
1661 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
1662 | tree function) | |
1663 | { | |
1664 | int this_regno; | |
1665 | ||
1666 | /* Make sure unwind info is emitted for the thunk if needed. */ | |
1667 | final_start_function (emit_barrier (), file, 1); | |
1668 | ||
1669 | this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) | |
1670 | ? 1 | |
1671 | : 0); | |
1672 | ||
1673 | if (delta != 0) | |
1674 | { | |
1675 | if (satisfies_constraint_Is15 (GEN_INT (delta))) | |
1676 | { | |
1677 | fprintf (file, "\taddi\t$r%d, $r%d, %ld\n", | |
1678 | this_regno, this_regno, delta); | |
1679 | } | |
1680 | else if (satisfies_constraint_Is20 (GEN_INT (delta))) | |
1681 | { | |
1682 | fprintf (file, "\tmovi\t$ta, %ld\n", delta); | |
1683 | fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); | |
1684 | } | |
1685 | else | |
1686 | { | |
1687 | fprintf (file, "\tsethi\t$ta, hi20(%ld)\n", delta); | |
1688 | fprintf (file, "\tori\t$ta, $ta, lo12(%ld)\n", delta); | |
1689 | fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | fprintf (file, "\tb\t"); | |
1694 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
1695 | fprintf (file, "\n"); | |
1696 | ||
1697 | final_end_function (); | |
1698 | } | |
1699 | ||
1700 | /* -- Permitting tail calls. */ | |
1701 | ||
1702 | /* Determine whether we need to enable warning for function return check. */ | |
1703 | static bool | |
1704 | nds32_warn_func_return (tree decl) | |
1705 | { | |
8a498f99 CJW |
1706 | /* Naked functions are implemented entirely in assembly, including the |
1707 | return sequence, so suppress warnings about this. */ | |
9304f876 CJW |
1708 | return !nds32_naked_function_p (decl); |
1709 | } | |
1710 | ||
1711 | \f | |
1712 | /* Implementing the Varargs Macros. */ | |
1713 | ||
d4a6a4d9 CJW |
1714 | static void |
1715 | nds32_setup_incoming_varargs (cumulative_args_t ca, | |
ef4bddc2 | 1716 | machine_mode mode, |
d4a6a4d9 CJW |
1717 | tree type, |
1718 | int *pretend_args_size, | |
1719 | int second_time ATTRIBUTE_UNUSED) | |
1720 | { | |
1721 | unsigned int total_args_regs; | |
1722 | unsigned int num_of_used_regs; | |
1723 | unsigned int remaining_reg_count; | |
1724 | CUMULATIVE_ARGS *cum; | |
1725 | ||
1726 | /* If we are under hard float abi, we do not need to set *pretend_args_size. | |
1727 | So that all nameless arguments are pushed by caller and all situation | |
1728 | can be handled by GCC itself. */ | |
1729 | if (TARGET_HARD_FLOAT) | |
1730 | return; | |
1731 | ||
1732 | /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers, | |
1733 | counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments. | |
1734 | However, for nameless(anonymous) arguments, we should push them on the | |
1735 | stack so that all the nameless arguments appear to have been passed | |
1736 | consecutively in the memory for accessing. Hence, we need to check and | |
1737 | exclude the registers that are used for named arguments. */ | |
1738 | ||
1739 | cum = get_cumulative_args (ca); | |
1740 | ||
1741 | /* The MODE and TYPE describe the last argument. | |
1742 | We need those information to determine the remaining registers | |
1743 | for varargs. */ | |
1744 | total_args_regs | |
1745 | = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM; | |
1746 | num_of_used_regs | |
1747 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
1748 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
1749 | ||
1750 | remaining_reg_count = total_args_regs - num_of_used_regs; | |
1751 | *pretend_args_size = remaining_reg_count * UNITS_PER_WORD; | |
1752 | ||
1753 | return; | |
1754 | } | |
1755 | ||
9304f876 CJW |
1756 | static bool |
1757 | nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) | |
1758 | { | |
d4a6a4d9 CJW |
1759 | /* If this hook returns true, the named argument of FUNCTION_ARG is always |
1760 | true for named arguments, and false for unnamed arguments. */ | |
9304f876 CJW |
1761 | return true; |
1762 | } | |
1763 | ||
1764 | \f | |
1765 | /* Trampolines for Nested Functions. */ | |
1766 | ||
1767 | static void | |
1768 | nds32_asm_trampoline_template (FILE *f) | |
1769 | { | |
1770 | if (TARGET_REDUCED_REGS) | |
1771 | { | |
1772 | /* Trampoline is not supported on reduced-set registers yet. */ | |
1773 | sorry ("a nested function is not supported for reduced registers"); | |
1774 | } | |
1775 | else | |
1776 | { | |
1777 | asm_fprintf (f, "\t! Trampoline code template\n"); | |
1778 | asm_fprintf (f, "\t! This code fragment will be copied " | |
1779 | "into stack on demand\n"); | |
1780 | ||
1781 | asm_fprintf (f, "\tmfusr\t$r16,$pc\n"); | |
1782 | asm_fprintf (f, "\tlwi\t$r15,[$r16 + 20] " | |
1783 | "! load nested function address\n"); | |
1784 | asm_fprintf (f, "\tlwi\t$r16,[$r16 + 16] " | |
1785 | "! load chain_value\n"); | |
1786 | asm_fprintf (f, "\tjr\t$r15\n"); | |
1787 | } | |
1788 | ||
1789 | /* Preserve space ($pc + 16) for saving chain_value, | |
1790 | nds32_trampoline_init will fill the value in this slot. */ | |
1791 | asm_fprintf (f, "\t! space for saving chain_value\n"); | |
1792 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
1793 | ||
1794 | /* Preserve space ($pc + 20) for saving nested function address, | |
1795 | nds32_trampoline_init will fill the value in this slot. */ | |
1796 | asm_fprintf (f, "\t! space for saving nested function address\n"); | |
1797 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
1798 | } | |
1799 | ||
1800 | /* Emit RTL insns to initialize the variable parts of a trampoline. */ | |
1801 | static void | |
1802 | nds32_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
1803 | { | |
1804 | int i; | |
1805 | ||
1806 | /* Nested function address. */ | |
1807 | rtx fnaddr; | |
1808 | /* The memory rtx that is going to | |
1809 | be filled with chain_value. */ | |
1810 | rtx chain_value_mem; | |
1811 | /* The memory rtx that is going to | |
1812 | be filled with nested function address. */ | |
1813 | rtx nested_func_mem; | |
1814 | ||
1815 | /* Start address of trampoline code in stack, for doing cache sync. */ | |
1816 | rtx sync_cache_addr; | |
1817 | /* Temporary register for sync instruction. */ | |
1818 | rtx tmp_reg; | |
1819 | /* Instruction-cache sync instruction, | |
1820 | requesting an argument as starting address. */ | |
1821 | rtx isync_insn; | |
1822 | /* For convenience reason of doing comparison. */ | |
1823 | int tramp_align_in_bytes; | |
1824 | ||
1825 | /* Trampoline is not supported on reduced-set registers yet. */ | |
1826 | if (TARGET_REDUCED_REGS) | |
1827 | sorry ("a nested function is not supported for reduced registers"); | |
1828 | ||
1829 | /* STEP 1: Copy trampoline code template into stack, | |
8a498f99 | 1830 | fill up essential data into stack. */ |
9304f876 CJW |
1831 | |
1832 | /* Extract nested function address rtx. */ | |
1833 | fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
1834 | ||
1835 | /* m_tramp is memory rtx that is going to be filled with trampoline code. | |
1836 | We have nds32_asm_trampoline_template() to emit template pattern. */ | |
1837 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
1838 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
1839 | ||
1840 | /* After copying trampoline code into stack, | |
1841 | fill chain_value into stack. */ | |
1842 | chain_value_mem = adjust_address (m_tramp, SImode, 16); | |
1843 | emit_move_insn (chain_value_mem, chain_value); | |
1844 | /* After copying trampoline code int stack, | |
1845 | fill nested function address into stack. */ | |
1846 | nested_func_mem = adjust_address (m_tramp, SImode, 20); | |
1847 | emit_move_insn (nested_func_mem, fnaddr); | |
1848 | ||
1849 | /* STEP 2: Sync instruction-cache. */ | |
1850 | ||
1851 | /* We have successfully filled trampoline code into stack. | |
1852 | However, in order to execute code in stack correctly, | |
1853 | we must sync instruction cache. */ | |
1854 | sync_cache_addr = XEXP (m_tramp, 0); | |
1855 | tmp_reg = gen_reg_rtx (SImode); | |
1856 | isync_insn = gen_unspec_volatile_isync (tmp_reg); | |
1857 | ||
1858 | /* Because nds32_cache_block_size is in bytes, | |
1859 | we get trampoline alignment in bytes for convenient comparison. */ | |
1860 | tramp_align_in_bytes = TRAMPOLINE_ALIGNMENT / BITS_PER_UNIT; | |
1861 | ||
1862 | if (tramp_align_in_bytes >= nds32_cache_block_size | |
1863 | && (tramp_align_in_bytes % nds32_cache_block_size) == 0) | |
1864 | { | |
1865 | /* Under this condition, the starting address of trampoline | |
8a498f99 CJW |
1866 | must be aligned to the starting address of each cache block |
1867 | and we do not have to worry about cross-boundary issue. */ | |
9304f876 CJW |
1868 | for (i = 0; |
1869 | i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) | |
1870 | / nds32_cache_block_size; | |
1871 | i++) | |
1872 | { | |
1873 | emit_move_insn (tmp_reg, | |
1874 | plus_constant (Pmode, sync_cache_addr, | |
1875 | nds32_cache_block_size * i)); | |
1876 | emit_insn (isync_insn); | |
1877 | } | |
1878 | } | |
1879 | else if (TRAMPOLINE_SIZE > nds32_cache_block_size) | |
1880 | { | |
1881 | /* The starting address of trampoline code | |
8a498f99 CJW |
1882 | may not be aligned to the cache block, |
1883 | so the trampoline code may be across two cache block. | |
1884 | We need to sync the last element, which is 4-byte size, | |
1885 | of trampoline template. */ | |
9304f876 CJW |
1886 | for (i = 0; |
1887 | i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) | |
1888 | / nds32_cache_block_size; | |
1889 | i++) | |
1890 | { | |
1891 | emit_move_insn (tmp_reg, | |
1892 | plus_constant (Pmode, sync_cache_addr, | |
1893 | nds32_cache_block_size * i)); | |
1894 | emit_insn (isync_insn); | |
1895 | } | |
1896 | ||
1897 | /* The last element of trampoline template is 4-byte size. */ | |
1898 | emit_move_insn (tmp_reg, | |
1899 | plus_constant (Pmode, sync_cache_addr, | |
1900 | TRAMPOLINE_SIZE - 4)); | |
1901 | emit_insn (isync_insn); | |
1902 | } | |
1903 | else | |
1904 | { | |
1905 | /* This is the simplest case. | |
8a498f99 CJW |
1906 | Because TRAMPOLINE_SIZE is less than or |
1907 | equal to nds32_cache_block_size, | |
1908 | we can just sync start address and | |
1909 | the last element of trampoline code. */ | |
9304f876 CJW |
1910 | |
1911 | /* Sync starting address of tampoline code. */ | |
1912 | emit_move_insn (tmp_reg, sync_cache_addr); | |
1913 | emit_insn (isync_insn); | |
1914 | /* Sync the last element, which is 4-byte size, | |
8a498f99 | 1915 | of trampoline template. */ |
9304f876 CJW |
1916 | emit_move_insn (tmp_reg, |
1917 | plus_constant (Pmode, sync_cache_addr, | |
1918 | TRAMPOLINE_SIZE - 4)); | |
1919 | emit_insn (isync_insn); | |
1920 | } | |
1921 | ||
1922 | /* Set instruction serialization barrier | |
1923 | to guarantee the correct operations. */ | |
1924 | emit_insn (gen_unspec_volatile_isb ()); | |
1925 | } | |
1926 | ||
1927 | \f | |
1928 | /* Addressing Modes. */ | |
1929 | ||
1930 | static bool | |
ef4bddc2 | 1931 | nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict) |
9304f876 CJW |
1932 | { |
1933 | /* For (mem:DI addr) or (mem:DF addr) case, | |
1934 | we only allow 'addr' to be [reg], [symbol_ref], | |
8a498f99 | 1935 | [const], or [reg + const_int] pattern. */ |
9304f876 CJW |
1936 | if (mode == DImode || mode == DFmode) |
1937 | { | |
1938 | /* Allow [Reg + const_int] addressing mode. */ | |
1939 | if (GET_CODE (x) == PLUS) | |
1940 | { | |
1941 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict) | |
1942 | && nds32_legitimate_index_p (mode, XEXP (x, 1), strict) | |
1943 | && CONST_INT_P (XEXP (x, 1))) | |
1944 | return true; | |
9304f876 CJW |
1945 | else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) |
1946 | && nds32_legitimate_index_p (mode, XEXP (x, 0), strict) | |
1947 | && CONST_INT_P (XEXP (x, 0))) | |
1948 | return true; | |
1949 | } | |
1950 | ||
1951 | /* Now check [reg], [symbol_ref], and [const]. */ | |
1952 | if (GET_CODE (x) != REG | |
1953 | && GET_CODE (x) != SYMBOL_REF | |
1954 | && GET_CODE (x) != CONST) | |
1955 | return false; | |
1956 | } | |
1957 | ||
1958 | /* Check if 'x' is a valid address. */ | |
1959 | switch (GET_CODE (x)) | |
1960 | { | |
1961 | case REG: | |
1962 | /* (mem (reg A)) => [Ra] */ | |
1963 | return nds32_address_register_rtx_p (x, strict); | |
1964 | ||
1965 | case SYMBOL_REF: | |
4855be84 CJW |
1966 | /* (mem (symbol_ref A)) => [symbol_ref] */ |
1967 | /* If -mcmodel=large, the 'symbol_ref' is not a valid address | |
8a498f99 | 1968 | during or after LRA/reload phase. */ |
4855be84 | 1969 | if (TARGET_CMODEL_LARGE |
9304f876 CJW |
1970 | && (reload_completed |
1971 | || reload_in_progress | |
1972 | || lra_in_progress)) | |
1973 | return false; | |
4855be84 | 1974 | /* If -mcmodel=medium and the symbol references to rodata section, |
8a498f99 CJW |
1975 | the 'symbol_ref' is not a valid address during or after |
1976 | LRA/reload phase. */ | |
4855be84 CJW |
1977 | if (TARGET_CMODEL_MEDIUM |
1978 | && NDS32_SYMBOL_REF_RODATA_P (x) | |
9304f876 CJW |
1979 | && (reload_completed |
1980 | || reload_in_progress | |
1981 | || lra_in_progress)) | |
1982 | return false; | |
1983 | ||
4855be84 CJW |
1984 | return true; |
1985 | ||
1986 | case CONST: | |
9304f876 | 1987 | /* (mem (const (...))) |
8a498f99 | 1988 | => [ + const_addr ], where const_addr = symbol_ref + const_int */ |
9304f876 CJW |
1989 | if (GET_CODE (XEXP (x, 0)) == PLUS) |
1990 | { | |
1991 | rtx plus_op = XEXP (x, 0); | |
1992 | ||
1993 | rtx op0 = XEXP (plus_op, 0); | |
1994 | rtx op1 = XEXP (plus_op, 1); | |
1995 | ||
1996 | if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) | |
4855be84 CJW |
1997 | { |
1998 | /* Now we see the [ + const_addr ] pattern, but we need | |
8a498f99 | 1999 | some further checking. */ |
4855be84 | 2000 | /* If -mcmodel=large, the 'const_addr' is not a valid address |
8a498f99 | 2001 | during or after LRA/reload phase. */ |
4855be84 CJW |
2002 | if (TARGET_CMODEL_LARGE |
2003 | && (reload_completed | |
2004 | || reload_in_progress | |
2005 | || lra_in_progress)) | |
2006 | return false; | |
2007 | /* If -mcmodel=medium and the symbol references to rodata section, | |
8a498f99 CJW |
2008 | the 'const_addr' is not a valid address during or after |
2009 | LRA/reload phase. */ | |
4855be84 CJW |
2010 | if (TARGET_CMODEL_MEDIUM |
2011 | && NDS32_SYMBOL_REF_RODATA_P (op0) | |
2012 | && (reload_completed | |
2013 | || reload_in_progress | |
2014 | || lra_in_progress)) | |
2015 | return false; | |
2016 | ||
2017 | /* At this point we can make sure 'const_addr' is a | |
2018 | valid address. */ | |
2019 | return true; | |
2020 | } | |
9304f876 CJW |
2021 | } |
2022 | ||
2023 | return false; | |
2024 | ||
2025 | case POST_MODIFY: | |
2026 | /* (mem (post_modify (reg) (plus (reg) (reg)))) | |
8a498f99 | 2027 | => [Ra], Rb */ |
9304f876 | 2028 | /* (mem (post_modify (reg) (plus (reg) (const_int)))) |
8a498f99 | 2029 | => [Ra], const_int */ |
9304f876 CJW |
2030 | if (GET_CODE (XEXP (x, 0)) == REG |
2031 | && GET_CODE (XEXP (x, 1)) == PLUS) | |
2032 | { | |
2033 | rtx plus_op = XEXP (x, 1); | |
2034 | ||
2035 | rtx op0 = XEXP (plus_op, 0); | |
2036 | rtx op1 = XEXP (plus_op, 1); | |
2037 | ||
2038 | if (nds32_address_register_rtx_p (op0, strict) | |
2039 | && nds32_legitimate_index_p (mode, op1, strict)) | |
2040 | return true; | |
2041 | else | |
2042 | return false; | |
2043 | } | |
2044 | ||
2045 | return false; | |
2046 | ||
2047 | case POST_INC: | |
2048 | case POST_DEC: | |
2049 | /* (mem (post_inc reg)) => [Ra], 1/2/4 */ | |
2050 | /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */ | |
2051 | /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. | |
8a498f99 | 2052 | We only need to deal with register Ra. */ |
9304f876 CJW |
2053 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) |
2054 | return true; | |
2055 | else | |
2056 | return false; | |
2057 | ||
2058 | case PLUS: | |
2059 | /* (mem (plus reg const_int)) | |
8a498f99 | 2060 | => [Ra + imm] */ |
9304f876 | 2061 | /* (mem (plus reg reg)) |
8a498f99 | 2062 | => [Ra + Rb] */ |
9304f876 | 2063 | /* (mem (plus (mult reg const_int) reg)) |
8a498f99 | 2064 | => [Ra + Rb << sv] */ |
9304f876 CJW |
2065 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict) |
2066 | && nds32_legitimate_index_p (mode, XEXP (x, 1), strict)) | |
2067 | return true; | |
2068 | else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) | |
2069 | && nds32_legitimate_index_p (mode, XEXP (x, 0), strict)) | |
2070 | return true; | |
2071 | else | |
2072 | return false; | |
2073 | ||
2074 | case LO_SUM: | |
34425025 CJW |
2075 | /* (mem (lo_sum (reg) (symbol_ref))) */ |
2076 | /* (mem (lo_sum (reg) (const))) */ | |
2077 | gcc_assert (REG_P (XEXP (x, 0))); | |
2078 | if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF | |
2079 | || GET_CODE (XEXP (x, 1)) == CONST) | |
2080 | return nds32_legitimate_address_p (mode, XEXP (x, 1), strict); | |
2081 | else | |
2082 | return false; | |
9304f876 CJW |
2083 | |
2084 | default: | |
2085 | return false; | |
2086 | } | |
2087 | } | |
2088 | ||
2089 | \f | |
2090 | /* Describing Relative Costs of Operations. */ | |
2091 | ||
19ac960a | 2092 | static int |
ef4bddc2 | 2093 | nds32_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
19ac960a CJW |
2094 | reg_class_t from, |
2095 | reg_class_t to) | |
9304f876 CJW |
2096 | { |
2097 | if (from == HIGH_REGS || to == HIGH_REGS) | |
2098 | return 6; | |
2099 | ||
2100 | return 2; | |
2101 | } | |
2102 | ||
19ac960a | 2103 | static int |
ef4bddc2 | 2104 | nds32_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
19ac960a CJW |
2105 | reg_class_t rclass ATTRIBUTE_UNUSED, |
2106 | bool in ATTRIBUTE_UNUSED) | |
9304f876 CJW |
2107 | { |
2108 | return 8; | |
2109 | } | |
2110 | ||
2111 | /* This target hook describes the relative costs of RTL expressions. | |
2112 | Return 'true' when all subexpressions of x have been processed. | |
2113 | Return 'false' to sum the costs of sub-rtx, plus cost of this operation. | |
2114 | Refer to gcc/rtlanal.c for more information. */ | |
2115 | static bool | |
2116 | nds32_rtx_costs (rtx x, | |
e548c9df | 2117 | machine_mode mode, |
9304f876 | 2118 | int outer_code, |
89a4b547 | 2119 | int opno, |
9304f876 CJW |
2120 | int *total, |
2121 | bool speed) | |
2122 | { | |
e548c9df | 2123 | return nds32_rtx_costs_impl (x, mode, outer_code, opno, total, speed); |
9304f876 CJW |
2124 | } |
2125 | ||
19ac960a CJW |
2126 | static int |
2127 | nds32_address_cost (rtx address, | |
ef4bddc2 | 2128 | machine_mode mode, |
19ac960a CJW |
2129 | addr_space_t as, |
2130 | bool speed) | |
9304f876 | 2131 | { |
89a4b547 | 2132 | return nds32_address_cost_impl (address, mode, as, speed); |
9304f876 CJW |
2133 | } |
2134 | ||
511a41d7 CJW |
2135 | \f |
2136 | /* Dividing the Output into Sections (Texts, Data, . . . ). */ | |
2137 | ||
2138 | /* If references to a symbol or a constant must be treated differently | |
2139 | depending on something about the variable or function named by the symbol | |
2140 | (such as what section it is in), we use this hook to store flags | |
2141 | in symbol_ref rtx. */ | |
2142 | static void | |
2143 | nds32_encode_section_info (tree decl, rtx rtl, int new_decl_p) | |
2144 | { | |
2145 | default_encode_section_info (decl, rtl, new_decl_p); | |
2146 | ||
2147 | /* For the memory rtx, if it references to rodata section, we can store | |
2148 | NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the | |
2149 | nds32_legitimate_address_p() can determine how to treat such symbol_ref | |
2150 | based on -mcmodel=X and this information. */ | |
2151 | if (MEM_P (rtl) && MEM_READONLY_P (rtl)) | |
2152 | { | |
2153 | rtx addr = XEXP (rtl, 0); | |
2154 | ||
2155 | if (GET_CODE (addr) == SYMBOL_REF) | |
2156 | { | |
2157 | /* For (mem (symbol_ref X)) case. */ | |
2158 | SYMBOL_REF_FLAGS (addr) |= NDS32_SYMBOL_FLAG_RODATA; | |
2159 | } | |
2160 | else if (GET_CODE (addr) == CONST | |
2161 | && GET_CODE (XEXP (addr, 0)) == PLUS) | |
2162 | { | |
2163 | /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */ | |
2164 | rtx plus_op = XEXP (addr, 0); | |
2165 | rtx op0 = XEXP (plus_op, 0); | |
2166 | rtx op1 = XEXP (plus_op, 1); | |
2167 | ||
2168 | if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) | |
2169 | SYMBOL_REF_FLAGS (op0) |= NDS32_SYMBOL_FLAG_RODATA; | |
2170 | } | |
2171 | } | |
2172 | } | |
2173 | ||
9304f876 CJW |
2174 | \f |
2175 | /* Defining the Output Assembler Language. */ | |
2176 | ||
2177 | /* -- The Overall Framework of an Assembler File. */ | |
2178 | ||
2179 | static void | |
2180 | nds32_asm_file_start (void) | |
2181 | { | |
9304f876 CJW |
2182 | default_file_start (); |
2183 | ||
2184 | /* Tell assembler which ABI we are using. */ | |
2185 | fprintf (asm_out_file, "\t! ABI version\n"); | |
2186 | fprintf (asm_out_file, "\t.abi_2\n"); | |
2187 | ||
2188 | /* Tell assembler that this asm code is generated by compiler. */ | |
2189 | fprintf (asm_out_file, "\t! This asm file is generated by compiler\n"); | |
2190 | fprintf (asm_out_file, "\t.flag\tverbatim\n"); | |
2191 | /* Give assembler the size of each vector for interrupt handler. */ | |
2192 | fprintf (asm_out_file, "\t! This vector size directive is required " | |
2193 | "for checking inconsistency on interrupt handler\n"); | |
2194 | fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size); | |
2195 | ||
9304f876 CJW |
2196 | fprintf (asm_out_file, "\t! ------------------------------------\n"); |
2197 | ||
2198 | if (TARGET_ISA_V2) | |
2199 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V2"); | |
2200 | if (TARGET_ISA_V3) | |
2201 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3"); | |
2202 | if (TARGET_ISA_V3M) | |
2203 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M"); | |
2204 | ||
77b7a1ca CJW |
2205 | if (TARGET_CMODEL_SMALL) |
2206 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "SMALL"); | |
2207 | if (TARGET_CMODEL_MEDIUM) | |
2208 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "MEDIUM"); | |
2209 | if (TARGET_CMODEL_LARGE) | |
2210 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "LARGE"); | |
2211 | ||
9304f876 CJW |
2212 | fprintf (asm_out_file, "\t! Endian setting\t: %s\n", |
2213 | ((TARGET_BIG_ENDIAN) ? "big-endian" | |
2214 | : "little-endian")); | |
2215 | ||
2216 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2217 | ||
2218 | fprintf (asm_out_file, "\t! Use conditional move\t\t: %s\n", | |
2219 | ((TARGET_CMOV) ? "Yes" | |
2220 | : "No")); | |
2221 | fprintf (asm_out_file, "\t! Use performance extension\t: %s\n", | |
aa4b851c | 2222 | ((TARGET_EXT_PERF) ? "Yes" |
9304f876 | 2223 | : "No")); |
aa4b851c CJW |
2224 | fprintf (asm_out_file, "\t! Use performance extension 2\t: %s\n", |
2225 | ((TARGET_EXT_PERF2) ? "Yes" | |
2226 | : "No")); | |
2227 | fprintf (asm_out_file, "\t! Use string extension\t\t: %s\n", | |
2228 | ((TARGET_EXT_STRING) ? "Yes" | |
2229 | : "No")); | |
9304f876 CJW |
2230 | |
2231 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2232 | ||
2233 | fprintf (asm_out_file, "\t! V3PUSH instructions\t: %s\n", | |
2234 | ((TARGET_V3PUSH) ? "Yes" | |
2235 | : "No")); | |
2236 | fprintf (asm_out_file, "\t! 16-bit instructions\t: %s\n", | |
2237 | ((TARGET_16_BIT) ? "Yes" | |
2238 | : "No")); | |
9304f876 CJW |
2239 | fprintf (asm_out_file, "\t! Reduced registers set\t: %s\n", |
2240 | ((TARGET_REDUCED_REGS) ? "Yes" | |
2241 | : "No")); | |
2242 | ||
2243 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2244 | ||
2245 | if (optimize_size) | |
2246 | fprintf (asm_out_file, "\t! Optimization level\t: -Os\n"); | |
2247 | else | |
2248 | fprintf (asm_out_file, "\t! Optimization level\t: -O%d\n", optimize); | |
2249 | ||
2250 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2251 | ||
2252 | fprintf (asm_out_file, "\t! Cache block size\t: %d\n", | |
2253 | nds32_cache_block_size); | |
2254 | ||
2255 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2256 | ||
c23a919b | 2257 | nds32_asm_file_start_for_isr (); |
9304f876 CJW |
2258 | } |
2259 | ||
2260 | static void | |
2261 | nds32_asm_file_end (void) | |
2262 | { | |
c23a919b | 2263 | nds32_asm_file_end_for_isr (); |
9304f876 CJW |
2264 | |
2265 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2266 | } | |
2267 | ||
2268 | /* -- Output and Generation of Labels. */ | |
2269 | ||
2270 | static void | |
2271 | nds32_asm_globalize_label (FILE *stream, const char *name) | |
2272 | { | |
2273 | fputs ("\t.global\t", stream); | |
2274 | assemble_name (stream, name); | |
2275 | fputs ("\n", stream); | |
2276 | } | |
2277 | ||
2278 | /* -- Output of Assembler Instructions. */ | |
2279 | ||
2280 | static void | |
2281 | nds32_print_operand (FILE *stream, rtx x, int code) | |
2282 | { | |
2283 | int op_value; | |
2284 | ||
2285 | switch (code) | |
2286 | { | |
2287 | case 0 : | |
2288 | /* Do nothing special. */ | |
2289 | break; | |
2290 | ||
2291 | case 'V': | |
2292 | /* 'x' is supposed to be CONST_INT, get the value. */ | |
2293 | gcc_assert (CONST_INT_P (x)); | |
2294 | op_value = INTVAL (x); | |
2295 | ||
2296 | /* According to the Andes architecture, | |
8a498f99 CJW |
2297 | the system/user register index range is 0 ~ 1023. |
2298 | In order to avoid conflict between user-specified-integer value | |
2299 | and enum-specified-register value, | |
2300 | the 'enum nds32_intrinsic_registers' value | |
2301 | in nds32_intrinsic.h starts from 1024. */ | |
9304f876 CJW |
2302 | if (op_value < 1024 && op_value >= 0) |
2303 | { | |
2304 | /* If user gives integer value directly (0~1023), | |
2305 | we just print out the value. */ | |
2306 | fprintf (stream, "%d", op_value); | |
2307 | } | |
2308 | else if (op_value < 0 | |
2309 | || op_value >= ((int) ARRAY_SIZE (nds32_intrinsic_register_names) | |
2310 | + 1024)) | |
2311 | { | |
2312 | /* The enum index value for array size is out of range. */ | |
2313 | error ("intrinsic register index is out of range"); | |
2314 | } | |
2315 | else | |
2316 | { | |
2317 | /* If user applies normal way with __NDS32_REG_XXX__ enum data, | |
2318 | we can print out register name. Remember to substract 1024. */ | |
2319 | fprintf (stream, "%s", | |
2320 | nds32_intrinsic_register_names[op_value - 1024]); | |
2321 | } | |
2322 | ||
2323 | /* No need to handle following process, so return immediately. */ | |
2324 | return; | |
2325 | ||
2326 | default : | |
2327 | /* Unknown flag. */ | |
2328 | output_operand_lossage ("invalid operand output code"); | |
2329 | break; | |
2330 | } | |
2331 | ||
2332 | switch (GET_CODE (x)) | |
2333 | { | |
2334 | case LABEL_REF: | |
2335 | case SYMBOL_REF: | |
2336 | output_addr_const (stream, x); | |
2337 | break; | |
2338 | ||
2339 | case REG: | |
2340 | /* Forbid using static chain register ($r16) | |
8a498f99 | 2341 | on reduced-set registers configuration. */ |
9304f876 CJW |
2342 | if (TARGET_REDUCED_REGS |
2343 | && REGNO (x) == STATIC_CHAIN_REGNUM) | |
2344 | sorry ("a nested function is not supported for reduced registers"); | |
2345 | ||
2346 | /* Normal cases, print out register name. */ | |
2347 | fputs (reg_names[REGNO (x)], stream); | |
2348 | break; | |
2349 | ||
2350 | case MEM: | |
cc8ca59e | 2351 | output_address (GET_MODE (x), XEXP (x, 0)); |
9304f876 CJW |
2352 | break; |
2353 | ||
2354 | case CODE_LABEL: | |
2355 | case CONST_INT: | |
2356 | case CONST: | |
2357 | output_addr_const (stream, x); | |
2358 | break; | |
2359 | ||
2360 | default: | |
2361 | /* Generally, output_addr_const () is able to handle most cases. | |
8a498f99 CJW |
2362 | We want to see what CODE could appear, |
2363 | so we use gcc_unreachable() to stop it. */ | |
9304f876 CJW |
2364 | debug_rtx (x); |
2365 | gcc_unreachable (); | |
2366 | break; | |
2367 | } | |
2368 | } | |
2369 | ||
2370 | static void | |
cc8ca59e | 2371 | nds32_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x) |
9304f876 CJW |
2372 | { |
2373 | rtx op0, op1; | |
2374 | ||
2375 | switch (GET_CODE (x)) | |
2376 | { | |
2377 | case SYMBOL_REF: | |
2378 | case CONST: | |
2379 | /* [ + symbol_ref] */ | |
2380 | /* [ + const_addr], where const_addr = symbol_ref + const_int */ | |
2381 | fputs ("[ + ", stream); | |
2382 | output_addr_const (stream, x); | |
2383 | fputs ("]", stream); | |
2384 | break; | |
2385 | ||
2386 | case REG: | |
2387 | /* Forbid using static chain register ($r16) | |
8a498f99 | 2388 | on reduced-set registers configuration. */ |
9304f876 CJW |
2389 | if (TARGET_REDUCED_REGS |
2390 | && REGNO (x) == STATIC_CHAIN_REGNUM) | |
2391 | sorry ("a nested function is not supported for reduced registers"); | |
2392 | ||
2393 | /* [Ra] */ | |
2394 | fprintf (stream, "[%s]", reg_names[REGNO (x)]); | |
2395 | break; | |
2396 | ||
2397 | case PLUS: | |
2398 | op0 = XEXP (x, 0); | |
2399 | op1 = XEXP (x, 1); | |
2400 | ||
2401 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 2402 | on reduced-set registers configuration. */ |
9304f876 CJW |
2403 | if (TARGET_REDUCED_REGS |
2404 | && REG_P (op0) | |
2405 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
2406 | sorry ("a nested function is not supported for reduced registers"); | |
2407 | /* Checking op1, forbid using static chain register ($r16) | |
8a498f99 | 2408 | on reduced-set registers configuration. */ |
9304f876 CJW |
2409 | if (TARGET_REDUCED_REGS |
2410 | && REG_P (op1) | |
2411 | && REGNO (op1) == STATIC_CHAIN_REGNUM) | |
2412 | sorry ("a nested function is not supported for reduced registers"); | |
2413 | ||
2414 | if (REG_P (op0) && CONST_INT_P (op1)) | |
2415 | { | |
2416 | /* [Ra + imm] */ | |
2417 | fprintf (stream, "[%s + (%d)]", | |
2418 | reg_names[REGNO (op0)], (int)INTVAL (op1)); | |
2419 | } | |
2420 | else if (REG_P (op0) && REG_P (op1)) | |
2421 | { | |
2422 | /* [Ra + Rb] */ | |
2423 | fprintf (stream, "[%s + %s]", | |
2424 | reg_names[REGNO (op0)], reg_names[REGNO (op1)]); | |
2425 | } | |
2426 | else if (GET_CODE (op0) == MULT && REG_P (op1)) | |
2427 | { | |
2428 | /* [Ra + Rb << sv] | |
2429 | From observation, the pattern looks like: | |
2430 | (plus:SI (mult:SI (reg:SI 58) | |
8a498f99 CJW |
2431 | (const_int 4 [0x4])) |
2432 | (reg/f:SI 57)) */ | |
9304f876 CJW |
2433 | int sv; |
2434 | ||
2435 | /* We need to set sv to output shift value. */ | |
2436 | if (INTVAL (XEXP (op0, 1)) == 1) | |
2437 | sv = 0; | |
2438 | else if (INTVAL (XEXP (op0, 1)) == 2) | |
2439 | sv = 1; | |
2440 | else if (INTVAL (XEXP (op0, 1)) == 4) | |
2441 | sv = 2; | |
2442 | else | |
2443 | gcc_unreachable (); | |
2444 | ||
2445 | fprintf (stream, "[%s + %s << %d]", | |
2446 | reg_names[REGNO (op1)], | |
2447 | reg_names[REGNO (XEXP (op0, 0))], | |
2448 | sv); | |
2449 | } | |
2450 | else | |
2451 | { | |
2452 | /* The control flow is not supposed to be here. */ | |
2453 | debug_rtx (x); | |
2454 | gcc_unreachable (); | |
2455 | } | |
2456 | ||
2457 | break; | |
2458 | ||
2459 | case POST_MODIFY: | |
2460 | /* (post_modify (regA) (plus (regA) (regB))) | |
8a498f99 CJW |
2461 | (post_modify (regA) (plus (regA) (const_int))) |
2462 | We would like to extract | |
2463 | regA and regB (or const_int) from plus rtx. */ | |
9304f876 CJW |
2464 | op0 = XEXP (XEXP (x, 1), 0); |
2465 | op1 = XEXP (XEXP (x, 1), 1); | |
2466 | ||
2467 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 2468 | on reduced-set registers configuration. */ |
9304f876 CJW |
2469 | if (TARGET_REDUCED_REGS |
2470 | && REG_P (op0) | |
2471 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
2472 | sorry ("a nested function is not supported for reduced registers"); | |
2473 | /* Checking op1, forbid using static chain register ($r16) | |
8a498f99 | 2474 | on reduced-set registers configuration. */ |
9304f876 CJW |
2475 | if (TARGET_REDUCED_REGS |
2476 | && REG_P (op1) | |
2477 | && REGNO (op1) == STATIC_CHAIN_REGNUM) | |
2478 | sorry ("a nested function is not supported for reduced registers"); | |
2479 | ||
2480 | if (REG_P (op0) && REG_P (op1)) | |
2481 | { | |
2482 | /* [Ra], Rb */ | |
2483 | fprintf (stream, "[%s], %s", | |
2484 | reg_names[REGNO (op0)], reg_names[REGNO (op1)]); | |
2485 | } | |
2486 | else if (REG_P (op0) && CONST_INT_P (op1)) | |
2487 | { | |
2488 | /* [Ra], imm */ | |
2489 | fprintf (stream, "[%s], %d", | |
2490 | reg_names[REGNO (op0)], (int)INTVAL (op1)); | |
2491 | } | |
2492 | else | |
2493 | { | |
2494 | /* The control flow is not supposed to be here. */ | |
2495 | debug_rtx (x); | |
2496 | gcc_unreachable (); | |
2497 | } | |
2498 | ||
2499 | break; | |
2500 | ||
2501 | case POST_INC: | |
2502 | case POST_DEC: | |
2503 | op0 = XEXP (x, 0); | |
2504 | ||
2505 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 2506 | on reduced-set registers configuration. */ |
9304f876 CJW |
2507 | if (TARGET_REDUCED_REGS |
2508 | && REG_P (op0) | |
2509 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
2510 | sorry ("a nested function is not supported for reduced registers"); | |
2511 | ||
2512 | if (REG_P (op0)) | |
2513 | { | |
2514 | /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4" | |
2515 | The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. | |
2516 | We only need to deal with register Ra. */ | |
2517 | fprintf (stream, "[%s]", reg_names[REGNO (op0)]); | |
2518 | } | |
2519 | else | |
2520 | { | |
2521 | /* The control flow is not supposed to be here. */ | |
2522 | debug_rtx (x); | |
2523 | gcc_unreachable (); | |
2524 | } | |
2525 | ||
2526 | break; | |
2527 | ||
2528 | default : | |
2529 | /* Generally, output_addr_const () is able to handle most cases. | |
8a498f99 CJW |
2530 | We want to see what CODE could appear, |
2531 | so we use gcc_unreachable() to stop it. */ | |
9304f876 CJW |
2532 | debug_rtx (x); |
2533 | gcc_unreachable (); | |
2534 | break; | |
2535 | } | |
2536 | } | |
2537 | ||
2538 | \f | |
2539 | /* Defining target-specific uses of __attribute__. */ | |
2540 | ||
2541 | /* Add some checking after merging attributes. */ | |
2542 | static tree | |
2543 | nds32_merge_decl_attributes (tree olddecl, tree newdecl) | |
2544 | { | |
2545 | tree combined_attrs; | |
2546 | ||
2547 | /* Create combined attributes. */ | |
2548 | combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl), | |
2549 | DECL_ATTRIBUTES (newdecl)); | |
2550 | ||
59043e75 | 2551 | /* Since newdecl is acutally a duplicate of olddecl, |
9304f876 CJW |
2552 | we can take olddecl for some operations. */ |
2553 | if (TREE_CODE (olddecl) == FUNCTION_DECL) | |
2554 | { | |
2555 | /* Check isr-specific attributes conflict. */ | |
2556 | nds32_check_isr_attrs_conflict (olddecl, combined_attrs); | |
2557 | } | |
2558 | ||
2559 | return combined_attrs; | |
2560 | } | |
2561 | ||
2562 | /* Add some checking when inserting attributes. */ | |
2563 | static void | |
2564 | nds32_insert_attributes (tree decl, tree *attributes) | |
2565 | { | |
2566 | /* For function declaration, we need to check isr-specific attributes: | |
2567 | 1. Call nds32_check_isr_attrs_conflict() to check any conflict. | |
2568 | 2. Check valid integer value for interrupt/exception. | |
2569 | 3. Check valid integer value for reset. | |
2570 | 4. Check valid function for nmi/warm. */ | |
2571 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2572 | { | |
2573 | tree func_attrs; | |
2574 | tree intr, excp, reset; | |
2575 | ||
2576 | /* Pick up function attributes. */ | |
2577 | func_attrs = *attributes; | |
2578 | ||
2579 | /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */ | |
2580 | nds32_check_isr_attrs_conflict (decl, func_attrs); | |
2581 | ||
2582 | /* Now we are starting to check valid id value | |
8a498f99 CJW |
2583 | for interrupt/exception/reset. |
2584 | Note that we ONLY check its validity here. | |
2585 | To construct isr vector information, it is still performed | |
2586 | by nds32_construct_isr_vectors_information(). */ | |
9304f876 CJW |
2587 | intr = lookup_attribute ("interrupt", func_attrs); |
2588 | excp = lookup_attribute ("exception", func_attrs); | |
2589 | reset = lookup_attribute ("reset", func_attrs); | |
2590 | ||
2591 | if (intr || excp) | |
2592 | { | |
2593 | /* Deal with interrupt/exception. */ | |
2594 | tree id_list; | |
2595 | unsigned int lower_bound, upper_bound; | |
2596 | ||
2597 | /* The way to handle interrupt or exception is the same, | |
2598 | we just need to take care of actual vector number. | |
2599 | For interrupt(0..63), the actual vector number is (9..72). | |
2600 | For exception(1..8), the actual vector number is (1..8). */ | |
2601 | lower_bound = (intr) ? (0) : (1); | |
2602 | upper_bound = (intr) ? (63) : (8); | |
2603 | ||
2604 | /* Prepare id list so that we can traverse id value. */ | |
2605 | id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp)); | |
2606 | ||
2607 | /* 2. Check valid integer value for interrupt/exception. */ | |
2608 | while (id_list) | |
2609 | { | |
2610 | tree id; | |
2611 | ||
2612 | /* Pick up each vector id value. */ | |
2613 | id = TREE_VALUE (id_list); | |
2614 | /* Issue error if it is not a valid integer value. */ | |
2615 | if (TREE_CODE (id) != INTEGER_CST | |
8e6cdc90 RS |
2616 | || wi::ltu_p (wi::to_wide (id), lower_bound) |
2617 | || wi::gtu_p (wi::to_wide (id), upper_bound)) | |
9304f876 CJW |
2618 | error ("invalid id value for interrupt/exception attribute"); |
2619 | ||
2620 | /* Advance to next id. */ | |
2621 | id_list = TREE_CHAIN (id_list); | |
2622 | } | |
2623 | } | |
2624 | else if (reset) | |
2625 | { | |
2626 | /* Deal with reset. */ | |
2627 | tree id_list; | |
2628 | tree id; | |
2629 | tree nmi, warm; | |
2630 | unsigned int lower_bound; | |
2631 | unsigned int upper_bound; | |
2632 | ||
2633 | /* Prepare id_list and identify id value so that | |
2634 | we can check if total number of vectors is valid. */ | |
2635 | id_list = TREE_VALUE (reset); | |
2636 | id = TREE_VALUE (id_list); | |
2637 | ||
2638 | /* The maximum numbers for user's interrupt is 64. */ | |
2639 | lower_bound = 0; | |
2640 | upper_bound = 64; | |
2641 | ||
2642 | /* 3. Check valid integer value for reset. */ | |
2643 | if (TREE_CODE (id) != INTEGER_CST | |
8e6cdc90 RS |
2644 | || wi::ltu_p (wi::to_wide (id), lower_bound) |
2645 | || wi::gtu_p (wi::to_wide (id), upper_bound)) | |
9304f876 CJW |
2646 | error ("invalid id value for reset attribute"); |
2647 | ||
2648 | /* 4. Check valid function for nmi/warm. */ | |
2649 | nmi = lookup_attribute ("nmi", func_attrs); | |
2650 | warm = lookup_attribute ("warm", func_attrs); | |
2651 | ||
2652 | if (nmi != NULL_TREE) | |
2653 | { | |
2654 | tree nmi_func_list; | |
2655 | tree nmi_func; | |
2656 | ||
2657 | nmi_func_list = TREE_VALUE (nmi); | |
2658 | nmi_func = TREE_VALUE (nmi_func_list); | |
2659 | ||
2660 | /* Issue error if it is not a valid nmi function. */ | |
2661 | if (TREE_CODE (nmi_func) != IDENTIFIER_NODE) | |
2662 | error ("invalid nmi function for reset attribute"); | |
2663 | } | |
2664 | ||
2665 | if (warm != NULL_TREE) | |
2666 | { | |
2667 | tree warm_func_list; | |
2668 | tree warm_func; | |
2669 | ||
2670 | warm_func_list = TREE_VALUE (warm); | |
2671 | warm_func = TREE_VALUE (warm_func_list); | |
2672 | ||
2673 | /* Issue error if it is not a valid warm function. */ | |
2674 | if (TREE_CODE (warm_func) != IDENTIFIER_NODE) | |
2675 | error ("invalid warm function for reset attribute"); | |
2676 | } | |
2677 | } | |
2678 | else | |
2679 | { | |
2680 | /* No interrupt, exception, or reset attribute is set. */ | |
2681 | return; | |
2682 | } | |
2683 | } | |
2684 | } | |
2685 | ||
2686 | static bool | |
2687 | nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED, | |
2688 | tree pop_target ATTRIBUTE_UNUSED) | |
2689 | { | |
2690 | /* Currently, we do not parse any pragma target by ourself, | |
2691 | so just simply return false. */ | |
2692 | return false; | |
2693 | } | |
2694 | ||
2695 | static void | |
2696 | nds32_option_override (void) | |
2697 | { | |
2698 | /* After all the command options have been parsed, | |
2699 | we shall deal with some flags for changing compiler settings. */ | |
2700 | ||
2701 | /* At first, we check if we have to strictly | |
2702 | set some flags based on ISA family. */ | |
2703 | if (TARGET_ISA_V2) | |
2704 | { | |
2705 | /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */ | |
2706 | target_flags &= ~MASK_V3PUSH; | |
2707 | } | |
2708 | if (TARGET_ISA_V3) | |
2709 | { | |
2710 | /* Under V3 ISA, currently nothing should be strictly set. */ | |
2711 | } | |
2712 | if (TARGET_ISA_V3M) | |
2713 | { | |
2714 | /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */ | |
2715 | target_flags |= MASK_REDUCED_REGS; | |
aa4b851c CJW |
2716 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */ |
2717 | target_flags &= ~MASK_EXT_PERF; | |
2718 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */ | |
2719 | target_flags &= ~MASK_EXT_PERF2; | |
2720 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */ | |
2721 | target_flags &= ~MASK_EXT_STRING; | |
9304f876 CJW |
2722 | } |
2723 | ||
2724 | /* See if we are using reduced-set registers: | |
2725 | $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31 | |
2726 | If so, we must forbid using $r11~$r14, $r16~$r27. */ | |
2727 | if (TARGET_REDUCED_REGS) | |
2728 | { | |
2729 | int r; | |
2730 | ||
2731 | /* Prevent register allocator from | |
8a498f99 | 2732 | choosing it as doing register allocation. */ |
9304f876 CJW |
2733 | for (r = 11; r <= 14; r++) |
2734 | fixed_regs[r] = call_used_regs[r] = 1; | |
2735 | for (r = 16; r <= 27; r++) | |
2736 | fixed_regs[r] = call_used_regs[r] = 1; | |
2737 | } | |
2738 | ||
9304f876 CJW |
2739 | if (!TARGET_16_BIT) |
2740 | { | |
2741 | /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */ | |
2742 | target_flags &= ~MASK_V3PUSH; | |
2743 | } | |
2744 | ||
2745 | /* Currently, we don't support PIC code generation yet. */ | |
2746 | if (flag_pic) | |
afd78f02 | 2747 | sorry ("position-independent code not supported"); |
9304f876 CJW |
2748 | } |
2749 | ||
2750 | \f | |
2751 | /* Miscellaneous Parameters. */ | |
2752 | ||
823835a9 CJW |
2753 | static rtx_insn * |
2754 | nds32_md_asm_adjust (vec<rtx> &outputs ATTRIBUTE_UNUSED, | |
2755 | vec<rtx> &inputs ATTRIBUTE_UNUSED, | |
2756 | vec<const char *> &constraints ATTRIBUTE_UNUSED, | |
2757 | vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs) | |
2758 | { | |
2759 | clobbers.safe_push (gen_rtx_REG (SImode, TA_REGNUM)); | |
2760 | SET_HARD_REG_BIT (clobbered_regs, TA_REGNUM); | |
2761 | return NULL; | |
2762 | } | |
2763 | ||
9304f876 CJW |
2764 | static void |
2765 | nds32_init_builtins (void) | |
2766 | { | |
aaa44d2d | 2767 | nds32_init_builtins_impl (); |
9304f876 CJW |
2768 | } |
2769 | ||
7a12ea32 MC |
2770 | static tree |
2771 | nds32_builtin_decl (unsigned code, bool initialize_p) | |
2772 | { | |
2773 | /* Implement in nds32-intrinsic.c. */ | |
2774 | return nds32_builtin_decl_impl (code, initialize_p); | |
2775 | } | |
2776 | ||
9304f876 CJW |
2777 | static rtx |
2778 | nds32_expand_builtin (tree exp, | |
2779 | rtx target, | |
aaa44d2d | 2780 | rtx subtarget, |
ef4bddc2 | 2781 | machine_mode mode, |
aaa44d2d | 2782 | int ignore) |
9304f876 | 2783 | { |
aaa44d2d | 2784 | return nds32_expand_builtin_impl (exp, target, subtarget, mode, ignore); |
9304f876 CJW |
2785 | } |
2786 | ||
2787 | ||
2788 | /* ------------------------------------------------------------------------ */ | |
2789 | ||
2790 | /* PART 4: Implemet extern function definitions, | |
2791 | the prototype is in nds32-protos.h. */ | |
72b7e5e1 KC |
2792 | \f |
2793 | /* Run-time Target Specification. */ | |
2794 | ||
2795 | void | |
2796 | nds32_cpu_cpp_builtins(struct cpp_reader *pfile) | |
2797 | { | |
2798 | #define builtin_define(TXT) cpp_define (pfile, TXT) | |
2799 | #define builtin_assert(TXT) cpp_assert (pfile, TXT) | |
2800 | builtin_define ("__nds32__"); | |
2801 | builtin_define ("__NDS32__"); | |
2802 | ||
2803 | if (TARGET_ISA_V2) | |
2804 | builtin_define ("__NDS32_ISA_V2__"); | |
2805 | if (TARGET_ISA_V3) | |
2806 | builtin_define ("__NDS32_ISA_V3__"); | |
2807 | if (TARGET_ISA_V3M) | |
2808 | builtin_define ("__NDS32_ISA_V3M__"); | |
2809 | ||
2810 | if (TARGET_BIG_ENDIAN) | |
2811 | builtin_define ("__NDS32_EB__"); | |
2812 | else | |
2813 | builtin_define ("__NDS32_EL__"); | |
2814 | ||
2815 | if (TARGET_REDUCED_REGS) | |
2816 | builtin_define ("__NDS32_REDUCED_REGS__"); | |
2817 | if (TARGET_CMOV) | |
2818 | builtin_define ("__NDS32_CMOV__"); | |
2819 | if (TARGET_EXT_PERF) | |
2820 | builtin_define ("__NDS32_EXT_PERF__"); | |
2821 | if (TARGET_EXT_PERF2) | |
2822 | builtin_define ("__NDS32_EXT_PERF2__"); | |
2823 | if (TARGET_EXT_STRING) | |
2824 | builtin_define ("__NDS32_EXT_STRING__"); | |
2825 | if (TARGET_16_BIT) | |
2826 | builtin_define ("__NDS32_16_BIT__"); | |
2827 | if (TARGET_GP_DIRECT) | |
2828 | builtin_define ("__NDS32_GP_DIRECT__"); | |
ff77f6e8 KC |
2829 | if (TARGET_VH) |
2830 | builtin_define ("__NDS32_VH__"); | |
72b7e5e1 KC |
2831 | |
2832 | if (TARGET_BIG_ENDIAN) | |
2833 | builtin_define ("__big_endian__"); | |
2834 | ||
2835 | builtin_assert ("cpu=nds32"); | |
2836 | builtin_assert ("machine=nds32"); | |
2837 | #undef builtin_define | |
2838 | #undef builtin_assert | |
2839 | } | |
2840 | ||
9304f876 CJW |
2841 | \f |
2842 | /* Defining Data Structures for Per-function Information. */ | |
2843 | ||
2844 | void | |
2845 | nds32_init_expanders (void) | |
2846 | { | |
2847 | /* Arrange to initialize and mark the machine per-function status. */ | |
2848 | init_machine_status = nds32_init_machine_status; | |
2849 | } | |
2850 | ||
2851 | \f | |
2852 | /* Register Usage. */ | |
2853 | ||
2854 | /* -- How Values Fit in Registers. */ | |
2855 | ||
f939c3e6 RS |
2856 | /* Implement TARGET_HARD_REGNO_MODE_OK. */ |
2857 | ||
2858 | static bool | |
2859 | nds32_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
9304f876 CJW |
2860 | { |
2861 | /* Restrict double-word quantities to even register pairs. */ | |
c43f4279 | 2862 | if (targetm.hard_regno_nregs (regno, mode) == 1 |
9304f876 | 2863 | || !((regno) & 1)) |
f939c3e6 | 2864 | return true; |
9304f876 | 2865 | |
f939c3e6 | 2866 | return false; |
9304f876 CJW |
2867 | } |
2868 | ||
f939c3e6 RS |
2869 | #undef TARGET_HARD_REGNO_MODE_OK |
2870 | #define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok | |
99e1629f RS |
2871 | |
2872 | /* Implement TARGET_MODES_TIEABLE_P. We can use general registers to | |
2873 | tie QI/HI/SI modes together. */ | |
2874 | ||
2875 | static bool | |
2876 | nds32_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
2877 | { | |
2878 | return (GET_MODE_CLASS (mode1) == MODE_INT | |
2879 | && GET_MODE_CLASS (mode2) == MODE_INT | |
2880 | && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD | |
2881 | && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD); | |
2882 | } | |
2883 | ||
2884 | #undef TARGET_MODES_TIEABLE_P | |
2885 | #define TARGET_MODES_TIEABLE_P nds32_modes_tieable_p | |
9304f876 CJW |
2886 | \f |
2887 | /* Register Classes. */ | |
2888 | ||
2889 | enum reg_class | |
2890 | nds32_regno_reg_class (int regno) | |
2891 | { | |
2892 | /* Refer to nds32.h for more register class details. */ | |
2893 | ||
2894 | if (regno >= 0 && regno <= 7) | |
2895 | return LOW_REGS; | |
2896 | else if (regno >= 8 && regno <= 11) | |
2897 | return MIDDLE_REGS; | |
2898 | else if (regno >= 12 && regno <= 14) | |
2899 | return HIGH_REGS; | |
2900 | else if (regno == 15) | |
2901 | return R15_TA_REG; | |
2902 | else if (regno >= 16 && regno <= 19) | |
2903 | return MIDDLE_REGS; | |
2904 | else if (regno >= 20 && regno <= 31) | |
2905 | return HIGH_REGS; | |
2906 | else if (regno == 32 || regno == 33) | |
2907 | return FRAME_REGS; | |
2908 | else | |
2909 | return NO_REGS; | |
2910 | } | |
2911 | ||
2912 | \f | |
2913 | /* Stack Layout and Calling Conventions. */ | |
2914 | ||
2915 | /* -- Basic Stack Layout. */ | |
2916 | ||
2917 | rtx | |
2918 | nds32_return_addr_rtx (int count, | |
2919 | rtx frameaddr ATTRIBUTE_UNUSED) | |
2920 | { | |
2921 | /* There is no way to determine the return address | |
2922 | if frameaddr is the frame that has 'count' steps | |
2923 | up from current frame. */ | |
2924 | if (count != 0) | |
2925 | return NULL_RTX; | |
2926 | ||
2927 | /* If count == 0, it means we are at current frame, | |
2928 | the return address is $r30 ($lp). */ | |
2929 | return get_hard_reg_initial_val (Pmode, LP_REGNUM); | |
2930 | } | |
2931 | ||
2932 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
2933 | ||
2934 | HOST_WIDE_INT | |
2935 | nds32_initial_elimination_offset (unsigned int from_reg, unsigned int to_reg) | |
2936 | { | |
2937 | HOST_WIDE_INT offset; | |
2938 | ||
2939 | /* Compute and setup stack frame size. | |
2940 | The result will be in cfun->machine. */ | |
2941 | nds32_compute_stack_frame (); | |
2942 | ||
2943 | /* Remember to consider | |
8a498f99 | 2944 | cfun->machine->callee_saved_area_gpr_padding_bytes |
9304f876 CJW |
2945 | when calculating offset. */ |
2946 | if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
2947 | { | |
2948 | offset = (cfun->machine->fp_size | |
8a498f99 | 2949 | + cfun->machine->gp_size |
9304f876 | 2950 | + cfun->machine->lp_size |
c457f751 CJW |
2951 | + cfun->machine->callee_saved_gpr_regs_size |
2952 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
9304f876 CJW |
2953 | + cfun->machine->local_size |
2954 | + cfun->machine->out_args_size); | |
2955 | } | |
2956 | else if (from_reg == ARG_POINTER_REGNUM | |
2957 | && to_reg == HARD_FRAME_POINTER_REGNUM) | |
2958 | { | |
2959 | offset = 0; | |
2960 | } | |
2961 | else if (from_reg == FRAME_POINTER_REGNUM | |
2962 | && to_reg == STACK_POINTER_REGNUM) | |
2963 | { | |
2964 | offset = (cfun->machine->local_size + cfun->machine->out_args_size); | |
2965 | } | |
2966 | else if (from_reg == FRAME_POINTER_REGNUM | |
2967 | && to_reg == HARD_FRAME_POINTER_REGNUM) | |
2968 | { | |
2969 | offset = (-1) * (cfun->machine->fp_size | |
2970 | + cfun->machine->gp_size | |
2971 | + cfun->machine->lp_size | |
c457f751 CJW |
2972 | + cfun->machine->callee_saved_gpr_regs_size |
2973 | + cfun->machine->callee_saved_area_gpr_padding_bytes); | |
9304f876 CJW |
2974 | } |
2975 | else | |
2976 | { | |
2977 | gcc_unreachable (); | |
2978 | } | |
2979 | ||
2980 | return offset; | |
2981 | } | |
2982 | ||
2983 | /* -- Passing Arguments in Registers. */ | |
2984 | ||
2985 | void | |
2986 | nds32_init_cumulative_args (CUMULATIVE_ARGS *cum, | |
2987 | tree fntype ATTRIBUTE_UNUSED, | |
2988 | rtx libname ATTRIBUTE_UNUSED, | |
2989 | tree fndecl ATTRIBUTE_UNUSED, | |
2990 | int n_named_args ATTRIBUTE_UNUSED) | |
2991 | { | |
2992 | /* Initial available registers | |
2993 | (in offset, corresponding to NDS32_GPR_ARG_FIRST_REGNUM) | |
2994 | for passing arguments. */ | |
9d93cc24 | 2995 | cum->gpr_offset = 0; |
9304f876 CJW |
2996 | } |
2997 | ||
2998 | /* -- Function Entry and Exit. */ | |
2999 | ||
3000 | /* Function for normal multiple push prologue. */ | |
3001 | void | |
3002 | nds32_expand_prologue (void) | |
3003 | { | |
3004 | int fp_adjust; | |
3005 | int sp_adjust; | |
a6c7e777 | 3006 | unsigned Rb, Re; |
9304f876 | 3007 | |
9304f876 CJW |
3008 | /* Compute and setup stack frame size. |
3009 | The result will be in cfun->machine. */ | |
3010 | nds32_compute_stack_frame (); | |
3011 | ||
557430f1 CJW |
3012 | /* If this is a variadic function, first we need to push argument |
3013 | registers that hold the unnamed argument value. */ | |
3014 | if (cfun->machine->va_args_size != 0) | |
3015 | { | |
a6c7e777 MC |
3016 | Rb = cfun->machine->va_args_first_regno; |
3017 | Re = cfun->machine->va_args_last_regno; | |
3018 | /* No need to push $fp, $gp, or $lp. */ | |
3019 | nds32_emit_stack_push_multiple (Rb, Re, false, false, false, true); | |
557430f1 CJW |
3020 | |
3021 | /* We may also need to adjust stack pointer for padding bytes | |
3022 | because varargs may cause $sp not 8-byte aligned. */ | |
3023 | if (cfun->machine->va_args_area_padding_bytes) | |
3024 | { | |
3025 | /* Generate sp adjustment instruction. */ | |
3026 | sp_adjust = cfun->machine->va_args_area_padding_bytes; | |
557430f1 | 3027 | |
a6c7e777 MC |
3028 | nds32_emit_adjust_frame (stack_pointer_rtx, |
3029 | stack_pointer_rtx, | |
3030 | -1 * sp_adjust); | |
557430f1 CJW |
3031 | } |
3032 | } | |
3033 | ||
9304f876 CJW |
3034 | /* If the function is 'naked', |
3035 | we do not have to generate prologue code fragment. */ | |
3036 | if (cfun->machine->naked_p) | |
3037 | return; | |
3038 | ||
3039 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
3040 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
3041 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
3042 | |
3043 | /* If $fp, $gp, $lp, and all callee-save registers are NOT required | |
3044 | to be saved, we don't have to create multiple push instruction. | |
3045 | Otherwise, a multiple push instruction is needed. */ | |
a6c7e777 MC |
3046 | if (!(Rb == SP_REGNUM && Re == SP_REGNUM |
3047 | && cfun->machine->fp_size == 0 | |
3048 | && cfun->machine->gp_size == 0 | |
3049 | && cfun->machine->lp_size == 0)) | |
9304f876 CJW |
3050 | { |
3051 | /* Create multiple push instruction rtx. */ | |
a6c7e777 MC |
3052 | nds32_emit_stack_push_multiple ( |
3053 | Rb, Re, | |
3054 | cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size, | |
3055 | false); | |
9304f876 CJW |
3056 | } |
3057 | ||
3058 | /* Check frame_pointer_needed to see | |
3059 | if we shall emit fp adjustment instruction. */ | |
3060 | if (frame_pointer_needed) | |
3061 | { | |
3062 | /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size) | |
8a498f99 CJW |
3063 | + (4 * callee-saved-registers) |
3064 | Note: No need to adjust | |
3065 | cfun->machine->callee_saved_area_gpr_padding_bytes, | |
3066 | because, at this point, stack pointer is just | |
3067 | at the position after push instruction. */ | |
9304f876 CJW |
3068 | fp_adjust = cfun->machine->fp_size |
3069 | + cfun->machine->gp_size | |
3070 | + cfun->machine->lp_size | |
c457f751 | 3071 | + cfun->machine->callee_saved_gpr_regs_size; |
7064dcad | 3072 | |
a6c7e777 MC |
3073 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, |
3074 | stack_pointer_rtx, | |
3075 | fp_adjust); | |
9304f876 CJW |
3076 | } |
3077 | ||
3078 | /* Adjust $sp = $sp - local_size - out_args_size | |
8a498f99 | 3079 | - callee_saved_area_gpr_padding_bytes. */ |
9304f876 CJW |
3080 | sp_adjust = cfun->machine->local_size |
3081 | + cfun->machine->out_args_size | |
c457f751 | 3082 | + cfun->machine->callee_saved_area_gpr_padding_bytes; |
9304f876 CJW |
3083 | /* sp_adjust value may be out of range of the addi instruction, |
3084 | create alternative add behavior with TA_REGNUM if necessary, | |
3085 | using NEGATIVE value to tell that we are decreasing address. */ | |
a6c7e777 MC |
3086 | nds32_emit_adjust_frame (stack_pointer_rtx, |
3087 | stack_pointer_rtx, | |
3088 | -1 * sp_adjust); | |
9304f876 CJW |
3089 | |
3090 | /* Prevent the instruction scheduler from | |
3091 | moving instructions across the boundary. */ | |
3092 | emit_insn (gen_blockage ()); | |
3093 | } | |
3094 | ||
3095 | /* Function for normal multiple pop epilogue. */ | |
3096 | void | |
d6529176 | 3097 | nds32_expand_epilogue (bool sibcall_p) |
9304f876 CJW |
3098 | { |
3099 | int sp_adjust; | |
a6c7e777 | 3100 | unsigned Rb, Re; |
9304f876 CJW |
3101 | |
3102 | /* Compute and setup stack frame size. | |
3103 | The result will be in cfun->machine. */ | |
3104 | nds32_compute_stack_frame (); | |
3105 | ||
3106 | /* Prevent the instruction scheduler from | |
3107 | moving instructions across the boundary. */ | |
3108 | emit_insn (gen_blockage ()); | |
3109 | ||
3110 | /* If the function is 'naked', we do not have to generate | |
557430f1 CJW |
3111 | epilogue code fragment BUT 'ret' instruction. |
3112 | However, if this function is also a variadic function, | |
3113 | we need to create adjust stack pointer before 'ret' instruction. */ | |
9304f876 CJW |
3114 | if (cfun->machine->naked_p) |
3115 | { | |
557430f1 | 3116 | /* If this is a variadic function, we do not have to restore argument |
8a498f99 CJW |
3117 | registers but need to adjust stack pointer back to previous stack |
3118 | frame location before return. */ | |
557430f1 CJW |
3119 | if (cfun->machine->va_args_size != 0) |
3120 | { | |
3121 | /* Generate sp adjustment instruction. | |
3122 | We need to consider padding bytes here. */ | |
3123 | sp_adjust = cfun->machine->va_args_size | |
3124 | + cfun->machine->va_args_area_padding_bytes; | |
a6c7e777 MC |
3125 | |
3126 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
3127 | stack_pointer_rtx, | |
3128 | sp_adjust); | |
557430f1 CJW |
3129 | } |
3130 | ||
03390cda | 3131 | /* Generate return instruction by using 'return_internal' pattern. |
8a498f99 | 3132 | Make sure this instruction is after gen_blockage(). */ |
d6529176 CJW |
3133 | if (!sibcall_p) |
3134 | emit_jump_insn (gen_return_internal ()); | |
9304f876 CJW |
3135 | return; |
3136 | } | |
3137 | ||
3138 | if (frame_pointer_needed) | |
3139 | { | |
3140 | /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) | |
8a498f99 CJW |
3141 | - (4 * callee-saved-registers) |
3142 | Note: No need to adjust | |
3143 | cfun->machine->callee_saved_area_gpr_padding_bytes, | |
3144 | because we want to adjust stack pointer | |
3145 | to the position for pop instruction. */ | |
9304f876 CJW |
3146 | sp_adjust = cfun->machine->fp_size |
3147 | + cfun->machine->gp_size | |
3148 | + cfun->machine->lp_size | |
c457f751 | 3149 | + cfun->machine->callee_saved_gpr_regs_size; |
557430f1 | 3150 | |
a6c7e777 MC |
3151 | nds32_emit_adjust_frame (stack_pointer_rtx, |
3152 | hard_frame_pointer_rtx, | |
3153 | -1 * sp_adjust); | |
9304f876 CJW |
3154 | } |
3155 | else | |
3156 | { | |
3157 | /* If frame pointer is NOT needed, | |
8a498f99 CJW |
3158 | we cannot calculate the sp adjustment from frame pointer. |
3159 | Instead, we calculate the adjustment by local_size, | |
a6c7e777 | 3160 | out_args_size, and callee_saved_area_gpr_padding_bytes. |
8a498f99 CJW |
3161 | Notice that such sp adjustment value may be out of range, |
3162 | so we have to deal with it as well. */ | |
9304f876 CJW |
3163 | |
3164 | /* Adjust $sp = $sp + local_size + out_args_size | |
a6c7e777 | 3165 | + callee_saved_area_gpr_padding_bytes. */ |
9304f876 CJW |
3166 | sp_adjust = cfun->machine->local_size |
3167 | + cfun->machine->out_args_size | |
c457f751 | 3168 | + cfun->machine->callee_saved_area_gpr_padding_bytes; |
a6c7e777 MC |
3169 | |
3170 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
3171 | stack_pointer_rtx, | |
3172 | sp_adjust); | |
9304f876 CJW |
3173 | } |
3174 | ||
3175 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
3176 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
3177 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
3178 | |
3179 | /* If $fp, $gp, $lp, and all callee-save registers are NOT required | |
3180 | to be saved, we don't have to create multiple pop instruction. | |
3181 | Otherwise, a multiple pop instruction is needed. */ | |
a6c7e777 MC |
3182 | if (!(Rb == SP_REGNUM && Re == SP_REGNUM |
3183 | && cfun->machine->fp_size == 0 | |
3184 | && cfun->machine->gp_size == 0 | |
3185 | && cfun->machine->lp_size == 0)) | |
9304f876 CJW |
3186 | { |
3187 | /* Create multiple pop instruction rtx. */ | |
a6c7e777 MC |
3188 | nds32_emit_stack_pop_multiple ( |
3189 | Rb, Re, | |
3190 | cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size); | |
9304f876 CJW |
3191 | } |
3192 | ||
557430f1 CJW |
3193 | /* If this is a variadic function, we do not have to restore argument |
3194 | registers but need to adjust stack pointer back to previous stack | |
3195 | frame location before return. */ | |
3196 | if (cfun->machine->va_args_size != 0) | |
3197 | { | |
3198 | /* Generate sp adjustment instruction. | |
8a498f99 | 3199 | We need to consider padding bytes here. */ |
557430f1 CJW |
3200 | sp_adjust = cfun->machine->va_args_size |
3201 | + cfun->machine->va_args_area_padding_bytes; | |
557430f1 | 3202 | |
a6c7e777 MC |
3203 | nds32_emit_adjust_frame (stack_pointer_rtx, |
3204 | stack_pointer_rtx, | |
3205 | sp_adjust); | |
557430f1 CJW |
3206 | } |
3207 | ||
03390cda | 3208 | /* Generate return instruction. */ |
d6529176 CJW |
3209 | if (!sibcall_p) |
3210 | emit_jump_insn (gen_return_internal ()); | |
9304f876 CJW |
3211 | } |
3212 | ||
3213 | /* Function for v3push prologue. */ | |
3214 | void | |
3215 | nds32_expand_prologue_v3push (void) | |
3216 | { | |
3217 | int fp_adjust; | |
3218 | int sp_adjust; | |
a6c7e777 | 3219 | unsigned Rb, Re; |
9304f876 | 3220 | |
9304f876 CJW |
3221 | /* Compute and setup stack frame size. |
3222 | The result will be in cfun->machine. */ | |
3223 | nds32_compute_stack_frame (); | |
3224 | ||
a6c7e777 MC |
3225 | if (cfun->machine->callee_saved_gpr_regs_size > 0) |
3226 | df_set_regs_ever_live (FP_REGNUM, 1); | |
3227 | ||
9304f876 CJW |
3228 | /* If the function is 'naked', |
3229 | we do not have to generate prologue code fragment. */ | |
3230 | if (cfun->machine->naked_p) | |
3231 | return; | |
3232 | ||
3233 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
3234 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
3235 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
3236 | |
3237 | /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available, | |
3238 | where imm8u has to be 8-byte alignment. */ | |
3239 | sp_adjust = cfun->machine->local_size | |
3240 | + cfun->machine->out_args_size | |
c457f751 | 3241 | + cfun->machine->callee_saved_area_gpr_padding_bytes; |
9304f876 CJW |
3242 | |
3243 | if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
3244 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)) | |
3245 | { | |
3246 | /* We can use 'push25 Re,imm8u'. */ | |
3247 | ||
88437f39 | 3248 | /* nds32_emit_stack_v3push(last_regno, sp_adjust), |
a6c7e777 MC |
3249 | the pattern 'stack_v3push' is implemented in nds32.md. */ |
3250 | nds32_emit_stack_v3push (Rb, Re, sp_adjust); | |
9304f876 | 3251 | /* Check frame_pointer_needed to see |
8a498f99 | 3252 | if we shall emit fp adjustment instruction. */ |
9304f876 CJW |
3253 | if (frame_pointer_needed) |
3254 | { | |
3255 | /* adjust $fp = $sp + 4 ($fp size) | |
8a498f99 CJW |
3256 | + 4 ($gp size) |
3257 | + 4 ($lp size) | |
3258 | + (4 * n) (callee-saved registers) | |
3259 | + sp_adjust ('push25 Re,imm8u') | |
9304f876 | 3260 | Note: Since we use 'push25 Re,imm8u', |
8a498f99 CJW |
3261 | the position of stack pointer is further |
3262 | changed after push instruction. | |
3263 | Hence, we need to take sp_adjust value | |
3264 | into consideration. */ | |
9304f876 CJW |
3265 | fp_adjust = cfun->machine->fp_size |
3266 | + cfun->machine->gp_size | |
3267 | + cfun->machine->lp_size | |
c457f751 | 3268 | + cfun->machine->callee_saved_gpr_regs_size |
9304f876 | 3269 | + sp_adjust; |
a6c7e777 MC |
3270 | |
3271 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, | |
3272 | stack_pointer_rtx, | |
3273 | fp_adjust); | |
9304f876 CJW |
3274 | } |
3275 | } | |
3276 | else | |
3277 | { | |
3278 | /* We have to use 'push25 Re,0' and | |
8a498f99 | 3279 | expand one more instruction to adjust $sp later. */ |
9304f876 | 3280 | |
88437f39 | 3281 | /* nds32_emit_stack_v3push(last_regno, sp_adjust), |
a6c7e777 MC |
3282 | the pattern 'stack_v3push' is implemented in nds32.md. */ |
3283 | nds32_emit_stack_v3push (Rb, Re, 0); | |
9304f876 CJW |
3284 | |
3285 | /* Check frame_pointer_needed to see | |
8a498f99 | 3286 | if we shall emit fp adjustment instruction. */ |
9304f876 CJW |
3287 | if (frame_pointer_needed) |
3288 | { | |
3289 | /* adjust $fp = $sp + 4 ($fp size) | |
8a498f99 CJW |
3290 | + 4 ($gp size) |
3291 | + 4 ($lp size) | |
3292 | + (4 * n) (callee-saved registers) | |
9304f876 | 3293 | Note: Since we use 'push25 Re,0', |
8a498f99 CJW |
3294 | the stack pointer is just at the position |
3295 | after push instruction. | |
3296 | No need to take sp_adjust into consideration. */ | |
9304f876 CJW |
3297 | fp_adjust = cfun->machine->fp_size |
3298 | + cfun->machine->gp_size | |
3299 | + cfun->machine->lp_size | |
c457f751 | 3300 | + cfun->machine->callee_saved_gpr_regs_size; |
a6c7e777 MC |
3301 | |
3302 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, | |
3303 | stack_pointer_rtx, | |
3304 | fp_adjust); | |
9304f876 CJW |
3305 | } |
3306 | ||
3307 | /* Because we use 'push25 Re,0', | |
8a498f99 | 3308 | we need to expand one more instruction to adjust $sp. |
8a498f99 | 3309 | using NEGATIVE value to tell that we are decreasing address. */ |
a6c7e777 MC |
3310 | nds32_emit_adjust_frame (stack_pointer_rtx, |
3311 | stack_pointer_rtx, | |
3312 | -1 * sp_adjust); | |
9304f876 CJW |
3313 | } |
3314 | ||
3315 | /* Prevent the instruction scheduler from | |
3316 | moving instructions across the boundary. */ | |
3317 | emit_insn (gen_blockage ()); | |
3318 | } | |
3319 | ||
3320 | /* Function for v3pop epilogue. */ | |
3321 | void | |
d6529176 | 3322 | nds32_expand_epilogue_v3pop (bool sibcall_p) |
9304f876 CJW |
3323 | { |
3324 | int sp_adjust; | |
a6c7e777 | 3325 | unsigned Rb, Re; |
9304f876 CJW |
3326 | |
3327 | /* Compute and setup stack frame size. | |
3328 | The result will be in cfun->machine. */ | |
3329 | nds32_compute_stack_frame (); | |
3330 | ||
3331 | /* Prevent the instruction scheduler from | |
3332 | moving instructions across the boundary. */ | |
3333 | emit_insn (gen_blockage ()); | |
3334 | ||
3335 | /* If the function is 'naked', we do not have to generate | |
3336 | epilogue code fragment BUT 'ret' instruction. */ | |
3337 | if (cfun->machine->naked_p) | |
3338 | { | |
03390cda | 3339 | /* Generate return instruction by using 'return_internal' pattern. |
8a498f99 | 3340 | Make sure this instruction is after gen_blockage(). */ |
d6529176 CJW |
3341 | if (!sibcall_p) |
3342 | emit_jump_insn (gen_return_internal ()); | |
9304f876 CJW |
3343 | return; |
3344 | } | |
3345 | ||
3346 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
3347 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
3348 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
3349 | |
3350 | /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available, | |
3351 | where imm8u has to be 8-byte alignment. */ | |
3352 | sp_adjust = cfun->machine->local_size | |
3353 | + cfun->machine->out_args_size | |
c457f751 | 3354 | + cfun->machine->callee_saved_area_gpr_padding_bytes; |
9304f876 CJW |
3355 | |
3356 | /* We have to consider alloca issue as well. | |
3357 | If the function does call alloca(), the stack pointer is not fixed. | |
3358 | In that case, we cannot use 'pop25 Re,imm8u' directly. | |
3359 | We have to caculate stack pointer from frame pointer | |
3360 | and then use 'pop25 Re,0'. | |
3361 | Of course, the frame_pointer_needed should be nonzero | |
3362 | if the function calls alloca(). */ | |
3363 | if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
3364 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) | |
3365 | && !cfun->calls_alloca) | |
3366 | { | |
3367 | /* We can use 'pop25 Re,imm8u'. */ | |
3368 | ||
88437f39 | 3369 | /* nds32_emit_stack_v3pop(last_regno, sp_adjust), |
a6c7e777 MC |
3370 | the pattern 'stack_v3pop' is implementad in nds32.md. */ |
3371 | nds32_emit_stack_v3pop (Rb, Re, sp_adjust); | |
9304f876 CJW |
3372 | } |
3373 | else | |
3374 | { | |
3375 | /* We have to use 'pop25 Re,0', and prior to it, | |
8a498f99 | 3376 | we must expand one more instruction to adjust $sp. */ |
9304f876 CJW |
3377 | |
3378 | if (frame_pointer_needed) | |
3379 | { | |
3380 | /* adjust $sp = $fp - 4 ($fp size) | |
8a498f99 CJW |
3381 | - 4 ($gp size) |
3382 | - 4 ($lp size) | |
3383 | - (4 * n) (callee-saved registers) | |
9304f876 | 3384 | Note: No need to adjust |
8a498f99 CJW |
3385 | cfun->machine->callee_saved_area_gpr_padding_bytes, |
3386 | because we want to adjust stack pointer | |
3387 | to the position for pop instruction. */ | |
9304f876 CJW |
3388 | sp_adjust = cfun->machine->fp_size |
3389 | + cfun->machine->gp_size | |
3390 | + cfun->machine->lp_size | |
c457f751 | 3391 | + cfun->machine->callee_saved_gpr_regs_size; |
a6c7e777 MC |
3392 | |
3393 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
3394 | hard_frame_pointer_rtx, | |
3395 | -1 * sp_adjust); | |
9304f876 CJW |
3396 | } |
3397 | else | |
3398 | { | |
3399 | /* If frame pointer is NOT needed, | |
3400 | we cannot calculate the sp adjustment from frame pointer. | |
3401 | Instead, we calculate the adjustment by local_size, | |
3402 | out_args_size, and callee_saved_area_padding_bytes. | |
3403 | Notice that such sp adjustment value may be out of range, | |
3404 | so we have to deal with it as well. */ | |
3405 | ||
3406 | /* Adjust $sp = $sp + local_size + out_args_size | |
a6c7e777 | 3407 | + callee_saved_area_gpr_padding_bytes. */ |
9304f876 CJW |
3408 | sp_adjust = cfun->machine->local_size |
3409 | + cfun->machine->out_args_size | |
c457f751 | 3410 | + cfun->machine->callee_saved_area_gpr_padding_bytes; |
a6c7e777 MC |
3411 | /* sp_adjust value may be out of range of the addi instruction, |
3412 | create alternative add behavior with TA_REGNUM if necessary, | |
3413 | using POSITIVE value to tell that we are increasing | |
3414 | address. */ | |
3415 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
3416 | stack_pointer_rtx, | |
3417 | sp_adjust); | |
9304f876 CJW |
3418 | } |
3419 | ||
88437f39 | 3420 | /* nds32_emit_stack_v3pop(last_regno, sp_adjust), |
8a498f99 | 3421 | the pattern 'stack_v3pop' is implementad in nds32.md. */ |
a6c7e777 | 3422 | nds32_emit_stack_v3pop (Rb, Re, 0); |
9304f876 | 3423 | } |
aa2642ef CJW |
3424 | |
3425 | /* Generate return instruction. */ | |
3426 | emit_jump_insn (gen_pop25return ()); | |
9304f876 CJW |
3427 | } |
3428 | ||
03390cda CJW |
3429 | /* Return nonzero if this function is known to have a null epilogue. |
3430 | This allows the optimizer to omit jumps to jumps if no stack | |
3431 | was created. */ | |
3432 | int | |
3433 | nds32_can_use_return_insn (void) | |
3434 | { | |
3435 | /* Prior to reloading, we can't tell how many registers must be saved. | |
3436 | Thus we can not determine whether this function has null epilogue. */ | |
3437 | if (!reload_completed) | |
3438 | return 0; | |
3439 | ||
3440 | /* If no stack was created, two conditions must be satisfied: | |
3441 | 1. This is a naked function. | |
8a498f99 | 3442 | So there is no callee-saved, local size, or outgoing size. |
03390cda | 3443 | 2. This is NOT a variadic function. |
8a498f99 | 3444 | So there is no pushing arguement registers into the stack. */ |
03390cda CJW |
3445 | return (cfun->machine->naked_p && (cfun->machine->va_args_size == 0)); |
3446 | } | |
3447 | ||
9304f876 CJW |
3448 | /* ------------------------------------------------------------------------ */ |
3449 | ||
3450 | /* Function to test 333-form for load/store instructions. | |
3451 | This is auxiliary extern function for auxiliary macro in nds32.h. | |
3452 | Because it is a little complicated, we use function instead of macro. */ | |
3453 | bool | |
ef4bddc2 | 3454 | nds32_ls_333_p (rtx rt, rtx ra, rtx imm, machine_mode mode) |
9304f876 CJW |
3455 | { |
3456 | if (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS | |
3457 | && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS) | |
3458 | { | |
3459 | if (GET_MODE_SIZE (mode) == 4) | |
3460 | return satisfies_constraint_Iu05 (imm); | |
3461 | ||
3462 | if (GET_MODE_SIZE (mode) == 2) | |
3463 | return satisfies_constraint_Iu04 (imm); | |
3464 | ||
3465 | if (GET_MODE_SIZE (mode) == 1) | |
3466 | return satisfies_constraint_Iu03 (imm); | |
3467 | } | |
3468 | ||
3469 | return false; | |
3470 | } | |
3471 | ||
3472 | ||
9304f876 CJW |
3473 | /* Computing the Length of an Insn. |
3474 | Modifies the length assigned to instruction INSN. | |
3475 | LEN is the initially computed length of the insn. */ | |
3476 | int | |
ca009aee | 3477 | nds32_adjust_insn_length (rtx_insn *insn, int length) |
9304f876 CJW |
3478 | { |
3479 | rtx src, dst; | |
3480 | ||
3481 | switch (recog_memoized (insn)) | |
3482 | { | |
3483 | case CODE_FOR_move_df: | |
3484 | case CODE_FOR_move_di: | |
3485 | /* Adjust length of movd44 to 2. */ | |
3486 | src = XEXP (PATTERN (insn), 1); | |
3487 | dst = XEXP (PATTERN (insn), 0); | |
3488 | ||
3489 | if (REG_P (src) | |
3490 | && REG_P (dst) | |
3491 | && (REGNO (src) % 2) == 0 | |
3492 | && (REGNO (dst) % 2) == 0) | |
3493 | length = 2; | |
3494 | break; | |
3495 | ||
3496 | default: | |
3497 | break; | |
3498 | } | |
3499 | ||
3500 | return length; | |
3501 | } | |
3502 | ||
3503 | ||
9304f876 CJW |
3504 | /* Return align 2 (log base 2) if the next instruction of LABEL is 4 byte. */ |
3505 | int | |
82082f65 | 3506 | nds32_target_alignment (rtx_insn *label) |
9304f876 | 3507 | { |
84034c69 | 3508 | rtx_insn *insn; |
9304f876 CJW |
3509 | |
3510 | if (optimize_size) | |
3511 | return 0; | |
3512 | ||
3513 | insn = next_active_insn (label); | |
3514 | ||
3515 | if (insn == 0) | |
3516 | return 0; | |
3517 | else if ((get_attr_length (insn) % 4) == 0) | |
3518 | return 2; | |
3519 | else | |
3520 | return 0; | |
3521 | } | |
3522 | ||
3523 | /* ------------------------------------------------------------------------ */ | |
3524 | ||
3525 | /* PART 5: Initialize target hook structure and definitions. */ | |
3526 | \f | |
3527 | /* Controlling the Compilation Driver. */ | |
3528 | ||
3529 | \f | |
3530 | /* Run-time Target Specification. */ | |
3531 | ||
3532 | \f | |
3533 | /* Defining Data Structures for Per-function Information. */ | |
3534 | ||
3535 | \f | |
3536 | /* Storage Layout. */ | |
3537 | ||
3538 | #undef TARGET_PROMOTE_FUNCTION_MODE | |
3539 | #define TARGET_PROMOTE_FUNCTION_MODE \ | |
3540 | default_promote_function_mode_always_promote | |
3541 | ||
3542 | \f | |
3543 | /* Layout of Source Language Data Types. */ | |
3544 | ||
3545 | \f | |
3546 | /* Register Usage. */ | |
3547 | ||
3548 | /* -- Basic Characteristics of Registers. */ | |
3549 | ||
3550 | /* -- Order of Allocation of Registers. */ | |
3551 | ||
3552 | /* -- How Values Fit in Registers. */ | |
3553 | ||
3554 | /* -- Handling Leaf Functions. */ | |
3555 | ||
3556 | /* -- Registers That Form a Stack. */ | |
3557 | ||
3558 | \f | |
3559 | /* Register Classes. */ | |
3560 | ||
3561 | #undef TARGET_CLASS_MAX_NREGS | |
3562 | #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs | |
3563 | ||
9304f876 CJW |
3564 | #undef TARGET_REGISTER_PRIORITY |
3565 | #define TARGET_REGISTER_PRIORITY nds32_register_priority | |
3566 | ||
3567 | \f | |
3568 | /* Obsolete Macros for Defining Constraints. */ | |
3569 | ||
3570 | \f | |
3571 | /* Stack Layout and Calling Conventions. */ | |
3572 | ||
3573 | /* -- Basic Stack Layout. */ | |
3574 | ||
3575 | /* -- Exception Handling Support. */ | |
3576 | ||
3577 | /* -- Specifying How Stack Checking is Done. */ | |
3578 | ||
3579 | /* -- Registers That Address the Stack Frame. */ | |
3580 | ||
3581 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
3582 | ||
3583 | #undef TARGET_CAN_ELIMINATE | |
3584 | #define TARGET_CAN_ELIMINATE nds32_can_eliminate | |
3585 | ||
3586 | /* -- Passing Function Arguments on the Stack. */ | |
3587 | ||
3588 | /* -- Passing Arguments in Registers. */ | |
3589 | ||
3590 | #undef TARGET_FUNCTION_ARG | |
3591 | #define TARGET_FUNCTION_ARG nds32_function_arg | |
3592 | ||
d40f3c40 CJW |
3593 | #undef TARGET_MUST_PASS_IN_STACK |
3594 | #define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack | |
3595 | ||
650fc469 CJW |
3596 | #undef TARGET_ARG_PARTIAL_BYTES |
3597 | #define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes | |
3598 | ||
9304f876 CJW |
3599 | #undef TARGET_FUNCTION_ARG_ADVANCE |
3600 | #define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance | |
3601 | ||
3602 | #undef TARGET_FUNCTION_ARG_BOUNDARY | |
3603 | #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary | |
3604 | ||
3605 | /* -- How Scalar Function Values Are Returned. */ | |
3606 | ||
3607 | #undef TARGET_FUNCTION_VALUE | |
3608 | #define TARGET_FUNCTION_VALUE nds32_function_value | |
3609 | ||
3610 | #undef TARGET_LIBCALL_VALUE | |
3611 | #define TARGET_LIBCALL_VALUE nds32_libcall_value | |
3612 | ||
3613 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
3614 | #define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p | |
3615 | ||
3616 | /* -- How Large Values Are Returned. */ | |
3617 | ||
3618 | /* -- Caller-Saves Register Allocation. */ | |
3619 | ||
3620 | /* -- Function Entry and Exit. */ | |
3621 | ||
3622 | #undef TARGET_ASM_FUNCTION_PROLOGUE | |
3623 | #define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue | |
3624 | ||
3625 | #undef TARGET_ASM_FUNCTION_END_PROLOGUE | |
3626 | #define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue | |
3627 | ||
3628 | #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE | |
3629 | #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue | |
3630 | ||
3631 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
3632 | #define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue | |
3633 | ||
3634 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
3635 | #define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk | |
3636 | ||
3637 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
3638 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
3639 | ||
3640 | /* -- Generating Code for Profiling. */ | |
3641 | ||
3642 | /* -- Permitting tail calls. */ | |
3643 | ||
3644 | #undef TARGET_WARN_FUNC_RETURN | |
3645 | #define TARGET_WARN_FUNC_RETURN nds32_warn_func_return | |
3646 | ||
3647 | /* Stack smashing protection. */ | |
3648 | ||
3649 | \f | |
3650 | /* Implementing the Varargs Macros. */ | |
3651 | ||
d4a6a4d9 CJW |
3652 | #undef TARGET_SETUP_INCOMING_VARARGS |
3653 | #define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs | |
3654 | ||
9304f876 CJW |
3655 | #undef TARGET_STRICT_ARGUMENT_NAMING |
3656 | #define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming | |
3657 | ||
3658 | \f | |
3659 | /* Trampolines for Nested Functions. */ | |
3660 | ||
3661 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE | |
3662 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template | |
3663 | ||
3664 | #undef TARGET_TRAMPOLINE_INIT | |
3665 | #define TARGET_TRAMPOLINE_INIT nds32_trampoline_init | |
3666 | ||
3667 | \f | |
3668 | /* Implicit Calls to Library Routines. */ | |
3669 | ||
3670 | \f | |
3671 | /* Addressing Modes. */ | |
3672 | ||
3673 | #undef TARGET_LEGITIMATE_ADDRESS_P | |
3674 | #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p | |
3675 | ||
3676 | \f | |
3677 | /* Anchored Addresses. */ | |
3678 | ||
3679 | \f | |
3680 | /* Condition Code Status. */ | |
3681 | ||
3682 | /* -- Representation of condition codes using (cc0). */ | |
3683 | ||
3684 | /* -- Representation of condition codes using registers. */ | |
3685 | ||
3686 | /* -- Macros to control conditional execution. */ | |
3687 | ||
3688 | \f | |
3689 | /* Describing Relative Costs of Operations. */ | |
3690 | ||
3691 | #undef TARGET_REGISTER_MOVE_COST | |
3692 | #define TARGET_REGISTER_MOVE_COST nds32_register_move_cost | |
3693 | ||
3694 | #undef TARGET_MEMORY_MOVE_COST | |
3695 | #define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost | |
3696 | ||
3697 | #undef TARGET_RTX_COSTS | |
3698 | #define TARGET_RTX_COSTS nds32_rtx_costs | |
3699 | ||
3700 | #undef TARGET_ADDRESS_COST | |
3701 | #define TARGET_ADDRESS_COST nds32_address_cost | |
3702 | ||
3703 | \f | |
3704 | /* Adjusting the Instruction Scheduler. */ | |
3705 | ||
3706 | \f | |
3707 | /* Dividing the Output into Sections (Texts, Data, . . . ). */ | |
3708 | ||
511a41d7 CJW |
3709 | #undef TARGET_ENCODE_SECTION_INFO |
3710 | #define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info | |
3711 | ||
9304f876 CJW |
3712 | \f |
3713 | /* Position Independent Code. */ | |
3714 | ||
3715 | \f | |
3716 | /* Defining the Output Assembler Language. */ | |
3717 | ||
3718 | /* -- The Overall Framework of an Assembler File. */ | |
3719 | ||
3720 | #undef TARGET_ASM_FILE_START | |
3721 | #define TARGET_ASM_FILE_START nds32_asm_file_start | |
3722 | #undef TARGET_ASM_FILE_END | |
3723 | #define TARGET_ASM_FILE_END nds32_asm_file_end | |
3724 | ||
3725 | /* -- Output of Data. */ | |
3726 | ||
3727 | #undef TARGET_ASM_ALIGNED_HI_OP | |
3728 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
3729 | ||
3730 | #undef TARGET_ASM_ALIGNED_SI_OP | |
3731 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
3732 | ||
3733 | /* -- Output of Uninitialized Variables. */ | |
3734 | ||
3735 | /* -- Output and Generation of Labels. */ | |
3736 | ||
3737 | #undef TARGET_ASM_GLOBALIZE_LABEL | |
3738 | #define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label | |
3739 | ||
3740 | /* -- How Initialization Functions Are Handled. */ | |
3741 | ||
3742 | /* -- Macros Controlling Initialization Routines. */ | |
3743 | ||
3744 | /* -- Output of Assembler Instructions. */ | |
3745 | ||
3746 | #undef TARGET_PRINT_OPERAND | |
3747 | #define TARGET_PRINT_OPERAND nds32_print_operand | |
3748 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
3749 | #define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address | |
3750 | ||
3751 | /* -- Output of Dispatch Tables. */ | |
3752 | ||
3753 | /* -- Assembler Commands for Exception Regions. */ | |
3754 | ||
3755 | /* -- Assembler Commands for Alignment. */ | |
3756 | ||
3757 | \f | |
3758 | /* Controlling Debugging Information Format. */ | |
3759 | ||
3760 | /* -- Macros Affecting All Debugging Formats. */ | |
3761 | ||
3762 | /* -- Specific Options for DBX Output. */ | |
3763 | ||
3764 | /* -- Open-Ended Hooks for DBX Format. */ | |
3765 | ||
3766 | /* -- File Names in DBX Format. */ | |
3767 | ||
180295ed | 3768 | /* -- Macros for DWARF Output. */ |
9304f876 CJW |
3769 | |
3770 | /* -- Macros for VMS Debug Format. */ | |
3771 | ||
3772 | \f | |
3773 | /* Cross Compilation and Floating Point. */ | |
3774 | ||
3775 | \f | |
3776 | /* Mode Switching Instructions. */ | |
3777 | ||
3778 | \f | |
3779 | /* Defining target-specific uses of __attribute__. */ | |
3780 | ||
3781 | #undef TARGET_ATTRIBUTE_TABLE | |
3782 | #define TARGET_ATTRIBUTE_TABLE nds32_attribute_table | |
3783 | ||
3784 | #undef TARGET_MERGE_DECL_ATTRIBUTES | |
3785 | #define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes | |
3786 | ||
3787 | #undef TARGET_INSERT_ATTRIBUTES | |
3788 | #define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes | |
3789 | ||
3790 | #undef TARGET_OPTION_PRAGMA_PARSE | |
3791 | #define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse | |
3792 | ||
3793 | #undef TARGET_OPTION_OVERRIDE | |
3794 | #define TARGET_OPTION_OVERRIDE nds32_option_override | |
3795 | ||
3796 | \f | |
3797 | /* Emulating TLS. */ | |
3798 | ||
3799 | \f | |
3800 | /* Defining coprocessor specifics for MIPS targets. */ | |
3801 | ||
3802 | \f | |
3803 | /* Parameters for Precompiled Header Validity Checking. */ | |
3804 | ||
3805 | \f | |
3806 | /* C++ ABI parameters. */ | |
3807 | ||
3808 | \f | |
3809 | /* Adding support for named address spaces. */ | |
3810 | ||
3811 | \f | |
3812 | /* Miscellaneous Parameters. */ | |
3813 | ||
823835a9 CJW |
3814 | #undef TARGET_MD_ASM_ADJUST |
3815 | #define TARGET_MD_ASM_ADJUST nds32_md_asm_adjust | |
3816 | ||
9304f876 CJW |
3817 | #undef TARGET_INIT_BUILTINS |
3818 | #define TARGET_INIT_BUILTINS nds32_init_builtins | |
3819 | ||
7a12ea32 MC |
3820 | #undef TARGET_BUILTIN_DECL |
3821 | #define TARGET_BUILTIN_DECL nds32_builtin_decl | |
3822 | ||
9304f876 CJW |
3823 | #undef TARGET_EXPAND_BUILTIN |
3824 | #define TARGET_EXPAND_BUILTIN nds32_expand_builtin | |
3825 | ||
3826 | \f | |
3827 | /* ------------------------------------------------------------------------ */ | |
3828 | ||
3829 | /* Initialize the GCC target structure. */ | |
3830 | ||
3831 | struct gcc_target targetm = TARGET_INITIALIZER; | |
3832 | ||
3833 | /* ------------------------------------------------------------------------ */ |