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9304f876 | 1 | /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler |
85ec4feb | 2 | Copyright (C) 2012-2018 Free Software Foundation, Inc. |
9304f876 CJW |
3 | Contributed by Andes Technology Corporation. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 3, or (at your | |
10 | option) any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
19ac960a | 21 | /* ------------------------------------------------------------------------ */ |
9304f876 | 22 | |
8fcc61f8 RS |
23 | #define IN_TARGET_CODE 1 |
24 | ||
9304f876 CJW |
25 | #include "config.h" |
26 | #include "system.h" | |
27 | #include "coretypes.h" | |
c7131fb2 | 28 | #include "backend.h" |
e11c4407 | 29 | #include "target.h" |
c7131fb2 | 30 | #include "rtl.h" |
e11c4407 | 31 | #include "tree.h" |
c4d8d050 | 32 | #include "tree-pass.h" |
314e6352 ML |
33 | #include "stringpool.h" |
34 | #include "attribs.h" | |
c7131fb2 | 35 | #include "df.h" |
4d0cdd0c | 36 | #include "memmodel.h" |
e11c4407 AM |
37 | #include "tm_p.h" |
38 | #include "optabs.h" /* For GEN_FCN. */ | |
39 | #include "regs.h" | |
40 | #include "emit-rtl.h" | |
41 | #include "recog.h" | |
42 | #include "diagnostic-core.h" | |
d8a2d370 DN |
43 | #include "stor-layout.h" |
44 | #include "varasm.h" | |
45 | #include "calls.h" | |
9304f876 | 46 | #include "output.h" |
36566b39 | 47 | #include "explow.h" |
9304f876 | 48 | #include "expr.h" |
9304f876 | 49 | #include "tm-constrs.h" |
9b2b7279 | 50 | #include "builtins.h" |
72b7e5e1 | 51 | #include "cpplib.h" |
c4d8d050 | 52 | #include "context.h" |
9304f876 | 53 | |
994c5d85 | 54 | /* This file should be included last. */ |
d58627a0 RS |
55 | #include "target-def.h" |
56 | ||
9304f876 CJW |
57 | /* ------------------------------------------------------------------------ */ |
58 | ||
59 | /* This file is divided into five parts: | |
60 | ||
61 | PART 1: Auxiliary static variable definitions and | |
62 | target hook static variable definitions. | |
63 | ||
64 | PART 2: Auxiliary static function definitions. | |
65 | ||
66 | PART 3: Implement target hook stuff definitions. | |
67 | ||
68 | PART 4: Implemet extern function definitions, | |
69 | the prototype is in nds32-protos.h. | |
70 | ||
71 | PART 5: Initialize target hook structure and definitions. */ | |
72 | ||
73 | /* ------------------------------------------------------------------------ */ | |
74 | ||
75 | /* PART 1: Auxiliary static variable definitions and | |
76 | target hook static variable definitions. */ | |
77 | ||
9304f876 CJW |
78 | /* Define intrinsic register names. |
79 | Please refer to nds32_intrinsic.h file, the index is corresponding to | |
80 | 'enum nds32_intrinsic_registers' data type values. | |
81 | NOTE that the base value starting from 1024. */ | |
82 | static const char * const nds32_intrinsic_register_names[] = | |
83 | { | |
2095a9d5 MC |
84 | "$CPU_VER", |
85 | "$ICM_CFG", | |
86 | "$DCM_CFG", | |
87 | "$MMU_CFG", | |
88 | "$MSC_CFG", | |
89 | "$MSC_CFG2", | |
90 | "$CORE_ID", | |
91 | "$FUCOP_EXIST", | |
92 | ||
93 | "$PSW", | |
94 | "$IPSW", | |
95 | "$P_IPSW", | |
96 | "$IVB", | |
97 | "$EVA", | |
98 | "$P_EVA", | |
99 | "$ITYPE", | |
100 | "$P_ITYPE", | |
101 | ||
102 | "$MERR", | |
103 | "$IPC", | |
104 | "$P_IPC", | |
105 | "$OIPC", | |
106 | "$P_P0", | |
107 | "$P_P1", | |
108 | ||
109 | "$INT_MASK", | |
110 | "$INT_MASK2", | |
111 | "$INT_MASK3", | |
112 | "$INT_PEND", | |
113 | "$INT_PEND2", | |
114 | "$INT_PEND3", | |
115 | "$SP_USR", | |
116 | "$SP_PRIV", | |
117 | "$INT_PRI", | |
118 | "$INT_PRI2", | |
119 | "$INT_PRI3", | |
120 | "$INT_PRI4", | |
121 | "$INT_CTRL", | |
122 | "$INT_TRIGGER", | |
123 | "$INT_TRIGGER2", | |
124 | "$INT_GPR_PUSH_DIS", | |
125 | ||
126 | "$MMU_CTL", | |
127 | "$L1_PPTB", | |
128 | "$TLB_VPN", | |
129 | "$TLB_DATA", | |
130 | "$TLB_MISC", | |
131 | "$VLPT_IDX", | |
132 | "$ILMB", | |
133 | "$DLMB", | |
134 | ||
135 | "$CACHE_CTL", | |
136 | "$HSMP_SADDR", | |
137 | "$HSMP_EADDR", | |
138 | "$SDZ_CTL", | |
139 | "$N12MISC_CTL", | |
140 | "$MISC_CTL", | |
141 | "$ECC_MISC", | |
142 | ||
143 | "$BPC0", | |
144 | "$BPC1", | |
145 | "$BPC2", | |
146 | "$BPC3", | |
147 | "$BPC4", | |
148 | "$BPC5", | |
149 | "$BPC6", | |
150 | "$BPC7", | |
151 | ||
152 | "$BPA0", | |
153 | "$BPA1", | |
154 | "$BPA2", | |
155 | "$BPA3", | |
156 | "$BPA4", | |
157 | "$BPA5", | |
158 | "$BPA6", | |
159 | "$BPA7", | |
160 | ||
161 | "$BPAM0", | |
162 | "$BPAM1", | |
163 | "$BPAM2", | |
164 | "$BPAM3", | |
165 | "$BPAM4", | |
166 | "$BPAM5", | |
167 | "$BPAM6", | |
168 | "$BPAM7", | |
169 | ||
170 | "$BPV0", | |
171 | "$BPV1", | |
172 | "$BPV2", | |
173 | "$BPV3", | |
174 | "$BPV4", | |
175 | "$BPV5", | |
176 | "$BPV6", | |
177 | "$BPV7", | |
178 | ||
179 | "$BPCID0", | |
180 | "$BPCID1", | |
181 | "$BPCID2", | |
182 | "$BPCID3", | |
183 | "$BPCID4", | |
184 | "$BPCID5", | |
185 | "$BPCID6", | |
186 | "$BPCID7", | |
187 | ||
188 | "$EDM_CFG", | |
189 | "$EDMSW", | |
190 | "$EDM_CTL", | |
191 | "$EDM_DTR", | |
192 | "$BPMTC", | |
193 | "$DIMBR", | |
194 | ||
195 | "$TECR0", | |
196 | "$TECR1", | |
197 | "$PFMC0", | |
198 | "$PFMC1", | |
199 | "$PFMC2", | |
200 | "$PFM_CTL", | |
201 | "$PFT_CTL", | |
202 | "$HSP_CTL", | |
203 | "$SP_BOUND", | |
204 | "$SP_BOUND_PRIV", | |
205 | "$SP_BASE", | |
206 | "$SP_BASE_PRIV", | |
207 | "$FUCOP_CTL", | |
208 | "$PRUSR_ACC_CTL", | |
209 | ||
210 | "$DMA_CFG", | |
211 | "$DMA_GCSW", | |
212 | "$DMA_CHNSEL", | |
213 | "$DMA_ACT", | |
214 | "$DMA_SETUP", | |
215 | "$DMA_ISADDR", | |
216 | "$DMA_ESADDR", | |
217 | "$DMA_TCNT", | |
218 | "$DMA_STATUS", | |
219 | "$DMA_2DSET", | |
220 | "$DMA_2DSCTL", | |
221 | "$DMA_RCNT", | |
222 | "$DMA_HSTATUS", | |
223 | ||
224 | "$PC", | |
225 | "$SP_USR1", | |
226 | "$SP_USR2", | |
227 | "$SP_USR3", | |
228 | "$SP_PRIV1", | |
229 | "$SP_PRIV2", | |
230 | "$SP_PRIV3", | |
231 | "$BG_REGION", | |
232 | "$SFCR", | |
233 | "$SIGN", | |
234 | "$ISIGN", | |
235 | "$P_ISIGN", | |
236 | "$IFC_LP", | |
237 | "$ITB" | |
9304f876 CJW |
238 | }; |
239 | ||
f1a0afe2 MC |
240 | /* Define instrinsic cctl names. */ |
241 | static const char * const nds32_cctl_names[] = | |
242 | { | |
243 | "L1D_VA_FILLCK", | |
244 | "L1D_VA_ULCK", | |
245 | "L1I_VA_FILLCK", | |
246 | "L1I_VA_ULCK", | |
247 | ||
248 | "L1D_IX_WBINVAL", | |
249 | "L1D_IX_INVAL", | |
250 | "L1D_IX_WB", | |
251 | "L1I_IX_INVAL", | |
252 | ||
253 | "L1D_VA_INVAL", | |
254 | "L1D_VA_WB", | |
255 | "L1D_VA_WBINVAL", | |
256 | "L1I_VA_INVAL", | |
257 | ||
258 | "L1D_IX_RTAG", | |
259 | "L1D_IX_RWD", | |
260 | "L1I_IX_RTAG", | |
261 | "L1I_IX_RWD", | |
262 | ||
263 | "L1D_IX_WTAG", | |
264 | "L1D_IX_WWD", | |
265 | "L1I_IX_WTAG", | |
266 | "L1I_IX_WWD" | |
267 | }; | |
5e6ae0cc | 268 | |
57aaf0cc MC |
269 | static const char * const nds32_dpref_names[] = |
270 | { | |
271 | "SRD", | |
272 | "MRD", | |
273 | "SWR", | |
274 | "MWR", | |
275 | "PTE", | |
276 | "CLWR" | |
277 | }; | |
278 | ||
5e6ae0cc CJW |
279 | /* Defining register allocation order for performance. |
280 | We want to allocate callee-saved registers after others. | |
281 | It may be used by nds32_adjust_reg_alloc_order(). */ | |
282 | static const int nds32_reg_alloc_order_for_speed[] = | |
283 | { | |
284 | 0, 1, 2, 3, 4, 5, 16, 17, | |
285 | 18, 19, 20, 21, 22, 23, 24, 25, | |
286 | 26, 27, 6, 7, 8, 9, 10, 11, | |
287 | 12, 13, 14, 15 | |
288 | }; | |
289 | ||
9304f876 CJW |
290 | /* Defining target-specific uses of __attribute__. */ |
291 | static const struct attribute_spec nds32_attribute_table[] = | |
292 | { | |
293 | /* Syntax: { name, min_len, max_len, decl_required, type_required, | |
4849deb1 JJ |
294 | function_type_required, affects_type_identity, handler, |
295 | exclude } */ | |
9304f876 CJW |
296 | |
297 | /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */ | |
4849deb1 | 298 | { "interrupt", 1, 64, false, false, false, false, NULL, NULL }, |
9304f876 | 299 | /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */ |
4849deb1 | 300 | { "exception", 1, 8, false, false, false, false, NULL, NULL }, |
9304f876 | 301 | /* Argument is user's interrupt numbers. The vector number is always 0. */ |
4849deb1 | 302 | { "reset", 1, 1, false, false, false, false, NULL, NULL }, |
9304f876 CJW |
303 | |
304 | /* The attributes describing isr nested type. */ | |
4849deb1 JJ |
305 | { "nested", 0, 0, false, false, false, false, NULL, NULL }, |
306 | { "not_nested", 0, 0, false, false, false, false, NULL, NULL }, | |
307 | { "nested_ready", 0, 0, false, false, false, false, NULL, NULL }, | |
a4931745 | 308 | { "critical", 0, 0, false, false, false, false, NULL, NULL }, |
9304f876 CJW |
309 | |
310 | /* The attributes describing isr register save scheme. */ | |
4849deb1 JJ |
311 | { "save_all", 0, 0, false, false, false, false, NULL, NULL }, |
312 | { "partial_save", 0, 0, false, false, false, false, NULL, NULL }, | |
9304f876 CJW |
313 | |
314 | /* The attributes used by reset attribute. */ | |
4849deb1 JJ |
315 | { "nmi", 1, 1, false, false, false, false, NULL, NULL }, |
316 | { "warm", 1, 1, false, false, false, false, NULL, NULL }, | |
9304f876 | 317 | |
a4931745 CJW |
318 | /* The attributes describing isr security level. */ |
319 | { "secure", 1, 1, false, false, false, false, NULL, NULL }, | |
320 | ||
9304f876 | 321 | /* The attribute telling no prologue/epilogue. */ |
4849deb1 | 322 | { "naked", 0, 0, false, false, false, false, NULL, NULL }, |
9304f876 | 323 | |
85a98076 KLC |
324 | /* The attribute is used to tell this function to be ROM patch. */ |
325 | { "indirect_call",0, 0, false, false, false, false, NULL, NULL }, | |
326 | ||
54c537e6 CJW |
327 | /* FOR BACKWARD COMPATIBILITY, |
328 | this attribute also tells no prologue/epilogue. */ | |
329 | { "no_prologue", 0, 0, false, false, false, false, NULL, NULL }, | |
330 | ||
9304f876 | 331 | /* The last attribute spec is set to be NULL. */ |
4849deb1 | 332 | { NULL, 0, 0, false, false, false, false, NULL, NULL } |
9304f876 CJW |
333 | }; |
334 | ||
335 | ||
336 | /* ------------------------------------------------------------------------ */ | |
337 | ||
338 | /* PART 2: Auxiliary static function definitions. */ | |
339 | ||
340 | /* Function to save and restore machine-specific function data. */ | |
341 | static struct machine_function * | |
342 | nds32_init_machine_status (void) | |
343 | { | |
344 | struct machine_function *machine; | |
766090c2 | 345 | machine = ggc_cleared_alloc<machine_function> (); |
9304f876 | 346 | |
ca3a4a55 CJW |
347 | /* Initially assume this function does not use __builtin_eh_return. */ |
348 | machine->use_eh_return_p = 0; | |
349 | ||
9304f876 CJW |
350 | /* Initially assume this function needs prologue/epilogue. */ |
351 | machine->naked_p = 0; | |
352 | ||
353 | /* Initially assume this function does NOT use fp_as_gp optimization. */ | |
354 | machine->fp_as_gp_p = 0; | |
355 | ||
5f2a98c3 CJW |
356 | /* Initially this function is not under strictly aligned situation. */ |
357 | machine->strict_aligned_p = 0; | |
358 | ||
54c537e6 CJW |
359 | /* Initially this function has no naked and no_prologue attributes. */ |
360 | machine->attr_naked_p = 0; | |
361 | machine->attr_no_prologue_p = 0; | |
362 | ||
9304f876 CJW |
363 | return machine; |
364 | } | |
365 | ||
366 | /* Function to compute stack frame size and | |
367 | store into cfun->machine structure. */ | |
368 | static void | |
369 | nds32_compute_stack_frame (void) | |
370 | { | |
371 | int r; | |
372 | int block_size; | |
a6c7e777 | 373 | bool v3pushpop_p; |
9304f876 CJW |
374 | |
375 | /* Because nds32_compute_stack_frame() will be called from different place, | |
376 | everytime we enter this function, we have to assume this function | |
377 | needs prologue/epilogue. */ | |
378 | cfun->machine->naked_p = 0; | |
379 | ||
54c537e6 CJW |
380 | /* We need to mark whether this function has naked and no_prologue |
381 | attribute so that we can distinguish the difference if users applies | |
382 | -mret-in-naked-func option. */ | |
383 | cfun->machine->attr_naked_p | |
384 | = lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) | |
385 | ? 1 : 0; | |
386 | cfun->machine->attr_no_prologue_p | |
387 | = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) | |
388 | ? 1 : 0; | |
ca3a4a55 CJW |
389 | |
390 | /* If __builtin_eh_return is used, we better have frame pointer needed | |
391 | so that we can easily locate the stack slot of return address. */ | |
392 | if (crtl->calls_eh_return) | |
393 | { | |
394 | frame_pointer_needed = 1; | |
395 | ||
396 | /* We need to mark eh data registers that need to be saved | |
397 | in the stack. */ | |
398 | cfun->machine->eh_return_data_first_regno = EH_RETURN_DATA_REGNO (0); | |
399 | for (r = 0; EH_RETURN_DATA_REGNO (r) != INVALID_REGNUM; r++) | |
400 | cfun->machine->eh_return_data_last_regno = r; | |
401 | ||
402 | cfun->machine->eh_return_data_regs_size | |
403 | = 4 * (cfun->machine->eh_return_data_last_regno | |
404 | - cfun->machine->eh_return_data_first_regno | |
405 | + 1); | |
406 | cfun->machine->use_eh_return_p = 1; | |
407 | } | |
408 | else | |
409 | { | |
410 | /* Assigning SP_REGNUM to eh_first_regno and eh_last_regno means we | |
411 | do not need to handle __builtin_eh_return case in this function. */ | |
412 | cfun->machine->eh_return_data_first_regno = SP_REGNUM; | |
413 | cfun->machine->eh_return_data_last_regno = SP_REGNUM; | |
414 | ||
415 | cfun->machine->eh_return_data_regs_size = 0; | |
416 | cfun->machine->use_eh_return_p = 0; | |
417 | } | |
418 | ||
9304f876 | 419 | /* Get variadic arguments size to prepare pretend arguments and |
35da54a6 CJW |
420 | we will push them into stack at prologue by ourself. */ |
421 | cfun->machine->va_args_size = crtl->args.pretend_args_size; | |
422 | if (cfun->machine->va_args_size != 0) | |
423 | { | |
424 | cfun->machine->va_args_first_regno | |
8a498f99 CJW |
425 | = NDS32_GPR_ARG_FIRST_REGNUM |
426 | + NDS32_MAX_GPR_REGS_FOR_ARGS | |
427 | - (crtl->args.pretend_args_size / UNITS_PER_WORD); | |
35da54a6 | 428 | cfun->machine->va_args_last_regno |
8a498f99 | 429 | = NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS - 1; |
35da54a6 CJW |
430 | } |
431 | else | |
432 | { | |
433 | cfun->machine->va_args_first_regno = SP_REGNUM; | |
434 | cfun->machine->va_args_last_regno = SP_REGNUM; | |
435 | } | |
436 | ||
437 | /* Important: We need to make sure that varargs area is 8-byte alignment. */ | |
438 | block_size = cfun->machine->va_args_size; | |
439 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) | |
440 | { | |
441 | cfun->machine->va_args_area_padding_bytes | |
442 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; | |
443 | } | |
9304f876 CJW |
444 | |
445 | /* Get local variables, incoming variables, and temporary variables size. | |
446 | Note that we need to make sure it is 8-byte alignment because | |
447 | there may be no padding bytes if we are using LRA. */ | |
448 | cfun->machine->local_size = NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ()); | |
449 | ||
450 | /* Get outgoing arguments size. */ | |
451 | cfun->machine->out_args_size = crtl->outgoing_args_size; | |
452 | ||
453 | /* If $fp value is required to be saved on stack, it needs 4 bytes space. | |
454 | Check whether $fp is ever live. */ | |
455 | cfun->machine->fp_size = (df_regs_ever_live_p (FP_REGNUM)) ? 4 : 0; | |
456 | ||
457 | /* If $gp value is required to be saved on stack, it needs 4 bytes space. | |
458 | Check whether we are using PIC code genration. */ | |
b26fa4f9 KLC |
459 | cfun->machine->gp_size = |
460 | (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ? 4 : 0; | |
9304f876 CJW |
461 | |
462 | /* If $lp value is required to be saved on stack, it needs 4 bytes space. | |
463 | Check whether $lp is ever live. */ | |
13116651 CJW |
464 | cfun->machine->lp_size |
465 | = (flag_always_save_lp || df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0; | |
9304f876 CJW |
466 | |
467 | /* Initially there is no padding bytes. */ | |
c457f751 | 468 | cfun->machine->callee_saved_area_gpr_padding_bytes = 0; |
9304f876 CJW |
469 | |
470 | /* Calculate the bytes of saving callee-saved registers on stack. */ | |
c457f751 CJW |
471 | cfun->machine->callee_saved_gpr_regs_size = 0; |
472 | cfun->machine->callee_saved_first_gpr_regno = SP_REGNUM; | |
473 | cfun->machine->callee_saved_last_gpr_regno = SP_REGNUM; | |
e2286268 MC |
474 | cfun->machine->callee_saved_fpr_regs_size = 0; |
475 | cfun->machine->callee_saved_first_fpr_regno = SP_REGNUM; | |
476 | cfun->machine->callee_saved_last_fpr_regno = SP_REGNUM; | |
477 | ||
9304f876 CJW |
478 | /* Currently, there is no need to check $r28~$r31 |
479 | because we will save them in another way. */ | |
480 | for (r = 0; r < 28; r++) | |
481 | { | |
482 | if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) | |
483 | { | |
484 | /* Mark the first required callee-saved register | |
485 | (only need to set it once). | |
486 | If first regno == SP_REGNUM, we can tell that | |
487 | it is the first time to be here. */ | |
c457f751 CJW |
488 | if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) |
489 | cfun->machine->callee_saved_first_gpr_regno = r; | |
9304f876 | 490 | /* Mark the last required callee-saved register. */ |
c457f751 | 491 | cfun->machine->callee_saved_last_gpr_regno = r; |
9304f876 CJW |
492 | } |
493 | } | |
494 | ||
e2286268 MC |
495 | /* Recording fpu callee-saved register. */ |
496 | if (TARGET_HARD_FLOAT) | |
497 | { | |
498 | for (r = NDS32_FIRST_FPR_REGNUM; r < NDS32_LAST_FPR_REGNUM; r++) | |
499 | { | |
500 | if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) | |
501 | { | |
502 | /* Mark the first required callee-saved register. */ | |
503 | if (cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM) | |
504 | { | |
505 | /* Make first callee-saved number is even, | |
506 | bacause we use doubleword access, and this way | |
507 | promise 8-byte alignemt. */ | |
508 | if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (r)) | |
509 | cfun->machine->callee_saved_first_fpr_regno = r - 1; | |
510 | else | |
511 | cfun->machine->callee_saved_first_fpr_regno = r; | |
512 | } | |
513 | cfun->machine->callee_saved_last_fpr_regno = r; | |
514 | } | |
515 | } | |
516 | ||
517 | /* Make last callee-saved register number is odd, | |
518 | we hope callee-saved register is even. */ | |
519 | int last_fpr = cfun->machine->callee_saved_last_fpr_regno; | |
520 | if (NDS32_FPR_REGNO_OK_FOR_DOUBLE (last_fpr)) | |
521 | cfun->machine->callee_saved_last_fpr_regno++; | |
522 | } | |
523 | ||
9304f876 | 524 | /* Check if this function can omit prologue/epilogue code fragment. |
a4931745 | 525 | If there is 'no_prologue'/'naked'/'secure' attribute in this function, |
9304f876 CJW |
526 | we can set 'naked_p' flag to indicate that |
527 | we do not have to generate prologue/epilogue. | |
528 | Or, if all the following conditions succeed, | |
529 | we can set this function 'naked_p' as well: | |
530 | condition 1: first_regno == last_regno == SP_REGNUM, | |
8a498f99 CJW |
531 | which means we do not have to save |
532 | any callee-saved registers. | |
9304f876 | 533 | condition 2: Both $lp and $fp are NOT live in this function, |
8a498f99 CJW |
534 | which means we do not need to save them and there |
535 | is no outgoing size. | |
9304f876 | 536 | condition 3: There is no local_size, which means |
8a498f99 | 537 | we do not need to adjust $sp. */ |
54c537e6 CJW |
538 | if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) |
539 | || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) | |
a4931745 | 540 | || lookup_attribute ("secure", DECL_ATTRIBUTES (current_function_decl)) |
c457f751 CJW |
541 | || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM |
542 | && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM | |
e2286268 MC |
543 | && cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM |
544 | && cfun->machine->callee_saved_last_fpr_regno == SP_REGNUM | |
9304f876 CJW |
545 | && !df_regs_ever_live_p (FP_REGNUM) |
546 | && !df_regs_ever_live_p (LP_REGNUM) | |
b26fa4f9 KLC |
547 | && cfun->machine->local_size == 0 |
548 | && !flag_pic)) | |
9304f876 | 549 | { |
2da1e7c0 | 550 | /* Set this function 'naked_p' and other functions can check this flag. |
8a498f99 CJW |
551 | Note that in nds32 port, the 'naked_p = 1' JUST means there is no |
552 | callee-saved, local size, and outgoing size. | |
553 | The varargs space and ret instruction may still present in | |
554 | the prologue/epilogue expanding. */ | |
9304f876 CJW |
555 | cfun->machine->naked_p = 1; |
556 | ||
557 | /* No need to save $fp, $gp, and $lp. | |
8a498f99 CJW |
558 | We should set these value to be zero |
559 | so that nds32_initial_elimination_offset() can work properly. */ | |
9304f876 CJW |
560 | cfun->machine->fp_size = 0; |
561 | cfun->machine->gp_size = 0; | |
562 | cfun->machine->lp_size = 0; | |
563 | ||
564 | /* If stack usage computation is required, | |
8a498f99 | 565 | we need to provide the static stack size. */ |
9304f876 CJW |
566 | if (flag_stack_usage_info) |
567 | current_function_static_stack_size = 0; | |
568 | ||
569 | /* No need to do following adjustment, return immediately. */ | |
570 | return; | |
571 | } | |
572 | ||
a6c7e777 MC |
573 | v3pushpop_p = NDS32_V3PUSH_AVAILABLE_P; |
574 | ||
9304f876 CJW |
575 | /* Adjustment for v3push instructions: |
576 | If we are using v3push (push25/pop25) instructions, | |
577 | we need to make sure Rb is $r6 and Re is | |
578 | located on $r6, $r8, $r10, or $r14. | |
579 | Some results above will be discarded and recomputed. | |
2da1e7c0 CJW |
580 | Note that it is only available under V3/V3M ISA and we |
581 | DO NOT setup following stuff for isr or variadic function. */ | |
a6c7e777 | 582 | if (v3pushpop_p) |
9304f876 CJW |
583 | { |
584 | /* Recompute: | |
8a498f99 CJW |
585 | cfun->machine->fp_size |
586 | cfun->machine->gp_size | |
587 | cfun->machine->lp_size | |
588 | cfun->machine->callee_saved_first_gpr_regno | |
589 | cfun->machine->callee_saved_last_gpr_regno */ | |
9304f876 CJW |
590 | |
591 | /* For v3push instructions, $fp, $gp, and $lp are always saved. */ | |
592 | cfun->machine->fp_size = 4; | |
593 | cfun->machine->gp_size = 4; | |
594 | cfun->machine->lp_size = 4; | |
595 | ||
596 | /* Remember to set Rb = $r6. */ | |
c457f751 | 597 | cfun->machine->callee_saved_first_gpr_regno = 6; |
9304f876 | 598 | |
c457f751 | 599 | if (cfun->machine->callee_saved_last_gpr_regno <= 6) |
9304f876 CJW |
600 | { |
601 | /* Re = $r6 */ | |
c457f751 | 602 | cfun->machine->callee_saved_last_gpr_regno = 6; |
9304f876 | 603 | } |
c457f751 | 604 | else if (cfun->machine->callee_saved_last_gpr_regno <= 8) |
9304f876 CJW |
605 | { |
606 | /* Re = $r8 */ | |
c457f751 | 607 | cfun->machine->callee_saved_last_gpr_regno = 8; |
9304f876 | 608 | } |
c457f751 | 609 | else if (cfun->machine->callee_saved_last_gpr_regno <= 10) |
9304f876 CJW |
610 | { |
611 | /* Re = $r10 */ | |
c457f751 | 612 | cfun->machine->callee_saved_last_gpr_regno = 10; |
9304f876 | 613 | } |
c457f751 | 614 | else if (cfun->machine->callee_saved_last_gpr_regno <= 14) |
9304f876 CJW |
615 | { |
616 | /* Re = $r14 */ | |
c457f751 | 617 | cfun->machine->callee_saved_last_gpr_regno = 14; |
9304f876 | 618 | } |
c457f751 | 619 | else if (cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM) |
9304f876 CJW |
620 | { |
621 | /* If last_regno is SP_REGNUM, which means | |
622 | it is never changed, so set it to Re = $r6. */ | |
c457f751 | 623 | cfun->machine->callee_saved_last_gpr_regno = 6; |
9304f876 CJW |
624 | } |
625 | else | |
626 | { | |
627 | /* The program flow should not go here. */ | |
628 | gcc_unreachable (); | |
629 | } | |
630 | } | |
631 | ||
a6c7e777 MC |
632 | int sp_adjust = cfun->machine->local_size |
633 | + cfun->machine->out_args_size | |
e2286268 MC |
634 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
635 | + cfun->machine->callee_saved_fpr_regs_size; | |
a6c7e777 MC |
636 | |
637 | if (!v3pushpop_p | |
638 | && sp_adjust == 0 | |
639 | && !frame_pointer_needed) | |
640 | { | |
641 | block_size = cfun->machine->fp_size | |
642 | + cfun->machine->gp_size | |
361292be CJW |
643 | + cfun->machine->lp_size; |
644 | ||
645 | if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) | |
646 | block_size += (4 * (cfun->machine->callee_saved_last_gpr_regno | |
647 | - cfun->machine->callee_saved_first_gpr_regno | |
648 | + 1)); | |
a6c7e777 MC |
649 | |
650 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) | |
651 | { | |
652 | /* $r14 is last callee save register. */ | |
653 | if (cfun->machine->callee_saved_last_gpr_regno | |
654 | < NDS32_LAST_CALLEE_SAVE_GPR_REGNUM) | |
655 | { | |
656 | cfun->machine->callee_saved_last_gpr_regno++; | |
657 | } | |
658 | else if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) | |
659 | { | |
660 | cfun->machine->callee_saved_first_gpr_regno | |
661 | = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; | |
662 | cfun->machine->callee_saved_last_gpr_regno | |
663 | = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; | |
664 | } | |
665 | } | |
666 | } | |
667 | ||
8a498f99 CJW |
668 | /* We have correctly set callee_saved_first_gpr_regno |
669 | and callee_saved_last_gpr_regno. | |
670 | Initially, the callee_saved_gpr_regs_size is supposed to be 0. | |
671 | As long as callee_saved_last_gpr_regno is not SP_REGNUM, | |
672 | we can update callee_saved_gpr_regs_size with new size. */ | |
c457f751 | 673 | if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) |
9304f876 CJW |
674 | { |
675 | /* Compute pushed size of callee-saved registers. */ | |
c457f751 CJW |
676 | cfun->machine->callee_saved_gpr_regs_size |
677 | = 4 * (cfun->machine->callee_saved_last_gpr_regno | |
678 | - cfun->machine->callee_saved_first_gpr_regno | |
9304f876 CJW |
679 | + 1); |
680 | } | |
681 | ||
e2286268 MC |
682 | if (TARGET_HARD_FLOAT) |
683 | { | |
684 | /* Compute size of callee svaed floating-point registers. */ | |
685 | if (cfun->machine->callee_saved_last_fpr_regno != SP_REGNUM) | |
686 | { | |
687 | cfun->machine->callee_saved_fpr_regs_size | |
688 | = 4 * (cfun->machine->callee_saved_last_fpr_regno | |
689 | - cfun->machine->callee_saved_first_fpr_regno | |
690 | + 1); | |
691 | } | |
692 | } | |
693 | ||
9304f876 | 694 | /* Important: We need to make sure that |
8a498f99 CJW |
695 | (fp_size + gp_size + lp_size + callee_saved_gpr_regs_size) |
696 | is 8-byte alignment. | |
697 | If it is not, calculate the padding bytes. */ | |
35da54a6 | 698 | block_size = cfun->machine->fp_size |
9304f876 CJW |
699 | + cfun->machine->gp_size |
700 | + cfun->machine->lp_size | |
c457f751 | 701 | + cfun->machine->callee_saved_gpr_regs_size; |
9304f876 CJW |
702 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) |
703 | { | |
c457f751 | 704 | cfun->machine->callee_saved_area_gpr_padding_bytes |
9304f876 CJW |
705 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; |
706 | } | |
707 | ||
708 | /* If stack usage computation is required, | |
709 | we need to provide the static stack size. */ | |
710 | if (flag_stack_usage_info) | |
711 | { | |
712 | current_function_static_stack_size | |
713 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) | |
714 | + cfun->machine->local_size | |
715 | + cfun->machine->out_args_size; | |
716 | } | |
717 | } | |
718 | ||
719 | /* Function to create a parallel rtx pattern | |
720 | which presents stack push multiple behavior. | |
721 | The overall concept are: | |
722 | "push registers to memory", | |
723 | "adjust stack pointer". */ | |
4e9a2848 | 724 | static void |
a6c7e777 MC |
725 | nds32_emit_stack_push_multiple (unsigned Rb, unsigned Re, |
726 | bool save_fp_p, bool save_gp_p, bool save_lp_p, | |
727 | bool vaarg_p) | |
9304f876 | 728 | { |
a6c7e777 | 729 | unsigned regno; |
9304f876 CJW |
730 | int extra_count; |
731 | int num_use_regs; | |
732 | int par_index; | |
733 | int offset; | |
734 | ||
735 | rtx reg; | |
736 | rtx mem; | |
737 | rtx push_rtx; | |
738 | rtx adjust_sp_rtx; | |
739 | rtx parallel_insn; | |
47e0e7d2 | 740 | rtx dwarf; |
9304f876 CJW |
741 | |
742 | /* We need to provide a customized rtx which contains | |
743 | necessary information for data analysis, | |
744 | so we create a parallel rtx like this: | |
745 | (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) | |
8a498f99 CJW |
746 | (reg:SI Rb)) |
747 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) | |
748 | (reg:SI Rb+1)) | |
749 | ... | |
750 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) | |
751 | (reg:SI Re)) | |
752 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) | |
753 | (reg:SI FP_REGNUM)) | |
754 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) | |
755 | (reg:SI GP_REGNUM)) | |
756 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) | |
757 | (reg:SI LP_REGNUM)) | |
758 | (set (reg:SI SP_REGNUM) | |
759 | (plus (reg:SI SP_REGNUM) (const_int -32)))]) */ | |
9304f876 CJW |
760 | |
761 | /* Calculate the number of registers that will be pushed. */ | |
762 | extra_count = 0; | |
a6c7e777 | 763 | if (save_fp_p) |
9304f876 | 764 | extra_count++; |
a6c7e777 | 765 | if (save_gp_p) |
9304f876 | 766 | extra_count++; |
a6c7e777 | 767 | if (save_lp_p) |
9304f876 CJW |
768 | extra_count++; |
769 | /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ | |
a6c7e777 | 770 | if (Rb == SP_REGNUM && Re == SP_REGNUM) |
9304f876 CJW |
771 | num_use_regs = extra_count; |
772 | else | |
a6c7e777 | 773 | num_use_regs = Re - Rb + 1 + extra_count; |
9304f876 CJW |
774 | |
775 | /* In addition to used registers, | |
776 | we need one more space for (set sp sp-x) rtx. */ | |
777 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
778 | rtvec_alloc (num_use_regs + 1)); | |
779 | par_index = 0; | |
780 | ||
781 | /* Initialize offset and start to create push behavior. */ | |
782 | offset = -(num_use_regs * 4); | |
783 | ||
784 | /* Create (set mem regX) from Rb, Rb+1 up to Re. */ | |
a6c7e777 | 785 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
786 | { |
787 | /* Rb and Re may be SP_REGNUM. | |
8a498f99 | 788 | We need to break this loop immediately. */ |
9304f876 | 789 | if (regno == SP_REGNUM) |
4e9a2848 | 790 | break; |
9304f876 CJW |
791 | |
792 | reg = gen_rtx_REG (SImode, regno); | |
793 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
794 | stack_pointer_rtx, | |
795 | offset)); | |
f7df4a84 | 796 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
797 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
798 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
799 | offset = offset + 4; | |
800 | par_index++; | |
801 | } | |
802 | ||
803 | /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */ | |
a6c7e777 | 804 | if (save_fp_p) |
9304f876 CJW |
805 | { |
806 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
807 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
808 | stack_pointer_rtx, | |
809 | offset)); | |
f7df4a84 | 810 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
811 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
812 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
813 | offset = offset + 4; | |
814 | par_index++; | |
815 | } | |
a6c7e777 | 816 | if (save_gp_p) |
9304f876 CJW |
817 | { |
818 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
819 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
820 | stack_pointer_rtx, | |
821 | offset)); | |
f7df4a84 | 822 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
823 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
824 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
825 | offset = offset + 4; | |
826 | par_index++; | |
827 | } | |
a6c7e777 | 828 | if (save_lp_p) |
9304f876 CJW |
829 | { |
830 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
831 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
832 | stack_pointer_rtx, | |
833 | offset)); | |
f7df4a84 | 834 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
835 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
836 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
837 | offset = offset + 4; | |
838 | par_index++; | |
839 | } | |
840 | ||
841 | /* Create (set sp sp-x). */ | |
842 | ||
843 | /* We need to re-calculate the offset value again for adjustment. */ | |
844 | offset = -(num_use_regs * 4); | |
845 | adjust_sp_rtx | |
f7df4a84 | 846 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
847 | plus_constant (Pmode, stack_pointer_rtx, offset)); |
848 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
849 | RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; | |
850 | ||
4e9a2848 CJW |
851 | parallel_insn = emit_insn (parallel_insn); |
852 | ||
853 | /* The insn rtx 'parallel_insn' will change frame layout. | |
854 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
855 | generate CFI (Call Frame Information) stuff. */ | |
856 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
47e0e7d2 CJW |
857 | |
858 | /* Don't use GCC's logic for CFI info if we are generate a push for VAARG | |
859 | since we will not restore those register at epilogue. */ | |
860 | if (vaarg_p) | |
861 | { | |
862 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, | |
863 | copy_rtx (adjust_sp_rtx), NULL_RTX); | |
864 | REG_NOTES (parallel_insn) = dwarf; | |
865 | } | |
9304f876 CJW |
866 | } |
867 | ||
868 | /* Function to create a parallel rtx pattern | |
869 | which presents stack pop multiple behavior. | |
870 | The overall concept are: | |
871 | "pop registers from memory", | |
872 | "adjust stack pointer". */ | |
4e9a2848 | 873 | static void |
a6c7e777 MC |
874 | nds32_emit_stack_pop_multiple (unsigned Rb, unsigned Re, |
875 | bool save_fp_p, bool save_gp_p, bool save_lp_p) | |
9304f876 | 876 | { |
a6c7e777 | 877 | unsigned regno; |
9304f876 CJW |
878 | int extra_count; |
879 | int num_use_regs; | |
880 | int par_index; | |
881 | int offset; | |
882 | ||
883 | rtx reg; | |
884 | rtx mem; | |
885 | rtx pop_rtx; | |
886 | rtx adjust_sp_rtx; | |
887 | rtx parallel_insn; | |
4e9a2848 | 888 | rtx dwarf = NULL_RTX; |
9304f876 CJW |
889 | |
890 | /* We need to provide a customized rtx which contains | |
891 | necessary information for data analysis, | |
892 | so we create a parallel rtx like this: | |
893 | (parallel [(set (reg:SI Rb) | |
8a498f99 CJW |
894 | (mem (reg:SI SP_REGNUM))) |
895 | (set (reg:SI Rb+1) | |
896 | (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) | |
897 | ... | |
898 | (set (reg:SI Re) | |
899 | (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) | |
900 | (set (reg:SI FP_REGNUM) | |
901 | (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) | |
902 | (set (reg:SI GP_REGNUM) | |
903 | (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) | |
904 | (set (reg:SI LP_REGNUM) | |
905 | (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) | |
906 | (set (reg:SI SP_REGNUM) | |
907 | (plus (reg:SI SP_REGNUM) (const_int 32)))]) */ | |
9304f876 CJW |
908 | |
909 | /* Calculate the number of registers that will be poped. */ | |
910 | extra_count = 0; | |
a6c7e777 | 911 | if (save_fp_p) |
9304f876 | 912 | extra_count++; |
a6c7e777 | 913 | if (save_gp_p) |
9304f876 | 914 | extra_count++; |
a6c7e777 | 915 | if (save_lp_p) |
9304f876 CJW |
916 | extra_count++; |
917 | /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ | |
a6c7e777 | 918 | if (Rb == SP_REGNUM && Re == SP_REGNUM) |
9304f876 CJW |
919 | num_use_regs = extra_count; |
920 | else | |
a6c7e777 | 921 | num_use_regs = Re - Rb + 1 + extra_count; |
9304f876 CJW |
922 | |
923 | /* In addition to used registers, | |
924 | we need one more space for (set sp sp+x) rtx. */ | |
925 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
926 | rtvec_alloc (num_use_regs + 1)); | |
927 | par_index = 0; | |
928 | ||
929 | /* Initialize offset and start to create pop behavior. */ | |
930 | offset = 0; | |
931 | ||
932 | /* Create (set regX mem) from Rb, Rb+1 up to Re. */ | |
a6c7e777 | 933 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
934 | { |
935 | /* Rb and Re may be SP_REGNUM. | |
8a498f99 | 936 | We need to break this loop immediately. */ |
9304f876 | 937 | if (regno == SP_REGNUM) |
4e9a2848 | 938 | break; |
9304f876 CJW |
939 | |
940 | reg = gen_rtx_REG (SImode, regno); | |
941 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
942 | stack_pointer_rtx, | |
943 | offset)); | |
f7df4a84 | 944 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
945 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
946 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
947 | offset = offset + 4; | |
948 | par_index++; | |
4e9a2848 CJW |
949 | |
950 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
951 | } |
952 | ||
953 | /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */ | |
a6c7e777 | 954 | if (save_fp_p) |
9304f876 CJW |
955 | { |
956 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
957 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
958 | stack_pointer_rtx, | |
959 | offset)); | |
f7df4a84 | 960 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
961 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
962 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
963 | offset = offset + 4; | |
964 | par_index++; | |
4e9a2848 CJW |
965 | |
966 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 | 967 | } |
a6c7e777 | 968 | if (save_gp_p) |
9304f876 CJW |
969 | { |
970 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
971 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
972 | stack_pointer_rtx, | |
973 | offset)); | |
f7df4a84 | 974 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
975 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
976 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
977 | offset = offset + 4; | |
978 | par_index++; | |
4e9a2848 CJW |
979 | |
980 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 | 981 | } |
a6c7e777 | 982 | if (save_lp_p) |
9304f876 CJW |
983 | { |
984 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
985 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
986 | stack_pointer_rtx, | |
987 | offset)); | |
f7df4a84 | 988 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
989 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
990 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
991 | offset = offset + 4; | |
992 | par_index++; | |
4e9a2848 CJW |
993 | |
994 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
995 | } |
996 | ||
997 | /* Create (set sp sp+x). */ | |
998 | ||
999 | /* The offset value is already in place. No need to re-calculate it. */ | |
1000 | adjust_sp_rtx | |
f7df4a84 | 1001 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
1002 | plus_constant (Pmode, stack_pointer_rtx, offset)); |
1003 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
9304f876 | 1004 | |
4e9a2848 CJW |
1005 | /* Tell gcc we adjust SP in this insn. */ |
1006 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, copy_rtx (adjust_sp_rtx), dwarf); | |
1007 | ||
1008 | parallel_insn = emit_insn (parallel_insn); | |
1009 | ||
1010 | /* The insn rtx 'parallel_insn' will change frame layout. | |
1011 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1012 | generate CFI (Call Frame Information) stuff. */ | |
1013 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
1014 | ||
1015 | /* Add CFI info by manual. */ | |
1016 | REG_NOTES (parallel_insn) = dwarf; | |
9304f876 CJW |
1017 | } |
1018 | ||
1019 | /* Function to create a parallel rtx pattern | |
1020 | which presents stack v3push behavior. | |
1021 | The overall concept are: | |
1022 | "push registers to memory", | |
1023 | "adjust stack pointer". */ | |
88437f39 | 1024 | static void |
a6c7e777 MC |
1025 | nds32_emit_stack_v3push (unsigned Rb, |
1026 | unsigned Re, | |
1027 | unsigned imm8u) | |
9304f876 | 1028 | { |
a6c7e777 | 1029 | unsigned regno; |
9304f876 CJW |
1030 | int num_use_regs; |
1031 | int par_index; | |
1032 | int offset; | |
1033 | ||
1034 | rtx reg; | |
1035 | rtx mem; | |
1036 | rtx push_rtx; | |
1037 | rtx adjust_sp_rtx; | |
1038 | rtx parallel_insn; | |
1039 | ||
1040 | /* We need to provide a customized rtx which contains | |
1041 | necessary information for data analysis, | |
1042 | so we create a parallel rtx like this: | |
88437f39 | 1043 | (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) |
8a498f99 CJW |
1044 | (reg:SI Rb)) |
1045 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) | |
1046 | (reg:SI Rb+1)) | |
1047 | ... | |
1048 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) | |
1049 | (reg:SI Re)) | |
1050 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) | |
1051 | (reg:SI FP_REGNUM)) | |
1052 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) | |
1053 | (reg:SI GP_REGNUM)) | |
1054 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) | |
1055 | (reg:SI LP_REGNUM)) | |
1056 | (set (reg:SI SP_REGNUM) | |
1057 | (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */ | |
9304f876 CJW |
1058 | |
1059 | /* Calculate the number of registers that will be pushed. | |
1060 | Since $fp, $gp, and $lp is always pushed with v3push instruction, | |
1061 | we need to count these three registers. | |
1062 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1063 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1064 | num_use_regs = Re - Rb + 1 + 3; |
9304f876 CJW |
1065 | |
1066 | /* In addition to used registers, | |
1067 | we need one more space for (set sp sp-x-imm8u) rtx. */ | |
1068 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
1069 | rtvec_alloc (num_use_regs + 1)); | |
1070 | par_index = 0; | |
1071 | ||
1072 | /* Initialize offset and start to create push behavior. */ | |
1073 | offset = -(num_use_regs * 4); | |
1074 | ||
1075 | /* Create (set mem regX) from Rb, Rb+1 up to Re. | |
1076 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1077 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1078 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
1079 | { |
1080 | reg = gen_rtx_REG (SImode, regno); | |
1081 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1082 | stack_pointer_rtx, | |
1083 | offset)); | |
f7df4a84 | 1084 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1085 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1086 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1087 | offset = offset + 4; | |
1088 | par_index++; | |
1089 | } | |
1090 | ||
1091 | /* Create (set mem fp). */ | |
1092 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
1093 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1094 | stack_pointer_rtx, | |
1095 | offset)); | |
f7df4a84 | 1096 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1097 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1098 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1099 | offset = offset + 4; | |
1100 | par_index++; | |
1101 | /* Create (set mem gp). */ | |
1102 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
1103 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1104 | stack_pointer_rtx, | |
1105 | offset)); | |
f7df4a84 | 1106 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1107 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1108 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1109 | offset = offset + 4; | |
1110 | par_index++; | |
1111 | /* Create (set mem lp). */ | |
1112 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
1113 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1114 | stack_pointer_rtx, | |
1115 | offset)); | |
f7df4a84 | 1116 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
1117 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
1118 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
1119 | offset = offset + 4; | |
1120 | par_index++; | |
1121 | ||
1122 | /* Create (set sp sp-x-imm8u). */ | |
1123 | ||
1124 | /* We need to re-calculate the offset value again for adjustment. */ | |
1125 | offset = -(num_use_regs * 4); | |
1126 | adjust_sp_rtx | |
f7df4a84 | 1127 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
1128 | plus_constant (Pmode, |
1129 | stack_pointer_rtx, | |
a6c7e777 | 1130 | offset - imm8u)); |
9304f876 CJW |
1131 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; |
1132 | RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; | |
1133 | ||
88437f39 CJW |
1134 | parallel_insn = emit_insn (parallel_insn); |
1135 | ||
1136 | /* The insn rtx 'parallel_insn' will change frame layout. | |
1137 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1138 | generate CFI (Call Frame Information) stuff. */ | |
1139 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
9304f876 CJW |
1140 | } |
1141 | ||
1142 | /* Function to create a parallel rtx pattern | |
1143 | which presents stack v3pop behavior. | |
1144 | The overall concept are: | |
1145 | "pop registers from memory", | |
1146 | "adjust stack pointer". */ | |
88437f39 | 1147 | static void |
a6c7e777 MC |
1148 | nds32_emit_stack_v3pop (unsigned Rb, |
1149 | unsigned Re, | |
1150 | unsigned imm8u) | |
9304f876 | 1151 | { |
a6c7e777 | 1152 | unsigned regno; |
9304f876 CJW |
1153 | int num_use_regs; |
1154 | int par_index; | |
1155 | int offset; | |
1156 | ||
1157 | rtx reg; | |
1158 | rtx mem; | |
1159 | rtx pop_rtx; | |
1160 | rtx adjust_sp_rtx; | |
1161 | rtx parallel_insn; | |
88437f39 | 1162 | rtx dwarf = NULL_RTX; |
9304f876 CJW |
1163 | |
1164 | /* We need to provide a customized rtx which contains | |
1165 | necessary information for data analysis, | |
1166 | so we create a parallel rtx like this: | |
1167 | (parallel [(set (reg:SI Rb) | |
8a498f99 CJW |
1168 | (mem (reg:SI SP_REGNUM))) |
1169 | (set (reg:SI Rb+1) | |
1170 | (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) | |
1171 | ... | |
1172 | (set (reg:SI Re) | |
1173 | (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) | |
1174 | (set (reg:SI FP_REGNUM) | |
1175 | (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) | |
1176 | (set (reg:SI GP_REGNUM) | |
1177 | (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) | |
1178 | (set (reg:SI LP_REGNUM) | |
1179 | (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) | |
1180 | (set (reg:SI SP_REGNUM) | |
1181 | (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */ | |
9304f876 CJW |
1182 | |
1183 | /* Calculate the number of registers that will be poped. | |
1184 | Since $fp, $gp, and $lp is always poped with v3pop instruction, | |
1185 | we need to count these three registers. | |
1186 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1187 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1188 | num_use_regs = Re - Rb + 1 + 3; |
9304f876 CJW |
1189 | |
1190 | /* In addition to used registers, | |
1191 | we need one more space for (set sp sp+x+imm8u) rtx. */ | |
1192 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
1193 | rtvec_alloc (num_use_regs + 1)); | |
1194 | par_index = 0; | |
1195 | ||
1196 | /* Initialize offset and start to create pop behavior. */ | |
1197 | offset = 0; | |
1198 | ||
1199 | /* Create (set regX mem) from Rb, Rb+1 up to Re. | |
1200 | Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
1201 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
a6c7e777 | 1202 | for (regno = Rb; regno <= Re; regno++) |
9304f876 CJW |
1203 | { |
1204 | reg = gen_rtx_REG (SImode, regno); | |
1205 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1206 | stack_pointer_rtx, | |
1207 | offset)); | |
f7df4a84 | 1208 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1209 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1210 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1211 | offset = offset + 4; | |
1212 | par_index++; | |
88437f39 CJW |
1213 | |
1214 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
1215 | } |
1216 | ||
1217 | /* Create (set fp mem). */ | |
1218 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
1219 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1220 | stack_pointer_rtx, | |
1221 | offset)); | |
f7df4a84 | 1222 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1223 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1224 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1225 | offset = offset + 4; | |
1226 | par_index++; | |
88437f39 CJW |
1227 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
1228 | ||
9304f876 CJW |
1229 | /* Create (set gp mem). */ |
1230 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
1231 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1232 | stack_pointer_rtx, | |
1233 | offset)); | |
f7df4a84 | 1234 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1235 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1236 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1237 | offset = offset + 4; | |
1238 | par_index++; | |
88437f39 CJW |
1239 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
1240 | ||
9304f876 CJW |
1241 | /* Create (set lp mem ). */ |
1242 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
1243 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
1244 | stack_pointer_rtx, | |
1245 | offset)); | |
f7df4a84 | 1246 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
1247 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
1248 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
1249 | offset = offset + 4; | |
1250 | par_index++; | |
88437f39 | 1251 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
9304f876 CJW |
1252 | |
1253 | /* Create (set sp sp+x+imm8u). */ | |
1254 | ||
1255 | /* The offset value is already in place. No need to re-calculate it. */ | |
1256 | adjust_sp_rtx | |
f7df4a84 | 1257 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
1258 | plus_constant (Pmode, |
1259 | stack_pointer_rtx, | |
a6c7e777 | 1260 | offset + imm8u)); |
9304f876 | 1261 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; |
9304f876 | 1262 | |
a6c7e777 MC |
1263 | if (frame_pointer_needed) |
1264 | { | |
1265 | /* (expr_list:REG_CFA_DEF_CFA (plus:SI (reg/f:SI $sp) | |
1266 | (const_int 0)) | |
1267 | mean reset frame pointer to $sp and reset to offset 0. */ | |
1268 | rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
1269 | const0_rtx); | |
1270 | dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); | |
1271 | } | |
1272 | else | |
1273 | { | |
1274 | /* Tell gcc we adjust SP in this insn. */ | |
1275 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, | |
1276 | copy_rtx (adjust_sp_rtx), dwarf); | |
1277 | } | |
88437f39 CJW |
1278 | |
1279 | parallel_insn = emit_insn (parallel_insn); | |
1280 | ||
1281 | /* The insn rtx 'parallel_insn' will change frame layout. | |
1282 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1283 | generate CFI (Call Frame Information) stuff. */ | |
1284 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
1285 | ||
1286 | /* Add CFI info by manual. */ | |
1287 | REG_NOTES (parallel_insn) = dwarf; | |
9304f876 CJW |
1288 | } |
1289 | ||
b26fa4f9 KLC |
1290 | static void |
1291 | nds32_emit_load_gp (void) | |
1292 | { | |
1293 | rtx got_symbol, pat; | |
1294 | ||
1295 | /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ | |
1296 | emit_insn (gen_blockage ()); | |
1297 | ||
1298 | got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
1299 | /* sethi $gp, _GLOBAL_OFFSET_TABLE_ -8 */ | |
1300 | pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); | |
1301 | pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-8))); | |
1302 | emit_insn (gen_sethi (pic_offset_table_rtx,pat)); | |
1303 | ||
1304 | /* ori $gp, $gp, _GLOBAL_OFFSET_TABLE_ -4 */ | |
1305 | pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); | |
1306 | pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-4))); | |
1307 | emit_insn (gen_lo_sum (pic_offset_table_rtx, pic_offset_table_rtx, pat)); | |
1308 | ||
1309 | /* add5.pc $gp */ | |
1310 | emit_insn (gen_add_pc (pic_offset_table_rtx, pic_offset_table_rtx)); | |
1311 | ||
1312 | /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ | |
1313 | emit_insn (gen_blockage ()); | |
1314 | } | |
1315 | ||
9304f876 CJW |
1316 | /* Function that may creates more instructions |
1317 | for large value on adjusting stack pointer. | |
1318 | ||
1319 | In nds32 target, 'addi' can be used for stack pointer | |
1320 | adjustment in prologue/epilogue stage. | |
1321 | However, sometimes there are too many local variables so that | |
1322 | the adjustment value is not able to be fit in the 'addi' instruction. | |
1323 | One solution is to move value into a register | |
1324 | and then use 'add' instruction. | |
a6c7e777 MC |
1325 | In practice, we use TA_REGNUM ($r15) to accomplish this purpose. */ |
1326 | static void | |
1327 | nds32_emit_adjust_frame (rtx to_reg, rtx from_reg, int adjust_value) | |
9304f876 | 1328 | { |
9304f876 | 1329 | rtx tmp_reg; |
a6c7e777 MC |
1330 | rtx frame_adjust_insn; |
1331 | rtx adjust_value_rtx = GEN_INT (adjust_value); | |
9304f876 | 1332 | |
a6c7e777 MC |
1333 | if (adjust_value == 0) |
1334 | return; | |
1335 | ||
1336 | if (!satisfies_constraint_Is15 (adjust_value_rtx)) | |
9304f876 CJW |
1337 | { |
1338 | /* The value is not able to fit in single addi instruction. | |
8a498f99 CJW |
1339 | Create more instructions of moving value into a register |
1340 | and then add stack pointer with it. */ | |
9304f876 CJW |
1341 | |
1342 | /* $r15 is going to be temporary register to hold the value. */ | |
1343 | tmp_reg = gen_rtx_REG (SImode, TA_REGNUM); | |
1344 | ||
1345 | /* Create one more instruction to move value | |
8a498f99 | 1346 | into the temporary register. */ |
a6c7e777 | 1347 | emit_move_insn (tmp_reg, adjust_value_rtx); |
9304f876 CJW |
1348 | |
1349 | /* Create new 'add' rtx. */ | |
a6c7e777 MC |
1350 | frame_adjust_insn = gen_addsi3 (to_reg, |
1351 | from_reg, | |
1352 | tmp_reg); | |
9304f876 | 1353 | /* Emit rtx into insn list and receive its transformed insn rtx. */ |
a6c7e777 | 1354 | frame_adjust_insn = emit_insn (frame_adjust_insn); |
9304f876 | 1355 | |
a6c7e777 MC |
1356 | /* Because (tmp_reg <- full_value) may be split into two |
1357 | rtl patterns, we can not set its RTX_FRAME_RELATED_P. | |
1358 | We need to construct another (sp <- sp + full_value) | |
1359 | and then insert it into sp_adjust_insn's reg note to | |
1360 | represent a frame related expression. | |
1361 | GCC knows how to refer it and output debug information. */ | |
9304f876 | 1362 | |
a6c7e777 MC |
1363 | rtx plus_rtx; |
1364 | rtx set_rtx; | |
9304f876 | 1365 | |
a6c7e777 MC |
1366 | plus_rtx = plus_constant (Pmode, from_reg, adjust_value); |
1367 | set_rtx = gen_rtx_SET (to_reg, plus_rtx); | |
1368 | add_reg_note (frame_adjust_insn, REG_FRAME_RELATED_EXPR, set_rtx); | |
9304f876 CJW |
1369 | } |
1370 | else | |
1371 | { | |
a6c7e777 MC |
1372 | /* Generate sp adjustment instruction if and only if sp_adjust != 0. */ |
1373 | frame_adjust_insn = gen_addsi3 (to_reg, | |
1374 | from_reg, | |
1375 | adjust_value_rtx); | |
1376 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
1377 | frame_adjust_insn = emit_insn (frame_adjust_insn); | |
9304f876 | 1378 | } |
a6c7e777 MC |
1379 | |
1380 | /* The insn rtx 'sp_adjust_insn' will change frame layout. | |
1381 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
1382 | generate CFI (Call Frame Information) stuff. */ | |
1383 | RTX_FRAME_RELATED_P (frame_adjust_insn) = 1; | |
9304f876 CJW |
1384 | } |
1385 | ||
1386 | /* Return true if MODE/TYPE need double word alignment. */ | |
1387 | static bool | |
ef4bddc2 | 1388 | nds32_needs_double_word_align (machine_mode mode, const_tree type) |
9304f876 CJW |
1389 | { |
1390 | unsigned int align; | |
1391 | ||
634bdae9 CJW |
1392 | /* Pick up the alignment according to the mode or type. */ |
1393 | align = NDS32_MODE_TYPE_ALIGN (mode, type); | |
9304f876 CJW |
1394 | |
1395 | return (align > PARM_BOUNDARY); | |
1396 | } | |
1397 | ||
1398 | /* Return true if FUNC is a naked function. */ | |
2140297c | 1399 | bool |
810f736f | 1400 | nds32_naked_function_p (tree func) |
9304f876 | 1401 | { |
54c537e6 CJW |
1402 | /* FOR BACKWARD COMPATIBILITY, |
1403 | we need to support 'no_prologue' attribute as well. */ | |
1404 | tree t_naked; | |
1405 | tree t_no_prologue; | |
9304f876 CJW |
1406 | |
1407 | if (TREE_CODE (func) != FUNCTION_DECL) | |
1408 | abort (); | |
1409 | ||
54c537e6 CJW |
1410 | /* We have to use lookup_attribute() to check attributes. |
1411 | Because attr_naked_p and attr_no_prologue_p are set in | |
1412 | nds32_compute_stack_frame() and the function has not been | |
1413 | invoked yet. */ | |
1414 | t_naked = lookup_attribute ("naked", DECL_ATTRIBUTES (func)); | |
1415 | t_no_prologue = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (func)); | |
9304f876 | 1416 | |
54c537e6 | 1417 | return ((t_naked != NULL_TREE) || (t_no_prologue != NULL_TREE)); |
9304f876 CJW |
1418 | } |
1419 | ||
c411e9aa SC |
1420 | /* Function that determine whether a load postincrement is a good thing to use |
1421 | for a given mode. */ | |
1422 | bool | |
1423 | nds32_use_load_post_increment (machine_mode mode) | |
1424 | { | |
1425 | return (GET_MODE_SIZE (mode) <= GET_MODE_SIZE(E_DImode)); | |
1426 | } | |
1427 | ||
9304f876 CJW |
1428 | /* Function that check if 'X' is a valid address register. |
1429 | The variable 'STRICT' is very important to | |
1430 | make decision for register number. | |
1431 | ||
1432 | STRICT : true | |
1433 | => We are in reload pass or after reload pass. | |
8a498f99 | 1434 | The register number should be strictly limited in general registers. |
9304f876 CJW |
1435 | |
1436 | STRICT : false | |
1437 | => Before reload pass, we are free to use any register number. */ | |
1438 | static bool | |
1439 | nds32_address_register_rtx_p (rtx x, bool strict) | |
1440 | { | |
1441 | int regno; | |
1442 | ||
1443 | if (GET_CODE (x) != REG) | |
1444 | return false; | |
1445 | ||
1446 | regno = REGNO (x); | |
1447 | ||
1448 | if (strict) | |
1449 | return REGNO_OK_FOR_BASE_P (regno); | |
1450 | else | |
1451 | return true; | |
1452 | } | |
1453 | ||
1454 | /* Function that check if 'INDEX' is valid to be a index rtx for address. | |
1455 | ||
1456 | OUTER_MODE : Machine mode of outer address rtx. | |
8a498f99 | 1457 | INDEX : Check if this rtx is valid to be a index for address. |
9304f876 CJW |
1458 | STRICT : If it is true, we are in reload pass or after reload pass. */ |
1459 | static bool | |
ef4bddc2 | 1460 | nds32_legitimate_index_p (machine_mode outer_mode, |
9304f876 CJW |
1461 | rtx index, |
1462 | bool strict) | |
1463 | { | |
1464 | int regno; | |
1465 | rtx op0; | |
1466 | rtx op1; | |
1467 | ||
1468 | switch (GET_CODE (index)) | |
1469 | { | |
1470 | case REG: | |
1471 | regno = REGNO (index); | |
1472 | /* If we are in reload pass or after reload pass, | |
8a498f99 | 1473 | we need to limit it to general register. */ |
9304f876 CJW |
1474 | if (strict) |
1475 | return REGNO_OK_FOR_INDEX_P (regno); | |
1476 | else | |
1477 | return true; | |
1478 | ||
1479 | case CONST_INT: | |
1480 | /* The alignment of the integer value is determined by 'outer_mode'. */ | |
e2286268 | 1481 | switch (GET_MODE_SIZE (outer_mode)) |
9304f876 | 1482 | { |
e2286268 | 1483 | case 1: |
9304f876 | 1484 | /* Further check if the value is legal for the 'outer_mode'. */ |
e2286268 MC |
1485 | if (satisfies_constraint_Is15 (index)) |
1486 | return true; | |
1487 | break; | |
9304f876 | 1488 | |
e2286268 | 1489 | case 2: |
9304f876 | 1490 | /* Further check if the value is legal for the 'outer_mode'. */ |
e2286268 MC |
1491 | if (satisfies_constraint_Is16 (index)) |
1492 | { | |
5f2a98c3 CJW |
1493 | /* If it is not under strictly aligned situation, |
1494 | we can return true without checking alignment. */ | |
1495 | if (!cfun->machine->strict_aligned_p) | |
1496 | return true; | |
e2286268 | 1497 | /* Make sure address is half word alignment. */ |
5f2a98c3 | 1498 | else if (NDS32_HALF_WORD_ALIGN_P (INTVAL (index))) |
e2286268 MC |
1499 | return true; |
1500 | } | |
1501 | break; | |
9304f876 | 1502 | |
e2286268 | 1503 | case 4: |
9304f876 | 1504 | /* Further check if the value is legal for the 'outer_mode'. */ |
e2286268 MC |
1505 | if (satisfies_constraint_Is17 (index)) |
1506 | { | |
1507 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) | |
1508 | { | |
1509 | if (!satisfies_constraint_Is14 (index)) | |
1510 | return false; | |
1511 | } | |
1512 | ||
5f2a98c3 CJW |
1513 | /* If it is not under strictly aligned situation, |
1514 | we can return true without checking alignment. */ | |
1515 | if (!cfun->machine->strict_aligned_p) | |
1516 | return true; | |
e2286268 | 1517 | /* Make sure address is word alignment. */ |
5f2a98c3 | 1518 | else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) |
e2286268 MC |
1519 | return true; |
1520 | } | |
1521 | break; | |
9304f876 | 1522 | |
e2286268 MC |
1523 | case 8: |
1524 | if (satisfies_constraint_Is17 (gen_int_mode (INTVAL (index) + 4, | |
1525 | SImode))) | |
1526 | { | |
1527 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) | |
1528 | { | |
1529 | if (!satisfies_constraint_Is14 (index)) | |
1530 | return false; | |
1531 | } | |
1532 | ||
5f2a98c3 CJW |
1533 | /* If it is not under strictly aligned situation, |
1534 | we can return true without checking alignment. */ | |
1535 | if (!cfun->machine->strict_aligned_p) | |
1536 | return true; | |
e2286268 MC |
1537 | /* Make sure address is word alignment. |
1538 | Currently we do not have 64-bit load/store yet, | |
1539 | so we will use two 32-bit load/store instructions to do | |
1540 | memory access and they are single word alignment. */ | |
5f2a98c3 | 1541 | else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) |
e2286268 MC |
1542 | return true; |
1543 | } | |
1544 | break; | |
9304f876 | 1545 | |
e2286268 MC |
1546 | default: |
1547 | return false; | |
9304f876 CJW |
1548 | } |
1549 | ||
1550 | return false; | |
1551 | ||
1552 | case MULT: | |
1553 | op0 = XEXP (index, 0); | |
1554 | op1 = XEXP (index, 1); | |
1555 | ||
1556 | if (REG_P (op0) && CONST_INT_P (op1)) | |
1557 | { | |
1558 | int multiplier; | |
1559 | multiplier = INTVAL (op1); | |
1560 | ||
f62a2af5 CJW |
1561 | /* We only allow (mult reg const_int_1), (mult reg const_int_2), |
1562 | (mult reg const_int_4) or (mult reg const_int_8). */ | |
1563 | if (multiplier != 1 && multiplier != 2 | |
1564 | && multiplier != 4 && multiplier != 8) | |
9304f876 CJW |
1565 | return false; |
1566 | ||
1567 | regno = REGNO (op0); | |
1568 | /* Limit it in general registers if we are | |
1569 | in reload pass or after reload pass. */ | |
1570 | if(strict) | |
1571 | return REGNO_OK_FOR_INDEX_P (regno); | |
1572 | else | |
1573 | return true; | |
1574 | } | |
1575 | ||
1576 | return false; | |
1577 | ||
1578 | case ASHIFT: | |
1579 | op0 = XEXP (index, 0); | |
1580 | op1 = XEXP (index, 1); | |
1581 | ||
1582 | if (REG_P (op0) && CONST_INT_P (op1)) | |
1583 | { | |
1584 | int sv; | |
1585 | /* op1 is already the sv value for use to do left shift. */ | |
1586 | sv = INTVAL (op1); | |
1587 | ||
1588 | /* We only allow (ashift reg const_int_0) | |
f62a2af5 CJW |
1589 | or (ashift reg const_int_1) or (ashift reg const_int_2) or |
1590 | (ashift reg const_int_3). */ | |
1591 | if (sv != 0 && sv != 1 && sv !=2 && sv != 3) | |
9304f876 CJW |
1592 | return false; |
1593 | ||
1594 | regno = REGNO (op0); | |
1595 | /* Limit it in general registers if we are | |
1596 | in reload pass or after reload pass. */ | |
1597 | if(strict) | |
1598 | return REGNO_OK_FOR_INDEX_P (regno); | |
1599 | else | |
1600 | return true; | |
1601 | } | |
1602 | ||
1603 | return false; | |
1604 | ||
1605 | default: | |
1606 | return false; | |
1607 | } | |
1608 | } | |
1609 | ||
c4d8d050 CJW |
1610 | static void |
1611 | nds32_register_pass ( | |
1612 | rtl_opt_pass *(*make_pass_func) (gcc::context *), | |
1613 | enum pass_positioning_ops pass_pos, | |
1614 | const char *ref_pass_name) | |
1615 | { | |
1616 | opt_pass *new_opt_pass = make_pass_func (g); | |
1617 | ||
1618 | struct register_pass_info insert_pass = | |
1619 | { | |
1620 | new_opt_pass, /* pass */ | |
1621 | ref_pass_name, /* reference_pass_name */ | |
1622 | 1, /* ref_pass_instance_number */ | |
1623 | pass_pos /* po_op */ | |
1624 | }; | |
1625 | ||
1626 | register_pass (&insert_pass); | |
1627 | } | |
1628 | ||
1629 | /* This function is called from nds32_option_override (). | |
1630 | All new passes should be registered here. */ | |
1631 | static void | |
1632 | nds32_register_passes (void) | |
1633 | { | |
2140297c CJW |
1634 | nds32_register_pass ( |
1635 | make_pass_nds32_fp_as_gp, | |
1636 | PASS_POS_INSERT_BEFORE, | |
1637 | "ira"); | |
1638 | ||
c4d8d050 CJW |
1639 | nds32_register_pass ( |
1640 | make_pass_nds32_relax_opt, | |
1641 | PASS_POS_INSERT_AFTER, | |
1642 | "mach"); | |
1643 | } | |
1644 | ||
9304f876 CJW |
1645 | /* ------------------------------------------------------------------------ */ |
1646 | ||
1647 | /* PART 3: Implement target hook stuff definitions. */ | |
e2286268 MC |
1648 | \f |
1649 | ||
a5876228 CJW |
1650 | /* Computing the Length of an Insn. |
1651 | Modifies the length assigned to instruction INSN. | |
1652 | LEN is the initially computed length of the insn. */ | |
1653 | int | |
1654 | nds32_adjust_insn_length (rtx_insn *insn, int length) | |
1655 | { | |
1656 | int adjust_value = 0; | |
1657 | switch (recog_memoized (insn)) | |
1658 | { | |
1659 | case CODE_FOR_call_internal: | |
1660 | case CODE_FOR_call_value_internal: | |
1661 | { | |
43fa41c1 CJW |
1662 | if (NDS32_ALIGN_P ()) |
1663 | { | |
1664 | rtx_insn *next_insn = next_active_insn (insn); | |
1665 | if (next_insn && get_attr_length (next_insn) != 2) | |
1666 | adjust_value += 2; | |
1667 | } | |
a5876228 CJW |
1668 | /* We need insert a nop after a noretun function call |
1669 | to prevent software breakpoint corrupt the next function. */ | |
1670 | if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
1671 | { | |
1672 | if (TARGET_16_BIT) | |
1673 | adjust_value += 2; | |
1674 | else | |
1675 | adjust_value += 4; | |
1676 | } | |
1677 | } | |
1678 | return length + adjust_value; | |
1679 | ||
1680 | default: | |
1681 | return length; | |
1682 | } | |
1683 | } | |
1684 | ||
5f2a98c3 CJW |
1685 | /* Storage Layout. */ |
1686 | ||
1687 | /* This function will be called just before expansion into rtl. */ | |
1688 | static void | |
1689 | nds32_expand_to_rtl_hook (void) | |
1690 | { | |
1691 | /* We need to set strictly aligned situation. | |
1692 | After that, the memory address checking in nds32_legitimate_address_p() | |
1693 | will take alignment offset into consideration so that it will not create | |
1694 | unaligned [base + offset] access during the rtl optimization. */ | |
1695 | cfun->machine->strict_aligned_p = 1; | |
1696 | } | |
1697 | ||
1698 | \f | |
e2286268 MC |
1699 | /* Register Usage. */ |
1700 | ||
1701 | static void | |
1702 | nds32_conditional_register_usage (void) | |
1703 | { | |
1704 | int regno; | |
1705 | ||
cf3cd43d CJW |
1706 | if (TARGET_LINUX_ABI) |
1707 | fixed_regs[TP_REGNUM] = 1; | |
1708 | ||
e2286268 MC |
1709 | if (TARGET_HARD_FLOAT) |
1710 | { | |
1711 | for (regno = NDS32_FIRST_FPR_REGNUM; | |
1712 | regno <= NDS32_LAST_FPR_REGNUM; regno++) | |
1713 | { | |
1714 | fixed_regs[regno] = 0; | |
1715 | if (regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS) | |
1716 | call_used_regs[regno] = 1; | |
1717 | else if (regno >= NDS32_FIRST_FPR_REGNUM + 22 | |
1718 | && regno < NDS32_FIRST_FPR_REGNUM + 48) | |
1719 | call_used_regs[regno] = 1; | |
1720 | else | |
1721 | call_used_regs[regno] = 0; | |
1722 | } | |
1723 | } | |
1724 | else if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
1725 | { | |
1726 | for (regno = NDS32_FIRST_FPR_REGNUM; | |
1727 | regno <= NDS32_LAST_FPR_REGNUM; | |
1728 | regno++) | |
1729 | fixed_regs[regno] = 0; | |
1730 | } | |
1731 | } | |
1732 | ||
9304f876 CJW |
1733 | \f |
1734 | /* Register Classes. */ | |
1735 | ||
1736 | static unsigned char | |
1737 | nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED, | |
ef4bddc2 | 1738 | machine_mode mode) |
9304f876 CJW |
1739 | { |
1740 | /* Return the maximum number of consecutive registers | |
1741 | needed to represent "mode" in a register of "rclass". */ | |
1742 | return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); | |
1743 | } | |
1744 | ||
1745 | static int | |
1746 | nds32_register_priority (int hard_regno) | |
1747 | { | |
1748 | /* Encourage to use r0-r7 for LRA when optimize for size. */ | |
6a5a7ee3 CJW |
1749 | if (optimize_size) |
1750 | { | |
1751 | if (hard_regno < 8) | |
1752 | return 4; | |
1753 | else if (hard_regno < 16) | |
1754 | return 3; | |
1755 | else if (hard_regno < 28) | |
1756 | return 2; | |
1757 | else | |
1758 | return 1; | |
1759 | } | |
1760 | else | |
1761 | { | |
1762 | if (hard_regno > 27) | |
1763 | return 1; | |
1764 | else | |
1765 | return 4; | |
1766 | } | |
9304f876 CJW |
1767 | } |
1768 | ||
e2286268 MC |
1769 | static bool |
1770 | nds32_can_change_mode_class (machine_mode from, | |
1771 | machine_mode to, | |
1772 | reg_class_t rclass) | |
1773 | { | |
1774 | /* Don't spill double-precision register to two singal-precision | |
1775 | registers */ | |
1776 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
1777 | && GET_MODE_SIZE (from) != GET_MODE_SIZE (to)) | |
1778 | { | |
1779 | return !reg_classes_intersect_p (rclass, FP_REGS); | |
1780 | } | |
1781 | ||
1782 | return true; | |
1783 | } | |
1784 | ||
9304f876 CJW |
1785 | \f |
1786 | /* Stack Layout and Calling Conventions. */ | |
1787 | ||
1788 | /* There are three kinds of pointer concepts using in GCC compiler: | |
1789 | ||
1790 | frame pointer: A pointer to the first location of local variables. | |
1791 | stack pointer: A pointer to the top of a stack frame. | |
1792 | argument pointer: A pointer to the incoming arguments. | |
1793 | ||
1794 | In nds32 target calling convention, we are using 8-byte alignment. | |
1795 | Besides, we would like to have each stack frame of a function includes: | |
1796 | ||
1797 | [Block A] | |
1798 | 1. previous hard frame pointer | |
1799 | 2. return address | |
1800 | 3. callee-saved registers | |
1801 | 4. <padding bytes> (we will calculte in nds32_compute_stack_frame() | |
8a498f99 CJW |
1802 | and save it at |
1803 | cfun->machine->callee_saved_area_padding_bytes) | |
9304f876 CJW |
1804 | |
1805 | [Block B] | |
1806 | 1. local variables | |
1807 | 2. spilling location | |
1808 | 3. <padding bytes> (it will be calculated by GCC itself) | |
1809 | 4. incoming arguments | |
1810 | 5. <padding bytes> (it will be calculated by GCC itself) | |
1811 | ||
1812 | [Block C] | |
1813 | 1. <padding bytes> (it will be calculated by GCC itself) | |
1814 | 2. outgoing arguments | |
1815 | ||
1816 | We 'wrap' these blocks together with | |
1817 | hard frame pointer ($r28) and stack pointer ($r31). | |
1818 | By applying the basic frame/stack/argument pointers concept, | |
1819 | the layout of a stack frame shoule be like this: | |
1820 | ||
8a498f99 | 1821 | | | |
9304f876 | 1822 | old stack pointer -> ---- |
8a498f99 CJW |
1823 | | | \ |
1824 | | | saved arguments for | |
1825 | | | vararg functions | |
1826 | | | / | |
9304f876 CJW |
1827 | hard frame pointer -> -- |
1828 | & argument pointer | | \ | |
8a498f99 CJW |
1829 | | | previous hardware frame pointer |
1830 | | | return address | |
1831 | | | callee-saved registers | |
1832 | | | / | |
1833 | frame pointer -> -- | |
1834 | | | \ | |
1835 | | | local variables | |
1836 | | | and incoming arguments | |
1837 | | | / | |
1838 | -- | |
1839 | | | \ | |
1840 | | | outgoing | |
1841 | | | arguments | |
1842 | | | / | |
1843 | stack pointer -> ---- | |
9304f876 CJW |
1844 | |
1845 | $SFP and $AP are used to represent frame pointer and arguments pointer, | |
1846 | which will be both eliminated as hard frame pointer. */ | |
1847 | ||
1848 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
1849 | ||
19ac960a CJW |
1850 | static bool |
1851 | nds32_can_eliminate (const int from_reg, const int to_reg) | |
9304f876 CJW |
1852 | { |
1853 | if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
1854 | return true; | |
1855 | ||
1856 | if (from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) | |
1857 | return true; | |
1858 | ||
1859 | if (from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
1860 | return true; | |
1861 | ||
1862 | if (from_reg == FRAME_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) | |
1863 | return true; | |
1864 | ||
1865 | return false; | |
1866 | } | |
1867 | ||
1868 | /* -- Passing Arguments in Registers. */ | |
1869 | ||
1870 | static rtx | |
ef4bddc2 | 1871 | nds32_function_arg (cumulative_args_t ca, machine_mode mode, |
9304f876 CJW |
1872 | const_tree type, bool named) |
1873 | { | |
7f6cd86b | 1874 | unsigned int regno; |
9304f876 CJW |
1875 | CUMULATIVE_ARGS *cum = get_cumulative_args (ca); |
1876 | ||
1877 | /* The last time this hook is called, | |
1878 | it is called with MODE == VOIDmode. */ | |
1879 | if (mode == VOIDmode) | |
1880 | return NULL_RTX; | |
1881 | ||
7f6cd86b | 1882 | /* For nameless arguments, we need to take care it individually. */ |
9304f876 | 1883 | if (!named) |
9304f876 | 1884 | { |
7f6cd86b | 1885 | /* If we are under hard float abi, we have arguments passed on the |
8a498f99 | 1886 | stack and all situation can be handled by GCC itself. */ |
7f6cd86b CJW |
1887 | if (TARGET_HARD_FLOAT) |
1888 | return NULL_RTX; | |
1889 | ||
1890 | if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) | |
1891 | { | |
1892 | /* If we still have enough registers to pass argument, pick up | |
1893 | next available register number. */ | |
1894 | regno | |
1895 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1896 | return gen_rtx_REG (mode, regno); | |
1897 | } | |
634bdae9 | 1898 | |
9304f876 | 1899 | /* No register available, return NULL_RTX. |
8a498f99 | 1900 | The compiler will use stack to pass argument instead. */ |
9304f876 CJW |
1901 | return NULL_RTX; |
1902 | } | |
7f6cd86b CJW |
1903 | |
1904 | /* The following is to handle named argument. | |
1905 | Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT | |
1906 | are different. */ | |
1907 | if (TARGET_HARD_FLOAT) | |
1908 | { | |
e2286268 MC |
1909 | /* For TARGET_HARD_FLOAT calling convention, we use GPR and FPR |
1910 | to pass argument. We have to further check TYPE and MODE so | |
1911 | that we can determine which kind of register we shall use. */ | |
1912 | ||
1913 | /* Note that we need to pass argument entirely in registers under | |
1914 | hard float abi. */ | |
1915 | if (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1916 | && NDS32_ARG_ENTIRE_IN_FPR_REG_P (cum->fpr_offset, mode, type)) | |
1917 | { | |
1918 | /* Pick up the next available FPR register number. */ | |
1919 | regno | |
1920 | = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type); | |
1921 | return gen_rtx_REG (mode, regno); | |
1922 | } | |
1923 | else if (GET_MODE_CLASS (mode) != MODE_FLOAT | |
1924 | && NDS32_ARG_ENTIRE_IN_GPR_REG_P (cum->gpr_offset, mode, type)) | |
1925 | { | |
1926 | /* Pick up the next available GPR register number. */ | |
1927 | regno | |
1928 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1929 | return gen_rtx_REG (mode, regno); | |
1930 | } | |
7f6cd86b CJW |
1931 | } |
1932 | else | |
1933 | { | |
1934 | /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass | |
8a498f99 CJW |
1935 | argument. Since we allow to pass argument partially in registers, |
1936 | we can just return it if there are still registers available. */ | |
7f6cd86b CJW |
1937 | if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) |
1938 | { | |
1939 | /* Pick up the next available register number. */ | |
1940 | regno | |
1941 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1942 | return gen_rtx_REG (mode, regno); | |
1943 | } | |
1944 | ||
1945 | } | |
1946 | ||
1947 | /* No register available, return NULL_RTX. | |
1948 | The compiler will use stack to pass argument instead. */ | |
1949 | return NULL_RTX; | |
9304f876 CJW |
1950 | } |
1951 | ||
d40f3c40 | 1952 | static bool |
ef4bddc2 | 1953 | nds32_must_pass_in_stack (machine_mode mode, const_tree type) |
d40f3c40 CJW |
1954 | { |
1955 | /* Return true if a type must be passed in memory. | |
1956 | If it is NOT using hard float abi, small aggregates can be | |
1957 | passed in a register even we are calling a variadic function. | |
1958 | So there is no need to take padding into consideration. */ | |
1959 | if (TARGET_HARD_FLOAT) | |
1960 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
1961 | else | |
1962 | return must_pass_in_stack_var_size (mode, type); | |
1963 | } | |
1964 | ||
650fc469 | 1965 | static int |
ef4bddc2 | 1966 | nds32_arg_partial_bytes (cumulative_args_t ca, machine_mode mode, |
650fc469 CJW |
1967 | tree type, bool named ATTRIBUTE_UNUSED) |
1968 | { | |
1969 | /* Returns the number of bytes at the beginning of an argument that | |
1970 | must be put in registers. The value must be zero for arguments that are | |
1971 | passed entirely in registers or that are entirely pushed on the stack. | |
1972 | Besides, TARGET_FUNCTION_ARG for these arguments should return the | |
1973 | first register to be used by the caller for this argument. */ | |
1974 | unsigned int needed_reg_count; | |
1975 | unsigned int remaining_reg_count; | |
1976 | CUMULATIVE_ARGS *cum; | |
1977 | ||
1978 | cum = get_cumulative_args (ca); | |
1979 | ||
1980 | /* Under hard float abi, we better have argument entirely passed in | |
1981 | registers or pushed on the stack so that we can reduce the complexity | |
1982 | of dealing with cum->gpr_offset and cum->fpr_offset. */ | |
1983 | if (TARGET_HARD_FLOAT) | |
1984 | return 0; | |
1985 | ||
1986 | /* If we have already runned out of argument registers, return zero | |
1987 | so that the argument will be entirely pushed on the stack. */ | |
1988 | if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
1989 | >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS) | |
1990 | return 0; | |
1991 | ||
1992 | /* Calculate how many registers do we need for this argument. */ | |
1993 | needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
1994 | ||
1995 | /* Calculate how many argument registers have left for passing argument. | |
1996 | Note that we should count it from next available register number. */ | |
1997 | remaining_reg_count | |
1998 | = NDS32_MAX_GPR_REGS_FOR_ARGS | |
1999 | - (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
8a498f99 | 2000 | - NDS32_GPR_ARG_FIRST_REGNUM); |
650fc469 CJW |
2001 | |
2002 | /* Note that we have to return the nubmer of bytes, not registers count. */ | |
2003 | if (needed_reg_count > remaining_reg_count) | |
2004 | return remaining_reg_count * UNITS_PER_WORD; | |
2005 | ||
2006 | return 0; | |
2007 | } | |
2008 | ||
9304f876 | 2009 | static void |
ef4bddc2 | 2010 | nds32_function_arg_advance (cumulative_args_t ca, machine_mode mode, |
9304f876 CJW |
2011 | const_tree type, bool named) |
2012 | { | |
2013 | CUMULATIVE_ARGS *cum = get_cumulative_args (ca); | |
2014 | ||
9304f876 CJW |
2015 | if (named) |
2016 | { | |
7f6cd86b | 2017 | /* We need to further check TYPE and MODE so that we can determine |
e2286268 | 2018 | which kind of register we shall advance. */ |
7f6cd86b CJW |
2019 | |
2020 | /* Under hard float abi, we may advance FPR registers. */ | |
e2286268 | 2021 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) |
7f6cd86b | 2022 | { |
e2286268 MC |
2023 | cum->fpr_offset |
2024 | = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type) | |
2025 | - NDS32_FPR_ARG_FIRST_REGNUM | |
2026 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
7f6cd86b CJW |
2027 | } |
2028 | else | |
2029 | { | |
2030 | cum->gpr_offset | |
2031 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
2032 | - NDS32_GPR_ARG_FIRST_REGNUM | |
2033 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
2034 | } | |
2035 | } | |
2036 | else | |
2037 | { | |
2038 | /* If this nameless argument is NOT under TARGET_HARD_FLOAT, | |
8a498f99 CJW |
2039 | we can advance next register as well so that caller is |
2040 | able to pass arguments in registers and callee must be | |
2041 | in charge of pushing all of them into stack. */ | |
7f6cd86b CJW |
2042 | if (!TARGET_HARD_FLOAT) |
2043 | { | |
2044 | cum->gpr_offset | |
2045 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
2046 | - NDS32_GPR_ARG_FIRST_REGNUM | |
2047 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
2048 | } | |
9304f876 CJW |
2049 | } |
2050 | } | |
2051 | ||
2052 | static unsigned int | |
ef4bddc2 | 2053 | nds32_function_arg_boundary (machine_mode mode, const_tree type) |
9304f876 CJW |
2054 | { |
2055 | return (nds32_needs_double_word_align (mode, type) | |
2056 | ? NDS32_DOUBLE_WORD_ALIGNMENT | |
2057 | : PARM_BOUNDARY); | |
2058 | } | |
2059 | ||
7c32ef41 MC |
2060 | bool |
2061 | nds32_vector_mode_supported_p (machine_mode mode) | |
2062 | { | |
2063 | if (mode == V4QImode | |
2064 | || mode == V2HImode) | |
2065 | return NDS32_EXT_DSP_P (); | |
2066 | ||
2067 | return false; | |
2068 | } | |
2069 | ||
9304f876 CJW |
2070 | /* -- How Scalar Function Values Are Returned. */ |
2071 | ||
2072 | static rtx | |
2073 | nds32_function_value (const_tree ret_type, | |
2074 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
2075 | bool outgoing ATTRIBUTE_UNUSED) | |
2076 | { | |
ef4bddc2 | 2077 | machine_mode mode; |
9304f876 CJW |
2078 | int unsignedp; |
2079 | ||
2080 | mode = TYPE_MODE (ret_type); | |
2081 | unsignedp = TYPE_UNSIGNED (ret_type); | |
2082 | ||
e2286268 MC |
2083 | if (INTEGRAL_TYPE_P (ret_type)) |
2084 | mode = promote_mode (ret_type, mode, &unsignedp); | |
9304f876 | 2085 | |
e2286268 MC |
2086 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) |
2087 | return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM); | |
2088 | else | |
2089 | return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); | |
9304f876 CJW |
2090 | } |
2091 | ||
2092 | static rtx | |
ef4bddc2 | 2093 | nds32_libcall_value (machine_mode mode, |
9304f876 CJW |
2094 | const_rtx fun ATTRIBUTE_UNUSED) |
2095 | { | |
e2286268 MC |
2096 | if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) |
2097 | return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM); | |
2098 | ||
9304f876 CJW |
2099 | return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); |
2100 | } | |
2101 | ||
2102 | static bool | |
2103 | nds32_function_value_regno_p (const unsigned int regno) | |
2104 | { | |
e2286268 MC |
2105 | if (regno == NDS32_GPR_RET_FIRST_REGNUM |
2106 | || (TARGET_HARD_FLOAT | |
2107 | && regno == NDS32_FPR_RET_FIRST_REGNUM)) | |
2108 | return true; | |
2109 | ||
2110 | return false; | |
2111 | } | |
2112 | ||
2113 | /* -- How Large Values Are Returned. */ | |
2114 | ||
2115 | static bool | |
2116 | nds32_return_in_memory (const_tree type, | |
2117 | const_tree fntype ATTRIBUTE_UNUSED) | |
2118 | { | |
2119 | /* Note that int_size_in_bytes can return -1 if the size can vary | |
2120 | or is larger than an integer. */ | |
2121 | HOST_WIDE_INT size = int_size_in_bytes (type); | |
2122 | ||
2123 | /* For COMPLEX_TYPE, if the total size cannot be hold within two registers, | |
2124 | the return value is supposed to be in memory. We need to be aware of | |
2125 | that the size may be -1. */ | |
2126 | if (TREE_CODE (type) == COMPLEX_TYPE) | |
2127 | if (size < 0 || size > 2 * UNITS_PER_WORD) | |
2128 | return true; | |
2129 | ||
2130 | /* If it is BLKmode and the total size cannot be hold within two registers, | |
2131 | the return value is supposed to be in memory. We need to be aware of | |
2132 | that the size may be -1. */ | |
2133 | if (TYPE_MODE (type) == BLKmode) | |
2134 | if (size < 0 || size > 2 * UNITS_PER_WORD) | |
2135 | return true; | |
2136 | ||
2137 | /* For other cases, having result in memory is unnecessary. */ | |
2138 | return false; | |
9304f876 CJW |
2139 | } |
2140 | ||
2141 | /* -- Function Entry and Exit. */ | |
2142 | ||
2143 | /* The content produced from this function | |
2144 | will be placed before prologue body. */ | |
2145 | static void | |
42776416 | 2146 | nds32_asm_function_prologue (FILE *file) |
9304f876 CJW |
2147 | { |
2148 | int r; | |
2149 | const char *func_name; | |
2150 | tree attrs; | |
2151 | tree name; | |
2152 | ||
2153 | /* All stack frame information is supposed to be | |
2154 | already computed when expanding prologue. | |
2155 | The result is in cfun->machine. | |
2156 | DO NOT call nds32_compute_stack_frame() here | |
2157 | because it may corrupt the essential information. */ | |
2158 | ||
2159 | fprintf (file, "\t! BEGIN PROLOGUE\n"); | |
2160 | fprintf (file, "\t! fp needed: %d\n", frame_pointer_needed); | |
2161 | fprintf (file, "\t! pretend_args: %d\n", cfun->machine->va_args_size); | |
2162 | fprintf (file, "\t! local_size: %d\n", cfun->machine->local_size); | |
2163 | fprintf (file, "\t! out_args_size: %d\n", cfun->machine->out_args_size); | |
2164 | ||
2165 | /* Use df_regs_ever_live_p() to detect if the register | |
2166 | is ever used in the current function. */ | |
2167 | fprintf (file, "\t! registers ever_live: "); | |
e2286268 | 2168 | for (r = 0; r < 65; r++) |
9304f876 CJW |
2169 | { |
2170 | if (df_regs_ever_live_p (r)) | |
2171 | fprintf (file, "%s, ", reg_names[r]); | |
2172 | } | |
2173 | fputc ('\n', file); | |
2174 | ||
2175 | /* Display the attributes of this function. */ | |
2176 | fprintf (file, "\t! function attributes: "); | |
f2dafb91 CJW |
2177 | /* Get the attributes tree list. |
2178 | Note that GCC builds attributes list with reverse order. */ | |
2179 | attrs = DECL_ATTRIBUTES (current_function_decl); | |
9304f876 CJW |
2180 | |
2181 | /* If there is no any attribute, print out "None". */ | |
2182 | if (!attrs) | |
2183 | fprintf (file, "None"); | |
2184 | ||
2185 | /* If there are some attributes, try if we need to | |
2186 | construct isr vector information. */ | |
2187 | func_name = IDENTIFIER_POINTER (DECL_NAME (current_function_decl)); | |
2188 | nds32_construct_isr_vectors_information (attrs, func_name); | |
2189 | ||
2190 | /* Display all attributes of this function. */ | |
2191 | while (attrs) | |
2192 | { | |
2193 | name = TREE_PURPOSE (attrs); | |
2194 | fprintf (file, "%s ", IDENTIFIER_POINTER (name)); | |
2195 | ||
2196 | /* Pick up the next attribute. */ | |
2197 | attrs = TREE_CHAIN (attrs); | |
2198 | } | |
2199 | fputc ('\n', file); | |
2200 | } | |
2201 | ||
2202 | /* After rtl prologue has been expanded, this function is used. */ | |
2203 | static void | |
2204 | nds32_asm_function_end_prologue (FILE *file) | |
2205 | { | |
2206 | fprintf (file, "\t! END PROLOGUE\n"); | |
9304f876 CJW |
2207 | } |
2208 | ||
2209 | /* Before rtl epilogue has been expanded, this function is used. */ | |
2210 | static void | |
2211 | nds32_asm_function_begin_epilogue (FILE *file) | |
2212 | { | |
9304f876 CJW |
2213 | fprintf (file, "\t! BEGIN EPILOGUE\n"); |
2214 | } | |
2215 | ||
2216 | /* The content produced from this function | |
2217 | will be placed after epilogue body. */ | |
2218 | static void | |
42776416 | 2219 | nds32_asm_function_epilogue (FILE *file) |
9304f876 CJW |
2220 | { |
2221 | fprintf (file, "\t! END EPILOGUE\n"); | |
2222 | } | |
2223 | ||
2224 | static void | |
2225 | nds32_asm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, | |
2226 | HOST_WIDE_INT delta, | |
2227 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
2228 | tree function) | |
2229 | { | |
2230 | int this_regno; | |
2231 | ||
2232 | /* Make sure unwind info is emitted for the thunk if needed. */ | |
2233 | final_start_function (emit_barrier (), file, 1); | |
2234 | ||
2235 | this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) | |
2236 | ? 1 | |
2237 | : 0); | |
2238 | ||
b26fa4f9 KLC |
2239 | if (flag_pic) |
2240 | { | |
2241 | fprintf (file, "\tsmw.adm\t$r31, [$r31], $r31, 4\n"); | |
2242 | fprintf (file, "\tsethi\t%s, hi20(_GLOBAL_OFFSET_TABLE_-8)\n", | |
2243 | reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
2244 | fprintf (file, "\tori\t%s, %s, lo12(_GLOBAL_OFFSET_TABLE_-4)\n", | |
2245 | reg_names [PIC_OFFSET_TABLE_REGNUM], | |
2246 | reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
2247 | ||
2248 | if (TARGET_ISA_V3) | |
2249 | fprintf (file, "\tadd5.pc\t$gp\n"); | |
2250 | else | |
2251 | { | |
2252 | fprintf (file, "\tmfusr\t$ta, $pc\n"); | |
2253 | fprintf (file, "\tadd\t%s, $ta, %s\n", | |
2254 | reg_names [PIC_OFFSET_TABLE_REGNUM], | |
2255 | reg_names [PIC_OFFSET_TABLE_REGNUM]); | |
2256 | } | |
2257 | } | |
2258 | ||
9304f876 CJW |
2259 | if (delta != 0) |
2260 | { | |
2261 | if (satisfies_constraint_Is15 (GEN_INT (delta))) | |
2262 | { | |
5af50159 | 2263 | fprintf (file, "\taddi\t$r%d, $r%d, " HOST_WIDE_INT_PRINT_DEC "\n", |
9304f876 CJW |
2264 | this_regno, this_regno, delta); |
2265 | } | |
2266 | else if (satisfies_constraint_Is20 (GEN_INT (delta))) | |
2267 | { | |
5af50159 | 2268 | fprintf (file, "\tmovi\t$ta, " HOST_WIDE_INT_PRINT_DEC "\n", delta); |
9304f876 CJW |
2269 | fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); |
2270 | } | |
2271 | else | |
2272 | { | |
5af50159 KC |
2273 | fprintf (file, |
2274 | "\tsethi\t$ta, hi20(" HOST_WIDE_INT_PRINT_DEC ")\n", | |
2275 | delta); | |
2276 | fprintf (file, | |
2277 | "\tori\t$ta, $ta, lo12(" HOST_WIDE_INT_PRINT_DEC ")\n", | |
2278 | delta); | |
9304f876 CJW |
2279 | fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); |
2280 | } | |
2281 | } | |
2282 | ||
b26fa4f9 KLC |
2283 | if (flag_pic) |
2284 | { | |
2285 | fprintf (file, "\tla\t$ta, "); | |
2286 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2287 | fprintf (file, "@PLT\n"); | |
2288 | fprintf (file, "\t! epilogue\n"); | |
2289 | fprintf (file, "\tlwi.bi\t%s, [%s], 4\n", | |
2290 | reg_names[PIC_OFFSET_TABLE_REGNUM], | |
2291 | reg_names[STACK_POINTER_REGNUM]); | |
2292 | fprintf (file, "\tbr\t$ta\n"); | |
2293 | } | |
2294 | else | |
2295 | { | |
2296 | fprintf (file, "\tb\t"); | |
2297 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
2298 | fprintf (file, "\n"); | |
2299 | } | |
9304f876 CJW |
2300 | |
2301 | final_end_function (); | |
2302 | } | |
2303 | ||
2304 | /* -- Permitting tail calls. */ | |
2305 | ||
cc48a87f CJW |
2306 | /* Return true if it is ok to do sibling call optimization. */ |
2307 | static bool | |
2308 | nds32_function_ok_for_sibcall (tree decl, | |
2309 | tree exp ATTRIBUTE_UNUSED) | |
2310 | { | |
2311 | /* The DECL is NULL if it is an indirect call. */ | |
2312 | ||
2313 | /* 1. Do not apply sibling call if -mv3push is enabled, | |
2314 | because pop25 instruction also represents return behavior. | |
a4931745 CJW |
2315 | 2. If this function is a isr function, do not apply sibling call |
2316 | because it may perform the behavior that user does not expect. | |
2317 | 3. If this function is a variadic function, do not apply sibling call | |
cc48a87f | 2318 | because the stack layout may be a mess. |
a4931745 | 2319 | 4. We don't want to apply sibling call optimization for indirect |
cc48a87f CJW |
2320 | sibcall because the pop behavior in epilogue may pollute the |
2321 | content of caller-saved regsiter when the register is used for | |
b26fa4f9 | 2322 | indirect sibcall. |
a4931745 | 2323 | 5. In pic mode, it may use some registers for PLT call. */ |
cc48a87f | 2324 | return (!TARGET_V3PUSH |
a4931745 | 2325 | && !nds32_isr_function_p (current_function_decl) |
cc48a87f | 2326 | && (cfun->machine->va_args_size == 0) |
b26fa4f9 KLC |
2327 | && decl |
2328 | && !flag_pic); | |
cc48a87f CJW |
2329 | } |
2330 | ||
9304f876 CJW |
2331 | /* Determine whether we need to enable warning for function return check. */ |
2332 | static bool | |
2333 | nds32_warn_func_return (tree decl) | |
2334 | { | |
8a498f99 CJW |
2335 | /* Naked functions are implemented entirely in assembly, including the |
2336 | return sequence, so suppress warnings about this. */ | |
9304f876 CJW |
2337 | return !nds32_naked_function_p (decl); |
2338 | } | |
2339 | ||
2340 | \f | |
2341 | /* Implementing the Varargs Macros. */ | |
2342 | ||
d4a6a4d9 CJW |
2343 | static void |
2344 | nds32_setup_incoming_varargs (cumulative_args_t ca, | |
ef4bddc2 | 2345 | machine_mode mode, |
d4a6a4d9 CJW |
2346 | tree type, |
2347 | int *pretend_args_size, | |
2348 | int second_time ATTRIBUTE_UNUSED) | |
2349 | { | |
2350 | unsigned int total_args_regs; | |
2351 | unsigned int num_of_used_regs; | |
2352 | unsigned int remaining_reg_count; | |
2353 | CUMULATIVE_ARGS *cum; | |
2354 | ||
2355 | /* If we are under hard float abi, we do not need to set *pretend_args_size. | |
2356 | So that all nameless arguments are pushed by caller and all situation | |
2357 | can be handled by GCC itself. */ | |
2358 | if (TARGET_HARD_FLOAT) | |
2359 | return; | |
2360 | ||
2361 | /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers, | |
2362 | counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments. | |
2363 | However, for nameless(anonymous) arguments, we should push them on the | |
2364 | stack so that all the nameless arguments appear to have been passed | |
2365 | consecutively in the memory for accessing. Hence, we need to check and | |
2366 | exclude the registers that are used for named arguments. */ | |
2367 | ||
2368 | cum = get_cumulative_args (ca); | |
2369 | ||
2370 | /* The MODE and TYPE describe the last argument. | |
2371 | We need those information to determine the remaining registers | |
2372 | for varargs. */ | |
2373 | total_args_regs | |
2374 | = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM; | |
2375 | num_of_used_regs | |
2376 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
2377 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
2378 | ||
2379 | remaining_reg_count = total_args_regs - num_of_used_regs; | |
2380 | *pretend_args_size = remaining_reg_count * UNITS_PER_WORD; | |
2381 | ||
2382 | return; | |
2383 | } | |
2384 | ||
9304f876 CJW |
2385 | static bool |
2386 | nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) | |
2387 | { | |
d4a6a4d9 CJW |
2388 | /* If this hook returns true, the named argument of FUNCTION_ARG is always |
2389 | true for named arguments, and false for unnamed arguments. */ | |
9304f876 CJW |
2390 | return true; |
2391 | } | |
2392 | ||
2393 | \f | |
2394 | /* Trampolines for Nested Functions. */ | |
2395 | ||
2396 | static void | |
2397 | nds32_asm_trampoline_template (FILE *f) | |
2398 | { | |
2399 | if (TARGET_REDUCED_REGS) | |
2400 | { | |
2401 | /* Trampoline is not supported on reduced-set registers yet. */ | |
2402 | sorry ("a nested function is not supported for reduced registers"); | |
2403 | } | |
2404 | else | |
2405 | { | |
2406 | asm_fprintf (f, "\t! Trampoline code template\n"); | |
2407 | asm_fprintf (f, "\t! This code fragment will be copied " | |
2408 | "into stack on demand\n"); | |
2409 | ||
2410 | asm_fprintf (f, "\tmfusr\t$r16,$pc\n"); | |
2411 | asm_fprintf (f, "\tlwi\t$r15,[$r16 + 20] " | |
2412 | "! load nested function address\n"); | |
2413 | asm_fprintf (f, "\tlwi\t$r16,[$r16 + 16] " | |
2414 | "! load chain_value\n"); | |
2415 | asm_fprintf (f, "\tjr\t$r15\n"); | |
2416 | } | |
2417 | ||
2418 | /* Preserve space ($pc + 16) for saving chain_value, | |
2419 | nds32_trampoline_init will fill the value in this slot. */ | |
2420 | asm_fprintf (f, "\t! space for saving chain_value\n"); | |
2421 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
2422 | ||
2423 | /* Preserve space ($pc + 20) for saving nested function address, | |
2424 | nds32_trampoline_init will fill the value in this slot. */ | |
2425 | asm_fprintf (f, "\t! space for saving nested function address\n"); | |
2426 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
2427 | } | |
2428 | ||
2429 | /* Emit RTL insns to initialize the variable parts of a trampoline. */ | |
2430 | static void | |
2431 | nds32_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
2432 | { | |
2433 | int i; | |
2434 | ||
2435 | /* Nested function address. */ | |
2436 | rtx fnaddr; | |
2437 | /* The memory rtx that is going to | |
2438 | be filled with chain_value. */ | |
2439 | rtx chain_value_mem; | |
2440 | /* The memory rtx that is going to | |
2441 | be filled with nested function address. */ | |
2442 | rtx nested_func_mem; | |
2443 | ||
2444 | /* Start address of trampoline code in stack, for doing cache sync. */ | |
2445 | rtx sync_cache_addr; | |
2446 | /* Temporary register for sync instruction. */ | |
2447 | rtx tmp_reg; | |
2448 | /* Instruction-cache sync instruction, | |
2449 | requesting an argument as starting address. */ | |
2450 | rtx isync_insn; | |
2451 | /* For convenience reason of doing comparison. */ | |
2452 | int tramp_align_in_bytes; | |
2453 | ||
2454 | /* Trampoline is not supported on reduced-set registers yet. */ | |
2455 | if (TARGET_REDUCED_REGS) | |
2456 | sorry ("a nested function is not supported for reduced registers"); | |
2457 | ||
2458 | /* STEP 1: Copy trampoline code template into stack, | |
8a498f99 | 2459 | fill up essential data into stack. */ |
9304f876 CJW |
2460 | |
2461 | /* Extract nested function address rtx. */ | |
2462 | fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
2463 | ||
2464 | /* m_tramp is memory rtx that is going to be filled with trampoline code. | |
2465 | We have nds32_asm_trampoline_template() to emit template pattern. */ | |
2466 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
2467 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
2468 | ||
2469 | /* After copying trampoline code into stack, | |
2470 | fill chain_value into stack. */ | |
2471 | chain_value_mem = adjust_address (m_tramp, SImode, 16); | |
2472 | emit_move_insn (chain_value_mem, chain_value); | |
2473 | /* After copying trampoline code int stack, | |
2474 | fill nested function address into stack. */ | |
2475 | nested_func_mem = adjust_address (m_tramp, SImode, 20); | |
2476 | emit_move_insn (nested_func_mem, fnaddr); | |
2477 | ||
2478 | /* STEP 2: Sync instruction-cache. */ | |
2479 | ||
2480 | /* We have successfully filled trampoline code into stack. | |
2481 | However, in order to execute code in stack correctly, | |
2482 | we must sync instruction cache. */ | |
2483 | sync_cache_addr = XEXP (m_tramp, 0); | |
2484 | tmp_reg = gen_reg_rtx (SImode); | |
2485 | isync_insn = gen_unspec_volatile_isync (tmp_reg); | |
2486 | ||
2487 | /* Because nds32_cache_block_size is in bytes, | |
2488 | we get trampoline alignment in bytes for convenient comparison. */ | |
2489 | tramp_align_in_bytes = TRAMPOLINE_ALIGNMENT / BITS_PER_UNIT; | |
2490 | ||
2491 | if (tramp_align_in_bytes >= nds32_cache_block_size | |
2492 | && (tramp_align_in_bytes % nds32_cache_block_size) == 0) | |
2493 | { | |
2494 | /* Under this condition, the starting address of trampoline | |
8a498f99 CJW |
2495 | must be aligned to the starting address of each cache block |
2496 | and we do not have to worry about cross-boundary issue. */ | |
9304f876 CJW |
2497 | for (i = 0; |
2498 | i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) | |
2499 | / nds32_cache_block_size; | |
2500 | i++) | |
2501 | { | |
2502 | emit_move_insn (tmp_reg, | |
2503 | plus_constant (Pmode, sync_cache_addr, | |
2504 | nds32_cache_block_size * i)); | |
2505 | emit_insn (isync_insn); | |
2506 | } | |
2507 | } | |
2508 | else if (TRAMPOLINE_SIZE > nds32_cache_block_size) | |
2509 | { | |
2510 | /* The starting address of trampoline code | |
8a498f99 CJW |
2511 | may not be aligned to the cache block, |
2512 | so the trampoline code may be across two cache block. | |
2513 | We need to sync the last element, which is 4-byte size, | |
2514 | of trampoline template. */ | |
9304f876 CJW |
2515 | for (i = 0; |
2516 | i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) | |
2517 | / nds32_cache_block_size; | |
2518 | i++) | |
2519 | { | |
2520 | emit_move_insn (tmp_reg, | |
2521 | plus_constant (Pmode, sync_cache_addr, | |
2522 | nds32_cache_block_size * i)); | |
2523 | emit_insn (isync_insn); | |
2524 | } | |
2525 | ||
2526 | /* The last element of trampoline template is 4-byte size. */ | |
2527 | emit_move_insn (tmp_reg, | |
2528 | plus_constant (Pmode, sync_cache_addr, | |
2529 | TRAMPOLINE_SIZE - 4)); | |
2530 | emit_insn (isync_insn); | |
2531 | } | |
2532 | else | |
2533 | { | |
2534 | /* This is the simplest case. | |
8a498f99 CJW |
2535 | Because TRAMPOLINE_SIZE is less than or |
2536 | equal to nds32_cache_block_size, | |
2537 | we can just sync start address and | |
2538 | the last element of trampoline code. */ | |
9304f876 CJW |
2539 | |
2540 | /* Sync starting address of tampoline code. */ | |
2541 | emit_move_insn (tmp_reg, sync_cache_addr); | |
2542 | emit_insn (isync_insn); | |
2543 | /* Sync the last element, which is 4-byte size, | |
8a498f99 | 2544 | of trampoline template. */ |
9304f876 CJW |
2545 | emit_move_insn (tmp_reg, |
2546 | plus_constant (Pmode, sync_cache_addr, | |
2547 | TRAMPOLINE_SIZE - 4)); | |
2548 | emit_insn (isync_insn); | |
2549 | } | |
2550 | ||
2551 | /* Set instruction serialization barrier | |
2552 | to guarantee the correct operations. */ | |
2553 | emit_insn (gen_unspec_volatile_isb ()); | |
2554 | } | |
2555 | ||
2556 | \f | |
2557 | /* Addressing Modes. */ | |
2558 | ||
2559 | static bool | |
ef4bddc2 | 2560 | nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict) |
9304f876 | 2561 | { |
e2286268 MC |
2562 | if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) |
2563 | { | |
2564 | /* When using floating-point instructions, | |
2565 | we don't allow 'addr' to be [symbol_ref], [CONST] pattern. */ | |
2566 | if ((mode == DFmode || mode == SFmode) | |
2567 | && (GET_CODE (x) == SYMBOL_REF | |
2568 | || GET_CODE(x) == CONST)) | |
2569 | return false; | |
2570 | ||
2571 | /* Allow [post_modify] addressing mode, when using FPU instructions. */ | |
2572 | if (GET_CODE (x) == POST_MODIFY | |
2573 | && mode == DFmode) | |
2574 | { | |
2575 | if (GET_CODE (XEXP (x, 0)) == REG | |
2576 | && GET_CODE (XEXP (x, 1)) == PLUS) | |
2577 | { | |
2578 | rtx plus_op = XEXP (x, 1); | |
2579 | rtx op0 = XEXP (plus_op, 0); | |
2580 | rtx op1 = XEXP (plus_op, 1); | |
2581 | ||
2582 | if (nds32_address_register_rtx_p (op0, strict) | |
2583 | && CONST_INT_P (op1)) | |
2584 | { | |
2585 | if (satisfies_constraint_Is14 (op1)) | |
2586 | { | |
5f2a98c3 CJW |
2587 | /* If it is not under strictly aligned situation, |
2588 | we can return true without checking alignment. */ | |
2589 | if (!cfun->machine->strict_aligned_p) | |
2590 | return true; | |
e2286268 MC |
2591 | /* Make sure address is word alignment. |
2592 | Currently we do not have 64-bit load/store yet, | |
2593 | so we will use two 32-bit load/store instructions to do | |
2594 | memory access and they are single word alignment. */ | |
5f2a98c3 | 2595 | else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (op1))) |
e2286268 MC |
2596 | return true; |
2597 | } | |
2598 | } | |
2599 | } | |
2600 | } | |
2601 | } | |
2602 | ||
9304f876 CJW |
2603 | /* For (mem:DI addr) or (mem:DF addr) case, |
2604 | we only allow 'addr' to be [reg], [symbol_ref], | |
8a498f99 | 2605 | [const], or [reg + const_int] pattern. */ |
9304f876 CJW |
2606 | if (mode == DImode || mode == DFmode) |
2607 | { | |
2608 | /* Allow [Reg + const_int] addressing mode. */ | |
2609 | if (GET_CODE (x) == PLUS) | |
2610 | { | |
2611 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict) | |
2612 | && nds32_legitimate_index_p (mode, XEXP (x, 1), strict) | |
2613 | && CONST_INT_P (XEXP (x, 1))) | |
2614 | return true; | |
9304f876 CJW |
2615 | else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) |
2616 | && nds32_legitimate_index_p (mode, XEXP (x, 0), strict) | |
2617 | && CONST_INT_P (XEXP (x, 0))) | |
2618 | return true; | |
2619 | } | |
2620 | ||
e2286268 MC |
2621 | /* Allow [post_inc] and [post_dec] addressing mode. */ |
2622 | if (GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC) | |
2623 | { | |
2624 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) | |
2625 | return true; | |
2626 | } | |
2627 | ||
9304f876 CJW |
2628 | /* Now check [reg], [symbol_ref], and [const]. */ |
2629 | if (GET_CODE (x) != REG | |
2630 | && GET_CODE (x) != SYMBOL_REF | |
2631 | && GET_CODE (x) != CONST) | |
2632 | return false; | |
2633 | } | |
2634 | ||
2635 | /* Check if 'x' is a valid address. */ | |
2636 | switch (GET_CODE (x)) | |
2637 | { | |
2638 | case REG: | |
2639 | /* (mem (reg A)) => [Ra] */ | |
2640 | return nds32_address_register_rtx_p (x, strict); | |
2641 | ||
2642 | case SYMBOL_REF: | |
4855be84 | 2643 | /* (mem (symbol_ref A)) => [symbol_ref] */ |
b26fa4f9 KLC |
2644 | |
2645 | if (flag_pic || SYMBOL_REF_TLS_MODEL (x)) | |
2646 | return false; | |
2647 | ||
85a98076 KLC |
2648 | if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) |
2649 | return false; | |
2650 | ||
4855be84 | 2651 | /* If -mcmodel=large, the 'symbol_ref' is not a valid address |
8a498f99 | 2652 | during or after LRA/reload phase. */ |
4855be84 | 2653 | if (TARGET_CMODEL_LARGE |
9304f876 CJW |
2654 | && (reload_completed |
2655 | || reload_in_progress | |
2656 | || lra_in_progress)) | |
2657 | return false; | |
4855be84 | 2658 | /* If -mcmodel=medium and the symbol references to rodata section, |
8a498f99 CJW |
2659 | the 'symbol_ref' is not a valid address during or after |
2660 | LRA/reload phase. */ | |
4855be84 | 2661 | if (TARGET_CMODEL_MEDIUM |
b26fa4f9 KLC |
2662 | && (NDS32_SYMBOL_REF_RODATA_P (x) |
2663 | || CONSTANT_POOL_ADDRESS_P (x)) | |
9304f876 CJW |
2664 | && (reload_completed |
2665 | || reload_in_progress | |
2666 | || lra_in_progress)) | |
2667 | return false; | |
2668 | ||
4855be84 CJW |
2669 | return true; |
2670 | ||
2671 | case CONST: | |
9304f876 | 2672 | /* (mem (const (...))) |
8a498f99 | 2673 | => [ + const_addr ], where const_addr = symbol_ref + const_int */ |
9304f876 CJW |
2674 | if (GET_CODE (XEXP (x, 0)) == PLUS) |
2675 | { | |
2676 | rtx plus_op = XEXP (x, 0); | |
2677 | ||
2678 | rtx op0 = XEXP (plus_op, 0); | |
2679 | rtx op1 = XEXP (plus_op, 1); | |
2680 | ||
2681 | if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) | |
4855be84 CJW |
2682 | { |
2683 | /* Now we see the [ + const_addr ] pattern, but we need | |
8a498f99 | 2684 | some further checking. */ |
b26fa4f9 KLC |
2685 | |
2686 | if (flag_pic) | |
2687 | return false; | |
2688 | ||
4855be84 | 2689 | /* If -mcmodel=large, the 'const_addr' is not a valid address |
8a498f99 | 2690 | during or after LRA/reload phase. */ |
4855be84 CJW |
2691 | if (TARGET_CMODEL_LARGE |
2692 | && (reload_completed | |
2693 | || reload_in_progress | |
2694 | || lra_in_progress)) | |
2695 | return false; | |
2696 | /* If -mcmodel=medium and the symbol references to rodata section, | |
8a498f99 CJW |
2697 | the 'const_addr' is not a valid address during or after |
2698 | LRA/reload phase. */ | |
4855be84 CJW |
2699 | if (TARGET_CMODEL_MEDIUM |
2700 | && NDS32_SYMBOL_REF_RODATA_P (op0) | |
2701 | && (reload_completed | |
2702 | || reload_in_progress | |
2703 | || lra_in_progress)) | |
2704 | return false; | |
2705 | ||
2706 | /* At this point we can make sure 'const_addr' is a | |
2707 | valid address. */ | |
2708 | return true; | |
2709 | } | |
9304f876 CJW |
2710 | } |
2711 | ||
2712 | return false; | |
2713 | ||
2714 | case POST_MODIFY: | |
2715 | /* (mem (post_modify (reg) (plus (reg) (reg)))) | |
8a498f99 | 2716 | => [Ra], Rb */ |
9304f876 | 2717 | /* (mem (post_modify (reg) (plus (reg) (const_int)))) |
8a498f99 | 2718 | => [Ra], const_int */ |
9304f876 CJW |
2719 | if (GET_CODE (XEXP (x, 0)) == REG |
2720 | && GET_CODE (XEXP (x, 1)) == PLUS) | |
2721 | { | |
2722 | rtx plus_op = XEXP (x, 1); | |
2723 | ||
2724 | rtx op0 = XEXP (plus_op, 0); | |
2725 | rtx op1 = XEXP (plus_op, 1); | |
2726 | ||
2727 | if (nds32_address_register_rtx_p (op0, strict) | |
2728 | && nds32_legitimate_index_p (mode, op1, strict)) | |
2729 | return true; | |
2730 | else | |
2731 | return false; | |
2732 | } | |
2733 | ||
2734 | return false; | |
2735 | ||
2736 | case POST_INC: | |
2737 | case POST_DEC: | |
2738 | /* (mem (post_inc reg)) => [Ra], 1/2/4 */ | |
2739 | /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */ | |
2740 | /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. | |
8a498f99 | 2741 | We only need to deal with register Ra. */ |
9304f876 CJW |
2742 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) |
2743 | return true; | |
2744 | else | |
2745 | return false; | |
2746 | ||
2747 | case PLUS: | |
2748 | /* (mem (plus reg const_int)) | |
8a498f99 | 2749 | => [Ra + imm] */ |
9304f876 | 2750 | /* (mem (plus reg reg)) |
8a498f99 | 2751 | => [Ra + Rb] */ |
9304f876 | 2752 | /* (mem (plus (mult reg const_int) reg)) |
8a498f99 | 2753 | => [Ra + Rb << sv] */ |
9304f876 CJW |
2754 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict) |
2755 | && nds32_legitimate_index_p (mode, XEXP (x, 1), strict)) | |
2756 | return true; | |
2757 | else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) | |
2758 | && nds32_legitimate_index_p (mode, XEXP (x, 0), strict)) | |
2759 | return true; | |
2760 | else | |
2761 | return false; | |
2762 | ||
2763 | case LO_SUM: | |
34425025 | 2764 | /* (mem (lo_sum (reg) (symbol_ref))) */ |
85a98076 | 2765 | /* (mem (lo_sum (reg) (const (plus (symbol_ref) (reg)))) */ |
b26fa4f9 KLC |
2766 | /* TLS case: (mem (lo_sum (reg) (const (unspec symbol_ref X)))) */ |
2767 | /* The LO_SUM is a valid address if and only if we would like to | |
2768 | generate 32-bit full address memory access with any of following | |
2769 | circumstance: | |
2770 | 1. -mcmodel=large. | |
2771 | 2. -mcmodel=medium and the symbol_ref references to rodata. */ | |
85a98076 KLC |
2772 | { |
2773 | rtx sym = NULL_RTX; | |
2774 | ||
b26fa4f9 KLC |
2775 | if (flag_pic) |
2776 | return false; | |
2777 | ||
85a98076 KLC |
2778 | if (!REG_P (XEXP (x, 0))) |
2779 | return false; | |
2780 | ||
2781 | if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
2782 | sym = XEXP (x, 1); | |
2783 | else if (GET_CODE (XEXP (x, 1)) == CONST) | |
2784 | { | |
2785 | rtx plus = XEXP(XEXP (x, 1), 0); | |
2786 | if (GET_CODE (plus) == PLUS) | |
2787 | sym = XEXP (plus, 0); | |
2788 | else if (GET_CODE (plus) == UNSPEC) | |
2789 | sym = XVECEXP (plus, 0, 0); | |
2790 | } | |
2791 | else | |
2792 | return false; | |
2793 | ||
2794 | gcc_assert (GET_CODE (sym) == SYMBOL_REF); | |
2795 | ||
2796 | if (TARGET_ICT_MODEL_LARGE | |
2797 | && nds32_indirect_call_referenced_p (sym)) | |
2798 | return true; | |
2799 | ||
2800 | if (TARGET_CMODEL_LARGE) | |
2801 | return true; | |
2802 | else if (TARGET_CMODEL_MEDIUM | |
2803 | && NDS32_SYMBOL_REF_RODATA_P (sym)) | |
2804 | return true; | |
2805 | else | |
2806 | return false; | |
2807 | } | |
9304f876 CJW |
2808 | |
2809 | default: | |
2810 | return false; | |
2811 | } | |
2812 | } | |
2813 | ||
85a98076 KLC |
2814 | static rtx |
2815 | nds32_legitimize_address (rtx x, | |
2816 | rtx oldx ATTRIBUTE_UNUSED, | |
2817 | machine_mode mode ATTRIBUTE_UNUSED) | |
2818 | { | |
b26fa4f9 KLC |
2819 | if (nds32_tls_referenced_p (x)) |
2820 | x = nds32_legitimize_tls_address (x); | |
2821 | else if (flag_pic && SYMBOLIC_CONST_P (x)) | |
2822 | x = nds32_legitimize_pic_address (x); | |
2823 | else if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) | |
85a98076 KLC |
2824 | x = nds32_legitimize_ict_address (x); |
2825 | ||
2826 | return x; | |
2827 | } | |
2828 | ||
2829 | static bool | |
2830 | nds32_legitimate_constant_p (machine_mode mode, rtx x) | |
2831 | { | |
2832 | switch (GET_CODE (x)) | |
2833 | { | |
2834 | case CONST_DOUBLE: | |
2835 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
2836 | && (mode == DFmode || mode == SFmode)) | |
2837 | return false; | |
2838 | break; | |
2839 | case CONST: | |
2840 | x = XEXP (x, 0); | |
2841 | ||
2842 | if (GET_CODE (x) == PLUS) | |
2843 | { | |
2844 | if (!CONST_INT_P (XEXP (x, 1))) | |
2845 | return false; | |
2846 | x = XEXP (x, 0); | |
2847 | } | |
2848 | ||
2849 | if (GET_CODE (x) == UNSPEC) | |
2850 | { | |
2851 | switch (XINT (x, 1)) | |
2852 | { | |
b26fa4f9 KLC |
2853 | case UNSPEC_GOT: |
2854 | case UNSPEC_GOTOFF: | |
2855 | case UNSPEC_PLT: | |
2856 | case UNSPEC_TLSGD: | |
2857 | case UNSPEC_TLSLD: | |
2858 | case UNSPEC_TLSIE: | |
2859 | case UNSPEC_TLSLE: | |
85a98076 KLC |
2860 | case UNSPEC_ICT: |
2861 | return false; | |
2862 | default: | |
2863 | return true; | |
2864 | } | |
2865 | } | |
2866 | break; | |
b26fa4f9 KLC |
2867 | case SYMBOL_REF: |
2868 | /* TLS symbols need a call to resolve in | |
2869 | precompute_register_parameters. */ | |
2870 | if (SYMBOL_REF_TLS_MODEL (x)) | |
2871 | return false; | |
2872 | break; | |
85a98076 KLC |
2873 | default: |
2874 | return true; | |
2875 | } | |
2876 | ||
2877 | return true; | |
2878 | } | |
2879 | ||
2880 | /* Reorgnize the UNSPEC CONST and return its direct symbol. */ | |
2881 | static rtx | |
2882 | nds32_delegitimize_address (rtx x) | |
2883 | { | |
2884 | x = delegitimize_mem_from_attrs (x); | |
2885 | ||
2886 | if (GET_CODE(x) == CONST) | |
2887 | { | |
2888 | rtx inner = XEXP (x, 0); | |
2889 | ||
2890 | /* Handle for GOTOFF. */ | |
2891 | if (GET_CODE (inner) == PLUS) | |
2892 | inner = XEXP (inner, 0); | |
2893 | ||
2894 | if (GET_CODE (inner) == UNSPEC) | |
2895 | { | |
2896 | switch (XINT (inner, 1)) | |
2897 | { | |
b26fa4f9 KLC |
2898 | case UNSPEC_GOTINIT: |
2899 | case UNSPEC_GOT: | |
2900 | case UNSPEC_GOTOFF: | |
2901 | case UNSPEC_PLT: | |
2902 | case UNSPEC_TLSGD: | |
2903 | case UNSPEC_TLSLD: | |
2904 | case UNSPEC_TLSIE: | |
2905 | case UNSPEC_TLSLE: | |
85a98076 KLC |
2906 | case UNSPEC_ICT: |
2907 | x = XVECEXP (inner, 0, 0); | |
2908 | break; | |
2909 | default: | |
2910 | break; | |
2911 | } | |
2912 | } | |
2913 | } | |
2914 | return x; | |
2915 | } | |
2916 | ||
7c32ef41 MC |
2917 | static machine_mode |
2918 | nds32_vectorize_preferred_simd_mode (scalar_mode mode) | |
2919 | { | |
2920 | if (!NDS32_EXT_DSP_P ()) | |
2921 | return word_mode; | |
2922 | ||
2923 | switch (mode) | |
2924 | { | |
2925 | case E_QImode: | |
2926 | return V4QImode; | |
2927 | case E_HImode: | |
2928 | return V2HImode; | |
2929 | default: | |
2930 | return word_mode; | |
2931 | } | |
2932 | } | |
2933 | ||
85a98076 KLC |
2934 | static bool |
2935 | nds32_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
2936 | { | |
2937 | switch (GET_CODE (x)) | |
2938 | { | |
2939 | case CONST: | |
2940 | return !nds32_legitimate_constant_p (mode, x); | |
2941 | case SYMBOL_REF: | |
2942 | /* All symbols have to be accessed through gp-relative in PIC mode. */ | |
2943 | /* We don't want to force symbol as constant pool in .text section, | |
2944 | because we use the gp-relatived instruction to load in small | |
2945 | or medium model. */ | |
b26fa4f9 KLC |
2946 | if (flag_pic |
2947 | || SYMBOL_REF_TLS_MODEL (x) | |
85a98076 KLC |
2948 | || TARGET_CMODEL_SMALL |
2949 | || TARGET_CMODEL_MEDIUM) | |
2950 | return true; | |
2951 | break; | |
b26fa4f9 KLC |
2952 | case CONST_INT: |
2953 | case CONST_DOUBLE: | |
2954 | if (flag_pic && (lra_in_progress || reload_completed)) | |
2955 | return true; | |
2956 | break; | |
85a98076 KLC |
2957 | default: |
2958 | return false; | |
2959 | } | |
2960 | return false; | |
2961 | } | |
2962 | ||
5b6f2bf3 CJW |
2963 | \f |
2964 | /* Condition Code Status. */ | |
2965 | ||
2966 | /* -- Representation of condition codes using registers. */ | |
2967 | ||
2968 | static void | |
2969 | nds32_canonicalize_comparison (int *code, | |
2970 | rtx *op0 ATTRIBUTE_UNUSED, | |
2971 | rtx *op1, | |
2972 | bool op0_preserve_value ATTRIBUTE_UNUSED) | |
2973 | { | |
2974 | /* When the instruction combination pass tries to combine a comparison insn | |
2975 | with its previous insns, it also transforms the operator in order to | |
2976 | minimize its constant field. For example, it tries to transform a | |
2977 | comparison insn from | |
2978 | (set (reg:SI 54) | |
2979 | (ltu:SI (reg:SI 52) | |
2980 | (const_int 10 [0xa]))) | |
2981 | to | |
2982 | (set (reg:SI 54) | |
2983 | (leu:SI (reg:SI 52) | |
2984 | (const_int 9 [0x9]))) | |
2985 | ||
2986 | However, the nds32 target only provides instructions supporting the LTU | |
2987 | operation directly, and the implementation of the pattern "cbranchsi4" | |
2988 | only expands the LTU form. In order to handle the non-LTU operations | |
2989 | generated from passes other than the RTL expansion pass, we have to | |
2990 | implement this hook to revert those changes. Since we only expand the LTU | |
2991 | operator in the RTL expansion pass, we might only need to handle the LEU | |
2992 | case, unless we find other optimization passes perform more aggressive | |
2993 | transformations. */ | |
2994 | ||
2995 | if (*code == LEU && CONST_INT_P (*op1)) | |
2996 | { | |
2997 | *op1 = gen_int_mode (INTVAL (*op1) + 1, SImode); | |
2998 | *code = LTU; | |
2999 | } | |
3000 | } | |
3001 | ||
9304f876 CJW |
3002 | \f |
3003 | /* Describing Relative Costs of Operations. */ | |
3004 | ||
19ac960a | 3005 | static int |
69e7672a | 3006 | nds32_register_move_cost (machine_mode mode, |
19ac960a CJW |
3007 | reg_class_t from, |
3008 | reg_class_t to) | |
9304f876 | 3009 | { |
69e7672a KC |
3010 | /* In garywolf cpu, FPR to GPR is chaper than other cpu. */ |
3011 | if (TARGET_PIPELINE_GRAYWOLF) | |
3012 | { | |
3013 | if (GET_MODE_SIZE (mode) == 8) | |
3014 | { | |
3015 | /* DPR to GPR. */ | |
3016 | if (from == FP_REGS && to != FP_REGS) | |
3017 | return 3; | |
3018 | /* GPR to DPR. */ | |
3019 | if (from != FP_REGS && to == FP_REGS) | |
3020 | return 2; | |
3021 | } | |
3022 | else | |
3023 | { | |
3024 | if ((from == FP_REGS && to != FP_REGS) | |
3025 | || (from != FP_REGS && to == FP_REGS)) | |
3026 | return 2; | |
3027 | } | |
3028 | } | |
3029 | ||
e2286268 MC |
3030 | if ((from == FP_REGS && to != FP_REGS) |
3031 | || (from != FP_REGS && to == FP_REGS)) | |
69e7672a | 3032 | return 3; |
e2286268 MC |
3033 | else if (from == HIGH_REGS || to == HIGH_REGS) |
3034 | return optimize_size ? 6 : 2; | |
3035 | else | |
3036 | return 2; | |
9304f876 CJW |
3037 | } |
3038 | ||
19ac960a | 3039 | static int |
ef4bddc2 | 3040 | nds32_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
19ac960a CJW |
3041 | reg_class_t rclass ATTRIBUTE_UNUSED, |
3042 | bool in ATTRIBUTE_UNUSED) | |
9304f876 CJW |
3043 | { |
3044 | return 8; | |
3045 | } | |
3046 | ||
3047 | /* This target hook describes the relative costs of RTL expressions. | |
3048 | Return 'true' when all subexpressions of x have been processed. | |
3049 | Return 'false' to sum the costs of sub-rtx, plus cost of this operation. | |
3050 | Refer to gcc/rtlanal.c for more information. */ | |
3051 | static bool | |
3052 | nds32_rtx_costs (rtx x, | |
e548c9df | 3053 | machine_mode mode, |
9304f876 | 3054 | int outer_code, |
89a4b547 | 3055 | int opno, |
9304f876 CJW |
3056 | int *total, |
3057 | bool speed) | |
3058 | { | |
e548c9df | 3059 | return nds32_rtx_costs_impl (x, mode, outer_code, opno, total, speed); |
9304f876 CJW |
3060 | } |
3061 | ||
19ac960a CJW |
3062 | static int |
3063 | nds32_address_cost (rtx address, | |
ef4bddc2 | 3064 | machine_mode mode, |
19ac960a CJW |
3065 | addr_space_t as, |
3066 | bool speed) | |
9304f876 | 3067 | { |
89a4b547 | 3068 | return nds32_address_cost_impl (address, mode, as, speed); |
9304f876 CJW |
3069 | } |
3070 | ||
511a41d7 CJW |
3071 | \f |
3072 | /* Dividing the Output into Sections (Texts, Data, . . . ). */ | |
3073 | ||
3074 | /* If references to a symbol or a constant must be treated differently | |
3075 | depending on something about the variable or function named by the symbol | |
3076 | (such as what section it is in), we use this hook to store flags | |
3077 | in symbol_ref rtx. */ | |
3078 | static void | |
3079 | nds32_encode_section_info (tree decl, rtx rtl, int new_decl_p) | |
3080 | { | |
3081 | default_encode_section_info (decl, rtl, new_decl_p); | |
3082 | ||
3083 | /* For the memory rtx, if it references to rodata section, we can store | |
3084 | NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the | |
3085 | nds32_legitimate_address_p() can determine how to treat such symbol_ref | |
3086 | based on -mcmodel=X and this information. */ | |
3087 | if (MEM_P (rtl) && MEM_READONLY_P (rtl)) | |
3088 | { | |
3089 | rtx addr = XEXP (rtl, 0); | |
3090 | ||
3091 | if (GET_CODE (addr) == SYMBOL_REF) | |
3092 | { | |
3093 | /* For (mem (symbol_ref X)) case. */ | |
3094 | SYMBOL_REF_FLAGS (addr) |= NDS32_SYMBOL_FLAG_RODATA; | |
3095 | } | |
3096 | else if (GET_CODE (addr) == CONST | |
3097 | && GET_CODE (XEXP (addr, 0)) == PLUS) | |
3098 | { | |
3099 | /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */ | |
3100 | rtx plus_op = XEXP (addr, 0); | |
3101 | rtx op0 = XEXP (plus_op, 0); | |
3102 | rtx op1 = XEXP (plus_op, 1); | |
3103 | ||
3104 | if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) | |
3105 | SYMBOL_REF_FLAGS (op0) |= NDS32_SYMBOL_FLAG_RODATA; | |
3106 | } | |
3107 | } | |
3108 | } | |
3109 | ||
9304f876 CJW |
3110 | \f |
3111 | /* Defining the Output Assembler Language. */ | |
3112 | ||
3113 | /* -- The Overall Framework of an Assembler File. */ | |
3114 | ||
3115 | static void | |
3116 | nds32_asm_file_start (void) | |
3117 | { | |
9304f876 CJW |
3118 | default_file_start (); |
3119 | ||
b26fa4f9 KLC |
3120 | if (flag_pic) |
3121 | fprintf (asm_out_file, "\t.pic\n"); | |
3122 | ||
9304f876 CJW |
3123 | /* Tell assembler which ABI we are using. */ |
3124 | fprintf (asm_out_file, "\t! ABI version\n"); | |
e2286268 MC |
3125 | if (TARGET_HARD_FLOAT) |
3126 | fprintf (asm_out_file, "\t.abi_2fp_plus\n"); | |
3127 | else | |
3128 | fprintf (asm_out_file, "\t.abi_2\n"); | |
9304f876 CJW |
3129 | |
3130 | /* Tell assembler that this asm code is generated by compiler. */ | |
3131 | fprintf (asm_out_file, "\t! This asm file is generated by compiler\n"); | |
3132 | fprintf (asm_out_file, "\t.flag\tverbatim\n"); | |
85a98076 | 3133 | |
cf3cd43d CJW |
3134 | /* Insert directive for linker to distinguish object's ict flag. */ |
3135 | if (!TARGET_LINUX_ABI) | |
3136 | { | |
3137 | if (TARGET_ICT_MODEL_LARGE) | |
3138 | fprintf (asm_out_file, "\t.ict_model\tlarge\n"); | |
3139 | else | |
3140 | fprintf (asm_out_file, "\t.ict_model\tsmall\n"); | |
3141 | } | |
3142 | ||
3143 | /* We need to provide the size of each vector for interrupt handler | |
3144 | under elf toolchain. */ | |
3145 | if (!TARGET_LINUX_ABI) | |
3146 | { | |
3147 | fprintf (asm_out_file, "\t! This vector size directive is required " | |
3148 | "for checking inconsistency on interrupt handler\n"); | |
3149 | fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size); | |
3150 | } | |
9304f876 | 3151 | |
2140297c CJW |
3152 | /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os, |
3153 | the compiler may produce 'la $fp,_FP_BASE_' instruction | |
3154 | at prologue for fp-as-gp optimization. | |
3155 | We should emit weak reference of _FP_BASE_ to avoid undefined reference | |
3156 | in case user does not pass '--relax' option to linker. */ | |
cf3cd43d | 3157 | if (!TARGET_LINUX_ABI && (TARGET_FORCE_FP_AS_GP || optimize_size)) |
2140297c CJW |
3158 | { |
3159 | fprintf (asm_out_file, "\t! This weak reference is required to do " | |
3160 | "fp-as-gp link time optimization\n"); | |
3161 | fprintf (asm_out_file, "\t.weak\t_FP_BASE_\n"); | |
3162 | } | |
3163 | ||
9304f876 CJW |
3164 | fprintf (asm_out_file, "\t! ------------------------------------\n"); |
3165 | ||
3166 | if (TARGET_ISA_V2) | |
3167 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V2"); | |
3168 | if (TARGET_ISA_V3) | |
3169 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3"); | |
3170 | if (TARGET_ISA_V3M) | |
3171 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M"); | |
3172 | ||
dd000841 CJW |
3173 | switch (nds32_cpu_option) |
3174 | { | |
3175 | case CPU_N6: | |
3176 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N6"); | |
3177 | break; | |
3178 | ||
3179 | case CPU_N7: | |
3180 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N7"); | |
3181 | break; | |
3182 | ||
3183 | case CPU_N8: | |
3184 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N8"); | |
3185 | break; | |
3186 | ||
3187 | case CPU_E8: | |
3188 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "E8"); | |
3189 | break; | |
3190 | ||
3191 | case CPU_N9: | |
3192 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N9"); | |
3193 | break; | |
3194 | ||
3195 | case CPU_N10: | |
3196 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N10"); | |
3197 | break; | |
3198 | ||
3199 | case CPU_GRAYWOLF: | |
3200 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "Graywolf"); | |
3201 | break; | |
3202 | ||
3203 | case CPU_N12: | |
3204 | case CPU_N13: | |
3205 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N13"); | |
3206 | break; | |
3207 | ||
3208 | case CPU_SIMPLE: | |
3209 | fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "SIMPLE"); | |
3210 | break; | |
3211 | ||
3212 | default: | |
3213 | gcc_unreachable (); | |
3214 | } | |
3215 | ||
77b7a1ca CJW |
3216 | if (TARGET_CMODEL_SMALL) |
3217 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "SMALL"); | |
3218 | if (TARGET_CMODEL_MEDIUM) | |
3219 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "MEDIUM"); | |
3220 | if (TARGET_CMODEL_LARGE) | |
3221 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "LARGE"); | |
3222 | ||
9304f876 CJW |
3223 | fprintf (asm_out_file, "\t! Endian setting\t: %s\n", |
3224 | ((TARGET_BIG_ENDIAN) ? "big-endian" | |
3225 | : "little-endian")); | |
e2286268 MC |
3226 | fprintf (asm_out_file, "\t! Use SP floating-point instruction\t: %s\n", |
3227 | ((TARGET_FPU_SINGLE) ? "Yes" | |
3228 | : "No")); | |
3229 | fprintf (asm_out_file, "\t! Use DP floating-point instruction\t: %s\n", | |
3230 | ((TARGET_FPU_DOUBLE) ? "Yes" | |
3231 | : "No")); | |
3232 | fprintf (asm_out_file, "\t! ABI version\t\t: %s\n", | |
3233 | ((TARGET_HARD_FLOAT) ? "ABI2FP+" | |
3234 | : "ABI2")); | |
9304f876 CJW |
3235 | |
3236 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3237 | ||
3238 | fprintf (asm_out_file, "\t! Use conditional move\t\t: %s\n", | |
3239 | ((TARGET_CMOV) ? "Yes" | |
3240 | : "No")); | |
3241 | fprintf (asm_out_file, "\t! Use performance extension\t: %s\n", | |
aa4b851c | 3242 | ((TARGET_EXT_PERF) ? "Yes" |
9304f876 | 3243 | : "No")); |
aa4b851c CJW |
3244 | fprintf (asm_out_file, "\t! Use performance extension 2\t: %s\n", |
3245 | ((TARGET_EXT_PERF2) ? "Yes" | |
3246 | : "No")); | |
3247 | fprintf (asm_out_file, "\t! Use string extension\t\t: %s\n", | |
3248 | ((TARGET_EXT_STRING) ? "Yes" | |
3249 | : "No")); | |
9304f876 CJW |
3250 | |
3251 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3252 | ||
3253 | fprintf (asm_out_file, "\t! V3PUSH instructions\t: %s\n", | |
3254 | ((TARGET_V3PUSH) ? "Yes" | |
3255 | : "No")); | |
3256 | fprintf (asm_out_file, "\t! 16-bit instructions\t: %s\n", | |
3257 | ((TARGET_16_BIT) ? "Yes" | |
3258 | : "No")); | |
9304f876 CJW |
3259 | fprintf (asm_out_file, "\t! Reduced registers set\t: %s\n", |
3260 | ((TARGET_REDUCED_REGS) ? "Yes" | |
3261 | : "No")); | |
3262 | ||
bc8a8810 MC |
3263 | fprintf (asm_out_file, "\t! Support unaligned access\t\t: %s\n", |
3264 | (flag_unaligned_access ? "Yes" | |
3265 | : "No")); | |
3266 | ||
9304f876 CJW |
3267 | fprintf (asm_out_file, "\t! ------------------------------------\n"); |
3268 | ||
3269 | if (optimize_size) | |
3270 | fprintf (asm_out_file, "\t! Optimization level\t: -Os\n"); | |
10c8bd03 CJW |
3271 | else if (optimize_fast) |
3272 | fprintf (asm_out_file, "\t! Optimization level\t: -Ofast\n"); | |
3273 | else if (optimize_debug) | |
3274 | fprintf (asm_out_file, "\t! Optimization level\t: -Og\n"); | |
9304f876 CJW |
3275 | else |
3276 | fprintf (asm_out_file, "\t! Optimization level\t: -O%d\n", optimize); | |
3277 | ||
3278 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3279 | ||
3280 | fprintf (asm_out_file, "\t! Cache block size\t: %d\n", | |
3281 | nds32_cache_block_size); | |
3282 | ||
3283 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
3284 | ||
c23a919b | 3285 | nds32_asm_file_start_for_isr (); |
9304f876 CJW |
3286 | } |
3287 | ||
3288 | static void | |
3289 | nds32_asm_file_end (void) | |
3290 | { | |
c23a919b | 3291 | nds32_asm_file_end_for_isr (); |
9304f876 | 3292 | |
cf3cd43d CJW |
3293 | /* The NDS32 Linux stack is mapped non-executable by default, so add a |
3294 | .note.GNU-stack section. */ | |
3295 | if (TARGET_LINUX_ABI) | |
3296 | file_end_indicate_exec_stack (); | |
3297 | ||
9304f876 CJW |
3298 | fprintf (asm_out_file, "\t! ------------------------------------\n"); |
3299 | } | |
3300 | ||
85a98076 KLC |
3301 | static bool |
3302 | nds32_asm_output_addr_const_extra (FILE *file, rtx x) | |
3303 | { | |
3304 | if (GET_CODE (x) == UNSPEC) | |
3305 | { | |
3306 | switch (XINT (x, 1)) | |
3307 | { | |
b26fa4f9 KLC |
3308 | case UNSPEC_GOTINIT: |
3309 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3310 | break; | |
3311 | case UNSPEC_GOTOFF: | |
3312 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3313 | fputs ("@GOTOFF", file); | |
3314 | break; | |
3315 | case UNSPEC_GOT: | |
3316 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3317 | fputs ("@GOT", file); | |
3318 | break; | |
3319 | case UNSPEC_PLT: | |
3320 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3321 | fputs ("@PLT", file); | |
3322 | break; | |
3323 | case UNSPEC_TLSGD: | |
3324 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3325 | fputs ("@TLSDESC", file); | |
3326 | break; | |
3327 | case UNSPEC_TLSLD: | |
3328 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3329 | fputs ("@TLSDESC", file); | |
3330 | break; | |
3331 | case UNSPEC_TLSIE: | |
3332 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3333 | fputs ("@GOTTPOFF", file); | |
3334 | break; | |
3335 | case UNSPEC_TLSLE: | |
3336 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3337 | fputs ("@TPOFF", file); | |
3338 | break; | |
85a98076 KLC |
3339 | case UNSPEC_ICT: |
3340 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
3341 | fputs ("@ICT", file); | |
3342 | break; | |
3343 | default: | |
3344 | return false; | |
3345 | } | |
3346 | return true; | |
3347 | } | |
3348 | else | |
3349 | return false; | |
3350 | } | |
3351 | ||
9304f876 CJW |
3352 | /* -- Output and Generation of Labels. */ |
3353 | ||
3354 | static void | |
3355 | nds32_asm_globalize_label (FILE *stream, const char *name) | |
3356 | { | |
3357 | fputs ("\t.global\t", stream); | |
3358 | assemble_name (stream, name); | |
3359 | fputs ("\n", stream); | |
3360 | } | |
3361 | ||
3362 | /* -- Output of Assembler Instructions. */ | |
3363 | ||
3364 | static void | |
3365 | nds32_print_operand (FILE *stream, rtx x, int code) | |
3366 | { | |
bfeb6685 | 3367 | HOST_WIDE_INT op_value = 0; |
a3b13564 KC |
3368 | HOST_WIDE_INT one_position; |
3369 | HOST_WIDE_INT zero_position; | |
e2286268 MC |
3370 | bool pick_lsb_p = false; |
3371 | bool pick_msb_p = false; | |
3372 | int regno; | |
3373 | ||
bfeb6685 CJW |
3374 | if (CONST_INT_P (x)) |
3375 | op_value = INTVAL (x); | |
9304f876 CJW |
3376 | |
3377 | switch (code) | |
3378 | { | |
3379 | case 0 : | |
3380 | /* Do nothing special. */ | |
3381 | break; | |
3382 | ||
a3b13564 KC |
3383 | case 'b': |
3384 | /* Use exact_log2() to search the 0-bit position. */ | |
3385 | gcc_assert (CONST_INT_P (x)); | |
3386 | zero_position = exact_log2 (~UINTVAL (x) & GET_MODE_MASK (SImode)); | |
3387 | gcc_assert (zero_position != -1); | |
3388 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, zero_position); | |
3389 | ||
3390 | /* No need to handle following process, so return immediately. */ | |
3391 | return; | |
3392 | ||
8656bbcf SC |
3393 | case 'e': |
3394 | gcc_assert (MEM_P (x) | |
3395 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3396 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT); | |
3397 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (XEXP (x, 0), 1))); | |
3398 | ||
3399 | /* No need to handle following process, so return immediately. */ | |
3400 | return; | |
7c32ef41 MC |
3401 | |
3402 | case 'v': | |
3403 | gcc_assert (CONST_INT_P (x) | |
3404 | && (INTVAL (x) == 0 | |
3405 | || INTVAL (x) == 8 | |
3406 | || INTVAL (x) == 16 | |
3407 | || INTVAL (x) == 24)); | |
3408 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8); | |
3409 | ||
3410 | /* No need to handle following process, so return immediately. */ | |
3411 | return; | |
3412 | ||
a3b13564 KC |
3413 | case 'B': |
3414 | /* Use exact_log2() to search the 1-bit position. */ | |
3415 | gcc_assert (CONST_INT_P (x)); | |
3416 | one_position = exact_log2 (UINTVAL (x) & GET_MODE_MASK (SImode)); | |
3417 | gcc_assert (one_position != -1); | |
3418 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, one_position); | |
3419 | ||
3420 | /* No need to handle following process, so return immediately. */ | |
3421 | return; | |
3422 | ||
e2286268 MC |
3423 | case 'L': |
3424 | /* X is supposed to be REG rtx. */ | |
3425 | gcc_assert (REG_P (x)); | |
3426 | /* Claim that we are going to pick LSB part of X. */ | |
3427 | pick_lsb_p = true; | |
3428 | break; | |
3429 | ||
3430 | case 'H': | |
3431 | /* X is supposed to be REG rtx. */ | |
3432 | gcc_assert (REG_P (x)); | |
3433 | /* Claim that we are going to pick MSB part of X. */ | |
3434 | pick_msb_p = true; | |
3435 | break; | |
3436 | ||
9304f876 CJW |
3437 | case 'V': |
3438 | /* 'x' is supposed to be CONST_INT, get the value. */ | |
3439 | gcc_assert (CONST_INT_P (x)); | |
9304f876 CJW |
3440 | |
3441 | /* According to the Andes architecture, | |
8a498f99 CJW |
3442 | the system/user register index range is 0 ~ 1023. |
3443 | In order to avoid conflict between user-specified-integer value | |
3444 | and enum-specified-register value, | |
3445 | the 'enum nds32_intrinsic_registers' value | |
3446 | in nds32_intrinsic.h starts from 1024. */ | |
9304f876 CJW |
3447 | if (op_value < 1024 && op_value >= 0) |
3448 | { | |
3449 | /* If user gives integer value directly (0~1023), | |
3450 | we just print out the value. */ | |
5af50159 | 3451 | fprintf (stream, HOST_WIDE_INT_PRINT_DEC, op_value); |
9304f876 CJW |
3452 | } |
3453 | else if (op_value < 0 | |
3454 | || op_value >= ((int) ARRAY_SIZE (nds32_intrinsic_register_names) | |
3455 | + 1024)) | |
3456 | { | |
3457 | /* The enum index value for array size is out of range. */ | |
3458 | error ("intrinsic register index is out of range"); | |
3459 | } | |
3460 | else | |
3461 | { | |
3462 | /* If user applies normal way with __NDS32_REG_XXX__ enum data, | |
3463 | we can print out register name. Remember to substract 1024. */ | |
3464 | fprintf (stream, "%s", | |
3465 | nds32_intrinsic_register_names[op_value - 1024]); | |
3466 | } | |
3467 | ||
3468 | /* No need to handle following process, so return immediately. */ | |
3469 | return; | |
3470 | ||
f1a0afe2 MC |
3471 | case 'R': /* cctl valck */ |
3472 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3473 | if (op_value < 0 || op_value > 4) | |
3474 | error ("CCTL intrinsic function subtype out of range!"); | |
3475 | fprintf (stream, "%s", nds32_cctl_names[op_value]); | |
3476 | return; | |
3477 | ||
3478 | case 'T': /* cctl idxwbinv */ | |
3479 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3480 | if (op_value < 0 || op_value > 4) | |
3481 | error ("CCTL intrinsic function subtype out of range!"); | |
3482 | fprintf (stream, "%s", nds32_cctl_names[op_value + 4]); | |
3483 | return; | |
3484 | ||
3485 | case 'U': /* cctl vawbinv */ | |
3486 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3487 | if (op_value < 0 || op_value > 4) | |
3488 | error ("CCTL intrinsic function subtype out of range!"); | |
3489 | fprintf (stream, "%s", nds32_cctl_names[op_value + 8]); | |
3490 | return; | |
3491 | ||
3492 | case 'X': /* cctl idxread */ | |
3493 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3494 | if (op_value < 0 || op_value > 4) | |
3495 | error ("CCTL intrinsic function subtype out of range!"); | |
3496 | fprintf (stream, "%s", nds32_cctl_names[op_value + 12]); | |
3497 | return; | |
3498 | ||
3499 | case 'W': /* cctl idxwitre */ | |
3500 | /* Note the cctl divide to 5 group and share the same name table. */ | |
3501 | if (op_value < 0 || op_value > 4) | |
3502 | error ("CCTL intrinsic function subtype out of range!"); | |
3503 | fprintf (stream, "%s", nds32_cctl_names[op_value + 16]); | |
3504 | return; | |
3505 | ||
57aaf0cc MC |
3506 | case 'Z': /* dpref */ |
3507 | fprintf (stream, "%s", nds32_dpref_names[op_value]); | |
3508 | return; | |
3509 | ||
9304f876 CJW |
3510 | default : |
3511 | /* Unknown flag. */ | |
3512 | output_operand_lossage ("invalid operand output code"); | |
3513 | break; | |
3514 | } | |
3515 | ||
3516 | switch (GET_CODE (x)) | |
3517 | { | |
3518 | case LABEL_REF: | |
85a98076 KLC |
3519 | output_addr_const (stream, x); |
3520 | break; | |
3521 | ||
9304f876 CJW |
3522 | case SYMBOL_REF: |
3523 | output_addr_const (stream, x); | |
85a98076 | 3524 | |
cf3cd43d | 3525 | if (!TARGET_LINUX_ABI && nds32_indirect_call_referenced_p (x)) |
85a98076 KLC |
3526 | fprintf (stream, "@ICT"); |
3527 | ||
9304f876 CJW |
3528 | break; |
3529 | ||
3530 | case REG: | |
e2286268 MC |
3531 | /* Print a Double-precision register name. */ |
3532 | if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode) | |
3533 | && NDS32_IS_FPR_REGNUM (REGNO (x))) | |
3534 | { | |
3535 | regno = REGNO (x); | |
3536 | if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno)) | |
3537 | { | |
3538 | output_operand_lossage ("invalid operand for code '%c'", code); | |
3539 | break; | |
3540 | } | |
3541 | fprintf (stream, "$fd%d", (regno - NDS32_FIRST_FPR_REGNUM) >> 1); | |
3542 | break; | |
3543 | } | |
3544 | ||
3545 | /* Print LSB or MSB part of register pair if the | |
3546 | constraint modifier 'L' or 'H' is specified. */ | |
3547 | if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode) | |
3548 | && NDS32_IS_GPR_REGNUM (REGNO (x))) | |
3549 | { | |
3550 | if ((pick_lsb_p && WORDS_BIG_ENDIAN) | |
3551 | || (pick_msb_p && !WORDS_BIG_ENDIAN)) | |
3552 | { | |
3553 | /* If we would like to print out LSB register under big-endian, | |
3554 | or print out MSB register under little-endian, we need to | |
3555 | increase register number. */ | |
3556 | regno = REGNO (x); | |
3557 | regno++; | |
3558 | fputs (reg_names[regno], stream); | |
3559 | break; | |
3560 | } | |
3561 | } | |
3562 | ||
9304f876 | 3563 | /* Forbid using static chain register ($r16) |
8a498f99 | 3564 | on reduced-set registers configuration. */ |
9304f876 CJW |
3565 | if (TARGET_REDUCED_REGS |
3566 | && REGNO (x) == STATIC_CHAIN_REGNUM) | |
3567 | sorry ("a nested function is not supported for reduced registers"); | |
3568 | ||
3569 | /* Normal cases, print out register name. */ | |
3570 | fputs (reg_names[REGNO (x)], stream); | |
3571 | break; | |
3572 | ||
3573 | case MEM: | |
cc8ca59e | 3574 | output_address (GET_MODE (x), XEXP (x, 0)); |
9304f876 CJW |
3575 | break; |
3576 | ||
e2286268 MC |
3577 | case HIGH: |
3578 | if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE) | |
3579 | { | |
3580 | const REAL_VALUE_TYPE *rv; | |
3581 | long val; | |
3582 | gcc_assert (GET_MODE (x) == SFmode); | |
3583 | ||
3584 | rv = CONST_DOUBLE_REAL_VALUE (XEXP (x, 0)); | |
3585 | REAL_VALUE_TO_TARGET_SINGLE (*rv, val); | |
3586 | ||
3587 | fprintf (stream, "hi20(0x%lx)", val); | |
3588 | } | |
3589 | else | |
3590 | gcc_unreachable (); | |
3591 | break; | |
3592 | ||
3593 | case CONST_DOUBLE: | |
3594 | const REAL_VALUE_TYPE *rv; | |
3595 | long val; | |
3596 | gcc_assert (GET_MODE (x) == SFmode); | |
3597 | ||
3598 | rv = CONST_DOUBLE_REAL_VALUE (x); | |
3599 | REAL_VALUE_TO_TARGET_SINGLE (*rv, val); | |
3600 | ||
3601 | fprintf (stream, "0x%lx", val); | |
3602 | break; | |
3603 | ||
9304f876 CJW |
3604 | case CODE_LABEL: |
3605 | case CONST_INT: | |
3606 | case CONST: | |
3607 | output_addr_const (stream, x); | |
3608 | break; | |
3609 | ||
7c32ef41 MC |
3610 | case CONST_VECTOR: |
3611 | fprintf (stream, HOST_WIDE_INT_PRINT_HEX, const_vector_to_hwint (x)); | |
3612 | break; | |
3613 | ||
85a98076 KLC |
3614 | case LO_SUM: |
3615 | /* This is a special case for inline assembly using memory address 'p'. | |
3616 | The inline assembly code is expected to use pesudo instruction | |
3617 | for the operand. EX: la */ | |
3618 | output_addr_const (stream, XEXP(x, 1)); | |
3619 | break; | |
3620 | ||
9304f876 CJW |
3621 | default: |
3622 | /* Generally, output_addr_const () is able to handle most cases. | |
8a498f99 CJW |
3623 | We want to see what CODE could appear, |
3624 | so we use gcc_unreachable() to stop it. */ | |
9304f876 CJW |
3625 | debug_rtx (x); |
3626 | gcc_unreachable (); | |
3627 | break; | |
3628 | } | |
3629 | } | |
3630 | ||
3631 | static void | |
85a98076 KLC |
3632 | nds32_print_operand_address (FILE *stream, |
3633 | machine_mode mode ATTRIBUTE_UNUSED, | |
3634 | rtx x) | |
9304f876 CJW |
3635 | { |
3636 | rtx op0, op1; | |
3637 | ||
3638 | switch (GET_CODE (x)) | |
3639 | { | |
3640 | case SYMBOL_REF: | |
3641 | case CONST: | |
3642 | /* [ + symbol_ref] */ | |
3643 | /* [ + const_addr], where const_addr = symbol_ref + const_int */ | |
3644 | fputs ("[ + ", stream); | |
3645 | output_addr_const (stream, x); | |
3646 | fputs ("]", stream); | |
3647 | break; | |
3648 | ||
85a98076 KLC |
3649 | case LO_SUM: |
3650 | /* This is a special case for inline assembly using memory operand 'm'. | |
3651 | The inline assembly code is expected to use pesudo instruction | |
3652 | for the operand. EX: [ls].[bhw] */ | |
3653 | fputs ("[ + ", stream); | |
3654 | op1 = XEXP (x, 1); | |
3655 | output_addr_const (stream, op1); | |
3656 | fputs ("]", stream); | |
3657 | break; | |
3658 | ||
9304f876 CJW |
3659 | case REG: |
3660 | /* Forbid using static chain register ($r16) | |
8a498f99 | 3661 | on reduced-set registers configuration. */ |
9304f876 CJW |
3662 | if (TARGET_REDUCED_REGS |
3663 | && REGNO (x) == STATIC_CHAIN_REGNUM) | |
3664 | sorry ("a nested function is not supported for reduced registers"); | |
3665 | ||
3666 | /* [Ra] */ | |
3667 | fprintf (stream, "[%s]", reg_names[REGNO (x)]); | |
3668 | break; | |
3669 | ||
3670 | case PLUS: | |
3671 | op0 = XEXP (x, 0); | |
3672 | op1 = XEXP (x, 1); | |
3673 | ||
3674 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 3675 | on reduced-set registers configuration. */ |
9304f876 CJW |
3676 | if (TARGET_REDUCED_REGS |
3677 | && REG_P (op0) | |
3678 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
3679 | sorry ("a nested function is not supported for reduced registers"); | |
3680 | /* Checking op1, forbid using static chain register ($r16) | |
8a498f99 | 3681 | on reduced-set registers configuration. */ |
9304f876 CJW |
3682 | if (TARGET_REDUCED_REGS |
3683 | && REG_P (op1) | |
3684 | && REGNO (op1) == STATIC_CHAIN_REGNUM) | |
3685 | sorry ("a nested function is not supported for reduced registers"); | |
3686 | ||
3687 | if (REG_P (op0) && CONST_INT_P (op1)) | |
3688 | { | |
3689 | /* [Ra + imm] */ | |
5af50159 KC |
3690 | fprintf (stream, "[%s + (" HOST_WIDE_INT_PRINT_DEC ")]", |
3691 | reg_names[REGNO (op0)], INTVAL (op1)); | |
9304f876 CJW |
3692 | } |
3693 | else if (REG_P (op0) && REG_P (op1)) | |
3694 | { | |
3695 | /* [Ra + Rb] */ | |
3696 | fprintf (stream, "[%s + %s]", | |
3697 | reg_names[REGNO (op0)], reg_names[REGNO (op1)]); | |
3698 | } | |
3699 | else if (GET_CODE (op0) == MULT && REG_P (op1)) | |
3700 | { | |
3701 | /* [Ra + Rb << sv] | |
3702 | From observation, the pattern looks like: | |
3703 | (plus:SI (mult:SI (reg:SI 58) | |
8a498f99 CJW |
3704 | (const_int 4 [0x4])) |
3705 | (reg/f:SI 57)) */ | |
9304f876 CJW |
3706 | int sv; |
3707 | ||
3708 | /* We need to set sv to output shift value. */ | |
3709 | if (INTVAL (XEXP (op0, 1)) == 1) | |
3710 | sv = 0; | |
3711 | else if (INTVAL (XEXP (op0, 1)) == 2) | |
3712 | sv = 1; | |
3713 | else if (INTVAL (XEXP (op0, 1)) == 4) | |
3714 | sv = 2; | |
f62a2af5 CJW |
3715 | else if (INTVAL (XEXP (op0, 1)) == 8) |
3716 | sv = 3; | |
9304f876 CJW |
3717 | else |
3718 | gcc_unreachable (); | |
3719 | ||
3720 | fprintf (stream, "[%s + %s << %d]", | |
3721 | reg_names[REGNO (op1)], | |
3722 | reg_names[REGNO (XEXP (op0, 0))], | |
3723 | sv); | |
3724 | } | |
7c32ef41 MC |
3725 | else if (GET_CODE (op0) == ASHIFT && REG_P (op1)) |
3726 | { | |
3727 | /* [Ra + Rb << sv] | |
3728 | In normal, ASHIFT can be converted to MULT like above case. | |
3729 | But when the address rtx does not go through canonicalize_address | |
3730 | defined in fwprop, we'll need this case. */ | |
3731 | int sv = INTVAL (XEXP (op0, 1)); | |
3732 | gcc_assert (sv <= 3 && sv >=0); | |
3733 | ||
3734 | fprintf (stream, "[%s + %s << %d]", | |
3735 | reg_names[REGNO (op1)], | |
3736 | reg_names[REGNO (XEXP (op0, 0))], | |
3737 | sv); | |
3738 | } | |
9304f876 CJW |
3739 | else |
3740 | { | |
3741 | /* The control flow is not supposed to be here. */ | |
3742 | debug_rtx (x); | |
3743 | gcc_unreachable (); | |
3744 | } | |
3745 | ||
3746 | break; | |
3747 | ||
3748 | case POST_MODIFY: | |
3749 | /* (post_modify (regA) (plus (regA) (regB))) | |
8a498f99 CJW |
3750 | (post_modify (regA) (plus (regA) (const_int))) |
3751 | We would like to extract | |
3752 | regA and regB (or const_int) from plus rtx. */ | |
9304f876 CJW |
3753 | op0 = XEXP (XEXP (x, 1), 0); |
3754 | op1 = XEXP (XEXP (x, 1), 1); | |
3755 | ||
3756 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 3757 | on reduced-set registers configuration. */ |
9304f876 CJW |
3758 | if (TARGET_REDUCED_REGS |
3759 | && REG_P (op0) | |
3760 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
3761 | sorry ("a nested function is not supported for reduced registers"); | |
3762 | /* Checking op1, forbid using static chain register ($r16) | |
8a498f99 | 3763 | on reduced-set registers configuration. */ |
9304f876 CJW |
3764 | if (TARGET_REDUCED_REGS |
3765 | && REG_P (op1) | |
3766 | && REGNO (op1) == STATIC_CHAIN_REGNUM) | |
3767 | sorry ("a nested function is not supported for reduced registers"); | |
3768 | ||
3769 | if (REG_P (op0) && REG_P (op1)) | |
3770 | { | |
3771 | /* [Ra], Rb */ | |
3772 | fprintf (stream, "[%s], %s", | |
3773 | reg_names[REGNO (op0)], reg_names[REGNO (op1)]); | |
3774 | } | |
3775 | else if (REG_P (op0) && CONST_INT_P (op1)) | |
3776 | { | |
3777 | /* [Ra], imm */ | |
5af50159 KC |
3778 | fprintf (stream, "[%s], " HOST_WIDE_INT_PRINT_DEC, |
3779 | reg_names[REGNO (op0)], INTVAL (op1)); | |
9304f876 CJW |
3780 | } |
3781 | else | |
3782 | { | |
3783 | /* The control flow is not supposed to be here. */ | |
3784 | debug_rtx (x); | |
3785 | gcc_unreachable (); | |
3786 | } | |
3787 | ||
3788 | break; | |
3789 | ||
3790 | case POST_INC: | |
3791 | case POST_DEC: | |
3792 | op0 = XEXP (x, 0); | |
3793 | ||
3794 | /* Checking op0, forbid using static chain register ($r16) | |
8a498f99 | 3795 | on reduced-set registers configuration. */ |
9304f876 CJW |
3796 | if (TARGET_REDUCED_REGS |
3797 | && REG_P (op0) | |
3798 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
3799 | sorry ("a nested function is not supported for reduced registers"); | |
3800 | ||
3801 | if (REG_P (op0)) | |
3802 | { | |
3803 | /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4" | |
3804 | The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. | |
3805 | We only need to deal with register Ra. */ | |
3806 | fprintf (stream, "[%s]", reg_names[REGNO (op0)]); | |
3807 | } | |
3808 | else | |
3809 | { | |
3810 | /* The control flow is not supposed to be here. */ | |
3811 | debug_rtx (x); | |
3812 | gcc_unreachable (); | |
3813 | } | |
3814 | ||
3815 | break; | |
3816 | ||
3817 | default : | |
3818 | /* Generally, output_addr_const () is able to handle most cases. | |
8a498f99 CJW |
3819 | We want to see what CODE could appear, |
3820 | so we use gcc_unreachable() to stop it. */ | |
9304f876 CJW |
3821 | debug_rtx (x); |
3822 | gcc_unreachable (); | |
3823 | break; | |
3824 | } | |
3825 | } | |
3826 | ||
e2286268 MC |
3827 | /* -- Assembler Commands for Exception Regions. */ |
3828 | ||
3829 | static rtx | |
3830 | nds32_dwarf_register_span (rtx reg) | |
3831 | { | |
3832 | rtx dwarf_high, dwarf_low; | |
3833 | rtx dwarf_single; | |
3834 | machine_mode mode; | |
3835 | int regno; | |
3836 | ||
3837 | mode = GET_MODE (reg); | |
3838 | regno = REGNO (reg); | |
3839 | ||
3840 | /* We need to adjust dwarf register information for floating-point registers | |
3841 | rather than using default register number mapping. */ | |
3842 | if (regno >= NDS32_FIRST_FPR_REGNUM | |
3843 | && regno <= NDS32_LAST_FPR_REGNUM) | |
3844 | { | |
3845 | if (mode == DFmode || mode == SCmode) | |
3846 | { | |
3847 | /* By default, GCC maps increasing register numbers to increasing | |
3848 | memory locations, but paired FPRs in NDS32 target are always | |
3849 | big-endian, i.e.: | |
3850 | ||
3851 | fd0 : fs0 fs1 | |
3852 | (MSB) (LSB) | |
3853 | ||
3854 | We must return parallel rtx to represent such layout. */ | |
3855 | dwarf_high = gen_rtx_REG (word_mode, regno); | |
3856 | dwarf_low = gen_rtx_REG (word_mode, regno + 1); | |
3857 | return gen_rtx_PARALLEL (VOIDmode, | |
3858 | gen_rtvec (2, dwarf_low, dwarf_high)); | |
3859 | } | |
3860 | else if (mode == DCmode) | |
3861 | { | |
3862 | rtx dwarf_high_re = gen_rtx_REG (word_mode, regno); | |
3863 | rtx dwarf_low_re = gen_rtx_REG (word_mode, regno + 1); | |
3864 | rtx dwarf_high_im = gen_rtx_REG (word_mode, regno); | |
3865 | rtx dwarf_low_im = gen_rtx_REG (word_mode, regno + 1); | |
3866 | return gen_rtx_PARALLEL (VOIDmode, | |
3867 | gen_rtvec (4, dwarf_low_re, dwarf_high_re, | |
3868 | dwarf_high_im, dwarf_low_im)); | |
3869 | } | |
3870 | else if (mode == SFmode || mode == SImode) | |
3871 | { | |
3872 | /* Create new dwarf information with adjusted register number. */ | |
3873 | dwarf_single = gen_rtx_REG (word_mode, regno); | |
3874 | return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, dwarf_single)); | |
3875 | } | |
3876 | else | |
3877 | { | |
3878 | /* We should not be here. */ | |
3879 | gcc_unreachable (); | |
3880 | } | |
3881 | } | |
3882 | ||
3883 | return NULL_RTX; | |
3884 | } | |
3885 | ||
3886 | /* Map internal gcc register numbers to DWARF2 register numbers. */ | |
3887 | ||
3888 | unsigned int | |
3889 | nds32_dbx_register_number (unsigned int regno) | |
3890 | { | |
3891 | /* The nds32 port in GDB maintains a mapping between dwarf register | |
3892 | number and displayed register name. For backward compatibility to | |
3893 | previous toolchain, currently our gdb still has four registers | |
3894 | (d0.l, d0.h, d1.l, and d1.h) between GPR and FPR while compiler | |
3895 | does not count those four registers in its register number table. | |
3896 | So we have to add 4 on its register number and then create new | |
3897 | dwarf information. Hopefully we can discard such workaround | |
3898 | in the future. */ | |
3899 | if (NDS32_IS_FPR_REGNUM (regno)) | |
3900 | return regno + 4; | |
3901 | ||
3902 | return regno; | |
3903 | } | |
3904 | ||
9304f876 CJW |
3905 | \f |
3906 | /* Defining target-specific uses of __attribute__. */ | |
3907 | ||
3908 | /* Add some checking after merging attributes. */ | |
3909 | static tree | |
3910 | nds32_merge_decl_attributes (tree olddecl, tree newdecl) | |
3911 | { | |
3912 | tree combined_attrs; | |
3913 | ||
3914 | /* Create combined attributes. */ | |
3915 | combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl), | |
3916 | DECL_ATTRIBUTES (newdecl)); | |
3917 | ||
59043e75 | 3918 | /* Since newdecl is acutally a duplicate of olddecl, |
9304f876 CJW |
3919 | we can take olddecl for some operations. */ |
3920 | if (TREE_CODE (olddecl) == FUNCTION_DECL) | |
3921 | { | |
3922 | /* Check isr-specific attributes conflict. */ | |
3923 | nds32_check_isr_attrs_conflict (olddecl, combined_attrs); | |
3924 | } | |
3925 | ||
3926 | return combined_attrs; | |
3927 | } | |
3928 | ||
3929 | /* Add some checking when inserting attributes. */ | |
3930 | static void | |
3931 | nds32_insert_attributes (tree decl, tree *attributes) | |
3932 | { | |
85a98076 KLC |
3933 | /* A "indirect_call" function attribute implies "noinline" and "noclone" |
3934 | for elf toolchain to support ROM patch mechanism. */ | |
3935 | if (TREE_CODE (decl) == FUNCTION_DECL | |
3936 | && lookup_attribute ("indirect_call", *attributes) != NULL) | |
3937 | { | |
3938 | tree new_attrs = *attributes; | |
3939 | ||
cf3cd43d CJW |
3940 | if (TARGET_LINUX_ABI) |
3941 | error("cannot use indirect_call attribute under linux toolchain"); | |
3942 | ||
85a98076 KLC |
3943 | if (lookup_attribute ("noinline", new_attrs) == NULL) |
3944 | new_attrs = tree_cons (get_identifier ("noinline"), NULL, new_attrs); | |
3945 | if (lookup_attribute ("noclone", new_attrs) == NULL) | |
3946 | new_attrs = tree_cons (get_identifier ("noclone"), NULL, new_attrs); | |
3947 | ||
3948 | if (!TREE_PUBLIC (decl)) | |
3949 | error("indirect_call attribute can't apply for static function"); | |
3950 | ||
3951 | *attributes = new_attrs; | |
3952 | } | |
3953 | ||
9304f876 CJW |
3954 | /* For function declaration, we need to check isr-specific attributes: |
3955 | 1. Call nds32_check_isr_attrs_conflict() to check any conflict. | |
3956 | 2. Check valid integer value for interrupt/exception. | |
3957 | 3. Check valid integer value for reset. | |
3958 | 4. Check valid function for nmi/warm. */ | |
3959 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
3960 | { | |
3961 | tree func_attrs; | |
3962 | tree intr, excp, reset; | |
3963 | ||
3964 | /* Pick up function attributes. */ | |
3965 | func_attrs = *attributes; | |
3966 | ||
3967 | /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */ | |
3968 | nds32_check_isr_attrs_conflict (decl, func_attrs); | |
3969 | ||
3970 | /* Now we are starting to check valid id value | |
8a498f99 CJW |
3971 | for interrupt/exception/reset. |
3972 | Note that we ONLY check its validity here. | |
3973 | To construct isr vector information, it is still performed | |
3974 | by nds32_construct_isr_vectors_information(). */ | |
9304f876 CJW |
3975 | intr = lookup_attribute ("interrupt", func_attrs); |
3976 | excp = lookup_attribute ("exception", func_attrs); | |
3977 | reset = lookup_attribute ("reset", func_attrs); | |
3978 | ||
a4931745 CJW |
3979 | /* The following code may use attribute arguments. If there is no |
3980 | argument from source code, it will cause segmentation fault. | |
3981 | Therefore, return dircetly and report error message later. */ | |
3982 | if ((intr && TREE_VALUE (intr) == NULL) | |
3983 | || (excp && TREE_VALUE (excp) == NULL) | |
3984 | || (reset && TREE_VALUE (reset) == NULL)) | |
3985 | return; | |
3986 | ||
3987 | /* ------------------------------------------------------------- */ | |
3988 | /* FIXME: | |
3989 | FOR BACKWARD COMPATIBILITY, we need to support following patterns: | |
3990 | ||
3991 | __attribute__((interrupt("XXX;YYY;id=ZZZ"))) | |
3992 | __attribute__((exception("XXX;YYY;id=ZZZ"))) | |
3993 | __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) | |
3994 | ||
3995 | If interrupt/exception/reset appears and its argument is a | |
3996 | STRING_CST, we will use other functions to parse string in the | |
3997 | nds32_construct_isr_vectors_information() and then set necessary | |
3998 | isr information in the nds32_isr_vectors[] array. Here we can | |
3999 | just return immediately to avoid new-syntax checking. */ | |
4000 | if (intr != NULL_TREE | |
4001 | && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST) | |
4002 | return; | |
4003 | if (excp != NULL_TREE | |
4004 | && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST) | |
4005 | return; | |
4006 | if (reset != NULL_TREE | |
4007 | && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST) | |
4008 | return; | |
4009 | /* ------------------------------------------------------------- */ | |
4010 | ||
9304f876 CJW |
4011 | if (intr || excp) |
4012 | { | |
4013 | /* Deal with interrupt/exception. */ | |
4014 | tree id_list; | |
4015 | unsigned int lower_bound, upper_bound; | |
4016 | ||
4017 | /* The way to handle interrupt or exception is the same, | |
4018 | we just need to take care of actual vector number. | |
4019 | For interrupt(0..63), the actual vector number is (9..72). | |
4020 | For exception(1..8), the actual vector number is (1..8). */ | |
4021 | lower_bound = (intr) ? (0) : (1); | |
4022 | upper_bound = (intr) ? (63) : (8); | |
4023 | ||
4024 | /* Prepare id list so that we can traverse id value. */ | |
4025 | id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp)); | |
4026 | ||
4027 | /* 2. Check valid integer value for interrupt/exception. */ | |
4028 | while (id_list) | |
4029 | { | |
4030 | tree id; | |
4031 | ||
4032 | /* Pick up each vector id value. */ | |
4033 | id = TREE_VALUE (id_list); | |
4034 | /* Issue error if it is not a valid integer value. */ | |
4035 | if (TREE_CODE (id) != INTEGER_CST | |
8e6cdc90 RS |
4036 | || wi::ltu_p (wi::to_wide (id), lower_bound) |
4037 | || wi::gtu_p (wi::to_wide (id), upper_bound)) | |
9304f876 CJW |
4038 | error ("invalid id value for interrupt/exception attribute"); |
4039 | ||
4040 | /* Advance to next id. */ | |
4041 | id_list = TREE_CHAIN (id_list); | |
4042 | } | |
4043 | } | |
4044 | else if (reset) | |
4045 | { | |
4046 | /* Deal with reset. */ | |
4047 | tree id_list; | |
4048 | tree id; | |
4049 | tree nmi, warm; | |
4050 | unsigned int lower_bound; | |
4051 | unsigned int upper_bound; | |
4052 | ||
4053 | /* Prepare id_list and identify id value so that | |
4054 | we can check if total number of vectors is valid. */ | |
4055 | id_list = TREE_VALUE (reset); | |
4056 | id = TREE_VALUE (id_list); | |
4057 | ||
4058 | /* The maximum numbers for user's interrupt is 64. */ | |
4059 | lower_bound = 0; | |
4060 | upper_bound = 64; | |
4061 | ||
4062 | /* 3. Check valid integer value for reset. */ | |
4063 | if (TREE_CODE (id) != INTEGER_CST | |
8e6cdc90 RS |
4064 | || wi::ltu_p (wi::to_wide (id), lower_bound) |
4065 | || wi::gtu_p (wi::to_wide (id), upper_bound)) | |
9304f876 CJW |
4066 | error ("invalid id value for reset attribute"); |
4067 | ||
4068 | /* 4. Check valid function for nmi/warm. */ | |
4069 | nmi = lookup_attribute ("nmi", func_attrs); | |
4070 | warm = lookup_attribute ("warm", func_attrs); | |
4071 | ||
4072 | if (nmi != NULL_TREE) | |
4073 | { | |
4074 | tree nmi_func_list; | |
4075 | tree nmi_func; | |
4076 | ||
4077 | nmi_func_list = TREE_VALUE (nmi); | |
4078 | nmi_func = TREE_VALUE (nmi_func_list); | |
4079 | ||
4080 | /* Issue error if it is not a valid nmi function. */ | |
4081 | if (TREE_CODE (nmi_func) != IDENTIFIER_NODE) | |
4082 | error ("invalid nmi function for reset attribute"); | |
4083 | } | |
4084 | ||
4085 | if (warm != NULL_TREE) | |
4086 | { | |
4087 | tree warm_func_list; | |
4088 | tree warm_func; | |
4089 | ||
4090 | warm_func_list = TREE_VALUE (warm); | |
4091 | warm_func = TREE_VALUE (warm_func_list); | |
4092 | ||
4093 | /* Issue error if it is not a valid warm function. */ | |
4094 | if (TREE_CODE (warm_func) != IDENTIFIER_NODE) | |
4095 | error ("invalid warm function for reset attribute"); | |
4096 | } | |
4097 | } | |
4098 | else | |
4099 | { | |
4100 | /* No interrupt, exception, or reset attribute is set. */ | |
4101 | return; | |
4102 | } | |
4103 | } | |
4104 | } | |
4105 | ||
4106 | static bool | |
4107 | nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED, | |
4108 | tree pop_target ATTRIBUTE_UNUSED) | |
4109 | { | |
4110 | /* Currently, we do not parse any pragma target by ourself, | |
4111 | so just simply return false. */ | |
4112 | return false; | |
4113 | } | |
4114 | ||
4115 | static void | |
4116 | nds32_option_override (void) | |
4117 | { | |
4118 | /* After all the command options have been parsed, | |
4119 | we shall deal with some flags for changing compiler settings. */ | |
4120 | ||
4121 | /* At first, we check if we have to strictly | |
4122 | set some flags based on ISA family. */ | |
4123 | if (TARGET_ISA_V2) | |
4124 | { | |
4125 | /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */ | |
4126 | target_flags &= ~MASK_V3PUSH; | |
4127 | } | |
4128 | if (TARGET_ISA_V3) | |
4129 | { | |
37d8f611 CJW |
4130 | /* If this is ARCH_V3J, we need to enable TARGET_REDUCED_REGS. */ |
4131 | if (nds32_arch_option == ARCH_V3J) | |
4132 | target_flags |= MASK_REDUCED_REGS; | |
9304f876 CJW |
4133 | } |
4134 | if (TARGET_ISA_V3M) | |
4135 | { | |
4136 | /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */ | |
4137 | target_flags |= MASK_REDUCED_REGS; | |
aa4b851c CJW |
4138 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */ |
4139 | target_flags &= ~MASK_EXT_PERF; | |
4140 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */ | |
4141 | target_flags &= ~MASK_EXT_PERF2; | |
4142 | /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */ | |
4143 | target_flags &= ~MASK_EXT_STRING; | |
b26fa4f9 KLC |
4144 | |
4145 | if (flag_pic) | |
4146 | error ("not support -fpic option for v3m toolchain"); | |
9304f876 CJW |
4147 | } |
4148 | ||
4149 | /* See if we are using reduced-set registers: | |
4150 | $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31 | |
4151 | If so, we must forbid using $r11~$r14, $r16~$r27. */ | |
4152 | if (TARGET_REDUCED_REGS) | |
4153 | { | |
4154 | int r; | |
4155 | ||
4156 | /* Prevent register allocator from | |
8a498f99 | 4157 | choosing it as doing register allocation. */ |
9304f876 CJW |
4158 | for (r = 11; r <= 14; r++) |
4159 | fixed_regs[r] = call_used_regs[r] = 1; | |
4160 | for (r = 16; r <= 27; r++) | |
4161 | fixed_regs[r] = call_used_regs[r] = 1; | |
4162 | } | |
4163 | ||
2140297c CJW |
4164 | /* See if user explicitly would like to use fp-as-gp optimization. |
4165 | If so, we must prevent $fp from being allocated | |
4166 | during register allocation. */ | |
4167 | if (TARGET_FORCE_FP_AS_GP) | |
4168 | fixed_regs[FP_REGNUM] = call_used_regs[FP_REGNUM] = 1; | |
4169 | ||
9304f876 CJW |
4170 | if (!TARGET_16_BIT) |
4171 | { | |
4172 | /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */ | |
4173 | target_flags &= ~MASK_V3PUSH; | |
4174 | } | |
4175 | ||
e2286268 MC |
4176 | if (TARGET_HARD_FLOAT && !(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) |
4177 | { | |
4178 | if (nds32_arch_option == ARCH_V3S || nds32_arch_option == ARCH_V3F) | |
4179 | error ("Disable FPU ISA, " | |
4180 | "the ABI option must be enable '-mfloat-abi=soft'"); | |
4181 | else | |
4182 | error ("'-mabi=2fp+' option only support when FPU available, " | |
4183 | "must be enable '-mext-fpu-sp' or '-mext-fpu-dp'"); | |
4184 | } | |
4185 | ||
19c93809 | 4186 | nds32_init_rtx_costs (); |
c4d8d050 CJW |
4187 | |
4188 | nds32_register_passes (); | |
9304f876 CJW |
4189 | } |
4190 | ||
4191 | \f | |
4192 | /* Miscellaneous Parameters. */ | |
4193 | ||
823835a9 CJW |
4194 | static rtx_insn * |
4195 | nds32_md_asm_adjust (vec<rtx> &outputs ATTRIBUTE_UNUSED, | |
4196 | vec<rtx> &inputs ATTRIBUTE_UNUSED, | |
4197 | vec<const char *> &constraints ATTRIBUTE_UNUSED, | |
4198 | vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs) | |
4199 | { | |
b28c01ab CJW |
4200 | if (!flag_inline_asm_r15) |
4201 | { | |
4202 | clobbers.safe_push (gen_rtx_REG (SImode, TA_REGNUM)); | |
4203 | SET_HARD_REG_BIT (clobbered_regs, TA_REGNUM); | |
4204 | } | |
823835a9 CJW |
4205 | return NULL; |
4206 | } | |
4207 | ||
9304f876 CJW |
4208 | static void |
4209 | nds32_init_builtins (void) | |
4210 | { | |
aaa44d2d | 4211 | nds32_init_builtins_impl (); |
9304f876 CJW |
4212 | } |
4213 | ||
7a12ea32 MC |
4214 | static tree |
4215 | nds32_builtin_decl (unsigned code, bool initialize_p) | |
4216 | { | |
4217 | /* Implement in nds32-intrinsic.c. */ | |
4218 | return nds32_builtin_decl_impl (code, initialize_p); | |
4219 | } | |
4220 | ||
9304f876 CJW |
4221 | static rtx |
4222 | nds32_expand_builtin (tree exp, | |
4223 | rtx target, | |
aaa44d2d | 4224 | rtx subtarget, |
ef4bddc2 | 4225 | machine_mode mode, |
aaa44d2d | 4226 | int ignore) |
9304f876 | 4227 | { |
aaa44d2d | 4228 | return nds32_expand_builtin_impl (exp, target, subtarget, mode, ignore); |
9304f876 CJW |
4229 | } |
4230 | ||
cf3cd43d CJW |
4231 | /* Implement TARGET_INIT_LIBFUNCS. */ |
4232 | static void | |
4233 | nds32_init_libfuncs (void) | |
4234 | { | |
4235 | if (TARGET_LINUX_ABI) | |
4236 | init_sync_libfuncs (UNITS_PER_WORD); | |
4237 | } | |
9304f876 CJW |
4238 | |
4239 | /* ------------------------------------------------------------------------ */ | |
4240 | ||
4241 | /* PART 4: Implemet extern function definitions, | |
4242 | the prototype is in nds32-protos.h. */ | |
72b7e5e1 KC |
4243 | \f |
4244 | /* Run-time Target Specification. */ | |
4245 | ||
4246 | void | |
4247 | nds32_cpu_cpp_builtins(struct cpp_reader *pfile) | |
4248 | { | |
4249 | #define builtin_define(TXT) cpp_define (pfile, TXT) | |
4250 | #define builtin_assert(TXT) cpp_assert (pfile, TXT) | |
4251 | builtin_define ("__nds32__"); | |
4252 | builtin_define ("__NDS32__"); | |
4253 | ||
a4931745 CJW |
4254 | /* We need to provide builtin macro to describe the size of |
4255 | each vector for interrupt handler under elf toolchain. */ | |
4256 | if (!TARGET_LINUX_ABI) | |
4257 | { | |
4258 | if (TARGET_ISR_VECTOR_SIZE_4_BYTE) | |
4259 | builtin_define ("__NDS32_ISR_VECTOR_SIZE_4__"); | |
4260 | else | |
4261 | builtin_define ("__NDS32_ISR_VECTOR_SIZE_16__"); | |
4262 | } | |
4263 | ||
e2286268 MC |
4264 | if (TARGET_HARD_FLOAT) |
4265 | builtin_define ("__NDS32_ABI_2FP_PLUS__"); | |
4266 | else | |
4267 | builtin_define ("__NDS32_ABI_2__"); | |
4268 | ||
72b7e5e1 KC |
4269 | if (TARGET_ISA_V2) |
4270 | builtin_define ("__NDS32_ISA_V2__"); | |
4271 | if (TARGET_ISA_V3) | |
4272 | builtin_define ("__NDS32_ISA_V3__"); | |
4273 | if (TARGET_ISA_V3M) | |
4274 | builtin_define ("__NDS32_ISA_V3M__"); | |
4275 | ||
e2286268 MC |
4276 | if (TARGET_FPU_SINGLE) |
4277 | builtin_define ("__NDS32_EXT_FPU_SP__"); | |
4278 | if (TARGET_FPU_DOUBLE) | |
4279 | builtin_define ("__NDS32_EXT_FPU_DP__"); | |
4280 | ||
4281 | if (TARGET_EXT_FPU_FMA) | |
4282 | builtin_define ("__NDS32_EXT_FPU_FMA__"); | |
4283 | if (NDS32_EXT_FPU_DOT_E) | |
4284 | builtin_define ("__NDS32_EXT_FPU_DOT_E__"); | |
4285 | if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
4286 | { | |
4287 | switch (nds32_fp_regnum) | |
4288 | { | |
4289 | case 0: | |
4290 | case 4: | |
4291 | builtin_define ("__NDS32_EXT_FPU_CONFIG_0__"); | |
4292 | break; | |
4293 | case 1: | |
4294 | case 5: | |
4295 | builtin_define ("__NDS32_EXT_FPU_CONFIG_1__"); | |
4296 | break; | |
4297 | case 2: | |
4298 | case 6: | |
4299 | builtin_define ("__NDS32_EXT_FPU_CONFIG_2__"); | |
4300 | break; | |
4301 | case 3: | |
4302 | case 7: | |
4303 | builtin_define ("__NDS32_EXT_FPU_CONFIG_3__"); | |
4304 | break; | |
4305 | default: | |
4306 | abort (); | |
4307 | } | |
4308 | } | |
4309 | ||
72b7e5e1 KC |
4310 | if (TARGET_BIG_ENDIAN) |
4311 | builtin_define ("__NDS32_EB__"); | |
4312 | else | |
4313 | builtin_define ("__NDS32_EL__"); | |
4314 | ||
4315 | if (TARGET_REDUCED_REGS) | |
4316 | builtin_define ("__NDS32_REDUCED_REGS__"); | |
4317 | if (TARGET_CMOV) | |
4318 | builtin_define ("__NDS32_CMOV__"); | |
4319 | if (TARGET_EXT_PERF) | |
4320 | builtin_define ("__NDS32_EXT_PERF__"); | |
4321 | if (TARGET_EXT_PERF2) | |
4322 | builtin_define ("__NDS32_EXT_PERF2__"); | |
4323 | if (TARGET_EXT_STRING) | |
4324 | builtin_define ("__NDS32_EXT_STRING__"); | |
4325 | if (TARGET_16_BIT) | |
4326 | builtin_define ("__NDS32_16_BIT__"); | |
4327 | if (TARGET_GP_DIRECT) | |
4328 | builtin_define ("__NDS32_GP_DIRECT__"); | |
ff77f6e8 KC |
4329 | if (TARGET_VH) |
4330 | builtin_define ("__NDS32_VH__"); | |
7c32ef41 MC |
4331 | if (NDS32_EXT_DSP_P ()) |
4332 | builtin_define ("__NDS32_EXT_DSP__"); | |
72b7e5e1 KC |
4333 | |
4334 | if (TARGET_BIG_ENDIAN) | |
4335 | builtin_define ("__big_endian__"); | |
4336 | ||
4337 | builtin_assert ("cpu=nds32"); | |
4338 | builtin_assert ("machine=nds32"); | |
e2286268 MC |
4339 | |
4340 | if (TARGET_HARD_FLOAT) | |
4341 | builtin_define ("__NDS32_ABI_2FP_PLUS"); | |
4342 | else | |
4343 | builtin_define ("__NDS32_ABI_2"); | |
4344 | ||
72b7e5e1 KC |
4345 | #undef builtin_define |
4346 | #undef builtin_assert | |
4347 | } | |
4348 | ||
9304f876 CJW |
4349 | \f |
4350 | /* Defining Data Structures for Per-function Information. */ | |
4351 | ||
4352 | void | |
4353 | nds32_init_expanders (void) | |
4354 | { | |
4355 | /* Arrange to initialize and mark the machine per-function status. */ | |
4356 | init_machine_status = nds32_init_machine_status; | |
4357 | } | |
4358 | ||
4359 | \f | |
4360 | /* Register Usage. */ | |
4361 | ||
5e6ae0cc CJW |
4362 | /* -- Order of Allocation of Registers. */ |
4363 | ||
4364 | void | |
4365 | nds32_adjust_reg_alloc_order (void) | |
4366 | { | |
4367 | const int nds32_reg_alloc_order[] = REG_ALLOC_ORDER; | |
4368 | ||
4369 | /* Copy the default register allocation order, which is designed | |
4370 | to optimize for code size. */ | |
4371 | memcpy(reg_alloc_order, nds32_reg_alloc_order, sizeof (reg_alloc_order)); | |
4372 | ||
4373 | /* Adjust few register allocation order when optimizing for speed. */ | |
4374 | if (!optimize_size) | |
4375 | { | |
4376 | memcpy (reg_alloc_order, nds32_reg_alloc_order_for_speed, | |
4377 | sizeof (nds32_reg_alloc_order_for_speed)); | |
4378 | } | |
4379 | } | |
4380 | ||
9304f876 CJW |
4381 | /* -- How Values Fit in Registers. */ |
4382 | ||
e2286268 MC |
4383 | static unsigned |
4384 | nds32_hard_regno_nregs (unsigned regno ATTRIBUTE_UNUSED, | |
4385 | machine_mode mode) | |
4386 | { | |
4387 | return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); | |
4388 | } | |
4389 | ||
f939c3e6 RS |
4390 | /* Implement TARGET_HARD_REGNO_MODE_OK. */ |
4391 | ||
4392 | static bool | |
4393 | nds32_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
9304f876 | 4394 | { |
65e87462 | 4395 | if (regno >= FIRST_PSEUDO_REGISTER) |
f939c3e6 | 4396 | return true; |
9304f876 | 4397 | |
e2286268 MC |
4398 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) && NDS32_IS_FPR_REGNUM (regno)) |
4399 | { | |
4400 | if (NDS32_IS_EXT_FPR_REGNUM(regno)) | |
4401 | return (NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) && (mode == DFmode)); | |
4402 | else if (mode == SFmode || mode == SImode) | |
4403 | return NDS32_FPR_REGNO_OK_FOR_SINGLE (regno); | |
4404 | else if (mode == DFmode) | |
4405 | return NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno); | |
4406 | ||
4407 | return false; | |
4408 | } | |
4409 | ||
4410 | /* Restrict double-word quantities to even register pairs. */ | |
4411 | if (regno <= NDS32_LAST_GPR_REGNUM) | |
4412 | return (targetm.hard_regno_nregs (regno, mode) == 1 | |
4413 | || !((regno) & 1)); | |
4414 | ||
f939c3e6 | 4415 | return false; |
9304f876 CJW |
4416 | } |
4417 | ||
99e1629f RS |
4418 | /* Implement TARGET_MODES_TIEABLE_P. We can use general registers to |
4419 | tie QI/HI/SI modes together. */ | |
4420 | ||
4421 | static bool | |
4422 | nds32_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
4423 | { | |
e2286268 MC |
4424 | if ((GET_MODE_CLASS (mode1) == MODE_INT |
4425 | && GET_MODE_CLASS (mode2) == MODE_INT) | |
4426 | && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD | |
4427 | && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD) | |
4428 | return true; | |
4429 | ||
4430 | if (GET_MODE_SIZE (mode1) == GET_MODE_SIZE (mode2)) | |
4431 | { | |
4432 | if ((TARGET_FPU_SINGLE && !TARGET_FPU_DOUBLE) | |
4433 | && (mode1 == DFmode || mode2 == DFmode)) | |
4434 | return false; | |
4435 | else | |
4436 | return true; | |
4437 | } | |
4438 | ||
4439 | return false; | |
99e1629f | 4440 | } |
9304f876 CJW |
4441 | \f |
4442 | /* Register Classes. */ | |
4443 | ||
4444 | enum reg_class | |
4445 | nds32_regno_reg_class (int regno) | |
4446 | { | |
4447 | /* Refer to nds32.h for more register class details. */ | |
4448 | ||
4449 | if (regno >= 0 && regno <= 7) | |
4450 | return LOW_REGS; | |
4451 | else if (regno >= 8 && regno <= 11) | |
4452 | return MIDDLE_REGS; | |
4453 | else if (regno >= 12 && regno <= 14) | |
4454 | return HIGH_REGS; | |
4455 | else if (regno == 15) | |
4456 | return R15_TA_REG; | |
4457 | else if (regno >= 16 && regno <= 19) | |
4458 | return MIDDLE_REGS; | |
4459 | else if (regno >= 20 && regno <= 31) | |
4460 | return HIGH_REGS; | |
4461 | else if (regno == 32 || regno == 33) | |
e2286268 MC |
4462 | { |
4463 | /* $SFP and $AP is FRAME_REGS in fact, However prevent IRA don't | |
4464 | know how to allocate register for $SFP and $AP, just tell IRA they | |
4465 | are GENERAL_REGS, and ARM do this hack too. */ | |
4466 | return GENERAL_REGS; | |
4467 | } | |
4468 | else if (regno >= 34 && regno <= 97) | |
4469 | return FP_REGS; | |
9304f876 CJW |
4470 | else |
4471 | return NO_REGS; | |
4472 | } | |
4473 | ||
4474 | \f | |
4475 | /* Stack Layout and Calling Conventions. */ | |
4476 | ||
4477 | /* -- Basic Stack Layout. */ | |
4478 | ||
ca3a4a55 CJW |
4479 | rtx |
4480 | nds32_dynamic_chain_address (rtx frameaddr) | |
4481 | { | |
4482 | if (TARGET_V3PUSH) | |
4483 | { | |
4484 | /* If -mv3push is specified, we push $fp, $gp, and $lp into stack. | |
4485 | We can access dynamic chain address from stack by [$fp - 12]. */ | |
4486 | return plus_constant (Pmode, frameaddr, -12); | |
4487 | } | |
4488 | else | |
4489 | { | |
4490 | /* For general case we push $fp and $lp into stack at prologue. | |
4491 | We can access dynamic chain address from stack by [$fp - 8]. */ | |
4492 | return plus_constant (Pmode, frameaddr, -8); | |
4493 | } | |
4494 | } | |
4495 | ||
9304f876 CJW |
4496 | rtx |
4497 | nds32_return_addr_rtx (int count, | |
ca3a4a55 | 4498 | rtx frameaddr) |
9304f876 | 4499 | { |
ca3a4a55 CJW |
4500 | int offset; |
4501 | rtx addr; | |
4502 | ||
9304f876 | 4503 | if (count != 0) |
ca3a4a55 CJW |
4504 | { |
4505 | /* In nds32 ABI design, we can expect that $lp is always available | |
4506 | from stack by [$fp - 4] location. */ | |
4507 | offset = -4; | |
4508 | addr = plus_constant (Pmode, frameaddr, offset); | |
4509 | addr = memory_address (Pmode, addr); | |
4510 | ||
4511 | return gen_rtx_MEM (Pmode, addr); | |
4512 | } | |
9304f876 CJW |
4513 | |
4514 | /* If count == 0, it means we are at current frame, | |
4515 | the return address is $r30 ($lp). */ | |
4516 | return get_hard_reg_initial_val (Pmode, LP_REGNUM); | |
4517 | } | |
4518 | ||
4519 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
4520 | ||
4521 | HOST_WIDE_INT | |
4522 | nds32_initial_elimination_offset (unsigned int from_reg, unsigned int to_reg) | |
4523 | { | |
4524 | HOST_WIDE_INT offset; | |
4525 | ||
4526 | /* Compute and setup stack frame size. | |
4527 | The result will be in cfun->machine. */ | |
4528 | nds32_compute_stack_frame (); | |
4529 | ||
4530 | /* Remember to consider | |
ca3a4a55 CJW |
4531 | cfun->machine->callee_saved_area_gpr_padding_bytes and |
4532 | cfun->machine->eh_return_data_regs_size | |
9304f876 CJW |
4533 | when calculating offset. */ |
4534 | if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
4535 | { | |
4536 | offset = (cfun->machine->fp_size | |
8a498f99 | 4537 | + cfun->machine->gp_size |
9304f876 | 4538 | + cfun->machine->lp_size |
c457f751 CJW |
4539 | + cfun->machine->callee_saved_gpr_regs_size |
4540 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
e2286268 | 4541 | + cfun->machine->callee_saved_fpr_regs_size |
ca3a4a55 | 4542 | + cfun->machine->eh_return_data_regs_size |
9304f876 CJW |
4543 | + cfun->machine->local_size |
4544 | + cfun->machine->out_args_size); | |
4545 | } | |
4546 | else if (from_reg == ARG_POINTER_REGNUM | |
4547 | && to_reg == HARD_FRAME_POINTER_REGNUM) | |
4548 | { | |
4549 | offset = 0; | |
4550 | } | |
4551 | else if (from_reg == FRAME_POINTER_REGNUM | |
4552 | && to_reg == STACK_POINTER_REGNUM) | |
4553 | { | |
4554 | offset = (cfun->machine->local_size + cfun->machine->out_args_size); | |
4555 | } | |
4556 | else if (from_reg == FRAME_POINTER_REGNUM | |
4557 | && to_reg == HARD_FRAME_POINTER_REGNUM) | |
4558 | { | |
4559 | offset = (-1) * (cfun->machine->fp_size | |
4560 | + cfun->machine->gp_size | |
4561 | + cfun->machine->lp_size | |
c457f751 | 4562 | + cfun->machine->callee_saved_gpr_regs_size |
e2286268 | 4563 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
ca3a4a55 CJW |
4564 | + cfun->machine->callee_saved_fpr_regs_size |
4565 | + cfun->machine->eh_return_data_regs_size); | |
9304f876 CJW |
4566 | } |
4567 | else | |
4568 | { | |
4569 | gcc_unreachable (); | |
4570 | } | |
4571 | ||
4572 | return offset; | |
4573 | } | |
4574 | ||
4575 | /* -- Passing Arguments in Registers. */ | |
4576 | ||
4577 | void | |
4578 | nds32_init_cumulative_args (CUMULATIVE_ARGS *cum, | |
4579 | tree fntype ATTRIBUTE_UNUSED, | |
4580 | rtx libname ATTRIBUTE_UNUSED, | |
4581 | tree fndecl ATTRIBUTE_UNUSED, | |
4582 | int n_named_args ATTRIBUTE_UNUSED) | |
4583 | { | |
e2286268 MC |
4584 | /* Initial available registers. The values are offset against |
4585 | NDS32_GPR_ARG_FIRST_REGNUM and NDS32_FPR_ARG_FIRST_REGNUM | |
9304f876 | 4586 | for passing arguments. */ |
9d93cc24 | 4587 | cum->gpr_offset = 0; |
e2286268 | 4588 | cum->fpr_offset = 0; |
9304f876 CJW |
4589 | } |
4590 | ||
4591 | /* -- Function Entry and Exit. */ | |
4592 | ||
4593 | /* Function for normal multiple push prologue. */ | |
4594 | void | |
4595 | nds32_expand_prologue (void) | |
4596 | { | |
4597 | int fp_adjust; | |
4598 | int sp_adjust; | |
a6c7e777 | 4599 | unsigned Rb, Re; |
9304f876 | 4600 | |
9304f876 CJW |
4601 | /* Compute and setup stack frame size. |
4602 | The result will be in cfun->machine. */ | |
4603 | nds32_compute_stack_frame (); | |
4604 | ||
2140297c CJW |
4605 | /* Check frame_pointer_needed again to prevent fp is need after reload. */ |
4606 | if (frame_pointer_needed) | |
4607 | cfun->machine->fp_as_gp_p = false; | |
4608 | ||
557430f1 CJW |
4609 | /* If this is a variadic function, first we need to push argument |
4610 | registers that hold the unnamed argument value. */ | |
4611 | if (cfun->machine->va_args_size != 0) | |
4612 | { | |
a6c7e777 MC |
4613 | Rb = cfun->machine->va_args_first_regno; |
4614 | Re = cfun->machine->va_args_last_regno; | |
4615 | /* No need to push $fp, $gp, or $lp. */ | |
4616 | nds32_emit_stack_push_multiple (Rb, Re, false, false, false, true); | |
557430f1 CJW |
4617 | |
4618 | /* We may also need to adjust stack pointer for padding bytes | |
4619 | because varargs may cause $sp not 8-byte aligned. */ | |
4620 | if (cfun->machine->va_args_area_padding_bytes) | |
4621 | { | |
4622 | /* Generate sp adjustment instruction. */ | |
4623 | sp_adjust = cfun->machine->va_args_area_padding_bytes; | |
557430f1 | 4624 | |
a6c7e777 MC |
4625 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4626 | stack_pointer_rtx, | |
4627 | -1 * sp_adjust); | |
557430f1 CJW |
4628 | } |
4629 | } | |
4630 | ||
9304f876 CJW |
4631 | /* If the function is 'naked', |
4632 | we do not have to generate prologue code fragment. */ | |
b26fa4f9 | 4633 | if (cfun->machine->naked_p && !flag_pic) |
9304f876 CJW |
4634 | return; |
4635 | ||
4636 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
4637 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
4638 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
4639 | |
4640 | /* If $fp, $gp, $lp, and all callee-save registers are NOT required | |
4641 | to be saved, we don't have to create multiple push instruction. | |
4642 | Otherwise, a multiple push instruction is needed. */ | |
a6c7e777 MC |
4643 | if (!(Rb == SP_REGNUM && Re == SP_REGNUM |
4644 | && cfun->machine->fp_size == 0 | |
4645 | && cfun->machine->gp_size == 0 | |
4646 | && cfun->machine->lp_size == 0)) | |
9304f876 CJW |
4647 | { |
4648 | /* Create multiple push instruction rtx. */ | |
a6c7e777 MC |
4649 | nds32_emit_stack_push_multiple ( |
4650 | Rb, Re, | |
4651 | cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size, | |
4652 | false); | |
9304f876 CJW |
4653 | } |
4654 | ||
ca3a4a55 CJW |
4655 | /* Save eh data registers. */ |
4656 | if (cfun->machine->use_eh_return_p) | |
4657 | { | |
4658 | Rb = cfun->machine->eh_return_data_first_regno; | |
4659 | Re = cfun->machine->eh_return_data_last_regno; | |
4660 | ||
4661 | /* No need to push $fp, $gp, or $lp. | |
4662 | Also, this is not variadic arguments push. */ | |
4663 | nds32_emit_stack_push_multiple (Rb, Re, false, false, false, false); | |
4664 | } | |
4665 | ||
9304f876 CJW |
4666 | /* Check frame_pointer_needed to see |
4667 | if we shall emit fp adjustment instruction. */ | |
4668 | if (frame_pointer_needed) | |
4669 | { | |
4670 | /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size) | |
8a498f99 | 4671 | + (4 * callee-saved-registers) |
ca3a4a55 | 4672 | + (4 * exception-handling-data-registers) |
8a498f99 CJW |
4673 | Note: No need to adjust |
4674 | cfun->machine->callee_saved_area_gpr_padding_bytes, | |
4675 | because, at this point, stack pointer is just | |
4676 | at the position after push instruction. */ | |
9304f876 CJW |
4677 | fp_adjust = cfun->machine->fp_size |
4678 | + cfun->machine->gp_size | |
4679 | + cfun->machine->lp_size | |
ca3a4a55 CJW |
4680 | + cfun->machine->callee_saved_gpr_regs_size |
4681 | + cfun->machine->eh_return_data_regs_size; | |
7064dcad | 4682 | |
a6c7e777 MC |
4683 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, |
4684 | stack_pointer_rtx, | |
4685 | fp_adjust); | |
9304f876 CJW |
4686 | } |
4687 | ||
e2286268 MC |
4688 | /* Save fpu registers. */ |
4689 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
4690 | { | |
4691 | /* When $sp moved to bottom of stack, we need to check whether | |
4692 | the range of offset in the FPU instruction. */ | |
4693 | int fpr_offset = cfun->machine->local_size | |
4694 | + cfun->machine->out_args_size | |
4695 | + cfun->machine->callee_saved_fpr_regs_size; | |
4696 | ||
4697 | /* Check FPU instruction offset imm14s. */ | |
4698 | if (!satisfies_constraint_Is14 (GEN_INT (fpr_offset))) | |
4699 | { | |
4700 | int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes | |
4701 | + cfun->machine->callee_saved_fpr_regs_size; | |
4702 | ||
4703 | /* Save fpu registers, need to allocate stack space | |
4704 | for fpu callee registers. And now $sp position | |
4705 | on callee saved fpr registers. */ | |
4706 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4707 | stack_pointer_rtx, | |
4708 | -1 * fpr_space); | |
4709 | ||
4710 | /* Emit fpu store instruction, using [$sp + offset] store | |
4711 | fpu registers. */ | |
4712 | nds32_emit_push_fpr_callee_saved (0); | |
4713 | ||
4714 | /* Adjust $sp = $sp - local_size - out_args_size. */ | |
4715 | sp_adjust = cfun->machine->local_size | |
4716 | + cfun->machine->out_args_size; | |
4717 | ||
4718 | /* Allocate stack space for local size and out args size. */ | |
4719 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4720 | stack_pointer_rtx, | |
4721 | -1 * sp_adjust); | |
4722 | } | |
4723 | else | |
4724 | { | |
4725 | /* Offset range in Is14, so $sp moved to bottom of stack. */ | |
4726 | ||
4727 | /* Adjust $sp = $sp - local_size - out_args_size | |
4728 | - callee_saved_area_gpr_padding_bytes | |
4729 | - callee_saved_fpr_regs_size. */ | |
4730 | sp_adjust = cfun->machine->local_size | |
4731 | + cfun->machine->out_args_size | |
4732 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
4733 | + cfun->machine->callee_saved_fpr_regs_size; | |
4734 | ||
4735 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4736 | stack_pointer_rtx, | |
4737 | -1 * sp_adjust); | |
4738 | ||
4739 | /* Emit fpu store instruction, using [$sp + offset] store | |
4740 | fpu registers. */ | |
4741 | int fpr_position = cfun->machine->out_args_size | |
4742 | + cfun->machine->local_size; | |
4743 | nds32_emit_push_fpr_callee_saved (fpr_position); | |
4744 | } | |
4745 | } | |
4746 | else | |
4747 | { | |
4748 | /* Adjust $sp = $sp - local_size - out_args_size | |
4749 | - callee_saved_area_gpr_padding_bytes. */ | |
4750 | sp_adjust = cfun->machine->local_size | |
4751 | + cfun->machine->out_args_size | |
4752 | + cfun->machine->callee_saved_area_gpr_padding_bytes; | |
4753 | ||
4754 | /* sp_adjust value may be out of range of the addi instruction, | |
4755 | create alternative add behavior with TA_REGNUM if necessary, | |
4756 | using NEGATIVE value to tell that we are decreasing address. */ | |
4757 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4758 | stack_pointer_rtx, | |
4759 | -1 * sp_adjust); | |
4760 | } | |
9304f876 | 4761 | |
b26fa4f9 KLC |
4762 | /* Emit gp setup instructions for -fpic. */ |
4763 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) | |
4764 | nds32_emit_load_gp (); | |
4765 | ||
d057a470 CJW |
4766 | /* If user applies -mno-sched-prolog-epilog option, |
4767 | we need to prevent instructions of function body from being | |
4768 | scheduled with stack adjustment in prologue. */ | |
4769 | if (!flag_sched_prolog_epilog) | |
4770 | emit_insn (gen_blockage ()); | |
9304f876 CJW |
4771 | } |
4772 | ||
4773 | /* Function for normal multiple pop epilogue. */ | |
4774 | void | |
d6529176 | 4775 | nds32_expand_epilogue (bool sibcall_p) |
9304f876 CJW |
4776 | { |
4777 | int sp_adjust; | |
a6c7e777 | 4778 | unsigned Rb, Re; |
9304f876 CJW |
4779 | |
4780 | /* Compute and setup stack frame size. | |
4781 | The result will be in cfun->machine. */ | |
4782 | nds32_compute_stack_frame (); | |
4783 | ||
d057a470 CJW |
4784 | /* If user applies -mno-sched-prolog-epilog option, |
4785 | we need to prevent instructions of function body from being | |
4786 | scheduled with stack adjustment in epilogue. */ | |
4787 | if (!flag_sched_prolog_epilog) | |
4788 | emit_insn (gen_blockage ()); | |
9304f876 CJW |
4789 | |
4790 | /* If the function is 'naked', we do not have to generate | |
557430f1 CJW |
4791 | epilogue code fragment BUT 'ret' instruction. |
4792 | However, if this function is also a variadic function, | |
4793 | we need to create adjust stack pointer before 'ret' instruction. */ | |
9304f876 CJW |
4794 | if (cfun->machine->naked_p) |
4795 | { | |
557430f1 | 4796 | /* If this is a variadic function, we do not have to restore argument |
8a498f99 CJW |
4797 | registers but need to adjust stack pointer back to previous stack |
4798 | frame location before return. */ | |
557430f1 CJW |
4799 | if (cfun->machine->va_args_size != 0) |
4800 | { | |
4801 | /* Generate sp adjustment instruction. | |
4802 | We need to consider padding bytes here. */ | |
4803 | sp_adjust = cfun->machine->va_args_size | |
4804 | + cfun->machine->va_args_area_padding_bytes; | |
a6c7e777 MC |
4805 | |
4806 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4807 | stack_pointer_rtx, | |
4808 | sp_adjust); | |
557430f1 CJW |
4809 | } |
4810 | ||
03390cda | 4811 | /* Generate return instruction by using 'return_internal' pattern. |
8a498f99 | 4812 | Make sure this instruction is after gen_blockage(). */ |
d6529176 | 4813 | if (!sibcall_p) |
54c537e6 CJW |
4814 | { |
4815 | /* We need to further check attributes to determine whether | |
4816 | there should be return instruction at epilogue. | |
4817 | If the attribute naked exists but -mno-ret-in-naked-func | |
4818 | is issued, there is NO need to generate return instruction. */ | |
4819 | if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) | |
4820 | return; | |
4821 | ||
4822 | emit_jump_insn (gen_return_internal ()); | |
4823 | } | |
9304f876 CJW |
4824 | return; |
4825 | } | |
4826 | ||
4827 | if (frame_pointer_needed) | |
4828 | { | |
e2286268 MC |
4829 | /* Restore fpu registers. */ |
4830 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
4831 | { | |
4832 | int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes; | |
4833 | ||
4834 | /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) | |
4835 | - (4 * callee-saved-registers) | |
4836 | - (4 * exception-handling-data-registers) | |
4837 | - (4 * callee-saved-gpr-registers padding byte) | |
4838 | - (4 * callee-saved-fpr-registers) | |
4839 | Note: we want to adjust stack pointer | |
4840 | to the position for callee-saved fpr register, | |
4841 | And restore fpu register use .bi instruction to adjust $sp | |
4842 | from callee-saved fpr register to pop instruction. */ | |
4843 | sp_adjust = cfun->machine->fp_size | |
4844 | + cfun->machine->gp_size | |
4845 | + cfun->machine->lp_size | |
4846 | + cfun->machine->callee_saved_gpr_regs_size | |
ca3a4a55 | 4847 | + cfun->machine->eh_return_data_regs_size |
e2286268 MC |
4848 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
4849 | + cfun->machine->callee_saved_fpr_regs_size; | |
557430f1 | 4850 | |
e2286268 MC |
4851 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4852 | hard_frame_pointer_rtx, | |
4853 | -1 * sp_adjust); | |
4854 | ||
4855 | /* Emit fpu load instruction, using .bi instruction | |
4856 | load fpu registers. */ | |
4857 | nds32_emit_pop_fpr_callee_saved (gpr_padding); | |
4858 | } | |
4859 | else | |
4860 | { | |
4861 | /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) | |
4862 | - (4 * callee-saved-registers) | |
4863 | - (4 * exception-handling-data-registers) | |
4864 | Note: No need to adjust | |
4865 | cfun->machine->callee_saved_area_gpr_padding_bytes, | |
4866 | because we want to adjust stack pointer | |
4867 | to the position for pop instruction. */ | |
4868 | sp_adjust = cfun->machine->fp_size | |
4869 | + cfun->machine->gp_size | |
4870 | + cfun->machine->lp_size | |
ca3a4a55 CJW |
4871 | + cfun->machine->callee_saved_gpr_regs_size |
4872 | + cfun->machine->eh_return_data_regs_size; | |
e2286268 MC |
4873 | |
4874 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4875 | hard_frame_pointer_rtx, | |
4876 | -1 * sp_adjust); | |
4877 | } | |
9304f876 CJW |
4878 | } |
4879 | else | |
4880 | { | |
e2286268 MC |
4881 | /* Restore fpu registers. */ |
4882 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
4883 | { | |
4884 | int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes; | |
9304f876 | 4885 | |
e2286268 MC |
4886 | /* Adjust $sp = $sp + local_size + out_args_size. */ |
4887 | sp_adjust = cfun->machine->local_size | |
4888 | + cfun->machine->out_args_size; | |
a6c7e777 | 4889 | |
e2286268 MC |
4890 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4891 | stack_pointer_rtx, | |
4892 | sp_adjust); | |
4893 | ||
4894 | /* Emit fpu load instruction, using .bi instruction | |
4895 | load fpu registers, and adjust $sp from callee-saved fpr register | |
4896 | to callee-saved gpr register. */ | |
4897 | nds32_emit_pop_fpr_callee_saved (gpr_padding); | |
4898 | } | |
4899 | else | |
4900 | { | |
4901 | /* If frame pointer is NOT needed, | |
4902 | we cannot calculate the sp adjustment from frame pointer. | |
4903 | Instead, we calculate the adjustment by local_size, | |
4904 | out_args_size, and callee_saved_area_gpr_padding_bytes. | |
4905 | Notice that such sp adjustment value may be out of range, | |
4906 | so we have to deal with it as well. */ | |
4907 | ||
4908 | /* Adjust $sp = $sp + local_size + out_args_size | |
4909 | + callee_saved_area_gpr_padding_bytes. */ | |
4910 | sp_adjust = cfun->machine->local_size | |
4911 | + cfun->machine->out_args_size | |
4912 | + cfun->machine->callee_saved_area_gpr_padding_bytes; | |
4913 | ||
4914 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
4915 | stack_pointer_rtx, | |
4916 | sp_adjust); | |
4917 | } | |
9304f876 CJW |
4918 | } |
4919 | ||
ca3a4a55 CJW |
4920 | /* Restore eh data registers. */ |
4921 | if (cfun->machine->use_eh_return_p) | |
4922 | { | |
4923 | Rb = cfun->machine->eh_return_data_first_regno; | |
4924 | Re = cfun->machine->eh_return_data_last_regno; | |
4925 | ||
4926 | /* No need to pop $fp, $gp, or $lp. */ | |
4927 | nds32_emit_stack_pop_multiple (Rb, Re, false, false, false); | |
4928 | } | |
4929 | ||
9304f876 | 4930 | /* Get callee_first_regno and callee_last_regno. */ |
a6c7e777 MC |
4931 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
4932 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
4933 | |
4934 | /* If $fp, $gp, $lp, and all callee-save registers are NOT required | |
4935 | to be saved, we don't have to create multiple pop instruction. | |
4936 | Otherwise, a multiple pop instruction is needed. */ | |
a6c7e777 MC |
4937 | if (!(Rb == SP_REGNUM && Re == SP_REGNUM |
4938 | && cfun->machine->fp_size == 0 | |
4939 | && cfun->machine->gp_size == 0 | |
4940 | && cfun->machine->lp_size == 0)) | |
9304f876 CJW |
4941 | { |
4942 | /* Create multiple pop instruction rtx. */ | |
a6c7e777 MC |
4943 | nds32_emit_stack_pop_multiple ( |
4944 | Rb, Re, | |
4945 | cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size); | |
9304f876 CJW |
4946 | } |
4947 | ||
557430f1 CJW |
4948 | /* If this is a variadic function, we do not have to restore argument |
4949 | registers but need to adjust stack pointer back to previous stack | |
4950 | frame location before return. */ | |
4951 | if (cfun->machine->va_args_size != 0) | |
4952 | { | |
4953 | /* Generate sp adjustment instruction. | |
8a498f99 | 4954 | We need to consider padding bytes here. */ |
557430f1 CJW |
4955 | sp_adjust = cfun->machine->va_args_size |
4956 | + cfun->machine->va_args_area_padding_bytes; | |
557430f1 | 4957 | |
a6c7e777 MC |
4958 | nds32_emit_adjust_frame (stack_pointer_rtx, |
4959 | stack_pointer_rtx, | |
4960 | sp_adjust); | |
557430f1 CJW |
4961 | } |
4962 | ||
ca3a4a55 CJW |
4963 | /* If this function uses __builtin_eh_return, make stack adjustment |
4964 | for exception handler. */ | |
4965 | if (cfun->machine->use_eh_return_p) | |
4966 | { | |
4967 | /* We need to unwind the stack by the offset computed by | |
4968 | EH_RETURN_STACKADJ_RTX. However, at this point the CFA is | |
4969 | based on SP. Ideally we would update the SP and define the | |
4970 | CFA along the lines of: | |
4971 | ||
4972 | SP = SP + EH_RETURN_STACKADJ_RTX | |
4973 | (regnote CFA = SP - EH_RETURN_STACKADJ_RTX) | |
4974 | ||
4975 | However the dwarf emitter only understands a constant | |
4976 | register offset. | |
4977 | ||
4978 | The solution chosen here is to use the otherwise $ta ($r15) | |
4979 | as a temporary register to hold the current SP value. The | |
4980 | CFA is described using $ta then SP is modified. */ | |
4981 | ||
4982 | rtx ta_reg; | |
4983 | rtx insn; | |
4984 | ||
4985 | ta_reg = gen_rtx_REG (SImode, TA_REGNUM); | |
4986 | ||
4987 | insn = emit_move_insn (ta_reg, stack_pointer_rtx); | |
4988 | add_reg_note (insn, REG_CFA_DEF_CFA, ta_reg); | |
4989 | RTX_FRAME_RELATED_P (insn) = 1; | |
4990 | ||
4991 | emit_insn (gen_addsi3 (stack_pointer_rtx, | |
4992 | stack_pointer_rtx, | |
4993 | EH_RETURN_STACKADJ_RTX)); | |
4994 | ||
4995 | /* Ensure the assignment to $ta does not get optimized away. */ | |
4996 | emit_use (ta_reg); | |
4997 | } | |
4998 | ||
03390cda | 4999 | /* Generate return instruction. */ |
d6529176 CJW |
5000 | if (!sibcall_p) |
5001 | emit_jump_insn (gen_return_internal ()); | |
9304f876 CJW |
5002 | } |
5003 | ||
5004 | /* Function for v3push prologue. */ | |
5005 | void | |
5006 | nds32_expand_prologue_v3push (void) | |
5007 | { | |
5008 | int fp_adjust; | |
5009 | int sp_adjust; | |
e2286268 | 5010 | int fpr_space = 0; |
a6c7e777 | 5011 | unsigned Rb, Re; |
9304f876 | 5012 | |
9304f876 CJW |
5013 | /* Compute and setup stack frame size. |
5014 | The result will be in cfun->machine. */ | |
5015 | nds32_compute_stack_frame (); | |
5016 | ||
a6c7e777 MC |
5017 | if (cfun->machine->callee_saved_gpr_regs_size > 0) |
5018 | df_set_regs_ever_live (FP_REGNUM, 1); | |
5019 | ||
2140297c CJW |
5020 | /* Check frame_pointer_needed again to prevent fp is need after reload. */ |
5021 | if (frame_pointer_needed) | |
5022 | cfun->machine->fp_as_gp_p = false; | |
5023 | ||
9304f876 CJW |
5024 | /* If the function is 'naked', |
5025 | we do not have to generate prologue code fragment. */ | |
b26fa4f9 | 5026 | if (cfun->machine->naked_p && !flag_pic) |
9304f876 CJW |
5027 | return; |
5028 | ||
5029 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
5030 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
5031 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
5032 | |
5033 | /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available, | |
5034 | where imm8u has to be 8-byte alignment. */ | |
5035 | sp_adjust = cfun->machine->local_size | |
5036 | + cfun->machine->out_args_size | |
e2286268 MC |
5037 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
5038 | + cfun->machine->callee_saved_fpr_regs_size; | |
9304f876 CJW |
5039 | |
5040 | if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
5041 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)) | |
5042 | { | |
5043 | /* We can use 'push25 Re,imm8u'. */ | |
5044 | ||
88437f39 | 5045 | /* nds32_emit_stack_v3push(last_regno, sp_adjust), |
a6c7e777 MC |
5046 | the pattern 'stack_v3push' is implemented in nds32.md. */ |
5047 | nds32_emit_stack_v3push (Rb, Re, sp_adjust); | |
e2286268 MC |
5048 | |
5049 | /* Save fpu registers. */ | |
5050 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
5051 | { | |
5052 | /* Calculate fpr position. */ | |
5053 | int fpr_position = cfun->machine->local_size | |
5054 | + cfun->machine->out_args_size; | |
5055 | /* Emit fpu store instruction, using [$sp + offset] store | |
5056 | fpu registers. */ | |
5057 | nds32_emit_push_fpr_callee_saved (fpr_position); | |
5058 | } | |
5059 | ||
9304f876 | 5060 | /* Check frame_pointer_needed to see |
8a498f99 | 5061 | if we shall emit fp adjustment instruction. */ |
9304f876 CJW |
5062 | if (frame_pointer_needed) |
5063 | { | |
5064 | /* adjust $fp = $sp + 4 ($fp size) | |
8a498f99 CJW |
5065 | + 4 ($gp size) |
5066 | + 4 ($lp size) | |
5067 | + (4 * n) (callee-saved registers) | |
5068 | + sp_adjust ('push25 Re,imm8u') | |
9304f876 | 5069 | Note: Since we use 'push25 Re,imm8u', |
8a498f99 CJW |
5070 | the position of stack pointer is further |
5071 | changed after push instruction. | |
5072 | Hence, we need to take sp_adjust value | |
5073 | into consideration. */ | |
9304f876 CJW |
5074 | fp_adjust = cfun->machine->fp_size |
5075 | + cfun->machine->gp_size | |
5076 | + cfun->machine->lp_size | |
c457f751 | 5077 | + cfun->machine->callee_saved_gpr_regs_size |
9304f876 | 5078 | + sp_adjust; |
a6c7e777 MC |
5079 | |
5080 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, | |
5081 | stack_pointer_rtx, | |
5082 | fp_adjust); | |
9304f876 CJW |
5083 | } |
5084 | } | |
5085 | else | |
5086 | { | |
e2286268 MC |
5087 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5088 | { | |
5089 | /* Calculate fpr space. */ | |
5090 | fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes | |
5091 | + cfun->machine->callee_saved_fpr_regs_size; | |
5092 | ||
5093 | /* We have to use 'push25 Re, fpr_space', to pre-allocate | |
5094 | callee saved fpr registers space. */ | |
5095 | nds32_emit_stack_v3push (Rb, Re, fpr_space); | |
5096 | nds32_emit_push_fpr_callee_saved (0); | |
5097 | } | |
5098 | else | |
5099 | { | |
5100 | /* We have to use 'push25 Re,0' and | |
5101 | expand one more instruction to adjust $sp later. */ | |
9304f876 | 5102 | |
e2286268 MC |
5103 | /* nds32_emit_stack_v3push(last_regno, sp_adjust), |
5104 | the pattern 'stack_v3push' is implemented in nds32.md. */ | |
5105 | nds32_emit_stack_v3push (Rb, Re, 0); | |
5106 | } | |
9304f876 CJW |
5107 | |
5108 | /* Check frame_pointer_needed to see | |
8a498f99 | 5109 | if we shall emit fp adjustment instruction. */ |
9304f876 CJW |
5110 | if (frame_pointer_needed) |
5111 | { | |
5112 | /* adjust $fp = $sp + 4 ($fp size) | |
8a498f99 CJW |
5113 | + 4 ($gp size) |
5114 | + 4 ($lp size) | |
5115 | + (4 * n) (callee-saved registers) | |
9304f876 | 5116 | Note: Since we use 'push25 Re,0', |
8a498f99 CJW |
5117 | the stack pointer is just at the position |
5118 | after push instruction. | |
5119 | No need to take sp_adjust into consideration. */ | |
9304f876 CJW |
5120 | fp_adjust = cfun->machine->fp_size |
5121 | + cfun->machine->gp_size | |
5122 | + cfun->machine->lp_size | |
c457f751 | 5123 | + cfun->machine->callee_saved_gpr_regs_size; |
a6c7e777 | 5124 | |
e2286268 MC |
5125 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5126 | { | |
5127 | /* We use 'push25 Re, fpr_space', the $sp is | |
5128 | on callee saved fpr position, so need to consider | |
5129 | fpr space. */ | |
5130 | fp_adjust = fp_adjust + fpr_space; | |
5131 | } | |
5132 | ||
a6c7e777 MC |
5133 | nds32_emit_adjust_frame (hard_frame_pointer_rtx, |
5134 | stack_pointer_rtx, | |
5135 | fp_adjust); | |
9304f876 CJW |
5136 | } |
5137 | ||
e2286268 MC |
5138 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5139 | { | |
5140 | /* We use 'push25 Re, fpr_space', | |
5141 | the $sp is on callee saved fpr position, | |
5142 | no need to consider fpr space. */ | |
5143 | sp_adjust = sp_adjust - fpr_space; | |
5144 | } | |
5145 | ||
9304f876 | 5146 | /* Because we use 'push25 Re,0', |
8a498f99 | 5147 | we need to expand one more instruction to adjust $sp. |
8a498f99 | 5148 | using NEGATIVE value to tell that we are decreasing address. */ |
a6c7e777 MC |
5149 | nds32_emit_adjust_frame (stack_pointer_rtx, |
5150 | stack_pointer_rtx, | |
5151 | -1 * sp_adjust); | |
9304f876 CJW |
5152 | } |
5153 | ||
b26fa4f9 KLC |
5154 | /* Emit gp setup instructions for -fpic. */ |
5155 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) | |
5156 | nds32_emit_load_gp (); | |
5157 | ||
9304f876 CJW |
5158 | /* Prevent the instruction scheduler from |
5159 | moving instructions across the boundary. */ | |
5160 | emit_insn (gen_blockage ()); | |
5161 | } | |
5162 | ||
5163 | /* Function for v3pop epilogue. */ | |
5164 | void | |
d6529176 | 5165 | nds32_expand_epilogue_v3pop (bool sibcall_p) |
9304f876 CJW |
5166 | { |
5167 | int sp_adjust; | |
a6c7e777 | 5168 | unsigned Rb, Re; |
9304f876 CJW |
5169 | |
5170 | /* Compute and setup stack frame size. | |
5171 | The result will be in cfun->machine. */ | |
5172 | nds32_compute_stack_frame (); | |
5173 | ||
5174 | /* Prevent the instruction scheduler from | |
5175 | moving instructions across the boundary. */ | |
5176 | emit_insn (gen_blockage ()); | |
5177 | ||
5178 | /* If the function is 'naked', we do not have to generate | |
5179 | epilogue code fragment BUT 'ret' instruction. */ | |
5180 | if (cfun->machine->naked_p) | |
5181 | { | |
03390cda | 5182 | /* Generate return instruction by using 'return_internal' pattern. |
54c537e6 CJW |
5183 | Make sure this instruction is after gen_blockage(). |
5184 | First we need to check this is a function without sibling call. */ | |
d6529176 | 5185 | if (!sibcall_p) |
54c537e6 CJW |
5186 | { |
5187 | /* We need to further check attributes to determine whether | |
5188 | there should be return instruction at epilogue. | |
5189 | If the attribute naked exists but -mno-ret-in-naked-func | |
5190 | is issued, there is NO need to generate return instruction. */ | |
5191 | if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) | |
5192 | return; | |
5193 | ||
5194 | emit_jump_insn (gen_return_internal ()); | |
5195 | } | |
9304f876 CJW |
5196 | return; |
5197 | } | |
5198 | ||
5199 | /* Get callee_first_regno and callee_last_regno. */ | |
a6c7e777 MC |
5200 | Rb = cfun->machine->callee_saved_first_gpr_regno; |
5201 | Re = cfun->machine->callee_saved_last_gpr_regno; | |
9304f876 CJW |
5202 | |
5203 | /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available, | |
5204 | where imm8u has to be 8-byte alignment. */ | |
5205 | sp_adjust = cfun->machine->local_size | |
5206 | + cfun->machine->out_args_size | |
e2286268 MC |
5207 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
5208 | + cfun->machine->callee_saved_fpr_regs_size; | |
9304f876 CJW |
5209 | |
5210 | /* We have to consider alloca issue as well. | |
5211 | If the function does call alloca(), the stack pointer is not fixed. | |
5212 | In that case, we cannot use 'pop25 Re,imm8u' directly. | |
5213 | We have to caculate stack pointer from frame pointer | |
5214 | and then use 'pop25 Re,0'. | |
5215 | Of course, the frame_pointer_needed should be nonzero | |
5216 | if the function calls alloca(). */ | |
5217 | if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
5218 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) | |
5219 | && !cfun->calls_alloca) | |
5220 | { | |
e2286268 MC |
5221 | /* Restore fpu registers. */ |
5222 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
5223 | { | |
5224 | int fpr_position = cfun->machine->local_size | |
5225 | + cfun->machine->out_args_size; | |
5226 | /* Emit fpu load instruction, using [$sp + offset] restore | |
5227 | fpu registers. */ | |
5228 | nds32_emit_v3pop_fpr_callee_saved (fpr_position); | |
5229 | } | |
5230 | ||
9304f876 CJW |
5231 | /* We can use 'pop25 Re,imm8u'. */ |
5232 | ||
88437f39 | 5233 | /* nds32_emit_stack_v3pop(last_regno, sp_adjust), |
a6c7e777 MC |
5234 | the pattern 'stack_v3pop' is implementad in nds32.md. */ |
5235 | nds32_emit_stack_v3pop (Rb, Re, sp_adjust); | |
9304f876 CJW |
5236 | } |
5237 | else | |
5238 | { | |
5239 | /* We have to use 'pop25 Re,0', and prior to it, | |
8a498f99 | 5240 | we must expand one more instruction to adjust $sp. */ |
9304f876 CJW |
5241 | |
5242 | if (frame_pointer_needed) | |
5243 | { | |
5244 | /* adjust $sp = $fp - 4 ($fp size) | |
8a498f99 CJW |
5245 | - 4 ($gp size) |
5246 | - 4 ($lp size) | |
5247 | - (4 * n) (callee-saved registers) | |
9304f876 | 5248 | Note: No need to adjust |
8a498f99 CJW |
5249 | cfun->machine->callee_saved_area_gpr_padding_bytes, |
5250 | because we want to adjust stack pointer | |
5251 | to the position for pop instruction. */ | |
9304f876 CJW |
5252 | sp_adjust = cfun->machine->fp_size |
5253 | + cfun->machine->gp_size | |
5254 | + cfun->machine->lp_size | |
c457f751 | 5255 | + cfun->machine->callee_saved_gpr_regs_size; |
a6c7e777 | 5256 | |
e2286268 MC |
5257 | /* Restore fpu registers. */ |
5258 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
5259 | { | |
5260 | /* Set $sp to callee saved fpr position, we need to restore | |
5261 | fpr registers. */ | |
5262 | sp_adjust = sp_adjust | |
5263 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
5264 | + cfun->machine->callee_saved_fpr_regs_size; | |
5265 | ||
5266 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5267 | hard_frame_pointer_rtx, | |
5268 | -1 * sp_adjust); | |
5269 | ||
5270 | /* Emit fpu load instruction, using [$sp + offset] restore | |
5271 | fpu registers. */ | |
5272 | nds32_emit_v3pop_fpr_callee_saved (0); | |
5273 | } | |
5274 | else | |
5275 | { | |
5276 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5277 | hard_frame_pointer_rtx, | |
5278 | -1 * sp_adjust); | |
5279 | } | |
9304f876 CJW |
5280 | } |
5281 | else | |
5282 | { | |
5283 | /* If frame pointer is NOT needed, | |
5284 | we cannot calculate the sp adjustment from frame pointer. | |
5285 | Instead, we calculate the adjustment by local_size, | |
5286 | out_args_size, and callee_saved_area_padding_bytes. | |
5287 | Notice that such sp adjustment value may be out of range, | |
5288 | so we have to deal with it as well. */ | |
5289 | ||
5290 | /* Adjust $sp = $sp + local_size + out_args_size | |
e2286268 MC |
5291 | + callee_saved_area_gpr_padding_bytes |
5292 | + callee_saved_fpr_regs_size. */ | |
9304f876 CJW |
5293 | sp_adjust = cfun->machine->local_size |
5294 | + cfun->machine->out_args_size | |
e2286268 MC |
5295 | + cfun->machine->callee_saved_area_gpr_padding_bytes |
5296 | + cfun->machine->callee_saved_fpr_regs_size; | |
5297 | ||
5298 | /* Restore fpu registers. */ | |
5299 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) | |
5300 | { | |
5301 | /* Set $sp to callee saved fpr position, we need to restore | |
5302 | fpr registers. */ | |
5303 | sp_adjust = sp_adjust | |
5304 | - cfun->machine->callee_saved_area_gpr_padding_bytes | |
5305 | - cfun->machine->callee_saved_fpr_regs_size; | |
5306 | ||
5307 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5308 | stack_pointer_rtx, | |
5309 | sp_adjust); | |
5310 | ||
5311 | /* Emit fpu load instruction, using [$sp + offset] restore | |
5312 | fpu registers. */ | |
5313 | nds32_emit_v3pop_fpr_callee_saved (0); | |
5314 | } | |
5315 | else | |
5316 | { | |
5317 | /* sp_adjust value may be out of range of the addi instruction, | |
5318 | create alternative add behavior with TA_REGNUM if necessary, | |
5319 | using POSITIVE value to tell that we are increasing | |
5320 | address. */ | |
5321 | nds32_emit_adjust_frame (stack_pointer_rtx, | |
5322 | stack_pointer_rtx, | |
5323 | sp_adjust); | |
5324 | } | |
9304f876 CJW |
5325 | } |
5326 | ||
e2286268 MC |
5327 | if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) |
5328 | { | |
5329 | /* We have fpr need to restore, so $sp is set on callee saved fpr | |
5330 | position. And we use 'pop25 Re, fpr_space' to adjust $sp. */ | |
5331 | int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes | |
5332 | + cfun->machine->callee_saved_fpr_regs_size; | |
5333 | nds32_emit_stack_v3pop (Rb, Re, fpr_space); | |
5334 | } | |
5335 | else | |
5336 | { | |
5337 | /* nds32_emit_stack_v3pop(last_regno, sp_adjust), | |
5338 | the pattern 'stack_v3pop' is implementad in nds32.md. */ | |
5339 | nds32_emit_stack_v3pop (Rb, Re, 0); | |
5340 | } | |
9304f876 | 5341 | } |
aa2642ef CJW |
5342 | /* Generate return instruction. */ |
5343 | emit_jump_insn (gen_pop25return ()); | |
9304f876 CJW |
5344 | } |
5345 | ||
03390cda CJW |
5346 | /* Return nonzero if this function is known to have a null epilogue. |
5347 | This allows the optimizer to omit jumps to jumps if no stack | |
5348 | was created. */ | |
5349 | int | |
5350 | nds32_can_use_return_insn (void) | |
5351 | { | |
e2286268 MC |
5352 | int sp_adjust; |
5353 | ||
03390cda CJW |
5354 | /* Prior to reloading, we can't tell how many registers must be saved. |
5355 | Thus we can not determine whether this function has null epilogue. */ | |
5356 | if (!reload_completed) | |
5357 | return 0; | |
5358 | ||
54c537e6 CJW |
5359 | /* If attribute 'naked' appears but -mno-ret-in-naked-func is used, |
5360 | we cannot use return instruction. */ | |
5361 | if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) | |
5362 | return 0; | |
5363 | ||
e2286268 MC |
5364 | sp_adjust = cfun->machine->local_size |
5365 | + cfun->machine->out_args_size | |
5366 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
5367 | + cfun->machine->callee_saved_fpr_regs_size; | |
5368 | if (!cfun->machine->fp_as_gp_p | |
5369 | && satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
5370 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) | |
5371 | && !cfun->calls_alloca | |
5372 | && NDS32_V3PUSH_AVAILABLE_P | |
5373 | && !(TARGET_HARD_FLOAT | |
5374 | && (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM))) | |
5375 | return 1; | |
5376 | ||
03390cda CJW |
5377 | /* If no stack was created, two conditions must be satisfied: |
5378 | 1. This is a naked function. | |
8a498f99 | 5379 | So there is no callee-saved, local size, or outgoing size. |
03390cda | 5380 | 2. This is NOT a variadic function. |
8a498f99 | 5381 | So there is no pushing arguement registers into the stack. */ |
03390cda CJW |
5382 | return (cfun->machine->naked_p && (cfun->machine->va_args_size == 0)); |
5383 | } | |
5384 | ||
2f1bb3ca SC |
5385 | scalar_int_mode |
5386 | nds32_case_vector_shorten_mode (int min_offset, int max_offset, | |
5387 | rtx body ATTRIBUTE_UNUSED) | |
5388 | { | |
5389 | if (min_offset < 0 || max_offset >= 0x2000) | |
5390 | return SImode; | |
5391 | else | |
5392 | { | |
5393 | /* The jump table maybe need to 2 byte alignment, | |
5394 | so reserved 1 byte for check max_offset. */ | |
5395 | if (max_offset >= 0xff) | |
5396 | return HImode; | |
5397 | else | |
5398 | return QImode; | |
5399 | } | |
5400 | } | |
5401 | ||
9304f876 CJW |
5402 | /* ------------------------------------------------------------------------ */ |
5403 | ||
43fa41c1 CJW |
5404 | /* Return alignment for the label. */ |
5405 | int | |
5406 | nds32_target_alignment (rtx_insn *label) | |
5407 | { | |
5408 | rtx_insn *insn; | |
5409 | ||
5410 | if (!NDS32_ALIGN_P ()) | |
5411 | return 0; | |
5412 | ||
5413 | insn = next_active_insn (label); | |
5414 | ||
5415 | /* Always align to 4 byte when first instruction after label is jump | |
5416 | instruction since length for that might changed, so let's always align | |
5417 | it for make sure we don't lose any perfomance here. */ | |
5418 | if (insn == 0 | |
5419 | || (get_attr_length (insn) == 2 | |
5420 | && !JUMP_P (insn) && !CALL_P (insn))) | |
5421 | return 0; | |
5422 | else | |
5423 | return 2; | |
5424 | } | |
5425 | ||
79498ad8 CJW |
5426 | /* Return alignment for data. */ |
5427 | unsigned int | |
5428 | nds32_data_alignment (tree data, | |
5429 | unsigned int basic_align) | |
5430 | { | |
5431 | if ((basic_align < BITS_PER_WORD) | |
5432 | && (TREE_CODE (data) == ARRAY_TYPE | |
5433 | || TREE_CODE (data) == UNION_TYPE | |
5434 | || TREE_CODE (data) == RECORD_TYPE)) | |
5435 | return BITS_PER_WORD; | |
5436 | else | |
5437 | return basic_align; | |
5438 | } | |
5439 | ||
5440 | /* Return alignment for constant value. */ | |
5441 | static HOST_WIDE_INT | |
5442 | nds32_constant_alignment (const_tree constant, | |
5443 | HOST_WIDE_INT basic_align) | |
5444 | { | |
5445 | /* Make string literal and constant for constructor to word align. */ | |
5446 | if (((TREE_CODE (constant) == STRING_CST | |
5447 | || TREE_CODE (constant) == CONSTRUCTOR | |
5448 | || TREE_CODE (constant) == UNION_TYPE | |
5449 | || TREE_CODE (constant) == RECORD_TYPE | |
5450 | || TREE_CODE (constant) == ARRAY_TYPE) | |
5451 | && basic_align < BITS_PER_WORD)) | |
5452 | return BITS_PER_WORD; | |
5453 | else | |
5454 | return basic_align; | |
5455 | } | |
5456 | ||
5457 | /* Return alignment for local variable. */ | |
5458 | unsigned int | |
5459 | nds32_local_alignment (tree local ATTRIBUTE_UNUSED, | |
5460 | unsigned int basic_align) | |
5461 | { | |
5462 | bool at_least_align_to_word = false; | |
5463 | /* Make local array, struct and union at least align to word for make | |
5464 | sure it can unroll memcpy when initialize by constant. */ | |
5465 | switch (TREE_CODE (local)) | |
5466 | { | |
5467 | case ARRAY_TYPE: | |
5468 | case RECORD_TYPE: | |
5469 | case UNION_TYPE: | |
5470 | at_least_align_to_word = true; | |
5471 | break; | |
5472 | default: | |
5473 | at_least_align_to_word = false; | |
5474 | break; | |
5475 | } | |
5476 | if (at_least_align_to_word | |
5477 | && (basic_align < BITS_PER_WORD)) | |
5478 | return BITS_PER_WORD; | |
5479 | else | |
5480 | return basic_align; | |
5481 | } | |
5482 | ||
e2286268 MC |
5483 | bool |
5484 | nds32_split_double_word_load_store_p(rtx *operands, bool load_p) | |
5485 | { | |
5486 | rtx mem = load_p ? operands[1] : operands[0]; | |
5487 | /* Do split at split2 if -O0 or schedule 2 not enable. */ | |
5488 | if (optimize == 0 || !flag_schedule_insns_after_reload) | |
5489 | return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem); | |
5490 | ||
5491 | /* Split double word load store after copy propgation. */ | |
5492 | if (current_pass == NULL) | |
5493 | return false; | |
5494 | ||
5495 | const char *pass_name = current_pass->name; | |
5496 | if (pass_name && ((strcmp (pass_name, "split4") == 0) | |
5497 | || (strcmp (pass_name, "split5") == 0))) | |
5498 | return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem); | |
5499 | ||
5500 | return false; | |
5501 | } | |
5502 | ||
5503 | static bool | |
5504 | nds32_use_blocks_for_constant_p (machine_mode mode, | |
5505 | const_rtx x ATTRIBUTE_UNUSED) | |
5506 | { | |
5507 | if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) | |
5508 | && (mode == DFmode || mode == SFmode)) | |
5509 | return true; | |
5510 | else | |
5511 | return false; | |
5512 | } | |
9304f876 | 5513 | |
9304f876 CJW |
5514 | /* ------------------------------------------------------------------------ */ |
5515 | ||
5516 | /* PART 5: Initialize target hook structure and definitions. */ | |
5517 | \f | |
5518 | /* Controlling the Compilation Driver. */ | |
5519 | ||
5520 | \f | |
5521 | /* Run-time Target Specification. */ | |
5522 | ||
5523 | \f | |
5524 | /* Defining Data Structures for Per-function Information. */ | |
5525 | ||
5526 | \f | |
5527 | /* Storage Layout. */ | |
5528 | ||
5529 | #undef TARGET_PROMOTE_FUNCTION_MODE | |
5530 | #define TARGET_PROMOTE_FUNCTION_MODE \ | |
5531 | default_promote_function_mode_always_promote | |
5532 | ||
5f2a98c3 CJW |
5533 | #undef TARGET_EXPAND_TO_RTL_HOOK |
5534 | #define TARGET_EXPAND_TO_RTL_HOOK nds32_expand_to_rtl_hook | |
5535 | ||
79498ad8 CJW |
5536 | #undef TARGET_CONSTANT_ALIGNMENT |
5537 | #define TARGET_CONSTANT_ALIGNMENT nds32_constant_alignment | |
5538 | ||
9304f876 CJW |
5539 | \f |
5540 | /* Layout of Source Language Data Types. */ | |
5541 | ||
5542 | \f | |
5543 | /* Register Usage. */ | |
5544 | ||
5545 | /* -- Basic Characteristics of Registers. */ | |
5546 | ||
e2286268 MC |
5547 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
5548 | #define TARGET_CONDITIONAL_REGISTER_USAGE nds32_conditional_register_usage | |
5549 | ||
9304f876 CJW |
5550 | /* -- Order of Allocation of Registers. */ |
5551 | ||
5552 | /* -- How Values Fit in Registers. */ | |
5553 | ||
e2286268 MC |
5554 | #undef TARGET_HARD_REGNO_NREGS |
5555 | #define TARGET_HARD_REGNO_NREGS nds32_hard_regno_nregs | |
5556 | ||
50256c75 CJW |
5557 | #undef TARGET_HARD_REGNO_MODE_OK |
5558 | #define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok | |
5559 | ||
5560 | #undef TARGET_MODES_TIEABLE_P | |
5561 | #define TARGET_MODES_TIEABLE_P nds32_modes_tieable_p | |
5562 | ||
9304f876 CJW |
5563 | /* -- Handling Leaf Functions. */ |
5564 | ||
5565 | /* -- Registers That Form a Stack. */ | |
5566 | ||
5567 | \f | |
5568 | /* Register Classes. */ | |
5569 | ||
5570 | #undef TARGET_CLASS_MAX_NREGS | |
5571 | #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs | |
5572 | ||
9304f876 CJW |
5573 | #undef TARGET_REGISTER_PRIORITY |
5574 | #define TARGET_REGISTER_PRIORITY nds32_register_priority | |
5575 | ||
e2286268 MC |
5576 | #undef TARGET_CAN_CHANGE_MODE_CLASS |
5577 | #define TARGET_CAN_CHANGE_MODE_CLASS nds32_can_change_mode_class | |
5578 | ||
9304f876 CJW |
5579 | \f |
5580 | /* Obsolete Macros for Defining Constraints. */ | |
5581 | ||
5582 | \f | |
5583 | /* Stack Layout and Calling Conventions. */ | |
5584 | ||
5585 | /* -- Basic Stack Layout. */ | |
5586 | ||
5587 | /* -- Exception Handling Support. */ | |
5588 | ||
5589 | /* -- Specifying How Stack Checking is Done. */ | |
5590 | ||
5591 | /* -- Registers That Address the Stack Frame. */ | |
5592 | ||
5593 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
5594 | ||
5595 | #undef TARGET_CAN_ELIMINATE | |
5596 | #define TARGET_CAN_ELIMINATE nds32_can_eliminate | |
5597 | ||
5598 | /* -- Passing Function Arguments on the Stack. */ | |
5599 | ||
5600 | /* -- Passing Arguments in Registers. */ | |
5601 | ||
5602 | #undef TARGET_FUNCTION_ARG | |
5603 | #define TARGET_FUNCTION_ARG nds32_function_arg | |
5604 | ||
d40f3c40 CJW |
5605 | #undef TARGET_MUST_PASS_IN_STACK |
5606 | #define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack | |
5607 | ||
650fc469 CJW |
5608 | #undef TARGET_ARG_PARTIAL_BYTES |
5609 | #define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes | |
5610 | ||
9304f876 CJW |
5611 | #undef TARGET_FUNCTION_ARG_ADVANCE |
5612 | #define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance | |
5613 | ||
5614 | #undef TARGET_FUNCTION_ARG_BOUNDARY | |
5615 | #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary | |
5616 | ||
7c32ef41 MC |
5617 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
5618 | #define TARGET_VECTOR_MODE_SUPPORTED_P nds32_vector_mode_supported_p | |
5619 | ||
9304f876 CJW |
5620 | /* -- How Scalar Function Values Are Returned. */ |
5621 | ||
5622 | #undef TARGET_FUNCTION_VALUE | |
5623 | #define TARGET_FUNCTION_VALUE nds32_function_value | |
5624 | ||
5625 | #undef TARGET_LIBCALL_VALUE | |
5626 | #define TARGET_LIBCALL_VALUE nds32_libcall_value | |
5627 | ||
5628 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
5629 | #define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p | |
5630 | ||
5631 | /* -- How Large Values Are Returned. */ | |
5632 | ||
e2286268 MC |
5633 | #undef TARGET_RETURN_IN_MEMORY |
5634 | #define TARGET_RETURN_IN_MEMORY nds32_return_in_memory | |
5635 | ||
9304f876 CJW |
5636 | /* -- Caller-Saves Register Allocation. */ |
5637 | ||
5638 | /* -- Function Entry and Exit. */ | |
5639 | ||
5640 | #undef TARGET_ASM_FUNCTION_PROLOGUE | |
5641 | #define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue | |
5642 | ||
5643 | #undef TARGET_ASM_FUNCTION_END_PROLOGUE | |
5644 | #define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue | |
5645 | ||
5646 | #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE | |
5647 | #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue | |
5648 | ||
5649 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
5650 | #define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue | |
5651 | ||
5652 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
5653 | #define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk | |
5654 | ||
5655 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
5656 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
5657 | ||
5658 | /* -- Generating Code for Profiling. */ | |
5659 | ||
5660 | /* -- Permitting tail calls. */ | |
5661 | ||
cc48a87f CJW |
5662 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
5663 | #define TARGET_FUNCTION_OK_FOR_SIBCALL nds32_function_ok_for_sibcall | |
5664 | ||
9304f876 CJW |
5665 | #undef TARGET_WARN_FUNC_RETURN |
5666 | #define TARGET_WARN_FUNC_RETURN nds32_warn_func_return | |
5667 | ||
5668 | /* Stack smashing protection. */ | |
5669 | ||
5670 | \f | |
5671 | /* Implementing the Varargs Macros. */ | |
5672 | ||
d4a6a4d9 CJW |
5673 | #undef TARGET_SETUP_INCOMING_VARARGS |
5674 | #define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs | |
5675 | ||
9304f876 CJW |
5676 | #undef TARGET_STRICT_ARGUMENT_NAMING |
5677 | #define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming | |
5678 | ||
5679 | \f | |
5680 | /* Trampolines for Nested Functions. */ | |
5681 | ||
5682 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE | |
5683 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template | |
5684 | ||
5685 | #undef TARGET_TRAMPOLINE_INIT | |
5686 | #define TARGET_TRAMPOLINE_INIT nds32_trampoline_init | |
5687 | ||
5688 | \f | |
5689 | /* Implicit Calls to Library Routines. */ | |
5690 | ||
5691 | \f | |
5692 | /* Addressing Modes. */ | |
5693 | ||
5694 | #undef TARGET_LEGITIMATE_ADDRESS_P | |
5695 | #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p | |
5696 | ||
85a98076 KLC |
5697 | #undef TARGET_LEGITIMIZE_ADDRESS |
5698 | #define TARGET_LEGITIMIZE_ADDRESS nds32_legitimize_address | |
5699 | ||
5700 | #undef TARGET_LEGITIMATE_CONSTANT_P | |
5701 | #define TARGET_LEGITIMATE_CONSTANT_P nds32_legitimate_constant_p | |
5702 | ||
7c32ef41 MC |
5703 | #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE |
5704 | #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE nds32_vectorize_preferred_simd_mode | |
5705 | ||
85a98076 KLC |
5706 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
5707 | #define TARGET_CANNOT_FORCE_CONST_MEM nds32_cannot_force_const_mem | |
5708 | ||
5709 | #undef TARGET_DELEGITIMIZE_ADDRESS | |
5710 | #define TARGET_DELEGITIMIZE_ADDRESS nds32_delegitimize_address | |
5711 | ||
9304f876 CJW |
5712 | \f |
5713 | /* Anchored Addresses. */ | |
5714 | ||
5715 | \f | |
5716 | /* Condition Code Status. */ | |
5717 | ||
5718 | /* -- Representation of condition codes using (cc0). */ | |
5719 | ||
5720 | /* -- Representation of condition codes using registers. */ | |
5721 | ||
5b6f2bf3 CJW |
5722 | #undef TARGET_CANONICALIZE_COMPARISON |
5723 | #define TARGET_CANONICALIZE_COMPARISON nds32_canonicalize_comparison | |
5724 | ||
9304f876 CJW |
5725 | /* -- Macros to control conditional execution. */ |
5726 | ||
5727 | \f | |
5728 | /* Describing Relative Costs of Operations. */ | |
5729 | ||
5730 | #undef TARGET_REGISTER_MOVE_COST | |
5731 | #define TARGET_REGISTER_MOVE_COST nds32_register_move_cost | |
5732 | ||
5733 | #undef TARGET_MEMORY_MOVE_COST | |
5734 | #define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost | |
5735 | ||
5736 | #undef TARGET_RTX_COSTS | |
5737 | #define TARGET_RTX_COSTS nds32_rtx_costs | |
5738 | ||
5739 | #undef TARGET_ADDRESS_COST | |
5740 | #define TARGET_ADDRESS_COST nds32_address_cost | |
5741 | ||
5742 | \f | |
5743 | /* Adjusting the Instruction Scheduler. */ | |
5744 | ||
5745 | \f | |
5746 | /* Dividing the Output into Sections (Texts, Data, . . . ). */ | |
5747 | ||
511a41d7 CJW |
5748 | #undef TARGET_ENCODE_SECTION_INFO |
5749 | #define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info | |
5750 | ||
9304f876 CJW |
5751 | \f |
5752 | /* Position Independent Code. */ | |
5753 | ||
5754 | \f | |
5755 | /* Defining the Output Assembler Language. */ | |
5756 | ||
5757 | /* -- The Overall Framework of an Assembler File. */ | |
5758 | ||
5759 | #undef TARGET_ASM_FILE_START | |
5760 | #define TARGET_ASM_FILE_START nds32_asm_file_start | |
5761 | #undef TARGET_ASM_FILE_END | |
5762 | #define TARGET_ASM_FILE_END nds32_asm_file_end | |
5763 | ||
5764 | /* -- Output of Data. */ | |
5765 | ||
5766 | #undef TARGET_ASM_ALIGNED_HI_OP | |
5767 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
5768 | ||
5769 | #undef TARGET_ASM_ALIGNED_SI_OP | |
5770 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
5771 | ||
85a98076 KLC |
5772 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
5773 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nds32_asm_output_addr_const_extra | |
5774 | ||
9304f876 CJW |
5775 | /* -- Output of Uninitialized Variables. */ |
5776 | ||
5777 | /* -- Output and Generation of Labels. */ | |
5778 | ||
5779 | #undef TARGET_ASM_GLOBALIZE_LABEL | |
5780 | #define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label | |
5781 | ||
5782 | /* -- How Initialization Functions Are Handled. */ | |
5783 | ||
5784 | /* -- Macros Controlling Initialization Routines. */ | |
5785 | ||
5786 | /* -- Output of Assembler Instructions. */ | |
5787 | ||
5788 | #undef TARGET_PRINT_OPERAND | |
5789 | #define TARGET_PRINT_OPERAND nds32_print_operand | |
5790 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
5791 | #define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address | |
5792 | ||
5793 | /* -- Output of Dispatch Tables. */ | |
5794 | ||
5795 | /* -- Assembler Commands for Exception Regions. */ | |
5796 | ||
e2286268 MC |
5797 | #undef TARGET_DWARF_REGISTER_SPAN |
5798 | #define TARGET_DWARF_REGISTER_SPAN nds32_dwarf_register_span | |
5799 | ||
9304f876 CJW |
5800 | /* -- Assembler Commands for Alignment. */ |
5801 | ||
5802 | \f | |
5803 | /* Controlling Debugging Information Format. */ | |
5804 | ||
5805 | /* -- Macros Affecting All Debugging Formats. */ | |
5806 | ||
5807 | /* -- Specific Options for DBX Output. */ | |
5808 | ||
5809 | /* -- Open-Ended Hooks for DBX Format. */ | |
5810 | ||
5811 | /* -- File Names in DBX Format. */ | |
5812 | ||
180295ed | 5813 | /* -- Macros for DWARF Output. */ |
9304f876 CJW |
5814 | |
5815 | /* -- Macros for VMS Debug Format. */ | |
5816 | ||
5817 | \f | |
5818 | /* Cross Compilation and Floating Point. */ | |
5819 | ||
5820 | \f | |
5821 | /* Mode Switching Instructions. */ | |
5822 | ||
5823 | \f | |
5824 | /* Defining target-specific uses of __attribute__. */ | |
5825 | ||
5826 | #undef TARGET_ATTRIBUTE_TABLE | |
5827 | #define TARGET_ATTRIBUTE_TABLE nds32_attribute_table | |
5828 | ||
5829 | #undef TARGET_MERGE_DECL_ATTRIBUTES | |
5830 | #define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes | |
5831 | ||
5832 | #undef TARGET_INSERT_ATTRIBUTES | |
5833 | #define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes | |
5834 | ||
5835 | #undef TARGET_OPTION_PRAGMA_PARSE | |
5836 | #define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse | |
5837 | ||
5838 | #undef TARGET_OPTION_OVERRIDE | |
5839 | #define TARGET_OPTION_OVERRIDE nds32_option_override | |
5840 | ||
5841 | \f | |
5842 | /* Emulating TLS. */ | |
5843 | ||
cf3cd43d CJW |
5844 | #undef TARGET_HAVE_TLS |
5845 | #define TARGET_HAVE_TLS TARGET_LINUX_ABI | |
5846 | ||
9304f876 CJW |
5847 | \f |
5848 | /* Defining coprocessor specifics for MIPS targets. */ | |
5849 | ||
5850 | \f | |
5851 | /* Parameters for Precompiled Header Validity Checking. */ | |
5852 | ||
5853 | \f | |
5854 | /* C++ ABI parameters. */ | |
5855 | ||
5856 | \f | |
5857 | /* Adding support for named address spaces. */ | |
5858 | ||
5859 | \f | |
5860 | /* Miscellaneous Parameters. */ | |
5861 | ||
823835a9 CJW |
5862 | #undef TARGET_MD_ASM_ADJUST |
5863 | #define TARGET_MD_ASM_ADJUST nds32_md_asm_adjust | |
5864 | ||
9304f876 CJW |
5865 | #undef TARGET_INIT_BUILTINS |
5866 | #define TARGET_INIT_BUILTINS nds32_init_builtins | |
5867 | ||
7a12ea32 MC |
5868 | #undef TARGET_BUILTIN_DECL |
5869 | #define TARGET_BUILTIN_DECL nds32_builtin_decl | |
5870 | ||
9304f876 CJW |
5871 | #undef TARGET_EXPAND_BUILTIN |
5872 | #define TARGET_EXPAND_BUILTIN nds32_expand_builtin | |
5873 | ||
cf3cd43d CJW |
5874 | #undef TARGET_INIT_LIBFUNCS |
5875 | #define TARGET_INIT_LIBFUNCS nds32_init_libfuncs | |
e2286268 MC |
5876 | |
5877 | #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P | |
5878 | #define TARGET_USE_BLOCKS_FOR_CONSTANT_P nds32_use_blocks_for_constant_p | |
5879 | ||
9304f876 CJW |
5880 | \f |
5881 | /* ------------------------------------------------------------------------ */ | |
5882 | ||
5883 | /* Initialize the GCC target structure. */ | |
5884 | ||
5885 | struct gcc_target targetm = TARGET_INITIALIZER; | |
5886 | ||
5887 | /* ------------------------------------------------------------------------ */ |