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9304f876 | 1 | /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler |
cbe34bb5 | 2 | Copyright (C) 2012-2017 Free Software Foundation, Inc. |
9304f876 CJW |
3 | Contributed by Andes Technology Corporation. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 3, or (at your | |
10 | option) any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
19ac960a | 21 | /* ------------------------------------------------------------------------ */ |
9304f876 CJW |
22 | |
23 | #include "config.h" | |
24 | #include "system.h" | |
25 | #include "coretypes.h" | |
c7131fb2 | 26 | #include "backend.h" |
e11c4407 | 27 | #include "target.h" |
c7131fb2 | 28 | #include "rtl.h" |
e11c4407 | 29 | #include "tree.h" |
314e6352 ML |
30 | #include "stringpool.h" |
31 | #include "attribs.h" | |
c7131fb2 | 32 | #include "df.h" |
4d0cdd0c | 33 | #include "memmodel.h" |
e11c4407 AM |
34 | #include "tm_p.h" |
35 | #include "optabs.h" /* For GEN_FCN. */ | |
36 | #include "regs.h" | |
37 | #include "emit-rtl.h" | |
38 | #include "recog.h" | |
39 | #include "diagnostic-core.h" | |
d8a2d370 DN |
40 | #include "stor-layout.h" |
41 | #include "varasm.h" | |
42 | #include "calls.h" | |
9304f876 | 43 | #include "output.h" |
36566b39 | 44 | #include "explow.h" |
9304f876 | 45 | #include "expr.h" |
9304f876 | 46 | #include "tm-constrs.h" |
9b2b7279 | 47 | #include "builtins.h" |
9304f876 | 48 | |
994c5d85 | 49 | /* This file should be included last. */ |
d58627a0 RS |
50 | #include "target-def.h" |
51 | ||
9304f876 CJW |
52 | /* ------------------------------------------------------------------------ */ |
53 | ||
54 | /* This file is divided into five parts: | |
55 | ||
56 | PART 1: Auxiliary static variable definitions and | |
57 | target hook static variable definitions. | |
58 | ||
59 | PART 2: Auxiliary static function definitions. | |
60 | ||
61 | PART 3: Implement target hook stuff definitions. | |
62 | ||
63 | PART 4: Implemet extern function definitions, | |
64 | the prototype is in nds32-protos.h. | |
65 | ||
66 | PART 5: Initialize target hook structure and definitions. */ | |
67 | ||
68 | /* ------------------------------------------------------------------------ */ | |
69 | ||
70 | /* PART 1: Auxiliary static variable definitions and | |
71 | target hook static variable definitions. */ | |
72 | ||
9304f876 CJW |
73 | /* Define intrinsic register names. |
74 | Please refer to nds32_intrinsic.h file, the index is corresponding to | |
75 | 'enum nds32_intrinsic_registers' data type values. | |
76 | NOTE that the base value starting from 1024. */ | |
77 | static const char * const nds32_intrinsic_register_names[] = | |
78 | { | |
79 | "$PSW", "$IPSW", "$ITYPE", "$IPC" | |
80 | }; | |
81 | ||
82 | /* Defining target-specific uses of __attribute__. */ | |
83 | static const struct attribute_spec nds32_attribute_table[] = | |
84 | { | |
85 | /* Syntax: { name, min_len, max_len, decl_required, type_required, | |
86 | function_type_required, handler, affects_type_identity } */ | |
87 | ||
88 | /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */ | |
89 | { "interrupt", 1, 64, false, false, false, NULL, false }, | |
90 | /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */ | |
91 | { "exception", 1, 8, false, false, false, NULL, false }, | |
92 | /* Argument is user's interrupt numbers. The vector number is always 0. */ | |
93 | { "reset", 1, 1, false, false, false, NULL, false }, | |
94 | ||
95 | /* The attributes describing isr nested type. */ | |
96 | { "nested", 0, 0, false, false, false, NULL, false }, | |
97 | { "not_nested", 0, 0, false, false, false, NULL, false }, | |
98 | { "nested_ready", 0, 0, false, false, false, NULL, false }, | |
99 | ||
100 | /* The attributes describing isr register save scheme. */ | |
101 | { "save_all", 0, 0, false, false, false, NULL, false }, | |
102 | { "partial_save", 0, 0, false, false, false, NULL, false }, | |
103 | ||
104 | /* The attributes used by reset attribute. */ | |
105 | { "nmi", 1, 1, false, false, false, NULL, false }, | |
106 | { "warm", 1, 1, false, false, false, NULL, false }, | |
107 | ||
108 | /* The attribute telling no prologue/epilogue. */ | |
109 | { "naked", 0, 0, false, false, false, NULL, false }, | |
110 | ||
111 | /* The last attribute spec is set to be NULL. */ | |
112 | { NULL, 0, 0, false, false, false, NULL, false } | |
113 | }; | |
114 | ||
115 | ||
116 | /* ------------------------------------------------------------------------ */ | |
117 | ||
118 | /* PART 2: Auxiliary static function definitions. */ | |
119 | ||
120 | /* Function to save and restore machine-specific function data. */ | |
121 | static struct machine_function * | |
122 | nds32_init_machine_status (void) | |
123 | { | |
124 | struct machine_function *machine; | |
766090c2 | 125 | machine = ggc_cleared_alloc<machine_function> (); |
9304f876 CJW |
126 | |
127 | /* Initially assume this function needs prologue/epilogue. */ | |
128 | machine->naked_p = 0; | |
129 | ||
130 | /* Initially assume this function does NOT use fp_as_gp optimization. */ | |
131 | machine->fp_as_gp_p = 0; | |
132 | ||
133 | return machine; | |
134 | } | |
135 | ||
136 | /* Function to compute stack frame size and | |
137 | store into cfun->machine structure. */ | |
138 | static void | |
139 | nds32_compute_stack_frame (void) | |
140 | { | |
141 | int r; | |
142 | int block_size; | |
143 | ||
144 | /* Because nds32_compute_stack_frame() will be called from different place, | |
145 | everytime we enter this function, we have to assume this function | |
146 | needs prologue/epilogue. */ | |
147 | cfun->machine->naked_p = 0; | |
148 | ||
149 | /* Get variadic arguments size to prepare pretend arguments and | |
35da54a6 CJW |
150 | we will push them into stack at prologue by ourself. */ |
151 | cfun->machine->va_args_size = crtl->args.pretend_args_size; | |
152 | if (cfun->machine->va_args_size != 0) | |
153 | { | |
154 | cfun->machine->va_args_first_regno | |
155 | = NDS32_GPR_ARG_FIRST_REGNUM | |
156 | + NDS32_MAX_GPR_REGS_FOR_ARGS | |
157 | - (crtl->args.pretend_args_size / UNITS_PER_WORD); | |
158 | cfun->machine->va_args_last_regno | |
159 | = NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS - 1; | |
160 | } | |
161 | else | |
162 | { | |
163 | cfun->machine->va_args_first_regno = SP_REGNUM; | |
164 | cfun->machine->va_args_last_regno = SP_REGNUM; | |
165 | } | |
166 | ||
167 | /* Important: We need to make sure that varargs area is 8-byte alignment. */ | |
168 | block_size = cfun->machine->va_args_size; | |
169 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) | |
170 | { | |
171 | cfun->machine->va_args_area_padding_bytes | |
172 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; | |
173 | } | |
9304f876 CJW |
174 | |
175 | /* Get local variables, incoming variables, and temporary variables size. | |
176 | Note that we need to make sure it is 8-byte alignment because | |
177 | there may be no padding bytes if we are using LRA. */ | |
178 | cfun->machine->local_size = NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ()); | |
179 | ||
180 | /* Get outgoing arguments size. */ | |
181 | cfun->machine->out_args_size = crtl->outgoing_args_size; | |
182 | ||
183 | /* If $fp value is required to be saved on stack, it needs 4 bytes space. | |
184 | Check whether $fp is ever live. */ | |
185 | cfun->machine->fp_size = (df_regs_ever_live_p (FP_REGNUM)) ? 4 : 0; | |
186 | ||
187 | /* If $gp value is required to be saved on stack, it needs 4 bytes space. | |
188 | Check whether we are using PIC code genration. */ | |
189 | cfun->machine->gp_size = (flag_pic) ? 4 : 0; | |
190 | ||
191 | /* If $lp value is required to be saved on stack, it needs 4 bytes space. | |
192 | Check whether $lp is ever live. */ | |
193 | cfun->machine->lp_size = (df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0; | |
194 | ||
195 | /* Initially there is no padding bytes. */ | |
c457f751 | 196 | cfun->machine->callee_saved_area_gpr_padding_bytes = 0; |
9304f876 CJW |
197 | |
198 | /* Calculate the bytes of saving callee-saved registers on stack. */ | |
c457f751 CJW |
199 | cfun->machine->callee_saved_gpr_regs_size = 0; |
200 | cfun->machine->callee_saved_first_gpr_regno = SP_REGNUM; | |
201 | cfun->machine->callee_saved_last_gpr_regno = SP_REGNUM; | |
9304f876 CJW |
202 | /* Currently, there is no need to check $r28~$r31 |
203 | because we will save them in another way. */ | |
204 | for (r = 0; r < 28; r++) | |
205 | { | |
206 | if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) | |
207 | { | |
208 | /* Mark the first required callee-saved register | |
209 | (only need to set it once). | |
210 | If first regno == SP_REGNUM, we can tell that | |
211 | it is the first time to be here. */ | |
c457f751 CJW |
212 | if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) |
213 | cfun->machine->callee_saved_first_gpr_regno = r; | |
9304f876 | 214 | /* Mark the last required callee-saved register. */ |
c457f751 | 215 | cfun->machine->callee_saved_last_gpr_regno = r; |
9304f876 CJW |
216 | } |
217 | } | |
218 | ||
219 | /* Check if this function can omit prologue/epilogue code fragment. | |
220 | If there is 'naked' attribute in this function, | |
221 | we can set 'naked_p' flag to indicate that | |
222 | we do not have to generate prologue/epilogue. | |
223 | Or, if all the following conditions succeed, | |
224 | we can set this function 'naked_p' as well: | |
225 | condition 1: first_regno == last_regno == SP_REGNUM, | |
226 | which means we do not have to save | |
227 | any callee-saved registers. | |
228 | condition 2: Both $lp and $fp are NOT live in this function, | |
2da1e7c0 CJW |
229 | which means we do not need to save them and there |
230 | is no outgoing size. | |
9304f876 CJW |
231 | condition 3: There is no local_size, which means |
232 | we do not need to adjust $sp. */ | |
233 | if (lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) | |
c457f751 CJW |
234 | || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM |
235 | && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM | |
9304f876 CJW |
236 | && !df_regs_ever_live_p (FP_REGNUM) |
237 | && !df_regs_ever_live_p (LP_REGNUM) | |
238 | && cfun->machine->local_size == 0)) | |
239 | { | |
2da1e7c0 CJW |
240 | /* Set this function 'naked_p' and other functions can check this flag. |
241 | Note that in nds32 port, the 'naked_p = 1' JUST means there is no | |
242 | callee-saved, local size, and outgoing size. | |
243 | The varargs space and ret instruction may still present in | |
244 | the prologue/epilogue expanding. */ | |
9304f876 CJW |
245 | cfun->machine->naked_p = 1; |
246 | ||
247 | /* No need to save $fp, $gp, and $lp. | |
248 | We should set these value to be zero | |
249 | so that nds32_initial_elimination_offset() can work properly. */ | |
250 | cfun->machine->fp_size = 0; | |
251 | cfun->machine->gp_size = 0; | |
252 | cfun->machine->lp_size = 0; | |
253 | ||
254 | /* If stack usage computation is required, | |
255 | we need to provide the static stack size. */ | |
256 | if (flag_stack_usage_info) | |
257 | current_function_static_stack_size = 0; | |
258 | ||
259 | /* No need to do following adjustment, return immediately. */ | |
260 | return; | |
261 | } | |
262 | ||
263 | /* Adjustment for v3push instructions: | |
264 | If we are using v3push (push25/pop25) instructions, | |
265 | we need to make sure Rb is $r6 and Re is | |
266 | located on $r6, $r8, $r10, or $r14. | |
267 | Some results above will be discarded and recomputed. | |
2da1e7c0 CJW |
268 | Note that it is only available under V3/V3M ISA and we |
269 | DO NOT setup following stuff for isr or variadic function. */ | |
270 | if (TARGET_V3PUSH | |
271 | && !nds32_isr_function_p (current_function_decl) | |
272 | && (cfun->machine->va_args_size == 0)) | |
9304f876 CJW |
273 | { |
274 | /* Recompute: | |
275 | cfun->machine->fp_size | |
276 | cfun->machine->gp_size | |
277 | cfun->machine->lp_size | |
278 | cfun->machine->callee_saved_regs_first_regno | |
279 | cfun->machine->callee_saved_regs_last_regno */ | |
280 | ||
281 | /* For v3push instructions, $fp, $gp, and $lp are always saved. */ | |
282 | cfun->machine->fp_size = 4; | |
283 | cfun->machine->gp_size = 4; | |
284 | cfun->machine->lp_size = 4; | |
285 | ||
286 | /* Remember to set Rb = $r6. */ | |
c457f751 | 287 | cfun->machine->callee_saved_first_gpr_regno = 6; |
9304f876 | 288 | |
c457f751 | 289 | if (cfun->machine->callee_saved_last_gpr_regno <= 6) |
9304f876 CJW |
290 | { |
291 | /* Re = $r6 */ | |
c457f751 | 292 | cfun->machine->callee_saved_last_gpr_regno = 6; |
9304f876 | 293 | } |
c457f751 | 294 | else if (cfun->machine->callee_saved_last_gpr_regno <= 8) |
9304f876 CJW |
295 | { |
296 | /* Re = $r8 */ | |
c457f751 | 297 | cfun->machine->callee_saved_last_gpr_regno = 8; |
9304f876 | 298 | } |
c457f751 | 299 | else if (cfun->machine->callee_saved_last_gpr_regno <= 10) |
9304f876 CJW |
300 | { |
301 | /* Re = $r10 */ | |
c457f751 | 302 | cfun->machine->callee_saved_last_gpr_regno = 10; |
9304f876 | 303 | } |
c457f751 | 304 | else if (cfun->machine->callee_saved_last_gpr_regno <= 14) |
9304f876 CJW |
305 | { |
306 | /* Re = $r14 */ | |
c457f751 | 307 | cfun->machine->callee_saved_last_gpr_regno = 14; |
9304f876 | 308 | } |
c457f751 | 309 | else if (cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM) |
9304f876 CJW |
310 | { |
311 | /* If last_regno is SP_REGNUM, which means | |
312 | it is never changed, so set it to Re = $r6. */ | |
c457f751 | 313 | cfun->machine->callee_saved_last_gpr_regno = 6; |
9304f876 CJW |
314 | } |
315 | else | |
316 | { | |
317 | /* The program flow should not go here. */ | |
318 | gcc_unreachable (); | |
319 | } | |
320 | } | |
321 | ||
322 | /* We have correctly set callee_saved_regs_first_regno | |
323 | and callee_saved_regs_last_regno. | |
324 | Initially, the callee_saved_regs_size is supposed to be 0. | |
325 | As long as callee_saved_regs_last_regno is not SP_REGNUM, | |
326 | we can update callee_saved_regs_size with new size. */ | |
c457f751 | 327 | if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) |
9304f876 CJW |
328 | { |
329 | /* Compute pushed size of callee-saved registers. */ | |
c457f751 CJW |
330 | cfun->machine->callee_saved_gpr_regs_size |
331 | = 4 * (cfun->machine->callee_saved_last_gpr_regno | |
332 | - cfun->machine->callee_saved_first_gpr_regno | |
9304f876 CJW |
333 | + 1); |
334 | } | |
335 | ||
336 | /* Important: We need to make sure that | |
35da54a6 | 337 | (fp_size + gp_size + lp_size + callee_saved_regs_size) |
9304f876 CJW |
338 | is 8-byte alignment. |
339 | If it is not, calculate the padding bytes. */ | |
35da54a6 | 340 | block_size = cfun->machine->fp_size |
9304f876 CJW |
341 | + cfun->machine->gp_size |
342 | + cfun->machine->lp_size | |
c457f751 | 343 | + cfun->machine->callee_saved_gpr_regs_size; |
9304f876 CJW |
344 | if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) |
345 | { | |
c457f751 | 346 | cfun->machine->callee_saved_area_gpr_padding_bytes |
9304f876 CJW |
347 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; |
348 | } | |
349 | ||
350 | /* If stack usage computation is required, | |
351 | we need to provide the static stack size. */ | |
352 | if (flag_stack_usage_info) | |
353 | { | |
354 | current_function_static_stack_size | |
355 | = NDS32_ROUND_UP_DOUBLE_WORD (block_size) | |
356 | + cfun->machine->local_size | |
357 | + cfun->machine->out_args_size; | |
358 | } | |
359 | } | |
360 | ||
361 | /* Function to create a parallel rtx pattern | |
362 | which presents stack push multiple behavior. | |
363 | The overall concept are: | |
364 | "push registers to memory", | |
365 | "adjust stack pointer". */ | |
4e9a2848 | 366 | static void |
47e0e7d2 | 367 | nds32_emit_stack_push_multiple (rtx Rb, rtx Re, rtx En4, bool vaarg_p) |
9304f876 CJW |
368 | { |
369 | int regno; | |
370 | int extra_count; | |
371 | int num_use_regs; | |
372 | int par_index; | |
373 | int offset; | |
4e9a2848 | 374 | int save_fp, save_gp, save_lp; |
9304f876 CJW |
375 | |
376 | rtx reg; | |
377 | rtx mem; | |
378 | rtx push_rtx; | |
379 | rtx adjust_sp_rtx; | |
380 | rtx parallel_insn; | |
47e0e7d2 | 381 | rtx dwarf; |
9304f876 CJW |
382 | |
383 | /* We need to provide a customized rtx which contains | |
384 | necessary information for data analysis, | |
385 | so we create a parallel rtx like this: | |
386 | (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) | |
387 | (reg:SI Rb)) | |
388 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) | |
389 | (reg:SI Rb+1)) | |
390 | ... | |
391 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) | |
392 | (reg:SI Re)) | |
393 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) | |
394 | (reg:SI FP_REGNUM)) | |
395 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) | |
396 | (reg:SI GP_REGNUM)) | |
397 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) | |
398 | (reg:SI LP_REGNUM)) | |
399 | (set (reg:SI SP_REGNUM) | |
400 | (plus (reg:SI SP_REGNUM) (const_int -32)))]) */ | |
401 | ||
4e9a2848 CJW |
402 | /* Determine whether we need to save $fp, $gp, or $lp. */ |
403 | save_fp = INTVAL (En4) & 0x8; | |
404 | save_gp = INTVAL (En4) & 0x4; | |
405 | save_lp = INTVAL (En4) & 0x2; | |
406 | ||
9304f876 CJW |
407 | /* Calculate the number of registers that will be pushed. */ |
408 | extra_count = 0; | |
4e9a2848 | 409 | if (save_fp) |
9304f876 | 410 | extra_count++; |
4e9a2848 | 411 | if (save_gp) |
9304f876 | 412 | extra_count++; |
4e9a2848 | 413 | if (save_lp) |
9304f876 CJW |
414 | extra_count++; |
415 | /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ | |
416 | if (REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM) | |
417 | num_use_regs = extra_count; | |
418 | else | |
419 | num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + extra_count; | |
420 | ||
421 | /* In addition to used registers, | |
422 | we need one more space for (set sp sp-x) rtx. */ | |
423 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
424 | rtvec_alloc (num_use_regs + 1)); | |
425 | par_index = 0; | |
426 | ||
427 | /* Initialize offset and start to create push behavior. */ | |
428 | offset = -(num_use_regs * 4); | |
429 | ||
430 | /* Create (set mem regX) from Rb, Rb+1 up to Re. */ | |
431 | for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++) | |
432 | { | |
433 | /* Rb and Re may be SP_REGNUM. | |
434 | We need to break this loop immediately. */ | |
435 | if (regno == SP_REGNUM) | |
4e9a2848 | 436 | break; |
9304f876 CJW |
437 | |
438 | reg = gen_rtx_REG (SImode, regno); | |
439 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
440 | stack_pointer_rtx, | |
441 | offset)); | |
f7df4a84 | 442 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
443 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
444 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
445 | offset = offset + 4; | |
446 | par_index++; | |
447 | } | |
448 | ||
449 | /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */ | |
4e9a2848 | 450 | if (save_fp) |
9304f876 CJW |
451 | { |
452 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
453 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
454 | stack_pointer_rtx, | |
455 | offset)); | |
f7df4a84 | 456 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
457 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
458 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
459 | offset = offset + 4; | |
460 | par_index++; | |
461 | } | |
4e9a2848 | 462 | if (save_gp) |
9304f876 CJW |
463 | { |
464 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
465 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
466 | stack_pointer_rtx, | |
467 | offset)); | |
f7df4a84 | 468 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
469 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
470 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
471 | offset = offset + 4; | |
472 | par_index++; | |
473 | } | |
4e9a2848 | 474 | if (save_lp) |
9304f876 CJW |
475 | { |
476 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
477 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
478 | stack_pointer_rtx, | |
479 | offset)); | |
f7df4a84 | 480 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
481 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
482 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
483 | offset = offset + 4; | |
484 | par_index++; | |
485 | } | |
486 | ||
487 | /* Create (set sp sp-x). */ | |
488 | ||
489 | /* We need to re-calculate the offset value again for adjustment. */ | |
490 | offset = -(num_use_regs * 4); | |
491 | adjust_sp_rtx | |
f7df4a84 | 492 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
493 | plus_constant (Pmode, stack_pointer_rtx, offset)); |
494 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
495 | RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; | |
496 | ||
4e9a2848 CJW |
497 | parallel_insn = emit_insn (parallel_insn); |
498 | ||
499 | /* The insn rtx 'parallel_insn' will change frame layout. | |
500 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
501 | generate CFI (Call Frame Information) stuff. */ | |
502 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
47e0e7d2 CJW |
503 | |
504 | /* Don't use GCC's logic for CFI info if we are generate a push for VAARG | |
505 | since we will not restore those register at epilogue. */ | |
506 | if (vaarg_p) | |
507 | { | |
508 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, | |
509 | copy_rtx (adjust_sp_rtx), NULL_RTX); | |
510 | REG_NOTES (parallel_insn) = dwarf; | |
511 | } | |
9304f876 CJW |
512 | } |
513 | ||
514 | /* Function to create a parallel rtx pattern | |
515 | which presents stack pop multiple behavior. | |
516 | The overall concept are: | |
517 | "pop registers from memory", | |
518 | "adjust stack pointer". */ | |
4e9a2848 CJW |
519 | static void |
520 | nds32_emit_stack_pop_multiple (rtx Rb, rtx Re, rtx En4) | |
9304f876 CJW |
521 | { |
522 | int regno; | |
523 | int extra_count; | |
524 | int num_use_regs; | |
525 | int par_index; | |
526 | int offset; | |
4e9a2848 | 527 | int save_fp, save_gp, save_lp; |
9304f876 CJW |
528 | |
529 | rtx reg; | |
530 | rtx mem; | |
531 | rtx pop_rtx; | |
532 | rtx adjust_sp_rtx; | |
533 | rtx parallel_insn; | |
4e9a2848 | 534 | rtx dwarf = NULL_RTX; |
9304f876 CJW |
535 | |
536 | /* We need to provide a customized rtx which contains | |
537 | necessary information for data analysis, | |
538 | so we create a parallel rtx like this: | |
539 | (parallel [(set (reg:SI Rb) | |
540 | (mem (reg:SI SP_REGNUM))) | |
541 | (set (reg:SI Rb+1) | |
542 | (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) | |
543 | ... | |
544 | (set (reg:SI Re) | |
545 | (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) | |
546 | (set (reg:SI FP_REGNUM) | |
547 | (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) | |
548 | (set (reg:SI GP_REGNUM) | |
549 | (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) | |
550 | (set (reg:SI LP_REGNUM) | |
551 | (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) | |
552 | (set (reg:SI SP_REGNUM) | |
553 | (plus (reg:SI SP_REGNUM) (const_int 32)))]) */ | |
554 | ||
4e9a2848 CJW |
555 | /* Determine whether we need to restore $fp, $gp, or $lp. */ |
556 | save_fp = INTVAL (En4) & 0x8; | |
557 | save_gp = INTVAL (En4) & 0x4; | |
558 | save_lp = INTVAL (En4) & 0x2; | |
559 | ||
9304f876 CJW |
560 | /* Calculate the number of registers that will be poped. */ |
561 | extra_count = 0; | |
4e9a2848 | 562 | if (save_fp) |
9304f876 | 563 | extra_count++; |
4e9a2848 | 564 | if (save_gp) |
9304f876 | 565 | extra_count++; |
4e9a2848 | 566 | if (save_lp) |
9304f876 CJW |
567 | extra_count++; |
568 | /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ | |
569 | if (REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM) | |
570 | num_use_regs = extra_count; | |
571 | else | |
572 | num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + extra_count; | |
573 | ||
574 | /* In addition to used registers, | |
575 | we need one more space for (set sp sp+x) rtx. */ | |
576 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
577 | rtvec_alloc (num_use_regs + 1)); | |
578 | par_index = 0; | |
579 | ||
580 | /* Initialize offset and start to create pop behavior. */ | |
581 | offset = 0; | |
582 | ||
583 | /* Create (set regX mem) from Rb, Rb+1 up to Re. */ | |
584 | for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++) | |
585 | { | |
586 | /* Rb and Re may be SP_REGNUM. | |
587 | We need to break this loop immediately. */ | |
588 | if (regno == SP_REGNUM) | |
4e9a2848 | 589 | break; |
9304f876 CJW |
590 | |
591 | reg = gen_rtx_REG (SImode, regno); | |
592 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
593 | stack_pointer_rtx, | |
594 | offset)); | |
f7df4a84 | 595 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
596 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
597 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
598 | offset = offset + 4; | |
599 | par_index++; | |
4e9a2848 CJW |
600 | |
601 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
602 | } |
603 | ||
604 | /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */ | |
4e9a2848 | 605 | if (save_fp) |
9304f876 CJW |
606 | { |
607 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
608 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
609 | stack_pointer_rtx, | |
610 | offset)); | |
f7df4a84 | 611 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
612 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
613 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
614 | offset = offset + 4; | |
615 | par_index++; | |
4e9a2848 CJW |
616 | |
617 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 | 618 | } |
4e9a2848 | 619 | if (save_gp) |
9304f876 CJW |
620 | { |
621 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
622 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
623 | stack_pointer_rtx, | |
624 | offset)); | |
f7df4a84 | 625 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
626 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
627 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
628 | offset = offset + 4; | |
629 | par_index++; | |
4e9a2848 CJW |
630 | |
631 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 | 632 | } |
4e9a2848 | 633 | if (save_lp) |
9304f876 CJW |
634 | { |
635 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
636 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
637 | stack_pointer_rtx, | |
638 | offset)); | |
f7df4a84 | 639 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
640 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
641 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
642 | offset = offset + 4; | |
643 | par_index++; | |
4e9a2848 CJW |
644 | |
645 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
646 | } |
647 | ||
648 | /* Create (set sp sp+x). */ | |
649 | ||
650 | /* The offset value is already in place. No need to re-calculate it. */ | |
651 | adjust_sp_rtx | |
f7df4a84 | 652 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
653 | plus_constant (Pmode, stack_pointer_rtx, offset)); |
654 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
9304f876 | 655 | |
4e9a2848 CJW |
656 | /* Tell gcc we adjust SP in this insn. */ |
657 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, copy_rtx (adjust_sp_rtx), dwarf); | |
658 | ||
659 | parallel_insn = emit_insn (parallel_insn); | |
660 | ||
661 | /* The insn rtx 'parallel_insn' will change frame layout. | |
662 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
663 | generate CFI (Call Frame Information) stuff. */ | |
664 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
665 | ||
666 | /* Add CFI info by manual. */ | |
667 | REG_NOTES (parallel_insn) = dwarf; | |
9304f876 CJW |
668 | } |
669 | ||
670 | /* Function to create a parallel rtx pattern | |
671 | which presents stack v3push behavior. | |
672 | The overall concept are: | |
673 | "push registers to memory", | |
674 | "adjust stack pointer". */ | |
88437f39 CJW |
675 | static void |
676 | nds32_emit_stack_v3push (rtx Rb, | |
677 | rtx Re, | |
678 | rtx En4 ATTRIBUTE_UNUSED, | |
679 | rtx imm8u) | |
9304f876 CJW |
680 | { |
681 | int regno; | |
682 | int num_use_regs; | |
683 | int par_index; | |
684 | int offset; | |
685 | ||
686 | rtx reg; | |
687 | rtx mem; | |
688 | rtx push_rtx; | |
689 | rtx adjust_sp_rtx; | |
690 | rtx parallel_insn; | |
691 | ||
692 | /* We need to provide a customized rtx which contains | |
693 | necessary information for data analysis, | |
694 | so we create a parallel rtx like this: | |
88437f39 | 695 | (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) |
9304f876 CJW |
696 | (reg:SI Rb)) |
697 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) | |
698 | (reg:SI Rb+1)) | |
699 | ... | |
700 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) | |
701 | (reg:SI Re)) | |
702 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) | |
703 | (reg:SI FP_REGNUM)) | |
704 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) | |
705 | (reg:SI GP_REGNUM)) | |
706 | (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) | |
707 | (reg:SI LP_REGNUM)) | |
708 | (set (reg:SI SP_REGNUM) | |
709 | (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */ | |
710 | ||
711 | /* Calculate the number of registers that will be pushed. | |
712 | Since $fp, $gp, and $lp is always pushed with v3push instruction, | |
713 | we need to count these three registers. | |
714 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
715 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
716 | num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + 3; | |
717 | ||
718 | /* In addition to used registers, | |
719 | we need one more space for (set sp sp-x-imm8u) rtx. */ | |
720 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
721 | rtvec_alloc (num_use_regs + 1)); | |
722 | par_index = 0; | |
723 | ||
724 | /* Initialize offset and start to create push behavior. */ | |
725 | offset = -(num_use_regs * 4); | |
726 | ||
727 | /* Create (set mem regX) from Rb, Rb+1 up to Re. | |
728 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
729 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
730 | for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++) | |
731 | { | |
732 | reg = gen_rtx_REG (SImode, regno); | |
733 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
734 | stack_pointer_rtx, | |
735 | offset)); | |
f7df4a84 | 736 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
737 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
738 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
739 | offset = offset + 4; | |
740 | par_index++; | |
741 | } | |
742 | ||
743 | /* Create (set mem fp). */ | |
744 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
745 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
746 | stack_pointer_rtx, | |
747 | offset)); | |
f7df4a84 | 748 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
749 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
750 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
751 | offset = offset + 4; | |
752 | par_index++; | |
753 | /* Create (set mem gp). */ | |
754 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
755 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
756 | stack_pointer_rtx, | |
757 | offset)); | |
f7df4a84 | 758 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
759 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
760 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
761 | offset = offset + 4; | |
762 | par_index++; | |
763 | /* Create (set mem lp). */ | |
764 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
765 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
766 | stack_pointer_rtx, | |
767 | offset)); | |
f7df4a84 | 768 | push_rtx = gen_rtx_SET (mem, reg); |
9304f876 CJW |
769 | XVECEXP (parallel_insn, 0, par_index) = push_rtx; |
770 | RTX_FRAME_RELATED_P (push_rtx) = 1; | |
771 | offset = offset + 4; | |
772 | par_index++; | |
773 | ||
774 | /* Create (set sp sp-x-imm8u). */ | |
775 | ||
776 | /* We need to re-calculate the offset value again for adjustment. */ | |
777 | offset = -(num_use_regs * 4); | |
778 | adjust_sp_rtx | |
f7df4a84 | 779 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
780 | plus_constant (Pmode, |
781 | stack_pointer_rtx, | |
782 | offset - INTVAL (imm8u))); | |
783 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
784 | RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; | |
785 | ||
88437f39 CJW |
786 | parallel_insn = emit_insn (parallel_insn); |
787 | ||
788 | /* The insn rtx 'parallel_insn' will change frame layout. | |
789 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
790 | generate CFI (Call Frame Information) stuff. */ | |
791 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
9304f876 CJW |
792 | } |
793 | ||
794 | /* Function to create a parallel rtx pattern | |
795 | which presents stack v3pop behavior. | |
796 | The overall concept are: | |
797 | "pop registers from memory", | |
798 | "adjust stack pointer". */ | |
88437f39 CJW |
799 | static void |
800 | nds32_emit_stack_v3pop (rtx Rb, | |
801 | rtx Re, | |
802 | rtx En4 ATTRIBUTE_UNUSED, | |
803 | rtx imm8u) | |
9304f876 CJW |
804 | { |
805 | int regno; | |
806 | int num_use_regs; | |
807 | int par_index; | |
808 | int offset; | |
809 | ||
810 | rtx reg; | |
811 | rtx mem; | |
812 | rtx pop_rtx; | |
813 | rtx adjust_sp_rtx; | |
814 | rtx parallel_insn; | |
88437f39 | 815 | rtx dwarf = NULL_RTX; |
9304f876 CJW |
816 | |
817 | /* We need to provide a customized rtx which contains | |
818 | necessary information for data analysis, | |
819 | so we create a parallel rtx like this: | |
820 | (parallel [(set (reg:SI Rb) | |
821 | (mem (reg:SI SP_REGNUM))) | |
822 | (set (reg:SI Rb+1) | |
823 | (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) | |
824 | ... | |
825 | (set (reg:SI Re) | |
826 | (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) | |
827 | (set (reg:SI FP_REGNUM) | |
828 | (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) | |
829 | (set (reg:SI GP_REGNUM) | |
830 | (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) | |
831 | (set (reg:SI LP_REGNUM) | |
832 | (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) | |
833 | (set (reg:SI SP_REGNUM) | |
834 | (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */ | |
835 | ||
836 | /* Calculate the number of registers that will be poped. | |
837 | Since $fp, $gp, and $lp is always poped with v3pop instruction, | |
838 | we need to count these three registers. | |
839 | Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
840 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
841 | num_use_regs = REGNO (Re) - REGNO (Rb) + 1 + 3; | |
842 | ||
843 | /* In addition to used registers, | |
844 | we need one more space for (set sp sp+x+imm8u) rtx. */ | |
845 | parallel_insn = gen_rtx_PARALLEL (VOIDmode, | |
846 | rtvec_alloc (num_use_regs + 1)); | |
847 | par_index = 0; | |
848 | ||
849 | /* Initialize offset and start to create pop behavior. */ | |
850 | offset = 0; | |
851 | ||
852 | /* Create (set regX mem) from Rb, Rb+1 up to Re. | |
853 | Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. | |
854 | So there is no need to worry about Rb=Re=SP_REGNUM case. */ | |
855 | for (regno = REGNO (Rb); regno <= (int) REGNO (Re); regno++) | |
856 | { | |
857 | reg = gen_rtx_REG (SImode, regno); | |
858 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
859 | stack_pointer_rtx, | |
860 | offset)); | |
f7df4a84 | 861 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
862 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
863 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
864 | offset = offset + 4; | |
865 | par_index++; | |
88437f39 CJW |
866 | |
867 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); | |
9304f876 CJW |
868 | } |
869 | ||
870 | /* Create (set fp mem). */ | |
871 | reg = gen_rtx_REG (SImode, FP_REGNUM); | |
872 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
873 | stack_pointer_rtx, | |
874 | offset)); | |
f7df4a84 | 875 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
876 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
877 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
878 | offset = offset + 4; | |
879 | par_index++; | |
88437f39 CJW |
880 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
881 | ||
9304f876 CJW |
882 | /* Create (set gp mem). */ |
883 | reg = gen_rtx_REG (SImode, GP_REGNUM); | |
884 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
885 | stack_pointer_rtx, | |
886 | offset)); | |
f7df4a84 | 887 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
888 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
889 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
890 | offset = offset + 4; | |
891 | par_index++; | |
88437f39 CJW |
892 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
893 | ||
9304f876 CJW |
894 | /* Create (set lp mem ). */ |
895 | reg = gen_rtx_REG (SImode, LP_REGNUM); | |
896 | mem = gen_frame_mem (SImode, plus_constant (Pmode, | |
897 | stack_pointer_rtx, | |
898 | offset)); | |
f7df4a84 | 899 | pop_rtx = gen_rtx_SET (reg, mem); |
9304f876 CJW |
900 | XVECEXP (parallel_insn, 0, par_index) = pop_rtx; |
901 | RTX_FRAME_RELATED_P (pop_rtx) = 1; | |
902 | offset = offset + 4; | |
903 | par_index++; | |
88437f39 | 904 | dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); |
9304f876 CJW |
905 | |
906 | /* Create (set sp sp+x+imm8u). */ | |
907 | ||
908 | /* The offset value is already in place. No need to re-calculate it. */ | |
909 | adjust_sp_rtx | |
f7df4a84 | 910 | = gen_rtx_SET (stack_pointer_rtx, |
9304f876 CJW |
911 | plus_constant (Pmode, |
912 | stack_pointer_rtx, | |
913 | offset + INTVAL (imm8u))); | |
914 | XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; | |
9304f876 | 915 | |
88437f39 CJW |
916 | /* Tell gcc we adjust SP in this insn. */ |
917 | dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, copy_rtx (adjust_sp_rtx), dwarf); | |
918 | ||
919 | parallel_insn = emit_insn (parallel_insn); | |
920 | ||
921 | /* The insn rtx 'parallel_insn' will change frame layout. | |
922 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
923 | generate CFI (Call Frame Information) stuff. */ | |
924 | RTX_FRAME_RELATED_P (parallel_insn) = 1; | |
925 | ||
926 | /* Add CFI info by manual. */ | |
927 | REG_NOTES (parallel_insn) = dwarf; | |
9304f876 CJW |
928 | } |
929 | ||
9304f876 CJW |
930 | /* Function that may creates more instructions |
931 | for large value on adjusting stack pointer. | |
932 | ||
933 | In nds32 target, 'addi' can be used for stack pointer | |
934 | adjustment in prologue/epilogue stage. | |
935 | However, sometimes there are too many local variables so that | |
936 | the adjustment value is not able to be fit in the 'addi' instruction. | |
937 | One solution is to move value into a register | |
938 | and then use 'add' instruction. | |
939 | In practice, we use TA_REGNUM ($r15) to accomplish this purpose. | |
940 | Also, we need to return zero for sp adjustment so that | |
941 | proglogue/epilogue knows there is no need to create 'addi' instruction. */ | |
942 | static int | |
943 | nds32_force_addi_stack_int (int full_value) | |
944 | { | |
945 | int adjust_value; | |
946 | ||
947 | rtx tmp_reg; | |
948 | rtx sp_adjust_insn; | |
949 | ||
950 | if (!satisfies_constraint_Is15 (GEN_INT (full_value))) | |
951 | { | |
952 | /* The value is not able to fit in single addi instruction. | |
953 | Create more instructions of moving value into a register | |
954 | and then add stack pointer with it. */ | |
955 | ||
956 | /* $r15 is going to be temporary register to hold the value. */ | |
957 | tmp_reg = gen_rtx_REG (SImode, TA_REGNUM); | |
958 | ||
959 | /* Create one more instruction to move value | |
960 | into the temporary register. */ | |
961 | emit_move_insn (tmp_reg, GEN_INT (full_value)); | |
962 | ||
963 | /* Create new 'add' rtx. */ | |
964 | sp_adjust_insn = gen_addsi3 (stack_pointer_rtx, | |
965 | stack_pointer_rtx, | |
966 | tmp_reg); | |
967 | /* Emit rtx into insn list and receive its transformed insn rtx. */ | |
968 | sp_adjust_insn = emit_insn (sp_adjust_insn); | |
969 | ||
970 | /* At prologue, we need to tell GCC that this is frame related insn, | |
971 | so that we can consider this instruction to output debug information. | |
972 | If full_value is NEGATIVE, it means this function | |
973 | is invoked by expand_prologue. */ | |
974 | if (full_value < 0) | |
975 | { | |
976 | /* Because (tmp_reg <- full_value) may be split into two | |
977 | rtl patterns, we can not set its RTX_FRAME_RELATED_P. | |
978 | We need to construct another (sp <- sp + full_value) | |
979 | and then insert it into sp_adjust_insn's reg note to | |
980 | represent a frame related expression. | |
981 | GCC knows how to refer it and output debug information. */ | |
982 | ||
983 | rtx plus_rtx; | |
984 | rtx set_rtx; | |
985 | ||
986 | plus_rtx = plus_constant (Pmode, stack_pointer_rtx, full_value); | |
f7df4a84 | 987 | set_rtx = gen_rtx_SET (stack_pointer_rtx, plus_rtx); |
9304f876 CJW |
988 | add_reg_note (sp_adjust_insn, REG_FRAME_RELATED_EXPR, set_rtx); |
989 | ||
990 | RTX_FRAME_RELATED_P (sp_adjust_insn) = 1; | |
991 | } | |
992 | ||
993 | /* We have used alternative way to adjust stack pointer value. | |
994 | Return zero so that prologue/epilogue | |
995 | will not generate other instructions. */ | |
996 | return 0; | |
997 | } | |
998 | else | |
999 | { | |
1000 | /* The value is able to fit in addi instruction. | |
1001 | However, remember to make it to be positive value | |
1002 | because we want to return 'adjustment' result. */ | |
1003 | adjust_value = (full_value < 0) ? (-full_value) : (full_value); | |
1004 | ||
1005 | return adjust_value; | |
1006 | } | |
1007 | } | |
1008 | ||
1009 | /* Return true if MODE/TYPE need double word alignment. */ | |
1010 | static bool | |
ef4bddc2 | 1011 | nds32_needs_double_word_align (machine_mode mode, const_tree type) |
9304f876 CJW |
1012 | { |
1013 | unsigned int align; | |
1014 | ||
634bdae9 CJW |
1015 | /* Pick up the alignment according to the mode or type. */ |
1016 | align = NDS32_MODE_TYPE_ALIGN (mode, type); | |
9304f876 CJW |
1017 | |
1018 | return (align > PARM_BOUNDARY); | |
1019 | } | |
1020 | ||
1021 | /* Return true if FUNC is a naked function. */ | |
810f736f CJW |
1022 | static bool |
1023 | nds32_naked_function_p (tree func) | |
9304f876 CJW |
1024 | { |
1025 | tree t; | |
1026 | ||
1027 | if (TREE_CODE (func) != FUNCTION_DECL) | |
1028 | abort (); | |
1029 | ||
1030 | t = lookup_attribute ("naked", DECL_ATTRIBUTES (func)); | |
1031 | ||
1032 | return (t != NULL_TREE); | |
1033 | } | |
1034 | ||
1035 | /* Function that check if 'X' is a valid address register. | |
1036 | The variable 'STRICT' is very important to | |
1037 | make decision for register number. | |
1038 | ||
1039 | STRICT : true | |
1040 | => We are in reload pass or after reload pass. | |
1041 | The register number should be strictly limited in general registers. | |
1042 | ||
1043 | STRICT : false | |
1044 | => Before reload pass, we are free to use any register number. */ | |
1045 | static bool | |
1046 | nds32_address_register_rtx_p (rtx x, bool strict) | |
1047 | { | |
1048 | int regno; | |
1049 | ||
1050 | if (GET_CODE (x) != REG) | |
1051 | return false; | |
1052 | ||
1053 | regno = REGNO (x); | |
1054 | ||
1055 | if (strict) | |
1056 | return REGNO_OK_FOR_BASE_P (regno); | |
1057 | else | |
1058 | return true; | |
1059 | } | |
1060 | ||
1061 | /* Function that check if 'INDEX' is valid to be a index rtx for address. | |
1062 | ||
1063 | OUTER_MODE : Machine mode of outer address rtx. | |
1064 | INDEX : Check if this rtx is valid to be a index for address. | |
1065 | STRICT : If it is true, we are in reload pass or after reload pass. */ | |
1066 | static bool | |
ef4bddc2 | 1067 | nds32_legitimate_index_p (machine_mode outer_mode, |
9304f876 CJW |
1068 | rtx index, |
1069 | bool strict) | |
1070 | { | |
1071 | int regno; | |
1072 | rtx op0; | |
1073 | rtx op1; | |
1074 | ||
1075 | switch (GET_CODE (index)) | |
1076 | { | |
1077 | case REG: | |
1078 | regno = REGNO (index); | |
1079 | /* If we are in reload pass or after reload pass, | |
1080 | we need to limit it to general register. */ | |
1081 | if (strict) | |
1082 | return REGNO_OK_FOR_INDEX_P (regno); | |
1083 | else | |
1084 | return true; | |
1085 | ||
1086 | case CONST_INT: | |
1087 | /* The alignment of the integer value is determined by 'outer_mode'. */ | |
1088 | if (GET_MODE_SIZE (outer_mode) == 1) | |
1089 | { | |
1090 | /* Further check if the value is legal for the 'outer_mode'. */ | |
1091 | if (!satisfies_constraint_Is15 (index)) | |
1092 | return false; | |
1093 | ||
1094 | /* Pass all test, the value is valid, return true. */ | |
1095 | return true; | |
1096 | } | |
1097 | if (GET_MODE_SIZE (outer_mode) == 2 | |
1098 | && NDS32_HALF_WORD_ALIGN_P (INTVAL (index))) | |
1099 | { | |
1100 | /* Further check if the value is legal for the 'outer_mode'. */ | |
1101 | if (!satisfies_constraint_Is16 (index)) | |
1102 | return false; | |
1103 | ||
1104 | /* Pass all test, the value is valid, return true. */ | |
1105 | return true; | |
1106 | } | |
1107 | if (GET_MODE_SIZE (outer_mode) == 4 | |
1108 | && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) | |
1109 | { | |
1110 | /* Further check if the value is legal for the 'outer_mode'. */ | |
1111 | if (!satisfies_constraint_Is17 (index)) | |
1112 | return false; | |
1113 | ||
1114 | /* Pass all test, the value is valid, return true. */ | |
1115 | return true; | |
1116 | } | |
1117 | if (GET_MODE_SIZE (outer_mode) == 8 | |
1118 | && NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) | |
1119 | { | |
1120 | /* Further check if the value is legal for the 'outer_mode'. */ | |
1121 | if (!satisfies_constraint_Is17 (gen_int_mode (INTVAL (index) + 4, | |
1122 | SImode))) | |
1123 | return false; | |
1124 | ||
1125 | /* Pass all test, the value is valid, return true. */ | |
1126 | return true; | |
1127 | } | |
1128 | ||
1129 | return false; | |
1130 | ||
1131 | case MULT: | |
1132 | op0 = XEXP (index, 0); | |
1133 | op1 = XEXP (index, 1); | |
1134 | ||
1135 | if (REG_P (op0) && CONST_INT_P (op1)) | |
1136 | { | |
1137 | int multiplier; | |
1138 | multiplier = INTVAL (op1); | |
1139 | ||
1140 | /* We only allow (mult reg const_int_1) | |
1141 | or (mult reg const_int_2) or (mult reg const_int_4). */ | |
1142 | if (multiplier != 1 && multiplier != 2 && multiplier != 4) | |
1143 | return false; | |
1144 | ||
1145 | regno = REGNO (op0); | |
1146 | /* Limit it in general registers if we are | |
1147 | in reload pass or after reload pass. */ | |
1148 | if(strict) | |
1149 | return REGNO_OK_FOR_INDEX_P (regno); | |
1150 | else | |
1151 | return true; | |
1152 | } | |
1153 | ||
1154 | return false; | |
1155 | ||
1156 | case ASHIFT: | |
1157 | op0 = XEXP (index, 0); | |
1158 | op1 = XEXP (index, 1); | |
1159 | ||
1160 | if (REG_P (op0) && CONST_INT_P (op1)) | |
1161 | { | |
1162 | int sv; | |
1163 | /* op1 is already the sv value for use to do left shift. */ | |
1164 | sv = INTVAL (op1); | |
1165 | ||
1166 | /* We only allow (ashift reg const_int_0) | |
1167 | or (ashift reg const_int_1) or (ashift reg const_int_2). */ | |
1168 | if (sv != 0 && sv != 1 && sv !=2) | |
1169 | return false; | |
1170 | ||
1171 | regno = REGNO (op0); | |
1172 | /* Limit it in general registers if we are | |
1173 | in reload pass or after reload pass. */ | |
1174 | if(strict) | |
1175 | return REGNO_OK_FOR_INDEX_P (regno); | |
1176 | else | |
1177 | return true; | |
1178 | } | |
1179 | ||
1180 | return false; | |
1181 | ||
1182 | default: | |
1183 | return false; | |
1184 | } | |
1185 | } | |
1186 | ||
9304f876 CJW |
1187 | /* ------------------------------------------------------------------------ */ |
1188 | ||
1189 | /* PART 3: Implement target hook stuff definitions. */ | |
1190 | \f | |
1191 | /* Register Classes. */ | |
1192 | ||
1193 | static unsigned char | |
1194 | nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED, | |
ef4bddc2 | 1195 | machine_mode mode) |
9304f876 CJW |
1196 | { |
1197 | /* Return the maximum number of consecutive registers | |
1198 | needed to represent "mode" in a register of "rclass". */ | |
1199 | return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); | |
1200 | } | |
1201 | ||
1202 | static int | |
1203 | nds32_register_priority (int hard_regno) | |
1204 | { | |
1205 | /* Encourage to use r0-r7 for LRA when optimize for size. */ | |
1206 | if (optimize_size && hard_regno < 8) | |
1207 | return 4; | |
1208 | return 3; | |
1209 | } | |
1210 | ||
1211 | \f | |
1212 | /* Stack Layout and Calling Conventions. */ | |
1213 | ||
1214 | /* There are three kinds of pointer concepts using in GCC compiler: | |
1215 | ||
1216 | frame pointer: A pointer to the first location of local variables. | |
1217 | stack pointer: A pointer to the top of a stack frame. | |
1218 | argument pointer: A pointer to the incoming arguments. | |
1219 | ||
1220 | In nds32 target calling convention, we are using 8-byte alignment. | |
1221 | Besides, we would like to have each stack frame of a function includes: | |
1222 | ||
1223 | [Block A] | |
1224 | 1. previous hard frame pointer | |
1225 | 2. return address | |
1226 | 3. callee-saved registers | |
1227 | 4. <padding bytes> (we will calculte in nds32_compute_stack_frame() | |
1228 | and save it at | |
1229 | cfun->machine->callee_saved_area_padding_bytes) | |
1230 | ||
1231 | [Block B] | |
1232 | 1. local variables | |
1233 | 2. spilling location | |
1234 | 3. <padding bytes> (it will be calculated by GCC itself) | |
1235 | 4. incoming arguments | |
1236 | 5. <padding bytes> (it will be calculated by GCC itself) | |
1237 | ||
1238 | [Block C] | |
1239 | 1. <padding bytes> (it will be calculated by GCC itself) | |
1240 | 2. outgoing arguments | |
1241 | ||
1242 | We 'wrap' these blocks together with | |
1243 | hard frame pointer ($r28) and stack pointer ($r31). | |
1244 | By applying the basic frame/stack/argument pointers concept, | |
1245 | the layout of a stack frame shoule be like this: | |
1246 | ||
1247 | | | | |
1248 | old stack pointer -> ---- | |
1249 | | | \ | |
1250 | | | saved arguments for | |
1251 | | | vararg functions | |
1252 | | | / | |
1253 | hard frame pointer -> -- | |
1254 | & argument pointer | | \ | |
1255 | | | previous hardware frame pointer | |
1256 | | | return address | |
1257 | | | callee-saved registers | |
1258 | | | / | |
1259 | frame pointer -> -- | |
1260 | | | \ | |
1261 | | | local variables | |
1262 | | | and incoming arguments | |
1263 | | | / | |
1264 | -- | |
1265 | | | \ | |
1266 | | | outgoing | |
1267 | | | arguments | |
1268 | | | / | |
1269 | stack pointer -> ---- | |
1270 | ||
1271 | $SFP and $AP are used to represent frame pointer and arguments pointer, | |
1272 | which will be both eliminated as hard frame pointer. */ | |
1273 | ||
1274 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
1275 | ||
19ac960a CJW |
1276 | static bool |
1277 | nds32_can_eliminate (const int from_reg, const int to_reg) | |
9304f876 CJW |
1278 | { |
1279 | if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
1280 | return true; | |
1281 | ||
1282 | if (from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) | |
1283 | return true; | |
1284 | ||
1285 | if (from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
1286 | return true; | |
1287 | ||
1288 | if (from_reg == FRAME_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) | |
1289 | return true; | |
1290 | ||
1291 | return false; | |
1292 | } | |
1293 | ||
1294 | /* -- Passing Arguments in Registers. */ | |
1295 | ||
1296 | static rtx | |
ef4bddc2 | 1297 | nds32_function_arg (cumulative_args_t ca, machine_mode mode, |
9304f876 CJW |
1298 | const_tree type, bool named) |
1299 | { | |
7f6cd86b | 1300 | unsigned int regno; |
9304f876 CJW |
1301 | CUMULATIVE_ARGS *cum = get_cumulative_args (ca); |
1302 | ||
1303 | /* The last time this hook is called, | |
1304 | it is called with MODE == VOIDmode. */ | |
1305 | if (mode == VOIDmode) | |
1306 | return NULL_RTX; | |
1307 | ||
7f6cd86b | 1308 | /* For nameless arguments, we need to take care it individually. */ |
9304f876 | 1309 | if (!named) |
9304f876 | 1310 | { |
7f6cd86b CJW |
1311 | /* If we are under hard float abi, we have arguments passed on the |
1312 | stack and all situation can be handled by GCC itself. */ | |
1313 | if (TARGET_HARD_FLOAT) | |
1314 | return NULL_RTX; | |
1315 | ||
1316 | if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) | |
1317 | { | |
1318 | /* If we still have enough registers to pass argument, pick up | |
1319 | next available register number. */ | |
1320 | regno | |
1321 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1322 | return gen_rtx_REG (mode, regno); | |
1323 | } | |
634bdae9 | 1324 | |
9304f876 CJW |
1325 | /* No register available, return NULL_RTX. |
1326 | The compiler will use stack to pass argument instead. */ | |
1327 | return NULL_RTX; | |
1328 | } | |
7f6cd86b CJW |
1329 | |
1330 | /* The following is to handle named argument. | |
1331 | Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT | |
1332 | are different. */ | |
1333 | if (TARGET_HARD_FLOAT) | |
1334 | { | |
1335 | /* Currently we have not implemented hard float yet. */ | |
1336 | gcc_unreachable (); | |
1337 | } | |
1338 | else | |
1339 | { | |
1340 | /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass | |
1341 | argument. Since we allow to pass argument partially in registers, | |
1342 | we can just return it if there are still registers available. */ | |
1343 | if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) | |
1344 | { | |
1345 | /* Pick up the next available register number. */ | |
1346 | regno | |
1347 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); | |
1348 | return gen_rtx_REG (mode, regno); | |
1349 | } | |
1350 | ||
1351 | } | |
1352 | ||
1353 | /* No register available, return NULL_RTX. | |
1354 | The compiler will use stack to pass argument instead. */ | |
1355 | return NULL_RTX; | |
9304f876 CJW |
1356 | } |
1357 | ||
d40f3c40 | 1358 | static bool |
ef4bddc2 | 1359 | nds32_must_pass_in_stack (machine_mode mode, const_tree type) |
d40f3c40 CJW |
1360 | { |
1361 | /* Return true if a type must be passed in memory. | |
1362 | If it is NOT using hard float abi, small aggregates can be | |
1363 | passed in a register even we are calling a variadic function. | |
1364 | So there is no need to take padding into consideration. */ | |
1365 | if (TARGET_HARD_FLOAT) | |
1366 | return must_pass_in_stack_var_size_or_pad (mode, type); | |
1367 | else | |
1368 | return must_pass_in_stack_var_size (mode, type); | |
1369 | } | |
1370 | ||
650fc469 | 1371 | static int |
ef4bddc2 | 1372 | nds32_arg_partial_bytes (cumulative_args_t ca, machine_mode mode, |
650fc469 CJW |
1373 | tree type, bool named ATTRIBUTE_UNUSED) |
1374 | { | |
1375 | /* Returns the number of bytes at the beginning of an argument that | |
1376 | must be put in registers. The value must be zero for arguments that are | |
1377 | passed entirely in registers or that are entirely pushed on the stack. | |
1378 | Besides, TARGET_FUNCTION_ARG for these arguments should return the | |
1379 | first register to be used by the caller for this argument. */ | |
1380 | unsigned int needed_reg_count; | |
1381 | unsigned int remaining_reg_count; | |
1382 | CUMULATIVE_ARGS *cum; | |
1383 | ||
1384 | cum = get_cumulative_args (ca); | |
1385 | ||
1386 | /* Under hard float abi, we better have argument entirely passed in | |
1387 | registers or pushed on the stack so that we can reduce the complexity | |
1388 | of dealing with cum->gpr_offset and cum->fpr_offset. */ | |
1389 | if (TARGET_HARD_FLOAT) | |
1390 | return 0; | |
1391 | ||
1392 | /* If we have already runned out of argument registers, return zero | |
1393 | so that the argument will be entirely pushed on the stack. */ | |
1394 | if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
1395 | >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS) | |
1396 | return 0; | |
1397 | ||
1398 | /* Calculate how many registers do we need for this argument. */ | |
1399 | needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
1400 | ||
1401 | /* Calculate how many argument registers have left for passing argument. | |
1402 | Note that we should count it from next available register number. */ | |
1403 | remaining_reg_count | |
1404 | = NDS32_MAX_GPR_REGS_FOR_ARGS | |
1405 | - (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
1406 | - NDS32_GPR_ARG_FIRST_REGNUM); | |
1407 | ||
1408 | /* Note that we have to return the nubmer of bytes, not registers count. */ | |
1409 | if (needed_reg_count > remaining_reg_count) | |
1410 | return remaining_reg_count * UNITS_PER_WORD; | |
1411 | ||
1412 | return 0; | |
1413 | } | |
1414 | ||
9304f876 | 1415 | static void |
ef4bddc2 | 1416 | nds32_function_arg_advance (cumulative_args_t ca, machine_mode mode, |
9304f876 CJW |
1417 | const_tree type, bool named) |
1418 | { | |
ef4bddc2 | 1419 | machine_mode sub_mode; |
9304f876 CJW |
1420 | CUMULATIVE_ARGS *cum = get_cumulative_args (ca); |
1421 | ||
9304f876 CJW |
1422 | if (named) |
1423 | { | |
7f6cd86b CJW |
1424 | /* We need to further check TYPE and MODE so that we can determine |
1425 | which kind of register we shall advance. */ | |
1426 | if (type && TREE_CODE (type) == COMPLEX_TYPE) | |
1427 | sub_mode = TYPE_MODE (TREE_TYPE (type)); | |
1428 | else | |
1429 | sub_mode = mode; | |
1430 | ||
1431 | /* Under hard float abi, we may advance FPR registers. */ | |
1432 | if (TARGET_HARD_FLOAT && GET_MODE_CLASS (sub_mode) == MODE_FLOAT) | |
1433 | { | |
1434 | /* Currently we have not implemented hard float yet. */ | |
1435 | gcc_unreachable (); | |
1436 | } | |
1437 | else | |
1438 | { | |
1439 | cum->gpr_offset | |
1440 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
1441 | - NDS32_GPR_ARG_FIRST_REGNUM | |
1442 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
1443 | } | |
1444 | } | |
1445 | else | |
1446 | { | |
1447 | /* If this nameless argument is NOT under TARGET_HARD_FLOAT, | |
1448 | we can advance next register as well so that caller is | |
1449 | able to pass arguments in registers and callee must be | |
1450 | in charge of pushing all of them into stack. */ | |
1451 | if (!TARGET_HARD_FLOAT) | |
1452 | { | |
1453 | cum->gpr_offset | |
1454 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
1455 | - NDS32_GPR_ARG_FIRST_REGNUM | |
1456 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
1457 | } | |
9304f876 CJW |
1458 | } |
1459 | } | |
1460 | ||
1461 | static unsigned int | |
ef4bddc2 | 1462 | nds32_function_arg_boundary (machine_mode mode, const_tree type) |
9304f876 CJW |
1463 | { |
1464 | return (nds32_needs_double_word_align (mode, type) | |
1465 | ? NDS32_DOUBLE_WORD_ALIGNMENT | |
1466 | : PARM_BOUNDARY); | |
1467 | } | |
1468 | ||
1469 | /* -- How Scalar Function Values Are Returned. */ | |
1470 | ||
1471 | static rtx | |
1472 | nds32_function_value (const_tree ret_type, | |
1473 | const_tree fn_decl_or_type ATTRIBUTE_UNUSED, | |
1474 | bool outgoing ATTRIBUTE_UNUSED) | |
1475 | { | |
ef4bddc2 | 1476 | machine_mode mode; |
9304f876 CJW |
1477 | int unsignedp; |
1478 | ||
1479 | mode = TYPE_MODE (ret_type); | |
1480 | unsignedp = TYPE_UNSIGNED (ret_type); | |
1481 | ||
1482 | mode = promote_mode (ret_type, mode, &unsignedp); | |
1483 | ||
1484 | return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); | |
1485 | } | |
1486 | ||
1487 | static rtx | |
ef4bddc2 | 1488 | nds32_libcall_value (machine_mode mode, |
9304f876 CJW |
1489 | const_rtx fun ATTRIBUTE_UNUSED) |
1490 | { | |
1491 | return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); | |
1492 | } | |
1493 | ||
1494 | static bool | |
1495 | nds32_function_value_regno_p (const unsigned int regno) | |
1496 | { | |
1497 | return (regno == NDS32_GPR_RET_FIRST_REGNUM); | |
1498 | } | |
1499 | ||
1500 | /* -- Function Entry and Exit. */ | |
1501 | ||
1502 | /* The content produced from this function | |
1503 | will be placed before prologue body. */ | |
1504 | static void | |
42776416 | 1505 | nds32_asm_function_prologue (FILE *file) |
9304f876 CJW |
1506 | { |
1507 | int r; | |
1508 | const char *func_name; | |
1509 | tree attrs; | |
1510 | tree name; | |
1511 | ||
1512 | /* All stack frame information is supposed to be | |
1513 | already computed when expanding prologue. | |
1514 | The result is in cfun->machine. | |
1515 | DO NOT call nds32_compute_stack_frame() here | |
1516 | because it may corrupt the essential information. */ | |
1517 | ||
1518 | fprintf (file, "\t! BEGIN PROLOGUE\n"); | |
1519 | fprintf (file, "\t! fp needed: %d\n", frame_pointer_needed); | |
1520 | fprintf (file, "\t! pretend_args: %d\n", cfun->machine->va_args_size); | |
1521 | fprintf (file, "\t! local_size: %d\n", cfun->machine->local_size); | |
1522 | fprintf (file, "\t! out_args_size: %d\n", cfun->machine->out_args_size); | |
1523 | ||
1524 | /* Use df_regs_ever_live_p() to detect if the register | |
1525 | is ever used in the current function. */ | |
1526 | fprintf (file, "\t! registers ever_live: "); | |
1527 | for (r = 0; r < 32; r++) | |
1528 | { | |
1529 | if (df_regs_ever_live_p (r)) | |
1530 | fprintf (file, "%s, ", reg_names[r]); | |
1531 | } | |
1532 | fputc ('\n', file); | |
1533 | ||
1534 | /* Display the attributes of this function. */ | |
1535 | fprintf (file, "\t! function attributes: "); | |
f2dafb91 CJW |
1536 | /* Get the attributes tree list. |
1537 | Note that GCC builds attributes list with reverse order. */ | |
1538 | attrs = DECL_ATTRIBUTES (current_function_decl); | |
9304f876 CJW |
1539 | |
1540 | /* If there is no any attribute, print out "None". */ | |
1541 | if (!attrs) | |
1542 | fprintf (file, "None"); | |
1543 | ||
1544 | /* If there are some attributes, try if we need to | |
1545 | construct isr vector information. */ | |
1546 | func_name = IDENTIFIER_POINTER (DECL_NAME (current_function_decl)); | |
1547 | nds32_construct_isr_vectors_information (attrs, func_name); | |
1548 | ||
1549 | /* Display all attributes of this function. */ | |
1550 | while (attrs) | |
1551 | { | |
1552 | name = TREE_PURPOSE (attrs); | |
1553 | fprintf (file, "%s ", IDENTIFIER_POINTER (name)); | |
1554 | ||
1555 | /* Pick up the next attribute. */ | |
1556 | attrs = TREE_CHAIN (attrs); | |
1557 | } | |
1558 | fputc ('\n', file); | |
1559 | } | |
1560 | ||
1561 | /* After rtl prologue has been expanded, this function is used. */ | |
1562 | static void | |
1563 | nds32_asm_function_end_prologue (FILE *file) | |
1564 | { | |
1565 | fprintf (file, "\t! END PROLOGUE\n"); | |
1566 | ||
1567 | /* If frame pointer is NOT needed and -mfp-as-gp is issued, | |
1568 | we can generate special directive: ".omit_fp_begin" | |
1569 | to guide linker doing fp-as-gp optimization. | |
1570 | However, for a naked function, which means | |
1571 | it should not have prologue/epilogue, | |
1572 | using fp-as-gp still requires saving $fp by push/pop behavior and | |
1573 | there is no benefit to use fp-as-gp on such small function. | |
1574 | So we need to make sure this function is NOT naked as well. */ | |
1575 | if (!frame_pointer_needed | |
1576 | && !cfun->machine->naked_p | |
1577 | && cfun->machine->fp_as_gp_p) | |
1578 | { | |
1579 | fprintf (file, "\t! ----------------------------------------\n"); | |
1580 | fprintf (file, "\t! Guide linker to do " | |
1581 | "link time optimization: fp-as-gp\n"); | |
1582 | fprintf (file, "\t! We add one more instruction to " | |
1583 | "initialize $fp near to $gp location.\n"); | |
1584 | fprintf (file, "\t! If linker fails to use fp-as-gp transformation,\n"); | |
1585 | fprintf (file, "\t! this extra instruction should be " | |
1586 | "eliminated at link stage.\n"); | |
1587 | fprintf (file, "\t.omit_fp_begin\n"); | |
1588 | fprintf (file, "\tla\t$fp,_FP_BASE_\n"); | |
1589 | fprintf (file, "\t! ----------------------------------------\n"); | |
1590 | } | |
1591 | } | |
1592 | ||
1593 | /* Before rtl epilogue has been expanded, this function is used. */ | |
1594 | static void | |
1595 | nds32_asm_function_begin_epilogue (FILE *file) | |
1596 | { | |
1597 | /* If frame pointer is NOT needed and -mfp-as-gp is issued, | |
1598 | we can generate special directive: ".omit_fp_end" | |
1599 | to claim fp-as-gp optimization range. | |
1600 | However, for a naked function, | |
1601 | which means it should not have prologue/epilogue, | |
1602 | using fp-as-gp still requires saving $fp by push/pop behavior and | |
1603 | there is no benefit to use fp-as-gp on such small function. | |
1604 | So we need to make sure this function is NOT naked as well. */ | |
1605 | if (!frame_pointer_needed | |
1606 | && !cfun->machine->naked_p | |
1607 | && cfun->machine->fp_as_gp_p) | |
1608 | { | |
1609 | fprintf (file, "\t! ----------------------------------------\n"); | |
1610 | fprintf (file, "\t! Claim the range of fp-as-gp " | |
1611 | "link time optimization\n"); | |
1612 | fprintf (file, "\t.omit_fp_end\n"); | |
1613 | fprintf (file, "\t! ----------------------------------------\n"); | |
1614 | } | |
1615 | ||
1616 | fprintf (file, "\t! BEGIN EPILOGUE\n"); | |
1617 | } | |
1618 | ||
1619 | /* The content produced from this function | |
1620 | will be placed after epilogue body. */ | |
1621 | static void | |
42776416 | 1622 | nds32_asm_function_epilogue (FILE *file) |
9304f876 CJW |
1623 | { |
1624 | fprintf (file, "\t! END EPILOGUE\n"); | |
1625 | } | |
1626 | ||
1627 | static void | |
1628 | nds32_asm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, | |
1629 | HOST_WIDE_INT delta, | |
1630 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
1631 | tree function) | |
1632 | { | |
1633 | int this_regno; | |
1634 | ||
1635 | /* Make sure unwind info is emitted for the thunk if needed. */ | |
1636 | final_start_function (emit_barrier (), file, 1); | |
1637 | ||
1638 | this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) | |
1639 | ? 1 | |
1640 | : 0); | |
1641 | ||
1642 | if (delta != 0) | |
1643 | { | |
1644 | if (satisfies_constraint_Is15 (GEN_INT (delta))) | |
1645 | { | |
1646 | fprintf (file, "\taddi\t$r%d, $r%d, %ld\n", | |
1647 | this_regno, this_regno, delta); | |
1648 | } | |
1649 | else if (satisfies_constraint_Is20 (GEN_INT (delta))) | |
1650 | { | |
1651 | fprintf (file, "\tmovi\t$ta, %ld\n", delta); | |
1652 | fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); | |
1653 | } | |
1654 | else | |
1655 | { | |
1656 | fprintf (file, "\tsethi\t$ta, hi20(%ld)\n", delta); | |
1657 | fprintf (file, "\tori\t$ta, $ta, lo12(%ld)\n", delta); | |
1658 | fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); | |
1659 | } | |
1660 | } | |
1661 | ||
1662 | fprintf (file, "\tb\t"); | |
1663 | assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
1664 | fprintf (file, "\n"); | |
1665 | ||
1666 | final_end_function (); | |
1667 | } | |
1668 | ||
1669 | /* -- Permitting tail calls. */ | |
1670 | ||
1671 | /* Determine whether we need to enable warning for function return check. */ | |
1672 | static bool | |
1673 | nds32_warn_func_return (tree decl) | |
1674 | { | |
1675 | /* Naked functions are implemented entirely in assembly, including the | |
1676 | return sequence, so suppress warnings about this. */ | |
1677 | return !nds32_naked_function_p (decl); | |
1678 | } | |
1679 | ||
1680 | \f | |
1681 | /* Implementing the Varargs Macros. */ | |
1682 | ||
d4a6a4d9 CJW |
1683 | static void |
1684 | nds32_setup_incoming_varargs (cumulative_args_t ca, | |
ef4bddc2 | 1685 | machine_mode mode, |
d4a6a4d9 CJW |
1686 | tree type, |
1687 | int *pretend_args_size, | |
1688 | int second_time ATTRIBUTE_UNUSED) | |
1689 | { | |
1690 | unsigned int total_args_regs; | |
1691 | unsigned int num_of_used_regs; | |
1692 | unsigned int remaining_reg_count; | |
1693 | CUMULATIVE_ARGS *cum; | |
1694 | ||
1695 | /* If we are under hard float abi, we do not need to set *pretend_args_size. | |
1696 | So that all nameless arguments are pushed by caller and all situation | |
1697 | can be handled by GCC itself. */ | |
1698 | if (TARGET_HARD_FLOAT) | |
1699 | return; | |
1700 | ||
1701 | /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers, | |
1702 | counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments. | |
1703 | However, for nameless(anonymous) arguments, we should push them on the | |
1704 | stack so that all the nameless arguments appear to have been passed | |
1705 | consecutively in the memory for accessing. Hence, we need to check and | |
1706 | exclude the registers that are used for named arguments. */ | |
1707 | ||
1708 | cum = get_cumulative_args (ca); | |
1709 | ||
1710 | /* The MODE and TYPE describe the last argument. | |
1711 | We need those information to determine the remaining registers | |
1712 | for varargs. */ | |
1713 | total_args_regs | |
1714 | = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM; | |
1715 | num_of_used_regs | |
1716 | = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) | |
1717 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type); | |
1718 | ||
1719 | remaining_reg_count = total_args_regs - num_of_used_regs; | |
1720 | *pretend_args_size = remaining_reg_count * UNITS_PER_WORD; | |
1721 | ||
1722 | return; | |
1723 | } | |
1724 | ||
9304f876 CJW |
1725 | static bool |
1726 | nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) | |
1727 | { | |
d4a6a4d9 CJW |
1728 | /* If this hook returns true, the named argument of FUNCTION_ARG is always |
1729 | true for named arguments, and false for unnamed arguments. */ | |
9304f876 CJW |
1730 | return true; |
1731 | } | |
1732 | ||
1733 | \f | |
1734 | /* Trampolines for Nested Functions. */ | |
1735 | ||
1736 | static void | |
1737 | nds32_asm_trampoline_template (FILE *f) | |
1738 | { | |
1739 | if (TARGET_REDUCED_REGS) | |
1740 | { | |
1741 | /* Trampoline is not supported on reduced-set registers yet. */ | |
1742 | sorry ("a nested function is not supported for reduced registers"); | |
1743 | } | |
1744 | else | |
1745 | { | |
1746 | asm_fprintf (f, "\t! Trampoline code template\n"); | |
1747 | asm_fprintf (f, "\t! This code fragment will be copied " | |
1748 | "into stack on demand\n"); | |
1749 | ||
1750 | asm_fprintf (f, "\tmfusr\t$r16,$pc\n"); | |
1751 | asm_fprintf (f, "\tlwi\t$r15,[$r16 + 20] " | |
1752 | "! load nested function address\n"); | |
1753 | asm_fprintf (f, "\tlwi\t$r16,[$r16 + 16] " | |
1754 | "! load chain_value\n"); | |
1755 | asm_fprintf (f, "\tjr\t$r15\n"); | |
1756 | } | |
1757 | ||
1758 | /* Preserve space ($pc + 16) for saving chain_value, | |
1759 | nds32_trampoline_init will fill the value in this slot. */ | |
1760 | asm_fprintf (f, "\t! space for saving chain_value\n"); | |
1761 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
1762 | ||
1763 | /* Preserve space ($pc + 20) for saving nested function address, | |
1764 | nds32_trampoline_init will fill the value in this slot. */ | |
1765 | asm_fprintf (f, "\t! space for saving nested function address\n"); | |
1766 | assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); | |
1767 | } | |
1768 | ||
1769 | /* Emit RTL insns to initialize the variable parts of a trampoline. */ | |
1770 | static void | |
1771 | nds32_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
1772 | { | |
1773 | int i; | |
1774 | ||
1775 | /* Nested function address. */ | |
1776 | rtx fnaddr; | |
1777 | /* The memory rtx that is going to | |
1778 | be filled with chain_value. */ | |
1779 | rtx chain_value_mem; | |
1780 | /* The memory rtx that is going to | |
1781 | be filled with nested function address. */ | |
1782 | rtx nested_func_mem; | |
1783 | ||
1784 | /* Start address of trampoline code in stack, for doing cache sync. */ | |
1785 | rtx sync_cache_addr; | |
1786 | /* Temporary register for sync instruction. */ | |
1787 | rtx tmp_reg; | |
1788 | /* Instruction-cache sync instruction, | |
1789 | requesting an argument as starting address. */ | |
1790 | rtx isync_insn; | |
1791 | /* For convenience reason of doing comparison. */ | |
1792 | int tramp_align_in_bytes; | |
1793 | ||
1794 | /* Trampoline is not supported on reduced-set registers yet. */ | |
1795 | if (TARGET_REDUCED_REGS) | |
1796 | sorry ("a nested function is not supported for reduced registers"); | |
1797 | ||
1798 | /* STEP 1: Copy trampoline code template into stack, | |
1799 | fill up essential data into stack. */ | |
1800 | ||
1801 | /* Extract nested function address rtx. */ | |
1802 | fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
1803 | ||
1804 | /* m_tramp is memory rtx that is going to be filled with trampoline code. | |
1805 | We have nds32_asm_trampoline_template() to emit template pattern. */ | |
1806 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
1807 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
1808 | ||
1809 | /* After copying trampoline code into stack, | |
1810 | fill chain_value into stack. */ | |
1811 | chain_value_mem = adjust_address (m_tramp, SImode, 16); | |
1812 | emit_move_insn (chain_value_mem, chain_value); | |
1813 | /* After copying trampoline code int stack, | |
1814 | fill nested function address into stack. */ | |
1815 | nested_func_mem = adjust_address (m_tramp, SImode, 20); | |
1816 | emit_move_insn (nested_func_mem, fnaddr); | |
1817 | ||
1818 | /* STEP 2: Sync instruction-cache. */ | |
1819 | ||
1820 | /* We have successfully filled trampoline code into stack. | |
1821 | However, in order to execute code in stack correctly, | |
1822 | we must sync instruction cache. */ | |
1823 | sync_cache_addr = XEXP (m_tramp, 0); | |
1824 | tmp_reg = gen_reg_rtx (SImode); | |
1825 | isync_insn = gen_unspec_volatile_isync (tmp_reg); | |
1826 | ||
1827 | /* Because nds32_cache_block_size is in bytes, | |
1828 | we get trampoline alignment in bytes for convenient comparison. */ | |
1829 | tramp_align_in_bytes = TRAMPOLINE_ALIGNMENT / BITS_PER_UNIT; | |
1830 | ||
1831 | if (tramp_align_in_bytes >= nds32_cache_block_size | |
1832 | && (tramp_align_in_bytes % nds32_cache_block_size) == 0) | |
1833 | { | |
1834 | /* Under this condition, the starting address of trampoline | |
1835 | must be aligned to the starting address of each cache block | |
1836 | and we do not have to worry about cross-boundary issue. */ | |
1837 | for (i = 0; | |
1838 | i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) | |
1839 | / nds32_cache_block_size; | |
1840 | i++) | |
1841 | { | |
1842 | emit_move_insn (tmp_reg, | |
1843 | plus_constant (Pmode, sync_cache_addr, | |
1844 | nds32_cache_block_size * i)); | |
1845 | emit_insn (isync_insn); | |
1846 | } | |
1847 | } | |
1848 | else if (TRAMPOLINE_SIZE > nds32_cache_block_size) | |
1849 | { | |
1850 | /* The starting address of trampoline code | |
1851 | may not be aligned to the cache block, | |
1852 | so the trampoline code may be across two cache block. | |
1853 | We need to sync the last element, which is 4-byte size, | |
1854 | of trampoline template. */ | |
1855 | for (i = 0; | |
1856 | i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) | |
1857 | / nds32_cache_block_size; | |
1858 | i++) | |
1859 | { | |
1860 | emit_move_insn (tmp_reg, | |
1861 | plus_constant (Pmode, sync_cache_addr, | |
1862 | nds32_cache_block_size * i)); | |
1863 | emit_insn (isync_insn); | |
1864 | } | |
1865 | ||
1866 | /* The last element of trampoline template is 4-byte size. */ | |
1867 | emit_move_insn (tmp_reg, | |
1868 | plus_constant (Pmode, sync_cache_addr, | |
1869 | TRAMPOLINE_SIZE - 4)); | |
1870 | emit_insn (isync_insn); | |
1871 | } | |
1872 | else | |
1873 | { | |
1874 | /* This is the simplest case. | |
1875 | Because TRAMPOLINE_SIZE is less than or | |
1876 | equal to nds32_cache_block_size, | |
1877 | we can just sync start address and | |
1878 | the last element of trampoline code. */ | |
1879 | ||
1880 | /* Sync starting address of tampoline code. */ | |
1881 | emit_move_insn (tmp_reg, sync_cache_addr); | |
1882 | emit_insn (isync_insn); | |
1883 | /* Sync the last element, which is 4-byte size, | |
1884 | of trampoline template. */ | |
1885 | emit_move_insn (tmp_reg, | |
1886 | plus_constant (Pmode, sync_cache_addr, | |
1887 | TRAMPOLINE_SIZE - 4)); | |
1888 | emit_insn (isync_insn); | |
1889 | } | |
1890 | ||
1891 | /* Set instruction serialization barrier | |
1892 | to guarantee the correct operations. */ | |
1893 | emit_insn (gen_unspec_volatile_isb ()); | |
1894 | } | |
1895 | ||
1896 | \f | |
1897 | /* Addressing Modes. */ | |
1898 | ||
1899 | static bool | |
ef4bddc2 | 1900 | nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict) |
9304f876 CJW |
1901 | { |
1902 | /* For (mem:DI addr) or (mem:DF addr) case, | |
1903 | we only allow 'addr' to be [reg], [symbol_ref], | |
1904 | [const], or [reg + const_int] pattern. */ | |
1905 | if (mode == DImode || mode == DFmode) | |
1906 | { | |
1907 | /* Allow [Reg + const_int] addressing mode. */ | |
1908 | if (GET_CODE (x) == PLUS) | |
1909 | { | |
1910 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict) | |
1911 | && nds32_legitimate_index_p (mode, XEXP (x, 1), strict) | |
1912 | && CONST_INT_P (XEXP (x, 1))) | |
1913 | return true; | |
1914 | ||
1915 | else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) | |
1916 | && nds32_legitimate_index_p (mode, XEXP (x, 0), strict) | |
1917 | && CONST_INT_P (XEXP (x, 0))) | |
1918 | return true; | |
1919 | } | |
1920 | ||
1921 | /* Now check [reg], [symbol_ref], and [const]. */ | |
1922 | if (GET_CODE (x) != REG | |
1923 | && GET_CODE (x) != SYMBOL_REF | |
1924 | && GET_CODE (x) != CONST) | |
1925 | return false; | |
1926 | } | |
1927 | ||
1928 | /* Check if 'x' is a valid address. */ | |
1929 | switch (GET_CODE (x)) | |
1930 | { | |
1931 | case REG: | |
1932 | /* (mem (reg A)) => [Ra] */ | |
1933 | return nds32_address_register_rtx_p (x, strict); | |
1934 | ||
1935 | case SYMBOL_REF: | |
4855be84 CJW |
1936 | /* (mem (symbol_ref A)) => [symbol_ref] */ |
1937 | /* If -mcmodel=large, the 'symbol_ref' is not a valid address | |
1938 | during or after LRA/reload phase. */ | |
1939 | if (TARGET_CMODEL_LARGE | |
9304f876 CJW |
1940 | && (reload_completed |
1941 | || reload_in_progress | |
1942 | || lra_in_progress)) | |
1943 | return false; | |
4855be84 CJW |
1944 | /* If -mcmodel=medium and the symbol references to rodata section, |
1945 | the 'symbol_ref' is not a valid address during or after | |
1946 | LRA/reload phase. */ | |
1947 | if (TARGET_CMODEL_MEDIUM | |
1948 | && NDS32_SYMBOL_REF_RODATA_P (x) | |
9304f876 CJW |
1949 | && (reload_completed |
1950 | || reload_in_progress | |
1951 | || lra_in_progress)) | |
1952 | return false; | |
1953 | ||
4855be84 CJW |
1954 | return true; |
1955 | ||
1956 | case CONST: | |
9304f876 CJW |
1957 | /* (mem (const (...))) |
1958 | => [ + const_addr ], where const_addr = symbol_ref + const_int */ | |
1959 | if (GET_CODE (XEXP (x, 0)) == PLUS) | |
1960 | { | |
1961 | rtx plus_op = XEXP (x, 0); | |
1962 | ||
1963 | rtx op0 = XEXP (plus_op, 0); | |
1964 | rtx op1 = XEXP (plus_op, 1); | |
1965 | ||
1966 | if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) | |
4855be84 CJW |
1967 | { |
1968 | /* Now we see the [ + const_addr ] pattern, but we need | |
1969 | some further checking. */ | |
1970 | /* If -mcmodel=large, the 'const_addr' is not a valid address | |
1971 | during or after LRA/reload phase. */ | |
1972 | if (TARGET_CMODEL_LARGE | |
1973 | && (reload_completed | |
1974 | || reload_in_progress | |
1975 | || lra_in_progress)) | |
1976 | return false; | |
1977 | /* If -mcmodel=medium and the symbol references to rodata section, | |
1978 | the 'const_addr' is not a valid address during or after | |
1979 | LRA/reload phase. */ | |
1980 | if (TARGET_CMODEL_MEDIUM | |
1981 | && NDS32_SYMBOL_REF_RODATA_P (op0) | |
1982 | && (reload_completed | |
1983 | || reload_in_progress | |
1984 | || lra_in_progress)) | |
1985 | return false; | |
1986 | ||
1987 | /* At this point we can make sure 'const_addr' is a | |
1988 | valid address. */ | |
1989 | return true; | |
1990 | } | |
9304f876 CJW |
1991 | } |
1992 | ||
1993 | return false; | |
1994 | ||
1995 | case POST_MODIFY: | |
1996 | /* (mem (post_modify (reg) (plus (reg) (reg)))) | |
1997 | => [Ra], Rb */ | |
1998 | /* (mem (post_modify (reg) (plus (reg) (const_int)))) | |
1999 | => [Ra], const_int */ | |
2000 | if (GET_CODE (XEXP (x, 0)) == REG | |
2001 | && GET_CODE (XEXP (x, 1)) == PLUS) | |
2002 | { | |
2003 | rtx plus_op = XEXP (x, 1); | |
2004 | ||
2005 | rtx op0 = XEXP (plus_op, 0); | |
2006 | rtx op1 = XEXP (plus_op, 1); | |
2007 | ||
2008 | if (nds32_address_register_rtx_p (op0, strict) | |
2009 | && nds32_legitimate_index_p (mode, op1, strict)) | |
2010 | return true; | |
2011 | else | |
2012 | return false; | |
2013 | } | |
2014 | ||
2015 | return false; | |
2016 | ||
2017 | case POST_INC: | |
2018 | case POST_DEC: | |
2019 | /* (mem (post_inc reg)) => [Ra], 1/2/4 */ | |
2020 | /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */ | |
2021 | /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. | |
2022 | We only need to deal with register Ra. */ | |
2023 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) | |
2024 | return true; | |
2025 | else | |
2026 | return false; | |
2027 | ||
2028 | case PLUS: | |
2029 | /* (mem (plus reg const_int)) | |
2030 | => [Ra + imm] */ | |
2031 | /* (mem (plus reg reg)) | |
2032 | => [Ra + Rb] */ | |
2033 | /* (mem (plus (mult reg const_int) reg)) | |
2034 | => [Ra + Rb << sv] */ | |
2035 | if (nds32_address_register_rtx_p (XEXP (x, 0), strict) | |
2036 | && nds32_legitimate_index_p (mode, XEXP (x, 1), strict)) | |
2037 | return true; | |
2038 | else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) | |
2039 | && nds32_legitimate_index_p (mode, XEXP (x, 0), strict)) | |
2040 | return true; | |
2041 | else | |
2042 | return false; | |
2043 | ||
2044 | case LO_SUM: | |
34425025 CJW |
2045 | /* (mem (lo_sum (reg) (symbol_ref))) */ |
2046 | /* (mem (lo_sum (reg) (const))) */ | |
2047 | gcc_assert (REG_P (XEXP (x, 0))); | |
2048 | if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF | |
2049 | || GET_CODE (XEXP (x, 1)) == CONST) | |
2050 | return nds32_legitimate_address_p (mode, XEXP (x, 1), strict); | |
2051 | else | |
2052 | return false; | |
9304f876 CJW |
2053 | |
2054 | default: | |
2055 | return false; | |
2056 | } | |
2057 | } | |
2058 | ||
2059 | \f | |
2060 | /* Describing Relative Costs of Operations. */ | |
2061 | ||
19ac960a | 2062 | static int |
ef4bddc2 | 2063 | nds32_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
19ac960a CJW |
2064 | reg_class_t from, |
2065 | reg_class_t to) | |
9304f876 CJW |
2066 | { |
2067 | if (from == HIGH_REGS || to == HIGH_REGS) | |
2068 | return 6; | |
2069 | ||
2070 | return 2; | |
2071 | } | |
2072 | ||
19ac960a | 2073 | static int |
ef4bddc2 | 2074 | nds32_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
19ac960a CJW |
2075 | reg_class_t rclass ATTRIBUTE_UNUSED, |
2076 | bool in ATTRIBUTE_UNUSED) | |
9304f876 CJW |
2077 | { |
2078 | return 8; | |
2079 | } | |
2080 | ||
2081 | /* This target hook describes the relative costs of RTL expressions. | |
2082 | Return 'true' when all subexpressions of x have been processed. | |
2083 | Return 'false' to sum the costs of sub-rtx, plus cost of this operation. | |
2084 | Refer to gcc/rtlanal.c for more information. */ | |
2085 | static bool | |
2086 | nds32_rtx_costs (rtx x, | |
e548c9df | 2087 | machine_mode mode, |
9304f876 | 2088 | int outer_code, |
89a4b547 | 2089 | int opno, |
9304f876 CJW |
2090 | int *total, |
2091 | bool speed) | |
2092 | { | |
e548c9df | 2093 | return nds32_rtx_costs_impl (x, mode, outer_code, opno, total, speed); |
9304f876 CJW |
2094 | } |
2095 | ||
19ac960a CJW |
2096 | static int |
2097 | nds32_address_cost (rtx address, | |
ef4bddc2 | 2098 | machine_mode mode, |
19ac960a CJW |
2099 | addr_space_t as, |
2100 | bool speed) | |
9304f876 | 2101 | { |
89a4b547 | 2102 | return nds32_address_cost_impl (address, mode, as, speed); |
9304f876 CJW |
2103 | } |
2104 | ||
511a41d7 CJW |
2105 | \f |
2106 | /* Dividing the Output into Sections (Texts, Data, . . . ). */ | |
2107 | ||
2108 | /* If references to a symbol or a constant must be treated differently | |
2109 | depending on something about the variable or function named by the symbol | |
2110 | (such as what section it is in), we use this hook to store flags | |
2111 | in symbol_ref rtx. */ | |
2112 | static void | |
2113 | nds32_encode_section_info (tree decl, rtx rtl, int new_decl_p) | |
2114 | { | |
2115 | default_encode_section_info (decl, rtl, new_decl_p); | |
2116 | ||
2117 | /* For the memory rtx, if it references to rodata section, we can store | |
2118 | NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the | |
2119 | nds32_legitimate_address_p() can determine how to treat such symbol_ref | |
2120 | based on -mcmodel=X and this information. */ | |
2121 | if (MEM_P (rtl) && MEM_READONLY_P (rtl)) | |
2122 | { | |
2123 | rtx addr = XEXP (rtl, 0); | |
2124 | ||
2125 | if (GET_CODE (addr) == SYMBOL_REF) | |
2126 | { | |
2127 | /* For (mem (symbol_ref X)) case. */ | |
2128 | SYMBOL_REF_FLAGS (addr) |= NDS32_SYMBOL_FLAG_RODATA; | |
2129 | } | |
2130 | else if (GET_CODE (addr) == CONST | |
2131 | && GET_CODE (XEXP (addr, 0)) == PLUS) | |
2132 | { | |
2133 | /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */ | |
2134 | rtx plus_op = XEXP (addr, 0); | |
2135 | rtx op0 = XEXP (plus_op, 0); | |
2136 | rtx op1 = XEXP (plus_op, 1); | |
2137 | ||
2138 | if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) | |
2139 | SYMBOL_REF_FLAGS (op0) |= NDS32_SYMBOL_FLAG_RODATA; | |
2140 | } | |
2141 | } | |
2142 | } | |
2143 | ||
9304f876 CJW |
2144 | \f |
2145 | /* Defining the Output Assembler Language. */ | |
2146 | ||
2147 | /* -- The Overall Framework of an Assembler File. */ | |
2148 | ||
2149 | static void | |
2150 | nds32_asm_file_start (void) | |
2151 | { | |
9304f876 CJW |
2152 | default_file_start (); |
2153 | ||
2154 | /* Tell assembler which ABI we are using. */ | |
2155 | fprintf (asm_out_file, "\t! ABI version\n"); | |
2156 | fprintf (asm_out_file, "\t.abi_2\n"); | |
2157 | ||
2158 | /* Tell assembler that this asm code is generated by compiler. */ | |
2159 | fprintf (asm_out_file, "\t! This asm file is generated by compiler\n"); | |
2160 | fprintf (asm_out_file, "\t.flag\tverbatim\n"); | |
2161 | /* Give assembler the size of each vector for interrupt handler. */ | |
2162 | fprintf (asm_out_file, "\t! This vector size directive is required " | |
2163 | "for checking inconsistency on interrupt handler\n"); | |
2164 | fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size); | |
2165 | ||
9304f876 CJW |
2166 | fprintf (asm_out_file, "\t! ------------------------------------\n"); |
2167 | ||
2168 | if (TARGET_ISA_V2) | |
2169 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V2"); | |
2170 | if (TARGET_ISA_V3) | |
2171 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3"); | |
2172 | if (TARGET_ISA_V3M) | |
2173 | fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M"); | |
2174 | ||
77b7a1ca CJW |
2175 | if (TARGET_CMODEL_SMALL) |
2176 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "SMALL"); | |
2177 | if (TARGET_CMODEL_MEDIUM) | |
2178 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "MEDIUM"); | |
2179 | if (TARGET_CMODEL_LARGE) | |
2180 | fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "LARGE"); | |
2181 | ||
9304f876 CJW |
2182 | fprintf (asm_out_file, "\t! Endian setting\t: %s\n", |
2183 | ((TARGET_BIG_ENDIAN) ? "big-endian" | |
2184 | : "little-endian")); | |
2185 | ||
2186 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2187 | ||
2188 | fprintf (asm_out_file, "\t! Use conditional move\t\t: %s\n", | |
2189 | ((TARGET_CMOV) ? "Yes" | |
2190 | : "No")); | |
2191 | fprintf (asm_out_file, "\t! Use performance extension\t: %s\n", | |
2192 | ((TARGET_PERF_EXT) ? "Yes" | |
2193 | : "No")); | |
2194 | ||
2195 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2196 | ||
2197 | fprintf (asm_out_file, "\t! V3PUSH instructions\t: %s\n", | |
2198 | ((TARGET_V3PUSH) ? "Yes" | |
2199 | : "No")); | |
2200 | fprintf (asm_out_file, "\t! 16-bit instructions\t: %s\n", | |
2201 | ((TARGET_16_BIT) ? "Yes" | |
2202 | : "No")); | |
9304f876 CJW |
2203 | fprintf (asm_out_file, "\t! Reduced registers set\t: %s\n", |
2204 | ((TARGET_REDUCED_REGS) ? "Yes" | |
2205 | : "No")); | |
2206 | ||
2207 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2208 | ||
2209 | if (optimize_size) | |
2210 | fprintf (asm_out_file, "\t! Optimization level\t: -Os\n"); | |
2211 | else | |
2212 | fprintf (asm_out_file, "\t! Optimization level\t: -O%d\n", optimize); | |
2213 | ||
2214 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2215 | ||
2216 | fprintf (asm_out_file, "\t! Cache block size\t: %d\n", | |
2217 | nds32_cache_block_size); | |
2218 | ||
2219 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2220 | ||
c23a919b | 2221 | nds32_asm_file_start_for_isr (); |
9304f876 CJW |
2222 | } |
2223 | ||
2224 | static void | |
2225 | nds32_asm_file_end (void) | |
2226 | { | |
c23a919b | 2227 | nds32_asm_file_end_for_isr (); |
9304f876 CJW |
2228 | |
2229 | fprintf (asm_out_file, "\t! ------------------------------------\n"); | |
2230 | } | |
2231 | ||
2232 | /* -- Output and Generation of Labels. */ | |
2233 | ||
2234 | static void | |
2235 | nds32_asm_globalize_label (FILE *stream, const char *name) | |
2236 | { | |
2237 | fputs ("\t.global\t", stream); | |
2238 | assemble_name (stream, name); | |
2239 | fputs ("\n", stream); | |
2240 | } | |
2241 | ||
2242 | /* -- Output of Assembler Instructions. */ | |
2243 | ||
2244 | static void | |
2245 | nds32_print_operand (FILE *stream, rtx x, int code) | |
2246 | { | |
2247 | int op_value; | |
2248 | ||
2249 | switch (code) | |
2250 | { | |
2251 | case 0 : | |
2252 | /* Do nothing special. */ | |
2253 | break; | |
2254 | ||
2255 | case 'V': | |
2256 | /* 'x' is supposed to be CONST_INT, get the value. */ | |
2257 | gcc_assert (CONST_INT_P (x)); | |
2258 | op_value = INTVAL (x); | |
2259 | ||
2260 | /* According to the Andes architecture, | |
2261 | the system/user register index range is 0 ~ 1023. | |
2262 | In order to avoid conflict between user-specified-integer value | |
2263 | and enum-specified-register value, | |
2264 | the 'enum nds32_intrinsic_registers' value | |
2265 | in nds32_intrinsic.h starts from 1024. */ | |
2266 | if (op_value < 1024 && op_value >= 0) | |
2267 | { | |
2268 | /* If user gives integer value directly (0~1023), | |
2269 | we just print out the value. */ | |
2270 | fprintf (stream, "%d", op_value); | |
2271 | } | |
2272 | else if (op_value < 0 | |
2273 | || op_value >= ((int) ARRAY_SIZE (nds32_intrinsic_register_names) | |
2274 | + 1024)) | |
2275 | { | |
2276 | /* The enum index value for array size is out of range. */ | |
2277 | error ("intrinsic register index is out of range"); | |
2278 | } | |
2279 | else | |
2280 | { | |
2281 | /* If user applies normal way with __NDS32_REG_XXX__ enum data, | |
2282 | we can print out register name. Remember to substract 1024. */ | |
2283 | fprintf (stream, "%s", | |
2284 | nds32_intrinsic_register_names[op_value - 1024]); | |
2285 | } | |
2286 | ||
2287 | /* No need to handle following process, so return immediately. */ | |
2288 | return; | |
2289 | ||
2290 | default : | |
2291 | /* Unknown flag. */ | |
2292 | output_operand_lossage ("invalid operand output code"); | |
2293 | break; | |
2294 | } | |
2295 | ||
2296 | switch (GET_CODE (x)) | |
2297 | { | |
2298 | case LABEL_REF: | |
2299 | case SYMBOL_REF: | |
2300 | output_addr_const (stream, x); | |
2301 | break; | |
2302 | ||
2303 | case REG: | |
2304 | /* Forbid using static chain register ($r16) | |
2305 | on reduced-set registers configuration. */ | |
2306 | if (TARGET_REDUCED_REGS | |
2307 | && REGNO (x) == STATIC_CHAIN_REGNUM) | |
2308 | sorry ("a nested function is not supported for reduced registers"); | |
2309 | ||
2310 | /* Normal cases, print out register name. */ | |
2311 | fputs (reg_names[REGNO (x)], stream); | |
2312 | break; | |
2313 | ||
2314 | case MEM: | |
cc8ca59e | 2315 | output_address (GET_MODE (x), XEXP (x, 0)); |
9304f876 CJW |
2316 | break; |
2317 | ||
2318 | case CODE_LABEL: | |
2319 | case CONST_INT: | |
2320 | case CONST: | |
2321 | output_addr_const (stream, x); | |
2322 | break; | |
2323 | ||
2324 | default: | |
2325 | /* Generally, output_addr_const () is able to handle most cases. | |
2326 | We want to see what CODE could appear, | |
2327 | so we use gcc_unreachable() to stop it. */ | |
2328 | debug_rtx (x); | |
2329 | gcc_unreachable (); | |
2330 | break; | |
2331 | } | |
2332 | } | |
2333 | ||
2334 | static void | |
cc8ca59e | 2335 | nds32_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x) |
9304f876 CJW |
2336 | { |
2337 | rtx op0, op1; | |
2338 | ||
2339 | switch (GET_CODE (x)) | |
2340 | { | |
2341 | case SYMBOL_REF: | |
2342 | case CONST: | |
2343 | /* [ + symbol_ref] */ | |
2344 | /* [ + const_addr], where const_addr = symbol_ref + const_int */ | |
2345 | fputs ("[ + ", stream); | |
2346 | output_addr_const (stream, x); | |
2347 | fputs ("]", stream); | |
2348 | break; | |
2349 | ||
2350 | case REG: | |
2351 | /* Forbid using static chain register ($r16) | |
2352 | on reduced-set registers configuration. */ | |
2353 | if (TARGET_REDUCED_REGS | |
2354 | && REGNO (x) == STATIC_CHAIN_REGNUM) | |
2355 | sorry ("a nested function is not supported for reduced registers"); | |
2356 | ||
2357 | /* [Ra] */ | |
2358 | fprintf (stream, "[%s]", reg_names[REGNO (x)]); | |
2359 | break; | |
2360 | ||
2361 | case PLUS: | |
2362 | op0 = XEXP (x, 0); | |
2363 | op1 = XEXP (x, 1); | |
2364 | ||
2365 | /* Checking op0, forbid using static chain register ($r16) | |
2366 | on reduced-set registers configuration. */ | |
2367 | if (TARGET_REDUCED_REGS | |
2368 | && REG_P (op0) | |
2369 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
2370 | sorry ("a nested function is not supported for reduced registers"); | |
2371 | /* Checking op1, forbid using static chain register ($r16) | |
2372 | on reduced-set registers configuration. */ | |
2373 | if (TARGET_REDUCED_REGS | |
2374 | && REG_P (op1) | |
2375 | && REGNO (op1) == STATIC_CHAIN_REGNUM) | |
2376 | sorry ("a nested function is not supported for reduced registers"); | |
2377 | ||
2378 | if (REG_P (op0) && CONST_INT_P (op1)) | |
2379 | { | |
2380 | /* [Ra + imm] */ | |
2381 | fprintf (stream, "[%s + (%d)]", | |
2382 | reg_names[REGNO (op0)], (int)INTVAL (op1)); | |
2383 | } | |
2384 | else if (REG_P (op0) && REG_P (op1)) | |
2385 | { | |
2386 | /* [Ra + Rb] */ | |
2387 | fprintf (stream, "[%s + %s]", | |
2388 | reg_names[REGNO (op0)], reg_names[REGNO (op1)]); | |
2389 | } | |
2390 | else if (GET_CODE (op0) == MULT && REG_P (op1)) | |
2391 | { | |
2392 | /* [Ra + Rb << sv] | |
2393 | From observation, the pattern looks like: | |
2394 | (plus:SI (mult:SI (reg:SI 58) | |
2395 | (const_int 4 [0x4])) | |
2396 | (reg/f:SI 57)) */ | |
2397 | int sv; | |
2398 | ||
2399 | /* We need to set sv to output shift value. */ | |
2400 | if (INTVAL (XEXP (op0, 1)) == 1) | |
2401 | sv = 0; | |
2402 | else if (INTVAL (XEXP (op0, 1)) == 2) | |
2403 | sv = 1; | |
2404 | else if (INTVAL (XEXP (op0, 1)) == 4) | |
2405 | sv = 2; | |
2406 | else | |
2407 | gcc_unreachable (); | |
2408 | ||
2409 | fprintf (stream, "[%s + %s << %d]", | |
2410 | reg_names[REGNO (op1)], | |
2411 | reg_names[REGNO (XEXP (op0, 0))], | |
2412 | sv); | |
2413 | } | |
2414 | else | |
2415 | { | |
2416 | /* The control flow is not supposed to be here. */ | |
2417 | debug_rtx (x); | |
2418 | gcc_unreachable (); | |
2419 | } | |
2420 | ||
2421 | break; | |
2422 | ||
2423 | case POST_MODIFY: | |
2424 | /* (post_modify (regA) (plus (regA) (regB))) | |
2425 | (post_modify (regA) (plus (regA) (const_int))) | |
2426 | We would like to extract | |
2427 | regA and regB (or const_int) from plus rtx. */ | |
2428 | op0 = XEXP (XEXP (x, 1), 0); | |
2429 | op1 = XEXP (XEXP (x, 1), 1); | |
2430 | ||
2431 | /* Checking op0, forbid using static chain register ($r16) | |
2432 | on reduced-set registers configuration. */ | |
2433 | if (TARGET_REDUCED_REGS | |
2434 | && REG_P (op0) | |
2435 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
2436 | sorry ("a nested function is not supported for reduced registers"); | |
2437 | /* Checking op1, forbid using static chain register ($r16) | |
2438 | on reduced-set registers configuration. */ | |
2439 | if (TARGET_REDUCED_REGS | |
2440 | && REG_P (op1) | |
2441 | && REGNO (op1) == STATIC_CHAIN_REGNUM) | |
2442 | sorry ("a nested function is not supported for reduced registers"); | |
2443 | ||
2444 | if (REG_P (op0) && REG_P (op1)) | |
2445 | { | |
2446 | /* [Ra], Rb */ | |
2447 | fprintf (stream, "[%s], %s", | |
2448 | reg_names[REGNO (op0)], reg_names[REGNO (op1)]); | |
2449 | } | |
2450 | else if (REG_P (op0) && CONST_INT_P (op1)) | |
2451 | { | |
2452 | /* [Ra], imm */ | |
2453 | fprintf (stream, "[%s], %d", | |
2454 | reg_names[REGNO (op0)], (int)INTVAL (op1)); | |
2455 | } | |
2456 | else | |
2457 | { | |
2458 | /* The control flow is not supposed to be here. */ | |
2459 | debug_rtx (x); | |
2460 | gcc_unreachable (); | |
2461 | } | |
2462 | ||
2463 | break; | |
2464 | ||
2465 | case POST_INC: | |
2466 | case POST_DEC: | |
2467 | op0 = XEXP (x, 0); | |
2468 | ||
2469 | /* Checking op0, forbid using static chain register ($r16) | |
2470 | on reduced-set registers configuration. */ | |
2471 | if (TARGET_REDUCED_REGS | |
2472 | && REG_P (op0) | |
2473 | && REGNO (op0) == STATIC_CHAIN_REGNUM) | |
2474 | sorry ("a nested function is not supported for reduced registers"); | |
2475 | ||
2476 | if (REG_P (op0)) | |
2477 | { | |
2478 | /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4" | |
2479 | The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. | |
2480 | We only need to deal with register Ra. */ | |
2481 | fprintf (stream, "[%s]", reg_names[REGNO (op0)]); | |
2482 | } | |
2483 | else | |
2484 | { | |
2485 | /* The control flow is not supposed to be here. */ | |
2486 | debug_rtx (x); | |
2487 | gcc_unreachable (); | |
2488 | } | |
2489 | ||
2490 | break; | |
2491 | ||
2492 | default : | |
2493 | /* Generally, output_addr_const () is able to handle most cases. | |
2494 | We want to see what CODE could appear, | |
2495 | so we use gcc_unreachable() to stop it. */ | |
2496 | debug_rtx (x); | |
2497 | gcc_unreachable (); | |
2498 | break; | |
2499 | } | |
2500 | } | |
2501 | ||
2502 | \f | |
2503 | /* Defining target-specific uses of __attribute__. */ | |
2504 | ||
2505 | /* Add some checking after merging attributes. */ | |
2506 | static tree | |
2507 | nds32_merge_decl_attributes (tree olddecl, tree newdecl) | |
2508 | { | |
2509 | tree combined_attrs; | |
2510 | ||
2511 | /* Create combined attributes. */ | |
2512 | combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl), | |
2513 | DECL_ATTRIBUTES (newdecl)); | |
2514 | ||
59043e75 | 2515 | /* Since newdecl is acutally a duplicate of olddecl, |
9304f876 CJW |
2516 | we can take olddecl for some operations. */ |
2517 | if (TREE_CODE (olddecl) == FUNCTION_DECL) | |
2518 | { | |
2519 | /* Check isr-specific attributes conflict. */ | |
2520 | nds32_check_isr_attrs_conflict (olddecl, combined_attrs); | |
2521 | } | |
2522 | ||
2523 | return combined_attrs; | |
2524 | } | |
2525 | ||
2526 | /* Add some checking when inserting attributes. */ | |
2527 | static void | |
2528 | nds32_insert_attributes (tree decl, tree *attributes) | |
2529 | { | |
2530 | /* For function declaration, we need to check isr-specific attributes: | |
2531 | 1. Call nds32_check_isr_attrs_conflict() to check any conflict. | |
2532 | 2. Check valid integer value for interrupt/exception. | |
2533 | 3. Check valid integer value for reset. | |
2534 | 4. Check valid function for nmi/warm. */ | |
2535 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2536 | { | |
2537 | tree func_attrs; | |
2538 | tree intr, excp, reset; | |
2539 | ||
2540 | /* Pick up function attributes. */ | |
2541 | func_attrs = *attributes; | |
2542 | ||
2543 | /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */ | |
2544 | nds32_check_isr_attrs_conflict (decl, func_attrs); | |
2545 | ||
2546 | /* Now we are starting to check valid id value | |
2547 | for interrupt/exception/reset. | |
2548 | Note that we ONLY check its validity here. | |
2549 | To construct isr vector information, it is still performed | |
2550 | by nds32_construct_isr_vectors_information(). */ | |
2551 | intr = lookup_attribute ("interrupt", func_attrs); | |
2552 | excp = lookup_attribute ("exception", func_attrs); | |
2553 | reset = lookup_attribute ("reset", func_attrs); | |
2554 | ||
2555 | if (intr || excp) | |
2556 | { | |
2557 | /* Deal with interrupt/exception. */ | |
2558 | tree id_list; | |
2559 | unsigned int lower_bound, upper_bound; | |
2560 | ||
2561 | /* The way to handle interrupt or exception is the same, | |
2562 | we just need to take care of actual vector number. | |
2563 | For interrupt(0..63), the actual vector number is (9..72). | |
2564 | For exception(1..8), the actual vector number is (1..8). */ | |
2565 | lower_bound = (intr) ? (0) : (1); | |
2566 | upper_bound = (intr) ? (63) : (8); | |
2567 | ||
2568 | /* Prepare id list so that we can traverse id value. */ | |
2569 | id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp)); | |
2570 | ||
2571 | /* 2. Check valid integer value for interrupt/exception. */ | |
2572 | while (id_list) | |
2573 | { | |
2574 | tree id; | |
2575 | ||
2576 | /* Pick up each vector id value. */ | |
2577 | id = TREE_VALUE (id_list); | |
2578 | /* Issue error if it is not a valid integer value. */ | |
2579 | if (TREE_CODE (id) != INTEGER_CST | |
807e902e KZ |
2580 | || wi::ltu_p (id, lower_bound) |
2581 | || wi::gtu_p (id, upper_bound)) | |
9304f876 CJW |
2582 | error ("invalid id value for interrupt/exception attribute"); |
2583 | ||
2584 | /* Advance to next id. */ | |
2585 | id_list = TREE_CHAIN (id_list); | |
2586 | } | |
2587 | } | |
2588 | else if (reset) | |
2589 | { | |
2590 | /* Deal with reset. */ | |
2591 | tree id_list; | |
2592 | tree id; | |
2593 | tree nmi, warm; | |
2594 | unsigned int lower_bound; | |
2595 | unsigned int upper_bound; | |
2596 | ||
2597 | /* Prepare id_list and identify id value so that | |
2598 | we can check if total number of vectors is valid. */ | |
2599 | id_list = TREE_VALUE (reset); | |
2600 | id = TREE_VALUE (id_list); | |
2601 | ||
2602 | /* The maximum numbers for user's interrupt is 64. */ | |
2603 | lower_bound = 0; | |
2604 | upper_bound = 64; | |
2605 | ||
2606 | /* 3. Check valid integer value for reset. */ | |
2607 | if (TREE_CODE (id) != INTEGER_CST | |
807e902e KZ |
2608 | || wi::ltu_p (id, lower_bound) |
2609 | || wi::gtu_p (id, upper_bound)) | |
9304f876 CJW |
2610 | error ("invalid id value for reset attribute"); |
2611 | ||
2612 | /* 4. Check valid function for nmi/warm. */ | |
2613 | nmi = lookup_attribute ("nmi", func_attrs); | |
2614 | warm = lookup_attribute ("warm", func_attrs); | |
2615 | ||
2616 | if (nmi != NULL_TREE) | |
2617 | { | |
2618 | tree nmi_func_list; | |
2619 | tree nmi_func; | |
2620 | ||
2621 | nmi_func_list = TREE_VALUE (nmi); | |
2622 | nmi_func = TREE_VALUE (nmi_func_list); | |
2623 | ||
2624 | /* Issue error if it is not a valid nmi function. */ | |
2625 | if (TREE_CODE (nmi_func) != IDENTIFIER_NODE) | |
2626 | error ("invalid nmi function for reset attribute"); | |
2627 | } | |
2628 | ||
2629 | if (warm != NULL_TREE) | |
2630 | { | |
2631 | tree warm_func_list; | |
2632 | tree warm_func; | |
2633 | ||
2634 | warm_func_list = TREE_VALUE (warm); | |
2635 | warm_func = TREE_VALUE (warm_func_list); | |
2636 | ||
2637 | /* Issue error if it is not a valid warm function. */ | |
2638 | if (TREE_CODE (warm_func) != IDENTIFIER_NODE) | |
2639 | error ("invalid warm function for reset attribute"); | |
2640 | } | |
2641 | } | |
2642 | else | |
2643 | { | |
2644 | /* No interrupt, exception, or reset attribute is set. */ | |
2645 | return; | |
2646 | } | |
2647 | } | |
2648 | } | |
2649 | ||
2650 | static bool | |
2651 | nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED, | |
2652 | tree pop_target ATTRIBUTE_UNUSED) | |
2653 | { | |
2654 | /* Currently, we do not parse any pragma target by ourself, | |
2655 | so just simply return false. */ | |
2656 | return false; | |
2657 | } | |
2658 | ||
2659 | static void | |
2660 | nds32_option_override (void) | |
2661 | { | |
2662 | /* After all the command options have been parsed, | |
2663 | we shall deal with some flags for changing compiler settings. */ | |
2664 | ||
2665 | /* At first, we check if we have to strictly | |
2666 | set some flags based on ISA family. */ | |
2667 | if (TARGET_ISA_V2) | |
2668 | { | |
2669 | /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */ | |
2670 | target_flags &= ~MASK_V3PUSH; | |
2671 | } | |
2672 | if (TARGET_ISA_V3) | |
2673 | { | |
2674 | /* Under V3 ISA, currently nothing should be strictly set. */ | |
2675 | } | |
2676 | if (TARGET_ISA_V3M) | |
2677 | { | |
2678 | /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */ | |
2679 | target_flags |= MASK_REDUCED_REGS; | |
2680 | /* Under V3M ISA, we need to strictly disable TARGET_PERF_EXT. */ | |
2681 | target_flags &= ~MASK_PERF_EXT; | |
2682 | } | |
2683 | ||
2684 | /* See if we are using reduced-set registers: | |
2685 | $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31 | |
2686 | If so, we must forbid using $r11~$r14, $r16~$r27. */ | |
2687 | if (TARGET_REDUCED_REGS) | |
2688 | { | |
2689 | int r; | |
2690 | ||
2691 | /* Prevent register allocator from | |
2692 | choosing it as doing register allocation. */ | |
2693 | for (r = 11; r <= 14; r++) | |
2694 | fixed_regs[r] = call_used_regs[r] = 1; | |
2695 | for (r = 16; r <= 27; r++) | |
2696 | fixed_regs[r] = call_used_regs[r] = 1; | |
2697 | } | |
2698 | ||
9304f876 CJW |
2699 | if (!TARGET_16_BIT) |
2700 | { | |
2701 | /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */ | |
2702 | target_flags &= ~MASK_V3PUSH; | |
2703 | } | |
2704 | ||
2705 | /* Currently, we don't support PIC code generation yet. */ | |
2706 | if (flag_pic) | |
afd78f02 | 2707 | sorry ("position-independent code not supported"); |
9304f876 CJW |
2708 | } |
2709 | ||
2710 | \f | |
2711 | /* Miscellaneous Parameters. */ | |
2712 | ||
2713 | static void | |
2714 | nds32_init_builtins (void) | |
2715 | { | |
aaa44d2d | 2716 | nds32_init_builtins_impl (); |
9304f876 CJW |
2717 | } |
2718 | ||
2719 | static rtx | |
2720 | nds32_expand_builtin (tree exp, | |
2721 | rtx target, | |
aaa44d2d | 2722 | rtx subtarget, |
ef4bddc2 | 2723 | machine_mode mode, |
aaa44d2d | 2724 | int ignore) |
9304f876 | 2725 | { |
aaa44d2d | 2726 | return nds32_expand_builtin_impl (exp, target, subtarget, mode, ignore); |
9304f876 CJW |
2727 | } |
2728 | ||
2729 | ||
2730 | /* ------------------------------------------------------------------------ */ | |
2731 | ||
2732 | /* PART 4: Implemet extern function definitions, | |
2733 | the prototype is in nds32-protos.h. */ | |
2734 | \f | |
2735 | /* Defining Data Structures for Per-function Information. */ | |
2736 | ||
2737 | void | |
2738 | nds32_init_expanders (void) | |
2739 | { | |
2740 | /* Arrange to initialize and mark the machine per-function status. */ | |
2741 | init_machine_status = nds32_init_machine_status; | |
2742 | } | |
2743 | ||
2744 | \f | |
2745 | /* Register Usage. */ | |
2746 | ||
2747 | /* -- How Values Fit in Registers. */ | |
2748 | ||
f939c3e6 RS |
2749 | /* Implement TARGET_HARD_REGNO_MODE_OK. */ |
2750 | ||
2751 | static bool | |
2752 | nds32_hard_regno_mode_ok (unsigned int regno, machine_mode mode) | |
9304f876 CJW |
2753 | { |
2754 | /* Restrict double-word quantities to even register pairs. */ | |
c43f4279 | 2755 | if (targetm.hard_regno_nregs (regno, mode) == 1 |
9304f876 | 2756 | || !((regno) & 1)) |
f939c3e6 | 2757 | return true; |
9304f876 | 2758 | |
f939c3e6 | 2759 | return false; |
9304f876 CJW |
2760 | } |
2761 | ||
f939c3e6 RS |
2762 | #undef TARGET_HARD_REGNO_MODE_OK |
2763 | #define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok | |
99e1629f RS |
2764 | |
2765 | /* Implement TARGET_MODES_TIEABLE_P. We can use general registers to | |
2766 | tie QI/HI/SI modes together. */ | |
2767 | ||
2768 | static bool | |
2769 | nds32_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
2770 | { | |
2771 | return (GET_MODE_CLASS (mode1) == MODE_INT | |
2772 | && GET_MODE_CLASS (mode2) == MODE_INT | |
2773 | && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD | |
2774 | && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD); | |
2775 | } | |
2776 | ||
2777 | #undef TARGET_MODES_TIEABLE_P | |
2778 | #define TARGET_MODES_TIEABLE_P nds32_modes_tieable_p | |
9304f876 CJW |
2779 | \f |
2780 | /* Register Classes. */ | |
2781 | ||
2782 | enum reg_class | |
2783 | nds32_regno_reg_class (int regno) | |
2784 | { | |
2785 | /* Refer to nds32.h for more register class details. */ | |
2786 | ||
2787 | if (regno >= 0 && regno <= 7) | |
2788 | return LOW_REGS; | |
2789 | else if (regno >= 8 && regno <= 11) | |
2790 | return MIDDLE_REGS; | |
2791 | else if (regno >= 12 && regno <= 14) | |
2792 | return HIGH_REGS; | |
2793 | else if (regno == 15) | |
2794 | return R15_TA_REG; | |
2795 | else if (regno >= 16 && regno <= 19) | |
2796 | return MIDDLE_REGS; | |
2797 | else if (regno >= 20 && regno <= 31) | |
2798 | return HIGH_REGS; | |
2799 | else if (regno == 32 || regno == 33) | |
2800 | return FRAME_REGS; | |
2801 | else | |
2802 | return NO_REGS; | |
2803 | } | |
2804 | ||
2805 | \f | |
2806 | /* Stack Layout and Calling Conventions. */ | |
2807 | ||
2808 | /* -- Basic Stack Layout. */ | |
2809 | ||
2810 | rtx | |
2811 | nds32_return_addr_rtx (int count, | |
2812 | rtx frameaddr ATTRIBUTE_UNUSED) | |
2813 | { | |
2814 | /* There is no way to determine the return address | |
2815 | if frameaddr is the frame that has 'count' steps | |
2816 | up from current frame. */ | |
2817 | if (count != 0) | |
2818 | return NULL_RTX; | |
2819 | ||
2820 | /* If count == 0, it means we are at current frame, | |
2821 | the return address is $r30 ($lp). */ | |
2822 | return get_hard_reg_initial_val (Pmode, LP_REGNUM); | |
2823 | } | |
2824 | ||
2825 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
2826 | ||
2827 | HOST_WIDE_INT | |
2828 | nds32_initial_elimination_offset (unsigned int from_reg, unsigned int to_reg) | |
2829 | { | |
2830 | HOST_WIDE_INT offset; | |
2831 | ||
2832 | /* Compute and setup stack frame size. | |
2833 | The result will be in cfun->machine. */ | |
2834 | nds32_compute_stack_frame (); | |
2835 | ||
2836 | /* Remember to consider | |
2837 | cfun->machine->callee_saved_area_padding_bytes | |
2838 | when calculating offset. */ | |
2839 | if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) | |
2840 | { | |
2841 | offset = (cfun->machine->fp_size | |
2842 | + cfun->machine->gp_size | |
2843 | + cfun->machine->lp_size | |
c457f751 CJW |
2844 | + cfun->machine->callee_saved_gpr_regs_size |
2845 | + cfun->machine->callee_saved_area_gpr_padding_bytes | |
9304f876 CJW |
2846 | + cfun->machine->local_size |
2847 | + cfun->machine->out_args_size); | |
2848 | } | |
2849 | else if (from_reg == ARG_POINTER_REGNUM | |
2850 | && to_reg == HARD_FRAME_POINTER_REGNUM) | |
2851 | { | |
2852 | offset = 0; | |
2853 | } | |
2854 | else if (from_reg == FRAME_POINTER_REGNUM | |
2855 | && to_reg == STACK_POINTER_REGNUM) | |
2856 | { | |
2857 | offset = (cfun->machine->local_size + cfun->machine->out_args_size); | |
2858 | } | |
2859 | else if (from_reg == FRAME_POINTER_REGNUM | |
2860 | && to_reg == HARD_FRAME_POINTER_REGNUM) | |
2861 | { | |
2862 | offset = (-1) * (cfun->machine->fp_size | |
2863 | + cfun->machine->gp_size | |
2864 | + cfun->machine->lp_size | |
c457f751 CJW |
2865 | + cfun->machine->callee_saved_gpr_regs_size |
2866 | + cfun->machine->callee_saved_area_gpr_padding_bytes); | |
9304f876 CJW |
2867 | } |
2868 | else | |
2869 | { | |
2870 | gcc_unreachable (); | |
2871 | } | |
2872 | ||
2873 | return offset; | |
2874 | } | |
2875 | ||
2876 | /* -- Passing Arguments in Registers. */ | |
2877 | ||
2878 | void | |
2879 | nds32_init_cumulative_args (CUMULATIVE_ARGS *cum, | |
2880 | tree fntype ATTRIBUTE_UNUSED, | |
2881 | rtx libname ATTRIBUTE_UNUSED, | |
2882 | tree fndecl ATTRIBUTE_UNUSED, | |
2883 | int n_named_args ATTRIBUTE_UNUSED) | |
2884 | { | |
2885 | /* Initial available registers | |
2886 | (in offset, corresponding to NDS32_GPR_ARG_FIRST_REGNUM) | |
2887 | for passing arguments. */ | |
9d93cc24 | 2888 | cum->gpr_offset = 0; |
9304f876 CJW |
2889 | } |
2890 | ||
2891 | /* -- Function Entry and Exit. */ | |
2892 | ||
2893 | /* Function for normal multiple push prologue. */ | |
2894 | void | |
2895 | nds32_expand_prologue (void) | |
2896 | { | |
2897 | int fp_adjust; | |
2898 | int sp_adjust; | |
2899 | int en4_const; | |
2900 | ||
2901 | rtx Rb, Re; | |
9304f876 CJW |
2902 | rtx fp_adjust_insn, sp_adjust_insn; |
2903 | ||
9304f876 CJW |
2904 | /* Compute and setup stack frame size. |
2905 | The result will be in cfun->machine. */ | |
2906 | nds32_compute_stack_frame (); | |
2907 | ||
557430f1 CJW |
2908 | /* If this is a variadic function, first we need to push argument |
2909 | registers that hold the unnamed argument value. */ | |
2910 | if (cfun->machine->va_args_size != 0) | |
2911 | { | |
2912 | Rb = gen_rtx_REG (SImode, cfun->machine->va_args_first_regno); | |
2913 | Re = gen_rtx_REG (SImode, cfun->machine->va_args_last_regno); | |
2914 | /* No need to push $fp, $gp, or $lp, so use GEN_INT(0). */ | |
47e0e7d2 | 2915 | nds32_emit_stack_push_multiple (Rb, Re, GEN_INT (0), true); |
557430f1 CJW |
2916 | |
2917 | /* We may also need to adjust stack pointer for padding bytes | |
2918 | because varargs may cause $sp not 8-byte aligned. */ | |
2919 | if (cfun->machine->va_args_area_padding_bytes) | |
2920 | { | |
2921 | /* Generate sp adjustment instruction. */ | |
2922 | sp_adjust = cfun->machine->va_args_area_padding_bytes; | |
2923 | sp_adjust_insn = gen_addsi3 (stack_pointer_rtx, | |
2924 | stack_pointer_rtx, | |
2925 | GEN_INT (-1 * sp_adjust)); | |
2926 | ||
2927 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
2928 | sp_adjust_insn = emit_insn (sp_adjust_insn); | |
2929 | ||
2930 | /* The insn rtx 'sp_adjust_insn' will change frame layout. | |
2931 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
2932 | generate CFI (Call Frame Information) stuff. */ | |
2933 | RTX_FRAME_RELATED_P (sp_adjust_insn) = 1; | |
2934 | } | |
2935 | } | |
2936 | ||
9304f876 CJW |
2937 | /* If the function is 'naked', |
2938 | we do not have to generate prologue code fragment. */ | |
2939 | if (cfun->machine->naked_p) | |
2940 | return; | |
2941 | ||
2942 | /* Get callee_first_regno and callee_last_regno. */ | |
c457f751 CJW |
2943 | Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_first_gpr_regno); |
2944 | Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_last_gpr_regno); | |
9304f876 | 2945 | |
4e9a2848 | 2946 | /* nds32_emit_stack_push_multiple(first_regno, last_regno), |
9304f876 CJW |
2947 | the pattern 'stack_push_multiple' is implemented in nds32.md. |
2948 | For En4 field, we have to calculate its constant value. | |
2949 | Refer to Andes ISA for more information. */ | |
2950 | en4_const = 0; | |
2951 | if (cfun->machine->fp_size) | |
2952 | en4_const += 8; | |
2953 | if (cfun->machine->gp_size) | |
2954 | en4_const += 4; | |
2955 | if (cfun->machine->lp_size) | |
2956 | en4_const += 2; | |
2957 | ||
2958 | /* If $fp, $gp, $lp, and all callee-save registers are NOT required | |
2959 | to be saved, we don't have to create multiple push instruction. | |
2960 | Otherwise, a multiple push instruction is needed. */ | |
2961 | if (!(REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM && en4_const == 0)) | |
2962 | { | |
2963 | /* Create multiple push instruction rtx. */ | |
47e0e7d2 | 2964 | nds32_emit_stack_push_multiple (Rb, Re, GEN_INT (en4_const), false); |
9304f876 CJW |
2965 | } |
2966 | ||
2967 | /* Check frame_pointer_needed to see | |
2968 | if we shall emit fp adjustment instruction. */ | |
2969 | if (frame_pointer_needed) | |
2970 | { | |
2971 | /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size) | |
2972 | + (4 * callee-saved-registers) | |
2973 | Note: No need to adjust | |
2974 | cfun->machine->callee_saved_area_padding_bytes, | |
2975 | because, at this point, stack pointer is just | |
2976 | at the position after push instruction. */ | |
2977 | fp_adjust = cfun->machine->fp_size | |
2978 | + cfun->machine->gp_size | |
2979 | + cfun->machine->lp_size | |
c457f751 | 2980 | + cfun->machine->callee_saved_gpr_regs_size; |
9304f876 CJW |
2981 | fp_adjust_insn = gen_addsi3 (hard_frame_pointer_rtx, |
2982 | stack_pointer_rtx, | |
2983 | GEN_INT (fp_adjust)); | |
2984 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
2985 | fp_adjust_insn = emit_insn (fp_adjust_insn); | |
7064dcad CJW |
2986 | |
2987 | /* The insn rtx 'fp_adjust_insn' will change frame layout. */ | |
2988 | RTX_FRAME_RELATED_P (fp_adjust_insn) = 1; | |
9304f876 CJW |
2989 | } |
2990 | ||
2991 | /* Adjust $sp = $sp - local_size - out_args_size | |
2992 | - callee_saved_area_padding_bytes. */ | |
2993 | sp_adjust = cfun->machine->local_size | |
2994 | + cfun->machine->out_args_size | |
c457f751 | 2995 | + cfun->machine->callee_saved_area_gpr_padding_bytes; |
9304f876 CJW |
2996 | /* sp_adjust value may be out of range of the addi instruction, |
2997 | create alternative add behavior with TA_REGNUM if necessary, | |
2998 | using NEGATIVE value to tell that we are decreasing address. */ | |
2999 | sp_adjust = nds32_force_addi_stack_int ( (-1) * sp_adjust); | |
3000 | if (sp_adjust) | |
3001 | { | |
3002 | /* Generate sp adjustment instruction if and only if sp_adjust != 0. */ | |
3003 | sp_adjust_insn = gen_addsi3 (stack_pointer_rtx, | |
3004 | stack_pointer_rtx, | |
3005 | GEN_INT (-1 * sp_adjust)); | |
3006 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
3007 | sp_adjust_insn = emit_insn (sp_adjust_insn); | |
3008 | ||
3009 | /* The insn rtx 'sp_adjust_insn' will change frame layout. | |
3010 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
3011 | generate CFI (Call Frame Information) stuff. */ | |
3012 | RTX_FRAME_RELATED_P (sp_adjust_insn) = 1; | |
3013 | } | |
3014 | ||
3015 | /* Prevent the instruction scheduler from | |
3016 | moving instructions across the boundary. */ | |
3017 | emit_insn (gen_blockage ()); | |
3018 | } | |
3019 | ||
3020 | /* Function for normal multiple pop epilogue. */ | |
3021 | void | |
d6529176 | 3022 | nds32_expand_epilogue (bool sibcall_p) |
9304f876 CJW |
3023 | { |
3024 | int sp_adjust; | |
3025 | int en4_const; | |
3026 | ||
3027 | rtx Rb, Re; | |
9304f876 CJW |
3028 | rtx sp_adjust_insn; |
3029 | ||
3030 | /* Compute and setup stack frame size. | |
3031 | The result will be in cfun->machine. */ | |
3032 | nds32_compute_stack_frame (); | |
3033 | ||
3034 | /* Prevent the instruction scheduler from | |
3035 | moving instructions across the boundary. */ | |
3036 | emit_insn (gen_blockage ()); | |
3037 | ||
3038 | /* If the function is 'naked', we do not have to generate | |
557430f1 CJW |
3039 | epilogue code fragment BUT 'ret' instruction. |
3040 | However, if this function is also a variadic function, | |
3041 | we need to create adjust stack pointer before 'ret' instruction. */ | |
9304f876 CJW |
3042 | if (cfun->machine->naked_p) |
3043 | { | |
557430f1 CJW |
3044 | /* If this is a variadic function, we do not have to restore argument |
3045 | registers but need to adjust stack pointer back to previous stack | |
3046 | frame location before return. */ | |
3047 | if (cfun->machine->va_args_size != 0) | |
3048 | { | |
3049 | /* Generate sp adjustment instruction. | |
3050 | We need to consider padding bytes here. */ | |
3051 | sp_adjust = cfun->machine->va_args_size | |
3052 | + cfun->machine->va_args_area_padding_bytes; | |
3053 | sp_adjust_insn = gen_addsi3 (stack_pointer_rtx, | |
3054 | stack_pointer_rtx, | |
3055 | GEN_INT (sp_adjust)); | |
3056 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
3057 | sp_adjust_insn = emit_insn (sp_adjust_insn); | |
3058 | ||
3059 | /* The insn rtx 'sp_adjust_insn' will change frame layout. | |
3060 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
3061 | generate CFI (Call Frame Information) stuff. */ | |
3062 | RTX_FRAME_RELATED_P (sp_adjust_insn) = 1; | |
3063 | } | |
3064 | ||
03390cda CJW |
3065 | /* Generate return instruction by using 'return_internal' pattern. |
3066 | Make sure this instruction is after gen_blockage(). */ | |
d6529176 CJW |
3067 | if (!sibcall_p) |
3068 | emit_jump_insn (gen_return_internal ()); | |
9304f876 CJW |
3069 | return; |
3070 | } | |
3071 | ||
3072 | if (frame_pointer_needed) | |
3073 | { | |
3074 | /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) | |
3075 | - (4 * callee-saved-registers) | |
3076 | Note: No need to adjust | |
3077 | cfun->machine->callee_saved_area_padding_bytes, | |
3078 | because we want to adjust stack pointer | |
3079 | to the position for pop instruction. */ | |
3080 | sp_adjust = cfun->machine->fp_size | |
3081 | + cfun->machine->gp_size | |
3082 | + cfun->machine->lp_size | |
c457f751 | 3083 | + cfun->machine->callee_saved_gpr_regs_size; |
9304f876 CJW |
3084 | sp_adjust_insn = gen_addsi3 (stack_pointer_rtx, |
3085 | hard_frame_pointer_rtx, | |
3086 | GEN_INT (-1 * sp_adjust)); | |
3087 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
3088 | sp_adjust_insn = emit_insn (sp_adjust_insn); | |
557430f1 CJW |
3089 | |
3090 | /* The insn rtx 'sp_adjust_insn' will change frame layout. */ | |
3091 | RTX_FRAME_RELATED_P (sp_adjust_insn) = 1; | |
9304f876 CJW |
3092 | } |
3093 | else | |
3094 | { | |
3095 | /* If frame pointer is NOT needed, | |
3096 | we cannot calculate the sp adjustment from frame pointer. | |
3097 | Instead, we calculate the adjustment by local_size, | |
3098 | out_args_size, and callee_saved_area_padding_bytes. | |
3099 | Notice that such sp adjustment value may be out of range, | |
3100 | so we have to deal with it as well. */ | |
3101 | ||
3102 | /* Adjust $sp = $sp + local_size + out_args_size | |
3103 | + callee_saved_area_padding_bytes. */ | |
3104 | sp_adjust = cfun->machine->local_size | |
3105 | + cfun->machine->out_args_size | |
c457f751 | 3106 | + cfun->machine->callee_saved_area_gpr_padding_bytes; |
9304f876 CJW |
3107 | /* sp_adjust value may be out of range of the addi instruction, |
3108 | create alternative add behavior with TA_REGNUM if necessary, | |
3109 | using POSITIVE value to tell that we are increasing address. */ | |
3110 | sp_adjust = nds32_force_addi_stack_int (sp_adjust); | |
3111 | if (sp_adjust) | |
3112 | { | |
3113 | /* Generate sp adjustment instruction | |
3114 | if and only if sp_adjust != 0. */ | |
3115 | sp_adjust_insn = gen_addsi3 (stack_pointer_rtx, | |
3116 | stack_pointer_rtx, | |
3117 | GEN_INT (sp_adjust)); | |
3118 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
3119 | sp_adjust_insn = emit_insn (sp_adjust_insn); | |
557430f1 CJW |
3120 | |
3121 | /* The insn rtx 'sp_adjust_insn' will change frame layout. */ | |
3122 | RTX_FRAME_RELATED_P (sp_adjust_insn) = 1; | |
9304f876 CJW |
3123 | } |
3124 | } | |
3125 | ||
3126 | /* Get callee_first_regno and callee_last_regno. */ | |
c457f751 CJW |
3127 | Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_first_gpr_regno); |
3128 | Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_last_gpr_regno); | |
9304f876 | 3129 | |
4e9a2848 | 3130 | /* nds32_emit_stack_pop_multiple(first_regno, last_regno), |
9304f876 CJW |
3131 | the pattern 'stack_pop_multiple' is implementad in nds32.md. |
3132 | For En4 field, we have to calculate its constant value. | |
3133 | Refer to Andes ISA for more information. */ | |
3134 | en4_const = 0; | |
3135 | if (cfun->machine->fp_size) | |
3136 | en4_const += 8; | |
3137 | if (cfun->machine->gp_size) | |
3138 | en4_const += 4; | |
3139 | if (cfun->machine->lp_size) | |
3140 | en4_const += 2; | |
3141 | ||
3142 | /* If $fp, $gp, $lp, and all callee-save registers are NOT required | |
3143 | to be saved, we don't have to create multiple pop instruction. | |
3144 | Otherwise, a multiple pop instruction is needed. */ | |
3145 | if (!(REGNO (Rb) == SP_REGNUM && REGNO (Re) == SP_REGNUM && en4_const == 0)) | |
3146 | { | |
3147 | /* Create multiple pop instruction rtx. */ | |
4e9a2848 | 3148 | nds32_emit_stack_pop_multiple (Rb, Re, GEN_INT (en4_const)); |
9304f876 CJW |
3149 | } |
3150 | ||
557430f1 CJW |
3151 | /* If this is a variadic function, we do not have to restore argument |
3152 | registers but need to adjust stack pointer back to previous stack | |
3153 | frame location before return. */ | |
3154 | if (cfun->machine->va_args_size != 0) | |
3155 | { | |
3156 | /* Generate sp adjustment instruction. | |
3157 | We need to consider padding bytes here. */ | |
3158 | sp_adjust = cfun->machine->va_args_size | |
3159 | + cfun->machine->va_args_area_padding_bytes; | |
3160 | sp_adjust_insn = gen_addsi3 (stack_pointer_rtx, | |
3161 | stack_pointer_rtx, | |
3162 | GEN_INT (sp_adjust)); | |
3163 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
3164 | sp_adjust_insn = emit_insn (sp_adjust_insn); | |
3165 | ||
3166 | /* The insn rtx 'sp_adjust_insn' will change frame layout. | |
3167 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
3168 | generate CFI (Call Frame Information) stuff. */ | |
3169 | RTX_FRAME_RELATED_P (sp_adjust_insn) = 1; | |
3170 | } | |
3171 | ||
03390cda | 3172 | /* Generate return instruction. */ |
d6529176 CJW |
3173 | if (!sibcall_p) |
3174 | emit_jump_insn (gen_return_internal ()); | |
9304f876 CJW |
3175 | } |
3176 | ||
3177 | /* Function for v3push prologue. */ | |
3178 | void | |
3179 | nds32_expand_prologue_v3push (void) | |
3180 | { | |
3181 | int fp_adjust; | |
3182 | int sp_adjust; | |
3183 | ||
3184 | rtx Rb, Re; | |
9304f876 CJW |
3185 | rtx fp_adjust_insn, sp_adjust_insn; |
3186 | ||
9304f876 CJW |
3187 | /* Compute and setup stack frame size. |
3188 | The result will be in cfun->machine. */ | |
3189 | nds32_compute_stack_frame (); | |
3190 | ||
3191 | /* If the function is 'naked', | |
3192 | we do not have to generate prologue code fragment. */ | |
3193 | if (cfun->machine->naked_p) | |
3194 | return; | |
3195 | ||
3196 | /* Get callee_first_regno and callee_last_regno. */ | |
c457f751 CJW |
3197 | Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_first_gpr_regno); |
3198 | Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_last_gpr_regno); | |
9304f876 CJW |
3199 | |
3200 | /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available, | |
3201 | where imm8u has to be 8-byte alignment. */ | |
3202 | sp_adjust = cfun->machine->local_size | |
3203 | + cfun->machine->out_args_size | |
c457f751 | 3204 | + cfun->machine->callee_saved_area_gpr_padding_bytes; |
9304f876 CJW |
3205 | |
3206 | if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
3207 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)) | |
3208 | { | |
3209 | /* We can use 'push25 Re,imm8u'. */ | |
3210 | ||
88437f39 | 3211 | /* nds32_emit_stack_v3push(last_regno, sp_adjust), |
9304f876 CJW |
3212 | the pattern 'stack_v3push' is implemented in nds32.md. |
3213 | The (const_int 14) means v3push always push { $fp $gp $lp }. */ | |
88437f39 CJW |
3214 | nds32_emit_stack_v3push (Rb, Re, |
3215 | GEN_INT (14), GEN_INT (sp_adjust)); | |
9304f876 CJW |
3216 | |
3217 | /* Check frame_pointer_needed to see | |
3218 | if we shall emit fp adjustment instruction. */ | |
3219 | if (frame_pointer_needed) | |
3220 | { | |
3221 | /* adjust $fp = $sp + 4 ($fp size) | |
3222 | + 4 ($gp size) | |
3223 | + 4 ($lp size) | |
3224 | + (4 * n) (callee-saved registers) | |
3225 | + sp_adjust ('push25 Re,imm8u') | |
3226 | Note: Since we use 'push25 Re,imm8u', | |
3227 | the position of stack pointer is further | |
3228 | changed after push instruction. | |
3229 | Hence, we need to take sp_adjust value | |
3230 | into consideration. */ | |
3231 | fp_adjust = cfun->machine->fp_size | |
3232 | + cfun->machine->gp_size | |
3233 | + cfun->machine->lp_size | |
c457f751 | 3234 | + cfun->machine->callee_saved_gpr_regs_size |
9304f876 CJW |
3235 | + sp_adjust; |
3236 | fp_adjust_insn = gen_addsi3 (hard_frame_pointer_rtx, | |
3237 | stack_pointer_rtx, | |
3238 | GEN_INT (fp_adjust)); | |
3239 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
3240 | fp_adjust_insn = emit_insn (fp_adjust_insn); | |
3241 | } | |
3242 | } | |
3243 | else | |
3244 | { | |
3245 | /* We have to use 'push25 Re,0' and | |
3246 | expand one more instruction to adjust $sp later. */ | |
3247 | ||
88437f39 | 3248 | /* nds32_emit_stack_v3push(last_regno, sp_adjust), |
9304f876 CJW |
3249 | the pattern 'stack_v3push' is implemented in nds32.md. |
3250 | The (const_int 14) means v3push always push { $fp $gp $lp }. */ | |
88437f39 CJW |
3251 | nds32_emit_stack_v3push (Rb, Re, |
3252 | GEN_INT (14), GEN_INT (0)); | |
9304f876 CJW |
3253 | |
3254 | /* Check frame_pointer_needed to see | |
3255 | if we shall emit fp adjustment instruction. */ | |
3256 | if (frame_pointer_needed) | |
3257 | { | |
3258 | /* adjust $fp = $sp + 4 ($fp size) | |
3259 | + 4 ($gp size) | |
3260 | + 4 ($lp size) | |
3261 | + (4 * n) (callee-saved registers) | |
3262 | Note: Since we use 'push25 Re,0', | |
3263 | the stack pointer is just at the position | |
3264 | after push instruction. | |
3265 | No need to take sp_adjust into consideration. */ | |
3266 | fp_adjust = cfun->machine->fp_size | |
3267 | + cfun->machine->gp_size | |
3268 | + cfun->machine->lp_size | |
c457f751 | 3269 | + cfun->machine->callee_saved_gpr_regs_size; |
9304f876 CJW |
3270 | fp_adjust_insn = gen_addsi3 (hard_frame_pointer_rtx, |
3271 | stack_pointer_rtx, | |
3272 | GEN_INT (fp_adjust)); | |
3273 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
3274 | fp_adjust_insn = emit_insn (fp_adjust_insn); | |
3275 | } | |
3276 | ||
3277 | /* Because we use 'push25 Re,0', | |
3278 | we need to expand one more instruction to adjust $sp. | |
3279 | However, sp_adjust value may be out of range of the addi instruction, | |
3280 | create alternative add behavior with TA_REGNUM if necessary, | |
3281 | using NEGATIVE value to tell that we are decreasing address. */ | |
3282 | sp_adjust = nds32_force_addi_stack_int ( (-1) * sp_adjust); | |
3283 | if (sp_adjust) | |
3284 | { | |
3285 | /* Generate sp adjustment instruction | |
3286 | if and only if sp_adjust != 0. */ | |
3287 | sp_adjust_insn = gen_addsi3 (stack_pointer_rtx, | |
3288 | stack_pointer_rtx, | |
3289 | GEN_INT (-1 * sp_adjust)); | |
3290 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
3291 | sp_adjust_insn = emit_insn (sp_adjust_insn); | |
3292 | ||
3293 | /* The insn rtx 'sp_adjust_insn' will change frame layout. | |
3294 | We need to use RTX_FRAME_RELATED_P so that GCC is able to | |
3295 | generate CFI (Call Frame Information) stuff. */ | |
3296 | RTX_FRAME_RELATED_P (sp_adjust_insn) = 1; | |
3297 | } | |
3298 | } | |
3299 | ||
3300 | /* Prevent the instruction scheduler from | |
3301 | moving instructions across the boundary. */ | |
3302 | emit_insn (gen_blockage ()); | |
3303 | } | |
3304 | ||
3305 | /* Function for v3pop epilogue. */ | |
3306 | void | |
d6529176 | 3307 | nds32_expand_epilogue_v3pop (bool sibcall_p) |
9304f876 CJW |
3308 | { |
3309 | int sp_adjust; | |
3310 | ||
3311 | rtx Rb, Re; | |
9304f876 CJW |
3312 | rtx sp_adjust_insn; |
3313 | ||
3314 | /* Compute and setup stack frame size. | |
3315 | The result will be in cfun->machine. */ | |
3316 | nds32_compute_stack_frame (); | |
3317 | ||
3318 | /* Prevent the instruction scheduler from | |
3319 | moving instructions across the boundary. */ | |
3320 | emit_insn (gen_blockage ()); | |
3321 | ||
3322 | /* If the function is 'naked', we do not have to generate | |
3323 | epilogue code fragment BUT 'ret' instruction. */ | |
3324 | if (cfun->machine->naked_p) | |
3325 | { | |
03390cda CJW |
3326 | /* Generate return instruction by using 'return_internal' pattern. |
3327 | Make sure this instruction is after gen_blockage(). */ | |
d6529176 CJW |
3328 | if (!sibcall_p) |
3329 | emit_jump_insn (gen_return_internal ()); | |
9304f876 CJW |
3330 | return; |
3331 | } | |
3332 | ||
3333 | /* Get callee_first_regno and callee_last_regno. */ | |
c457f751 CJW |
3334 | Rb = gen_rtx_REG (SImode, cfun->machine->callee_saved_first_gpr_regno); |
3335 | Re = gen_rtx_REG (SImode, cfun->machine->callee_saved_last_gpr_regno); | |
9304f876 CJW |
3336 | |
3337 | /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available, | |
3338 | where imm8u has to be 8-byte alignment. */ | |
3339 | sp_adjust = cfun->machine->local_size | |
3340 | + cfun->machine->out_args_size | |
c457f751 | 3341 | + cfun->machine->callee_saved_area_gpr_padding_bytes; |
9304f876 CJW |
3342 | |
3343 | /* We have to consider alloca issue as well. | |
3344 | If the function does call alloca(), the stack pointer is not fixed. | |
3345 | In that case, we cannot use 'pop25 Re,imm8u' directly. | |
3346 | We have to caculate stack pointer from frame pointer | |
3347 | and then use 'pop25 Re,0'. | |
3348 | Of course, the frame_pointer_needed should be nonzero | |
3349 | if the function calls alloca(). */ | |
3350 | if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) | |
3351 | && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) | |
3352 | && !cfun->calls_alloca) | |
3353 | { | |
3354 | /* We can use 'pop25 Re,imm8u'. */ | |
3355 | ||
88437f39 | 3356 | /* nds32_emit_stack_v3pop(last_regno, sp_adjust), |
9304f876 CJW |
3357 | the pattern 'stack_v3pop' is implementad in nds32.md. |
3358 | The (const_int 14) means v3pop always pop { $fp $gp $lp }. */ | |
88437f39 CJW |
3359 | nds32_emit_stack_v3pop (Rb, Re, |
3360 | GEN_INT (14), GEN_INT (sp_adjust)); | |
9304f876 CJW |
3361 | } |
3362 | else | |
3363 | { | |
3364 | /* We have to use 'pop25 Re,0', and prior to it, | |
3365 | we must expand one more instruction to adjust $sp. */ | |
3366 | ||
3367 | if (frame_pointer_needed) | |
3368 | { | |
3369 | /* adjust $sp = $fp - 4 ($fp size) | |
3370 | - 4 ($gp size) | |
3371 | - 4 ($lp size) | |
3372 | - (4 * n) (callee-saved registers) | |
3373 | Note: No need to adjust | |
3374 | cfun->machine->callee_saved_area_padding_bytes, | |
3375 | because we want to adjust stack pointer | |
3376 | to the position for pop instruction. */ | |
3377 | sp_adjust = cfun->machine->fp_size | |
3378 | + cfun->machine->gp_size | |
3379 | + cfun->machine->lp_size | |
c457f751 | 3380 | + cfun->machine->callee_saved_gpr_regs_size; |
9304f876 CJW |
3381 | sp_adjust_insn = gen_addsi3 (stack_pointer_rtx, |
3382 | hard_frame_pointer_rtx, | |
3383 | GEN_INT (-1 * sp_adjust)); | |
3384 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
3385 | sp_adjust_insn = emit_insn (sp_adjust_insn); | |
3386 | } | |
3387 | else | |
3388 | { | |
3389 | /* If frame pointer is NOT needed, | |
3390 | we cannot calculate the sp adjustment from frame pointer. | |
3391 | Instead, we calculate the adjustment by local_size, | |
3392 | out_args_size, and callee_saved_area_padding_bytes. | |
3393 | Notice that such sp adjustment value may be out of range, | |
3394 | so we have to deal with it as well. */ | |
3395 | ||
3396 | /* Adjust $sp = $sp + local_size + out_args_size | |
3397 | + callee_saved_area_padding_bytes. */ | |
3398 | sp_adjust = cfun->machine->local_size | |
3399 | + cfun->machine->out_args_size | |
c457f751 | 3400 | + cfun->machine->callee_saved_area_gpr_padding_bytes; |
9304f876 CJW |
3401 | /* sp_adjust value may be out of range of the addi instruction, |
3402 | create alternative add behavior with TA_REGNUM if necessary, | |
3403 | using POSITIVE value to tell that we are increasing address. */ | |
3404 | sp_adjust = nds32_force_addi_stack_int (sp_adjust); | |
3405 | if (sp_adjust) | |
3406 | { | |
3407 | /* Generate sp adjustment instruction | |
3408 | if and only if sp_adjust != 0. */ | |
3409 | sp_adjust_insn = gen_addsi3 (stack_pointer_rtx, | |
3410 | stack_pointer_rtx, | |
3411 | GEN_INT (sp_adjust)); | |
3412 | /* Emit rtx into instructions list and receive INSN rtx form. */ | |
3413 | sp_adjust_insn = emit_insn (sp_adjust_insn); | |
3414 | } | |
3415 | } | |
3416 | ||
88437f39 | 3417 | /* nds32_emit_stack_v3pop(last_regno, sp_adjust), |
9304f876 CJW |
3418 | the pattern 'stack_v3pop' is implementad in nds32.md. */ |
3419 | /* The (const_int 14) means v3pop always pop { $fp $gp $lp }. */ | |
88437f39 CJW |
3420 | nds32_emit_stack_v3pop (Rb, Re, |
3421 | GEN_INT (14), GEN_INT (0)); | |
9304f876 | 3422 | } |
aa2642ef CJW |
3423 | |
3424 | /* Generate return instruction. */ | |
3425 | emit_jump_insn (gen_pop25return ()); | |
9304f876 CJW |
3426 | } |
3427 | ||
03390cda CJW |
3428 | /* Return nonzero if this function is known to have a null epilogue. |
3429 | This allows the optimizer to omit jumps to jumps if no stack | |
3430 | was created. */ | |
3431 | int | |
3432 | nds32_can_use_return_insn (void) | |
3433 | { | |
3434 | /* Prior to reloading, we can't tell how many registers must be saved. | |
3435 | Thus we can not determine whether this function has null epilogue. */ | |
3436 | if (!reload_completed) | |
3437 | return 0; | |
3438 | ||
3439 | /* If no stack was created, two conditions must be satisfied: | |
3440 | 1. This is a naked function. | |
3441 | So there is no callee-saved, local size, or outgoing size. | |
3442 | 2. This is NOT a variadic function. | |
3443 | So there is no pushing arguement registers into the stack. */ | |
3444 | return (cfun->machine->naked_p && (cfun->machine->va_args_size == 0)); | |
3445 | } | |
3446 | ||
9304f876 CJW |
3447 | /* ------------------------------------------------------------------------ */ |
3448 | ||
3449 | /* Function to test 333-form for load/store instructions. | |
3450 | This is auxiliary extern function for auxiliary macro in nds32.h. | |
3451 | Because it is a little complicated, we use function instead of macro. */ | |
3452 | bool | |
ef4bddc2 | 3453 | nds32_ls_333_p (rtx rt, rtx ra, rtx imm, machine_mode mode) |
9304f876 CJW |
3454 | { |
3455 | if (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS | |
3456 | && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS) | |
3457 | { | |
3458 | if (GET_MODE_SIZE (mode) == 4) | |
3459 | return satisfies_constraint_Iu05 (imm); | |
3460 | ||
3461 | if (GET_MODE_SIZE (mode) == 2) | |
3462 | return satisfies_constraint_Iu04 (imm); | |
3463 | ||
3464 | if (GET_MODE_SIZE (mode) == 1) | |
3465 | return satisfies_constraint_Iu03 (imm); | |
3466 | } | |
3467 | ||
3468 | return false; | |
3469 | } | |
3470 | ||
3471 | ||
9304f876 CJW |
3472 | /* Computing the Length of an Insn. |
3473 | Modifies the length assigned to instruction INSN. | |
3474 | LEN is the initially computed length of the insn. */ | |
3475 | int | |
ca009aee | 3476 | nds32_adjust_insn_length (rtx_insn *insn, int length) |
9304f876 CJW |
3477 | { |
3478 | rtx src, dst; | |
3479 | ||
3480 | switch (recog_memoized (insn)) | |
3481 | { | |
3482 | case CODE_FOR_move_df: | |
3483 | case CODE_FOR_move_di: | |
3484 | /* Adjust length of movd44 to 2. */ | |
3485 | src = XEXP (PATTERN (insn), 1); | |
3486 | dst = XEXP (PATTERN (insn), 0); | |
3487 | ||
3488 | if (REG_P (src) | |
3489 | && REG_P (dst) | |
3490 | && (REGNO (src) % 2) == 0 | |
3491 | && (REGNO (dst) % 2) == 0) | |
3492 | length = 2; | |
3493 | break; | |
3494 | ||
3495 | default: | |
3496 | break; | |
3497 | } | |
3498 | ||
3499 | return length; | |
3500 | } | |
3501 | ||
3502 | ||
9304f876 CJW |
3503 | /* Return align 2 (log base 2) if the next instruction of LABEL is 4 byte. */ |
3504 | int | |
82082f65 | 3505 | nds32_target_alignment (rtx_insn *label) |
9304f876 | 3506 | { |
84034c69 | 3507 | rtx_insn *insn; |
9304f876 CJW |
3508 | |
3509 | if (optimize_size) | |
3510 | return 0; | |
3511 | ||
3512 | insn = next_active_insn (label); | |
3513 | ||
3514 | if (insn == 0) | |
3515 | return 0; | |
3516 | else if ((get_attr_length (insn) % 4) == 0) | |
3517 | return 2; | |
3518 | else | |
3519 | return 0; | |
3520 | } | |
3521 | ||
3522 | /* ------------------------------------------------------------------------ */ | |
3523 | ||
3524 | /* PART 5: Initialize target hook structure and definitions. */ | |
3525 | \f | |
3526 | /* Controlling the Compilation Driver. */ | |
3527 | ||
3528 | \f | |
3529 | /* Run-time Target Specification. */ | |
3530 | ||
3531 | \f | |
3532 | /* Defining Data Structures for Per-function Information. */ | |
3533 | ||
3534 | \f | |
3535 | /* Storage Layout. */ | |
3536 | ||
3537 | #undef TARGET_PROMOTE_FUNCTION_MODE | |
3538 | #define TARGET_PROMOTE_FUNCTION_MODE \ | |
3539 | default_promote_function_mode_always_promote | |
3540 | ||
3541 | \f | |
3542 | /* Layout of Source Language Data Types. */ | |
3543 | ||
3544 | \f | |
3545 | /* Register Usage. */ | |
3546 | ||
3547 | /* -- Basic Characteristics of Registers. */ | |
3548 | ||
3549 | /* -- Order of Allocation of Registers. */ | |
3550 | ||
3551 | /* -- How Values Fit in Registers. */ | |
3552 | ||
3553 | /* -- Handling Leaf Functions. */ | |
3554 | ||
3555 | /* -- Registers That Form a Stack. */ | |
3556 | ||
3557 | \f | |
3558 | /* Register Classes. */ | |
3559 | ||
3560 | #undef TARGET_CLASS_MAX_NREGS | |
3561 | #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs | |
3562 | ||
9304f876 CJW |
3563 | #undef TARGET_REGISTER_PRIORITY |
3564 | #define TARGET_REGISTER_PRIORITY nds32_register_priority | |
3565 | ||
3566 | \f | |
3567 | /* Obsolete Macros for Defining Constraints. */ | |
3568 | ||
3569 | \f | |
3570 | /* Stack Layout and Calling Conventions. */ | |
3571 | ||
3572 | /* -- Basic Stack Layout. */ | |
3573 | ||
3574 | /* -- Exception Handling Support. */ | |
3575 | ||
3576 | /* -- Specifying How Stack Checking is Done. */ | |
3577 | ||
3578 | /* -- Registers That Address the Stack Frame. */ | |
3579 | ||
3580 | /* -- Eliminating Frame Pointer and Arg Pointer. */ | |
3581 | ||
3582 | #undef TARGET_CAN_ELIMINATE | |
3583 | #define TARGET_CAN_ELIMINATE nds32_can_eliminate | |
3584 | ||
3585 | /* -- Passing Function Arguments on the Stack. */ | |
3586 | ||
3587 | /* -- Passing Arguments in Registers. */ | |
3588 | ||
3589 | #undef TARGET_FUNCTION_ARG | |
3590 | #define TARGET_FUNCTION_ARG nds32_function_arg | |
3591 | ||
d40f3c40 CJW |
3592 | #undef TARGET_MUST_PASS_IN_STACK |
3593 | #define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack | |
3594 | ||
650fc469 CJW |
3595 | #undef TARGET_ARG_PARTIAL_BYTES |
3596 | #define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes | |
3597 | ||
9304f876 CJW |
3598 | #undef TARGET_FUNCTION_ARG_ADVANCE |
3599 | #define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance | |
3600 | ||
3601 | #undef TARGET_FUNCTION_ARG_BOUNDARY | |
3602 | #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary | |
3603 | ||
3604 | /* -- How Scalar Function Values Are Returned. */ | |
3605 | ||
3606 | #undef TARGET_FUNCTION_VALUE | |
3607 | #define TARGET_FUNCTION_VALUE nds32_function_value | |
3608 | ||
3609 | #undef TARGET_LIBCALL_VALUE | |
3610 | #define TARGET_LIBCALL_VALUE nds32_libcall_value | |
3611 | ||
3612 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
3613 | #define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p | |
3614 | ||
3615 | /* -- How Large Values Are Returned. */ | |
3616 | ||
3617 | /* -- Caller-Saves Register Allocation. */ | |
3618 | ||
3619 | /* -- Function Entry and Exit. */ | |
3620 | ||
3621 | #undef TARGET_ASM_FUNCTION_PROLOGUE | |
3622 | #define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue | |
3623 | ||
3624 | #undef TARGET_ASM_FUNCTION_END_PROLOGUE | |
3625 | #define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue | |
3626 | ||
3627 | #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE | |
3628 | #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue | |
3629 | ||
3630 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
3631 | #define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue | |
3632 | ||
3633 | #undef TARGET_ASM_OUTPUT_MI_THUNK | |
3634 | #define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk | |
3635 | ||
3636 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
3637 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
3638 | ||
3639 | /* -- Generating Code for Profiling. */ | |
3640 | ||
3641 | /* -- Permitting tail calls. */ | |
3642 | ||
3643 | #undef TARGET_WARN_FUNC_RETURN | |
3644 | #define TARGET_WARN_FUNC_RETURN nds32_warn_func_return | |
3645 | ||
3646 | /* Stack smashing protection. */ | |
3647 | ||
3648 | \f | |
3649 | /* Implementing the Varargs Macros. */ | |
3650 | ||
d4a6a4d9 CJW |
3651 | #undef TARGET_SETUP_INCOMING_VARARGS |
3652 | #define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs | |
3653 | ||
9304f876 CJW |
3654 | #undef TARGET_STRICT_ARGUMENT_NAMING |
3655 | #define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming | |
3656 | ||
3657 | \f | |
3658 | /* Trampolines for Nested Functions. */ | |
3659 | ||
3660 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE | |
3661 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template | |
3662 | ||
3663 | #undef TARGET_TRAMPOLINE_INIT | |
3664 | #define TARGET_TRAMPOLINE_INIT nds32_trampoline_init | |
3665 | ||
3666 | \f | |
3667 | /* Implicit Calls to Library Routines. */ | |
3668 | ||
3669 | \f | |
3670 | /* Addressing Modes. */ | |
3671 | ||
3672 | #undef TARGET_LEGITIMATE_ADDRESS_P | |
3673 | #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p | |
3674 | ||
3675 | \f | |
3676 | /* Anchored Addresses. */ | |
3677 | ||
3678 | \f | |
3679 | /* Condition Code Status. */ | |
3680 | ||
3681 | /* -- Representation of condition codes using (cc0). */ | |
3682 | ||
3683 | /* -- Representation of condition codes using registers. */ | |
3684 | ||
3685 | /* -- Macros to control conditional execution. */ | |
3686 | ||
3687 | \f | |
3688 | /* Describing Relative Costs of Operations. */ | |
3689 | ||
3690 | #undef TARGET_REGISTER_MOVE_COST | |
3691 | #define TARGET_REGISTER_MOVE_COST nds32_register_move_cost | |
3692 | ||
3693 | #undef TARGET_MEMORY_MOVE_COST | |
3694 | #define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost | |
3695 | ||
3696 | #undef TARGET_RTX_COSTS | |
3697 | #define TARGET_RTX_COSTS nds32_rtx_costs | |
3698 | ||
3699 | #undef TARGET_ADDRESS_COST | |
3700 | #define TARGET_ADDRESS_COST nds32_address_cost | |
3701 | ||
3702 | \f | |
3703 | /* Adjusting the Instruction Scheduler. */ | |
3704 | ||
3705 | \f | |
3706 | /* Dividing the Output into Sections (Texts, Data, . . . ). */ | |
3707 | ||
511a41d7 CJW |
3708 | #undef TARGET_ENCODE_SECTION_INFO |
3709 | #define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info | |
3710 | ||
9304f876 CJW |
3711 | \f |
3712 | /* Position Independent Code. */ | |
3713 | ||
3714 | \f | |
3715 | /* Defining the Output Assembler Language. */ | |
3716 | ||
3717 | /* -- The Overall Framework of an Assembler File. */ | |
3718 | ||
3719 | #undef TARGET_ASM_FILE_START | |
3720 | #define TARGET_ASM_FILE_START nds32_asm_file_start | |
3721 | #undef TARGET_ASM_FILE_END | |
3722 | #define TARGET_ASM_FILE_END nds32_asm_file_end | |
3723 | ||
3724 | /* -- Output of Data. */ | |
3725 | ||
3726 | #undef TARGET_ASM_ALIGNED_HI_OP | |
3727 | #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" | |
3728 | ||
3729 | #undef TARGET_ASM_ALIGNED_SI_OP | |
3730 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
3731 | ||
3732 | /* -- Output of Uninitialized Variables. */ | |
3733 | ||
3734 | /* -- Output and Generation of Labels. */ | |
3735 | ||
3736 | #undef TARGET_ASM_GLOBALIZE_LABEL | |
3737 | #define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label | |
3738 | ||
3739 | /* -- How Initialization Functions Are Handled. */ | |
3740 | ||
3741 | /* -- Macros Controlling Initialization Routines. */ | |
3742 | ||
3743 | /* -- Output of Assembler Instructions. */ | |
3744 | ||
3745 | #undef TARGET_PRINT_OPERAND | |
3746 | #define TARGET_PRINT_OPERAND nds32_print_operand | |
3747 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
3748 | #define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address | |
3749 | ||
3750 | /* -- Output of Dispatch Tables. */ | |
3751 | ||
3752 | /* -- Assembler Commands for Exception Regions. */ | |
3753 | ||
3754 | /* -- Assembler Commands for Alignment. */ | |
3755 | ||
3756 | \f | |
3757 | /* Controlling Debugging Information Format. */ | |
3758 | ||
3759 | /* -- Macros Affecting All Debugging Formats. */ | |
3760 | ||
3761 | /* -- Specific Options for DBX Output. */ | |
3762 | ||
3763 | /* -- Open-Ended Hooks for DBX Format. */ | |
3764 | ||
3765 | /* -- File Names in DBX Format. */ | |
3766 | ||
3767 | /* -- Macros for SDB and DWARF Output. */ | |
3768 | ||
3769 | /* -- Macros for VMS Debug Format. */ | |
3770 | ||
3771 | \f | |
3772 | /* Cross Compilation and Floating Point. */ | |
3773 | ||
3774 | \f | |
3775 | /* Mode Switching Instructions. */ | |
3776 | ||
3777 | \f | |
3778 | /* Defining target-specific uses of __attribute__. */ | |
3779 | ||
3780 | #undef TARGET_ATTRIBUTE_TABLE | |
3781 | #define TARGET_ATTRIBUTE_TABLE nds32_attribute_table | |
3782 | ||
3783 | #undef TARGET_MERGE_DECL_ATTRIBUTES | |
3784 | #define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes | |
3785 | ||
3786 | #undef TARGET_INSERT_ATTRIBUTES | |
3787 | #define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes | |
3788 | ||
3789 | #undef TARGET_OPTION_PRAGMA_PARSE | |
3790 | #define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse | |
3791 | ||
3792 | #undef TARGET_OPTION_OVERRIDE | |
3793 | #define TARGET_OPTION_OVERRIDE nds32_option_override | |
3794 | ||
3795 | \f | |
3796 | /* Emulating TLS. */ | |
3797 | ||
3798 | \f | |
3799 | /* Defining coprocessor specifics for MIPS targets. */ | |
3800 | ||
3801 | \f | |
3802 | /* Parameters for Precompiled Header Validity Checking. */ | |
3803 | ||
3804 | \f | |
3805 | /* C++ ABI parameters. */ | |
3806 | ||
3807 | \f | |
3808 | /* Adding support for named address spaces. */ | |
3809 | ||
3810 | \f | |
3811 | /* Miscellaneous Parameters. */ | |
3812 | ||
3813 | #undef TARGET_INIT_BUILTINS | |
3814 | #define TARGET_INIT_BUILTINS nds32_init_builtins | |
3815 | ||
3816 | #undef TARGET_EXPAND_BUILTIN | |
3817 | #define TARGET_EXPAND_BUILTIN nds32_expand_builtin | |
3818 | ||
3819 | \f | |
3820 | /* ------------------------------------------------------------------------ */ | |
3821 | ||
3822 | /* Initialize the GCC target structure. */ | |
3823 | ||
3824 | struct gcc_target targetm = TARGET_INITIALIZER; | |
3825 | ||
3826 | /* ------------------------------------------------------------------------ */ |