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[NDS32] Clean up nds32.h.
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9304f876 1/* Definitions of target machine of Andes NDS32 cpu for GNU compiler
85ec4feb 2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
9304f876
CJW		 3 Contributed by Andes Technology Corporation.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21
22/* ------------------------------------------------------------------------ */
23
24/* The following are auxiliary macros or structure declarations
25 that are used all over the nds32.c and nds32.h. */
26
a5876228
CJW		 27#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
28 (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
29
511a41d7
CJW		 30/* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
31 It is used in nds32_encode_section_info() to store flag in symbol_ref
32 in case the symbol should be placed in .rodata section.
33 So that we can check it in nds32_legitimate_address_p(). */
34#define NDS32_SYMBOL_FLAG_RODATA \
35 (SYMBOL_FLAG_MACH_DEP << 0)
36#define NDS32_SYMBOL_REF_RODATA_P(x) \
37 ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
9304f876 38
6e9ca932
CJW		 39/* Classifies expand result for expand helper function. */
40enum nds32_expand_result_type
41{
42 EXPAND_DONE,
43 EXPAND_FAIL,
44 EXPAND_CREATE_TEMPLATE
45};
46
9304f876
CJW		 47/* Classifies address type to distinguish 16-bit/32-bit format. */
48enum nds32_16bit_address_type
49{
50 /* [reg]: 45 format address. */
51 ADDRESS_REG,
52 /* [lo_reg + imm3u]: 333 format address. */
53 ADDRESS_LO_REG_IMM3U,
54 /* post_inc [lo_reg + imm3u]: 333 format address. */
55 ADDRESS_POST_INC_LO_REG_IMM3U,
67e1eb3d
SC		 56 /* post_modify [lo_reg + imm3u]: 333 format address. */
57 ADDRESS_POST_MODIFY_LO_REG_IMM3U,
8656bbcf
SC		 58 /* [$r8 + imm7u]: r8 imply address. */
59 ADDRESS_R8_IMM7U,
9304f876
CJW		 60 /* [$fp + imm7u]: fp imply address. */
61 ADDRESS_FP_IMM7U,
62 /* [$sp + imm7u]: sp imply address. */
63 ADDRESS_SP_IMM7U,
64 /* Other address format. */
65 ADDRESS_NOT_16BIT_FORMAT
66};
67
68
69/* ------------------------------------------------------------------------ */
70
71/* Define maximum numbers of registers for passing arguments. */
9d93cc24 72#define NDS32_MAX_GPR_REGS_FOR_ARGS 6
e2286268 73#define NDS32_MAX_FPR_REGS_FOR_ARGS 6
9304f876
CJW		 74
75/* Define the register number for first argument. */
76#define NDS32_GPR_ARG_FIRST_REGNUM 0
e2286268 77#define NDS32_FPR_ARG_FIRST_REGNUM 34
9304f876
CJW		 78
79/* Define the register number for return value. */
80#define NDS32_GPR_RET_FIRST_REGNUM 0
e2286268 81#define NDS32_FPR_RET_FIRST_REGNUM 34
9304f876 82
9d93cc24
CJW		 83/* Define the first integer register number. */
84#define NDS32_FIRST_GPR_REGNUM 0
85/* Define the last integer register number. */
86#define NDS32_LAST_GPR_REGNUM 31
9304f876 87
a6c7e777
MC		 88#define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6
89#define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \
90 (TARGET_REDUCED_REGS ? 10 : 14)
91
e2286268
MC		 92/* Define the floating-point number of registers. */
93#define NDS32_FLOAT_REGISTER_NUMBER \
94 (((nds32_fp_regnum == NDS32_CONFIG_FPU_0) \
95 || (nds32_fp_regnum == NDS32_CONFIG_FPU_4)) ? 8 \
96 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_1) \
97 || (nds32_fp_regnum == NDS32_CONFIG_FPU_5)) ? 16 \
98 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_2) \
99 || (nds32_fp_regnum == NDS32_CONFIG_FPU_6)) ? 32 \
100 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_3) \
101 || (nds32_fp_regnum == NDS32_CONFIG_FPU_7)) ? 64 \
102 : 32)
103
104#define NDS32_EXT_FPU_DOT_E (nds32_fp_regnum >= 4)
105
106/* Define the first floating-point register number. */
107#define NDS32_FIRST_FPR_REGNUM 34
108/* Define the last floating-point register number. */
109#define NDS32_LAST_FPR_REGNUM \
110 (NDS32_FIRST_FPR_REGNUM + NDS32_FLOAT_REGISTER_NUMBER - 1)
111
112
113#define NDS32_IS_EXT_FPR_REGNUM(regno) \
114 (((regno) >= NDS32_FIRST_FPR_REGNUM + 32) \
115 && ((regno) < NDS32_FIRST_FPR_REGNUM + 64))
116
117#define NDS32_IS_FPR_REGNUM(regno) \
118 (((regno) >= NDS32_FIRST_FPR_REGNUM) \
119 && ((regno) <= NDS32_LAST_FPR_REGNUM))
120
121#define NDS32_FPR_REGNO_OK_FOR_SINGLE(regno) \
122 ((regno) <= NDS32_LAST_FPR_REGNUM)
123
124#define NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) \
125 ((((regno) - NDS32_FIRST_FPR_REGNUM) & 1) == 0)
126
127#define NDS32_IS_GPR_REGNUM(regno) \
128 (((regno) <= NDS32_LAST_GPR_REGNUM))
129
9304f876
CJW		 130/* Define double word alignment bits. */
131#define NDS32_DOUBLE_WORD_ALIGNMENT 64
132
133/* Define alignment checking macros for convenience. */
134#define NDS32_HALF_WORD_ALIGN_P(value) (((value) & 0x01) == 0)
135#define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
136#define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
137
634bdae9
CJW		 138/* Get alignment according to mode or type information.
139 When 'type' is nonnull, there is no need to look at 'mode'. */
140#define NDS32_MODE_TYPE_ALIGN(mode, type) \
141 (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
142
9304f876
CJW		 143/* Round X up to the nearest double word. */
144#define NDS32_ROUND_UP_DOUBLE_WORD(value) (((value) + 7) & ~7)
145
146
147/* This macro is used to calculate the numbers of registers for
148 containing 'size' bytes of the argument.
149 The size of a register is a word in nds32 target.
150 So we use UNITS_PER_WORD to do the calculation. */
151#define NDS32_NEED_N_REGS_FOR_ARG(mode, type) \
152 ((mode == BLKmode) \
153 ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
154 : ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
155
156/* This macro is used to return the register number for passing argument.
157 We need to obey the following rules:
158 1. If it is required MORE THAN one register,
8a498f99
CJW		 159 we need to further check if it really needs to be
160 aligned on double words.
161 a) If double word alignment is necessary,
162 the register number must be even value.
163 b) Otherwise, the register number can be odd or even value.
9304f876 164 2. If it is required ONLY one register,
8a498f99
CJW		 165 the register number can be odd or even value. */
166#define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
167 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
168 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
169 ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
170 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
9304f876
CJW		 171 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
172
e2286268
MC		 173#define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \
174 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
175 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
176 ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1) \
177 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM)) \
178 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
179
180/* These two macros are to check if there are still available registers
7f6cd86b
CJW		 181 for passing argument, which must be entirely in registers. */
182#define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \
183 ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
184 + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \
185 <= (NDS32_GPR_ARG_FIRST_REGNUM \
186 + NDS32_MAX_GPR_REGS_FOR_ARGS))
187
e2286268
MC		 188#define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type) \
189 ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
190 + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \
191 <= (NDS32_FPR_ARG_FIRST_REGNUM \
192 + NDS32_MAX_FPR_REGS_FOR_ARGS))
193
194/* These two macros are to check if there are still available registers
7f6cd86b
CJW		 195 for passing argument, either entirely in registers or partially
196 in registers. */
197#define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
198 (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
199 < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
9304f876 200
e2286268
MC		 201#define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \
202 (NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
203 < NDS32_FPR_ARG_FIRST_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS)
204
9304f876
CJW		 205/* This macro is to check if the register is required to be saved on stack.
206 If call_used_regs[regno] == 0, regno is the callee-saved register.
207 If df_regs_ever_live_p(regno) == true, it is used in the current function.
208 As long as the register satisfies both criteria above,
209 it is required to be saved. */
210#define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \
211 ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
212
a6c7e777
MC		 213/* This macro is to check if the push25/pop25 are available to be used
214 for code generation. Because pop25 also performs return behavior,
215 the instructions may not be available for some cases.
216 If we want to use push25/pop25, all the following conditions must
217 be satisfied:
218 1. TARGET_V3PUSH is set.
219 2. Current function is not an ISR function.
220 3. Current function is not a variadic function.*/
221#define NDS32_V3PUSH_AVAILABLE_P \
222 (TARGET_V3PUSH \
223 && !nds32_isr_function_p (current_function_decl) \
224 && (cfun->machine->va_args_size == 0))
225
9304f876
CJW		 226/* ------------------------------------------------------------------------ */
227
228/* A C structure for machine-specific, per-function data.
229 This is added to the cfun structure. */
230struct GTY(()) machine_function
231{
232 /* Number of bytes allocated on the stack for variadic args
233 if we want to push them into stack as pretend arguments by ourself. */
234 int va_args_size;
235 /* Number of bytes reserved on the stack for
236 local and temporary variables. */
237 int local_size;
238 /* Number of bytes allocated on the stack for outgoing arguments. */
239 int out_args_size;
240
241 /* Number of bytes on the stack for saving $fp. */
242 int fp_size;
243 /* Number of bytes on the stack for saving $gp. */
244 int gp_size;
245 /* Number of bytes on the stack for saving $lp. */
246 int lp_size;
247
c457f751
CJW		 248 /* Number of bytes on the stack for saving general purpose
249 callee-saved registers. */
250 int callee_saved_gpr_regs_size;
251
e2286268
MC		 252 /* Number of bytes on the stack for saving floating-point
253 callee-saved registers. */
254 int callee_saved_fpr_regs_size;
255
9304f876 256 /* The padding bytes in callee-saved area may be required. */
c457f751 257 int callee_saved_area_gpr_padding_bytes;
9304f876 258
c457f751
CJW		 259 /* The first required general purpose callee-saved register. */
260 int callee_saved_first_gpr_regno;
261 /* The last required general purpose callee-saved register. */
262 int callee_saved_last_gpr_regno;
9304f876 263
e2286268
MC		 264 /* The first required floating-point callee-saved register. */
265 int callee_saved_first_fpr_regno;
266 /* The last required floating-point callee-saved register. */
267 int callee_saved_last_fpr_regno;
268
dd1536a7
CJW		 269 /* The padding bytes in varargs area may be required. */
270 int va_args_area_padding_bytes;
271
272 /* The first required register that should be saved on stack for va_args. */
273 int va_args_first_regno;
274 /* The last required register that should be saved on stack for va_args. */
275 int va_args_last_regno;
276
9304f876
CJW		 277 /* Indicate that whether this function needs
278 prologue/epilogue code generation. */
279 int naked_p;
280 /* Indicate that whether this function
281 uses fp_as_gp optimization. */
282 int fp_as_gp_p;
283};
284
285/* A C structure that contains the arguments information. */
286typedef struct
287{
9d93cc24 288 unsigned int gpr_offset;
e2286268 289 unsigned int fpr_offset;
9304f876
CJW		 290} nds32_cumulative_args;
291
292/* ------------------------------------------------------------------------ */
293
294/* The following we define C-ISR related stuff.
295 In nds32 architecture, we have 73 vectors for interrupt/exception.
296 For each vector (except for vector 0, which is used for reset behavior),
297 we allow users to set its register saving scheme and interrupt level. */
298
299/* There are 73 vectors in nds32 architecture.
300 0 for reset handler,
301 1-8 for exception handler,
302 and 9-72 for interrupt handler.
303 We use an array, which is defined in nds32.c, to record
304 essential information for each vector. */
305#define NDS32_N_ISR_VECTORS 73
306
307/* Define possible isr category. */
308enum nds32_isr_category
309{
310 NDS32_ISR_NONE,
311 NDS32_ISR_INTERRUPT,
312 NDS32_ISR_EXCEPTION,
313 NDS32_ISR_RESET
314};
315
316/* Define isr register saving scheme. */
317enum nds32_isr_save_reg
318{
319 NDS32_SAVE_ALL,
320 NDS32_PARTIAL_SAVE
321};
322
323/* Define isr nested type. */
324enum nds32_isr_nested_type
325{
326 NDS32_NESTED,
327 NDS32_NOT_NESTED,
328 NDS32_NESTED_READY
329};
330
331/* Define structure to record isr information.
332 The isr vector array 'isr_vectors[]' with this structure
333 is defined in nds32.c. */
334struct nds32_isr_info
335{
336 /* The field to identify isr category.
337 It should be set to NDS32_ISR_NONE by default.
338 If user specifies a function as isr by using attribute,
339 this field will be set accordingly. */
340 enum nds32_isr_category category;
341
342 /* A string for the applied function name.
343 It should be set to empty string by default. */
344 char func_name[100];
345
346 /* The register saving scheme.
347 It should be set to NDS32_PARTIAL_SAVE by default
348 unless user specifies attribute to change it. */
349 enum nds32_isr_save_reg save_reg;
350
351 /* The nested type.
352 It should be set to NDS32_NOT_NESTED by default
353 unless user specifies attribute to change it. */
354 enum nds32_isr_nested_type nested_type;
355
356 /* Total vectors.
357 The total vectors = interrupt + exception numbers + reset.
358 It should be set to 0 by default.
359 This field is ONLY used in NDS32_ISR_RESET category. */
360 unsigned int total_n_vectors;
361
362 /* A string for nmi handler name.
363 It should be set to empty string by default.
364 This field is ONLY used in NDS32_ISR_RESET category. */
365 char nmi_name[100];
366
367 /* A string for warm handler name.
368 It should be set to empty string by default.
369 This field is ONLY used in NDS32_ISR_RESET category. */
370 char warm_name[100];
371};
372
373/* ------------------------------------------------------------------------ */
374
375/* Define code for all nds32 builtins. */
376enum nds32_builtins
377{
378 NDS32_BUILTIN_ISYNC,
379 NDS32_BUILTIN_ISB,
154e3ea6
MC		 380 NDS32_BUILTIN_DSB,
381 NDS32_BUILTIN_MSYNC_ALL,
382 NDS32_BUILTIN_MSYNC_STORE,
9304f876
CJW		 383 NDS32_BUILTIN_MFSR,
384 NDS32_BUILTIN_MFUSR,
385 NDS32_BUILTIN_MTSR,
154e3ea6
MC		 386 NDS32_BUILTIN_MTSR_ISB,
387 NDS32_BUILTIN_MTSR_DSB,
9304f876
CJW		 388 NDS32_BUILTIN_MTUSR,
389 NDS32_BUILTIN_SETGIE_EN,
7a12ea32 390 NDS32_BUILTIN_SETGIE_DIS,
0bb4423d
MC		 391 NDS32_BUILTIN_FMFCFG,
392 NDS32_BUILTIN_FMFCSR,
393 NDS32_BUILTIN_FMTCSR,
394 NDS32_BUILTIN_FCPYNSS,
395 NDS32_BUILTIN_FCPYSS,
396 NDS32_BUILTIN_FCPYNSD,
397 NDS32_BUILTIN_FCPYSD,
2feae6cd
MC		 398 NDS32_BUILTIN_ABS,
399 NDS32_BUILTIN_AVE,
400 NDS32_BUILTIN_BCLR,
401 NDS32_BUILTIN_BSET,
402 NDS32_BUILTIN_BTGL,
403 NDS32_BUILTIN_BTST,
404 NDS32_BUILTIN_CLIP,
405 NDS32_BUILTIN_CLIPS,
406 NDS32_BUILTIN_CLZ,
407 NDS32_BUILTIN_CLO,
408 NDS32_BUILTIN_MAX,
409 NDS32_BUILTIN_MIN,
410 NDS32_BUILTIN_PBSAD,
411 NDS32_BUILTIN_PBSADA,
412 NDS32_BUILTIN_BSE,
413 NDS32_BUILTIN_BSP,
3999578c
MC		 414 NDS32_BUILTIN_FFB,
415 NDS32_BUILTIN_FFMISM,
416 NDS32_BUILTIN_FLMISM,
2feae6cd
MC		 417
418 NDS32_BUILTIN_ROTR,
419 NDS32_BUILTIN_SVA,
420 NDS32_BUILTIN_SVS,
421 NDS32_BUILTIN_WSBH,
422 NDS32_BUILTIN_JR_ITOFF,
423 NDS32_BUILTIN_JR_TOFF,
424 NDS32_BUILTIN_JRAL_ITON,
425 NDS32_BUILTIN_JRAL_TON,
426 NDS32_BUILTIN_RET_ITOFF,
427 NDS32_BUILTIN_RET_TOFF,
428 NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT,
429 NDS32_BUILTIN_STANDBY_WAKE_GRANT,
430 NDS32_BUILTIN_STANDBY_WAKE_DONE,
431 NDS32_BUILTIN_TEQZ,
432 NDS32_BUILTIN_TNEZ,
433 NDS32_BUILTIN_TRAP,
434 NDS32_BUILTIN_SETEND_BIG,
435 NDS32_BUILTIN_SETEND_LITTLE,
436 NDS32_BUILTIN_SYSCALL,
437 NDS32_BUILTIN_BREAK,
438 NDS32_BUILTIN_NOP,
439 NDS32_BUILTIN_SCHE_BARRIER,
440 NDS32_BUILTIN_GET_CURRENT_SP,
441 NDS32_BUILTIN_SET_CURRENT_SP,
442 NDS32_BUILTIN_RETURN_ADDRESS,
154e3ea6
MC		 443 NDS32_BUILTIN_LLW,
444 NDS32_BUILTIN_LWUP,
445 NDS32_BUILTIN_LBUP,
446 NDS32_BUILTIN_SCW,
447 NDS32_BUILTIN_SWUP,
448 NDS32_BUILTIN_SBUP,
f1a0afe2
MC		 449 NDS32_BUILTIN_CCTL_VA_LCK,
450 NDS32_BUILTIN_CCTL_IDX_WBINVAL,
451 NDS32_BUILTIN_CCTL_VA_WBINVAL_L1,
452 NDS32_BUILTIN_CCTL_VA_WBINVAL_LA,
453 NDS32_BUILTIN_CCTL_IDX_READ,
454 NDS32_BUILTIN_CCTL_IDX_WRITE,
455 NDS32_BUILTIN_CCTL_L1D_INVALALL,
456 NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL,
457 NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL,
e576ddb5
KC		 458 NDS32_BUILTIN_UALOAD_HW,
459 NDS32_BUILTIN_UALOAD_W,
460 NDS32_BUILTIN_UALOAD_DW,
461 NDS32_BUILTIN_UASTORE_HW,
462 NDS32_BUILTIN_UASTORE_W,
463 NDS32_BUILTIN_UASTORE_DW,
7a12ea32 464 NDS32_BUILTIN_COUNT
9304f876
CJW		 465};
466
467/* ------------------------------------------------------------------------ */
468
469#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
e2286268
MC		 470
471#define TARGET_ISA_V3 \
472 (nds32_arch_option == ARCH_V3 \
473 || nds32_arch_option == ARCH_V3F \
474 || nds32_arch_option == ARCH_V3S)
9304f876
CJW		 475#define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M)
476
77b7a1ca
CJW		 477#define TARGET_CMODEL_SMALL \
478 (nds32_cmodel_option == CMODEL_SMALL)
479#define TARGET_CMODEL_MEDIUM \
480 (nds32_cmodel_option == CMODEL_MEDIUM)
481#define TARGET_CMODEL_LARGE \
482 (nds32_cmodel_option == CMODEL_LARGE)
483
484/* When -mcmodel=small or -mcmodel=medium,
485 compiler may generate gp-base instruction directly. */
486#define TARGET_GP_DIRECT \
487 (nds32_cmodel_option == CMODEL_SMALL\
488 || nds32_cmodel_option == CMODEL_MEDIUM)
489
d4a6a4d9 490
e2286268
MC		 491/* Run-time Target Specification. */
492#define TARGET_SOFT_FLOAT (nds32_abi == NDS32_ABI_V2)
493/* Use hardware floating point calling convention. */
494#define TARGET_HARD_FLOAT (nds32_abi == NDS32_ABI_V2_FP_PLUS)
495
496/* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI,
497 1 means hard ABI and using full floating-point instruction,
498 2 means hard ABI and only using single-precision floating-point
499 instruction */
500#if TARGET_ARCH_DEFAULT == 1
501# define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
502# define TARGET_DEFAULT_FPU_ISA MASK_FPU_DOUBLE | MASK_FPU_SINGLE
503# define TARGET_DEFAULT_FPU_FMA 0
504#else
505# if TARGET_ARCH_DEFAULT == 2
506# define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
507# define TARGET_DEFAULT_FPU_ISA MASK_FPU_SINGLE
508# define TARGET_DEFAULT_FPU_FMA 0
509# else
510# define TARGET_DEFAULT_ABI NDS32_ABI_V2
511# define TARGET_DEFAULT_FPU_ISA 0
512# define TARGET_DEFAULT_FPU_FMA 0
513# endif
514#endif
515
516#define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2
9304f876
CJW		 517/* ------------------------------------------------------------------------ */
518\f
519/* Controlling the Compilation Driver. */
520
521#define OPTION_DEFAULT_SPECS \
e2286268
MC		 522 {"arch", " %{!march=*:-march=%(VALUE)}" \
523 " %{march=v3f:%{!mfloat-abi=*:-mfloat-abi=hard}" \
524 " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}" \
525 " %{!mno-ext-fpu-dp:%{!mext-fpu-dp:-mext-fpu-dp}}}" \
526 " %{march=v3s:%{!mfloat-abi=*:-mfloat-abi=hard}" \
527 " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}}" }, \
528 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }
9304f876
CJW		 529
530#define CC1_SPEC \
531 ""
532
533#define ASM_SPEC \
e2286268
MC		 534 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
535 " %{march=*:-march=%*}" \
536 " %{mabi=*:-mabi=v%*}" \
537 " %{mconfig-fpu=*:-mfpu-freg=%*}" \
538 " %{mext-fpu-mac:-mmac}" \
539 " %{mno-ext-fpu-mac:-mno-mac}" \
540 " %{mext-fpu-sp:-mfpu-sp-ext}" \
541 " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \
542 " %{mext-fpu-dp:-mfpu-dp-ext}" \
543 " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}"
9304f876 544
2ca1ca65 545/* If user issues -mrelax, we need to pass '--relax' to linker. */
9304f876
CJW		 546#define LINK_SPEC \
547 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
2ca1ca65 548 " %{mrelax:--relax}"
9304f876
CJW		 549
550#define LIB_SPEC \
551 " -lc -lgloss"
552
553/* The option -mno-ctor-dtor can disable constructor/destructor feature
554 by applying different crt stuff. In the convention, crt0.o is the
555 startup file without constructor/destructor;
556 crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
557 startup files with constructor/destructor.
558 Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
559 by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
560 currently provided by GCC for nds32 target.
561
562 For nds32 target so far:
563 If -mno-ctor-dtor, we are going to link
564 "crt0.o [user objects]".
565 If general cases, we are going to link
566 "crt1.o crtbegin1.o [user objects] crtend1.o". */
567#define STARTFILE_SPEC \
568 " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
569 " %{!mno-ctor-dtor:crtbegin1.o%s}"
570#define ENDFILE_SPEC \
571 " %{!mno-ctor-dtor:crtend1.o%s}"
572
c9eb51a7
CJW		 573/* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
574 configure gcc with --target=nds32be-* setting.
575 Check gcc/config.gcc for more information. */
9304f876 576#ifdef TARGET_BIG_ENDIAN_DEFAULT
c9eb51a7 577# define NDS32_ENDIAN_DEFAULT "mbig-endian"
9304f876 578#else
c9eb51a7 579# define NDS32_ENDIAN_DEFAULT "mlittle-endian"
9304f876
CJW		 580#endif
581
c9eb51a7
CJW		 582/* Currently we only have elf toolchain,
583 where -mcmodel=medium is always the default. */
584#define NDS32_CMODEL_DEFAULT "mcmodel=medium"
585
586#define MULTILIB_DEFAULTS \
587 { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
588
9304f876
CJW		 589\f
590/* Run-time Target Specification. */
591
72b7e5e1
KC		 592#define TARGET_CPU_CPP_BUILTINS() \
593 nds32_cpu_cpp_builtins (pfile)
9304f876
CJW		 594
595\f
596/* Defining Data Structures for Per-function Information. */
597
598/* This macro is called once per function,
599 before generation of any RTL has begun. */
600#define INIT_EXPANDERS nds32_init_expanders ()
601
602\f
603/* Storage Layout. */
604
605#define BITS_BIG_ENDIAN 0
606
607#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
608
609#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
610
611#define UNITS_PER_WORD 4
612
613#define PROMOTE_MODE(m, unsignedp, type) \
614 if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
615 { \
616 (m) = SImode; \
617 }
618
619#define PARM_BOUNDARY 32
620
621#define STACK_BOUNDARY 64
622
623#define FUNCTION_BOUNDARY 32
624
625#define BIGGEST_ALIGNMENT 64
626
627#define EMPTY_FIELD_BOUNDARY 32
628
629#define STRUCTURE_SIZE_BOUNDARY 8
630
631#define STRICT_ALIGNMENT 1
632
633#define PCC_BITFIELD_TYPE_MATTERS 1
634
635\f
636/* Layout of Source Language Data Types. */
637
638#define INT_TYPE_SIZE 32
639#define SHORT_TYPE_SIZE 16
640#define LONG_TYPE_SIZE 32
641#define LONG_LONG_TYPE_SIZE 64
642
643#define FLOAT_TYPE_SIZE 32
644#define DOUBLE_TYPE_SIZE 64
645#define LONG_DOUBLE_TYPE_SIZE 64
646
647#define DEFAULT_SIGNED_CHAR 1
648
649#define SIZE_TYPE "long unsigned int"
650#define PTRDIFF_TYPE "long int"
7f983342
CJW		 651#define WCHAR_TYPE "unsigned int"
652#define WCHAR_TYPE_SIZE 32
9304f876
CJW		 653
654\f
655/* Register Usage. */
656
657/* Number of actual hardware registers.
658 The hardware registers are assigned numbers for the compiler
659 from 0 to just below FIRST_PSEUDO_REGISTER.
660 All registers that the compiler knows about must be given numbers,
661 even those that are not normally considered general registers. */
71d8eff1 662#define FIRST_PSEUDO_REGISTER 101
9304f876
CJW		 663
664/* An initializer that says which registers are used for fixed
665 purposes all throughout the compiled code and are therefore
666 not available for general allocation.
667
668 $r28 : $fp
669 $r29 : $gp
670 $r30 : $lp
671 $r31 : $sp
672
e2286268
MC		 673 caller-save registers: $r0 ~ $r5, $r16 ~ $r23, $fs0 ~ $fs5, $fs22 ~ $fs47
674 callee-save registers: $r6 ~ $r10, $r11 ~ $r14, $fs6 ~ $fs21, $fs48 ~ $fs63
9304f876
CJW		 675
676 reserved for assembler : $r15
677 reserved for other use : $r24, $r25, $r26, $r27 */
71d8eff1
CJW		 678#define FIXED_REGISTERS \
679{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
680 0, 0, 0, 0, 0, 0, 0, 0, \
681 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
682 0, 0, 0, 0, 0, 0, 0, 1, \
683 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
684 0, 0, 0, 0, 0, 0, 0, 0, \
685 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
686 1, 1, 1, 1, 0, 1, 0, 1, \
e2286268 687 /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \
71d8eff1 688 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 689 /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \
71d8eff1 690 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 691 /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
71d8eff1 692 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 693 /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
71d8eff1 694 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 695 /* fs30 fs31 fd16 fd17 fd18 */ \
71d8eff1 696 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 697 /* fd19 fd20 fd21 fd22 */ \
71d8eff1 698 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 699 /* fd23 fd24 fd25 fd26 */ \
71d8eff1 700 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 701 /* fd27 fd28 fd29 fd30 */ \
71d8eff1 702 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 703 /* fd31 Reserved..................... */ \
71d8eff1 704 1, 1, 1, 1, 1 \
9304f876
CJW		 705}
706
707/* Identifies the registers that are not available for
708 general allocation of values that must live across
709 function calls -- so they are caller-save registers.
710
711 0 : callee-save registers
712 1 : caller-save registers */
71d8eff1
CJW		 713#define CALL_USED_REGISTERS \
714{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
715 1, 1, 1, 1, 1, 1, 0, 0, \
716 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
717 0, 0, 0, 0, 0, 0, 0, 1, \
718 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
719 1, 1, 1, 1, 1, 1, 1, 1, \
720 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
721 1, 1, 1, 1, 0, 1, 0, 1, \
e2286268 722 /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \
71d8eff1 723 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 724 /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \
71d8eff1 725 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 726 /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
71d8eff1 727 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 728 /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
71d8eff1 729 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 730 /* fs30 fs31 fd16 fd17 fd18 */ \
71d8eff1 731 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 732 /* fd19 fd20 fd21 fd22 */ \
71d8eff1 733 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 734 /* fd23 fd24 fd25 fd26 */ \
71d8eff1 735 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 736 /* fd27 fd28 fd29 fd30 */ \
71d8eff1 737 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 738 /* fd31 Reserved..................... */ \
71d8eff1 739 1, 1, 1, 1, 1 \
9304f876
CJW		 740}
741
742/* In nds32 target, we have three levels of registers:
743 LOW_COST_REGS : $r0 ~ $r7
744 MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
745 HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */
71d8eff1
CJW		 746#define REG_ALLOC_ORDER \
747{ 0, 1, 2, 3, 4, 5, 6, 7, \
748 16, 17, 18, 19, 9, 10, 11, 12, \
749 13, 14, 8, 15, 20, 21, 22, 23, \
750 24, 25, 26, 27, 28, 29, 30, 31, \
751 32, 33, 34, 35, 36, 37, 38, 39, \
752 40, 41, 42, 43, 44, 45, 46, 47, \
753 48, 49, 50, 51, 52, 53, 54, 55, \
754 56, 57, 58, 59, 60, 61, 62, 63, \
755 64, 65, 66, 67, 68, 69, 70, 71, \
756 72, 73, 74, 75, 76, 77, 78, 79, \
757 80, 81, 82, 83, 84, 85, 86, 87, \
758 88, 89, 90, 91, 92, 93, 94, 95, \
759 96, 97, 98, 99, 100, \
9304f876
CJW		 760}
761
5e6ae0cc
CJW		 762/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
763 to be rearranged based on optimizing for speed or size. */
764#define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order ()
765
9304f876
CJW		 766/* Tell IRA to use the order we define rather than messing it up with its
767 own cost calculations. */
96092404 768#define HONOR_REG_ALLOC_ORDER optimize_size
9304f876 769
9304f876
CJW		 770\f
771/* Register Classes. */
772
773/* In nds32 target, we have three levels of registers:
774 Low cost regsiters : $r0 ~ $r7
775 Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
776 High cost registers : $r12 ~ $r14, $r20 ~ $r31
777
778 In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
779 so that it provides more chance to use low cost registers. */
780enum reg_class
781{
782 NO_REGS,
36f28760
CJW		 783 R5_REG,
784 R8_REG,
9304f876
CJW		 785 R15_TA_REG,
786 STACK_REG,
36f28760 787 FRAME_POINTER_REG,
9304f876
CJW		 788 LOW_REGS,
789 MIDDLE_REGS,
790 HIGH_REGS,
791 GENERAL_REGS,
792 FRAME_REGS,
e2286268 793 FP_REGS,
9304f876
CJW		 794 ALL_REGS,
795 LIM_REG_CLASSES
796};
797
798#define N_REG_CLASSES (int) LIM_REG_CLASSES
799
800#define REG_CLASS_NAMES \
801{ \
802 "NO_REGS", \
36f28760
CJW		 803 "R5_REG", \
804 "R8_REG", \
9304f876
CJW		 805 "R15_TA_REG", \
806 "STACK_REG", \
36f28760 807 "FRAME_POINTER_REG", \
9304f876
CJW		 808 "LOW_REGS", \
809 "MIDDLE_REGS", \
810 "HIGH_REGS", \
811 "GENERAL_REGS", \
812 "FRAME_REGS", \
e2286268 813 "FP_REGS", \
9304f876
CJW		 814 "ALL_REGS" \
815}
816
817#define REG_CLASS_CONTENTS \
71d8eff1
CJW		 818{ /* NO_REGS */ \
819 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
820 /* R5_REG : 5 */ \
821 {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
822 /* R8_REG : 8 */ \
823 {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
824 /* R15_TA_REG : 15 */ \
825 {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
826 /* STACK_REG : 31 */ \
827 {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
828 /* FRAME_POINTER_REG : 28 */ \
829 {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
830 /* LOW_REGS : 0-7 */ \
831 {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
832 /* MIDDLE_REGS : 0-11, 16-19 */ \
833 {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
834 /* HIGH_REGS : 12-14, 20-31 */ \
835 {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
836 /* GENERAL_REGS : 0-31 */ \
837 {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
838 /* FRAME_REGS : 32, 33 */ \
839 {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
e2286268
MC		 840 /* FP_REGS : 34-98 */ \
841 {0x00000000, 0xfffffffc, 0xffffffff, 0x00000003}, \
71d8eff1
CJW		 842 /* ALL_REGS : 0-100 */ \
843 {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f} \
9304f876
CJW		 844}
845
846#define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
847
848#define BASE_REG_CLASS GENERAL_REGS
849#define INDEX_REG_CLASS GENERAL_REGS
850
e2286268
MC		 851#define TEST_REGNO(R, TEST, VALUE) \
852 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
853
9304f876
CJW		 854/* Return nonzero if it is suitable for use as a
855 base register in operand addresses.
856 So far, we return nonzero only if "num" is a hard reg
857 of the suitable class or a pseudo register which is
858 allocated to a suitable hard reg. */
859#define REGNO_OK_FOR_BASE_P(num) \
e2286268
MC		 860 (TEST_REGNO (num, <, 32) \
861 || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
862 || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
9304f876
CJW		 863
864/* Return nonzero if it is suitable for use as a
865 index register in operand addresses.
866 So far, we return nonzero only if "num" is a hard reg
867 of the suitable class or a pseudo register which is
868 allocated to a suitable hard reg.
869 The difference between an index register and a base register is that
870 the index register may be scaled. */
871#define REGNO_OK_FOR_INDEX_P(num) \
e2286268
MC		 872 (TEST_REGNO (num, <, 32) \
873 || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
874 || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
9304f876
CJW		 875
876\f
877/* Obsolete Macros for Defining Constraints. */
878
879\f
880/* Stack Layout and Calling Conventions. */
881
62f9f30b 882#define STACK_GROWS_DOWNWARD 1
9304f876
CJW		 883
884#define FRAME_GROWS_DOWNWARD 1
885
9304f876
CJW		 886#define STACK_POINTER_OFFSET 0
887
4f44e960
CJW		 888#define FIRST_PARM_OFFSET(fundecl) \
889 (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
9304f876
CJW		 890
891#define RETURN_ADDR_RTX(count, frameaddr) \
892 nds32_return_addr_rtx (count, frameaddr)
893
894/* A C expression whose value is RTL representing the location
895 of the incoming return address at the beginning of any function
896 before the prologue.
897 If this RTL is REG, you should also define
898 DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO). */
899#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM)
900#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM)
901
e2286268
MC		 902#define DBX_REGISTER_NUMBER(REGNO) nds32_dbx_register_number (REGNO)
903
9304f876
CJW		 904#define STACK_POINTER_REGNUM SP_REGNUM
905
906#define FRAME_POINTER_REGNUM 33
907
908#define HARD_FRAME_POINTER_REGNUM FP_REGNUM
909
910#define ARG_POINTER_REGNUM 32
911
912#define STATIC_CHAIN_REGNUM 16
913
914#define ELIMINABLE_REGS \
915{ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
916 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
917 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
918 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
919
920#define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
921 (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
922
923#define ACCUMULATE_OUTGOING_ARGS 1
924
925#define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
926
927#define CUMULATIVE_ARGS nds32_cumulative_args
928
929#define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
930 nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
931
e2286268
MC		 932#define FUNCTION_ARG_REGNO_P(regno) \
933 (IN_RANGE ((regno), NDS32_FIRST_GPR_REGNUM, NDS32_MAX_GPR_REGS_FOR_ARGS - 1) \
934 || ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) \
935 && IN_RANGE ((regno), NDS32_FPR_ARG_FIRST_REGNUM, \
936 NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS - 1)))
9304f876
CJW		 937
938#define DEFAULT_PCC_STRUCT_RETURN 0
939
940/* EXIT_IGNORE_STACK should be nonzero if, when returning
941 from a function, the stack pointer does not matter.
942 The value is tested only in functions that have frame pointers.
943 In nds32 target, the function epilogue recovers the
944 stack pointer from the frame. */
945#define EXIT_IGNORE_STACK 1
946
947#define FUNCTION_PROFILER(file, labelno) \
9e362bd0
CJW		 948 fprintf (file, "/* profiler %d */\n", (labelno))
949
950#define PROFILE_HOOK(LABEL) \
951 { \
952 rtx fun, lp; \
953 lp = get_hard_reg_initial_val (Pmode, LP_REGNUM); \
954 fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \
955 emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode); \
956 }
9304f876
CJW		 957
958\f
959/* Implementing the Varargs Macros. */
960
961\f
962/* Trampolines for Nested Functions. */
963
964/* Giving A-function and B-function,
965 if B-function wants to call A-function's nested function,
966 we need to fill trampoline code into A-function's stack
967 so that B-function can execute the code in stack to indirectly
968 jump to (like 'trampoline' action) desired nested function.
969
970 The trampoline code for nds32 target must contains following parts:
971
972 1. instructions (4 * 4 = 16 bytes):
8a498f99
CJW		 973 get $pc first
974 load chain_value to static chain register via $pc
975 load nested function address to $r15 via $pc
976 jump to desired nested function via $r15
9304f876 977 2. data (4 * 2 = 8 bytes):
8a498f99
CJW		 978 chain_value
979 nested function address
9304f876
CJW		 980
981 Please check nds32.c implementation for more information. */
982#define TRAMPOLINE_SIZE 24
983
984/* Because all instructions/data in trampoline template are 4-byte size,
985 we set trampoline alignment 8*4=32 bits. */
986#define TRAMPOLINE_ALIGNMENT 32
987
988\f
989/* Implicit Calls to Library Routines. */
990
991\f
992/* Addressing Modes. */
993
994/* We can use "LWI.bi Rt, [Ra], 4" to support post increment. */
995#define HAVE_POST_INCREMENT 1
996/* We can use "LWI.bi Rt, [Ra], -4" to support post decrement. */
997#define HAVE_POST_DECREMENT 1
998
999/* We have "LWI.bi Rt, [Ra], imm" instruction form. */
1000#define HAVE_POST_MODIFY_DISP 1
1001/* We have "LW.bi Rt, [Ra], Rb" instruction form. */
1002#define HAVE_POST_MODIFY_REG 1
1003
1004#define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
1005
566f31a4 1006#define MAX_REGS_PER_ADDRESS 3
9304f876
CJW		 1007
1008\f
1009/* Anchored Addresses. */
1010
1011\f
1012/* Condition Code Status. */
1013
1014\f
1015/* Describing Relative Costs of Operations. */
1016
1017/* A C expression for the cost of a branch instruction.
1018 A value of 1 is the default;
1019 other values are interpreted relative to that. */
15c193e2 1020#define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1)
9304f876 1021
08ed6d29
CJW		 1022/* Override BRANCH_COST heuristic which empirically produces worse
1023 performance for removing short circuiting from the logical ops. */
1024#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1025
9304f876
CJW		 1026#define SLOW_BYTE_ACCESS 1
1027
1e8552c2 1028#define NO_FUNCTION_CSE 1
9304f876
CJW		 1029
1030\f
1031/* Adjusting the Instruction Scheduler. */
1032
1033\f
1034/* Dividing the Output into Sections (Texts, Data, . . . ). */
1035
1036#define TEXT_SECTION_ASM_OP "\t.text"
1037#define DATA_SECTION_ASM_OP "\t.data"
1038
1039/* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
1040 So we use '.section .bss' alternatively. */
1041#define BSS_SECTION_ASM_OP "\t.section\t.bss"
1042
1043/* Define this macro to be an expression with a nonzero value if jump tables
1044 (for tablejump insns) should be output in the text section,
1045 along with the assembler instructions.
1046 Otherwise, the readonly data section is used. */
1047#define JUMP_TABLES_IN_TEXT_SECTION 1
1048
1049\f
1050/* Position Independent Code. */
1051
64a08b7f
CJW		 1052#define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
1053
9304f876
CJW		 1054\f
1055/* Defining the Output Assembler Language. */
1056
1057#define ASM_COMMENT_START "!"
1058
1059#define ASM_APP_ON "! #APP"
1060
1061#define ASM_APP_OFF "! #NO_APP\n"
1062
1063#define ASM_OUTPUT_LABELREF(stream, name) \
1064 asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
1065
1066#define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
1067 assemble_name (stream, XSTR (sym, 0))
1068
1069#define ASM_OUTPUT_LABEL_REF(stream, buf) \
1070 assemble_name (stream, buf)
1071
1072#define LOCAL_LABEL_PREFIX "."
1073
71d8eff1
CJW		 1074#define REGISTER_NAMES \
1075{ "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
9304f876
CJW		 1076 "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \
1077 "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
1078 "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \
e2286268
MC		 1079 "$AP", "$SFP", "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", \
1080 "$fs6", "$fs7", "$fs8", "$fs9", "$fs10","$fs11","$fs12","$fs13",\
1081 "$fs14","$fs15","$fs16","$fs17","$fs18","$fs19","$fs20","$fs21",\
1082 "$fs22","$fs23","$fs24","$fs25","$fs26","$fs27","$fs28","$fs29",\
1083 "$fs30","$fs31","$fs32","$fs33","$fs34","$fs35","$fs36","$fs37",\
1084 "$fs38","$fs39","$fs40","$fs41","$fs42","$fs43","$fs44","$fs45",\
1085 "$fs46","$fs47","$fs48","$fs49","$fs50","$fs51","$fs52","$fs53",\
1086 "$fs54","$fs55","$fs56","$fs57","$fs58","$fs59","$fs60","$fs61",\
1087 "$fs62","$fs63", "LB", "LE", "LC" \
1088}
1089
1090#define ADDITIONAL_REGISTER_NAMES \
1091{ \
1092 {"$r15", 15}, \
1093 {"$r28", 28}, {"$r29", 29}, {"$r30", 30}, {"$r31", 31}, \
1094 {"$a0", 0}, {"$a1", 1}, {"$a2", 2}, \
1095 {"$a3", 3}, {"$a4", 4}, {"$a5", 5}, \
1096 {"$s0", 6}, {"$s1", 7}, {"$s2", 8}, {"$s3", 9}, \
1097 {"$s4", 10}, {"$s5", 11}, {"$s6", 12}, {"$s7", 13}, \
1098 {"$s8", 14}, \
1099 {"$t0", 16}, {"$t1", 17}, {"$t2", 18}, {"$t3", 19}, \
1100 {"$t4", 20}, {"$t5", 21}, {"$t6", 22}, {"$t7", 23}, \
1101 {"$t8", 24}, {"$t9", 25}, \
1102 {"$p0", 26}, {"$p1", 27}, \
1103 {"$h0", 0}, {"$h1", 1}, {"$h2", 2}, {"$h3", 3}, \
1104 {"$h4", 4}, {"$h5", 5}, {"$h6", 6}, {"$h7", 7}, \
1105 {"$h8", 8}, {"$h9", 9}, {"$h10", 10}, {"$h11", 11}, \
1106 {"$h12", 16}, {"$h13", 17}, {"$h14", 18}, {"$h15", 19}, \
1107 {"$o0", 0}, {"$o1", 1}, {"$o2", 2}, {"$o3", 3}, \
1108 {"$o4", 4}, {"$o5", 5}, {"$o6", 6}, {"$o7", 7}, \
1109}
1110
1111#define OVERLAPPING_REGISTER_NAMES \
1112{ \
1113 {"$fd0", NDS32_FIRST_FPR_REGNUM + 0, 2}, \
1114 {"$fd1", NDS32_FIRST_FPR_REGNUM + 2, 2}, \
1115 {"$fd2", NDS32_FIRST_FPR_REGNUM + 4, 2}, \
1116 {"$fd3", NDS32_FIRST_FPR_REGNUM + 6, 2}, \
1117 {"$fd4", NDS32_FIRST_FPR_REGNUM + 8, 2}, \
1118 {"$fd5", NDS32_FIRST_FPR_REGNUM + 10, 2}, \
1119 {"$fd6", NDS32_FIRST_FPR_REGNUM + 12, 2}, \
1120 {"$fd7", NDS32_FIRST_FPR_REGNUM + 14, 2}, \
1121 {"$fd8", NDS32_FIRST_FPR_REGNUM + 16, 2}, \
1122 {"$fd9", NDS32_FIRST_FPR_REGNUM + 18, 2}, \
1123 {"$fd10", NDS32_FIRST_FPR_REGNUM + 20, 2}, \
1124 {"$fd11", NDS32_FIRST_FPR_REGNUM + 22, 2}, \
1125 {"$fd12", NDS32_FIRST_FPR_REGNUM + 24, 2}, \
1126 {"$fd13", NDS32_FIRST_FPR_REGNUM + 26, 2}, \
1127 {"$fd14", NDS32_FIRST_FPR_REGNUM + 28, 2}, \
1128 {"$fd15", NDS32_FIRST_FPR_REGNUM + 30, 2}, \
1129 {"$fd16", NDS32_FIRST_FPR_REGNUM + 32, 2}, \
1130 {"$fd17", NDS32_FIRST_FPR_REGNUM + 34, 2}, \
1131 {"$fd18", NDS32_FIRST_FPR_REGNUM + 36, 2}, \
1132 {"$fd19", NDS32_FIRST_FPR_REGNUM + 38, 2}, \
1133 {"$fd20", NDS32_FIRST_FPR_REGNUM + 40, 2}, \
1134 {"$fd21", NDS32_FIRST_FPR_REGNUM + 42, 2}, \
1135 {"$fd22", NDS32_FIRST_FPR_REGNUM + 44, 2}, \
1136 {"$fd23", NDS32_FIRST_FPR_REGNUM + 46, 2}, \
1137 {"$fd24", NDS32_FIRST_FPR_REGNUM + 48, 2}, \
1138 {"$fd25", NDS32_FIRST_FPR_REGNUM + 50, 2}, \
1139 {"$fd26", NDS32_FIRST_FPR_REGNUM + 52, 2}, \
1140 {"$fd27", NDS32_FIRST_FPR_REGNUM + 54, 2}, \
1141 {"$fd28", NDS32_FIRST_FPR_REGNUM + 56, 2}, \
1142 {"$fd29", NDS32_FIRST_FPR_REGNUM + 58, 2}, \
1143 {"$fd30", NDS32_FIRST_FPR_REGNUM + 60, 2}, \
1144 {"$fd31", NDS32_FIRST_FPR_REGNUM + 62, 2}, \
9304f876
CJW		 1145}
1146
1147/* Output normal jump table entry. */
1148#define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
1149 asm_fprintf (stream, "\t.word\t%LL%d\n", value)
1150
1151/* Output pc relative jump table entry. */
1152#define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel) \
1153 do \
1154 { \
1155 switch (GET_MODE (body)) \
1156 { \
4e10a5a7 1157 case E_QImode: \
9304f876
CJW		 1158 asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \
1159 break; \
4e10a5a7 1160 case E_HImode: \
9304f876
CJW		 1161 asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \
1162 break; \
4e10a5a7 1163 case E_SImode: \
9304f876
CJW		 1164 asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \
1165 break; \
1166 default: \
1167 gcc_unreachable(); \
1168 } \
1169 } while (0)
1170
1171/* We have to undef it first because elfos.h formerly define it
1172 check gcc/config.gcc and gcc/config/elfos.h for more information. */
1173#undef ASM_OUTPUT_CASE_LABEL
1174#define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table) \
1175 do \
1176 { \
1177 asm_fprintf (stream, "\t! Jump Table Begin\n"); \
1178 (*targetm.asm_out.internal_label) (stream, prefix, num); \
1179 } while (0)
1180
1181#define ASM_OUTPUT_CASE_END(stream, num, table) \
1182 do \
1183 { \
1184 /* Because our jump table is in text section, \
8a498f99
CJW		 1185 we need to make sure 2-byte alignment after \
1186 the jump table for instructions fetch. */ \
9304f876 1187 if (GET_MODE (PATTERN (table)) == QImode) \
8a498f99 1188 ASM_OUTPUT_ALIGN (stream, 1); \
9304f876
CJW		 1189 asm_fprintf (stream, "\t! Jump Table End\n"); \
1190 } while (0)
1191
1192/* This macro is not documented yet.
1193 But we do need it to make jump table vector aligned. */
1194#define ADDR_VEC_ALIGN(JUMPTABLE) 2
1195
1196#define DWARF2_UNWIND_INFO 1
1197
1198#define JUMP_ALIGN(x) \
1199 (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
1200
1201#define LOOP_ALIGN(x) \
1202 (align_loops_log ? align_loops_log : nds32_target_alignment (x))
1203
1204#define LABEL_ALIGN(x) \
1205 (align_labels_log ? align_labels_log : nds32_target_alignment (x))
1206
1207#define ASM_OUTPUT_ALIGN(stream, power) \
1208 fprintf (stream, "\t.align\t%d\n", power)
1209
1210\f
1211/* Controlling Debugging Information Format. */
1212
1213#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1214
1215#define DWARF2_DEBUGGING_INFO 1
1216
1217#define DWARF2_ASM_LINE_DEBUG_INFO 1
1218
1219\f
1220/* Cross Compilation and Floating Point. */
1221
1222\f
1223/* Mode Switching Instructions. */
1224
1225\f
1226/* Defining target-specific uses of __attribute__. */
1227
1228\f
1229/* Emulating TLS. */
1230
1231\f
1232/* Defining coprocessor specifics for MIPS targets. */
1233
1234\f
1235/* Parameters for Precompiled Header Validity Checking. */
1236
1237\f
1238/* C++ ABI parameters. */
1239
1240\f
1241/* Adding support for named address spaces. */
1242
1243\f
1244/* Miscellaneous Parameters. */
1245
1246/* This is the machine mode that elements of a jump-table should have. */
1247#define CASE_VECTOR_MODE Pmode
1248
1249/* Return the preferred mode for and addr_diff_vec when the mininum
1250 and maximum offset are known. */
1251#define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \
1252 ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode \
1253 : (max_offset >= 100) ? HImode \
1254 : QImode)
1255
1256/* Generate pc relative jump table when -fpic or -Os. */
1257#define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1258
1259/* Define this macro if operations between registers with integral mode
1260 smaller than a word are always performed on the entire register. */
9e11bfef 1261#define WORD_REGISTER_OPERATIONS 1
9304f876
CJW		 1262
1263/* A C expression indicating when insns that read memory in mem_mode,
1264 an integral mode narrower than a word, set the bits outside of mem_mode
1265 to be either the sign-extension or the zero-extension of the data read. */
1266#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1267
1268/* The maximum number of bytes that a single instruction can move quickly
1269 between memory and registers or between two memory locations. */
1270#define MOVE_MAX 4
1271
1272/* A C expression that is nonzero if on this machine the number of bits
1273 actually used for the count of a shift operation is equal to the number
1274 of bits needed to represent the size of the object being shifted. */
1275#define SHIFT_COUNT_TRUNCATED 1
1276
9304f876
CJW		 1277/* A C expression describing the value returned by a comparison operator with
1278 an integral mode and stored by a store-flag instruction ('cstoremode4')
1279 when the condition is true. */
1280#define STORE_FLAG_VALUE 1
1281
24a71166
CJW		 1282/* A C expression that indicates whether the architecture defines a value for
1283 clz or ctz with a zero operand. In nds32 clz for 0 result 32 is defined
1284 in ISA spec */
1285#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
1286
9304f876
CJW		 1287/* An alias for the machine mode for pointers. */
1288#define Pmode SImode
1289
1290/* An alias for the machine mode used for memory references to functions
1291 being called, in call RTL expressions. */
1292#define FUNCTION_MODE SImode
1293
1294/* ------------------------------------------------------------------------ */
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