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9304f876 1/* Definitions of target machine of Andes NDS32 cpu for GNU compiler
85ec4feb 2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
9304f876
CJW		 3 Contributed by Andes Technology Corporation.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21
22/* ------------------------------------------------------------------------ */
23
24/* The following are auxiliary macros or structure declarations
25 that are used all over the nds32.c and nds32.h. */
26
a5876228
CJW		 27#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
28 (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
29
511a41d7
CJW		 30/* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
31 It is used in nds32_encode_section_info() to store flag in symbol_ref
32 in case the symbol should be placed in .rodata section.
33 So that we can check it in nds32_legitimate_address_p(). */
34#define NDS32_SYMBOL_FLAG_RODATA \
35 (SYMBOL_FLAG_MACH_DEP << 0)
36#define NDS32_SYMBOL_REF_RODATA_P(x) \
37 ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
9304f876 38
b26fa4f9
KLC		 39enum nds32_relax_insn_type
40{
41 RELAX_ORI,
42 RELAX_PLT_ADD,
43 RELAX_TLS_ADD_or_LW,
44 RELAX_TLS_ADD_LW,
45 RELAX_TLS_LW_JRAL,
46 RELAX_DONE
47};
48
6e9ca932
CJW		 49/* Classifies expand result for expand helper function. */
50enum nds32_expand_result_type
51{
52 EXPAND_DONE,
53 EXPAND_FAIL,
54 EXPAND_CREATE_TEMPLATE
55};
56
9304f876
CJW		 57/* Classifies address type to distinguish 16-bit/32-bit format. */
58enum nds32_16bit_address_type
59{
60 /* [reg]: 45 format address. */
61 ADDRESS_REG,
62 /* [lo_reg + imm3u]: 333 format address. */
63 ADDRESS_LO_REG_IMM3U,
64 /* post_inc [lo_reg + imm3u]: 333 format address. */
65 ADDRESS_POST_INC_LO_REG_IMM3U,
67e1eb3d
SC		 66 /* post_modify [lo_reg + imm3u]: 333 format address. */
67 ADDRESS_POST_MODIFY_LO_REG_IMM3U,
8656bbcf
SC		 68 /* [$r8 + imm7u]: r8 imply address. */
69 ADDRESS_R8_IMM7U,
9304f876
CJW		 70 /* [$fp + imm7u]: fp imply address. */
71 ADDRESS_FP_IMM7U,
72 /* [$sp + imm7u]: sp imply address. */
73 ADDRESS_SP_IMM7U,
74 /* Other address format. */
75 ADDRESS_NOT_16BIT_FORMAT
76};
77
78
79/* ------------------------------------------------------------------------ */
80
81/* Define maximum numbers of registers for passing arguments. */
9d93cc24 82#define NDS32_MAX_GPR_REGS_FOR_ARGS 6
e2286268 83#define NDS32_MAX_FPR_REGS_FOR_ARGS 6
9304f876
CJW		 84
85/* Define the register number for first argument. */
86#define NDS32_GPR_ARG_FIRST_REGNUM 0
e2286268 87#define NDS32_FPR_ARG_FIRST_REGNUM 34
9304f876
CJW		 88
89/* Define the register number for return value. */
90#define NDS32_GPR_RET_FIRST_REGNUM 0
e2286268 91#define NDS32_FPR_RET_FIRST_REGNUM 34
9304f876 92
9d93cc24
CJW		 93/* Define the first integer register number. */
94#define NDS32_FIRST_GPR_REGNUM 0
95/* Define the last integer register number. */
96#define NDS32_LAST_GPR_REGNUM 31
9304f876 97
a6c7e777
MC		 98#define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6
99#define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \
100 (TARGET_REDUCED_REGS ? 10 : 14)
101
e2286268
MC		 102/* Define the floating-point number of registers. */
103#define NDS32_FLOAT_REGISTER_NUMBER \
104 (((nds32_fp_regnum == NDS32_CONFIG_FPU_0) \
105 || (nds32_fp_regnum == NDS32_CONFIG_FPU_4)) ? 8 \
106 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_1) \
107 || (nds32_fp_regnum == NDS32_CONFIG_FPU_5)) ? 16 \
108 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_2) \
109 || (nds32_fp_regnum == NDS32_CONFIG_FPU_6)) ? 32 \
110 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_3) \
111 || (nds32_fp_regnum == NDS32_CONFIG_FPU_7)) ? 64 \
112 : 32)
113
114#define NDS32_EXT_FPU_DOT_E (nds32_fp_regnum >= 4)
115
116/* Define the first floating-point register number. */
117#define NDS32_FIRST_FPR_REGNUM 34
118/* Define the last floating-point register number. */
119#define NDS32_LAST_FPR_REGNUM \
120 (NDS32_FIRST_FPR_REGNUM + NDS32_FLOAT_REGISTER_NUMBER - 1)
121
122
123#define NDS32_IS_EXT_FPR_REGNUM(regno) \
124 (((regno) >= NDS32_FIRST_FPR_REGNUM + 32) \
125 && ((regno) < NDS32_FIRST_FPR_REGNUM + 64))
126
127#define NDS32_IS_FPR_REGNUM(regno) \
128 (((regno) >= NDS32_FIRST_FPR_REGNUM) \
129 && ((regno) <= NDS32_LAST_FPR_REGNUM))
130
131#define NDS32_FPR_REGNO_OK_FOR_SINGLE(regno) \
132 ((regno) <= NDS32_LAST_FPR_REGNUM)
133
134#define NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) \
135 ((((regno) - NDS32_FIRST_FPR_REGNUM) & 1) == 0)
136
137#define NDS32_IS_GPR_REGNUM(regno) \
138 (((regno) <= NDS32_LAST_GPR_REGNUM))
139
9304f876
CJW		 140/* Define double word alignment bits. */
141#define NDS32_DOUBLE_WORD_ALIGNMENT 64
142
143/* Define alignment checking macros for convenience. */
144#define NDS32_HALF_WORD_ALIGN_P(value) (((value) & 0x01) == 0)
145#define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
146#define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
147
43fa41c1
CJW		 148/* Determine whether we would like to have code generation strictly aligned.
149 We set it strictly aligned when -malways-align is enabled.
150 Check gcc/common/config/nds32/nds32-common.c for the optimizations that
151 apply -malways-align. */
152#define NDS32_ALIGN_P() (TARGET_ALWAYS_ALIGN)
7c32ef41
MC		 153
154#define NDS32_EXT_DSP_P() (TARGET_EXT_DSP && !TARGET_FORCE_NO_EXT_DSP)
155
634bdae9
CJW		 156/* Get alignment according to mode or type information.
157 When 'type' is nonnull, there is no need to look at 'mode'. */
158#define NDS32_MODE_TYPE_ALIGN(mode, type) \
159 (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
160
9304f876
CJW		 161/* Round X up to the nearest double word. */
162#define NDS32_ROUND_UP_DOUBLE_WORD(value) (((value) + 7) & ~7)
163
164
165/* This macro is used to calculate the numbers of registers for
166 containing 'size' bytes of the argument.
167 The size of a register is a word in nds32 target.
168 So we use UNITS_PER_WORD to do the calculation. */
169#define NDS32_NEED_N_REGS_FOR_ARG(mode, type) \
170 ((mode == BLKmode) \
171 ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
172 : ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
173
174/* This macro is used to return the register number for passing argument.
175 We need to obey the following rules:
176 1. If it is required MORE THAN one register,
8a498f99
CJW		 177 we need to further check if it really needs to be
178 aligned on double words.
179 a) If double word alignment is necessary,
180 the register number must be even value.
181 b) Otherwise, the register number can be odd or even value.
9304f876 182 2. If it is required ONLY one register,
8a498f99
CJW		 183 the register number can be odd or even value. */
184#define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
185 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
186 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
187 ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
188 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
9304f876
CJW		 189 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
190
e2286268
MC		 191#define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \
192 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
193 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
194 ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1) \
195 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM)) \
196 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
197
198/* These two macros are to check if there are still available registers
7f6cd86b
CJW		 199 for passing argument, which must be entirely in registers. */
200#define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \
201 ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
202 + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \
203 <= (NDS32_GPR_ARG_FIRST_REGNUM \
204 + NDS32_MAX_GPR_REGS_FOR_ARGS))
205
e2286268
MC		 206#define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type) \
207 ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
208 + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \
209 <= (NDS32_FPR_ARG_FIRST_REGNUM \
210 + NDS32_MAX_FPR_REGS_FOR_ARGS))
211
212/* These two macros are to check if there are still available registers
7f6cd86b
CJW		 213 for passing argument, either entirely in registers or partially
214 in registers. */
215#define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
216 (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
217 < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
9304f876 218
e2286268
MC		 219#define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \
220 (NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
221 < NDS32_FPR_ARG_FIRST_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS)
222
9304f876
CJW		 223/* This macro is to check if the register is required to be saved on stack.
224 If call_used_regs[regno] == 0, regno is the callee-saved register.
225 If df_regs_ever_live_p(regno) == true, it is used in the current function.
226 As long as the register satisfies both criteria above,
227 it is required to be saved. */
228#define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \
229 ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
230
a6c7e777
MC		 231/* This macro is to check if the push25/pop25 are available to be used
232 for code generation. Because pop25 also performs return behavior,
233 the instructions may not be available for some cases.
234 If we want to use push25/pop25, all the following conditions must
235 be satisfied:
236 1. TARGET_V3PUSH is set.
237 2. Current function is not an ISR function.
238 3. Current function is not a variadic function.*/
239#define NDS32_V3PUSH_AVAILABLE_P \
240 (TARGET_V3PUSH \
241 && !nds32_isr_function_p (current_function_decl) \
242 && (cfun->machine->va_args_size == 0))
243
9304f876
CJW		 244/* ------------------------------------------------------------------------ */
245
246/* A C structure for machine-specific, per-function data.
247 This is added to the cfun structure. */
248struct GTY(()) machine_function
249{
250 /* Number of bytes allocated on the stack for variadic args
251 if we want to push them into stack as pretend arguments by ourself. */
252 int va_args_size;
253 /* Number of bytes reserved on the stack for
254 local and temporary variables. */
255 int local_size;
256 /* Number of bytes allocated on the stack for outgoing arguments. */
257 int out_args_size;
258
259 /* Number of bytes on the stack for saving $fp. */
260 int fp_size;
261 /* Number of bytes on the stack for saving $gp. */
262 int gp_size;
263 /* Number of bytes on the stack for saving $lp. */
264 int lp_size;
265
c457f751
CJW		 266 /* Number of bytes on the stack for saving general purpose
267 callee-saved registers. */
268 int callee_saved_gpr_regs_size;
269
e2286268
MC		 270 /* Number of bytes on the stack for saving floating-point
271 callee-saved registers. */
272 int callee_saved_fpr_regs_size;
273
9304f876 274 /* The padding bytes in callee-saved area may be required. */
c457f751 275 int callee_saved_area_gpr_padding_bytes;
9304f876 276
c457f751
CJW		 277 /* The first required general purpose callee-saved register. */
278 int callee_saved_first_gpr_regno;
279 /* The last required general purpose callee-saved register. */
280 int callee_saved_last_gpr_regno;
9304f876 281
e2286268
MC		 282 /* The first required floating-point callee-saved register. */
283 int callee_saved_first_fpr_regno;
284 /* The last required floating-point callee-saved register. */
285 int callee_saved_last_fpr_regno;
286
dd1536a7
CJW		 287 /* The padding bytes in varargs area may be required. */
288 int va_args_area_padding_bytes;
289
290 /* The first required register that should be saved on stack for va_args. */
291 int va_args_first_regno;
292 /* The last required register that should be saved on stack for va_args. */
293 int va_args_last_regno;
294
ca3a4a55
CJW		 295 /* Number of bytes on the stack for saving exception handling registers. */
296 int eh_return_data_regs_size;
297 /* The first register of passing exception handling information. */
298 int eh_return_data_first_regno;
299 /* The last register of passing exception handling information. */
300 int eh_return_data_last_regno;
301
302 /* Indicate that whether this function
303 calls __builtin_eh_return. */
304 int use_eh_return_p;
305
9304f876
CJW		 306 /* Indicate that whether this function needs
307 prologue/epilogue code generation. */
308 int naked_p;
309 /* Indicate that whether this function
310 uses fp_as_gp optimization. */
311 int fp_as_gp_p;
5f2a98c3
CJW		 312 /* Indicate that whether this function is under strictly aligned
313 situation for legitimate address checking. This flag informs
314 nds32_legitimate_address_p() how to treat offset alignment:
315 1. The IVOPT phase needs to detect available range for memory access,
316 such as checking [base + 32767] ~ [base + (-32768)].
317 For this case we do not want address to be strictly aligned.
318 2. The rtl lowering and optimization are close to target code.
319 For this case we need address to be strictly aligned. */
320 int strict_aligned_p;
9304f876
CJW		 321};
322
323/* A C structure that contains the arguments information. */
324typedef struct
325{
9d93cc24 326 unsigned int gpr_offset;
e2286268 327 unsigned int fpr_offset;
9304f876
CJW		 328} nds32_cumulative_args;
329
330/* ------------------------------------------------------------------------ */
331
332/* The following we define C-ISR related stuff.
333 In nds32 architecture, we have 73 vectors for interrupt/exception.
334 For each vector (except for vector 0, which is used for reset behavior),
335 we allow users to set its register saving scheme and interrupt level. */
336
337/* There are 73 vectors in nds32 architecture.
338 0 for reset handler,
339 1-8 for exception handler,
340 and 9-72 for interrupt handler.
341 We use an array, which is defined in nds32.c, to record
342 essential information for each vector. */
343#define NDS32_N_ISR_VECTORS 73
344
345/* Define possible isr category. */
346enum nds32_isr_category
347{
348 NDS32_ISR_NONE,
349 NDS32_ISR_INTERRUPT,
350 NDS32_ISR_EXCEPTION,
351 NDS32_ISR_RESET
352};
353
354/* Define isr register saving scheme. */
355enum nds32_isr_save_reg
356{
357 NDS32_SAVE_ALL,
358 NDS32_PARTIAL_SAVE
359};
360
361/* Define isr nested type. */
362enum nds32_isr_nested_type
363{
364 NDS32_NESTED,
365 NDS32_NOT_NESTED,
366 NDS32_NESTED_READY
367};
368
369/* Define structure to record isr information.
370 The isr vector array 'isr_vectors[]' with this structure
371 is defined in nds32.c. */
372struct nds32_isr_info
373{
374 /* The field to identify isr category.
375 It should be set to NDS32_ISR_NONE by default.
376 If user specifies a function as isr by using attribute,
377 this field will be set accordingly. */
378 enum nds32_isr_category category;
379
380 /* A string for the applied function name.
381 It should be set to empty string by default. */
382 char func_name[100];
383
384 /* The register saving scheme.
385 It should be set to NDS32_PARTIAL_SAVE by default
386 unless user specifies attribute to change it. */
387 enum nds32_isr_save_reg save_reg;
388
389 /* The nested type.
390 It should be set to NDS32_NOT_NESTED by default
391 unless user specifies attribute to change it. */
392 enum nds32_isr_nested_type nested_type;
393
394 /* Total vectors.
395 The total vectors = interrupt + exception numbers + reset.
396 It should be set to 0 by default.
397 This field is ONLY used in NDS32_ISR_RESET category. */
398 unsigned int total_n_vectors;
399
400 /* A string for nmi handler name.
401 It should be set to empty string by default.
402 This field is ONLY used in NDS32_ISR_RESET category. */
403 char nmi_name[100];
404
405 /* A string for warm handler name.
406 It should be set to empty string by default.
407 This field is ONLY used in NDS32_ISR_RESET category. */
408 char warm_name[100];
409};
410
411/* ------------------------------------------------------------------------ */
412
413/* Define code for all nds32 builtins. */
414enum nds32_builtins
415{
416 NDS32_BUILTIN_ISYNC,
417 NDS32_BUILTIN_ISB,
154e3ea6
MC		 418 NDS32_BUILTIN_DSB,
419 NDS32_BUILTIN_MSYNC_ALL,
420 NDS32_BUILTIN_MSYNC_STORE,
9304f876
CJW		 421 NDS32_BUILTIN_MFSR,
422 NDS32_BUILTIN_MFUSR,
423 NDS32_BUILTIN_MTSR,
154e3ea6
MC		 424 NDS32_BUILTIN_MTSR_ISB,
425 NDS32_BUILTIN_MTSR_DSB,
9304f876
CJW		 426 NDS32_BUILTIN_MTUSR,
427 NDS32_BUILTIN_SETGIE_EN,
7a12ea32 428 NDS32_BUILTIN_SETGIE_DIS,
0bb4423d
MC		 429 NDS32_BUILTIN_FMFCFG,
430 NDS32_BUILTIN_FMFCSR,
431 NDS32_BUILTIN_FMTCSR,
432 NDS32_BUILTIN_FCPYNSS,
433 NDS32_BUILTIN_FCPYSS,
434 NDS32_BUILTIN_FCPYNSD,
435 NDS32_BUILTIN_FCPYSD,
2feae6cd
MC		 436 NDS32_BUILTIN_ABS,
437 NDS32_BUILTIN_AVE,
438 NDS32_BUILTIN_BCLR,
439 NDS32_BUILTIN_BSET,
440 NDS32_BUILTIN_BTGL,
441 NDS32_BUILTIN_BTST,
442 NDS32_BUILTIN_CLIP,
443 NDS32_BUILTIN_CLIPS,
444 NDS32_BUILTIN_CLZ,
445 NDS32_BUILTIN_CLO,
446 NDS32_BUILTIN_MAX,
447 NDS32_BUILTIN_MIN,
448 NDS32_BUILTIN_PBSAD,
449 NDS32_BUILTIN_PBSADA,
450 NDS32_BUILTIN_BSE,
451 NDS32_BUILTIN_BSP,
3999578c
MC		 452 NDS32_BUILTIN_FFB,
453 NDS32_BUILTIN_FFMISM,
454 NDS32_BUILTIN_FLMISM,
7c32ef41
MC		 455 NDS32_BUILTIN_KADDW,
456 NDS32_BUILTIN_KSUBW,
457 NDS32_BUILTIN_KADDH,
458 NDS32_BUILTIN_KSUBH,
459 NDS32_BUILTIN_KDMBB,
460 NDS32_BUILTIN_V_KDMBB,
461 NDS32_BUILTIN_KDMBT,
462 NDS32_BUILTIN_V_KDMBT,
463 NDS32_BUILTIN_KDMTB,
464 NDS32_BUILTIN_V_KDMTB,
465 NDS32_BUILTIN_KDMTT,
466 NDS32_BUILTIN_V_KDMTT,
467 NDS32_BUILTIN_KHMBB,
468 NDS32_BUILTIN_V_KHMBB,
469 NDS32_BUILTIN_KHMBT,
470 NDS32_BUILTIN_V_KHMBT,
471 NDS32_BUILTIN_KHMTB,
472 NDS32_BUILTIN_V_KHMTB,
473 NDS32_BUILTIN_KHMTT,
474 NDS32_BUILTIN_V_KHMTT,
475 NDS32_BUILTIN_KSLRAW,
476 NDS32_BUILTIN_KSLRAW_U,
477 NDS32_BUILTIN_RDOV,
478 NDS32_BUILTIN_CLROV,
2feae6cd
MC		 479 NDS32_BUILTIN_ROTR,
480 NDS32_BUILTIN_SVA,
481 NDS32_BUILTIN_SVS,
482 NDS32_BUILTIN_WSBH,
483 NDS32_BUILTIN_JR_ITOFF,
484 NDS32_BUILTIN_JR_TOFF,
485 NDS32_BUILTIN_JRAL_ITON,
486 NDS32_BUILTIN_JRAL_TON,
487 NDS32_BUILTIN_RET_ITOFF,
488 NDS32_BUILTIN_RET_TOFF,
489 NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT,
490 NDS32_BUILTIN_STANDBY_WAKE_GRANT,
491 NDS32_BUILTIN_STANDBY_WAKE_DONE,
492 NDS32_BUILTIN_TEQZ,
493 NDS32_BUILTIN_TNEZ,
494 NDS32_BUILTIN_TRAP,
495 NDS32_BUILTIN_SETEND_BIG,
496 NDS32_BUILTIN_SETEND_LITTLE,
497 NDS32_BUILTIN_SYSCALL,
498 NDS32_BUILTIN_BREAK,
499 NDS32_BUILTIN_NOP,
500 NDS32_BUILTIN_SCHE_BARRIER,
501 NDS32_BUILTIN_GET_CURRENT_SP,
502 NDS32_BUILTIN_SET_CURRENT_SP,
503 NDS32_BUILTIN_RETURN_ADDRESS,
154e3ea6
MC		 504 NDS32_BUILTIN_LLW,
505 NDS32_BUILTIN_LWUP,
506 NDS32_BUILTIN_LBUP,
507 NDS32_BUILTIN_SCW,
508 NDS32_BUILTIN_SWUP,
509 NDS32_BUILTIN_SBUP,
f1a0afe2
MC		 510 NDS32_BUILTIN_CCTL_VA_LCK,
511 NDS32_BUILTIN_CCTL_IDX_WBINVAL,
512 NDS32_BUILTIN_CCTL_VA_WBINVAL_L1,
513 NDS32_BUILTIN_CCTL_VA_WBINVAL_LA,
514 NDS32_BUILTIN_CCTL_IDX_READ,
515 NDS32_BUILTIN_CCTL_IDX_WRITE,
516 NDS32_BUILTIN_CCTL_L1D_INVALALL,
517 NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL,
518 NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL,
57aaf0cc
MC		 519 NDS32_BUILTIN_DPREF_QW,
520 NDS32_BUILTIN_DPREF_HW,
521 NDS32_BUILTIN_DPREF_W,
522 NDS32_BUILTIN_DPREF_DW,
523 NDS32_BUILTIN_TLBOP_TRD,
524 NDS32_BUILTIN_TLBOP_TWR,
525 NDS32_BUILTIN_TLBOP_RWR,
526 NDS32_BUILTIN_TLBOP_RWLK,
527 NDS32_BUILTIN_TLBOP_UNLK,
528 NDS32_BUILTIN_TLBOP_PB,
529 NDS32_BUILTIN_TLBOP_INV,
530 NDS32_BUILTIN_TLBOP_FLUA,
e576ddb5
KC		 531 NDS32_BUILTIN_UALOAD_HW,
532 NDS32_BUILTIN_UALOAD_W,
533 NDS32_BUILTIN_UALOAD_DW,
534 NDS32_BUILTIN_UASTORE_HW,
535 NDS32_BUILTIN_UASTORE_W,
536 NDS32_BUILTIN_UASTORE_DW,
8b9322f0
MC		 537 NDS32_BUILTIN_GIE_DIS,
538 NDS32_BUILTIN_GIE_EN,
539 NDS32_BUILTIN_ENABLE_INT,
540 NDS32_BUILTIN_DISABLE_INT,
541 NDS32_BUILTIN_SET_PENDING_SWINT,
542 NDS32_BUILTIN_CLR_PENDING_SWINT,
543 NDS32_BUILTIN_CLR_PENDING_HWINT,
544 NDS32_BUILTIN_GET_ALL_PENDING_INT,
545 NDS32_BUILTIN_GET_PENDING_INT,
546 NDS32_BUILTIN_SET_INT_PRIORITY,
547 NDS32_BUILTIN_GET_INT_PRIORITY,
548 NDS32_BUILTIN_SET_TRIG_LEVEL,
549 NDS32_BUILTIN_SET_TRIG_EDGE,
550 NDS32_BUILTIN_GET_TRIG_TYPE,
7c32ef41
MC		 551 NDS32_BUILTIN_DSP_BEGIN,
552 NDS32_BUILTIN_ADD16,
553 NDS32_BUILTIN_V_UADD16,
554 NDS32_BUILTIN_V_SADD16,
555 NDS32_BUILTIN_RADD16,
556 NDS32_BUILTIN_V_RADD16,
557 NDS32_BUILTIN_URADD16,
558 NDS32_BUILTIN_V_URADD16,
559 NDS32_BUILTIN_KADD16,
560 NDS32_BUILTIN_V_KADD16,
561 NDS32_BUILTIN_UKADD16,
562 NDS32_BUILTIN_V_UKADD16,
563 NDS32_BUILTIN_SUB16,
564 NDS32_BUILTIN_V_USUB16,
565 NDS32_BUILTIN_V_SSUB16,
566 NDS32_BUILTIN_RSUB16,
567 NDS32_BUILTIN_V_RSUB16,
568 NDS32_BUILTIN_URSUB16,
569 NDS32_BUILTIN_V_URSUB16,
570 NDS32_BUILTIN_KSUB16,
571 NDS32_BUILTIN_V_KSUB16,
572 NDS32_BUILTIN_UKSUB16,
573 NDS32_BUILTIN_V_UKSUB16,
574 NDS32_BUILTIN_CRAS16,
575 NDS32_BUILTIN_V_UCRAS16,
576 NDS32_BUILTIN_V_SCRAS16,
577 NDS32_BUILTIN_RCRAS16,
578 NDS32_BUILTIN_V_RCRAS16,
579 NDS32_BUILTIN_URCRAS16,
580 NDS32_BUILTIN_V_URCRAS16,
581 NDS32_BUILTIN_KCRAS16,
582 NDS32_BUILTIN_V_KCRAS16,
583 NDS32_BUILTIN_UKCRAS16,
584 NDS32_BUILTIN_V_UKCRAS16,
585 NDS32_BUILTIN_CRSA16,
586 NDS32_BUILTIN_V_UCRSA16,
587 NDS32_BUILTIN_V_SCRSA16,
588 NDS32_BUILTIN_RCRSA16,
589 NDS32_BUILTIN_V_RCRSA16,
590 NDS32_BUILTIN_URCRSA16,
591 NDS32_BUILTIN_V_URCRSA16,
592 NDS32_BUILTIN_KCRSA16,
593 NDS32_BUILTIN_V_KCRSA16,
594 NDS32_BUILTIN_UKCRSA16,
595 NDS32_BUILTIN_V_UKCRSA16,
596 NDS32_BUILTIN_ADD8,
597 NDS32_BUILTIN_V_UADD8,
598 NDS32_BUILTIN_V_SADD8,
599 NDS32_BUILTIN_RADD8,
600 NDS32_BUILTIN_V_RADD8,
601 NDS32_BUILTIN_URADD8,
602 NDS32_BUILTIN_V_URADD8,
603 NDS32_BUILTIN_KADD8,
604 NDS32_BUILTIN_V_KADD8,
605 NDS32_BUILTIN_UKADD8,
606 NDS32_BUILTIN_V_UKADD8,
607 NDS32_BUILTIN_SUB8,
608 NDS32_BUILTIN_V_USUB8,
609 NDS32_BUILTIN_V_SSUB8,
610 NDS32_BUILTIN_RSUB8,
611 NDS32_BUILTIN_V_RSUB8,
612 NDS32_BUILTIN_URSUB8,
613 NDS32_BUILTIN_V_URSUB8,
614 NDS32_BUILTIN_KSUB8,
615 NDS32_BUILTIN_V_KSUB8,
616 NDS32_BUILTIN_UKSUB8,
617 NDS32_BUILTIN_V_UKSUB8,
618 NDS32_BUILTIN_SRA16,
619 NDS32_BUILTIN_V_SRA16,
620 NDS32_BUILTIN_SRA16_U,
621 NDS32_BUILTIN_V_SRA16_U,
622 NDS32_BUILTIN_SRL16,
623 NDS32_BUILTIN_V_SRL16,
624 NDS32_BUILTIN_SRL16_U,
625 NDS32_BUILTIN_V_SRL16_U,
626 NDS32_BUILTIN_SLL16,
627 NDS32_BUILTIN_V_SLL16,
628 NDS32_BUILTIN_KSLL16,
629 NDS32_BUILTIN_V_KSLL16,
630 NDS32_BUILTIN_KSLRA16,
631 NDS32_BUILTIN_V_KSLRA16,
632 NDS32_BUILTIN_KSLRA16_U,
633 NDS32_BUILTIN_V_KSLRA16_U,
634 NDS32_BUILTIN_CMPEQ16,
635 NDS32_BUILTIN_V_SCMPEQ16,
636 NDS32_BUILTIN_V_UCMPEQ16,
637 NDS32_BUILTIN_SCMPLT16,
638 NDS32_BUILTIN_V_SCMPLT16,
639 NDS32_BUILTIN_SCMPLE16,
640 NDS32_BUILTIN_V_SCMPLE16,
641 NDS32_BUILTIN_UCMPLT16,
642 NDS32_BUILTIN_V_UCMPLT16,
643 NDS32_BUILTIN_UCMPLE16,
644 NDS32_BUILTIN_V_UCMPLE16,
645 NDS32_BUILTIN_CMPEQ8,
646 NDS32_BUILTIN_V_SCMPEQ8,
647 NDS32_BUILTIN_V_UCMPEQ8,
648 NDS32_BUILTIN_SCMPLT8,
649 NDS32_BUILTIN_V_SCMPLT8,
650 NDS32_BUILTIN_SCMPLE8,
651 NDS32_BUILTIN_V_SCMPLE8,
652 NDS32_BUILTIN_UCMPLT8,
653 NDS32_BUILTIN_V_UCMPLT8,
654 NDS32_BUILTIN_UCMPLE8,
655 NDS32_BUILTIN_V_UCMPLE8,
656 NDS32_BUILTIN_SMIN16,
657 NDS32_BUILTIN_V_SMIN16,
658 NDS32_BUILTIN_UMIN16,
659 NDS32_BUILTIN_V_UMIN16,
660 NDS32_BUILTIN_SMAX16,
661 NDS32_BUILTIN_V_SMAX16,
662 NDS32_BUILTIN_UMAX16,
663 NDS32_BUILTIN_V_UMAX16,
664 NDS32_BUILTIN_SCLIP16,
665 NDS32_BUILTIN_V_SCLIP16,
666 NDS32_BUILTIN_UCLIP16,
667 NDS32_BUILTIN_V_UCLIP16,
668 NDS32_BUILTIN_KHM16,
669 NDS32_BUILTIN_V_KHM16,
670 NDS32_BUILTIN_KHMX16,
671 NDS32_BUILTIN_V_KHMX16,
672 NDS32_BUILTIN_KABS16,
673 NDS32_BUILTIN_V_KABS16,
674 NDS32_BUILTIN_SMIN8,
675 NDS32_BUILTIN_V_SMIN8,
676 NDS32_BUILTIN_UMIN8,
677 NDS32_BUILTIN_V_UMIN8,
678 NDS32_BUILTIN_SMAX8,
679 NDS32_BUILTIN_V_SMAX8,
680 NDS32_BUILTIN_UMAX8,
681 NDS32_BUILTIN_V_UMAX8,
682 NDS32_BUILTIN_KABS8,
683 NDS32_BUILTIN_V_KABS8,
684 NDS32_BUILTIN_SUNPKD810,
685 NDS32_BUILTIN_V_SUNPKD810,
686 NDS32_BUILTIN_SUNPKD820,
687 NDS32_BUILTIN_V_SUNPKD820,
688 NDS32_BUILTIN_SUNPKD830,
689 NDS32_BUILTIN_V_SUNPKD830,
690 NDS32_BUILTIN_SUNPKD831,
691 NDS32_BUILTIN_V_SUNPKD831,
692 NDS32_BUILTIN_ZUNPKD810,
693 NDS32_BUILTIN_V_ZUNPKD810,
694 NDS32_BUILTIN_ZUNPKD820,
695 NDS32_BUILTIN_V_ZUNPKD820,
696 NDS32_BUILTIN_ZUNPKD830,
697 NDS32_BUILTIN_V_ZUNPKD830,
698 NDS32_BUILTIN_ZUNPKD831,
699 NDS32_BUILTIN_V_ZUNPKD831,
700 NDS32_BUILTIN_RADDW,
701 NDS32_BUILTIN_URADDW,
702 NDS32_BUILTIN_RSUBW,
703 NDS32_BUILTIN_URSUBW,
704 NDS32_BUILTIN_SRA_U,
705 NDS32_BUILTIN_KSLL,
706 NDS32_BUILTIN_PKBB16,
707 NDS32_BUILTIN_V_PKBB16,
708 NDS32_BUILTIN_PKBT16,
709 NDS32_BUILTIN_V_PKBT16,
710 NDS32_BUILTIN_PKTB16,
711 NDS32_BUILTIN_V_PKTB16,
712 NDS32_BUILTIN_PKTT16,
713 NDS32_BUILTIN_V_PKTT16,
714 NDS32_BUILTIN_SMMUL,
715 NDS32_BUILTIN_SMMUL_U,
716 NDS32_BUILTIN_KMMAC,
717 NDS32_BUILTIN_KMMAC_U,
718 NDS32_BUILTIN_KMMSB,
719 NDS32_BUILTIN_KMMSB_U,
720 NDS32_BUILTIN_KWMMUL,
721 NDS32_BUILTIN_KWMMUL_U,
722 NDS32_BUILTIN_SMMWB,
723 NDS32_BUILTIN_V_SMMWB,
724 NDS32_BUILTIN_SMMWB_U,
725 NDS32_BUILTIN_V_SMMWB_U,
726 NDS32_BUILTIN_SMMWT,
727 NDS32_BUILTIN_V_SMMWT,
728 NDS32_BUILTIN_SMMWT_U,
729 NDS32_BUILTIN_V_SMMWT_U,
730 NDS32_BUILTIN_KMMAWB,
731 NDS32_BUILTIN_V_KMMAWB,
732 NDS32_BUILTIN_KMMAWB_U,
733 NDS32_BUILTIN_V_KMMAWB_U,
734 NDS32_BUILTIN_KMMAWT,
735 NDS32_BUILTIN_V_KMMAWT,
736 NDS32_BUILTIN_KMMAWT_U,
737 NDS32_BUILTIN_V_KMMAWT_U,
738 NDS32_BUILTIN_SMBB,
739 NDS32_BUILTIN_V_SMBB,
740 NDS32_BUILTIN_SMBT,
741 NDS32_BUILTIN_V_SMBT,
742 NDS32_BUILTIN_SMTT,
743 NDS32_BUILTIN_V_SMTT,
744 NDS32_BUILTIN_KMDA,
745 NDS32_BUILTIN_V_KMDA,
746 NDS32_BUILTIN_KMXDA,
747 NDS32_BUILTIN_V_KMXDA,
748 NDS32_BUILTIN_SMDS,
749 NDS32_BUILTIN_V_SMDS,
750 NDS32_BUILTIN_SMDRS,
751 NDS32_BUILTIN_V_SMDRS,
752 NDS32_BUILTIN_SMXDS,
753 NDS32_BUILTIN_V_SMXDS,
754 NDS32_BUILTIN_KMABB,
755 NDS32_BUILTIN_V_KMABB,
756 NDS32_BUILTIN_KMABT,
757 NDS32_BUILTIN_V_KMABT,
758 NDS32_BUILTIN_KMATT,
759 NDS32_BUILTIN_V_KMATT,
760 NDS32_BUILTIN_KMADA,
761 NDS32_BUILTIN_V_KMADA,
762 NDS32_BUILTIN_KMAXDA,
763 NDS32_BUILTIN_V_KMAXDA,
764 NDS32_BUILTIN_KMADS,
765 NDS32_BUILTIN_V_KMADS,
766 NDS32_BUILTIN_KMADRS,
767 NDS32_BUILTIN_V_KMADRS,
768 NDS32_BUILTIN_KMAXDS,
769 NDS32_BUILTIN_V_KMAXDS,
770 NDS32_BUILTIN_KMSDA,
771 NDS32_BUILTIN_V_KMSDA,
772 NDS32_BUILTIN_KMSXDA,
773 NDS32_BUILTIN_V_KMSXDA,
774 NDS32_BUILTIN_SMAL,
775 NDS32_BUILTIN_V_SMAL,
776 NDS32_BUILTIN_BITREV,
777 NDS32_BUILTIN_WEXT,
778 NDS32_BUILTIN_BPICK,
779 NDS32_BUILTIN_INSB,
780 NDS32_BUILTIN_SADD64,
781 NDS32_BUILTIN_UADD64,
782 NDS32_BUILTIN_RADD64,
783 NDS32_BUILTIN_URADD64,
784 NDS32_BUILTIN_KADD64,
785 NDS32_BUILTIN_UKADD64,
786 NDS32_BUILTIN_SSUB64,
787 NDS32_BUILTIN_USUB64,
788 NDS32_BUILTIN_RSUB64,
789 NDS32_BUILTIN_URSUB64,
790 NDS32_BUILTIN_KSUB64,
791 NDS32_BUILTIN_UKSUB64,
792 NDS32_BUILTIN_SMAR64,
793 NDS32_BUILTIN_SMSR64,
794 NDS32_BUILTIN_UMAR64,
795 NDS32_BUILTIN_UMSR64,
796 NDS32_BUILTIN_KMAR64,
797 NDS32_BUILTIN_KMSR64,
798 NDS32_BUILTIN_UKMAR64,
799 NDS32_BUILTIN_UKMSR64,
800 NDS32_BUILTIN_SMALBB,
801 NDS32_BUILTIN_V_SMALBB,
802 NDS32_BUILTIN_SMALBT,
803 NDS32_BUILTIN_V_SMALBT,
804 NDS32_BUILTIN_SMALTT,
805 NDS32_BUILTIN_V_SMALTT,
806 NDS32_BUILTIN_SMALDA,
807 NDS32_BUILTIN_V_SMALDA,
808 NDS32_BUILTIN_SMALXDA,
809 NDS32_BUILTIN_V_SMALXDA,
810 NDS32_BUILTIN_SMALDS,
811 NDS32_BUILTIN_V_SMALDS,
812 NDS32_BUILTIN_SMALDRS,
813 NDS32_BUILTIN_V_SMALDRS,
814 NDS32_BUILTIN_SMALXDS,
815 NDS32_BUILTIN_V_SMALXDS,
816 NDS32_BUILTIN_SMUL16,
817 NDS32_BUILTIN_V_SMUL16,
818 NDS32_BUILTIN_SMULX16,
819 NDS32_BUILTIN_V_SMULX16,
820 NDS32_BUILTIN_UMUL16,
821 NDS32_BUILTIN_V_UMUL16,
822 NDS32_BUILTIN_UMULX16,
823 NDS32_BUILTIN_V_UMULX16,
824 NDS32_BUILTIN_SMSLDA,
825 NDS32_BUILTIN_V_SMSLDA,
826 NDS32_BUILTIN_SMSLXDA,
827 NDS32_BUILTIN_V_SMSLXDA,
828 NDS32_BUILTIN_UCLIP32,
829 NDS32_BUILTIN_SCLIP32,
830 NDS32_BUILTIN_KABS,
831 NDS32_BUILTIN_UALOAD_U16,
832 NDS32_BUILTIN_UALOAD_S16,
833 NDS32_BUILTIN_UALOAD_U8,
834 NDS32_BUILTIN_UALOAD_S8,
835 NDS32_BUILTIN_UASTORE_U16,
836 NDS32_BUILTIN_UASTORE_S16,
837 NDS32_BUILTIN_UASTORE_U8,
838 NDS32_BUILTIN_UASTORE_S8,
839 NDS32_BUILTIN_DSP_END,
bc8a8810
MC		 840 NDS32_BUILTIN_UNALIGNED_FEATURE,
841 NDS32_BUILTIN_ENABLE_UNALIGNED,
842 NDS32_BUILTIN_DISABLE_UNALIGNED,
7a12ea32 843 NDS32_BUILTIN_COUNT
9304f876
CJW		 844};
845
846/* ------------------------------------------------------------------------ */
847
848#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
e2286268
MC		 849
850#define TARGET_ISA_V3 \
851 (nds32_arch_option == ARCH_V3 \
852 || nds32_arch_option == ARCH_V3F \
853 || nds32_arch_option == ARCH_V3S)
9304f876
CJW		 854#define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M)
855
dd000841
CJW		 856#define TARGET_PIPELINE_N7 \
857 (nds32_cpu_option == CPU_N7)
858#define TARGET_PIPELINE_N8 \
859 (nds32_cpu_option == CPU_N6 \
860 || nds32_cpu_option == CPU_N8)
b99353a2
KC		 861#define TARGET_PIPELINE_N9 \
862 (nds32_cpu_option == CPU_N9)
dd000841
CJW		 863#define TARGET_PIPELINE_N10 \
864 (nds32_cpu_option == CPU_N10)
865#define TARGET_PIPELINE_N13 \
866 (nds32_cpu_option == CPU_N12 || nds32_cpu_option == CPU_N13)
867#define TARGET_PIPELINE_GRAYWOLF \
868 (nds32_cpu_option == CPU_GRAYWOLF)
b99353a2
KC		 869#define TARGET_PIPELINE_SIMPLE \
870 (nds32_cpu_option == CPU_SIMPLE)
871
77b7a1ca
CJW		 872#define TARGET_CMODEL_SMALL \
873 (nds32_cmodel_option == CMODEL_SMALL)
874#define TARGET_CMODEL_MEDIUM \
875 (nds32_cmodel_option == CMODEL_MEDIUM)
876#define TARGET_CMODEL_LARGE \
877 (nds32_cmodel_option == CMODEL_LARGE)
878
85a98076
KLC		 879#define TARGET_ICT_MODEL_SMALL \
880 (nds32_ict_model == ICT_MODEL_SMALL)
881
882#define TARGET_ICT_MODEL_LARGE \
883 (nds32_ict_model == ICT_MODEL_LARGE)
884
77b7a1ca
CJW		 885/* When -mcmodel=small or -mcmodel=medium,
886 compiler may generate gp-base instruction directly. */
887#define TARGET_GP_DIRECT \
888 (nds32_cmodel_option == CMODEL_SMALL\
889 || nds32_cmodel_option == CMODEL_MEDIUM)
890
b99353a2
KC		 891#define TARGET_MUL_SLOW \
892 (nds32_mul_config == MUL_TYPE_SLOW)
d4a6a4d9 893
e2286268
MC		 894/* Run-time Target Specification. */
895#define TARGET_SOFT_FLOAT (nds32_abi == NDS32_ABI_V2)
896/* Use hardware floating point calling convention. */
897#define TARGET_HARD_FLOAT (nds32_abi == NDS32_ABI_V2_FP_PLUS)
898
899/* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI,
900 1 means hard ABI and using full floating-point instruction,
901 2 means hard ABI and only using single-precision floating-point
902 instruction */
903#if TARGET_ARCH_DEFAULT == 1
904# define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
905# define TARGET_DEFAULT_FPU_ISA MASK_FPU_DOUBLE | MASK_FPU_SINGLE
906# define TARGET_DEFAULT_FPU_FMA 0
907#else
908# if TARGET_ARCH_DEFAULT == 2
909# define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
910# define TARGET_DEFAULT_FPU_ISA MASK_FPU_SINGLE
911# define TARGET_DEFAULT_FPU_FMA 0
912# else
913# define TARGET_DEFAULT_ABI NDS32_ABI_V2
914# define TARGET_DEFAULT_FPU_ISA 0
915# define TARGET_DEFAULT_FPU_FMA 0
916# endif
917#endif
918
919#define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2
7c32ef41
MC		 920
921#ifdef TARGET_DEFAULT_EXT_DSP
922# define NDS32_EXT_DSP_SPEC " %{!mno-ext-dsp:-mext-dsp}"
923#else
924# define NDS32_EXT_DSP_SPEC ""
925#endif
926
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CJW		 927/* ------------------------------------------------------------------------ */
928\f
929/* Controlling the Compilation Driver. */
930
931#define OPTION_DEFAULT_SPECS \
e2286268
MC		 932 {"arch", " %{!march=*:-march=%(VALUE)}" \
933 " %{march=v3f:%{!mfloat-abi=*:-mfloat-abi=hard}" \
934 " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}" \
935 " %{!mno-ext-fpu-dp:%{!mext-fpu-dp:-mext-fpu-dp}}}" \
936 " %{march=v3s:%{!mfloat-abi=*:-mfloat-abi=hard}" \
937 " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}}" }, \
b99353a2 938 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
e2286268 939 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }
9304f876
CJW		 940
941#define CC1_SPEC \
7c32ef41 942 NDS32_EXT_DSP_SPEC
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CJW		 943
944#define ASM_SPEC \
e2286268
MC		 945 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
946 " %{march=*:-march=%*}" \
8aa27a4c
CJW		 947 " %{mno-16-bit|mno-16bit:-mno-16bit-ext}" \
948 " %{march=v3m:%{!mfull-regs:%{!mreduced-regs:-mreduced-regs}}}" \
949 " %{mfull-regs:-mno-reduced-regs}" \
950 " %{mreduced-regs:-mreduced-regs}" \
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MC		 951 " %{mabi=*:-mabi=v%*}" \
952 " %{mconfig-fpu=*:-mfpu-freg=%*}" \
953 " %{mext-fpu-mac:-mmac}" \
954 " %{mno-ext-fpu-mac:-mno-mac}" \
955 " %{mext-fpu-sp:-mfpu-sp-ext}" \
956 " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \
957 " %{mext-fpu-dp:-mfpu-dp-ext}" \
7c32ef41 958 " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}" \
8aa27a4c
CJW		 959 " %{mext-dsp:-mdsp-ext}" \
960 " %{O|O1|O2|O3|Ofast:-O1;:-Os}"
9304f876 961
2ca1ca65 962/* If user issues -mrelax, we need to pass '--relax' to linker. */
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CJW		 963#define LINK_SPEC \
964 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
2ca1ca65 965 " %{mrelax:--relax}"
9304f876
CJW		 966
967#define LIB_SPEC \
968 " -lc -lgloss"
969
970/* The option -mno-ctor-dtor can disable constructor/destructor feature
971 by applying different crt stuff. In the convention, crt0.o is the
972 startup file without constructor/destructor;
973 crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
974 startup files with constructor/destructor.
975 Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
976 by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
977 currently provided by GCC for nds32 target.
978
979 For nds32 target so far:
980 If -mno-ctor-dtor, we are going to link
981 "crt0.o [user objects]".
982 If general cases, we are going to link
983 "crt1.o crtbegin1.o [user objects] crtend1.o". */
984#define STARTFILE_SPEC \
985 " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
986 " %{!mno-ctor-dtor:crtbegin1.o%s}"
987#define ENDFILE_SPEC \
988 " %{!mno-ctor-dtor:crtend1.o%s}"
989
c9eb51a7
CJW		 990/* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
991 configure gcc with --target=nds32be-* setting.
992 Check gcc/config.gcc for more information. */
9304f876 993#ifdef TARGET_BIG_ENDIAN_DEFAULT
c9eb51a7 994# define NDS32_ENDIAN_DEFAULT "mbig-endian"
9304f876 995#else
c9eb51a7 996# define NDS32_ENDIAN_DEFAULT "mlittle-endian"
9304f876
CJW		 997#endif
998
c9eb51a7
CJW		 999/* Currently we only have elf toolchain,
1000 where -mcmodel=medium is always the default. */
1001#define NDS32_CMODEL_DEFAULT "mcmodel=medium"
1002
1003#define MULTILIB_DEFAULTS \
1004 { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
1005
9304f876
CJW		 1006\f
1007/* Run-time Target Specification. */
1008
72b7e5e1
KC		 1009#define TARGET_CPU_CPP_BUILTINS() \
1010 nds32_cpu_cpp_builtins (pfile)
9304f876
CJW		 1011
1012\f
1013/* Defining Data Structures for Per-function Information. */
1014
1015/* This macro is called once per function,
1016 before generation of any RTL has begun. */
1017#define INIT_EXPANDERS nds32_init_expanders ()
1018
1019\f
1020/* Storage Layout. */
1021
1022#define BITS_BIG_ENDIAN 0
1023
1024#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
1025
1026#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
1027
1028#define UNITS_PER_WORD 4
1029
1030#define PROMOTE_MODE(m, unsignedp, type) \
1031 if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
1032 { \
1033 (m) = SImode; \
1034 }
1035
1036#define PARM_BOUNDARY 32
1037
1038#define STACK_BOUNDARY 64
1039
43fa41c1
CJW		 1040#define FUNCTION_BOUNDARY \
1041 ((NDS32_ALIGN_P () || TARGET_ALIGN_FUNCTION) ? 32 : 16)
9304f876
CJW		 1042
1043#define BIGGEST_ALIGNMENT 64
1044
79498ad8
CJW		 1045#define DATA_ALIGNMENT(constant, basic_align) \
1046 nds32_data_alignment (constant, basic_align)
1047
1048#define LOCAL_ALIGNMENT(type, basic_align) \
1049 nds32_local_alignment (type, basic_align)
1050
9304f876
CJW		 1051#define EMPTY_FIELD_BOUNDARY 32
1052
1053#define STRUCTURE_SIZE_BOUNDARY 8
1054
1055#define STRICT_ALIGNMENT 1
1056
1057#define PCC_BITFIELD_TYPE_MATTERS 1
1058
1059\f
1060/* Layout of Source Language Data Types. */
1061
1062#define INT_TYPE_SIZE 32
1063#define SHORT_TYPE_SIZE 16
1064#define LONG_TYPE_SIZE 32
1065#define LONG_LONG_TYPE_SIZE 64
1066
1067#define FLOAT_TYPE_SIZE 32
1068#define DOUBLE_TYPE_SIZE 64
1069#define LONG_DOUBLE_TYPE_SIZE 64
1070
1071#define DEFAULT_SIGNED_CHAR 1
1072
1073#define SIZE_TYPE "long unsigned int"
1074#define PTRDIFF_TYPE "long int"
7f983342
CJW		 1075#define WCHAR_TYPE "unsigned int"
1076#define WCHAR_TYPE_SIZE 32
9304f876
CJW		 1077
1078\f
1079/* Register Usage. */
1080
1081/* Number of actual hardware registers.
1082 The hardware registers are assigned numbers for the compiler
1083 from 0 to just below FIRST_PSEUDO_REGISTER.
1084 All registers that the compiler knows about must be given numbers,
1085 even those that are not normally considered general registers. */
71d8eff1 1086#define FIRST_PSEUDO_REGISTER 101
9304f876
CJW		 1087
1088/* An initializer that says which registers are used for fixed
1089 purposes all throughout the compiled code and are therefore
1090 not available for general allocation.
1091
1092 $r28 : $fp
1093 $r29 : $gp
1094 $r30 : $lp
1095 $r31 : $sp
1096
e2286268
MC		 1097 caller-save registers: $r0 ~ $r5, $r16 ~ $r23, $fs0 ~ $fs5, $fs22 ~ $fs47
1098 callee-save registers: $r6 ~ $r10, $r11 ~ $r14, $fs6 ~ $fs21, $fs48 ~ $fs63
9304f876
CJW		 1099
1100 reserved for assembler : $r15
1101 reserved for other use : $r24, $r25, $r26, $r27 */
71d8eff1
CJW		 1102#define FIXED_REGISTERS \
1103{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
1104 0, 0, 0, 0, 0, 0, 0, 0, \
1105 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
1106 0, 0, 0, 0, 0, 0, 0, 1, \
1107 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
1108 0, 0, 0, 0, 0, 0, 0, 0, \
1109 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
1110 1, 1, 1, 1, 0, 1, 0, 1, \
e2286268 1111 /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \
71d8eff1 1112 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1113 /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \
71d8eff1 1114 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1115 /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
71d8eff1 1116 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1117 /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
71d8eff1 1118 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1119 /* fs30 fs31 fd16 fd17 fd18 */ \
71d8eff1 1120 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1121 /* fd19 fd20 fd21 fd22 */ \
71d8eff1 1122 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1123 /* fd23 fd24 fd25 fd26 */ \
71d8eff1 1124 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1125 /* fd27 fd28 fd29 fd30 */ \
71d8eff1 1126 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1127 /* fd31 Reserved..................... */ \
71d8eff1 1128 1, 1, 1, 1, 1 \
9304f876
CJW		 1129}
1130
1131/* Identifies the registers that are not available for
1132 general allocation of values that must live across
1133 function calls -- so they are caller-save registers.
1134
1135 0 : callee-save registers
1136 1 : caller-save registers */
71d8eff1
CJW		 1137#define CALL_USED_REGISTERS \
1138{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
1139 1, 1, 1, 1, 1, 1, 0, 0, \
1140 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
1141 0, 0, 0, 0, 0, 0, 0, 1, \
1142 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
1143 1, 1, 1, 1, 1, 1, 1, 1, \
1144 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
1145 1, 1, 1, 1, 0, 1, 0, 1, \
e2286268 1146 /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \
71d8eff1 1147 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1148 /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \
71d8eff1 1149 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1150 /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
71d8eff1 1151 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1152 /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
71d8eff1 1153 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1154 /* fs30 fs31 fd16 fd17 fd18 */ \
71d8eff1 1155 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1156 /* fd19 fd20 fd21 fd22 */ \
71d8eff1 1157 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1158 /* fd23 fd24 fd25 fd26 */ \
71d8eff1 1159 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1160 /* fd27 fd28 fd29 fd30 */ \
71d8eff1 1161 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1162 /* fd31 Reserved..................... */ \
71d8eff1 1163 1, 1, 1, 1, 1 \
9304f876
CJW		 1164}
1165
1166/* In nds32 target, we have three levels of registers:
1167 LOW_COST_REGS : $r0 ~ $r7
1168 MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
1169 HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */
71d8eff1
CJW		 1170#define REG_ALLOC_ORDER \
1171{ 0, 1, 2, 3, 4, 5, 6, 7, \
1172 16, 17, 18, 19, 9, 10, 11, 12, \
1173 13, 14, 8, 15, 20, 21, 22, 23, \
1174 24, 25, 26, 27, 28, 29, 30, 31, \
1175 32, 33, 34, 35, 36, 37, 38, 39, \
1176 40, 41, 42, 43, 44, 45, 46, 47, \
1177 48, 49, 50, 51, 52, 53, 54, 55, \
1178 56, 57, 58, 59, 60, 61, 62, 63, \
1179 64, 65, 66, 67, 68, 69, 70, 71, \
1180 72, 73, 74, 75, 76, 77, 78, 79, \
1181 80, 81, 82, 83, 84, 85, 86, 87, \
1182 88, 89, 90, 91, 92, 93, 94, 95, \
1183 96, 97, 98, 99, 100, \
9304f876
CJW		 1184}
1185
5e6ae0cc
CJW		 1186/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1187 to be rearranged based on optimizing for speed or size. */
1188#define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order ()
1189
9304f876
CJW		 1190/* Tell IRA to use the order we define rather than messing it up with its
1191 own cost calculations. */
96092404 1192#define HONOR_REG_ALLOC_ORDER optimize_size
9304f876 1193
9304f876
CJW		 1194\f
1195/* Register Classes. */
1196
1197/* In nds32 target, we have three levels of registers:
1198 Low cost regsiters : $r0 ~ $r7
1199 Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
1200 High cost registers : $r12 ~ $r14, $r20 ~ $r31
1201
1202 In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
1203 so that it provides more chance to use low cost registers. */
1204enum reg_class
1205{
1206 NO_REGS,
36f28760
CJW		 1207 R5_REG,
1208 R8_REG,
9304f876
CJW		 1209 R15_TA_REG,
1210 STACK_REG,
36f28760 1211 FRAME_POINTER_REG,
9304f876
CJW		 1212 LOW_REGS,
1213 MIDDLE_REGS,
1214 HIGH_REGS,
1215 GENERAL_REGS,
1216 FRAME_REGS,
e2286268 1217 FP_REGS,
9304f876
CJW		 1218 ALL_REGS,
1219 LIM_REG_CLASSES
1220};
1221
1222#define N_REG_CLASSES (int) LIM_REG_CLASSES
1223
1224#define REG_CLASS_NAMES \
1225{ \
1226 "NO_REGS", \
36f28760
CJW		 1227 "R5_REG", \
1228 "R8_REG", \
9304f876
CJW		 1229 "R15_TA_REG", \
1230 "STACK_REG", \
36f28760 1231 "FRAME_POINTER_REG", \
9304f876
CJW		 1232 "LOW_REGS", \
1233 "MIDDLE_REGS", \
1234 "HIGH_REGS", \
1235 "GENERAL_REGS", \
1236 "FRAME_REGS", \
e2286268 1237 "FP_REGS", \
9304f876
CJW		 1238 "ALL_REGS" \
1239}
1240
1241#define REG_CLASS_CONTENTS \
71d8eff1
CJW		 1242{ /* NO_REGS */ \
1243 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
1244 /* R5_REG : 5 */ \
1245 {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
1246 /* R8_REG : 8 */ \
1247 {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
1248 /* R15_TA_REG : 15 */ \
1249 {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
1250 /* STACK_REG : 31 */ \
1251 {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
1252 /* FRAME_POINTER_REG : 28 */ \
1253 {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
1254 /* LOW_REGS : 0-7 */ \
1255 {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
1256 /* MIDDLE_REGS : 0-11, 16-19 */ \
1257 {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
1258 /* HIGH_REGS : 12-14, 20-31 */ \
1259 {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
1260 /* GENERAL_REGS : 0-31 */ \
1261 {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
1262 /* FRAME_REGS : 32, 33 */ \
1263 {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
e2286268
MC		 1264 /* FP_REGS : 34-98 */ \
1265 {0x00000000, 0xfffffffc, 0xffffffff, 0x00000003}, \
71d8eff1
CJW		 1266 /* ALL_REGS : 0-100 */ \
1267 {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f} \
9304f876
CJW		 1268}
1269
1270#define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
1271
1272#define BASE_REG_CLASS GENERAL_REGS
1273#define INDEX_REG_CLASS GENERAL_REGS
1274
e2286268
MC		 1275#define TEST_REGNO(R, TEST, VALUE) \
1276 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1277
9304f876
CJW		 1278/* Return nonzero if it is suitable for use as a
1279 base register in operand addresses.
1280 So far, we return nonzero only if "num" is a hard reg
1281 of the suitable class or a pseudo register which is
1282 allocated to a suitable hard reg. */
1283#define REGNO_OK_FOR_BASE_P(num) \
e2286268
MC		 1284 (TEST_REGNO (num, <, 32) \
1285 || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
1286 || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
9304f876
CJW		 1287
1288/* Return nonzero if it is suitable for use as a
1289 index register in operand addresses.
1290 So far, we return nonzero only if "num" is a hard reg
1291 of the suitable class or a pseudo register which is
1292 allocated to a suitable hard reg.
1293 The difference between an index register and a base register is that
1294 the index register may be scaled. */
1295#define REGNO_OK_FOR_INDEX_P(num) \
e2286268
MC		 1296 (TEST_REGNO (num, <, 32) \
1297 || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
1298 || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
9304f876
CJW		 1299
1300\f
1301/* Obsolete Macros for Defining Constraints. */
1302
1303\f
1304/* Stack Layout and Calling Conventions. */
1305
62f9f30b 1306#define STACK_GROWS_DOWNWARD 1
9304f876
CJW		 1307
1308#define FRAME_GROWS_DOWNWARD 1
1309
9304f876
CJW		 1310#define STACK_POINTER_OFFSET 0
1311
4f44e960
CJW		 1312#define FIRST_PARM_OFFSET(fundecl) \
1313 (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
9304f876 1314
ca3a4a55
CJW		 1315/* A C expression whose value is RTL representing the address in a stack frame
1316 where the pointer to the caller's frame is stored. */
1317#define DYNAMIC_CHAIN_ADDRESS(frameaddr) \
1318 nds32_dynamic_chain_address (frameaddr)
1319
9304f876
CJW		 1320#define RETURN_ADDR_RTX(count, frameaddr) \
1321 nds32_return_addr_rtx (count, frameaddr)
1322
1323/* A C expression whose value is RTL representing the location
1324 of the incoming return address at the beginning of any function
1325 before the prologue.
1326 If this RTL is REG, you should also define
1327 DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO). */
1328#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM)
1329#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM)
1330
ca3a4a55
CJW		 1331/* Use $r0 $r1 to pass exception handling information. */
1332#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) : INVALID_REGNUM)
1333/* The register $r2 that represents a location in which to store a stack
1334 adjustment to be applied before function return.
1335 This is used to unwind the stack to an exception handler's call frame. */
1336#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
1337
e2286268
MC		 1338#define DBX_REGISTER_NUMBER(REGNO) nds32_dbx_register_number (REGNO)
1339
9304f876
CJW		 1340#define STACK_POINTER_REGNUM SP_REGNUM
1341
1342#define FRAME_POINTER_REGNUM 33
1343
1344#define HARD_FRAME_POINTER_REGNUM FP_REGNUM
1345
1346#define ARG_POINTER_REGNUM 32
1347
1348#define STATIC_CHAIN_REGNUM 16
1349
1350#define ELIMINABLE_REGS \
1351{ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1352 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
1353 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1354 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
1355
1356#define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
1357 (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
1358
1359#define ACCUMULATE_OUTGOING_ARGS 1
1360
1361#define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
1362
1363#define CUMULATIVE_ARGS nds32_cumulative_args
1364
1365#define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
1366 nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
1367
e2286268
MC		 1368#define FUNCTION_ARG_REGNO_P(regno) \
1369 (IN_RANGE ((regno), NDS32_FIRST_GPR_REGNUM, NDS32_MAX_GPR_REGS_FOR_ARGS - 1) \
1370 || ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) \
1371 && IN_RANGE ((regno), NDS32_FPR_ARG_FIRST_REGNUM, \
1372 NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS - 1)))
9304f876
CJW		 1373
1374#define DEFAULT_PCC_STRUCT_RETURN 0
1375
1376/* EXIT_IGNORE_STACK should be nonzero if, when returning
1377 from a function, the stack pointer does not matter.
1378 The value is tested only in functions that have frame pointers.
1379 In nds32 target, the function epilogue recovers the
1380 stack pointer from the frame. */
1381#define EXIT_IGNORE_STACK 1
1382
1383#define FUNCTION_PROFILER(file, labelno) \
9e362bd0
CJW		 1384 fprintf (file, "/* profiler %d */\n", (labelno))
1385
1386#define PROFILE_HOOK(LABEL) \
1387 { \
1388 rtx fun, lp; \
1389 lp = get_hard_reg_initial_val (Pmode, LP_REGNUM); \
1390 fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \
1391 emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode); \
1392 }
9304f876
CJW		 1393
1394\f
1395/* Implementing the Varargs Macros. */
1396
1397\f
1398/* Trampolines for Nested Functions. */
1399
1400/* Giving A-function and B-function,
1401 if B-function wants to call A-function's nested function,
1402 we need to fill trampoline code into A-function's stack
1403 so that B-function can execute the code in stack to indirectly
1404 jump to (like 'trampoline' action) desired nested function.
1405
1406 The trampoline code for nds32 target must contains following parts:
1407
1408 1. instructions (4 * 4 = 16 bytes):
8a498f99
CJW		 1409 get $pc first
1410 load chain_value to static chain register via $pc
1411 load nested function address to $r15 via $pc
1412 jump to desired nested function via $r15
9304f876 1413 2. data (4 * 2 = 8 bytes):
8a498f99
CJW		 1414 chain_value
1415 nested function address
9304f876
CJW		 1416
1417 Please check nds32.c implementation for more information. */
1418#define TRAMPOLINE_SIZE 24
1419
1420/* Because all instructions/data in trampoline template are 4-byte size,
1421 we set trampoline alignment 8*4=32 bits. */
1422#define TRAMPOLINE_ALIGNMENT 32
1423
1424\f
1425/* Implicit Calls to Library Routines. */
1426
1427\f
1428/* Addressing Modes. */
1429
1430/* We can use "LWI.bi Rt, [Ra], 4" to support post increment. */
1431#define HAVE_POST_INCREMENT 1
1432/* We can use "LWI.bi Rt, [Ra], -4" to support post decrement. */
1433#define HAVE_POST_DECREMENT 1
1434
1435/* We have "LWI.bi Rt, [Ra], imm" instruction form. */
1436#define HAVE_POST_MODIFY_DISP 1
1437/* We have "LW.bi Rt, [Ra], Rb" instruction form. */
1438#define HAVE_POST_MODIFY_REG 1
1439
c411e9aa
SC		 1440#define USE_LOAD_POST_INCREMENT(mode) \
1441 nds32_use_load_post_increment(mode)
1442#define USE_LOAD_POST_DECREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1443#define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
1444#define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1445
9304f876
CJW		 1446#define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
1447
566f31a4 1448#define MAX_REGS_PER_ADDRESS 3
9304f876
CJW		 1449
1450\f
1451/* Anchored Addresses. */
1452
1453\f
1454/* Condition Code Status. */
1455
1456\f
1457/* Describing Relative Costs of Operations. */
1458
1459/* A C expression for the cost of a branch instruction.
1460 A value of 1 is the default;
1461 other values are interpreted relative to that. */
15c193e2 1462#define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1)
9304f876 1463
08ed6d29
CJW		 1464/* Override BRANCH_COST heuristic which empirically produces worse
1465 performance for removing short circuiting from the logical ops. */
1466#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1467
9304f876
CJW		 1468#define SLOW_BYTE_ACCESS 1
1469
1e8552c2 1470#define NO_FUNCTION_CSE 1
9304f876
CJW		 1471
1472\f
1473/* Adjusting the Instruction Scheduler. */
1474
1475\f
1476/* Dividing the Output into Sections (Texts, Data, . . . ). */
1477
1478#define TEXT_SECTION_ASM_OP "\t.text"
1479#define DATA_SECTION_ASM_OP "\t.data"
1480
1481/* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
1482 So we use '.section .bss' alternatively. */
1483#define BSS_SECTION_ASM_OP "\t.section\t.bss"
1484
1485/* Define this macro to be an expression with a nonzero value if jump tables
1486 (for tablejump insns) should be output in the text section,
1487 along with the assembler instructions.
1488 Otherwise, the readonly data section is used. */
1489#define JUMP_TABLES_IN_TEXT_SECTION 1
1490
1491\f
1492/* Position Independent Code. */
1493
64a08b7f
CJW		 1494#define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
1495
85a98076
KLC		 1496#define SYMBOLIC_CONST_P(X) \
1497(GET_CODE (X) == SYMBOL_REF \
1498 || GET_CODE (X) == LABEL_REF \
1499 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1500
9304f876
CJW		 1501\f
1502/* Defining the Output Assembler Language. */
1503
1504#define ASM_COMMENT_START "!"
1505
c77562ca 1506#define ASM_APP_ON "! #APP\n"
9304f876
CJW		 1507
1508#define ASM_APP_OFF "! #NO_APP\n"
1509
1510#define ASM_OUTPUT_LABELREF(stream, name) \
1511 asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
1512
1513#define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
1514 assemble_name (stream, XSTR (sym, 0))
1515
1516#define ASM_OUTPUT_LABEL_REF(stream, buf) \
1517 assemble_name (stream, buf)
1518
1519#define LOCAL_LABEL_PREFIX "."
1520
71d8eff1
CJW		 1521#define REGISTER_NAMES \
1522{ "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
9304f876
CJW		 1523 "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \
1524 "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
1525 "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \
e2286268
MC		 1526 "$AP", "$SFP", "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", \
1527 "$fs6", "$fs7", "$fs8", "$fs9", "$fs10","$fs11","$fs12","$fs13",\
1528 "$fs14","$fs15","$fs16","$fs17","$fs18","$fs19","$fs20","$fs21",\
1529 "$fs22","$fs23","$fs24","$fs25","$fs26","$fs27","$fs28","$fs29",\
1530 "$fs30","$fs31","$fs32","$fs33","$fs34","$fs35","$fs36","$fs37",\
1531 "$fs38","$fs39","$fs40","$fs41","$fs42","$fs43","$fs44","$fs45",\
1532 "$fs46","$fs47","$fs48","$fs49","$fs50","$fs51","$fs52","$fs53",\
1533 "$fs54","$fs55","$fs56","$fs57","$fs58","$fs59","$fs60","$fs61",\
1534 "$fs62","$fs63", "LB", "LE", "LC" \
1535}
1536
1537#define ADDITIONAL_REGISTER_NAMES \
1538{ \
1539 {"$r15", 15}, \
1540 {"$r28", 28}, {"$r29", 29}, {"$r30", 30}, {"$r31", 31}, \
1541 {"$a0", 0}, {"$a1", 1}, {"$a2", 2}, \
1542 {"$a3", 3}, {"$a4", 4}, {"$a5", 5}, \
1543 {"$s0", 6}, {"$s1", 7}, {"$s2", 8}, {"$s3", 9}, \
1544 {"$s4", 10}, {"$s5", 11}, {"$s6", 12}, {"$s7", 13}, \
1545 {"$s8", 14}, \
1546 {"$t0", 16}, {"$t1", 17}, {"$t2", 18}, {"$t3", 19}, \
1547 {"$t4", 20}, {"$t5", 21}, {"$t6", 22}, {"$t7", 23}, \
1548 {"$t8", 24}, {"$t9", 25}, \
1549 {"$p0", 26}, {"$p1", 27}, \
1550 {"$h0", 0}, {"$h1", 1}, {"$h2", 2}, {"$h3", 3}, \
1551 {"$h4", 4}, {"$h5", 5}, {"$h6", 6}, {"$h7", 7}, \
1552 {"$h8", 8}, {"$h9", 9}, {"$h10", 10}, {"$h11", 11}, \
1553 {"$h12", 16}, {"$h13", 17}, {"$h14", 18}, {"$h15", 19}, \
1554 {"$o0", 0}, {"$o1", 1}, {"$o2", 2}, {"$o3", 3}, \
1555 {"$o4", 4}, {"$o5", 5}, {"$o6", 6}, {"$o7", 7}, \
1556}
1557
1558#define OVERLAPPING_REGISTER_NAMES \
1559{ \
1560 {"$fd0", NDS32_FIRST_FPR_REGNUM + 0, 2}, \
1561 {"$fd1", NDS32_FIRST_FPR_REGNUM + 2, 2}, \
1562 {"$fd2", NDS32_FIRST_FPR_REGNUM + 4, 2}, \
1563 {"$fd3", NDS32_FIRST_FPR_REGNUM + 6, 2}, \
1564 {"$fd4", NDS32_FIRST_FPR_REGNUM + 8, 2}, \
1565 {"$fd5", NDS32_FIRST_FPR_REGNUM + 10, 2}, \
1566 {"$fd6", NDS32_FIRST_FPR_REGNUM + 12, 2}, \
1567 {"$fd7", NDS32_FIRST_FPR_REGNUM + 14, 2}, \
1568 {"$fd8", NDS32_FIRST_FPR_REGNUM + 16, 2}, \
1569 {"$fd9", NDS32_FIRST_FPR_REGNUM + 18, 2}, \
1570 {"$fd10", NDS32_FIRST_FPR_REGNUM + 20, 2}, \
1571 {"$fd11", NDS32_FIRST_FPR_REGNUM + 22, 2}, \
1572 {"$fd12", NDS32_FIRST_FPR_REGNUM + 24, 2}, \
1573 {"$fd13", NDS32_FIRST_FPR_REGNUM + 26, 2}, \
1574 {"$fd14", NDS32_FIRST_FPR_REGNUM + 28, 2}, \
1575 {"$fd15", NDS32_FIRST_FPR_REGNUM + 30, 2}, \
1576 {"$fd16", NDS32_FIRST_FPR_REGNUM + 32, 2}, \
1577 {"$fd17", NDS32_FIRST_FPR_REGNUM + 34, 2}, \
1578 {"$fd18", NDS32_FIRST_FPR_REGNUM + 36, 2}, \
1579 {"$fd19", NDS32_FIRST_FPR_REGNUM + 38, 2}, \
1580 {"$fd20", NDS32_FIRST_FPR_REGNUM + 40, 2}, \
1581 {"$fd21", NDS32_FIRST_FPR_REGNUM + 42, 2}, \
1582 {"$fd22", NDS32_FIRST_FPR_REGNUM + 44, 2}, \
1583 {"$fd23", NDS32_FIRST_FPR_REGNUM + 46, 2}, \
1584 {"$fd24", NDS32_FIRST_FPR_REGNUM + 48, 2}, \
1585 {"$fd25", NDS32_FIRST_FPR_REGNUM + 50, 2}, \
1586 {"$fd26", NDS32_FIRST_FPR_REGNUM + 52, 2}, \
1587 {"$fd27", NDS32_FIRST_FPR_REGNUM + 54, 2}, \
1588 {"$fd28", NDS32_FIRST_FPR_REGNUM + 56, 2}, \
1589 {"$fd29", NDS32_FIRST_FPR_REGNUM + 58, 2}, \
1590 {"$fd30", NDS32_FIRST_FPR_REGNUM + 60, 2}, \
1591 {"$fd31", NDS32_FIRST_FPR_REGNUM + 62, 2}, \
9304f876
CJW		 1592}
1593
1594/* Output normal jump table entry. */
1595#define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
1596 asm_fprintf (stream, "\t.word\t%LL%d\n", value)
1597
1598/* Output pc relative jump table entry. */
1599#define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel) \
1600 do \
1601 { \
1602 switch (GET_MODE (body)) \
1603 { \
4e10a5a7 1604 case E_QImode: \
9304f876
CJW		 1605 asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \
1606 break; \
4e10a5a7 1607 case E_HImode: \
9304f876
CJW		 1608 asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \
1609 break; \
4e10a5a7 1610 case E_SImode: \
9304f876
CJW		 1611 asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \
1612 break; \
1613 default: \
1614 gcc_unreachable(); \
1615 } \
1616 } while (0)
1617
1618/* We have to undef it first because elfos.h formerly define it
1619 check gcc/config.gcc and gcc/config/elfos.h for more information. */
1620#undef ASM_OUTPUT_CASE_LABEL
1621#define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table) \
1622 do \
1623 { \
1624 asm_fprintf (stream, "\t! Jump Table Begin\n"); \
1625 (*targetm.asm_out.internal_label) (stream, prefix, num); \
1626 } while (0)
1627
1628#define ASM_OUTPUT_CASE_END(stream, num, table) \
1629 do \
1630 { \
1631 /* Because our jump table is in text section, \
8a498f99
CJW		 1632 we need to make sure 2-byte alignment after \
1633 the jump table for instructions fetch. */ \
9304f876 1634 if (GET_MODE (PATTERN (table)) == QImode) \
8a498f99 1635 ASM_OUTPUT_ALIGN (stream, 1); \
9304f876
CJW		 1636 asm_fprintf (stream, "\t! Jump Table End\n"); \
1637 } while (0)
1638
1639/* This macro is not documented yet.
1640 But we do need it to make jump table vector aligned. */
1641#define ADDR_VEC_ALIGN(JUMPTABLE) 2
1642
1643#define DWARF2_UNWIND_INFO 1
1644
1645#define JUMP_ALIGN(x) \
1646 (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
1647
1648#define LOOP_ALIGN(x) \
1649 (align_loops_log ? align_loops_log : nds32_target_alignment (x))
1650
1651#define LABEL_ALIGN(x) \
1652 (align_labels_log ? align_labels_log : nds32_target_alignment (x))
1653
1654#define ASM_OUTPUT_ALIGN(stream, power) \
1655 fprintf (stream, "\t.align\t%d\n", power)
1656
1657\f
1658/* Controlling Debugging Information Format. */
1659
1660#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1661
1662#define DWARF2_DEBUGGING_INFO 1
1663
1664#define DWARF2_ASM_LINE_DEBUG_INFO 1
1665
1666\f
1667/* Cross Compilation and Floating Point. */
1668
1669\f
1670/* Mode Switching Instructions. */
1671
1672\f
1673/* Defining target-specific uses of __attribute__. */
1674
1675\f
1676/* Emulating TLS. */
1677
1678\f
1679/* Defining coprocessor specifics for MIPS targets. */
1680
1681\f
1682/* Parameters for Precompiled Header Validity Checking. */
1683
1684\f
1685/* C++ ABI parameters. */
1686
1687\f
1688/* Adding support for named address spaces. */
1689
1690\f
1691/* Miscellaneous Parameters. */
1692
1693/* This is the machine mode that elements of a jump-table should have. */
1694#define CASE_VECTOR_MODE Pmode
1695
1696/* Return the preferred mode for and addr_diff_vec when the mininum
1697 and maximum offset are known. */
1698#define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \
2f1bb3ca 1699 nds32_case_vector_shorten_mode (min_offset, max_offset, body)
9304f876
CJW		 1700
1701/* Generate pc relative jump table when -fpic or -Os. */
1702#define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1703
1704/* Define this macro if operations between registers with integral mode
1705 smaller than a word are always performed on the entire register. */
9e11bfef 1706#define WORD_REGISTER_OPERATIONS 1
9304f876
CJW		 1707
1708/* A C expression indicating when insns that read memory in mem_mode,
1709 an integral mode narrower than a word, set the bits outside of mem_mode
1710 to be either the sign-extension or the zero-extension of the data read. */
1711#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1712
1713/* The maximum number of bytes that a single instruction can move quickly
1714 between memory and registers or between two memory locations. */
1715#define MOVE_MAX 4
1716
1717/* A C expression that is nonzero if on this machine the number of bits
1718 actually used for the count of a shift operation is equal to the number
1719 of bits needed to represent the size of the object being shifted. */
1720#define SHIFT_COUNT_TRUNCATED 1
1721
9304f876
CJW		 1722/* A C expression describing the value returned by a comparison operator with
1723 an integral mode and stored by a store-flag instruction ('cstoremode4')
1724 when the condition is true. */
1725#define STORE_FLAG_VALUE 1
1726
24a71166
CJW		 1727/* A C expression that indicates whether the architecture defines a value for
1728 clz or ctz with a zero operand. In nds32 clz for 0 result 32 is defined
1729 in ISA spec */
1730#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
1731
9304f876
CJW		 1732/* An alias for the machine mode for pointers. */
1733#define Pmode SImode
1734
1735/* An alias for the machine mode used for memory references to functions
1736 being called, in call RTL expressions. */
1737#define FUNCTION_MODE SImode
1738
1739/* ------------------------------------------------------------------------ */
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