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9304f876 | 1 | /* Definitions of target machine of Andes NDS32 cpu for GNU compiler |
85ec4feb | 2 | Copyright (C) 2012-2018 Free Software Foundation, Inc. |
9304f876 CJW |
3 | Contributed by Andes Technology Corporation. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 3, or (at your | |
10 | option) any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* ------------------------------------------------------------------------ */ | |
23 | ||
24 | /* The following are auxiliary macros or structure declarations | |
25 | that are used all over the nds32.c and nds32.h. */ | |
26 | ||
511a41d7 CJW |
27 | /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag. |
28 | It is used in nds32_encode_section_info() to store flag in symbol_ref | |
29 | in case the symbol should be placed in .rodata section. | |
30 | So that we can check it in nds32_legitimate_address_p(). */ | |
31 | #define NDS32_SYMBOL_FLAG_RODATA \ | |
32 | (SYMBOL_FLAG_MACH_DEP << 0) | |
33 | #define NDS32_SYMBOL_REF_RODATA_P(x) \ | |
34 | ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0) | |
9304f876 | 35 | |
6e9ca932 CJW |
36 | /* Classifies expand result for expand helper function. */ |
37 | enum nds32_expand_result_type | |
38 | { | |
39 | EXPAND_DONE, | |
40 | EXPAND_FAIL, | |
41 | EXPAND_CREATE_TEMPLATE | |
42 | }; | |
43 | ||
9304f876 CJW |
44 | /* Computing the Length of an Insn. */ |
45 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
46 | (LENGTH = nds32_adjust_insn_length (INSN, LENGTH)) | |
47 | ||
48 | /* Check instruction LS-37-FP-implied form. | |
49 | Note: actually its immediate range is imm9u | |
50 | since it is used for lwi37/swi37 instructions. */ | |
51 | #define NDS32_LS_37_FP_P(rt, ra, imm) \ | |
52 | (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \ | |
53 | && REGNO (ra) == FP_REGNUM \ | |
54 | && satisfies_constraint_Iu09 (imm)) | |
55 | ||
56 | /* Check instruction LS-37-SP-implied form. | |
57 | Note: actually its immediate range is imm9u | |
58 | since it is used for lwi37/swi37 instructions. */ | |
59 | #define NDS32_LS_37_SP_P(rt, ra, imm) \ | |
60 | (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \ | |
61 | && REGNO (ra) == SP_REGNUM \ | |
62 | && satisfies_constraint_Iu09 (imm)) | |
63 | ||
64 | ||
65 | /* Check load/store instruction form : Rt3, Ra3, imm3u. */ | |
66 | #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode) | |
67 | ||
68 | /* Check load/store instruction form : Rt4, Ra5, const_int_0. | |
69 | Note: no need to check ra because Ra5 means it covers all registers. */ | |
70 | #define NDS32_LS_450_P(rt, ra, imm) \ | |
71 | ((imm == const0_rtx) \ | |
72 | && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \ | |
73 | || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS)) | |
74 | ||
75 | /* Check instruction RRI-333-form. */ | |
76 | #define NDS32_RRI_333_P(rt, ra, imm) \ | |
77 | (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \ | |
78 | && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \ | |
79 | && satisfies_constraint_Iu03 (imm)) | |
80 | ||
81 | /* Check instruction RI-45-form. */ | |
82 | #define NDS32_RI_45_P(rt, ra, imm) \ | |
83 | (REGNO (rt) == REGNO (ra) \ | |
84 | && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \ | |
85 | || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \ | |
86 | && satisfies_constraint_Iu05 (imm)) | |
87 | ||
88 | ||
89 | /* Check instruction RR-33-form. */ | |
90 | #define NDS32_RR_33_P(rt, ra) \ | |
91 | (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \ | |
92 | && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS) | |
93 | ||
94 | /* Check instruction RRR-333-form. */ | |
95 | #define NDS32_RRR_333_P(rt, ra, rb) \ | |
96 | (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \ | |
97 | && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \ | |
98 | && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS) | |
99 | ||
100 | /* Check instruction RR-45-form. | |
101 | Note: no need to check rb because Rb5 means it covers all registers. */ | |
102 | #define NDS32_RR_45_P(rt, ra, rb) \ | |
103 | (REGNO (rt) == REGNO (ra) \ | |
104 | && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \ | |
105 | || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS)) | |
106 | ||
107 | /* Classifies address type to distinguish 16-bit/32-bit format. */ | |
108 | enum nds32_16bit_address_type | |
109 | { | |
110 | /* [reg]: 45 format address. */ | |
111 | ADDRESS_REG, | |
112 | /* [lo_reg + imm3u]: 333 format address. */ | |
113 | ADDRESS_LO_REG_IMM3U, | |
114 | /* post_inc [lo_reg + imm3u]: 333 format address. */ | |
115 | ADDRESS_POST_INC_LO_REG_IMM3U, | |
116 | /* [$fp + imm7u]: fp imply address. */ | |
117 | ADDRESS_FP_IMM7U, | |
118 | /* [$sp + imm7u]: sp imply address. */ | |
119 | ADDRESS_SP_IMM7U, | |
120 | /* Other address format. */ | |
121 | ADDRESS_NOT_16BIT_FORMAT | |
122 | }; | |
123 | ||
124 | ||
125 | /* ------------------------------------------------------------------------ */ | |
126 | ||
127 | /* Define maximum numbers of registers for passing arguments. */ | |
9d93cc24 | 128 | #define NDS32_MAX_GPR_REGS_FOR_ARGS 6 |
9304f876 CJW |
129 | |
130 | /* Define the register number for first argument. */ | |
131 | #define NDS32_GPR_ARG_FIRST_REGNUM 0 | |
132 | ||
133 | /* Define the register number for return value. */ | |
134 | #define NDS32_GPR_RET_FIRST_REGNUM 0 | |
135 | ||
9d93cc24 CJW |
136 | /* Define the first integer register number. */ |
137 | #define NDS32_FIRST_GPR_REGNUM 0 | |
138 | /* Define the last integer register number. */ | |
139 | #define NDS32_LAST_GPR_REGNUM 31 | |
9304f876 | 140 | |
a6c7e777 MC |
141 | #define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6 |
142 | #define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \ | |
143 | (TARGET_REDUCED_REGS ? 10 : 14) | |
144 | ||
9304f876 CJW |
145 | /* Define double word alignment bits. */ |
146 | #define NDS32_DOUBLE_WORD_ALIGNMENT 64 | |
147 | ||
148 | /* Define alignment checking macros for convenience. */ | |
149 | #define NDS32_HALF_WORD_ALIGN_P(value) (((value) & 0x01) == 0) | |
150 | #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0) | |
151 | #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0) | |
152 | ||
634bdae9 CJW |
153 | /* Get alignment according to mode or type information. |
154 | When 'type' is nonnull, there is no need to look at 'mode'. */ | |
155 | #define NDS32_MODE_TYPE_ALIGN(mode, type) \ | |
156 | (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) | |
157 | ||
9304f876 CJW |
158 | /* Round X up to the nearest double word. */ |
159 | #define NDS32_ROUND_UP_DOUBLE_WORD(value) (((value) + 7) & ~7) | |
160 | ||
161 | ||
162 | /* This macro is used to calculate the numbers of registers for | |
163 | containing 'size' bytes of the argument. | |
164 | The size of a register is a word in nds32 target. | |
165 | So we use UNITS_PER_WORD to do the calculation. */ | |
166 | #define NDS32_NEED_N_REGS_FOR_ARG(mode, type) \ | |
167 | ((mode == BLKmode) \ | |
168 | ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \ | |
169 | : ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
170 | ||
171 | /* This macro is used to return the register number for passing argument. | |
172 | We need to obey the following rules: | |
173 | 1. If it is required MORE THAN one register, | |
8a498f99 CJW |
174 | we need to further check if it really needs to be |
175 | aligned on double words. | |
176 | a) If double word alignment is necessary, | |
177 | the register number must be even value. | |
178 | b) Otherwise, the register number can be odd or even value. | |
9304f876 | 179 | 2. If it is required ONLY one register, |
8a498f99 CJW |
180 | the register number can be odd or even value. */ |
181 | #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \ | |
182 | ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \ | |
183 | ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \ | |
184 | ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \ | |
185 | : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \ | |
9304f876 CJW |
186 | : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) |
187 | ||
188 | /* This macro is to check if there are still available registers | |
7f6cd86b CJW |
189 | for passing argument, which must be entirely in registers. */ |
190 | #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \ | |
191 | ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \ | |
192 | + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \ | |
193 | <= (NDS32_GPR_ARG_FIRST_REGNUM \ | |
194 | + NDS32_MAX_GPR_REGS_FOR_ARGS)) | |
195 | ||
196 | /* This macro is to check if there are still available registers | |
197 | for passing argument, either entirely in registers or partially | |
198 | in registers. */ | |
199 | #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \ | |
200 | (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \ | |
201 | < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS) | |
9304f876 CJW |
202 | |
203 | /* This macro is to check if the register is required to be saved on stack. | |
204 | If call_used_regs[regno] == 0, regno is the callee-saved register. | |
205 | If df_regs_ever_live_p(regno) == true, it is used in the current function. | |
206 | As long as the register satisfies both criteria above, | |
207 | it is required to be saved. */ | |
208 | #define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \ | |
209 | ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno))) | |
210 | ||
a6c7e777 MC |
211 | /* This macro is to check if the push25/pop25 are available to be used |
212 | for code generation. Because pop25 also performs return behavior, | |
213 | the instructions may not be available for some cases. | |
214 | If we want to use push25/pop25, all the following conditions must | |
215 | be satisfied: | |
216 | 1. TARGET_V3PUSH is set. | |
217 | 2. Current function is not an ISR function. | |
218 | 3. Current function is not a variadic function.*/ | |
219 | #define NDS32_V3PUSH_AVAILABLE_P \ | |
220 | (TARGET_V3PUSH \ | |
221 | && !nds32_isr_function_p (current_function_decl) \ | |
222 | && (cfun->machine->va_args_size == 0)) | |
223 | ||
9304f876 CJW |
224 | /* ------------------------------------------------------------------------ */ |
225 | ||
226 | /* A C structure for machine-specific, per-function data. | |
227 | This is added to the cfun structure. */ | |
228 | struct GTY(()) machine_function | |
229 | { | |
230 | /* Number of bytes allocated on the stack for variadic args | |
231 | if we want to push them into stack as pretend arguments by ourself. */ | |
232 | int va_args_size; | |
233 | /* Number of bytes reserved on the stack for | |
234 | local and temporary variables. */ | |
235 | int local_size; | |
236 | /* Number of bytes allocated on the stack for outgoing arguments. */ | |
237 | int out_args_size; | |
238 | ||
239 | /* Number of bytes on the stack for saving $fp. */ | |
240 | int fp_size; | |
241 | /* Number of bytes on the stack for saving $gp. */ | |
242 | int gp_size; | |
243 | /* Number of bytes on the stack for saving $lp. */ | |
244 | int lp_size; | |
245 | ||
c457f751 CJW |
246 | /* Number of bytes on the stack for saving general purpose |
247 | callee-saved registers. */ | |
248 | int callee_saved_gpr_regs_size; | |
249 | ||
9304f876 | 250 | /* The padding bytes in callee-saved area may be required. */ |
c457f751 | 251 | int callee_saved_area_gpr_padding_bytes; |
9304f876 | 252 | |
c457f751 CJW |
253 | /* The first required general purpose callee-saved register. */ |
254 | int callee_saved_first_gpr_regno; | |
255 | /* The last required general purpose callee-saved register. */ | |
256 | int callee_saved_last_gpr_regno; | |
9304f876 | 257 | |
dd1536a7 CJW |
258 | /* The padding bytes in varargs area may be required. */ |
259 | int va_args_area_padding_bytes; | |
260 | ||
261 | /* The first required register that should be saved on stack for va_args. */ | |
262 | int va_args_first_regno; | |
263 | /* The last required register that should be saved on stack for va_args. */ | |
264 | int va_args_last_regno; | |
265 | ||
9304f876 CJW |
266 | /* Indicate that whether this function needs |
267 | prologue/epilogue code generation. */ | |
268 | int naked_p; | |
269 | /* Indicate that whether this function | |
270 | uses fp_as_gp optimization. */ | |
271 | int fp_as_gp_p; | |
272 | }; | |
273 | ||
274 | /* A C structure that contains the arguments information. */ | |
275 | typedef struct | |
276 | { | |
9d93cc24 | 277 | unsigned int gpr_offset; |
9304f876 CJW |
278 | } nds32_cumulative_args; |
279 | ||
280 | /* ------------------------------------------------------------------------ */ | |
281 | ||
282 | /* The following we define C-ISR related stuff. | |
283 | In nds32 architecture, we have 73 vectors for interrupt/exception. | |
284 | For each vector (except for vector 0, which is used for reset behavior), | |
285 | we allow users to set its register saving scheme and interrupt level. */ | |
286 | ||
287 | /* There are 73 vectors in nds32 architecture. | |
288 | 0 for reset handler, | |
289 | 1-8 for exception handler, | |
290 | and 9-72 for interrupt handler. | |
291 | We use an array, which is defined in nds32.c, to record | |
292 | essential information for each vector. */ | |
293 | #define NDS32_N_ISR_VECTORS 73 | |
294 | ||
295 | /* Define possible isr category. */ | |
296 | enum nds32_isr_category | |
297 | { | |
298 | NDS32_ISR_NONE, | |
299 | NDS32_ISR_INTERRUPT, | |
300 | NDS32_ISR_EXCEPTION, | |
301 | NDS32_ISR_RESET | |
302 | }; | |
303 | ||
304 | /* Define isr register saving scheme. */ | |
305 | enum nds32_isr_save_reg | |
306 | { | |
307 | NDS32_SAVE_ALL, | |
308 | NDS32_PARTIAL_SAVE | |
309 | }; | |
310 | ||
311 | /* Define isr nested type. */ | |
312 | enum nds32_isr_nested_type | |
313 | { | |
314 | NDS32_NESTED, | |
315 | NDS32_NOT_NESTED, | |
316 | NDS32_NESTED_READY | |
317 | }; | |
318 | ||
319 | /* Define structure to record isr information. | |
320 | The isr vector array 'isr_vectors[]' with this structure | |
321 | is defined in nds32.c. */ | |
322 | struct nds32_isr_info | |
323 | { | |
324 | /* The field to identify isr category. | |
325 | It should be set to NDS32_ISR_NONE by default. | |
326 | If user specifies a function as isr by using attribute, | |
327 | this field will be set accordingly. */ | |
328 | enum nds32_isr_category category; | |
329 | ||
330 | /* A string for the applied function name. | |
331 | It should be set to empty string by default. */ | |
332 | char func_name[100]; | |
333 | ||
334 | /* The register saving scheme. | |
335 | It should be set to NDS32_PARTIAL_SAVE by default | |
336 | unless user specifies attribute to change it. */ | |
337 | enum nds32_isr_save_reg save_reg; | |
338 | ||
339 | /* The nested type. | |
340 | It should be set to NDS32_NOT_NESTED by default | |
341 | unless user specifies attribute to change it. */ | |
342 | enum nds32_isr_nested_type nested_type; | |
343 | ||
344 | /* Total vectors. | |
345 | The total vectors = interrupt + exception numbers + reset. | |
346 | It should be set to 0 by default. | |
347 | This field is ONLY used in NDS32_ISR_RESET category. */ | |
348 | unsigned int total_n_vectors; | |
349 | ||
350 | /* A string for nmi handler name. | |
351 | It should be set to empty string by default. | |
352 | This field is ONLY used in NDS32_ISR_RESET category. */ | |
353 | char nmi_name[100]; | |
354 | ||
355 | /* A string for warm handler name. | |
356 | It should be set to empty string by default. | |
357 | This field is ONLY used in NDS32_ISR_RESET category. */ | |
358 | char warm_name[100]; | |
359 | }; | |
360 | ||
361 | /* ------------------------------------------------------------------------ */ | |
362 | ||
363 | /* Define code for all nds32 builtins. */ | |
364 | enum nds32_builtins | |
365 | { | |
366 | NDS32_BUILTIN_ISYNC, | |
367 | NDS32_BUILTIN_ISB, | |
368 | NDS32_BUILTIN_MFSR, | |
369 | NDS32_BUILTIN_MFUSR, | |
370 | NDS32_BUILTIN_MTSR, | |
371 | NDS32_BUILTIN_MTUSR, | |
372 | NDS32_BUILTIN_SETGIE_EN, | |
7a12ea32 | 373 | NDS32_BUILTIN_SETGIE_DIS, |
3999578c MC |
374 | NDS32_BUILTIN_FFB, |
375 | NDS32_BUILTIN_FFMISM, | |
376 | NDS32_BUILTIN_FLMISM, | |
e576ddb5 KC |
377 | NDS32_BUILTIN_UALOAD_HW, |
378 | NDS32_BUILTIN_UALOAD_W, | |
379 | NDS32_BUILTIN_UALOAD_DW, | |
380 | NDS32_BUILTIN_UASTORE_HW, | |
381 | NDS32_BUILTIN_UASTORE_W, | |
382 | NDS32_BUILTIN_UASTORE_DW, | |
7a12ea32 | 383 | NDS32_BUILTIN_COUNT |
9304f876 CJW |
384 | }; |
385 | ||
386 | /* ------------------------------------------------------------------------ */ | |
387 | ||
388 | #define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2) | |
389 | #define TARGET_ISA_V3 (nds32_arch_option == ARCH_V3) | |
390 | #define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M) | |
391 | ||
77b7a1ca CJW |
392 | #define TARGET_CMODEL_SMALL \ |
393 | (nds32_cmodel_option == CMODEL_SMALL) | |
394 | #define TARGET_CMODEL_MEDIUM \ | |
395 | (nds32_cmodel_option == CMODEL_MEDIUM) | |
396 | #define TARGET_CMODEL_LARGE \ | |
397 | (nds32_cmodel_option == CMODEL_LARGE) | |
398 | ||
399 | /* When -mcmodel=small or -mcmodel=medium, | |
400 | compiler may generate gp-base instruction directly. */ | |
401 | #define TARGET_GP_DIRECT \ | |
402 | (nds32_cmodel_option == CMODEL_SMALL\ | |
403 | || nds32_cmodel_option == CMODEL_MEDIUM) | |
404 | ||
d4a6a4d9 CJW |
405 | #define TARGET_SOFT_FLOAT 1 |
406 | #define TARGET_HARD_FLOAT 0 | |
407 | ||
9304f876 CJW |
408 | /* ------------------------------------------------------------------------ */ |
409 | \f | |
410 | /* Controlling the Compilation Driver. */ | |
411 | ||
412 | #define OPTION_DEFAULT_SPECS \ | |
413 | {"arch", "%{!march=*:-march=%(VALUE)}" } | |
414 | ||
415 | #define CC1_SPEC \ | |
416 | "" | |
417 | ||
418 | #define ASM_SPEC \ | |
419 | " %{mbig-endian:-EB} %{mlittle-endian:-EL}" | |
420 | ||
2ca1ca65 | 421 | /* If user issues -mrelax, we need to pass '--relax' to linker. */ |
9304f876 CJW |
422 | #define LINK_SPEC \ |
423 | " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ | |
2ca1ca65 | 424 | " %{mrelax:--relax}" |
9304f876 CJW |
425 | |
426 | #define LIB_SPEC \ | |
427 | " -lc -lgloss" | |
428 | ||
429 | /* The option -mno-ctor-dtor can disable constructor/destructor feature | |
430 | by applying different crt stuff. In the convention, crt0.o is the | |
431 | startup file without constructor/destructor; | |
432 | crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the | |
433 | startup files with constructor/destructor. | |
434 | Note that crt0.o, crt1.o, crti.o, and crtn.o are provided | |
435 | by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are | |
436 | currently provided by GCC for nds32 target. | |
437 | ||
438 | For nds32 target so far: | |
439 | If -mno-ctor-dtor, we are going to link | |
440 | "crt0.o [user objects]". | |
441 | If general cases, we are going to link | |
442 | "crt1.o crtbegin1.o [user objects] crtend1.o". */ | |
443 | #define STARTFILE_SPEC \ | |
444 | " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \ | |
445 | " %{!mno-ctor-dtor:crtbegin1.o%s}" | |
446 | #define ENDFILE_SPEC \ | |
447 | " %{!mno-ctor-dtor:crtend1.o%s}" | |
448 | ||
c9eb51a7 CJW |
449 | /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we |
450 | configure gcc with --target=nds32be-* setting. | |
451 | Check gcc/config.gcc for more information. */ | |
9304f876 | 452 | #ifdef TARGET_BIG_ENDIAN_DEFAULT |
c9eb51a7 | 453 | # define NDS32_ENDIAN_DEFAULT "mbig-endian" |
9304f876 | 454 | #else |
c9eb51a7 | 455 | # define NDS32_ENDIAN_DEFAULT "mlittle-endian" |
9304f876 CJW |
456 | #endif |
457 | ||
c9eb51a7 CJW |
458 | /* Currently we only have elf toolchain, |
459 | where -mcmodel=medium is always the default. */ | |
460 | #define NDS32_CMODEL_DEFAULT "mcmodel=medium" | |
461 | ||
462 | #define MULTILIB_DEFAULTS \ | |
463 | { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT } | |
464 | ||
9304f876 CJW |
465 | \f |
466 | /* Run-time Target Specification. */ | |
467 | ||
72b7e5e1 KC |
468 | #define TARGET_CPU_CPP_BUILTINS() \ |
469 | nds32_cpu_cpp_builtins (pfile) | |
9304f876 CJW |
470 | |
471 | \f | |
472 | /* Defining Data Structures for Per-function Information. */ | |
473 | ||
474 | /* This macro is called once per function, | |
475 | before generation of any RTL has begun. */ | |
476 | #define INIT_EXPANDERS nds32_init_expanders () | |
477 | ||
478 | \f | |
479 | /* Storage Layout. */ | |
480 | ||
481 | #define BITS_BIG_ENDIAN 0 | |
482 | ||
483 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN) | |
484 | ||
485 | #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN) | |
486 | ||
487 | #define UNITS_PER_WORD 4 | |
488 | ||
489 | #define PROMOTE_MODE(m, unsignedp, type) \ | |
490 | if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \ | |
491 | { \ | |
492 | (m) = SImode; \ | |
493 | } | |
494 | ||
495 | #define PARM_BOUNDARY 32 | |
496 | ||
497 | #define STACK_BOUNDARY 64 | |
498 | ||
499 | #define FUNCTION_BOUNDARY 32 | |
500 | ||
501 | #define BIGGEST_ALIGNMENT 64 | |
502 | ||
503 | #define EMPTY_FIELD_BOUNDARY 32 | |
504 | ||
505 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
506 | ||
507 | #define STRICT_ALIGNMENT 1 | |
508 | ||
509 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
510 | ||
511 | \f | |
512 | /* Layout of Source Language Data Types. */ | |
513 | ||
514 | #define INT_TYPE_SIZE 32 | |
515 | #define SHORT_TYPE_SIZE 16 | |
516 | #define LONG_TYPE_SIZE 32 | |
517 | #define LONG_LONG_TYPE_SIZE 64 | |
518 | ||
519 | #define FLOAT_TYPE_SIZE 32 | |
520 | #define DOUBLE_TYPE_SIZE 64 | |
521 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
522 | ||
523 | #define DEFAULT_SIGNED_CHAR 1 | |
524 | ||
525 | #define SIZE_TYPE "long unsigned int" | |
526 | #define PTRDIFF_TYPE "long int" | |
7f983342 CJW |
527 | #define WCHAR_TYPE "unsigned int" |
528 | #define WCHAR_TYPE_SIZE 32 | |
9304f876 CJW |
529 | |
530 | \f | |
531 | /* Register Usage. */ | |
532 | ||
533 | /* Number of actual hardware registers. | |
534 | The hardware registers are assigned numbers for the compiler | |
535 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
536 | All registers that the compiler knows about must be given numbers, | |
537 | even those that are not normally considered general registers. */ | |
71d8eff1 | 538 | #define FIRST_PSEUDO_REGISTER 101 |
9304f876 CJW |
539 | |
540 | /* An initializer that says which registers are used for fixed | |
541 | purposes all throughout the compiled code and are therefore | |
542 | not available for general allocation. | |
543 | ||
544 | $r28 : $fp | |
545 | $r29 : $gp | |
546 | $r30 : $lp | |
547 | $r31 : $sp | |
548 | ||
549 | caller-save registers: $r0 ~ $r5, $r16 ~ $r23 | |
550 | callee-save registers: $r6 ~ $r10, $r11 ~ $r14 | |
551 | ||
552 | reserved for assembler : $r15 | |
553 | reserved for other use : $r24, $r25, $r26, $r27 */ | |
71d8eff1 CJW |
554 | #define FIXED_REGISTERS \ |
555 | { /* r0 r1 r2 r3 r4 r5 r6 r7 */ \ | |
556 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
557 | /* r8 r9 r10 r11 r12 r13 r14 r15 */ \ | |
558 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
559 | /* r16 r17 r18 r19 r20 r21 r22 r23 */ \ | |
560 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
561 | /* r24 r25 r26 r27 r28 r29 r30 r31 */ \ | |
562 | 1, 1, 1, 1, 0, 1, 0, 1, \ | |
563 | /* AP FP Reserved.................... */ \ | |
564 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
565 | /* Reserved............................... */ \ | |
566 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
567 | /* Reserved............................... */ \ | |
568 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
569 | /* Reserved............................... */ \ | |
570 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
571 | /* Reserved............................... */ \ | |
572 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
573 | /* Reserved............................... */ \ | |
574 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
575 | /* Reserved............................... */ \ | |
576 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
577 | /* Reserved............................... */ \ | |
578 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
579 | /* Reserved............................... */ \ | |
580 | 1, 1, 1, 1, 1 \ | |
9304f876 CJW |
581 | } |
582 | ||
583 | /* Identifies the registers that are not available for | |
584 | general allocation of values that must live across | |
585 | function calls -- so they are caller-save registers. | |
586 | ||
587 | 0 : callee-save registers | |
588 | 1 : caller-save registers */ | |
71d8eff1 CJW |
589 | #define CALL_USED_REGISTERS \ |
590 | { /* r0 r1 r2 r3 r4 r5 r6 r7 */ \ | |
591 | 1, 1, 1, 1, 1, 1, 0, 0, \ | |
592 | /* r8 r9 r10 r11 r12 r13 r14 r15 */ \ | |
593 | 0, 0, 0, 0, 0, 0, 0, 1, \ | |
594 | /* r16 r17 r18 r19 r20 r21 r22 r23 */ \ | |
595 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
596 | /* r24 r25 r26 r27 r28 r29 r30 r31 */ \ | |
597 | 1, 1, 1, 1, 0, 1, 0, 1, \ | |
598 | /* AP FP Reserved.................... */ \ | |
599 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
600 | /* Reserved............................... */ \ | |
601 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
602 | /* Reserved............................... */ \ | |
603 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
604 | /* Reserved............................... */ \ | |
605 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
606 | /* Reserved............................... */ \ | |
607 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
608 | /* Reserved............................... */ \ | |
609 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
610 | /* Reserved............................... */ \ | |
611 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
612 | /* Reserved............................... */ \ | |
613 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
614 | /* Reserved............................... */ \ | |
615 | 1, 1, 1, 1, 1 \ | |
9304f876 CJW |
616 | } |
617 | ||
618 | /* In nds32 target, we have three levels of registers: | |
619 | LOW_COST_REGS : $r0 ~ $r7 | |
620 | MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19 | |
621 | HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */ | |
71d8eff1 CJW |
622 | #define REG_ALLOC_ORDER \ |
623 | { 0, 1, 2, 3, 4, 5, 6, 7, \ | |
624 | 16, 17, 18, 19, 9, 10, 11, 12, \ | |
625 | 13, 14, 8, 15, 20, 21, 22, 23, \ | |
626 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
627 | 32, 33, 34, 35, 36, 37, 38, 39, \ | |
628 | 40, 41, 42, 43, 44, 45, 46, 47, \ | |
629 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
630 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
631 | 64, 65, 66, 67, 68, 69, 70, 71, \ | |
632 | 72, 73, 74, 75, 76, 77, 78, 79, \ | |
633 | 80, 81, 82, 83, 84, 85, 86, 87, \ | |
634 | 88, 89, 90, 91, 92, 93, 94, 95, \ | |
635 | 96, 97, 98, 99, 100, \ | |
9304f876 CJW |
636 | } |
637 | ||
5e6ae0cc CJW |
638 | /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order |
639 | to be rearranged based on optimizing for speed or size. */ | |
640 | #define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order () | |
641 | ||
9304f876 CJW |
642 | /* Tell IRA to use the order we define rather than messing it up with its |
643 | own cost calculations. */ | |
96092404 | 644 | #define HONOR_REG_ALLOC_ORDER optimize_size |
9304f876 | 645 | |
9304f876 CJW |
646 | \f |
647 | /* Register Classes. */ | |
648 | ||
649 | /* In nds32 target, we have three levels of registers: | |
650 | Low cost regsiters : $r0 ~ $r7 | |
651 | Middle cost registers : $r8 ~ $r11, $r16 ~ $r19 | |
652 | High cost registers : $r12 ~ $r14, $r20 ~ $r31 | |
653 | ||
654 | In practice, we have MIDDLE_REGS cover LOW_REGS register class contents | |
655 | so that it provides more chance to use low cost registers. */ | |
656 | enum reg_class | |
657 | { | |
658 | NO_REGS, | |
36f28760 CJW |
659 | R5_REG, |
660 | R8_REG, | |
9304f876 CJW |
661 | R15_TA_REG, |
662 | STACK_REG, | |
36f28760 | 663 | FRAME_POINTER_REG, |
9304f876 CJW |
664 | LOW_REGS, |
665 | MIDDLE_REGS, | |
666 | HIGH_REGS, | |
667 | GENERAL_REGS, | |
668 | FRAME_REGS, | |
669 | ALL_REGS, | |
670 | LIM_REG_CLASSES | |
671 | }; | |
672 | ||
673 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
674 | ||
675 | #define REG_CLASS_NAMES \ | |
676 | { \ | |
677 | "NO_REGS", \ | |
36f28760 CJW |
678 | "R5_REG", \ |
679 | "R8_REG", \ | |
9304f876 CJW |
680 | "R15_TA_REG", \ |
681 | "STACK_REG", \ | |
36f28760 | 682 | "FRAME_POINTER_REG", \ |
9304f876 CJW |
683 | "LOW_REGS", \ |
684 | "MIDDLE_REGS", \ | |
685 | "HIGH_REGS", \ | |
686 | "GENERAL_REGS", \ | |
687 | "FRAME_REGS", \ | |
688 | "ALL_REGS" \ | |
689 | } | |
690 | ||
691 | #define REG_CLASS_CONTENTS \ | |
71d8eff1 CJW |
692 | { /* NO_REGS */ \ |
693 | {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \ | |
694 | /* R5_REG : 5 */ \ | |
695 | {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \ | |
696 | /* R8_REG : 8 */ \ | |
697 | {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \ | |
698 | /* R15_TA_REG : 15 */ \ | |
699 | {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \ | |
700 | /* STACK_REG : 31 */ \ | |
701 | {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \ | |
702 | /* FRAME_POINTER_REG : 28 */ \ | |
703 | {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \ | |
704 | /* LOW_REGS : 0-7 */ \ | |
705 | {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \ | |
706 | /* MIDDLE_REGS : 0-11, 16-19 */ \ | |
707 | {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \ | |
708 | /* HIGH_REGS : 12-14, 20-31 */ \ | |
709 | {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \ | |
710 | /* GENERAL_REGS : 0-31 */ \ | |
711 | {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \ | |
712 | /* FRAME_REGS : 32, 33 */ \ | |
713 | {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \ | |
714 | /* ALL_REGS : 0-100 */ \ | |
715 | {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f} \ | |
9304f876 CJW |
716 | } |
717 | ||
718 | #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno) | |
719 | ||
720 | #define BASE_REG_CLASS GENERAL_REGS | |
721 | #define INDEX_REG_CLASS GENERAL_REGS | |
722 | ||
723 | /* Return nonzero if it is suitable for use as a | |
724 | base register in operand addresses. | |
725 | So far, we return nonzero only if "num" is a hard reg | |
726 | of the suitable class or a pseudo register which is | |
727 | allocated to a suitable hard reg. */ | |
728 | #define REGNO_OK_FOR_BASE_P(num) \ | |
729 | ((num) < 32 || (unsigned) reg_renumber[num] < 32) | |
730 | ||
731 | /* Return nonzero if it is suitable for use as a | |
732 | index register in operand addresses. | |
733 | So far, we return nonzero only if "num" is a hard reg | |
734 | of the suitable class or a pseudo register which is | |
735 | allocated to a suitable hard reg. | |
736 | The difference between an index register and a base register is that | |
737 | the index register may be scaled. */ | |
738 | #define REGNO_OK_FOR_INDEX_P(num) \ | |
739 | ((num) < 32 || (unsigned) reg_renumber[num] < 32) | |
740 | ||
741 | \f | |
742 | /* Obsolete Macros for Defining Constraints. */ | |
743 | ||
744 | \f | |
745 | /* Stack Layout and Calling Conventions. */ | |
746 | ||
62f9f30b | 747 | #define STACK_GROWS_DOWNWARD 1 |
9304f876 CJW |
748 | |
749 | #define FRAME_GROWS_DOWNWARD 1 | |
750 | ||
9304f876 CJW |
751 | #define STACK_POINTER_OFFSET 0 |
752 | ||
4f44e960 CJW |
753 | #define FIRST_PARM_OFFSET(fundecl) \ |
754 | (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4) | |
9304f876 CJW |
755 | |
756 | #define RETURN_ADDR_RTX(count, frameaddr) \ | |
757 | nds32_return_addr_rtx (count, frameaddr) | |
758 | ||
759 | /* A C expression whose value is RTL representing the location | |
760 | of the incoming return address at the beginning of any function | |
761 | before the prologue. | |
762 | If this RTL is REG, you should also define | |
763 | DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO). */ | |
764 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM) | |
765 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM) | |
766 | ||
767 | #define STACK_POINTER_REGNUM SP_REGNUM | |
768 | ||
769 | #define FRAME_POINTER_REGNUM 33 | |
770 | ||
771 | #define HARD_FRAME_POINTER_REGNUM FP_REGNUM | |
772 | ||
773 | #define ARG_POINTER_REGNUM 32 | |
774 | ||
775 | #define STATIC_CHAIN_REGNUM 16 | |
776 | ||
777 | #define ELIMINABLE_REGS \ | |
778 | { { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
779 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
780 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
781 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } } | |
782 | ||
783 | #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \ | |
784 | (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg) | |
785 | ||
786 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
787 | ||
788 | #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1 | |
789 | ||
790 | #define CUMULATIVE_ARGS nds32_cumulative_args | |
791 | ||
792 | #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \ | |
793 | nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args) | |
794 | ||
795 | /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0. | |
796 | We better cast REGNO into signed integer so that we can avoid | |
797 | 'comparison of unsigned expression >= 0 is always true' warning. */ | |
798 | #define FUNCTION_ARG_REGNO_P(regno) \ | |
799 | (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0) \ | |
9d93cc24 | 800 | && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_GPR_REGS_FOR_ARGS)) |
9304f876 CJW |
801 | |
802 | #define DEFAULT_PCC_STRUCT_RETURN 0 | |
803 | ||
804 | /* EXIT_IGNORE_STACK should be nonzero if, when returning | |
805 | from a function, the stack pointer does not matter. | |
806 | The value is tested only in functions that have frame pointers. | |
807 | In nds32 target, the function epilogue recovers the | |
808 | stack pointer from the frame. */ | |
809 | #define EXIT_IGNORE_STACK 1 | |
810 | ||
811 | #define FUNCTION_PROFILER(file, labelno) \ | |
9e362bd0 CJW |
812 | fprintf (file, "/* profiler %d */\n", (labelno)) |
813 | ||
814 | #define PROFILE_HOOK(LABEL) \ | |
815 | { \ | |
816 | rtx fun, lp; \ | |
817 | lp = get_hard_reg_initial_val (Pmode, LP_REGNUM); \ | |
818 | fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \ | |
819 | emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode); \ | |
820 | } | |
9304f876 CJW |
821 | |
822 | \f | |
823 | /* Implementing the Varargs Macros. */ | |
824 | ||
825 | \f | |
826 | /* Trampolines for Nested Functions. */ | |
827 | ||
828 | /* Giving A-function and B-function, | |
829 | if B-function wants to call A-function's nested function, | |
830 | we need to fill trampoline code into A-function's stack | |
831 | so that B-function can execute the code in stack to indirectly | |
832 | jump to (like 'trampoline' action) desired nested function. | |
833 | ||
834 | The trampoline code for nds32 target must contains following parts: | |
835 | ||
836 | 1. instructions (4 * 4 = 16 bytes): | |
8a498f99 CJW |
837 | get $pc first |
838 | load chain_value to static chain register via $pc | |
839 | load nested function address to $r15 via $pc | |
840 | jump to desired nested function via $r15 | |
9304f876 | 841 | 2. data (4 * 2 = 8 bytes): |
8a498f99 CJW |
842 | chain_value |
843 | nested function address | |
9304f876 CJW |
844 | |
845 | Please check nds32.c implementation for more information. */ | |
846 | #define TRAMPOLINE_SIZE 24 | |
847 | ||
848 | /* Because all instructions/data in trampoline template are 4-byte size, | |
849 | we set trampoline alignment 8*4=32 bits. */ | |
850 | #define TRAMPOLINE_ALIGNMENT 32 | |
851 | ||
852 | \f | |
853 | /* Implicit Calls to Library Routines. */ | |
854 | ||
855 | \f | |
856 | /* Addressing Modes. */ | |
857 | ||
858 | /* We can use "LWI.bi Rt, [Ra], 4" to support post increment. */ | |
859 | #define HAVE_POST_INCREMENT 1 | |
860 | /* We can use "LWI.bi Rt, [Ra], -4" to support post decrement. */ | |
861 | #define HAVE_POST_DECREMENT 1 | |
862 | ||
863 | /* We have "LWI.bi Rt, [Ra], imm" instruction form. */ | |
864 | #define HAVE_POST_MODIFY_DISP 1 | |
865 | /* We have "LW.bi Rt, [Ra], Rb" instruction form. */ | |
866 | #define HAVE_POST_MODIFY_REG 1 | |
867 | ||
868 | #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE) | |
869 | ||
566f31a4 | 870 | #define MAX_REGS_PER_ADDRESS 3 |
9304f876 CJW |
871 | |
872 | \f | |
873 | /* Anchored Addresses. */ | |
874 | ||
875 | \f | |
876 | /* Condition Code Status. */ | |
877 | ||
878 | \f | |
879 | /* Describing Relative Costs of Operations. */ | |
880 | ||
881 | /* A C expression for the cost of a branch instruction. | |
882 | A value of 1 is the default; | |
883 | other values are interpreted relative to that. */ | |
15c193e2 | 884 | #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1) |
9304f876 | 885 | |
08ed6d29 CJW |
886 | /* Override BRANCH_COST heuristic which empirically produces worse |
887 | performance for removing short circuiting from the logical ops. */ | |
888 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 | |
889 | ||
9304f876 CJW |
890 | #define SLOW_BYTE_ACCESS 1 |
891 | ||
1e8552c2 | 892 | #define NO_FUNCTION_CSE 1 |
9304f876 CJW |
893 | |
894 | \f | |
895 | /* Adjusting the Instruction Scheduler. */ | |
896 | ||
897 | \f | |
898 | /* Dividing the Output into Sections (Texts, Data, . . . ). */ | |
899 | ||
900 | #define TEXT_SECTION_ASM_OP "\t.text" | |
901 | #define DATA_SECTION_ASM_OP "\t.data" | |
902 | ||
903 | /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op. | |
904 | So we use '.section .bss' alternatively. */ | |
905 | #define BSS_SECTION_ASM_OP "\t.section\t.bss" | |
906 | ||
907 | /* Define this macro to be an expression with a nonzero value if jump tables | |
908 | (for tablejump insns) should be output in the text section, | |
909 | along with the assembler instructions. | |
910 | Otherwise, the readonly data section is used. */ | |
911 | #define JUMP_TABLES_IN_TEXT_SECTION 1 | |
912 | ||
913 | \f | |
914 | /* Position Independent Code. */ | |
915 | ||
64a08b7f CJW |
916 | #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM |
917 | ||
9304f876 CJW |
918 | \f |
919 | /* Defining the Output Assembler Language. */ | |
920 | ||
921 | #define ASM_COMMENT_START "!" | |
922 | ||
923 | #define ASM_APP_ON "! #APP" | |
924 | ||
925 | #define ASM_APP_OFF "! #NO_APP\n" | |
926 | ||
927 | #define ASM_OUTPUT_LABELREF(stream, name) \ | |
928 | asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name)) | |
929 | ||
930 | #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \ | |
931 | assemble_name (stream, XSTR (sym, 0)) | |
932 | ||
933 | #define ASM_OUTPUT_LABEL_REF(stream, buf) \ | |
934 | assemble_name (stream, buf) | |
935 | ||
936 | #define LOCAL_LABEL_PREFIX "." | |
937 | ||
71d8eff1 CJW |
938 | #define REGISTER_NAMES \ |
939 | { "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \ | |
9304f876 CJW |
940 | "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \ |
941 | "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \ | |
942 | "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \ | |
71d8eff1 CJW |
943 | "$AP", "$SFP", "NA", "NA", "NA", "NA", "NA", "NA", \ |
944 | "NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \ | |
945 | "NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \ | |
946 | "NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \ | |
947 | "NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \ | |
948 | "NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \ | |
949 | "NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \ | |
950 | "NA", "NA", "NA", "NA", "NA", "NA", "NA", "NA", \ | |
951 | "NA", "NA", "NA", "NA", "NA" \ | |
9304f876 CJW |
952 | } |
953 | ||
954 | /* Output normal jump table entry. */ | |
955 | #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \ | |
956 | asm_fprintf (stream, "\t.word\t%LL%d\n", value) | |
957 | ||
958 | /* Output pc relative jump table entry. */ | |
959 | #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel) \ | |
960 | do \ | |
961 | { \ | |
962 | switch (GET_MODE (body)) \ | |
963 | { \ | |
4e10a5a7 | 964 | case E_QImode: \ |
9304f876 CJW |
965 | asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \ |
966 | break; \ | |
4e10a5a7 | 967 | case E_HImode: \ |
9304f876 CJW |
968 | asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \ |
969 | break; \ | |
4e10a5a7 | 970 | case E_SImode: \ |
9304f876 CJW |
971 | asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \ |
972 | break; \ | |
973 | default: \ | |
974 | gcc_unreachable(); \ | |
975 | } \ | |
976 | } while (0) | |
977 | ||
978 | /* We have to undef it first because elfos.h formerly define it | |
979 | check gcc/config.gcc and gcc/config/elfos.h for more information. */ | |
980 | #undef ASM_OUTPUT_CASE_LABEL | |
981 | #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table) \ | |
982 | do \ | |
983 | { \ | |
984 | asm_fprintf (stream, "\t! Jump Table Begin\n"); \ | |
985 | (*targetm.asm_out.internal_label) (stream, prefix, num); \ | |
986 | } while (0) | |
987 | ||
988 | #define ASM_OUTPUT_CASE_END(stream, num, table) \ | |
989 | do \ | |
990 | { \ | |
991 | /* Because our jump table is in text section, \ | |
8a498f99 CJW |
992 | we need to make sure 2-byte alignment after \ |
993 | the jump table for instructions fetch. */ \ | |
9304f876 | 994 | if (GET_MODE (PATTERN (table)) == QImode) \ |
8a498f99 | 995 | ASM_OUTPUT_ALIGN (stream, 1); \ |
9304f876 CJW |
996 | asm_fprintf (stream, "\t! Jump Table End\n"); \ |
997 | } while (0) | |
998 | ||
999 | /* This macro is not documented yet. | |
1000 | But we do need it to make jump table vector aligned. */ | |
1001 | #define ADDR_VEC_ALIGN(JUMPTABLE) 2 | |
1002 | ||
1003 | #define DWARF2_UNWIND_INFO 1 | |
1004 | ||
1005 | #define JUMP_ALIGN(x) \ | |
1006 | (align_jumps_log ? align_jumps_log : nds32_target_alignment (x)) | |
1007 | ||
1008 | #define LOOP_ALIGN(x) \ | |
1009 | (align_loops_log ? align_loops_log : nds32_target_alignment (x)) | |
1010 | ||
1011 | #define LABEL_ALIGN(x) \ | |
1012 | (align_labels_log ? align_labels_log : nds32_target_alignment (x)) | |
1013 | ||
1014 | #define ASM_OUTPUT_ALIGN(stream, power) \ | |
1015 | fprintf (stream, "\t.align\t%d\n", power) | |
1016 | ||
1017 | \f | |
1018 | /* Controlling Debugging Information Format. */ | |
1019 | ||
1020 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
1021 | ||
1022 | #define DWARF2_DEBUGGING_INFO 1 | |
1023 | ||
1024 | #define DWARF2_ASM_LINE_DEBUG_INFO 1 | |
1025 | ||
1026 | \f | |
1027 | /* Cross Compilation and Floating Point. */ | |
1028 | ||
1029 | \f | |
1030 | /* Mode Switching Instructions. */ | |
1031 | ||
1032 | \f | |
1033 | /* Defining target-specific uses of __attribute__. */ | |
1034 | ||
1035 | \f | |
1036 | /* Emulating TLS. */ | |
1037 | ||
1038 | \f | |
1039 | /* Defining coprocessor specifics for MIPS targets. */ | |
1040 | ||
1041 | \f | |
1042 | /* Parameters for Precompiled Header Validity Checking. */ | |
1043 | ||
1044 | \f | |
1045 | /* C++ ABI parameters. */ | |
1046 | ||
1047 | \f | |
1048 | /* Adding support for named address spaces. */ | |
1049 | ||
1050 | \f | |
1051 | /* Miscellaneous Parameters. */ | |
1052 | ||
1053 | /* This is the machine mode that elements of a jump-table should have. */ | |
1054 | #define CASE_VECTOR_MODE Pmode | |
1055 | ||
1056 | /* Return the preferred mode for and addr_diff_vec when the mininum | |
1057 | and maximum offset are known. */ | |
1058 | #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \ | |
1059 | ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode \ | |
1060 | : (max_offset >= 100) ? HImode \ | |
1061 | : QImode) | |
1062 | ||
1063 | /* Generate pc relative jump table when -fpic or -Os. */ | |
1064 | #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size) | |
1065 | ||
1066 | /* Define this macro if operations between registers with integral mode | |
1067 | smaller than a word are always performed on the entire register. */ | |
9e11bfef | 1068 | #define WORD_REGISTER_OPERATIONS 1 |
9304f876 CJW |
1069 | |
1070 | /* A C expression indicating when insns that read memory in mem_mode, | |
1071 | an integral mode narrower than a word, set the bits outside of mem_mode | |
1072 | to be either the sign-extension or the zero-extension of the data read. */ | |
1073 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
1074 | ||
1075 | /* The maximum number of bytes that a single instruction can move quickly | |
1076 | between memory and registers or between two memory locations. */ | |
1077 | #define MOVE_MAX 4 | |
1078 | ||
1079 | /* A C expression that is nonzero if on this machine the number of bits | |
1080 | actually used for the count of a shift operation is equal to the number | |
1081 | of bits needed to represent the size of the object being shifted. */ | |
1082 | #define SHIFT_COUNT_TRUNCATED 1 | |
1083 | ||
9304f876 CJW |
1084 | /* A C expression describing the value returned by a comparison operator with |
1085 | an integral mode and stored by a store-flag instruction ('cstoremode4') | |
1086 | when the condition is true. */ | |
1087 | #define STORE_FLAG_VALUE 1 | |
1088 | ||
24a71166 CJW |
1089 | /* A C expression that indicates whether the architecture defines a value for |
1090 | clz or ctz with a zero operand. In nds32 clz for 0 result 32 is defined | |
1091 | in ISA spec */ | |
1092 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) | |
1093 | ||
9304f876 CJW |
1094 | /* An alias for the machine mode for pointers. */ |
1095 | #define Pmode SImode | |
1096 | ||
1097 | /* An alias for the machine mode used for memory references to functions | |
1098 | being called, in call RTL expressions. */ | |
1099 | #define FUNCTION_MODE SImode | |
1100 | ||
1101 | /* ------------------------------------------------------------------------ */ |