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[NDS32] Support dwarf exception handling.
[thirdparty/gcc.git] / gcc / config / nds32 / nds32.h
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9304f876 1/* Definitions of target machine of Andes NDS32 cpu for GNU compiler
85ec4feb 2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
9304f876
CJW		 3 Contributed by Andes Technology Corporation.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21
22/* ------------------------------------------------------------------------ */
23
24/* The following are auxiliary macros or structure declarations
25 that are used all over the nds32.c and nds32.h. */
26
a5876228
CJW		 27#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
28 (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
29
511a41d7
CJW		 30/* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
31 It is used in nds32_encode_section_info() to store flag in symbol_ref
32 in case the symbol should be placed in .rodata section.
33 So that we can check it in nds32_legitimate_address_p(). */
34#define NDS32_SYMBOL_FLAG_RODATA \
35 (SYMBOL_FLAG_MACH_DEP << 0)
36#define NDS32_SYMBOL_REF_RODATA_P(x) \
37 ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
9304f876 38
6e9ca932
CJW		 39/* Classifies expand result for expand helper function. */
40enum nds32_expand_result_type
41{
42 EXPAND_DONE,
43 EXPAND_FAIL,
44 EXPAND_CREATE_TEMPLATE
45};
46
9304f876
CJW		 47/* Classifies address type to distinguish 16-bit/32-bit format. */
48enum nds32_16bit_address_type
49{
50 /* [reg]: 45 format address. */
51 ADDRESS_REG,
52 /* [lo_reg + imm3u]: 333 format address. */
53 ADDRESS_LO_REG_IMM3U,
54 /* post_inc [lo_reg + imm3u]: 333 format address. */
55 ADDRESS_POST_INC_LO_REG_IMM3U,
67e1eb3d
SC		 56 /* post_modify [lo_reg + imm3u]: 333 format address. */
57 ADDRESS_POST_MODIFY_LO_REG_IMM3U,
8656bbcf
SC		 58 /* [$r8 + imm7u]: r8 imply address. */
59 ADDRESS_R8_IMM7U,
9304f876
CJW		 60 /* [$fp + imm7u]: fp imply address. */
61 ADDRESS_FP_IMM7U,
62 /* [$sp + imm7u]: sp imply address. */
63 ADDRESS_SP_IMM7U,
64 /* Other address format. */
65 ADDRESS_NOT_16BIT_FORMAT
66};
67
68
69/* ------------------------------------------------------------------------ */
70
71/* Define maximum numbers of registers for passing arguments. */
9d93cc24 72#define NDS32_MAX_GPR_REGS_FOR_ARGS 6
e2286268 73#define NDS32_MAX_FPR_REGS_FOR_ARGS 6
9304f876
CJW		 74
75/* Define the register number for first argument. */
76#define NDS32_GPR_ARG_FIRST_REGNUM 0
e2286268 77#define NDS32_FPR_ARG_FIRST_REGNUM 34
9304f876
CJW		 78
79/* Define the register number for return value. */
80#define NDS32_GPR_RET_FIRST_REGNUM 0
e2286268 81#define NDS32_FPR_RET_FIRST_REGNUM 34
9304f876 82
9d93cc24
CJW		 83/* Define the first integer register number. */
84#define NDS32_FIRST_GPR_REGNUM 0
85/* Define the last integer register number. */
86#define NDS32_LAST_GPR_REGNUM 31
9304f876 87
a6c7e777
MC		 88#define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6
89#define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \
90 (TARGET_REDUCED_REGS ? 10 : 14)
91
e2286268
MC		 92/* Define the floating-point number of registers. */
93#define NDS32_FLOAT_REGISTER_NUMBER \
94 (((nds32_fp_regnum == NDS32_CONFIG_FPU_0) \
95 || (nds32_fp_regnum == NDS32_CONFIG_FPU_4)) ? 8 \
96 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_1) \
97 || (nds32_fp_regnum == NDS32_CONFIG_FPU_5)) ? 16 \
98 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_2) \
99 || (nds32_fp_regnum == NDS32_CONFIG_FPU_6)) ? 32 \
100 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_3) \
101 || (nds32_fp_regnum == NDS32_CONFIG_FPU_7)) ? 64 \
102 : 32)
103
104#define NDS32_EXT_FPU_DOT_E (nds32_fp_regnum >= 4)
105
106/* Define the first floating-point register number. */
107#define NDS32_FIRST_FPR_REGNUM 34
108/* Define the last floating-point register number. */
109#define NDS32_LAST_FPR_REGNUM \
110 (NDS32_FIRST_FPR_REGNUM + NDS32_FLOAT_REGISTER_NUMBER - 1)
111
112
113#define NDS32_IS_EXT_FPR_REGNUM(regno) \
114 (((regno) >= NDS32_FIRST_FPR_REGNUM + 32) \
115 && ((regno) < NDS32_FIRST_FPR_REGNUM + 64))
116
117#define NDS32_IS_FPR_REGNUM(regno) \
118 (((regno) >= NDS32_FIRST_FPR_REGNUM) \
119 && ((regno) <= NDS32_LAST_FPR_REGNUM))
120
121#define NDS32_FPR_REGNO_OK_FOR_SINGLE(regno) \
122 ((regno) <= NDS32_LAST_FPR_REGNUM)
123
124#define NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) \
125 ((((regno) - NDS32_FIRST_FPR_REGNUM) & 1) == 0)
126
127#define NDS32_IS_GPR_REGNUM(regno) \
128 (((regno) <= NDS32_LAST_GPR_REGNUM))
129
9304f876
CJW		 130/* Define double word alignment bits. */
131#define NDS32_DOUBLE_WORD_ALIGNMENT 64
132
133/* Define alignment checking macros for convenience. */
134#define NDS32_HALF_WORD_ALIGN_P(value) (((value) & 0x01) == 0)
135#define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
136#define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
137
634bdae9
CJW		 138/* Get alignment according to mode or type information.
139 When 'type' is nonnull, there is no need to look at 'mode'. */
140#define NDS32_MODE_TYPE_ALIGN(mode, type) \
141 (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
142
9304f876
CJW		 143/* Round X up to the nearest double word. */
144#define NDS32_ROUND_UP_DOUBLE_WORD(value) (((value) + 7) & ~7)
145
146
147/* This macro is used to calculate the numbers of registers for
148 containing 'size' bytes of the argument.
149 The size of a register is a word in nds32 target.
150 So we use UNITS_PER_WORD to do the calculation. */
151#define NDS32_NEED_N_REGS_FOR_ARG(mode, type) \
152 ((mode == BLKmode) \
153 ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
154 : ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
155
156/* This macro is used to return the register number for passing argument.
157 We need to obey the following rules:
158 1. If it is required MORE THAN one register,
8a498f99
CJW		 159 we need to further check if it really needs to be
160 aligned on double words.
161 a) If double word alignment is necessary,
162 the register number must be even value.
163 b) Otherwise, the register number can be odd or even value.
9304f876 164 2. If it is required ONLY one register,
8a498f99
CJW		 165 the register number can be odd or even value. */
166#define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
167 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
168 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
169 ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
170 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
9304f876
CJW		 171 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
172
e2286268
MC		 173#define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \
174 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
175 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
176 ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1) \
177 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM)) \
178 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
179
180/* These two macros are to check if there are still available registers
7f6cd86b
CJW		 181 for passing argument, which must be entirely in registers. */
182#define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \
183 ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
184 + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \
185 <= (NDS32_GPR_ARG_FIRST_REGNUM \
186 + NDS32_MAX_GPR_REGS_FOR_ARGS))
187
e2286268
MC		 188#define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type) \
189 ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
190 + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \
191 <= (NDS32_FPR_ARG_FIRST_REGNUM \
192 + NDS32_MAX_FPR_REGS_FOR_ARGS))
193
194/* These two macros are to check if there are still available registers
7f6cd86b
CJW		 195 for passing argument, either entirely in registers or partially
196 in registers. */
197#define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
198 (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
199 < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
9304f876 200
e2286268
MC		 201#define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \
202 (NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
203 < NDS32_FPR_ARG_FIRST_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS)
204
9304f876
CJW		 205/* This macro is to check if the register is required to be saved on stack.
206 If call_used_regs[regno] == 0, regno is the callee-saved register.
207 If df_regs_ever_live_p(regno) == true, it is used in the current function.
208 As long as the register satisfies both criteria above,
209 it is required to be saved. */
210#define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \
211 ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
212
a6c7e777
MC		 213/* This macro is to check if the push25/pop25 are available to be used
214 for code generation. Because pop25 also performs return behavior,
215 the instructions may not be available for some cases.
216 If we want to use push25/pop25, all the following conditions must
217 be satisfied:
218 1. TARGET_V3PUSH is set.
219 2. Current function is not an ISR function.
220 3. Current function is not a variadic function.*/
221#define NDS32_V3PUSH_AVAILABLE_P \
222 (TARGET_V3PUSH \
223 && !nds32_isr_function_p (current_function_decl) \
224 && (cfun->machine->va_args_size == 0))
225
9304f876
CJW		 226/* ------------------------------------------------------------------------ */
227
228/* A C structure for machine-specific, per-function data.
229 This is added to the cfun structure. */
230struct GTY(()) machine_function
231{
232 /* Number of bytes allocated on the stack for variadic args
233 if we want to push them into stack as pretend arguments by ourself. */
234 int va_args_size;
235 /* Number of bytes reserved on the stack for
236 local and temporary variables. */
237 int local_size;
238 /* Number of bytes allocated on the stack for outgoing arguments. */
239 int out_args_size;
240
241 /* Number of bytes on the stack for saving $fp. */
242 int fp_size;
243 /* Number of bytes on the stack for saving $gp. */
244 int gp_size;
245 /* Number of bytes on the stack for saving $lp. */
246 int lp_size;
247
c457f751
CJW		 248 /* Number of bytes on the stack for saving general purpose
249 callee-saved registers. */
250 int callee_saved_gpr_regs_size;
251
e2286268
MC		 252 /* Number of bytes on the stack for saving floating-point
253 callee-saved registers. */
254 int callee_saved_fpr_regs_size;
255
9304f876 256 /* The padding bytes in callee-saved area may be required. */
c457f751 257 int callee_saved_area_gpr_padding_bytes;
9304f876 258
c457f751
CJW		 259 /* The first required general purpose callee-saved register. */
260 int callee_saved_first_gpr_regno;
261 /* The last required general purpose callee-saved register. */
262 int callee_saved_last_gpr_regno;
9304f876 263
e2286268
MC		 264 /* The first required floating-point callee-saved register. */
265 int callee_saved_first_fpr_regno;
266 /* The last required floating-point callee-saved register. */
267 int callee_saved_last_fpr_regno;
268
dd1536a7
CJW		 269 /* The padding bytes in varargs area may be required. */
270 int va_args_area_padding_bytes;
271
272 /* The first required register that should be saved on stack for va_args. */
273 int va_args_first_regno;
274 /* The last required register that should be saved on stack for va_args. */
275 int va_args_last_regno;
276
ca3a4a55
CJW		 277 /* Number of bytes on the stack for saving exception handling registers. */
278 int eh_return_data_regs_size;
279 /* The first register of passing exception handling information. */
280 int eh_return_data_first_regno;
281 /* The last register of passing exception handling information. */
282 int eh_return_data_last_regno;
283
284 /* Indicate that whether this function
285 calls __builtin_eh_return. */
286 int use_eh_return_p;
287
9304f876
CJW		 288 /* Indicate that whether this function needs
289 prologue/epilogue code generation. */
290 int naked_p;
291 /* Indicate that whether this function
292 uses fp_as_gp optimization. */
293 int fp_as_gp_p;
294};
295
296/* A C structure that contains the arguments information. */
297typedef struct
298{
9d93cc24 299 unsigned int gpr_offset;
e2286268 300 unsigned int fpr_offset;
9304f876
CJW		 301} nds32_cumulative_args;
302
303/* ------------------------------------------------------------------------ */
304
305/* The following we define C-ISR related stuff.
306 In nds32 architecture, we have 73 vectors for interrupt/exception.
307 For each vector (except for vector 0, which is used for reset behavior),
308 we allow users to set its register saving scheme and interrupt level. */
309
310/* There are 73 vectors in nds32 architecture.
311 0 for reset handler,
312 1-8 for exception handler,
313 and 9-72 for interrupt handler.
314 We use an array, which is defined in nds32.c, to record
315 essential information for each vector. */
316#define NDS32_N_ISR_VECTORS 73
317
318/* Define possible isr category. */
319enum nds32_isr_category
320{
321 NDS32_ISR_NONE,
322 NDS32_ISR_INTERRUPT,
323 NDS32_ISR_EXCEPTION,
324 NDS32_ISR_RESET
325};
326
327/* Define isr register saving scheme. */
328enum nds32_isr_save_reg
329{
330 NDS32_SAVE_ALL,
331 NDS32_PARTIAL_SAVE
332};
333
334/* Define isr nested type. */
335enum nds32_isr_nested_type
336{
337 NDS32_NESTED,
338 NDS32_NOT_NESTED,
339 NDS32_NESTED_READY
340};
341
342/* Define structure to record isr information.
343 The isr vector array 'isr_vectors[]' with this structure
344 is defined in nds32.c. */
345struct nds32_isr_info
346{
347 /* The field to identify isr category.
348 It should be set to NDS32_ISR_NONE by default.
349 If user specifies a function as isr by using attribute,
350 this field will be set accordingly. */
351 enum nds32_isr_category category;
352
353 /* A string for the applied function name.
354 It should be set to empty string by default. */
355 char func_name[100];
356
357 /* The register saving scheme.
358 It should be set to NDS32_PARTIAL_SAVE by default
359 unless user specifies attribute to change it. */
360 enum nds32_isr_save_reg save_reg;
361
362 /* The nested type.
363 It should be set to NDS32_NOT_NESTED by default
364 unless user specifies attribute to change it. */
365 enum nds32_isr_nested_type nested_type;
366
367 /* Total vectors.
368 The total vectors = interrupt + exception numbers + reset.
369 It should be set to 0 by default.
370 This field is ONLY used in NDS32_ISR_RESET category. */
371 unsigned int total_n_vectors;
372
373 /* A string for nmi handler name.
374 It should be set to empty string by default.
375 This field is ONLY used in NDS32_ISR_RESET category. */
376 char nmi_name[100];
377
378 /* A string for warm handler name.
379 It should be set to empty string by default.
380 This field is ONLY used in NDS32_ISR_RESET category. */
381 char warm_name[100];
382};
383
384/* ------------------------------------------------------------------------ */
385
386/* Define code for all nds32 builtins. */
387enum nds32_builtins
388{
389 NDS32_BUILTIN_ISYNC,
390 NDS32_BUILTIN_ISB,
154e3ea6
MC		 391 NDS32_BUILTIN_DSB,
392 NDS32_BUILTIN_MSYNC_ALL,
393 NDS32_BUILTIN_MSYNC_STORE,
9304f876
CJW		 394 NDS32_BUILTIN_MFSR,
395 NDS32_BUILTIN_MFUSR,
396 NDS32_BUILTIN_MTSR,
154e3ea6
MC		 397 NDS32_BUILTIN_MTSR_ISB,
398 NDS32_BUILTIN_MTSR_DSB,
9304f876
CJW		 399 NDS32_BUILTIN_MTUSR,
400 NDS32_BUILTIN_SETGIE_EN,
7a12ea32 401 NDS32_BUILTIN_SETGIE_DIS,
0bb4423d
MC		 402 NDS32_BUILTIN_FMFCFG,
403 NDS32_BUILTIN_FMFCSR,
404 NDS32_BUILTIN_FMTCSR,
405 NDS32_BUILTIN_FCPYNSS,
406 NDS32_BUILTIN_FCPYSS,
407 NDS32_BUILTIN_FCPYNSD,
408 NDS32_BUILTIN_FCPYSD,
2feae6cd
MC		 409 NDS32_BUILTIN_ABS,
410 NDS32_BUILTIN_AVE,
411 NDS32_BUILTIN_BCLR,
412 NDS32_BUILTIN_BSET,
413 NDS32_BUILTIN_BTGL,
414 NDS32_BUILTIN_BTST,
415 NDS32_BUILTIN_CLIP,
416 NDS32_BUILTIN_CLIPS,
417 NDS32_BUILTIN_CLZ,
418 NDS32_BUILTIN_CLO,
419 NDS32_BUILTIN_MAX,
420 NDS32_BUILTIN_MIN,
421 NDS32_BUILTIN_PBSAD,
422 NDS32_BUILTIN_PBSADA,
423 NDS32_BUILTIN_BSE,
424 NDS32_BUILTIN_BSP,
3999578c
MC		 425 NDS32_BUILTIN_FFB,
426 NDS32_BUILTIN_FFMISM,
427 NDS32_BUILTIN_FLMISM,
2feae6cd
MC		 428
429 NDS32_BUILTIN_ROTR,
430 NDS32_BUILTIN_SVA,
431 NDS32_BUILTIN_SVS,
432 NDS32_BUILTIN_WSBH,
433 NDS32_BUILTIN_JR_ITOFF,
434 NDS32_BUILTIN_JR_TOFF,
435 NDS32_BUILTIN_JRAL_ITON,
436 NDS32_BUILTIN_JRAL_TON,
437 NDS32_BUILTIN_RET_ITOFF,
438 NDS32_BUILTIN_RET_TOFF,
439 NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT,
440 NDS32_BUILTIN_STANDBY_WAKE_GRANT,
441 NDS32_BUILTIN_STANDBY_WAKE_DONE,
442 NDS32_BUILTIN_TEQZ,
443 NDS32_BUILTIN_TNEZ,
444 NDS32_BUILTIN_TRAP,
445 NDS32_BUILTIN_SETEND_BIG,
446 NDS32_BUILTIN_SETEND_LITTLE,
447 NDS32_BUILTIN_SYSCALL,
448 NDS32_BUILTIN_BREAK,
449 NDS32_BUILTIN_NOP,
450 NDS32_BUILTIN_SCHE_BARRIER,
451 NDS32_BUILTIN_GET_CURRENT_SP,
452 NDS32_BUILTIN_SET_CURRENT_SP,
453 NDS32_BUILTIN_RETURN_ADDRESS,
154e3ea6
MC		 454 NDS32_BUILTIN_LLW,
455 NDS32_BUILTIN_LWUP,
456 NDS32_BUILTIN_LBUP,
457 NDS32_BUILTIN_SCW,
458 NDS32_BUILTIN_SWUP,
459 NDS32_BUILTIN_SBUP,
f1a0afe2
MC		 460 NDS32_BUILTIN_CCTL_VA_LCK,
461 NDS32_BUILTIN_CCTL_IDX_WBINVAL,
462 NDS32_BUILTIN_CCTL_VA_WBINVAL_L1,
463 NDS32_BUILTIN_CCTL_VA_WBINVAL_LA,
464 NDS32_BUILTIN_CCTL_IDX_READ,
465 NDS32_BUILTIN_CCTL_IDX_WRITE,
466 NDS32_BUILTIN_CCTL_L1D_INVALALL,
467 NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL,
468 NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL,
e576ddb5
KC		 469 NDS32_BUILTIN_UALOAD_HW,
470 NDS32_BUILTIN_UALOAD_W,
471 NDS32_BUILTIN_UALOAD_DW,
472 NDS32_BUILTIN_UASTORE_HW,
473 NDS32_BUILTIN_UASTORE_W,
474 NDS32_BUILTIN_UASTORE_DW,
7a12ea32 475 NDS32_BUILTIN_COUNT
9304f876
CJW		 476};
477
478/* ------------------------------------------------------------------------ */
479
480#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
e2286268
MC		 481
482#define TARGET_ISA_V3 \
483 (nds32_arch_option == ARCH_V3 \
484 || nds32_arch_option == ARCH_V3F \
485 || nds32_arch_option == ARCH_V3S)
9304f876
CJW		 486#define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M)
487
77b7a1ca
CJW		 488#define TARGET_CMODEL_SMALL \
489 (nds32_cmodel_option == CMODEL_SMALL)
490#define TARGET_CMODEL_MEDIUM \
491 (nds32_cmodel_option == CMODEL_MEDIUM)
492#define TARGET_CMODEL_LARGE \
493 (nds32_cmodel_option == CMODEL_LARGE)
494
495/* When -mcmodel=small or -mcmodel=medium,
496 compiler may generate gp-base instruction directly. */
497#define TARGET_GP_DIRECT \
498 (nds32_cmodel_option == CMODEL_SMALL\
499 || nds32_cmodel_option == CMODEL_MEDIUM)
500
d4a6a4d9 501
e2286268
MC		 502/* Run-time Target Specification. */
503#define TARGET_SOFT_FLOAT (nds32_abi == NDS32_ABI_V2)
504/* Use hardware floating point calling convention. */
505#define TARGET_HARD_FLOAT (nds32_abi == NDS32_ABI_V2_FP_PLUS)
506
507/* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI,
508 1 means hard ABI and using full floating-point instruction,
509 2 means hard ABI and only using single-precision floating-point
510 instruction */
511#if TARGET_ARCH_DEFAULT == 1
512# define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
513# define TARGET_DEFAULT_FPU_ISA MASK_FPU_DOUBLE | MASK_FPU_SINGLE
514# define TARGET_DEFAULT_FPU_FMA 0
515#else
516# if TARGET_ARCH_DEFAULT == 2
517# define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
518# define TARGET_DEFAULT_FPU_ISA MASK_FPU_SINGLE
519# define TARGET_DEFAULT_FPU_FMA 0
520# else
521# define TARGET_DEFAULT_ABI NDS32_ABI_V2
522# define TARGET_DEFAULT_FPU_ISA 0
523# define TARGET_DEFAULT_FPU_FMA 0
524# endif
525#endif
526
527#define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2
9304f876
CJW		 528/* ------------------------------------------------------------------------ */
529\f
530/* Controlling the Compilation Driver. */
531
532#define OPTION_DEFAULT_SPECS \
e2286268
MC		 533 {"arch", " %{!march=*:-march=%(VALUE)}" \
534 " %{march=v3f:%{!mfloat-abi=*:-mfloat-abi=hard}" \
535 " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}" \
536 " %{!mno-ext-fpu-dp:%{!mext-fpu-dp:-mext-fpu-dp}}}" \
537 " %{march=v3s:%{!mfloat-abi=*:-mfloat-abi=hard}" \
538 " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}}" }, \
539 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }
9304f876
CJW		 540
541#define CC1_SPEC \
542 ""
543
544#define ASM_SPEC \
e2286268
MC		 545 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
546 " %{march=*:-march=%*}" \
547 " %{mabi=*:-mabi=v%*}" \
548 " %{mconfig-fpu=*:-mfpu-freg=%*}" \
549 " %{mext-fpu-mac:-mmac}" \
550 " %{mno-ext-fpu-mac:-mno-mac}" \
551 " %{mext-fpu-sp:-mfpu-sp-ext}" \
552 " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \
553 " %{mext-fpu-dp:-mfpu-dp-ext}" \
554 " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}"
9304f876 555
2ca1ca65 556/* If user issues -mrelax, we need to pass '--relax' to linker. */
9304f876
CJW		 557#define LINK_SPEC \
558 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
2ca1ca65 559 " %{mrelax:--relax}"
9304f876
CJW		 560
561#define LIB_SPEC \
562 " -lc -lgloss"
563
564/* The option -mno-ctor-dtor can disable constructor/destructor feature
565 by applying different crt stuff. In the convention, crt0.o is the
566 startup file without constructor/destructor;
567 crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
568 startup files with constructor/destructor.
569 Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
570 by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
571 currently provided by GCC for nds32 target.
572
573 For nds32 target so far:
574 If -mno-ctor-dtor, we are going to link
575 "crt0.o [user objects]".
576 If general cases, we are going to link
577 "crt1.o crtbegin1.o [user objects] crtend1.o". */
578#define STARTFILE_SPEC \
579 " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
580 " %{!mno-ctor-dtor:crtbegin1.o%s}"
581#define ENDFILE_SPEC \
582 " %{!mno-ctor-dtor:crtend1.o%s}"
583
c9eb51a7
CJW		 584/* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
585 configure gcc with --target=nds32be-* setting.
586 Check gcc/config.gcc for more information. */
9304f876 587#ifdef TARGET_BIG_ENDIAN_DEFAULT
c9eb51a7 588# define NDS32_ENDIAN_DEFAULT "mbig-endian"
9304f876 589#else
c9eb51a7 590# define NDS32_ENDIAN_DEFAULT "mlittle-endian"
9304f876
CJW		 591#endif
592
c9eb51a7
CJW		 593/* Currently we only have elf toolchain,
594 where -mcmodel=medium is always the default. */
595#define NDS32_CMODEL_DEFAULT "mcmodel=medium"
596
597#define MULTILIB_DEFAULTS \
598 { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
599
9304f876
CJW		 600\f
601/* Run-time Target Specification. */
602
72b7e5e1
KC		 603#define TARGET_CPU_CPP_BUILTINS() \
604 nds32_cpu_cpp_builtins (pfile)
9304f876
CJW		 605
606\f
607/* Defining Data Structures for Per-function Information. */
608
609/* This macro is called once per function,
610 before generation of any RTL has begun. */
611#define INIT_EXPANDERS nds32_init_expanders ()
612
613\f
614/* Storage Layout. */
615
616#define BITS_BIG_ENDIAN 0
617
618#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
619
620#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
621
622#define UNITS_PER_WORD 4
623
624#define PROMOTE_MODE(m, unsignedp, type) \
625 if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
626 { \
627 (m) = SImode; \
628 }
629
630#define PARM_BOUNDARY 32
631
632#define STACK_BOUNDARY 64
633
634#define FUNCTION_BOUNDARY 32
635
636#define BIGGEST_ALIGNMENT 64
637
638#define EMPTY_FIELD_BOUNDARY 32
639
640#define STRUCTURE_SIZE_BOUNDARY 8
641
642#define STRICT_ALIGNMENT 1
643
644#define PCC_BITFIELD_TYPE_MATTERS 1
645
646\f
647/* Layout of Source Language Data Types. */
648
649#define INT_TYPE_SIZE 32
650#define SHORT_TYPE_SIZE 16
651#define LONG_TYPE_SIZE 32
652#define LONG_LONG_TYPE_SIZE 64
653
654#define FLOAT_TYPE_SIZE 32
655#define DOUBLE_TYPE_SIZE 64
656#define LONG_DOUBLE_TYPE_SIZE 64
657
658#define DEFAULT_SIGNED_CHAR 1
659
660#define SIZE_TYPE "long unsigned int"
661#define PTRDIFF_TYPE "long int"
7f983342
CJW		 662#define WCHAR_TYPE "unsigned int"
663#define WCHAR_TYPE_SIZE 32
9304f876
CJW		 664
665\f
666/* Register Usage. */
667
668/* Number of actual hardware registers.
669 The hardware registers are assigned numbers for the compiler
670 from 0 to just below FIRST_PSEUDO_REGISTER.
671 All registers that the compiler knows about must be given numbers,
672 even those that are not normally considered general registers. */
71d8eff1 673#define FIRST_PSEUDO_REGISTER 101
9304f876
CJW		 674
675/* An initializer that says which registers are used for fixed
676 purposes all throughout the compiled code and are therefore
677 not available for general allocation.
678
679 $r28 : $fp
680 $r29 : $gp
681 $r30 : $lp
682 $r31 : $sp
683
e2286268
MC		 684 caller-save registers: $r0 ~ $r5, $r16 ~ $r23, $fs0 ~ $fs5, $fs22 ~ $fs47
685 callee-save registers: $r6 ~ $r10, $r11 ~ $r14, $fs6 ~ $fs21, $fs48 ~ $fs63
9304f876
CJW		 686
687 reserved for assembler : $r15
688 reserved for other use : $r24, $r25, $r26, $r27 */
71d8eff1
CJW		 689#define FIXED_REGISTERS \
690{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
691 0, 0, 0, 0, 0, 0, 0, 0, \
692 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
693 0, 0, 0, 0, 0, 0, 0, 1, \
694 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
695 0, 0, 0, 0, 0, 0, 0, 0, \
696 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
697 1, 1, 1, 1, 0, 1, 0, 1, \
e2286268 698 /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \
71d8eff1 699 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 700 /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \
71d8eff1 701 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 702 /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
71d8eff1 703 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 704 /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
71d8eff1 705 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 706 /* fs30 fs31 fd16 fd17 fd18 */ \
71d8eff1 707 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 708 /* fd19 fd20 fd21 fd22 */ \
71d8eff1 709 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 710 /* fd23 fd24 fd25 fd26 */ \
71d8eff1 711 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 712 /* fd27 fd28 fd29 fd30 */ \
71d8eff1 713 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 714 /* fd31 Reserved..................... */ \
71d8eff1 715 1, 1, 1, 1, 1 \
9304f876
CJW		 716}
717
718/* Identifies the registers that are not available for
719 general allocation of values that must live across
720 function calls -- so they are caller-save registers.
721
722 0 : callee-save registers
723 1 : caller-save registers */
71d8eff1
CJW		 724#define CALL_USED_REGISTERS \
725{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
726 1, 1, 1, 1, 1, 1, 0, 0, \
727 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
728 0, 0, 0, 0, 0, 0, 0, 1, \
729 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
730 1, 1, 1, 1, 1, 1, 1, 1, \
731 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
732 1, 1, 1, 1, 0, 1, 0, 1, \
e2286268 733 /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \
71d8eff1 734 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 735 /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \
71d8eff1 736 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 737 /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
71d8eff1 738 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 739 /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
71d8eff1 740 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 741 /* fs30 fs31 fd16 fd17 fd18 */ \
71d8eff1 742 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 743 /* fd19 fd20 fd21 fd22 */ \
71d8eff1 744 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 745 /* fd23 fd24 fd25 fd26 */ \
71d8eff1 746 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 747 /* fd27 fd28 fd29 fd30 */ \
71d8eff1 748 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 749 /* fd31 Reserved..................... */ \
71d8eff1 750 1, 1, 1, 1, 1 \
9304f876
CJW		 751}
752
753/* In nds32 target, we have three levels of registers:
754 LOW_COST_REGS : $r0 ~ $r7
755 MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
756 HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */
71d8eff1
CJW		 757#define REG_ALLOC_ORDER \
758{ 0, 1, 2, 3, 4, 5, 6, 7, \
759 16, 17, 18, 19, 9, 10, 11, 12, \
760 13, 14, 8, 15, 20, 21, 22, 23, \
761 24, 25, 26, 27, 28, 29, 30, 31, \
762 32, 33, 34, 35, 36, 37, 38, 39, \
763 40, 41, 42, 43, 44, 45, 46, 47, \
764 48, 49, 50, 51, 52, 53, 54, 55, \
765 56, 57, 58, 59, 60, 61, 62, 63, \
766 64, 65, 66, 67, 68, 69, 70, 71, \
767 72, 73, 74, 75, 76, 77, 78, 79, \
768 80, 81, 82, 83, 84, 85, 86, 87, \
769 88, 89, 90, 91, 92, 93, 94, 95, \
770 96, 97, 98, 99, 100, \
9304f876
CJW		 771}
772
5e6ae0cc
CJW		 773/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
774 to be rearranged based on optimizing for speed or size. */
775#define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order ()
776
9304f876
CJW		 777/* Tell IRA to use the order we define rather than messing it up with its
778 own cost calculations. */
96092404 779#define HONOR_REG_ALLOC_ORDER optimize_size
9304f876 780
9304f876
CJW		 781\f
782/* Register Classes. */
783
784/* In nds32 target, we have three levels of registers:
785 Low cost regsiters : $r0 ~ $r7
786 Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
787 High cost registers : $r12 ~ $r14, $r20 ~ $r31
788
789 In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
790 so that it provides more chance to use low cost registers. */
791enum reg_class
792{
793 NO_REGS,
36f28760
CJW		 794 R5_REG,
795 R8_REG,
9304f876
CJW		 796 R15_TA_REG,
797 STACK_REG,
36f28760 798 FRAME_POINTER_REG,
9304f876
CJW		 799 LOW_REGS,
800 MIDDLE_REGS,
801 HIGH_REGS,
802 GENERAL_REGS,
803 FRAME_REGS,
e2286268 804 FP_REGS,
9304f876
CJW		 805 ALL_REGS,
806 LIM_REG_CLASSES
807};
808
809#define N_REG_CLASSES (int) LIM_REG_CLASSES
810
811#define REG_CLASS_NAMES \
812{ \
813 "NO_REGS", \
36f28760
CJW		 814 "R5_REG", \
815 "R8_REG", \
9304f876
CJW		 816 "R15_TA_REG", \
817 "STACK_REG", \
36f28760 818 "FRAME_POINTER_REG", \
9304f876
CJW		 819 "LOW_REGS", \
820 "MIDDLE_REGS", \
821 "HIGH_REGS", \
822 "GENERAL_REGS", \
823 "FRAME_REGS", \
e2286268 824 "FP_REGS", \
9304f876
CJW		 825 "ALL_REGS" \
826}
827
828#define REG_CLASS_CONTENTS \
71d8eff1
CJW		 829{ /* NO_REGS */ \
830 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
831 /* R5_REG : 5 */ \
832 {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
833 /* R8_REG : 8 */ \
834 {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
835 /* R15_TA_REG : 15 */ \
836 {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
837 /* STACK_REG : 31 */ \
838 {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
839 /* FRAME_POINTER_REG : 28 */ \
840 {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
841 /* LOW_REGS : 0-7 */ \
842 {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
843 /* MIDDLE_REGS : 0-11, 16-19 */ \
844 {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
845 /* HIGH_REGS : 12-14, 20-31 */ \
846 {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
847 /* GENERAL_REGS : 0-31 */ \
848 {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
849 /* FRAME_REGS : 32, 33 */ \
850 {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
e2286268
MC		 851 /* FP_REGS : 34-98 */ \
852 {0x00000000, 0xfffffffc, 0xffffffff, 0x00000003}, \
71d8eff1
CJW		 853 /* ALL_REGS : 0-100 */ \
854 {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f} \
9304f876
CJW		 855}
856
857#define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
858
859#define BASE_REG_CLASS GENERAL_REGS
860#define INDEX_REG_CLASS GENERAL_REGS
861
e2286268
MC		 862#define TEST_REGNO(R, TEST, VALUE) \
863 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
864
9304f876
CJW		 865/* Return nonzero if it is suitable for use as a
866 base register in operand addresses.
867 So far, we return nonzero only if "num" is a hard reg
868 of the suitable class or a pseudo register which is
869 allocated to a suitable hard reg. */
870#define REGNO_OK_FOR_BASE_P(num) \
e2286268
MC		 871 (TEST_REGNO (num, <, 32) \
872 || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
873 || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
9304f876
CJW		 874
875/* Return nonzero if it is suitable for use as a
876 index register in operand addresses.
877 So far, we return nonzero only if "num" is a hard reg
878 of the suitable class or a pseudo register which is
879 allocated to a suitable hard reg.
880 The difference between an index register and a base register is that
881 the index register may be scaled. */
882#define REGNO_OK_FOR_INDEX_P(num) \
e2286268
MC		 883 (TEST_REGNO (num, <, 32) \
884 || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
885 || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
9304f876
CJW		 886
887\f
888/* Obsolete Macros for Defining Constraints. */
889
890\f
891/* Stack Layout and Calling Conventions. */
892
62f9f30b 893#define STACK_GROWS_DOWNWARD 1
9304f876
CJW		 894
895#define FRAME_GROWS_DOWNWARD 1
896
9304f876
CJW		 897#define STACK_POINTER_OFFSET 0
898
4f44e960
CJW		 899#define FIRST_PARM_OFFSET(fundecl) \
900 (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
9304f876 901
ca3a4a55
CJW		 902/* A C expression whose value is RTL representing the address in a stack frame
903 where the pointer to the caller's frame is stored. */
904#define DYNAMIC_CHAIN_ADDRESS(frameaddr) \
905 nds32_dynamic_chain_address (frameaddr)
906
9304f876
CJW		 907#define RETURN_ADDR_RTX(count, frameaddr) \
908 nds32_return_addr_rtx (count, frameaddr)
909
910/* A C expression whose value is RTL representing the location
911 of the incoming return address at the beginning of any function
912 before the prologue.
913 If this RTL is REG, you should also define
914 DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO). */
915#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM)
916#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM)
917
ca3a4a55
CJW		 918/* Use $r0 $r1 to pass exception handling information. */
919#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) : INVALID_REGNUM)
920/* The register $r2 that represents a location in which to store a stack
921 adjustment to be applied before function return.
922 This is used to unwind the stack to an exception handler's call frame. */
923#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
924
e2286268
MC		 925#define DBX_REGISTER_NUMBER(REGNO) nds32_dbx_register_number (REGNO)
926
9304f876
CJW		 927#define STACK_POINTER_REGNUM SP_REGNUM
928
929#define FRAME_POINTER_REGNUM 33
930
931#define HARD_FRAME_POINTER_REGNUM FP_REGNUM
932
933#define ARG_POINTER_REGNUM 32
934
935#define STATIC_CHAIN_REGNUM 16
936
937#define ELIMINABLE_REGS \
938{ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
939 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
940 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
941 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
942
943#define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
944 (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
945
946#define ACCUMULATE_OUTGOING_ARGS 1
947
948#define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
949
950#define CUMULATIVE_ARGS nds32_cumulative_args
951
952#define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
953 nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
954
e2286268
MC		 955#define FUNCTION_ARG_REGNO_P(regno) \
956 (IN_RANGE ((regno), NDS32_FIRST_GPR_REGNUM, NDS32_MAX_GPR_REGS_FOR_ARGS - 1) \
957 || ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) \
958 && IN_RANGE ((regno), NDS32_FPR_ARG_FIRST_REGNUM, \
959 NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS - 1)))
9304f876
CJW		 960
961#define DEFAULT_PCC_STRUCT_RETURN 0
962
963/* EXIT_IGNORE_STACK should be nonzero if, when returning
964 from a function, the stack pointer does not matter.
965 The value is tested only in functions that have frame pointers.
966 In nds32 target, the function epilogue recovers the
967 stack pointer from the frame. */
968#define EXIT_IGNORE_STACK 1
969
970#define FUNCTION_PROFILER(file, labelno) \
9e362bd0
CJW		 971 fprintf (file, "/* profiler %d */\n", (labelno))
972
973#define PROFILE_HOOK(LABEL) \
974 { \
975 rtx fun, lp; \
976 lp = get_hard_reg_initial_val (Pmode, LP_REGNUM); \
977 fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \
978 emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode); \
979 }
9304f876
CJW		 980
981\f
982/* Implementing the Varargs Macros. */
983
984\f
985/* Trampolines for Nested Functions. */
986
987/* Giving A-function and B-function,
988 if B-function wants to call A-function's nested function,
989 we need to fill trampoline code into A-function's stack
990 so that B-function can execute the code in stack to indirectly
991 jump to (like 'trampoline' action) desired nested function.
992
993 The trampoline code for nds32 target must contains following parts:
994
995 1. instructions (4 * 4 = 16 bytes):
8a498f99
CJW		 996 get $pc first
997 load chain_value to static chain register via $pc
998 load nested function address to $r15 via $pc
999 jump to desired nested function via $r15
9304f876 1000 2. data (4 * 2 = 8 bytes):
8a498f99
CJW		 1001 chain_value
1002 nested function address
9304f876
CJW		 1003
1004 Please check nds32.c implementation for more information. */
1005#define TRAMPOLINE_SIZE 24
1006
1007/* Because all instructions/data in trampoline template are 4-byte size,
1008 we set trampoline alignment 8*4=32 bits. */
1009#define TRAMPOLINE_ALIGNMENT 32
1010
1011\f
1012/* Implicit Calls to Library Routines. */
1013
1014\f
1015/* Addressing Modes. */
1016
1017/* We can use "LWI.bi Rt, [Ra], 4" to support post increment. */
1018#define HAVE_POST_INCREMENT 1
1019/* We can use "LWI.bi Rt, [Ra], -4" to support post decrement. */
1020#define HAVE_POST_DECREMENT 1
1021
1022/* We have "LWI.bi Rt, [Ra], imm" instruction form. */
1023#define HAVE_POST_MODIFY_DISP 1
1024/* We have "LW.bi Rt, [Ra], Rb" instruction form. */
1025#define HAVE_POST_MODIFY_REG 1
1026
1027#define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
1028
566f31a4 1029#define MAX_REGS_PER_ADDRESS 3
9304f876
CJW		 1030
1031\f
1032/* Anchored Addresses. */
1033
1034\f
1035/* Condition Code Status. */
1036
1037\f
1038/* Describing Relative Costs of Operations. */
1039
1040/* A C expression for the cost of a branch instruction.
1041 A value of 1 is the default;
1042 other values are interpreted relative to that. */
15c193e2 1043#define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1)
9304f876 1044
08ed6d29
CJW		 1045/* Override BRANCH_COST heuristic which empirically produces worse
1046 performance for removing short circuiting from the logical ops. */
1047#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1048
9304f876
CJW		 1049#define SLOW_BYTE_ACCESS 1
1050
1e8552c2 1051#define NO_FUNCTION_CSE 1
9304f876
CJW		 1052
1053\f
1054/* Adjusting the Instruction Scheduler. */
1055
1056\f
1057/* Dividing the Output into Sections (Texts, Data, . . . ). */
1058
1059#define TEXT_SECTION_ASM_OP "\t.text"
1060#define DATA_SECTION_ASM_OP "\t.data"
1061
1062/* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
1063 So we use '.section .bss' alternatively. */
1064#define BSS_SECTION_ASM_OP "\t.section\t.bss"
1065
1066/* Define this macro to be an expression with a nonzero value if jump tables
1067 (for tablejump insns) should be output in the text section,
1068 along with the assembler instructions.
1069 Otherwise, the readonly data section is used. */
1070#define JUMP_TABLES_IN_TEXT_SECTION 1
1071
1072\f
1073/* Position Independent Code. */
1074
64a08b7f
CJW		 1075#define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
1076
9304f876
CJW		 1077\f
1078/* Defining the Output Assembler Language. */
1079
1080#define ASM_COMMENT_START "!"
1081
1082#define ASM_APP_ON "! #APP"
1083
1084#define ASM_APP_OFF "! #NO_APP\n"
1085
1086#define ASM_OUTPUT_LABELREF(stream, name) \
1087 asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
1088
1089#define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
1090 assemble_name (stream, XSTR (sym, 0))
1091
1092#define ASM_OUTPUT_LABEL_REF(stream, buf) \
1093 assemble_name (stream, buf)
1094
1095#define LOCAL_LABEL_PREFIX "."
1096
71d8eff1
CJW		 1097#define REGISTER_NAMES \
1098{ "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
9304f876
CJW		 1099 "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \
1100 "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
1101 "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \
e2286268
MC		 1102 "$AP", "$SFP", "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", \
1103 "$fs6", "$fs7", "$fs8", "$fs9", "$fs10","$fs11","$fs12","$fs13",\
1104 "$fs14","$fs15","$fs16","$fs17","$fs18","$fs19","$fs20","$fs21",\
1105 "$fs22","$fs23","$fs24","$fs25","$fs26","$fs27","$fs28","$fs29",\
1106 "$fs30","$fs31","$fs32","$fs33","$fs34","$fs35","$fs36","$fs37",\
1107 "$fs38","$fs39","$fs40","$fs41","$fs42","$fs43","$fs44","$fs45",\
1108 "$fs46","$fs47","$fs48","$fs49","$fs50","$fs51","$fs52","$fs53",\
1109 "$fs54","$fs55","$fs56","$fs57","$fs58","$fs59","$fs60","$fs61",\
1110 "$fs62","$fs63", "LB", "LE", "LC" \
1111}
1112
1113#define ADDITIONAL_REGISTER_NAMES \
1114{ \
1115 {"$r15", 15}, \
1116 {"$r28", 28}, {"$r29", 29}, {"$r30", 30}, {"$r31", 31}, \
1117 {"$a0", 0}, {"$a1", 1}, {"$a2", 2}, \
1118 {"$a3", 3}, {"$a4", 4}, {"$a5", 5}, \
1119 {"$s0", 6}, {"$s1", 7}, {"$s2", 8}, {"$s3", 9}, \
1120 {"$s4", 10}, {"$s5", 11}, {"$s6", 12}, {"$s7", 13}, \
1121 {"$s8", 14}, \
1122 {"$t0", 16}, {"$t1", 17}, {"$t2", 18}, {"$t3", 19}, \
1123 {"$t4", 20}, {"$t5", 21}, {"$t6", 22}, {"$t7", 23}, \
1124 {"$t8", 24}, {"$t9", 25}, \
1125 {"$p0", 26}, {"$p1", 27}, \
1126 {"$h0", 0}, {"$h1", 1}, {"$h2", 2}, {"$h3", 3}, \
1127 {"$h4", 4}, {"$h5", 5}, {"$h6", 6}, {"$h7", 7}, \
1128 {"$h8", 8}, {"$h9", 9}, {"$h10", 10}, {"$h11", 11}, \
1129 {"$h12", 16}, {"$h13", 17}, {"$h14", 18}, {"$h15", 19}, \
1130 {"$o0", 0}, {"$o1", 1}, {"$o2", 2}, {"$o3", 3}, \
1131 {"$o4", 4}, {"$o5", 5}, {"$o6", 6}, {"$o7", 7}, \
1132}
1133
1134#define OVERLAPPING_REGISTER_NAMES \
1135{ \
1136 {"$fd0", NDS32_FIRST_FPR_REGNUM + 0, 2}, \
1137 {"$fd1", NDS32_FIRST_FPR_REGNUM + 2, 2}, \
1138 {"$fd2", NDS32_FIRST_FPR_REGNUM + 4, 2}, \
1139 {"$fd3", NDS32_FIRST_FPR_REGNUM + 6, 2}, \
1140 {"$fd4", NDS32_FIRST_FPR_REGNUM + 8, 2}, \
1141 {"$fd5", NDS32_FIRST_FPR_REGNUM + 10, 2}, \
1142 {"$fd6", NDS32_FIRST_FPR_REGNUM + 12, 2}, \
1143 {"$fd7", NDS32_FIRST_FPR_REGNUM + 14, 2}, \
1144 {"$fd8", NDS32_FIRST_FPR_REGNUM + 16, 2}, \
1145 {"$fd9", NDS32_FIRST_FPR_REGNUM + 18, 2}, \
1146 {"$fd10", NDS32_FIRST_FPR_REGNUM + 20, 2}, \
1147 {"$fd11", NDS32_FIRST_FPR_REGNUM + 22, 2}, \
1148 {"$fd12", NDS32_FIRST_FPR_REGNUM + 24, 2}, \
1149 {"$fd13", NDS32_FIRST_FPR_REGNUM + 26, 2}, \
1150 {"$fd14", NDS32_FIRST_FPR_REGNUM + 28, 2}, \
1151 {"$fd15", NDS32_FIRST_FPR_REGNUM + 30, 2}, \
1152 {"$fd16", NDS32_FIRST_FPR_REGNUM + 32, 2}, \
1153 {"$fd17", NDS32_FIRST_FPR_REGNUM + 34, 2}, \
1154 {"$fd18", NDS32_FIRST_FPR_REGNUM + 36, 2}, \
1155 {"$fd19", NDS32_FIRST_FPR_REGNUM + 38, 2}, \
1156 {"$fd20", NDS32_FIRST_FPR_REGNUM + 40, 2}, \
1157 {"$fd21", NDS32_FIRST_FPR_REGNUM + 42, 2}, \
1158 {"$fd22", NDS32_FIRST_FPR_REGNUM + 44, 2}, \
1159 {"$fd23", NDS32_FIRST_FPR_REGNUM + 46, 2}, \
1160 {"$fd24", NDS32_FIRST_FPR_REGNUM + 48, 2}, \
1161 {"$fd25", NDS32_FIRST_FPR_REGNUM + 50, 2}, \
1162 {"$fd26", NDS32_FIRST_FPR_REGNUM + 52, 2}, \
1163 {"$fd27", NDS32_FIRST_FPR_REGNUM + 54, 2}, \
1164 {"$fd28", NDS32_FIRST_FPR_REGNUM + 56, 2}, \
1165 {"$fd29", NDS32_FIRST_FPR_REGNUM + 58, 2}, \
1166 {"$fd30", NDS32_FIRST_FPR_REGNUM + 60, 2}, \
1167 {"$fd31", NDS32_FIRST_FPR_REGNUM + 62, 2}, \
9304f876
CJW		 1168}
1169
1170/* Output normal jump table entry. */
1171#define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
1172 asm_fprintf (stream, "\t.word\t%LL%d\n", value)
1173
1174/* Output pc relative jump table entry. */
1175#define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel) \
1176 do \
1177 { \
1178 switch (GET_MODE (body)) \
1179 { \
4e10a5a7 1180 case E_QImode: \
9304f876
CJW		 1181 asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \
1182 break; \
4e10a5a7 1183 case E_HImode: \
9304f876
CJW		 1184 asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \
1185 break; \
4e10a5a7 1186 case E_SImode: \
9304f876
CJW		 1187 asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \
1188 break; \
1189 default: \
1190 gcc_unreachable(); \
1191 } \
1192 } while (0)
1193
1194/* We have to undef it first because elfos.h formerly define it
1195 check gcc/config.gcc and gcc/config/elfos.h for more information. */
1196#undef ASM_OUTPUT_CASE_LABEL
1197#define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table) \
1198 do \
1199 { \
1200 asm_fprintf (stream, "\t! Jump Table Begin\n"); \
1201 (*targetm.asm_out.internal_label) (stream, prefix, num); \
1202 } while (0)
1203
1204#define ASM_OUTPUT_CASE_END(stream, num, table) \
1205 do \
1206 { \
1207 /* Because our jump table is in text section, \
8a498f99
CJW		 1208 we need to make sure 2-byte alignment after \
1209 the jump table for instructions fetch. */ \
9304f876 1210 if (GET_MODE (PATTERN (table)) == QImode) \
8a498f99 1211 ASM_OUTPUT_ALIGN (stream, 1); \
9304f876
CJW		 1212 asm_fprintf (stream, "\t! Jump Table End\n"); \
1213 } while (0)
1214
1215/* This macro is not documented yet.
1216 But we do need it to make jump table vector aligned. */
1217#define ADDR_VEC_ALIGN(JUMPTABLE) 2
1218
1219#define DWARF2_UNWIND_INFO 1
1220
1221#define JUMP_ALIGN(x) \
1222 (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
1223
1224#define LOOP_ALIGN(x) \
1225 (align_loops_log ? align_loops_log : nds32_target_alignment (x))
1226
1227#define LABEL_ALIGN(x) \
1228 (align_labels_log ? align_labels_log : nds32_target_alignment (x))
1229
1230#define ASM_OUTPUT_ALIGN(stream, power) \
1231 fprintf (stream, "\t.align\t%d\n", power)
1232
1233\f
1234/* Controlling Debugging Information Format. */
1235
1236#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1237
1238#define DWARF2_DEBUGGING_INFO 1
1239
1240#define DWARF2_ASM_LINE_DEBUG_INFO 1
1241
1242\f
1243/* Cross Compilation and Floating Point. */
1244
1245\f
1246/* Mode Switching Instructions. */
1247
1248\f
1249/* Defining target-specific uses of __attribute__. */
1250
1251\f
1252/* Emulating TLS. */
1253
1254\f
1255/* Defining coprocessor specifics for MIPS targets. */
1256
1257\f
1258/* Parameters for Precompiled Header Validity Checking. */
1259
1260\f
1261/* C++ ABI parameters. */
1262
1263\f
1264/* Adding support for named address spaces. */
1265
1266\f
1267/* Miscellaneous Parameters. */
1268
1269/* This is the machine mode that elements of a jump-table should have. */
1270#define CASE_VECTOR_MODE Pmode
1271
1272/* Return the preferred mode for and addr_diff_vec when the mininum
1273 and maximum offset are known. */
1274#define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \
1275 ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode \
1276 : (max_offset >= 100) ? HImode \
1277 : QImode)
1278
1279/* Generate pc relative jump table when -fpic or -Os. */
1280#define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1281
1282/* Define this macro if operations between registers with integral mode
1283 smaller than a word are always performed on the entire register. */
9e11bfef 1284#define WORD_REGISTER_OPERATIONS 1
9304f876
CJW		 1285
1286/* A C expression indicating when insns that read memory in mem_mode,
1287 an integral mode narrower than a word, set the bits outside of mem_mode
1288 to be either the sign-extension or the zero-extension of the data read. */
1289#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1290
1291/* The maximum number of bytes that a single instruction can move quickly
1292 between memory and registers or between two memory locations. */
1293#define MOVE_MAX 4
1294
1295/* A C expression that is nonzero if on this machine the number of bits
1296 actually used for the count of a shift operation is equal to the number
1297 of bits needed to represent the size of the object being shifted. */
1298#define SHIFT_COUNT_TRUNCATED 1
1299
9304f876
CJW		 1300/* A C expression describing the value returned by a comparison operator with
1301 an integral mode and stored by a store-flag instruction ('cstoremode4')
1302 when the condition is true. */
1303#define STORE_FLAG_VALUE 1
1304
24a71166
CJW		 1305/* A C expression that indicates whether the architecture defines a value for
1306 clz or ctz with a zero operand. In nds32 clz for 0 result 32 is defined
1307 in ISA spec */
1308#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
1309
9304f876
CJW		 1310/* An alias for the machine mode for pointers. */
1311#define Pmode SImode
1312
1313/* An alias for the machine mode used for memory references to functions
1314 being called, in call RTL expressions. */
1315#define FUNCTION_MODE SImode
1316
1317/* ------------------------------------------------------------------------ */
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