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[NDS32] Refine negsi2 pattern.
[thirdparty/gcc.git] / gcc / config / nds32 / nds32.md
CommitLineData
9304f876 1;; Machine description of Andes NDS32 cpu for GNU compiler
85ec4feb 2;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
9304f876
CJW		 3;; Contributed by Andes Technology Corporation.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15;; License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
22
23;; Include predicates definition.
24(include "predicates.md")
25
26;; Include constraints definition.
27(include "constraints.md")
28
29;; Include iterators definition.
30(include "iterators.md")
31
32;; Include pipelines definition.
33(include "pipelines.md")
34
35
36;; Include constants definition.
37(include "constants.md")
38
39
40;; Include intrinsic functions definition.
41(include "nds32-intrinsic.md")
42
43;; Include block move for nds32 multiple load/store behavior.
44(include "nds32-multiple.md")
45
46;; Include DImode/DFmode operations.
47(include "nds32-doubleword.md")
48
49;; Include peephole patterns.
50(include "nds32-peephole2.md")
51
52
53;; Insn type, it is used to default other attribute values.
54(define_attr "type"
5ba6d585 55 "unknown,load,store,load_multiple,store_multiple,alu,alu_shift,mul,mac,div,branch,call,misc"
9304f876
CJW		 56 (const_string "unknown"))
57
0aa683b3
CJW		 58;; Insn sub-type
59(define_attr "subtype"
60 "simple,shift"
61 (const_string "simple"))
62
9304f876
CJW		 63;; Length, in bytes, default is 4-bytes.
64(define_attr "length" "" (const_int 4))
65
264159d2
KC		 66;; Indicate the amount of micro instructions.
67(define_attr "combo"
68 "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25"
69 (const_string "1"))
9304f876 70
9be6885b
KC		 71;; Insn in which feature set, it is used to enable/disable insn alternatives.
72;; v1 : Baseline Instructions
73;; v2 : Baseline Version 2 Instructions
74;; v3m : Baseline Version 3m Instructions
75;; v3 : Baseline Version 3 Instructions
76;; pe1 : Performance Extension Instructions
77;; pe2 : Performance Extension Version 2 Instructions
78;; se : String Extension instructions
79(define_attr "feature"
80 "v1,v2,v3m,v3,pe1,pe2,se"
81 (const_string "v1"))
82
9304f876
CJW		 83;; Enabled, which is used to enable/disable insn alternatives.
84;; Note that we use length and TARGET_16_BIT here as criteria.
9be6885b
KC		 85;; If the instruction pattern already check TARGET_16_BIT to determine
86;; the length by itself, its enabled attribute should be customized to
87;; avoid the conflict between length attribute and this default setting.
30feb954 88(define_attr "enabled" "no,yes"
9be6885b
KC		 89 (if_then_else
90 (and (eq_attr "length" "2")
91 (match_test "!TARGET_16_BIT"))
92 (const_string "no")
93 (cond [(eq_attr "feature" "v1") (const_string "yes")
94 (eq_attr "feature" "v2") (if_then_else (match_test "TARGET_ISA_V2 || TARGET_ISA_V3 || TARGET_ISA_V3M")
95 (const_string "yes")
96 (const_string "no"))
97 (eq_attr "feature" "v3") (if_then_else (match_test "TARGET_ISA_V3")
98 (const_string "yes")
99 (const_string "no"))
100 (eq_attr "feature" "v3m") (if_then_else (match_test "TARGET_ISA_V3 || TARGET_ISA_V3M")
101 (const_string "yes")
102 (const_string "no"))
103 (eq_attr "feature" "pe1") (if_then_else (match_test "TARGET_EXT_PERF")
104 (const_string "yes")
105 (const_string "no"))
106 (eq_attr "feature" "pe2") (if_then_else (match_test "TARGET_EXT_PERF2")
107 (const_string "yes")
108 (const_string "no"))
109 (eq_attr "feature" "se") (if_then_else (match_test "TARGET_EXT_STRING")
110 (const_string "yes")
111 (const_string "no"))]
112 (const_string "yes"))))
9304f876
CJW		 113
114
115;; ----------------------------------------------------------------------------
116
117
118;; Move instructions.
119
120;; For QImode and HImode, the immediate value can be fit in imm20s.
121;; So there is no need to split rtx for QI and HI patterns.
122
76dc9cb5
CJW		 123(define_expand "mov<mode>"
124 [(set (match_operand:QIHI 0 "general_operand" "")
125 (match_operand:QIHI 1 "general_operand" ""))]
9304f876
CJW		 126 ""
127{
128 /* Need to force register if mem <- !reg. */
129 if (MEM_P (operands[0]) && !REG_P (operands[1]))
76dc9cb5 130 operands[1] = force_reg (<MODE>mode, operands[1]);
9304f876 131
76dc9cb5
CJW		 132 if (MEM_P (operands[1]) && optimize > 0)
133 {
134 rtx reg = gen_reg_rtx (SImode);
135
136 emit_insn (gen_zero_extend<mode>si2 (reg, operands[1]));
137 operands[1] = gen_lowpart (<MODE>mode, reg);
138 }
9304f876
CJW		 139})
140
2cf09a99
KC		 141(define_expand "movmisalign<mode>"
142 [(set (match_operand:SIDI 0 "general_operand" "")
143 (match_operand:SIDI 1 "general_operand" ""))]
144 ""
145{
146 rtx addr;
147 if (MEM_P (operands[0]) && !REG_P (operands[1]))
148 operands[1] = force_reg (<MODE>mode, operands[1]);
149
150 if (MEM_P (operands[0]))
151 {
152 addr = force_reg (Pmode, XEXP (operands[0], 0));
153 emit_insn (gen_unaligned_store<mode> (addr, operands[1]));
154 }
155 else
156 {
157 addr = force_reg (Pmode, XEXP (operands[1], 0));
158 emit_insn (gen_unaligned_load<mode> (operands[0], addr));
159 }
160 DONE;
161})
76dc9cb5 162
9304f876
CJW		 163(define_expand "movsi"
164 [(set (match_operand:SI 0 "general_operand" "")
165 (match_operand:SI 1 "general_operand" ""))]
166 ""
167{
168 /* Need to force register if mem <- !reg. */
169 if (MEM_P (operands[0]) && !REG_P (operands[1]))
170 operands[1] = force_reg (SImode, operands[1]);
171
172 /* If operands[1] is a large constant and cannot be performed
173 by a single instruction, we need to split it. */
174 if (CONST_INT_P (operands[1])
175 && !satisfies_constraint_Is20 (operands[1])
176 && !satisfies_constraint_Ihig (operands[1]))
177 {
178 rtx high20_rtx;
179 HOST_WIDE_INT low12_int;
180 rtx tmp_rtx;
181
182 tmp_rtx = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
183
184 high20_rtx = gen_int_mode ((INTVAL (operands[1]) >> 12) << 12, SImode);
185 low12_int = INTVAL (operands[1]) & 0xfff;
186
187 emit_move_insn (tmp_rtx, high20_rtx);
188 emit_move_insn (operands[0], plus_constant (SImode,
189 tmp_rtx,
190 low12_int));
191 DONE;
192 }
193})
194
195(define_insn "*mov<mode>"
196 [(set (match_operand:QIHISI 0 "nonimmediate_operand" "=r, r, U45, U33, U37, U45, m, l, l, l, d, r, d, r, r, r")
197 (match_operand:QIHISI 1 "nds32_move_operand" " r, r, l, l, l, d, r, U45, U33, U37, U45, m, Ip05, Is05, Is20, Ihig"))]
b4350271
KC		 198 "register_operand(operands[0], <MODE>mode)
199 || register_operand(operands[1], <MODE>mode)"
9304f876
CJW		 200{
201 switch (which_alternative)
202 {
203 case 0:
204 return "mov55\t%0, %1";
205 case 1:
206 return "ori\t%0, %1, 0";
207 case 2:
208 case 3:
209 case 4:
210 case 5:
211 return nds32_output_16bit_store (operands, <byte>);
212 case 6:
213 return nds32_output_32bit_store (operands, <byte>);
214 case 7:
215 case 8:
216 case 9:
217 case 10:
218 return nds32_output_16bit_load (operands, <byte>);
219 case 11:
220 return nds32_output_32bit_load (operands, <byte>);
221 case 12:
222 return "movpi45\t%0, %1";
223 case 13:
224 return "movi55\t%0, %1";
225 case 14:
226 return "movi\t%0, %1";
227 case 15:
228 return "sethi\t%0, hi20(%1)";
229 default:
230 gcc_unreachable ();
231 }
232}
233 [(set_attr "type" "alu,alu,store,store,store,store,store,load,load,load,load,load,alu,alu,alu,alu")
234 (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2, 2, 4, 2, 2, 4, 4")])
235
236
237;; We use nds32_symbolic_operand to limit that only CONST/SYMBOL_REF/LABEL_REF
238;; are able to match such instruction template.
c4d8d050 239(define_insn "move_addr"
9304f876
CJW		 240 [(set (match_operand:SI 0 "register_operand" "=l, r")
241 (match_operand:SI 1 "nds32_symbolic_operand" " i, i"))]
242 ""
243 "la\t%0, %1"
5ba6d585 244 [(set_attr "type" "alu")
9304f876
CJW		 245 (set_attr "length" "8")])
246
247
c4d8d050 248(define_insn "sethi"
9304f876
CJW		 249 [(set (match_operand:SI 0 "register_operand" "=r")
250 (high:SI (match_operand:SI 1 "nds32_symbolic_operand" " i")))]
251 ""
252 "sethi\t%0, hi20(%1)"
253 [(set_attr "type" "alu")
254 (set_attr "length" "4")])
255
256
c4d8d050 257(define_insn "lo_sum"
9304f876
CJW		 258 [(set (match_operand:SI 0 "register_operand" "=r")
259 (lo_sum:SI (match_operand:SI 1 "register_operand" " r")
260 (match_operand:SI 2 "nds32_symbolic_operand" " i")))]
261 ""
262 "ori\t%0, %1, lo12(%2)"
263 [(set_attr "type" "alu")
264 (set_attr "length" "4")])
265
266
267;; ----------------------------------------------------------------------------
268
269;; Zero extension instructions.
270
271(define_insn "zero_extend<mode>si2"
272 [(set (match_operand:SI 0 "register_operand" "=l, r, l, *r")
273 (zero_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, U33, m")))]
274 ""
275{
276 switch (which_alternative)
277 {
278 case 0:
279 return "ze<size>33\t%0, %1";
280 case 1:
281 return "ze<size>\t%0, %1";
282 case 2:
283 return nds32_output_16bit_load (operands, <byte>);
284 case 3:
285 return nds32_output_32bit_load (operands, <byte>);
286
287 default:
288 gcc_unreachable ();
289 }
290}
291 [(set_attr "type" "alu,alu,load,load")
292 (set_attr "length" " 2, 4, 2, 4")])
293
294
295;; Sign extension instructions.
296
297(define_insn "extend<mode>si2"
298 [(set (match_operand:SI 0 "register_operand" "=l, r, r")
299 (sign_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, m")))]
300 ""
301{
302 switch (which_alternative)
303 {
304 case 0:
305 return "se<size>33\t%0, %1";
306 case 1:
307 return "se<size>\t%0, %1";
308 case 2:
309 return nds32_output_32bit_load_s (operands, <byte>);
310
311 default:
312 gcc_unreachable ();
313 }
314}
315 [(set_attr "type" "alu,alu,load")
316 (set_attr "length" " 2, 4, 4")])
317
318
319;; ----------------------------------------------------------------------------
320
321;; Arithmetic instructions.
322
5c36be57
CJW		 323(define_insn "addsi3"
324 [(set (match_operand:SI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r")
325 (plus:SI (match_operand:SI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r")
a3b13564 326 (match_operand:SI 2 "nds32_rimm15s_operand" " In05,In03,Iu05,Iu03, r, l,Is10,Iu06, Is15, r")))]
9304f876
CJW		 327 ""
328{
329 switch (which_alternative)
330 {
331 case 0:
332 /* addi Rt4,Rt4,-x ==> subi45 Rt4,x
8a498f99 333 where 0 <= x <= 31 */
9304f876
CJW		 334 operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
335 return "subi45\t%0, %2";
336 case 1:
337 /* addi Rt3,Ra3,-x ==> subi333 Rt3,Ra3,x
8a498f99 338 where 0 <= x <= 7 */
9304f876
CJW		 339 operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
340 return "subi333\t%0, %1, %2";
341 case 2:
342 return "addi45\t%0, %2";
343 case 3:
344 return "addi333\t%0, %1, %2";
345 case 4:
346 return "add45\t%0, %2";
347 case 5:
348 return "add333\t%0, %1, %2";
349 case 6:
350 return "addi10.sp\t%2";
351 case 7:
352 return "addri36.sp\t%0, %2";
353 case 8:
354 return "addi\t%0, %1, %2";
355 case 9:
356 return "add\t%0, %1, %2";
357
358 default:
359 gcc_unreachable ();
360 }
361}
9be6885b
KC		 362 [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
363 (set_attr "length" " 2, 2, 2, 2, 2, 2, 2, 2, 4, 4")
364 (set_attr "feature" " v1, v1, v1, v1, v1, v1, v2, v1, v1, v1")])
9304f876 365
5c36be57
CJW		 366(define_insn "subsi3"
367 [(set (match_operand:SI 0 "register_operand" "=d, l, r, r")
368 (minus:SI (match_operand:SI 1 "nds32_rimm15s_operand" " 0, l, Is15, r")
369 (match_operand:SI 2 "register_operand" " r, l, r, r")))]
9304f876
CJW		 370 ""
371 "@
9c1a4c0f
CJW		 372 sub45\t%0, %2
373 sub333\t%0, %1, %2
374 subri\t%0, %2, %1
375 sub\t%0, %1, %2"
9304f876
CJW		 376 [(set_attr "type" "alu,alu,alu,alu")
377 (set_attr "length" " 2, 2, 4, 4")])
378
379
380;; GCC intends to simplify (plus (ashift ...) (reg))
381;; into (plus (mult ...) (reg)), so our matching pattern takes 'mult'
382;; and needs to ensure it is exact_log2 value.
383(define_insn "*add_slli"
384 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99 385 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
9304f876
CJW		 386 (match_operand:SI 2 "immediate_operand" " i"))
387 (match_operand:SI 3 "register_operand" " r")))]
388 "TARGET_ISA_V3
389 && (exact_log2 (INTVAL (operands[2])) != -1)
390 && (exact_log2 (INTVAL (operands[2])) <= 31)"
391{
392 /* Get floor_log2 of the immediate value
393 so that we can generate 'add_slli' instruction. */
394 operands[2] = GEN_INT (floor_log2 (INTVAL (operands[2])));
395
396 return "add_slli\t%0, %3, %1, %2";
397}
5ba6d585
KC		 398 [(set_attr "type" "alu_shift")
399 (set_attr "combo" "2")
400 (set_attr "length" "4")])
9304f876
CJW		 401
402(define_insn "*add_srli"
a3b13564
KC		 403 [(set (match_operand:SI 0 "register_operand" "= r")
404 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
405 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
406 (match_operand:SI 3 "register_operand" " r")))]
9304f876
CJW		 407 "TARGET_ISA_V3"
408 "add_srli\t%0, %3, %1, %2"
5ba6d585
KC		 409 [(set_attr "type" "alu_shift")
410 (set_attr "combo" "2")
411 (set_attr "length" "4")])
9304f876
CJW		 412
413
414;; GCC intends to simplify (minus (reg) (ashift ...))
415;; into (minus (reg) (mult ...)), so our matching pattern takes 'mult'
416;; and needs to ensure it is exact_log2 value.
417(define_insn "*sub_slli"
418 [(set (match_operand:SI 0 "register_operand" "=r")
419 (minus:SI (match_operand:SI 1 "register_operand" " r")
420 (mult:SI (match_operand:SI 2 "register_operand" " r")
421 (match_operand:SI 3 "immediate_operand" " i"))))]
422 "TARGET_ISA_V3
423 && (exact_log2 (INTVAL (operands[3])) != -1)
424 && (exact_log2 (INTVAL (operands[3])) <= 31)"
425{
426 /* Get floor_log2 of the immediate value
427 so that we can generate 'sub_slli' instruction. */
428 operands[3] = GEN_INT (floor_log2 (INTVAL (operands[3])));
429
430 return "sub_slli\t%0, %1, %2, %3";
431}
5ba6d585
KC		 432 [(set_attr "type" "alu_shift")
433 (set_attr "combo" "2")
434 (set_attr "length" "4")])
9304f876
CJW		 435
436(define_insn "*sub_srli"
77827557
CJW		 437 [(set (match_operand:SI 0 "register_operand" "= r")
438 (minus:SI (match_operand:SI 1 "register_operand" " r")
439 (lshiftrt:SI (match_operand:SI 2 "register_operand" " r")
440 (match_operand:SI 3 "nds32_imm5u_operand" " Iu05"))))]
9304f876
CJW		 441 "TARGET_ISA_V3"
442 "sub_srli\t%0, %1, %2, %3"
5ba6d585
KC		 443 [(set_attr "type" "alu_shift")
444 (set_attr "combo" "2")
445 (set_attr "length" "4")])
9304f876
CJW		 446
447
448;; Multiplication instructions.
449
450(define_insn "mulsi3"
73f793e3
RS		 451 [(set (match_operand:SI 0 "register_operand" "=w, r")
452 (mult:SI (match_operand:SI 1 "register_operand" "%0, r")
453 (match_operand:SI 2 "register_operand" " w, r")))]
9304f876
CJW		 454 ""
455 "@
9c1a4c0f
CJW		 456 mul33\t%0, %2
457 mul\t%0, %1, %2"
5ba6d585 458 [(set_attr "type" "mul,mul")
9be6885b
KC		 459 (set_attr "length" " 2, 4")
460 (set_attr "feature" "v3m, v1")])
9304f876
CJW		 461
462(define_insn "mulsidi3"
463 [(set (match_operand:DI 0 "register_operand" "=r")
464 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
465 (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
466 "TARGET_ISA_V2 || TARGET_ISA_V3"
467 "mulsr64\t%0, %1, %2"
5ba6d585 468 [(set_attr "type" "mul")
9304f876
CJW		 469 (set_attr "length" "4")])
470
471(define_insn "umulsidi3"
472 [(set (match_operand:DI 0 "register_operand" "=r")
473 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " r"))
474 (zero_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
475 "TARGET_ISA_V2 || TARGET_ISA_V3"
476 "mulr64\t%0, %1, %2"
5ba6d585 477 [(set_attr "type" "mul")
9304f876
CJW		 478 (set_attr "length" "4")])
479
480
481;; Multiply-accumulate instructions.
482
483(define_insn "*maddr32_0"
484 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 485 (plus:SI (match_operand:SI 3 "register_operand" " 0")
486 (mult:SI (match_operand:SI 1 "register_operand" " r")
487 (match_operand:SI 2 "register_operand" " r"))))]
9304f876
CJW		 488 ""
489 "maddr32\t%0, %1, %2"
5ba6d585 490 [(set_attr "type" "mac")
9304f876
CJW		 491 (set_attr "length" "4")])
492
493(define_insn "*maddr32_1"
494 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 495 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
496 (match_operand:SI 2 "register_operand" " r"))
497 (match_operand:SI 3 "register_operand" " 0")))]
9304f876
CJW		 498 ""
499 "maddr32\t%0, %1, %2"
5ba6d585 500 [(set_attr "type" "mac")
9304f876
CJW		 501 (set_attr "length" "4")])
502
503(define_insn "*msubr32"
504 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 505 (minus:SI (match_operand:SI 3 "register_operand" " 0")
506 (mult:SI (match_operand:SI 1 "register_operand" " r")
507 (match_operand:SI 2 "register_operand" " r"))))]
9304f876
CJW		 508 ""
509 "msubr32\t%0, %1, %2"
5ba6d585 510 [(set_attr "type" "mac")
9304f876
CJW		 511 (set_attr "length" "4")])
512
513
514;; Div Instructions.
515
516(define_insn "divmodsi4"
517 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 518 (div:SI (match_operand:SI 1 "register_operand" " r")
519 (match_operand:SI 2 "register_operand" " r")))
9304f876 520 (set (match_operand:SI 3 "register_operand" "=r")
8a498f99 521 (mod:SI (match_dup 1) (match_dup 2)))]
9304f876
CJW		 522 ""
523 "divsr\t%0, %3, %1, %2"
5ba6d585 524 [(set_attr "type" "div")
9304f876
CJW		 525 (set_attr "length" "4")])
526
527(define_insn "udivmodsi4"
528 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 529 (udiv:SI (match_operand:SI 1 "register_operand" " r")
530 (match_operand:SI 2 "register_operand" " r")))
9304f876 531 (set (match_operand:SI 3 "register_operand" "=r")
8a498f99 532 (umod:SI (match_dup 1) (match_dup 2)))]
9304f876
CJW		 533 ""
534 "divr\t%0, %3, %1, %2"
5ba6d585 535 [(set_attr "type" "div")
9304f876
CJW		 536 (set_attr "length" "4")])
537
538
539;; ----------------------------------------------------------------------------
540
541;; Boolean instructions.
542;; Note: We define the DImode versions in nds32-doubleword.md.
543
544;; ----------------------------------------------------------------------------
545;; 'AND' operation
546;; ----------------------------------------------------------------------------
547
548(define_insn "bitc"
549 [(set (match_operand:SI 0 "register_operand" "=r")
550 (and:SI (not:SI (match_operand:SI 1 "register_operand" " r"))
551 (match_operand:SI 2 "register_operand" " r")))]
552 "TARGET_ISA_V3"
553 "bitc\t%0, %2, %1"
554 [(set_attr "type" "alu")
555 (set_attr "length" "4")]
556)
557
a3b13564
KC		 558(define_expand "andsi3"
559 [(set (match_operand:SI 0 "register_operand" "")
560 (and:SI (match_operand:SI 1 "register_operand" "")
561 (match_operand:SI 2 "nds32_reg_constant_operand" "")))]
562 ""
563{
564 if (CONST_INT_P (operands[2])
565 && !nds32_and_operand (operands[2], SImode))
566 {
567 nds32_expand_constant (SImode, INTVAL (operands[2]),
568 operands[0], operands[1]);
569 DONE;
570 }
571})
572
573(define_insn "*andsi3"
574 [(set (match_operand:SI 0 "register_operand" "=l, r, l, l, l, l, l, l, r, r, r, r, r")
575 (and:SI (match_operand:SI 1 "register_operand" "%0, r, l, l, l, l, 0, 0, r, r, r, r, r")
576 (match_operand:SI 2 "nds32_and_operand" " l, r,Izeb,Izeh,Ixls,Ix11,Ibms,Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))]
9304f876
CJW		 577 ""
578{
579 HOST_WIDE_INT mask = INTVAL (operands[2]);
9304f876
CJW		 580
581 /* 16-bit andi instructions:
582 andi Rt3,Ra3,0xff -> zeb33 Rt3,Ra3
583 andi Rt3,Ra3,0xffff -> zeh33 Rt3,Ra3
584 andi Rt3,Ra3,0x01 -> xlsb33 Rt3,Ra3
585 andi Rt3,Ra3,0x7ff -> x11b33 Rt3,Ra3
586 andi Rt3,Rt3,2^imm3u -> bmski33 Rt3,imm3u
587 andi Rt3,Rt3,(2^(imm3u+1))-1 -> fexti33 Rt3,imm3u. */
588
589 switch (which_alternative)
590 {
591 case 0:
592 return "and33\t%0, %2";
593 case 1:
594 return "and\t%0, %1, %2";
595 case 2:
596 return "zeb33\t%0, %1";
597 case 3:
598 return "zeh33\t%0, %1";
599 case 4:
600 return "xlsb33\t%0, %1";
601 case 5:
602 return "x11b33\t%0, %1";
603 case 6:
a3b13564 604 return "bmski33\t%0, %B2";
9304f876
CJW		 605 case 7:
606 operands[2] = GEN_INT (floor_log2 (mask + 1) - 1);
607 return "fexti33\t%0, %2";
608 case 8:
609 return "zeb\t%0, %1";
610 case 9:
611 return "zeh\t%0, %1";
612 case 10:
613 return "andi\t%0, %1, %2";
614 case 11:
615 operands[2] = GEN_INT (~mask);
616 return "bitci\t%0, %1, %2";
617 case 12:
a3b13564 618 return "bclr\t%0, %1, %b2";
9304f876
CJW		 619
620 default:
621 gcc_unreachable ();
622 }
623}
9be6885b
KC		 624 [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
625 (set_attr "length" " 2, 4, 2, 2, 2, 2, 2, 2, 4, 4, 4, 4, 4")
626 (set_attr "feature" "v3m, v1, v1, v1, v1, v1,v3m,v3m, v1, v1, v1, v3,pe1")])
9304f876
CJW		 627
628(define_insn "*and_slli"
77827557
CJW		 629 [(set (match_operand:SI 0 "register_operand" "= r")
630 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
631 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
632 (match_operand:SI 3 "register_operand" " r")))]
9304f876
CJW		 633 "TARGET_ISA_V3"
634 "and_slli\t%0, %3, %1, %2"
5ba6d585
KC		 635 [(set_attr "type" "alu_shift")
636 (set_attr "length" "4")])
9304f876
CJW		 637
638(define_insn "*and_srli"
77827557
CJW		 639 [(set (match_operand:SI 0 "register_operand" "= r")
640 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
641 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
642 (match_operand:SI 3 "register_operand" " r")))]
9304f876
CJW		 643 "TARGET_ISA_V3"
644 "and_srli\t%0, %3, %1, %2"
5ba6d585
KC		 645 [(set_attr "type" "alu_shift")
646 (set_attr "length" "4")])
9304f876
CJW		 647
648
649;; ----------------------------------------------------------------------------
650;; 'OR' operation
651;; ----------------------------------------------------------------------------
652
653;; For V3/V3M ISA, we have 'or33' instruction.
654;; So we can identify 'or Rt3,Rt3,Ra3' case and set its length to be 2.
a3b13564
KC		 655
656(define_expand "iorsi3"
657 [(set (match_operand:SI 0 "register_operand" "")
658 (ior:SI (match_operand:SI 1 "register_operand" "")
659 (match_operand:SI 2 "general_operand" "")))]
9304f876
CJW		 660 ""
661{
a3b13564
KC		 662 if (!nds32_ior_operand (operands[2], SImode))
663 operands[2] = force_reg (SImode, operands[2]);
664})
9304f876 665
a3b13564
KC		 666(define_insn "*iorsi3"
667 [(set (match_operand:SI 0 "register_operand" "=l, r, r, r")
668 (ior:SI (match_operand:SI 1 "register_operand" "%0, r, r, r")
669 (match_operand:SI 2 "nds32_ior_operand" " l, r, Iu15, Ie15")))]
670 ""
671 "@
672 or33\t%0, %2
673 or\t%0, %1, %2
674 ori\t%0, %1, %2
675 bset\t%0, %1, %B2"
676 [(set_attr "type" "alu,alu,alu,alu")
677 (set_attr "length" " 2, 4, 4, 4")
678 (set_attr "feature" "v3m, v1, v1,pe1")])
9304f876
CJW		 679
680(define_insn "*or_slli"
a3b13564
KC		 681 [(set (match_operand:SI 0 "register_operand" "= r")
682 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
683 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
684 (match_operand:SI 3 "register_operand" " r")))]
9304f876
CJW		 685 "TARGET_ISA_V3"
686 "or_slli\t%0, %3, %1, %2"
5ba6d585
KC		 687 [(set_attr "type" "alu_shift")
688 (set_attr "length" "4")])
9304f876
CJW		 689
690(define_insn "*or_srli"
a3b13564
KC		 691 [(set (match_operand:SI 0 "register_operand" "= r")
692 (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
693 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
694 (match_operand:SI 3 "register_operand" " r")))]
9304f876
CJW		 695 "TARGET_ISA_V3"
696 "or_srli\t%0, %3, %1, %2"
5ba6d585
KC		 697 [(set_attr "type" "alu_shift")
698 (set_attr "length" "4")])
9304f876
CJW		 699
700
701;; ----------------------------------------------------------------------------
702;; 'XOR' operation
703;; ----------------------------------------------------------------------------
704
705;; For V3/V3M ISA, we have 'xor33' instruction.
706;; So we can identify 'xor Rt3,Rt3,Ra3' case and set its length to be 2.
a3b13564
KC		 707
708(define_expand "xorsi3"
709 [(set (match_operand:SI 0 "register_operand" "")
710 (xor:SI (match_operand:SI 1 "register_operand" "")
711 (match_operand:SI 2 "general_operand" "")))]
9304f876
CJW		 712 ""
713{
a3b13564
KC		 714 if (!nds32_xor_operand (operands[2], SImode))
715 operands[2] = force_reg (SImode, operands[2]);
716})
9304f876 717
a3b13564
KC		 718(define_insn "*xorsi3"
719 [(set (match_operand:SI 0 "register_operand" "=l, r, r, r")
720 (xor:SI (match_operand:SI 1 "register_operand" "%0, r, r, r")
721 (match_operand:SI 2 "nds32_xor_operand" " l, r, Iu15, It15")))]
722 ""
723 "@
724 xor33\t%0, %2
725 xor\t%0, %1, %2
726 xori\t%0, %1, %2
727 btgl\t%0, %1, %B2"
9be6885b
KC		 728 [(set_attr "type" "alu,alu,alu,alu")
729 (set_attr "length" " 2, 4, 4, 4")
730 (set_attr "feature" "v3m, v1, v1,pe1")])
9304f876
CJW		 731
732(define_insn "*xor_slli"
733 [(set (match_operand:SI 0 "register_operand" "= r")
734 (xor:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
a3b13564 735 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
9304f876
CJW		 736 (match_operand:SI 3 "register_operand" " r")))]
737 "TARGET_ISA_V3"
738 "xor_slli\t%0, %3, %1, %2"
5ba6d585
KC		 739 [(set_attr "type" "alu_shift")
740 (set_attr "length" "4")])
9304f876
CJW		 741
742(define_insn "*xor_srli"
a3b13564
KC		 743 [(set (match_operand:SI 0 "register_operand" "= r")
744 (xor:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
745 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
746 (match_operand:SI 3 "register_operand" " r")))]
9304f876
CJW		 747 "TARGET_ISA_V3"
748 "xor_srli\t%0, %3, %1, %2"
5ba6d585
KC		 749 [(set_attr "type" "alu_shift")
750 (set_attr "length" "4")])
9304f876
CJW		 751
752;; Rotate Right Instructions.
753
a3b13564
KC		 754(define_insn "*rotrsi3"
755 [(set (match_operand:SI 0 "register_operand" "= r, r")
756 (rotatert:SI (match_operand:SI 1 "register_operand" " r, r")
757 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r")))]
9304f876
CJW		 758 ""
759 "@
9c1a4c0f
CJW		 760 rotri\t%0, %1, %2
761 rotr\t%0, %1, %2"
5ba6d585 762 [(set_attr "type" " alu, alu")
0aa683b3 763 (set_attr "subtype" "shift,shift")
5ba6d585 764 (set_attr "length" " 4, 4")])
9304f876
CJW		 765
766
767;; ----------------------------------------------------------------------------
768;; 'NEG' operation
769;; ----------------------------------------------------------------------------
770
771;; For V3/V3M ISA, we have 'neg33' instruction.
772;; So we can identify 'xor Rt3,Ra3' case and set its length to be 2.
773;; And for V2 ISA, there is NO 'neg33' instruction.
774;; The only option is to use 'subri A,B,0' (its semantic is 'A = 0 - B').
775(define_insn "negsi2"
3fbbd9e5
CJW		 776 [(set (match_operand:SI 0 "register_operand" "=l, r")
777 (neg:SI (match_operand:SI 1 "register_operand" " l, r")))]
9304f876
CJW		 778 ""
779 "@
780 neg33\t%0, %1
781 subri\t%0, %1, 0"
3fbbd9e5
CJW		 782 [(set_attr "type" "alu,alu")
783 (set_attr "length" " 2, 4")
784 (set_attr "feature" "v3m, v1")])
9304f876
CJW		 785
786;; ----------------------------------------------------------------------------
787;; 'ONE_COMPLIMENT' operation
788;; ----------------------------------------------------------------------------
789
790;; For V3/V3M ISA, we have 'not33' instruction.
791;; So we can identify 'not Rt3,Ra3' case and set its length to be 2.
792(define_insn "one_cmplsi2"
793 [(set (match_operand:SI 0 "register_operand" "=w, r")
794 (not:SI (match_operand:SI 1 "register_operand" " w, r")))]
795 ""
796 "@
797 not33\t%0, %1
798 nor\t%0, %1, %1"
9be6885b
KC		 799 [(set_attr "type" "alu,alu")
800 (set_attr "length" " 2, 4")
801 (set_attr "feature" "v3m, v1")])
9304f876
CJW		 802
803
804;; ----------------------------------------------------------------------------
805
806;; Shift instructions.
807
a3b13564
KC		 808(define_expand "<shift>si3"
809 [(set (match_operand:SI 0 "register_operand" "")
810 (shift_rotate:SI (match_operand:SI 1 "register_operand" "")
811 (match_operand:SI 2 "nds32_rimm5u_operand" "")))]
812 ""
813{
814 if (operands[2] == const0_rtx)
815 {
816 emit_move_insn (operands[0], operands[1]);
817 DONE;
818 }
819})
820
821(define_insn "*ashlsi3"
822 [(set (match_operand:SI 0 "register_operand" "= l, r, r")
823 (ashift:SI (match_operand:SI 1 "register_operand" " l, r, r")
824 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu03, Iu05, r")))]
9304f876
CJW		 825 ""
826 "@
9c1a4c0f
CJW		 827 slli333\t%0, %1, %2
828 slli\t%0, %1, %2
829 sll\t%0, %1, %2"
0aa683b3
CJW		 830 [(set_attr "type" " alu, alu, alu")
831 (set_attr "subtype" "shift,shift,shift")
832 (set_attr "length" " 2, 4, 4")])
a3b13564
KC		 833
834(define_insn "*ashrsi3"
835 [(set (match_operand:SI 0 "register_operand" "= d, r, r")
836 (ashiftrt:SI (match_operand:SI 1 "register_operand" " 0, r, r")
837 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, Iu05, r")))]
9304f876
CJW		 838 ""
839 "@
9c1a4c0f
CJW		 840 srai45\t%0, %2
841 srai\t%0, %1, %2
842 sra\t%0, %1, %2"
0aa683b3
CJW		 843 [(set_attr "type" " alu, alu, alu")
844 (set_attr "subtype" "shift,shift,shift")
845 (set_attr "length" " 2, 4, 4")])
9304f876 846
a3b13564
KC		 847(define_insn "*lshrsi3"
848 [(set (match_operand:SI 0 "register_operand" "= d, r, r")
849 (lshiftrt:SI (match_operand:SI 1 "register_operand" " 0, r, r")
850 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, Iu05, r")))]
9304f876
CJW		 851 ""
852 "@
9c1a4c0f
CJW		 853 srli45\t%0, %2
854 srli\t%0, %1, %2
855 srl\t%0, %1, %2"
0aa683b3
CJW		 856 [(set_attr "type" " alu, alu, alu")
857 (set_attr "subtype" "shift,shift,shift")
858 (set_attr "length" " 2, 4, 4")])
9304f876
CJW		 859
860
861;; ----------------------------------------------------------------------------
862
863;; ----------------------------------------------------------------------------
864;; Conditional Move patterns
865;; ----------------------------------------------------------------------------
866
6e9ca932
CJW		 867(define_expand "mov<mode>cc"
868 [(set (match_operand:QIHISI 0 "register_operand" "")
869 (if_then_else:QIHISI (match_operand 1 "nds32_movecc_comparison_operator" "")
870 (match_operand:QIHISI 2 "register_operand" "")
871 (match_operand:QIHISI 3 "register_operand" "")))]
872 "TARGET_CMOV && !optimize_size"
9304f876 873{
6e9ca932
CJW		 874 enum nds32_expand_result_type result = nds32_expand_movcc (operands);
875 switch (result)
9304f876 876 {
6e9ca932
CJW		 877 case EXPAND_DONE:
878 DONE;
879 break;
880 case EXPAND_FAIL:
881 FAIL;
882 break;
883 case EXPAND_CREATE_TEMPLATE:
884 break;
885 default:
886 gcc_unreachable ();
9304f876 887 }
9304f876
CJW		 888})
889
6e9ca932
CJW		 890(define_insn "cmovz<mode>"
891 [(set (match_operand:QIHISI 0 "register_operand" "=r, r")
892 (if_then_else:QIHISI (eq (match_operand:SI 1 "register_operand" " r, r")
9304f876 893 (const_int 0))
6e9ca932
CJW		 894 (match_operand:QIHISI 2 "register_operand" " r, 0")
895 (match_operand:QIHISI 3 "register_operand" " 0, r")))]
9304f876
CJW		 896 "TARGET_CMOV"
897 "@
898 cmovz\t%0, %2, %1
899 cmovn\t%0, %3, %1"
5ba6d585 900 [(set_attr "type" "alu")
9304f876
CJW		 901 (set_attr "length" "4")])
902
6e9ca932
CJW		 903(define_insn "cmovn<mode>"
904 [(set (match_operand:QIHISI 0 "register_operand" "=r, r")
905 (if_then_else:QIHISI (ne (match_operand:SI 1 "register_operand" " r, r")
9304f876 906 (const_int 0))
6e9ca932
CJW		 907 (match_operand:QIHISI 2 "register_operand" " r, 0")
908 (match_operand:QIHISI 3 "register_operand" " 0, r")))]
9304f876
CJW		 909 "TARGET_CMOV"
910 "@
911 cmovn\t%0, %2, %1
912 cmovz\t%0, %3, %1"
5ba6d585 913 [(set_attr "type" "alu")
9304f876
CJW		 914 (set_attr "length" "4")])
915
6e9ca932
CJW		 916;; A hotfix to help RTL combiner to merge a cmovn insn and a zero_extend insn.
917;; It should be removed once after we change the expansion form of the cmovn.
918(define_insn "*cmovn_simplified_<mode>"
919 [(set (match_operand:QIHISI 0 "register_operand" "=r")
920 (if_then_else:QIHISI (match_operand:SI 1 "register_operand" "r")
921 (match_operand:QIHISI 2 "register_operand" "r")
922 (match_operand:QIHISI 3 "register_operand" "0")))]
923 ""
924 "cmovn\t%0, %2, %1"
925 [(set_attr "type" "alu")])
9304f876
CJW		 926
927;; ----------------------------------------------------------------------------
928;; Conditional Branch patterns
929;; ----------------------------------------------------------------------------
930
931(define_expand "cbranchsi4"
932 [(set (pc)
933 (if_then_else (match_operator 0 "comparison_operator"
934 [(match_operand:SI 1 "register_operand" "")
935 (match_operand:SI 2 "nds32_reg_constant_operand" "")])
936 (label_ref (match_operand 3 "" ""))
937 (pc)))]
938 ""
939{
6e9ca932
CJW		 940 enum nds32_expand_result_type result = nds32_expand_cbranch (operands);
941 switch (result)
9304f876 942 {
6e9ca932 943 case EXPAND_DONE:
9304f876 944 DONE;
6e9ca932
CJW		 945 break;
946 case EXPAND_FAIL:
9304f876 947 FAIL;
6e9ca932
CJW		 948 break;
949 case EXPAND_CREATE_TEMPLATE:
950 break;
951 default:
952 gcc_unreachable ();
9304f876 953 }
9304f876
CJW		 954})
955
956
6e9ca932 957(define_insn "cbranchsi4_equality_zero"
9304f876
CJW		 958 [(set (pc)
959 (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
6e9ca932 960 [(match_operand:SI 1 "register_operand" "t,l, r")
9304f876
CJW		 961 (const_int 0)])
962 (label_ref (match_operand 2 "" ""))
963 (pc)))]
964 ""
965{
6e9ca932 966 return nds32_output_cbranchsi4_equality_zero (insn, operands);
9304f876
CJW		 967}
968 [(set_attr "type" "branch")
6e9ca932
CJW		 969 (set_attr_alternative "enabled"
970 [
971 ;; Alternative 0
972 (if_then_else (match_test "TARGET_16_BIT")
973 (const_string "yes")
974 (const_string "no"))
975 ;; Alternative 1
976 (if_then_else (match_test "TARGET_16_BIT")
977 (const_string "yes")
978 (const_string "no"))
979 ;; Alternative 2
980 (const_string "yes")
981 ])
9304f876
CJW		 982 (set_attr_alternative "length"
983 [
984 ;; Alternative 0
6e9ca932
CJW		 985 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
986 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
987 (le (minus (match_dup 2) (pc)) (const_int 250)))
9304f876 988 (if_then_else (match_test "TARGET_16_BIT")
6e9ca932
CJW		 989 (const_int 2)
990 (const_int 4))
991 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
992 (le (minus (match_dup 2) (pc)) (const_int 65500)))
993 (const_int 4)
994 (if_then_else (match_test "TARGET_16_BIT")
995 (const_int 8)
996 (const_int 10))))
997 (const_int 10))
9304f876 998 ;; Alternative 1
6e9ca932
CJW		 999 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1000 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
1001 (le (minus (match_dup 2) (pc)) (const_int 250)))
1002 (if_then_else (match_test "TARGET_16_BIT")
1003 (const_int 2)
1004 (const_int 4))
1005 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
1006 (le (minus (match_dup 2) (pc)) (const_int 65500)))
1007 (const_int 4)
1008 (if_then_else (match_test "TARGET_16_BIT")
1009 (const_int 8)
1010 (const_int 10))))
1011 (const_int 10))
1012 ;; Alternative 2
1013 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
9304f876
CJW		 1014 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
1015 (le (minus (match_dup 2) (pc)) (const_int 65500)))
1016 (const_int 4)
6e9ca932
CJW		 1017 (const_int 10))
1018 (const_int 10))
9304f876
CJW		 1019 ])])
1020
1021
1022;; This pattern is dedicated to V2 ISA,
1023;; because V2 DOES NOT HAVE beqc/bnec instruction.
6e9ca932 1024(define_insn "cbranchsi4_equality_reg"
9304f876
CJW		 1025 [(set (pc)
1026 (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
6e9ca932
CJW		 1027 [(match_operand:SI 1 "register_operand" "v, r")
1028 (match_operand:SI 2 "register_operand" "l, r")])
9304f876
CJW		 1029 (label_ref (match_operand 3 "" ""))
1030 (pc)))]
1031 "TARGET_ISA_V2"
1032{
6e9ca932 1033 return nds32_output_cbranchsi4_equality_reg (insn, operands);
9304f876
CJW		 1034}
1035 [(set_attr "type" "branch")
6e9ca932
CJW		 1036 (set_attr_alternative "enabled"
1037 [
1038 ;; Alternative 0
1039 (if_then_else (match_test "TARGET_16_BIT")
1040 (const_string "yes")
1041 (const_string "no"))
1042 ;; Alternative 1
1043 (const_string "yes")
1044 ])
1045 (set_attr_alternative "length"
1046 [
1047 ;; Alternative 0
1048 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1049 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
1050 (le (minus (match_dup 3) (pc)) (const_int 250)))
1051 (const_int 2)
1052 (if_then_else (and (ge (minus (match_dup 3) (pc))
1053 (const_int -16350))
1054 (le (minus (match_dup 3) (pc))
1055 (const_int 16350)))
1056 (const_int 4)
1057 (const_int 8)))
1058 (const_int 8))
1059 ;; Alternative 1
1060 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1061 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
1062 (le (minus (match_dup 3) (pc)) (const_int 16350)))
1063 (const_int 4)
1064 (const_int 10))
1065 (const_int 10))
1066 ])])
9304f876
CJW		 1067
1068
1069;; This pattern is dedicated to V3/V3M,
1070;; because V3/V3M DO HAVE beqc/bnec instruction.
6e9ca932 1071(define_insn "cbranchsi4_equality_reg_or_const_int"
9304f876
CJW		 1072 [(set (pc)
1073 (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
6e9ca932
CJW		 1074 [(match_operand:SI 1 "register_operand" "v, r, r")
1075 (match_operand:SI 2 "nds32_rimm11s_operand" "l, r, Is11")])
9304f876
CJW		 1076 (label_ref (match_operand 3 "" ""))
1077 (pc)))]
1078 "TARGET_ISA_V3 || TARGET_ISA_V3M"
1079{
6e9ca932 1080 return nds32_output_cbranchsi4_equality_reg_or_const_int (insn, operands);
9304f876
CJW		 1081}
1082 [(set_attr "type" "branch")
6e9ca932
CJW		 1083 (set_attr_alternative "enabled"
1084 [
1085 ;; Alternative 0
1086 (if_then_else (match_test "TARGET_16_BIT")
1087 (const_string "yes")
1088 (const_string "no"))
1089 ;; Alternative 1
1090 (const_string "yes")
1091 ;; Alternative 2
1092 (const_string "yes")
1093 ])
9304f876
CJW		 1094 (set_attr_alternative "length"
1095 [
1096 ;; Alternative 0
6e9ca932
CJW		 1097 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1098 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
1099 (le (minus (match_dup 3) (pc)) (const_int 250)))
1100 (const_int 2)
1101 (if_then_else (and (ge (minus (match_dup 3) (pc))
1102 (const_int -16350))
1103 (le (minus (match_dup 3) (pc))
1104 (const_int 16350)))
1105 (const_int 4)
1106 (const_int 8)))
1107 (const_int 8))
9304f876 1108 ;; Alternative 1
6e9ca932
CJW		 1109 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1110 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
1111 (le (minus (match_dup 3) (pc)) (const_int 16350)))
1112 (const_int 4)
1113 (const_int 10))
1114 (const_int 10))
1115 ;; Alternative 2
1116 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1117 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
1118 (le (minus (match_dup 3) (pc)) (const_int 250)))
1119 (const_int 4)
1120 (const_int 10))
1121 (const_int 10))
9304f876
CJW		 1122 ])])
1123
1124
1125(define_insn "*cbranchsi4_greater_less_zero"
1126 [(set (pc)
1127 (if_then_else (match_operator 0 "nds32_greater_less_comparison_operator"
1128 [(match_operand:SI 1 "register_operand" "r")
1129 (const_int 0)])
1130 (label_ref (match_operand 2 "" ""))
1131 (pc)))]
1132 ""
1133{
6e9ca932 1134 return nds32_output_cbranchsi4_greater_less_zero (insn, operands);
9304f876
CJW		 1135}
1136 [(set_attr "type" "branch")
1137 (set (attr "length")
6e9ca932
CJW		 1138 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1139 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
1140 (le (minus (match_dup 2) (pc)) (const_int 65500)))
1141 (const_int 4)
1142 (const_int 10))
1143 (const_int 10)))])
9304f876
CJW		 1144
1145
1146(define_expand "cstoresi4"
1147 [(set (match_operand:SI 0 "register_operand" "")
1148 (match_operator:SI 1 "comparison_operator"
1149 [(match_operand:SI 2 "register_operand" "")
1150 (match_operand:SI 3 "nonmemory_operand" "")]))]
1151 ""
1152{
6e9ca932
CJW		 1153 enum nds32_expand_result_type result = nds32_expand_cstore (operands);
1154 switch (result)
9304f876 1155 {
6e9ca932 1156 case EXPAND_DONE:
9304f876 1157 DONE;
6e9ca932
CJW		 1158 break;
1159 case EXPAND_FAIL:
1160 FAIL;
1161 break;
1162 case EXPAND_CREATE_TEMPLATE:
1163 break;
9304f876
CJW		 1164 default:
1165 gcc_unreachable ();
1166 }
1167})
1168
1169
6e9ca932
CJW		 1170(define_expand "slts_compare"
1171 [(set (match_operand:SI 0 "register_operand" "")
1172 (lt:SI (match_operand:SI 1 "general_operand" "")
1173 (match_operand:SI 2 "general_operand" "")))]
1174 ""
1175{
1176 if (!REG_P (operands[1]))
1177 operands[1] = force_reg (SImode, operands[1]);
1178
1179 if (!REG_P (operands[2]) && !satisfies_constraint_Is15 (operands[2]))
1180 operands[2] = force_reg (SImode, operands[2]);
1181})
1182
1183(define_insn "slts_compare_impl"
1184 [(set (match_operand:SI 0 "register_operand" "=t, t, r, r")
1185 (lt:SI (match_operand:SI 1 "register_operand" " d, d, r, r")
1186 (match_operand:SI 2 "nds32_rimm15s_operand" " r,Iu05, r, Is15")))]
9304f876
CJW		 1187 ""
1188 "@
1189 slts45\t%1, %2
1190 sltsi45\t%1, %2
1191 slts\t%0, %1, %2
1192 sltsi\t%0, %1, %2"
6e9ca932
CJW		 1193 [(set_attr "type" "alu, alu, alu, alu")
1194 (set_attr "length" " 2, 2, 4, 4")])
1195
1196(define_insn "slt_eq0"
1197 [(set (match_operand:SI 0 "register_operand" "=t, r")
1198 (eq:SI (match_operand:SI 1 "register_operand" " d, r")
1199 (const_int 0)))]
1200 ""
1201 "@
1202 slti45\t%1, 1
1203 slti\t%0, %1, 1"
1204 [(set_attr "type" "alu, alu")
1205 (set_attr "length" " 2, 4")])
1206
1207(define_expand "slt_compare"
1208 [(set (match_operand:SI 0 "register_operand" "")
1209 (ltu:SI (match_operand:SI 1 "general_operand" "")
1210 (match_operand:SI 2 "general_operand" "")))]
1211 ""
1212{
1213 if (!REG_P (operands[1]))
1214 operands[1] = force_reg (SImode, operands[1]);
1215
1216 if (!REG_P (operands[2]) && !satisfies_constraint_Is15 (operands[2]))
1217 operands[2] = force_reg (SImode, operands[2]);
1218})
9304f876 1219
6e9ca932
CJW		 1220(define_insn "slt_compare_impl"
1221 [(set (match_operand:SI 0 "register_operand" "=t, t, r, r")
1222 (ltu:SI (match_operand:SI 1 "register_operand" " d, d, r, r")
1223 (match_operand:SI 2 "nds32_rimm15s_operand" " r, Iu05, r, Is15")))]
9304f876
CJW		 1224 ""
1225 "@
1226 slt45\t%1, %2
1227 slti45\t%1, %2
1228 slt\t%0, %1, %2
1229 slti\t%0, %1, %2"
5ba6d585
KC		 1230 [(set_attr "type" "alu, alu, alu, alu")
1231 (set_attr "length" " 2, 2, 4, 4")])
9304f876
CJW		 1232
1233
1234;; ----------------------------------------------------------------------------
1235
1236;; Unconditional and other jump instructions.
1237
1238(define_insn "jump"
1239 [(set (pc) (label_ref (match_operand 0 "" "")))]
1240 ""
1241{
1242 /* This unconditional jump has two forms:
1243 32-bit instruction => j imm24s << 1
1244 16-bit instruction => j8 imm8s << 1
1245
1246 For 32-bit case,
1247 we assume it is always reachable.
1248 For 16-bit case,
1249 it must satisfy { 255 >= (label - pc) >= -256 } condition.
1250 However, since the $pc for nds32 is at the beginning of the instruction,
1251 we should leave some length space for current insn.
1252 So we use range -250 ~ 250. */
1253 switch (get_attr_length (insn))
1254 {
1255 case 2:
1256 return "j8\t%0";
1257 case 4:
1258 return "j\t%0";
1259 default:
1260 gcc_unreachable ();
1261 }
1262}
1263 [(set_attr "type" "branch")
30feb954 1264 (set_attr "enabled" "yes")
9304f876 1265 (set (attr "length")
6e9ca932
CJW		 1266 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1267 (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -250))
1268 (le (minus (match_dup 0) (pc)) (const_int 250)))
1269 (if_then_else (match_test "TARGET_16_BIT")
1270 (const_int 2)
1271 (const_int 4))
9304f876
CJW		 1272 (const_int 4))
1273 (const_int 4)))])
1274
1275(define_insn "indirect_jump"
1276 [(set (pc) (match_operand:SI 0 "register_operand" "r, r"))]
1277 ""
1278 "@
9c1a4c0f
CJW		 1279 jr5\t%0
1280 jr\t%0"
9304f876
CJW		 1281 [(set_attr "type" "branch,branch")
1282 (set_attr "length" " 2, 4")])
1283
1284;; Subroutine call instruction returning no value.
1285;; operands[0]: It should be a mem RTX whose address is
026c3cfd 1286;; the address of the function.
9304f876
CJW		 1287;; operands[1]: It is the number of bytes of arguments pushed as a const_int.
1288;; operands[2]: It is the number of registers used as operands.
1289
1290(define_expand "call"
1291 [(parallel [(call (match_operand 0 "memory_operand" "")
1292 (match_operand 1))
1f7b8028
CJW		 1293 (clobber (reg:SI LP_REGNUM))
1294 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1295 ""
1296 ""
1297)
1298
1299(define_insn "*call_register"
1300 [(parallel [(call (mem (match_operand:SI 0 "register_operand" "r, r"))
1301 (match_operand 1))
1f7b8028
CJW		 1302 (clobber (reg:SI LP_REGNUM))
1303 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1304 ""
1305 "@
1306 jral5\t%0
1307 jral\t%0"
1308 [(set_attr "type" "branch,branch")
1309 (set_attr "length" " 2, 4")])
1310
1311(define_insn "*call_immediate"
1312 [(parallel [(call (mem (match_operand:SI 0 "immediate_operand" "i"))
1313 (match_operand 1))
1f7b8028
CJW		 1314 (clobber (reg:SI LP_REGNUM))
1315 (clobber (reg:SI TA_REGNUM))])]
9304f876 1316 ""
1f7b8028
CJW		 1317{
1318 if (TARGET_CMODEL_LARGE)
1319 return "bal\t%0";
1320 else
1321 return "jal\t%0";
1322}
9304f876 1323 [(set_attr "type" "branch")
1f7b8028
CJW		 1324 (set (attr "length")
1325 (if_then_else (match_test "TARGET_CMODEL_LARGE")
1326 (const_int 12)
1327 (const_int 4)))])
9304f876
CJW		 1328
1329
1330;; Subroutine call instruction returning a value.
1331;; operands[0]: It is the hard regiser in which the value is returned.
1332;; The rest three operands are the same as the
1333;; three operands of the 'call' instruction.
1334;; (but with numbers increased by one)
1335
1336(define_expand "call_value"
1337 [(parallel [(set (match_operand 0)
1338 (call (match_operand 1 "memory_operand" "")
1339 (match_operand 2)))
1f7b8028
CJW		 1340 (clobber (reg:SI LP_REGNUM))
1341 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1342 ""
1343 ""
1344)
1345
1346(define_insn "*call_value_register"
1347 [(parallel [(set (match_operand 0)
1348 (call (mem (match_operand:SI 1 "register_operand" "r, r"))
1349 (match_operand 2)))
1f7b8028
CJW		 1350 (clobber (reg:SI LP_REGNUM))
1351 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1352 ""
1353 "@
1354 jral5\t%1
1355 jral\t%1"
1356 [(set_attr "type" "branch,branch")
1357 (set_attr "length" " 2, 4")])
1358
1359(define_insn "*call_value_immediate"
1360 [(parallel [(set (match_operand 0)
1361 (call (mem (match_operand:SI 1 "immediate_operand" "i"))
1362 (match_operand 2)))
1f7b8028
CJW		 1363 (clobber (reg:SI LP_REGNUM))
1364 (clobber (reg:SI TA_REGNUM))])]
9304f876 1365 ""
1f7b8028
CJW		 1366{
1367 if (TARGET_CMODEL_LARGE)
1368 return "bal\t%1";
1369 else
1370 return "jal\t%1";
1371}
9304f876 1372 [(set_attr "type" "branch")
1f7b8028
CJW		 1373 (set (attr "length")
1374 (if_then_else (match_test "TARGET_CMODEL_LARGE")
1375 (const_int 12)
1376 (const_int 4)))])
9304f876
CJW		 1377
1378
d6529176
CJW		 1379;; ----------------------------------------------------------------------------
1380
1381;; The sibcall patterns.
1382
1383;; sibcall
cc48a87f 1384;; sibcall_internal
d6529176
CJW		 1385
1386(define_expand "sibcall"
1387 [(parallel [(call (match_operand 0 "memory_operand" "")
1388 (const_int 0))
1389 (clobber (reg:SI TA_REGNUM))
1390 (return)])]
cc48a87f 1391 "")
d6529176 1392
cc48a87f
CJW		 1393(define_insn "sibcall_internal"
1394 [(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, i"))
d6529176
CJW		 1395 (match_operand 1))
1396 (clobber (reg:SI TA_REGNUM))
1397 (return)])]
1398 ""
1399{
cc48a87f
CJW		 1400 switch (which_alternative)
1401 {
1402 case 0:
1403 if (TARGET_16_BIT)
1404 return "jr5\t%0";
1405 else
1406 return "jr\t%0";
1407 case 1:
1408 if (nds32_long_call_p (operands[0]))
1409 return "b\t%0";
1410 else
1411 return "j\t%0";
1412 default:
1413 gcc_unreachable ();
1414 }
d6529176 1415}
30feb954 1416 [(set_attr "enabled" "yes")
cc48a87f
CJW		 1417 (set_attr "type" "branch")
1418 (set_attr_alternative "length"
1419 [
1420 ;; Alternative 0
1421 (if_then_else (match_test "TARGET_16_BIT")
1422 (const_int 2)
1423 (const_int 4))
1424 ;; Alternative 1
1425 (if_then_else (match_test "nds32_long_call_p (operands[0])")
1426 (const_int 12)
1427 (const_int 4))
1428 ])]
1429)
d6529176
CJW		 1430
1431;; sibcall_value
cc48a87f 1432;; sibcall_value_internal
d6529176
CJW		 1433;; sibcall_value_immediate
1434
1435(define_expand "sibcall_value"
1436 [(parallel [(set (match_operand 0)
1437 (call (match_operand 1 "memory_operand" "")
1438 (const_int 0)))
1439 (clobber (reg:SI TA_REGNUM))
1440 (return)])]
cc48a87f 1441 "")
d6529176 1442
cc48a87f 1443(define_insn "sibcall_value_internal"
d6529176 1444 [(parallel [(set (match_operand 0)
cc48a87f 1445 (call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, i"))
d6529176
CJW		 1446 (match_operand 2)))
1447 (clobber (reg:SI TA_REGNUM))
1448 (return)])]
1449 ""
1450{
cc48a87f
CJW		 1451 switch (which_alternative)
1452 {
1453 case 0:
1454 if (TARGET_16_BIT)
1455 return "jr5\t%1";
1456 else
1457 return "jr\t%1";
1458 case 1:
1459 if (nds32_long_call_p (operands[1]))
1460 return "b\t%1";
1461 else
1462 return "j\t%1";
1463 default:
1464 gcc_unreachable ();
1465 }
d6529176 1466}
30feb954 1467 [(set_attr "enabled" "yes")
cc48a87f
CJW		 1468 (set_attr "type" "branch")
1469 (set_attr_alternative "length"
1470 [
1471 ;; Alternative 0
1472 (if_then_else (match_test "TARGET_16_BIT")
1473 (const_int 2)
1474 (const_int 4))
1475 ;; Alternative 1
1476 (if_then_else (match_test "nds32_long_call_p (operands[1])")
1477 (const_int 12)
1478 (const_int 4))
1479 ])]
1480)
d6529176
CJW		 1481
1482;; ----------------------------------------------------------------------------
1483
9304f876
CJW		 1484;; prologue and epilogue.
1485
1486(define_expand "prologue" [(const_int 0)]
1487 ""
1488{
2da1e7c0 1489 /* Note that only under V3/V3M ISA, we could use v3push prologue.
a6c7e777
MC		 1490 In addition, we need to check if v3push is indeed available. */
1491 if (NDS32_V3PUSH_AVAILABLE_P)
9304f876
CJW		 1492 nds32_expand_prologue_v3push ();
1493 else
1494 nds32_expand_prologue ();
1495 DONE;
1496})
1497
1498(define_expand "epilogue" [(const_int 0)]
1499 ""
1500{
2da1e7c0 1501 /* Note that only under V3/V3M ISA, we could use v3pop epilogue.
a6c7e777
MC		 1502 In addition, we need to check if v3push is indeed available. */
1503 if (NDS32_V3PUSH_AVAILABLE_P)
d6529176
CJW		 1504 nds32_expand_epilogue_v3pop (false);
1505 else
1506 nds32_expand_epilogue (false);
1507 DONE;
1508})
1509
1510(define_expand "sibcall_epilogue" [(const_int 0)]
1511 ""
1512{
1513 /* Pass true to indicate that this is sibcall epilogue and
1514 exit from a function without the final branch back to the
1515 calling function. */
a6c7e777 1516 nds32_expand_epilogue (true);
d6529176 1517
9304f876
CJW		 1518 DONE;
1519})
1520
1521
1522;; nop instruction.
1523
1524(define_insn "nop"
1525 [(const_int 0)]
1526 ""
1527{
1528 if (TARGET_16_BIT)
1529 return "nop16";
1530 else
1531 return "nop";
1532}
1533 [(set_attr "type" "misc")
30feb954 1534 (set_attr "enabled" "yes")
9304f876
CJW		 1535 (set (attr "length")
1536 (if_then_else (match_test "TARGET_16_BIT")
1537 (const_int 2)
1538 (const_int 4)))])
1539
1540
1541;; ----------------------------------------------------------------------------
1542;; Stack push/pop operations
1543;; ----------------------------------------------------------------------------
1544
1545;; The pattern for stack push.
1546;; Both stack_push_multiple and stack_v3push use the following pattern.
1547;; So we need to use TARGET_V3PUSH to determine the instruction length.
1548(define_insn "*stack_push"
1549 [(match_parallel 0 "nds32_stack_push_operation"
1550 [(set (mem:SI (plus:SI (reg:SI SP_REGNUM)
1551 (match_operand:SI 1 "const_int_operand" "")))
1552 (match_operand:SI 2 "register_operand" ""))
1553 ])]
1554 ""
1555{
6f3d3f9c 1556 return nds32_output_stack_push (operands[0]);
9304f876 1557}
264159d2
KC		 1558 [(set_attr "type" "store_multiple")
1559 (set_attr "combo" "12")
30feb954 1560 (set_attr "enabled" "yes")
9304f876 1561 (set (attr "length")
6f3d3f9c
CJW		 1562 (if_then_else (match_test "TARGET_V3PUSH
1563 && !nds32_isr_function_p (cfun->decl)
1564 && (cfun->machine->va_args_size == 0)")
9304f876
CJW		 1565 (const_int 2)
1566 (const_int 4)))])
1567
1568
1569;; The pattern for stack pop.
1570;; Both stack_pop_multiple and stack_v3pop use the following pattern.
1571;; So we need to use TARGET_V3PUSH to determine the instruction length.
1572(define_insn "*stack_pop"
1573 [(match_parallel 0 "nds32_stack_pop_operation"
1574 [(set (match_operand:SI 1 "register_operand" "")
1575 (mem:SI (reg:SI SP_REGNUM)))
1576 ])]
1577 ""
1578{
6f3d3f9c 1579 return nds32_output_stack_pop (operands[0]);
9304f876 1580}
264159d2
KC		 1581 [(set_attr "type" "load_multiple")
1582 (set_attr "combo" "12")
30feb954 1583 (set_attr "enabled" "yes")
9304f876 1584 (set (attr "length")
6f3d3f9c
CJW		 1585 (if_then_else (match_test "TARGET_V3PUSH
1586 && !nds32_isr_function_p (cfun->decl)
1587 && (cfun->machine->va_args_size == 0)")
9304f876
CJW		 1588 (const_int 2)
1589 (const_int 4)))])
1590
1591
1592;; ----------------------------------------------------------------------------
03390cda 1593;; Return operation patterns
9304f876
CJW		 1594;; ----------------------------------------------------------------------------
1595
03390cda
CJW		 1596;; Use this pattern to expand a return instruction
1597;; with simple_return rtx if no epilogue is required.
1598(define_expand "return"
1599 [(simple_return)]
1600 "nds32_can_use_return_insn ()"
1601 ""
1602)
9304f876 1603
03390cda
CJW		 1604;; This pattern is expanded only by the shrink-wrapping optimization
1605;; on paths where the function prologue has not been executed.
1606(define_expand "simple_return"
1607 [(simple_return)]
1608 ""
1609 ""
1610)
1611
1612(define_insn "return_internal"
1613 [(simple_return)]
9304f876
CJW		 1614 ""
1615{
1616 if (TARGET_16_BIT)
1617 return "ret5";
1618 else
1619 return "ret";
1620}
03390cda 1621 [(set_attr "type" "branch")
30feb954 1622 (set_attr "enabled" "yes")
9304f876
CJW		 1623 (set (attr "length")
1624 (if_then_else (match_test "TARGET_16_BIT")
1625 (const_int 2)
1626 (const_int 4)))])
1627
1628
1629;; ----------------------------------------------------------------------------
1630;; Jump Table patterns
1631;; ----------------------------------------------------------------------------
1632;; Need to implement ASM_OUTPUT_ADDR_VEC_ELT (for normal jump table)
1633;; or ASM_OUTPUT_ADDR_DIFF_ELT (for pc relative jump table) as well.
1634;;
1635;; operands[0]: The index to dispatch on.
1636;; operands[1]: The lower bound for indices in the table.
1637;; operands[2]: The total range of indices int the table.
1638;; i.e. The largest index minus the smallest one.
1639;; operands[3]: A label that precedes the table itself.
1640;; operands[4]: A label to jump to if the index has a value outside the bounds.
1641;;
1642;; We need to create following sequences for jump table code generation:
1643;; A) k <-- (plus (operands[0]) (-operands[1]))
1644;; B) if (gtu k operands[2]) then goto operands[4]
1645;; C) t <-- operands[3]
1646;; D) z <-- (mem (plus (k << 0 or 1 or 2) t))
1647;; E) z <-- t + z (NOTE: This is only required for pc relative jump table.)
1648;; F) jump to target with register t or z
1649;;
1650;; The steps C, D, E, and F are performed by casesi_internal pattern.
1651(define_expand "casesi"
1652 [(match_operand:SI 0 "register_operand" "r") ; index to jump on
1653 (match_operand:SI 1 "immediate_operand" "i") ; lower bound
1654 (match_operand:SI 2 "immediate_operand" "i") ; total range
1655 (match_operand:SI 3 "" "") ; table label
1656 (match_operand:SI 4 "" "")] ; Out of range label
1657 ""
1658{
1659 rtx add_tmp;
1660 rtx reg, test;
1661
1662 /* Step A: "k <-- (plus (operands[0]) (-operands[1]))". */
1663 if (operands[1] != const0_rtx)
1664 {
1665 reg = gen_reg_rtx (SImode);
1666 add_tmp = gen_int_mode (-INTVAL (operands[1]), SImode);
1667
1668 /* If the integer value is not in the range of imm15s,
8a498f99
CJW		 1669 we need to force register first because our addsi3 pattern
1670 only accept nds32_rimm15s_operand predicate. */
9304f876
CJW		 1671 add_tmp = force_reg (SImode, add_tmp);
1672
1673 emit_insn (gen_addsi3 (reg, operands[0], add_tmp));
1674 operands[0] = reg;
1675 }
1676
1677 /* Step B: "if (gtu k operands[2]) then goto operands[4]". */
1678 test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
1679 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2],
1680 operands[4]));
1681
9759608c
SB		 1682 /* Step C, D, E, and F, using another temporary register. */
1683 rtx tmp = gen_reg_rtx (SImode);
1684 emit_jump_insn (gen_casesi_internal (operands[0], operands[3], tmp));
9304f876
CJW		 1685 DONE;
1686})
1687
1688;; We are receiving operands from casesi pattern:
1689;;
1690;; operands[0]: The index that have been substracted with lower bound.
1691;; operands[1]: A label that precedes the table itself.
1692;; operands[2]: A temporary register to retrieve value in table.
1693;;
1694;; We need to perform steps C, D, E, and F:
1695;;
1696;; C) t <-- operands[1]
1697;; D) z <-- (mem (plus (operands[0] << m) t))
1698;; m is 2 for normal jump table.
1699;; m is 0, 1, or 2 for pc relative jump table based on diff size.
1700;; E) t <-- z + t (NOTE: This is only required for pc relative jump table.)
1701;; F) Jump to target with register t or z.
1702;;
1703;; The USE in this pattern is needed to tell flow analysis that this is
1704;; a CASESI insn. It has no other purpose.
1705(define_insn "casesi_internal"
1706 [(parallel [(set (pc)
1707 (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "r")
1708 (const_int 4))
1709 (label_ref (match_operand 1 "" "")))))
1710 (use (label_ref (match_dup 1)))
24f036fb 1711 (clobber (match_operand:SI 2 "register_operand" "=r"))
9304f876
CJW		 1712 (clobber (reg:SI TA_REGNUM))])]
1713 ""
1714{
1715 if (CASE_VECTOR_PC_RELATIVE)
1716 return nds32_output_casesi_pc_relative (operands);
1717 else
1718 return nds32_output_casesi (operands);
1719}
1720 [(set_attr "length" "20")
5ba6d585 1721 (set_attr "type" "branch")])
9304f876
CJW		 1722
1723;; ----------------------------------------------------------------------------
1724
1725;; Performance Extension
1726
1727(define_insn "clzsi2"
1728 [(set (match_operand:SI 0 "register_operand" "=r")
1729 (clz:SI (match_operand:SI 1 "register_operand" " r")))]
aa4b851c 1730 "TARGET_EXT_PERF"
9304f876
CJW		 1731 "clz\t%0, %1"
1732 [(set_attr "type" "alu")
1733 (set_attr "length" "4")])
1734
1735(define_insn "smaxsi3"
1736 [(set (match_operand:SI 0 "register_operand" "=r")
1737 (smax:SI (match_operand:SI 1 "register_operand" " r")
1738 (match_operand:SI 2 "register_operand" " r")))]
aa4b851c 1739 "TARGET_EXT_PERF"
9304f876
CJW		 1740 "max\t%0, %1, %2"
1741 [(set_attr "type" "alu")
1742 (set_attr "length" "4")])
1743
1744(define_insn "sminsi3"
1745 [(set (match_operand:SI 0 "register_operand" "=r")
1746 (smin:SI (match_operand:SI 1 "register_operand" " r")
1747 (match_operand:SI 2 "register_operand" " r")))]
aa4b851c 1748 "TARGET_EXT_PERF"
9304f876
CJW		 1749 "min\t%0, %1, %2"
1750 [(set_attr "type" "alu")
1751 (set_attr "length" "4")])
1752
1753(define_insn "*btst"
1754 [(set (match_operand:SI 0 "register_operand" "= r")
1755 (zero_extract:SI (match_operand:SI 1 "register_operand" " r")
1756 (const_int 1)
1757 (match_operand:SI 2 "immediate_operand" " Iu05")))]
aa4b851c 1758 "TARGET_EXT_PERF"
9304f876
CJW		 1759 "btst\t%0, %1, %2"
1760 [(set_attr "type" "alu")
1761 (set_attr "length" "4")])
1762
1763;; ----------------------------------------------------------------------------
aa2642ef
CJW		 1764
1765;; Pseudo NOPs
1766
c4d8d050
CJW		 1767(define_insn "relax_group"
1768 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_RELAX_GROUP)]
1769 ""
1770 ".relax_hint %0"
1771 [(set_attr "length" "0")]
1772)
1773
aa2642ef
CJW		 1774(define_insn "pop25return"
1775 [(return)
1776 (unspec_volatile:SI [(reg:SI LP_REGNUM)] UNSPEC_VOLATILE_POP25_RETURN)]
1777 ""
1778 "! return for pop 25"
1779 [(set_attr "length" "0")]
1780)
1781
1782;; ----------------------------------------------------------------------------
Mirror of https://gcc.gnu.org/git/gcc.git