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[NDS32] Enable relax hint by default.
[thirdparty/gcc.git] / gcc / config / nds32 / nds32.md
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9304f876 1;; Machine description of Andes NDS32 cpu for GNU compiler
85ec4feb 2;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
9304f876
CJW		 3;; Contributed by Andes Technology Corporation.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15;; License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
22
23;; Include predicates definition.
24(include "predicates.md")
25
26;; Include constraints definition.
27(include "constraints.md")
28
29;; Include iterators definition.
30(include "iterators.md")
31
32;; Include pipelines definition.
33(include "pipelines.md")
34
35
36;; Include constants definition.
37(include "constants.md")
38
39
40;; Include intrinsic functions definition.
41(include "nds32-intrinsic.md")
42
43;; Include block move for nds32 multiple load/store behavior.
44(include "nds32-multiple.md")
45
46;; Include DImode/DFmode operations.
47(include "nds32-doubleword.md")
48
49;; Include peephole patterns.
50(include "nds32-peephole2.md")
51
52
53;; Insn type, it is used to default other attribute values.
54(define_attr "type"
5ba6d585 55 "unknown,load,store,load_multiple,store_multiple,alu,alu_shift,mul,mac,div,branch,call,misc"
9304f876
CJW		 56 (const_string "unknown"))
57
0aa683b3
CJW		 58;; Insn sub-type
59(define_attr "subtype"
60 "simple,shift"
61 (const_string "simple"))
62
9304f876
CJW		 63;; Length, in bytes, default is 4-bytes.
64(define_attr "length" "" (const_int 4))
65
264159d2
KC		 66;; Indicate the amount of micro instructions.
67(define_attr "combo"
68 "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25"
69 (const_string "1"))
9304f876 70
9be6885b
KC		 71;; Insn in which feature set, it is used to enable/disable insn alternatives.
72;; v1 : Baseline Instructions
73;; v2 : Baseline Version 2 Instructions
74;; v3m : Baseline Version 3m Instructions
75;; v3 : Baseline Version 3 Instructions
76;; pe1 : Performance Extension Instructions
77;; pe2 : Performance Extension Version 2 Instructions
78;; se : String Extension instructions
79(define_attr "feature"
80 "v1,v2,v3m,v3,pe1,pe2,se"
81 (const_string "v1"))
82
9304f876
CJW		 83;; Enabled, which is used to enable/disable insn alternatives.
84;; Note that we use length and TARGET_16_BIT here as criteria.
9be6885b
KC		 85;; If the instruction pattern already check TARGET_16_BIT to determine
86;; the length by itself, its enabled attribute should be customized to
87;; avoid the conflict between length attribute and this default setting.
30feb954 88(define_attr "enabled" "no,yes"
9be6885b
KC		 89 (if_then_else
90 (and (eq_attr "length" "2")
91 (match_test "!TARGET_16_BIT"))
92 (const_string "no")
93 (cond [(eq_attr "feature" "v1") (const_string "yes")
94 (eq_attr "feature" "v2") (if_then_else (match_test "TARGET_ISA_V2 || TARGET_ISA_V3 || TARGET_ISA_V3M")
95 (const_string "yes")
96 (const_string "no"))
97 (eq_attr "feature" "v3") (if_then_else (match_test "TARGET_ISA_V3")
98 (const_string "yes")
99 (const_string "no"))
100 (eq_attr "feature" "v3m") (if_then_else (match_test "TARGET_ISA_V3 || TARGET_ISA_V3M")
101 (const_string "yes")
102 (const_string "no"))
103 (eq_attr "feature" "pe1") (if_then_else (match_test "TARGET_EXT_PERF")
104 (const_string "yes")
105 (const_string "no"))
106 (eq_attr "feature" "pe2") (if_then_else (match_test "TARGET_EXT_PERF2")
107 (const_string "yes")
108 (const_string "no"))
109 (eq_attr "feature" "se") (if_then_else (match_test "TARGET_EXT_STRING")
110 (const_string "yes")
111 (const_string "no"))]
112 (const_string "yes"))))
9304f876
CJW		 113
114
115;; ----------------------------------------------------------------------------
116
117
118;; Move instructions.
119
120;; For QImode and HImode, the immediate value can be fit in imm20s.
121;; So there is no need to split rtx for QI and HI patterns.
122
76dc9cb5
CJW		 123(define_expand "mov<mode>"
124 [(set (match_operand:QIHI 0 "general_operand" "")
125 (match_operand:QIHI 1 "general_operand" ""))]
9304f876
CJW		 126 ""
127{
128 /* Need to force register if mem <- !reg. */
129 if (MEM_P (operands[0]) && !REG_P (operands[1]))
76dc9cb5 130 operands[1] = force_reg (<MODE>mode, operands[1]);
9304f876 131
76dc9cb5
CJW		 132 if (MEM_P (operands[1]) && optimize > 0)
133 {
134 rtx reg = gen_reg_rtx (SImode);
135
136 emit_insn (gen_zero_extend<mode>si2 (reg, operands[1]));
137 operands[1] = gen_lowpart (<MODE>mode, reg);
138 }
9304f876
CJW		 139})
140
2cf09a99
KC		 141(define_expand "movmisalign<mode>"
142 [(set (match_operand:SIDI 0 "general_operand" "")
143 (match_operand:SIDI 1 "general_operand" ""))]
144 ""
145{
146 rtx addr;
147 if (MEM_P (operands[0]) && !REG_P (operands[1]))
148 operands[1] = force_reg (<MODE>mode, operands[1]);
149
150 if (MEM_P (operands[0]))
151 {
152 addr = force_reg (Pmode, XEXP (operands[0], 0));
153 emit_insn (gen_unaligned_store<mode> (addr, operands[1]));
154 }
155 else
156 {
157 addr = force_reg (Pmode, XEXP (operands[1], 0));
158 emit_insn (gen_unaligned_load<mode> (operands[0], addr));
159 }
160 DONE;
161})
76dc9cb5 162
9304f876
CJW		 163(define_expand "movsi"
164 [(set (match_operand:SI 0 "general_operand" "")
165 (match_operand:SI 1 "general_operand" ""))]
166 ""
167{
168 /* Need to force register if mem <- !reg. */
169 if (MEM_P (operands[0]) && !REG_P (operands[1]))
170 operands[1] = force_reg (SImode, operands[1]);
171
172 /* If operands[1] is a large constant and cannot be performed
173 by a single instruction, we need to split it. */
174 if (CONST_INT_P (operands[1])
175 && !satisfies_constraint_Is20 (operands[1])
176 && !satisfies_constraint_Ihig (operands[1]))
177 {
178 rtx high20_rtx;
179 HOST_WIDE_INT low12_int;
180 rtx tmp_rtx;
181
182 tmp_rtx = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
183
184 high20_rtx = gen_int_mode ((INTVAL (operands[1]) >> 12) << 12, SImode);
185 low12_int = INTVAL (operands[1]) & 0xfff;
186
187 emit_move_insn (tmp_rtx, high20_rtx);
188 emit_move_insn (operands[0], plus_constant (SImode,
189 tmp_rtx,
190 low12_int));
191 DONE;
192 }
193})
194
195(define_insn "*mov<mode>"
8656bbcf
SC		 196 [(set (match_operand:QIHISI 0 "nonimmediate_operand" "=r, r, U45, U33, U37, U45, m, l, l, l, d, d, r, d, r, r, r")
197 (match_operand:QIHISI 1 "nds32_move_operand" " r, r, l, l, l, d, r, U45, U33, U37, U45, Ufe, m, Ip05, Is05, Is20, Ihig"))]
b4350271
KC		 198 "register_operand(operands[0], <MODE>mode)
199 || register_operand(operands[1], <MODE>mode)"
9304f876
CJW		 200{
201 switch (which_alternative)
202 {
203 case 0:
204 return "mov55\t%0, %1";
205 case 1:
206 return "ori\t%0, %1, 0";
207 case 2:
208 case 3:
209 case 4:
210 case 5:
211 return nds32_output_16bit_store (operands, <byte>);
212 case 6:
213 return nds32_output_32bit_store (operands, <byte>);
214 case 7:
215 case 8:
216 case 9:
217 case 10:
9304f876 218 case 11:
8656bbcf 219 return nds32_output_16bit_load (operands, <byte>);
9304f876 220 case 12:
8656bbcf 221 return nds32_output_32bit_load (operands, <byte>);
9304f876 222 case 13:
8656bbcf 223 return "movpi45\t%0, %1";
9304f876 224 case 14:
8656bbcf 225 return "movi55\t%0, %1";
9304f876 226 case 15:
8656bbcf
SC		 227 return "movi\t%0, %1";
228 case 16:
9304f876
CJW		 229 return "sethi\t%0, hi20(%1)";
230 default:
231 gcc_unreachable ();
232 }
233}
8656bbcf
SC		 234 [(set_attr "type" "alu,alu,store,store,store,store,store,load,load,load,load,load,load,alu,alu,alu,alu")
235 (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 4, 2, 2, 4, 4")])
9304f876
CJW		 236
237
238;; We use nds32_symbolic_operand to limit that only CONST/SYMBOL_REF/LABEL_REF
239;; are able to match such instruction template.
c4d8d050 240(define_insn "move_addr"
9304f876
CJW		 241 [(set (match_operand:SI 0 "register_operand" "=l, r")
242 (match_operand:SI 1 "nds32_symbolic_operand" " i, i"))]
243 ""
244 "la\t%0, %1"
5ba6d585 245 [(set_attr "type" "alu")
9304f876
CJW		 246 (set_attr "length" "8")])
247
248
c4d8d050 249(define_insn "sethi"
9304f876
CJW		 250 [(set (match_operand:SI 0 "register_operand" "=r")
251 (high:SI (match_operand:SI 1 "nds32_symbolic_operand" " i")))]
252 ""
253 "sethi\t%0, hi20(%1)"
254 [(set_attr "type" "alu")
255 (set_attr "length" "4")])
256
257
c4d8d050 258(define_insn "lo_sum"
9304f876
CJW		 259 [(set (match_operand:SI 0 "register_operand" "=r")
260 (lo_sum:SI (match_operand:SI 1 "register_operand" " r")
261 (match_operand:SI 2 "nds32_symbolic_operand" " i")))]
262 ""
263 "ori\t%0, %1, lo12(%2)"
264 [(set_attr "type" "alu")
265 (set_attr "length" "4")])
266
267
268;; ----------------------------------------------------------------------------
269
270;; Zero extension instructions.
271
272(define_insn "zero_extend<mode>si2"
273 [(set (match_operand:SI 0 "register_operand" "=l, r, l, *r")
274 (zero_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, U33, m")))]
275 ""
276{
277 switch (which_alternative)
278 {
279 case 0:
280 return "ze<size>33\t%0, %1";
281 case 1:
282 return "ze<size>\t%0, %1";
283 case 2:
284 return nds32_output_16bit_load (operands, <byte>);
285 case 3:
286 return nds32_output_32bit_load (operands, <byte>);
287
288 default:
289 gcc_unreachable ();
290 }
291}
292 [(set_attr "type" "alu,alu,load,load")
293 (set_attr "length" " 2, 4, 2, 4")])
294
295
296;; Sign extension instructions.
297
298(define_insn "extend<mode>si2"
299 [(set (match_operand:SI 0 "register_operand" "=l, r, r")
300 (sign_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, m")))]
301 ""
302{
303 switch (which_alternative)
304 {
305 case 0:
306 return "se<size>33\t%0, %1";
307 case 1:
308 return "se<size>\t%0, %1";
309 case 2:
310 return nds32_output_32bit_load_s (operands, <byte>);
311
312 default:
313 gcc_unreachable ();
314 }
315}
316 [(set_attr "type" "alu,alu,load")
317 (set_attr "length" " 2, 4, 4")])
318
319
320;; ----------------------------------------------------------------------------
321
322;; Arithmetic instructions.
323
5c36be57
CJW		 324(define_insn "addsi3"
325 [(set (match_operand:SI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r")
326 (plus:SI (match_operand:SI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r")
a3b13564 327 (match_operand:SI 2 "nds32_rimm15s_operand" " In05,In03,Iu05,Iu03, r, l,Is10,Iu06, Is15, r")))]
9304f876
CJW		 328 ""
329{
330 switch (which_alternative)
331 {
332 case 0:
333 /* addi Rt4,Rt4,-x ==> subi45 Rt4,x
8a498f99 334 where 0 <= x <= 31 */
9304f876
CJW		 335 operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
336 return "subi45\t%0, %2";
337 case 1:
338 /* addi Rt3,Ra3,-x ==> subi333 Rt3,Ra3,x
8a498f99 339 where 0 <= x <= 7 */
9304f876
CJW		 340 operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
341 return "subi333\t%0, %1, %2";
342 case 2:
343 return "addi45\t%0, %2";
344 case 3:
345 return "addi333\t%0, %1, %2";
346 case 4:
347 return "add45\t%0, %2";
348 case 5:
349 return "add333\t%0, %1, %2";
350 case 6:
351 return "addi10.sp\t%2";
352 case 7:
353 return "addri36.sp\t%0, %2";
354 case 8:
355 return "addi\t%0, %1, %2";
356 case 9:
357 return "add\t%0, %1, %2";
358
359 default:
360 gcc_unreachable ();
361 }
362}
9be6885b
KC		 363 [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
364 (set_attr "length" " 2, 2, 2, 2, 2, 2, 2, 2, 4, 4")
365 (set_attr "feature" " v1, v1, v1, v1, v1, v1, v2, v1, v1, v1")])
9304f876 366
5c36be57
CJW		 367(define_insn "subsi3"
368 [(set (match_operand:SI 0 "register_operand" "=d, l, r, r")
369 (minus:SI (match_operand:SI 1 "nds32_rimm15s_operand" " 0, l, Is15, r")
370 (match_operand:SI 2 "register_operand" " r, l, r, r")))]
9304f876
CJW		 371 ""
372 "@
9c1a4c0f
CJW		 373 sub45\t%0, %2
374 sub333\t%0, %1, %2
375 subri\t%0, %2, %1
376 sub\t%0, %1, %2"
9304f876
CJW		 377 [(set_attr "type" "alu,alu,alu,alu")
378 (set_attr "length" " 2, 2, 4, 4")])
379
380
381;; GCC intends to simplify (plus (ashift ...) (reg))
382;; into (plus (mult ...) (reg)), so our matching pattern takes 'mult'
383;; and needs to ensure it is exact_log2 value.
384(define_insn "*add_slli"
385 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99 386 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
9304f876
CJW		 387 (match_operand:SI 2 "immediate_operand" " i"))
388 (match_operand:SI 3 "register_operand" " r")))]
b9774a97 389 "TARGET_ISA_V3 && optimize_size
9304f876
CJW		 390 && (exact_log2 (INTVAL (operands[2])) != -1)
391 && (exact_log2 (INTVAL (operands[2])) <= 31)"
392{
393 /* Get floor_log2 of the immediate value
394 so that we can generate 'add_slli' instruction. */
395 operands[2] = GEN_INT (floor_log2 (INTVAL (operands[2])));
396
397 return "add_slli\t%0, %3, %1, %2";
398}
5ba6d585
KC		 399 [(set_attr "type" "alu_shift")
400 (set_attr "combo" "2")
401 (set_attr "length" "4")])
9304f876
CJW		 402
403(define_insn "*add_srli"
a3b13564
KC		 404 [(set (match_operand:SI 0 "register_operand" "= r")
405 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
406 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
407 (match_operand:SI 3 "register_operand" " r")))]
b9774a97 408 "TARGET_ISA_V3 && optimize_size"
9304f876 409 "add_srli\t%0, %3, %1, %2"
5ba6d585
KC		 410 [(set_attr "type" "alu_shift")
411 (set_attr "combo" "2")
412 (set_attr "length" "4")])
9304f876
CJW		 413
414
415;; GCC intends to simplify (minus (reg) (ashift ...))
416;; into (minus (reg) (mult ...)), so our matching pattern takes 'mult'
417;; and needs to ensure it is exact_log2 value.
418(define_insn "*sub_slli"
419 [(set (match_operand:SI 0 "register_operand" "=r")
420 (minus:SI (match_operand:SI 1 "register_operand" " r")
421 (mult:SI (match_operand:SI 2 "register_operand" " r")
422 (match_operand:SI 3 "immediate_operand" " i"))))]
b9774a97 423 "TARGET_ISA_V3 && optimize_size
9304f876
CJW		 424 && (exact_log2 (INTVAL (operands[3])) != -1)
425 && (exact_log2 (INTVAL (operands[3])) <= 31)"
426{
427 /* Get floor_log2 of the immediate value
428 so that we can generate 'sub_slli' instruction. */
429 operands[3] = GEN_INT (floor_log2 (INTVAL (operands[3])));
430
431 return "sub_slli\t%0, %1, %2, %3";
432}
5ba6d585
KC		 433 [(set_attr "type" "alu_shift")
434 (set_attr "combo" "2")
435 (set_attr "length" "4")])
9304f876
CJW		 436
437(define_insn "*sub_srli"
77827557
CJW		 438 [(set (match_operand:SI 0 "register_operand" "= r")
439 (minus:SI (match_operand:SI 1 "register_operand" " r")
440 (lshiftrt:SI (match_operand:SI 2 "register_operand" " r")
441 (match_operand:SI 3 "nds32_imm5u_operand" " Iu05"))))]
b9774a97 442 "TARGET_ISA_V3 && optimize_size"
9304f876 443 "sub_srli\t%0, %1, %2, %3"
5ba6d585
KC		 444 [(set_attr "type" "alu_shift")
445 (set_attr "combo" "2")
446 (set_attr "length" "4")])
9304f876
CJW		 447
448
449;; Multiplication instructions.
450
451(define_insn "mulsi3"
73f793e3
RS		 452 [(set (match_operand:SI 0 "register_operand" "=w, r")
453 (mult:SI (match_operand:SI 1 "register_operand" "%0, r")
454 (match_operand:SI 2 "register_operand" " w, r")))]
9304f876
CJW		 455 ""
456 "@
9c1a4c0f
CJW		 457 mul33\t%0, %2
458 mul\t%0, %1, %2"
5ba6d585 459 [(set_attr "type" "mul,mul")
9be6885b
KC		 460 (set_attr "length" " 2, 4")
461 (set_attr "feature" "v3m, v1")])
9304f876
CJW		 462
463(define_insn "mulsidi3"
464 [(set (match_operand:DI 0 "register_operand" "=r")
465 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
466 (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
467 "TARGET_ISA_V2 || TARGET_ISA_V3"
468 "mulsr64\t%0, %1, %2"
5ba6d585 469 [(set_attr "type" "mul")
9304f876
CJW		 470 (set_attr "length" "4")])
471
472(define_insn "umulsidi3"
473 [(set (match_operand:DI 0 "register_operand" "=r")
474 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " r"))
475 (zero_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
476 "TARGET_ISA_V2 || TARGET_ISA_V3"
477 "mulr64\t%0, %1, %2"
5ba6d585 478 [(set_attr "type" "mul")
9304f876
CJW		 479 (set_attr "length" "4")])
480
481
482;; Multiply-accumulate instructions.
483
484(define_insn "*maddr32_0"
485 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 486 (plus:SI (match_operand:SI 3 "register_operand" " 0")
487 (mult:SI (match_operand:SI 1 "register_operand" " r")
488 (match_operand:SI 2 "register_operand" " r"))))]
9304f876
CJW		 489 ""
490 "maddr32\t%0, %1, %2"
5ba6d585 491 [(set_attr "type" "mac")
9304f876
CJW		 492 (set_attr "length" "4")])
493
494(define_insn "*maddr32_1"
495 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 496 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
497 (match_operand:SI 2 "register_operand" " r"))
498 (match_operand:SI 3 "register_operand" " 0")))]
9304f876
CJW		 499 ""
500 "maddr32\t%0, %1, %2"
5ba6d585 501 [(set_attr "type" "mac")
9304f876
CJW		 502 (set_attr "length" "4")])
503
504(define_insn "*msubr32"
505 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 506 (minus:SI (match_operand:SI 3 "register_operand" " 0")
507 (mult:SI (match_operand:SI 1 "register_operand" " r")
508 (match_operand:SI 2 "register_operand" " r"))))]
9304f876
CJW		 509 ""
510 "msubr32\t%0, %1, %2"
5ba6d585 511 [(set_attr "type" "mac")
9304f876
CJW		 512 (set_attr "length" "4")])
513
514
515;; Div Instructions.
516
517(define_insn "divmodsi4"
518 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 519 (div:SI (match_operand:SI 1 "register_operand" " r")
520 (match_operand:SI 2 "register_operand" " r")))
9304f876 521 (set (match_operand:SI 3 "register_operand" "=r")
8a498f99 522 (mod:SI (match_dup 1) (match_dup 2)))]
9304f876
CJW		 523 ""
524 "divsr\t%0, %3, %1, %2"
5ba6d585 525 [(set_attr "type" "div")
9304f876
CJW		 526 (set_attr "length" "4")])
527
528(define_insn "udivmodsi4"
529 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 530 (udiv:SI (match_operand:SI 1 "register_operand" " r")
531 (match_operand:SI 2 "register_operand" " r")))
9304f876 532 (set (match_operand:SI 3 "register_operand" "=r")
8a498f99 533 (umod:SI (match_dup 1) (match_dup 2)))]
9304f876
CJW		 534 ""
535 "divr\t%0, %3, %1, %2"
5ba6d585 536 [(set_attr "type" "div")
9304f876
CJW		 537 (set_attr "length" "4")])
538
50ea1e4a
CJW		 539;; divsr/divr will keep quotient only when quotient and remainder is the same
540;; register in our ISA spec, it's can reduce 1 register presure if we don't
541;; want remainder.
542(define_insn "divsi4"
543 [(set (match_operand:SI 0 "register_operand" "=r")
544 (div:SI (match_operand:SI 1 "register_operand" " r")
545 (match_operand:SI 2 "register_operand" " r")))]
546 ""
547 "divsr\t%0, %0, %1, %2"
548 [(set_attr "type" "div")
549 (set_attr "length" "4")])
550
551(define_insn "udivsi4"
552 [(set (match_operand:SI 0 "register_operand" "=r")
553 (udiv:SI (match_operand:SI 1 "register_operand" " r")
554 (match_operand:SI 2 "register_operand" " r")))]
555 ""
556 "divr\t%0, %0, %1, %2"
557 [(set_attr "type" "div")
558 (set_attr "length" "4")])
9304f876
CJW		 559
560;; ----------------------------------------------------------------------------
561
562;; Boolean instructions.
563;; Note: We define the DImode versions in nds32-doubleword.md.
564
565;; ----------------------------------------------------------------------------
566;; 'AND' operation
567;; ----------------------------------------------------------------------------
568
569(define_insn "bitc"
570 [(set (match_operand:SI 0 "register_operand" "=r")
571 (and:SI (not:SI (match_operand:SI 1 "register_operand" " r"))
572 (match_operand:SI 2 "register_operand" " r")))]
573 "TARGET_ISA_V3"
574 "bitc\t%0, %2, %1"
575 [(set_attr "type" "alu")
576 (set_attr "length" "4")]
577)
578
a3b13564
KC		 579(define_expand "andsi3"
580 [(set (match_operand:SI 0 "register_operand" "")
581 (and:SI (match_operand:SI 1 "register_operand" "")
582 (match_operand:SI 2 "nds32_reg_constant_operand" "")))]
583 ""
584{
585 if (CONST_INT_P (operands[2])
586 && !nds32_and_operand (operands[2], SImode))
587 {
588 nds32_expand_constant (SImode, INTVAL (operands[2]),
589 operands[0], operands[1]);
590 DONE;
591 }
592})
593
594(define_insn "*andsi3"
595 [(set (match_operand:SI 0 "register_operand" "=l, r, l, l, l, l, l, l, r, r, r, r, r")
596 (and:SI (match_operand:SI 1 "register_operand" "%0, r, l, l, l, l, 0, 0, r, r, r, r, r")
597 (match_operand:SI 2 "nds32_and_operand" " l, r,Izeb,Izeh,Ixls,Ix11,Ibms,Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))]
9304f876
CJW		 598 ""
599{
600 HOST_WIDE_INT mask = INTVAL (operands[2]);
9304f876
CJW		 601
602 /* 16-bit andi instructions:
603 andi Rt3,Ra3,0xff -> zeb33 Rt3,Ra3
604 andi Rt3,Ra3,0xffff -> zeh33 Rt3,Ra3
605 andi Rt3,Ra3,0x01 -> xlsb33 Rt3,Ra3
606 andi Rt3,Ra3,0x7ff -> x11b33 Rt3,Ra3
607 andi Rt3,Rt3,2^imm3u -> bmski33 Rt3,imm3u
608 andi Rt3,Rt3,(2^(imm3u+1))-1 -> fexti33 Rt3,imm3u. */
609
610 switch (which_alternative)
611 {
612 case 0:
613 return "and33\t%0, %2";
614 case 1:
615 return "and\t%0, %1, %2";
616 case 2:
617 return "zeb33\t%0, %1";
618 case 3:
619 return "zeh33\t%0, %1";
620 case 4:
621 return "xlsb33\t%0, %1";
622 case 5:
623 return "x11b33\t%0, %1";
624 case 6:
a3b13564 625 return "bmski33\t%0, %B2";
9304f876
CJW		 626 case 7:
627 operands[2] = GEN_INT (floor_log2 (mask + 1) - 1);
628 return "fexti33\t%0, %2";
629 case 8:
630 return "zeb\t%0, %1";
631 case 9:
632 return "zeh\t%0, %1";
633 case 10:
634 return "andi\t%0, %1, %2";
635 case 11:
636 operands[2] = GEN_INT (~mask);
637 return "bitci\t%0, %1, %2";
638 case 12:
a3b13564 639 return "bclr\t%0, %1, %b2";
9304f876
CJW		 640
641 default:
642 gcc_unreachable ();
643 }
644}
9be6885b
KC		 645 [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
646 (set_attr "length" " 2, 4, 2, 2, 2, 2, 2, 2, 4, 4, 4, 4, 4")
647 (set_attr "feature" "v3m, v1, v1, v1, v1, v1,v3m,v3m, v1, v1, v1, v3,pe1")])
9304f876
CJW		 648
649(define_insn "*and_slli"
77827557
CJW		 650 [(set (match_operand:SI 0 "register_operand" "= r")
651 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
652 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
653 (match_operand:SI 3 "register_operand" " r")))]
b9774a97 654 "TARGET_ISA_V3 && optimize_size"
9304f876 655 "and_slli\t%0, %3, %1, %2"
5ba6d585
KC		 656 [(set_attr "type" "alu_shift")
657 (set_attr "length" "4")])
9304f876
CJW		 658
659(define_insn "*and_srli"
77827557
CJW		 660 [(set (match_operand:SI 0 "register_operand" "= r")
661 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
662 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
663 (match_operand:SI 3 "register_operand" " r")))]
b9774a97 664 "TARGET_ISA_V3 && optimize_size"
9304f876 665 "and_srli\t%0, %3, %1, %2"
5ba6d585
KC		 666 [(set_attr "type" "alu_shift")
667 (set_attr "length" "4")])
9304f876
CJW		 668
669
670;; ----------------------------------------------------------------------------
671;; 'OR' operation
672;; ----------------------------------------------------------------------------
673
674;; For V3/V3M ISA, we have 'or33' instruction.
675;; So we can identify 'or Rt3,Rt3,Ra3' case and set its length to be 2.
a3b13564
KC		 676
677(define_expand "iorsi3"
678 [(set (match_operand:SI 0 "register_operand" "")
679 (ior:SI (match_operand:SI 1 "register_operand" "")
680 (match_operand:SI 2 "general_operand" "")))]
9304f876
CJW		 681 ""
682{
a3b13564
KC		 683 if (!nds32_ior_operand (operands[2], SImode))
684 operands[2] = force_reg (SImode, operands[2]);
685})
9304f876 686
a3b13564
KC		 687(define_insn "*iorsi3"
688 [(set (match_operand:SI 0 "register_operand" "=l, r, r, r")
689 (ior:SI (match_operand:SI 1 "register_operand" "%0, r, r, r")
690 (match_operand:SI 2 "nds32_ior_operand" " l, r, Iu15, Ie15")))]
691 ""
692 "@
693 or33\t%0, %2
694 or\t%0, %1, %2
695 ori\t%0, %1, %2
696 bset\t%0, %1, %B2"
697 [(set_attr "type" "alu,alu,alu,alu")
698 (set_attr "length" " 2, 4, 4, 4")
699 (set_attr "feature" "v3m, v1, v1,pe1")])
9304f876
CJW		 700
701(define_insn "*or_slli"
a3b13564
KC		 702 [(set (match_operand:SI 0 "register_operand" "= r")
703 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
704 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
705 (match_operand:SI 3 "register_operand" " r")))]
b9774a97 706 "TARGET_ISA_V3 && optimize_size"
9304f876 707 "or_slli\t%0, %3, %1, %2"
5ba6d585
KC		 708 [(set_attr "type" "alu_shift")
709 (set_attr "length" "4")])
9304f876
CJW		 710
711(define_insn "*or_srli"
a3b13564
KC		 712 [(set (match_operand:SI 0 "register_operand" "= r")
713 (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
714 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
715 (match_operand:SI 3 "register_operand" " r")))]
b9774a97 716 "TARGET_ISA_V3 && optimize_size"
9304f876 717 "or_srli\t%0, %3, %1, %2"
5ba6d585
KC		 718 [(set_attr "type" "alu_shift")
719 (set_attr "length" "4")])
9304f876
CJW		 720
721
722;; ----------------------------------------------------------------------------
723;; 'XOR' operation
724;; ----------------------------------------------------------------------------
725
726;; For V3/V3M ISA, we have 'xor33' instruction.
727;; So we can identify 'xor Rt3,Rt3,Ra3' case and set its length to be 2.
a3b13564
KC		 728
729(define_expand "xorsi3"
730 [(set (match_operand:SI 0 "register_operand" "")
731 (xor:SI (match_operand:SI 1 "register_operand" "")
732 (match_operand:SI 2 "general_operand" "")))]
9304f876
CJW		 733 ""
734{
a3b13564
KC		 735 if (!nds32_xor_operand (operands[2], SImode))
736 operands[2] = force_reg (SImode, operands[2]);
737})
9304f876 738
a3b13564
KC		 739(define_insn "*xorsi3"
740 [(set (match_operand:SI 0 "register_operand" "=l, r, r, r")
741 (xor:SI (match_operand:SI 1 "register_operand" "%0, r, r, r")
742 (match_operand:SI 2 "nds32_xor_operand" " l, r, Iu15, It15")))]
743 ""
744 "@
745 xor33\t%0, %2
746 xor\t%0, %1, %2
747 xori\t%0, %1, %2
748 btgl\t%0, %1, %B2"
9be6885b
KC		 749 [(set_attr "type" "alu,alu,alu,alu")
750 (set_attr "length" " 2, 4, 4, 4")
751 (set_attr "feature" "v3m, v1, v1,pe1")])
9304f876
CJW		 752
753(define_insn "*xor_slli"
754 [(set (match_operand:SI 0 "register_operand" "= r")
755 (xor:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
a3b13564 756 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
9304f876 757 (match_operand:SI 3 "register_operand" " r")))]
b9774a97 758 "TARGET_ISA_V3 && optimize_size"
9304f876 759 "xor_slli\t%0, %3, %1, %2"
5ba6d585
KC		 760 [(set_attr "type" "alu_shift")
761 (set_attr "length" "4")])
9304f876
CJW		 762
763(define_insn "*xor_srli"
a3b13564
KC		 764 [(set (match_operand:SI 0 "register_operand" "= r")
765 (xor:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
766 (match_operand:SI 2 "nds32_imm5u_operand" " Iu05"))
767 (match_operand:SI 3 "register_operand" " r")))]
b9774a97 768 "TARGET_ISA_V3 && optimize_size"
9304f876 769 "xor_srli\t%0, %3, %1, %2"
5ba6d585
KC		 770 [(set_attr "type" "alu_shift")
771 (set_attr "length" "4")])
9304f876
CJW		 772
773;; Rotate Right Instructions.
774
a3b13564
KC		 775(define_insn "*rotrsi3"
776 [(set (match_operand:SI 0 "register_operand" "= r, r")
777 (rotatert:SI (match_operand:SI 1 "register_operand" " r, r")
778 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r")))]
9304f876
CJW		 779 ""
780 "@
9c1a4c0f
CJW		 781 rotri\t%0, %1, %2
782 rotr\t%0, %1, %2"
5ba6d585 783 [(set_attr "type" " alu, alu")
0aa683b3 784 (set_attr "subtype" "shift,shift")
5ba6d585 785 (set_attr "length" " 4, 4")])
9304f876
CJW		 786
787
788;; ----------------------------------------------------------------------------
789;; 'NEG' operation
790;; ----------------------------------------------------------------------------
791
792;; For V3/V3M ISA, we have 'neg33' instruction.
793;; So we can identify 'xor Rt3,Ra3' case and set its length to be 2.
794;; And for V2 ISA, there is NO 'neg33' instruction.
795;; The only option is to use 'subri A,B,0' (its semantic is 'A = 0 - B').
796(define_insn "negsi2"
3fbbd9e5
CJW		 797 [(set (match_operand:SI 0 "register_operand" "=l, r")
798 (neg:SI (match_operand:SI 1 "register_operand" " l, r")))]
9304f876
CJW		 799 ""
800 "@
801 neg33\t%0, %1
802 subri\t%0, %1, 0"
3fbbd9e5
CJW		 803 [(set_attr "type" "alu,alu")
804 (set_attr "length" " 2, 4")
805 (set_attr "feature" "v3m, v1")])
9304f876
CJW		 806
807;; ----------------------------------------------------------------------------
808;; 'ONE_COMPLIMENT' operation
809;; ----------------------------------------------------------------------------
810
811;; For V3/V3M ISA, we have 'not33' instruction.
812;; So we can identify 'not Rt3,Ra3' case and set its length to be 2.
813(define_insn "one_cmplsi2"
814 [(set (match_operand:SI 0 "register_operand" "=w, r")
815 (not:SI (match_operand:SI 1 "register_operand" " w, r")))]
816 ""
817 "@
818 not33\t%0, %1
819 nor\t%0, %1, %1"
9be6885b
KC		 820 [(set_attr "type" "alu,alu")
821 (set_attr "length" " 2, 4")
822 (set_attr "feature" "v3m, v1")])
9304f876
CJW		 823
824
825;; ----------------------------------------------------------------------------
826
827;; Shift instructions.
828
a3b13564
KC		 829(define_expand "<shift>si3"
830 [(set (match_operand:SI 0 "register_operand" "")
831 (shift_rotate:SI (match_operand:SI 1 "register_operand" "")
832 (match_operand:SI 2 "nds32_rimm5u_operand" "")))]
833 ""
834{
835 if (operands[2] == const0_rtx)
836 {
837 emit_move_insn (operands[0], operands[1]);
838 DONE;
839 }
840})
841
842(define_insn "*ashlsi3"
843 [(set (match_operand:SI 0 "register_operand" "= l, r, r")
844 (ashift:SI (match_operand:SI 1 "register_operand" " l, r, r")
845 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu03, Iu05, r")))]
9304f876
CJW		 846 ""
847 "@
9c1a4c0f
CJW		 848 slli333\t%0, %1, %2
849 slli\t%0, %1, %2
850 sll\t%0, %1, %2"
0aa683b3
CJW		 851 [(set_attr "type" " alu, alu, alu")
852 (set_attr "subtype" "shift,shift,shift")
853 (set_attr "length" " 2, 4, 4")])
a3b13564
KC		 854
855(define_insn "*ashrsi3"
856 [(set (match_operand:SI 0 "register_operand" "= d, r, r")
857 (ashiftrt:SI (match_operand:SI 1 "register_operand" " 0, r, r")
858 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, Iu05, r")))]
9304f876
CJW		 859 ""
860 "@
9c1a4c0f
CJW		 861 srai45\t%0, %2
862 srai\t%0, %1, %2
863 sra\t%0, %1, %2"
0aa683b3
CJW		 864 [(set_attr "type" " alu, alu, alu")
865 (set_attr "subtype" "shift,shift,shift")
866 (set_attr "length" " 2, 4, 4")])
9304f876 867
a3b13564
KC		 868(define_insn "*lshrsi3"
869 [(set (match_operand:SI 0 "register_operand" "= d, r, r")
870 (lshiftrt:SI (match_operand:SI 1 "register_operand" " 0, r, r")
871 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, Iu05, r")))]
9304f876
CJW		 872 ""
873 "@
9c1a4c0f
CJW		 874 srli45\t%0, %2
875 srli\t%0, %1, %2
876 srl\t%0, %1, %2"
0aa683b3
CJW		 877 [(set_attr "type" " alu, alu, alu")
878 (set_attr "subtype" "shift,shift,shift")
879 (set_attr "length" " 2, 4, 4")])
9304f876
CJW		 880
881
882;; ----------------------------------------------------------------------------
883
884;; ----------------------------------------------------------------------------
885;; Conditional Move patterns
886;; ----------------------------------------------------------------------------
887
6e9ca932
CJW		 888(define_expand "mov<mode>cc"
889 [(set (match_operand:QIHISI 0 "register_operand" "")
890 (if_then_else:QIHISI (match_operand 1 "nds32_movecc_comparison_operator" "")
891 (match_operand:QIHISI 2 "register_operand" "")
892 (match_operand:QIHISI 3 "register_operand" "")))]
893 "TARGET_CMOV && !optimize_size"
9304f876 894{
6e9ca932
CJW		 895 enum nds32_expand_result_type result = nds32_expand_movcc (operands);
896 switch (result)
9304f876 897 {
6e9ca932
CJW		 898 case EXPAND_DONE:
899 DONE;
900 break;
901 case EXPAND_FAIL:
902 FAIL;
903 break;
904 case EXPAND_CREATE_TEMPLATE:
905 break;
906 default:
907 gcc_unreachable ();
9304f876 908 }
9304f876
CJW		 909})
910
6e9ca932
CJW		 911(define_insn "cmovz<mode>"
912 [(set (match_operand:QIHISI 0 "register_operand" "=r, r")
913 (if_then_else:QIHISI (eq (match_operand:SI 1 "register_operand" " r, r")
9304f876 914 (const_int 0))
6e9ca932
CJW		 915 (match_operand:QIHISI 2 "register_operand" " r, 0")
916 (match_operand:QIHISI 3 "register_operand" " 0, r")))]
9304f876
CJW		 917 "TARGET_CMOV"
918 "@
919 cmovz\t%0, %2, %1
920 cmovn\t%0, %3, %1"
5ba6d585 921 [(set_attr "type" "alu")
9304f876
CJW		 922 (set_attr "length" "4")])
923
6e9ca932
CJW		 924(define_insn "cmovn<mode>"
925 [(set (match_operand:QIHISI 0 "register_operand" "=r, r")
926 (if_then_else:QIHISI (ne (match_operand:SI 1 "register_operand" " r, r")
9304f876 927 (const_int 0))
6e9ca932
CJW		 928 (match_operand:QIHISI 2 "register_operand" " r, 0")
929 (match_operand:QIHISI 3 "register_operand" " 0, r")))]
9304f876
CJW		 930 "TARGET_CMOV"
931 "@
932 cmovn\t%0, %2, %1
933 cmovz\t%0, %3, %1"
5ba6d585 934 [(set_attr "type" "alu")
9304f876
CJW		 935 (set_attr "length" "4")])
936
6e9ca932
CJW		 937;; A hotfix to help RTL combiner to merge a cmovn insn and a zero_extend insn.
938;; It should be removed once after we change the expansion form of the cmovn.
939(define_insn "*cmovn_simplified_<mode>"
940 [(set (match_operand:QIHISI 0 "register_operand" "=r")
941 (if_then_else:QIHISI (match_operand:SI 1 "register_operand" "r")
942 (match_operand:QIHISI 2 "register_operand" "r")
943 (match_operand:QIHISI 3 "register_operand" "0")))]
944 ""
945 "cmovn\t%0, %2, %1"
946 [(set_attr "type" "alu")])
9304f876
CJW		 947
948;; ----------------------------------------------------------------------------
949;; Conditional Branch patterns
950;; ----------------------------------------------------------------------------
951
952(define_expand "cbranchsi4"
953 [(set (pc)
954 (if_then_else (match_operator 0 "comparison_operator"
955 [(match_operand:SI 1 "register_operand" "")
956 (match_operand:SI 2 "nds32_reg_constant_operand" "")])
957 (label_ref (match_operand 3 "" ""))
958 (pc)))]
959 ""
960{
6e9ca932
CJW		 961 enum nds32_expand_result_type result = nds32_expand_cbranch (operands);
962 switch (result)
9304f876 963 {
6e9ca932 964 case EXPAND_DONE:
9304f876 965 DONE;
6e9ca932
CJW		 966 break;
967 case EXPAND_FAIL:
9304f876 968 FAIL;
6e9ca932
CJW		 969 break;
970 case EXPAND_CREATE_TEMPLATE:
971 break;
972 default:
973 gcc_unreachable ();
9304f876 974 }
9304f876
CJW		 975})
976
977
6e9ca932 978(define_insn "cbranchsi4_equality_zero"
9304f876
CJW		 979 [(set (pc)
980 (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
6e9ca932 981 [(match_operand:SI 1 "register_operand" "t,l, r")
9304f876
CJW		 982 (const_int 0)])
983 (label_ref (match_operand 2 "" ""))
984 (pc)))]
985 ""
986{
6e9ca932 987 return nds32_output_cbranchsi4_equality_zero (insn, operands);
9304f876
CJW		 988}
989 [(set_attr "type" "branch")
6e9ca932
CJW		 990 (set_attr_alternative "enabled"
991 [
992 ;; Alternative 0
993 (if_then_else (match_test "TARGET_16_BIT")
994 (const_string "yes")
995 (const_string "no"))
996 ;; Alternative 1
997 (if_then_else (match_test "TARGET_16_BIT")
998 (const_string "yes")
999 (const_string "no"))
1000 ;; Alternative 2
1001 (const_string "yes")
1002 ])
9304f876
CJW		 1003 (set_attr_alternative "length"
1004 [
1005 ;; Alternative 0
6e9ca932
CJW		 1006 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1007 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
1008 (le (minus (match_dup 2) (pc)) (const_int 250)))
9304f876 1009 (if_then_else (match_test "TARGET_16_BIT")
6e9ca932
CJW		 1010 (const_int 2)
1011 (const_int 4))
1012 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
1013 (le (minus (match_dup 2) (pc)) (const_int 65500)))
1014 (const_int 4)
1015 (if_then_else (match_test "TARGET_16_BIT")
1016 (const_int 8)
1017 (const_int 10))))
1018 (const_int 10))
9304f876 1019 ;; Alternative 1
6e9ca932
CJW		 1020 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1021 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
1022 (le (minus (match_dup 2) (pc)) (const_int 250)))
1023 (if_then_else (match_test "TARGET_16_BIT")
1024 (const_int 2)
1025 (const_int 4))
1026 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
1027 (le (minus (match_dup 2) (pc)) (const_int 65500)))
1028 (const_int 4)
1029 (if_then_else (match_test "TARGET_16_BIT")
1030 (const_int 8)
1031 (const_int 10))))
1032 (const_int 10))
1033 ;; Alternative 2
1034 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
9304f876
CJW		 1035 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
1036 (le (minus (match_dup 2) (pc)) (const_int 65500)))
1037 (const_int 4)
6e9ca932
CJW		 1038 (const_int 10))
1039 (const_int 10))
9304f876
CJW		 1040 ])])
1041
1042
1043;; This pattern is dedicated to V2 ISA,
1044;; because V2 DOES NOT HAVE beqc/bnec instruction.
6e9ca932 1045(define_insn "cbranchsi4_equality_reg"
9304f876
CJW		 1046 [(set (pc)
1047 (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
6e9ca932
CJW		 1048 [(match_operand:SI 1 "register_operand" "v, r")
1049 (match_operand:SI 2 "register_operand" "l, r")])
9304f876
CJW		 1050 (label_ref (match_operand 3 "" ""))
1051 (pc)))]
1052 "TARGET_ISA_V2"
1053{
6e9ca932 1054 return nds32_output_cbranchsi4_equality_reg (insn, operands);
9304f876
CJW		 1055}
1056 [(set_attr "type" "branch")
6e9ca932
CJW		 1057 (set_attr_alternative "enabled"
1058 [
1059 ;; Alternative 0
1060 (if_then_else (match_test "TARGET_16_BIT")
1061 (const_string "yes")
1062 (const_string "no"))
1063 ;; Alternative 1
1064 (const_string "yes")
1065 ])
1066 (set_attr_alternative "length"
1067 [
1068 ;; Alternative 0
1069 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1070 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
1071 (le (minus (match_dup 3) (pc)) (const_int 250)))
1072 (const_int 2)
1073 (if_then_else (and (ge (minus (match_dup 3) (pc))
1074 (const_int -16350))
1075 (le (minus (match_dup 3) (pc))
1076 (const_int 16350)))
1077 (const_int 4)
1078 (const_int 8)))
1079 (const_int 8))
1080 ;; Alternative 1
1081 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1082 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
1083 (le (minus (match_dup 3) (pc)) (const_int 16350)))
1084 (const_int 4)
1085 (const_int 10))
1086 (const_int 10))
1087 ])])
9304f876
CJW		 1088
1089
1090;; This pattern is dedicated to V3/V3M,
1091;; because V3/V3M DO HAVE beqc/bnec instruction.
6e9ca932 1092(define_insn "cbranchsi4_equality_reg_or_const_int"
9304f876
CJW		 1093 [(set (pc)
1094 (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
6e9ca932
CJW		 1095 [(match_operand:SI 1 "register_operand" "v, r, r")
1096 (match_operand:SI 2 "nds32_rimm11s_operand" "l, r, Is11")])
9304f876
CJW		 1097 (label_ref (match_operand 3 "" ""))
1098 (pc)))]
1099 "TARGET_ISA_V3 || TARGET_ISA_V3M"
1100{
6e9ca932 1101 return nds32_output_cbranchsi4_equality_reg_or_const_int (insn, operands);
9304f876
CJW		 1102}
1103 [(set_attr "type" "branch")
6e9ca932
CJW		 1104 (set_attr_alternative "enabled"
1105 [
1106 ;; Alternative 0
1107 (if_then_else (match_test "TARGET_16_BIT")
1108 (const_string "yes")
1109 (const_string "no"))
1110 ;; Alternative 1
1111 (const_string "yes")
1112 ;; Alternative 2
1113 (const_string "yes")
1114 ])
9304f876
CJW		 1115 (set_attr_alternative "length"
1116 [
1117 ;; Alternative 0
6e9ca932
CJW		 1118 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1119 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
1120 (le (minus (match_dup 3) (pc)) (const_int 250)))
1121 (const_int 2)
1122 (if_then_else (and (ge (minus (match_dup 3) (pc))
1123 (const_int -16350))
1124 (le (minus (match_dup 3) (pc))
1125 (const_int 16350)))
1126 (const_int 4)
1127 (const_int 8)))
1128 (const_int 8))
9304f876 1129 ;; Alternative 1
6e9ca932
CJW		 1130 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1131 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
1132 (le (minus (match_dup 3) (pc)) (const_int 16350)))
1133 (const_int 4)
1134 (const_int 10))
1135 (const_int 10))
1136 ;; Alternative 2
1137 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1138 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
1139 (le (minus (match_dup 3) (pc)) (const_int 250)))
1140 (const_int 4)
1141 (const_int 10))
1142 (const_int 10))
9304f876
CJW		 1143 ])])
1144
1145
1146(define_insn "*cbranchsi4_greater_less_zero"
1147 [(set (pc)
1148 (if_then_else (match_operator 0 "nds32_greater_less_comparison_operator"
1149 [(match_operand:SI 1 "register_operand" "r")
1150 (const_int 0)])
1151 (label_ref (match_operand 2 "" ""))
1152 (pc)))]
1153 ""
1154{
6e9ca932 1155 return nds32_output_cbranchsi4_greater_less_zero (insn, operands);
9304f876
CJW		 1156}
1157 [(set_attr "type" "branch")
1158 (set (attr "length")
6e9ca932
CJW		 1159 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1160 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
1161 (le (minus (match_dup 2) (pc)) (const_int 65500)))
1162 (const_int 4)
1163 (const_int 10))
1164 (const_int 10)))])
9304f876
CJW		 1165
1166
1167(define_expand "cstoresi4"
1168 [(set (match_operand:SI 0 "register_operand" "")
1169 (match_operator:SI 1 "comparison_operator"
1170 [(match_operand:SI 2 "register_operand" "")
1171 (match_operand:SI 3 "nonmemory_operand" "")]))]
1172 ""
1173{
6e9ca932
CJW		 1174 enum nds32_expand_result_type result = nds32_expand_cstore (operands);
1175 switch (result)
9304f876 1176 {
6e9ca932 1177 case EXPAND_DONE:
9304f876 1178 DONE;
6e9ca932
CJW		 1179 break;
1180 case EXPAND_FAIL:
1181 FAIL;
1182 break;
1183 case EXPAND_CREATE_TEMPLATE:
1184 break;
9304f876
CJW		 1185 default:
1186 gcc_unreachable ();
1187 }
1188})
1189
1190
6e9ca932
CJW		 1191(define_expand "slts_compare"
1192 [(set (match_operand:SI 0 "register_operand" "")
1193 (lt:SI (match_operand:SI 1 "general_operand" "")
1194 (match_operand:SI 2 "general_operand" "")))]
1195 ""
1196{
1197 if (!REG_P (operands[1]))
1198 operands[1] = force_reg (SImode, operands[1]);
1199
1200 if (!REG_P (operands[2]) && !satisfies_constraint_Is15 (operands[2]))
1201 operands[2] = force_reg (SImode, operands[2]);
1202})
1203
1204(define_insn "slts_compare_impl"
1205 [(set (match_operand:SI 0 "register_operand" "=t, t, r, r")
1206 (lt:SI (match_operand:SI 1 "register_operand" " d, d, r, r")
1207 (match_operand:SI 2 "nds32_rimm15s_operand" " r,Iu05, r, Is15")))]
9304f876
CJW		 1208 ""
1209 "@
1210 slts45\t%1, %2
1211 sltsi45\t%1, %2
1212 slts\t%0, %1, %2
1213 sltsi\t%0, %1, %2"
6e9ca932
CJW		 1214 [(set_attr "type" "alu, alu, alu, alu")
1215 (set_attr "length" " 2, 2, 4, 4")])
1216
1217(define_insn "slt_eq0"
1218 [(set (match_operand:SI 0 "register_operand" "=t, r")
1219 (eq:SI (match_operand:SI 1 "register_operand" " d, r")
1220 (const_int 0)))]
1221 ""
1222 "@
1223 slti45\t%1, 1
1224 slti\t%0, %1, 1"
1225 [(set_attr "type" "alu, alu")
1226 (set_attr "length" " 2, 4")])
1227
1228(define_expand "slt_compare"
1229 [(set (match_operand:SI 0 "register_operand" "")
1230 (ltu:SI (match_operand:SI 1 "general_operand" "")
1231 (match_operand:SI 2 "general_operand" "")))]
1232 ""
1233{
1234 if (!REG_P (operands[1]))
1235 operands[1] = force_reg (SImode, operands[1]);
1236
1237 if (!REG_P (operands[2]) && !satisfies_constraint_Is15 (operands[2]))
1238 operands[2] = force_reg (SImode, operands[2]);
1239})
9304f876 1240
6e9ca932
CJW		 1241(define_insn "slt_compare_impl"
1242 [(set (match_operand:SI 0 "register_operand" "=t, t, r, r")
1243 (ltu:SI (match_operand:SI 1 "register_operand" " d, d, r, r")
1244 (match_operand:SI 2 "nds32_rimm15s_operand" " r, Iu05, r, Is15")))]
9304f876
CJW		 1245 ""
1246 "@
1247 slt45\t%1, %2
1248 slti45\t%1, %2
1249 slt\t%0, %1, %2
1250 slti\t%0, %1, %2"
5ba6d585
KC		 1251 [(set_attr "type" "alu, alu, alu, alu")
1252 (set_attr "length" " 2, 2, 4, 4")])
9304f876
CJW		 1253
1254
1255;; ----------------------------------------------------------------------------
1256
1257;; Unconditional and other jump instructions.
1258
1259(define_insn "jump"
1260 [(set (pc) (label_ref (match_operand 0 "" "")))]
1261 ""
1262{
1263 /* This unconditional jump has two forms:
1264 32-bit instruction => j imm24s << 1
1265 16-bit instruction => j8 imm8s << 1
1266
1267 For 32-bit case,
1268 we assume it is always reachable.
1269 For 16-bit case,
1270 it must satisfy { 255 >= (label - pc) >= -256 } condition.
1271 However, since the $pc for nds32 is at the beginning of the instruction,
1272 we should leave some length space for current insn.
1273 So we use range -250 ~ 250. */
1274 switch (get_attr_length (insn))
1275 {
1276 case 2:
1277 return "j8\t%0";
1278 case 4:
1279 return "j\t%0";
1280 default:
1281 gcc_unreachable ();
1282 }
1283}
1284 [(set_attr "type" "branch")
30feb954 1285 (set_attr "enabled" "yes")
9304f876 1286 (set (attr "length")
6e9ca932
CJW		 1287 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1288 (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -250))
1289 (le (minus (match_dup 0) (pc)) (const_int 250)))
1290 (if_then_else (match_test "TARGET_16_BIT")
1291 (const_int 2)
1292 (const_int 4))
9304f876
CJW		 1293 (const_int 4))
1294 (const_int 4)))])
1295
1296(define_insn "indirect_jump"
1297 [(set (pc) (match_operand:SI 0 "register_operand" "r, r"))]
1298 ""
1299 "@
9c1a4c0f
CJW		 1300 jr5\t%0
1301 jr\t%0"
9304f876
CJW		 1302 [(set_attr "type" "branch,branch")
1303 (set_attr "length" " 2, 4")])
1304
1305;; Subroutine call instruction returning no value.
1306;; operands[0]: It should be a mem RTX whose address is
026c3cfd 1307;; the address of the function.
9304f876
CJW		 1308;; operands[1]: It is the number of bytes of arguments pushed as a const_int.
1309;; operands[2]: It is the number of registers used as operands.
1310
1311(define_expand "call"
1312 [(parallel [(call (match_operand 0 "memory_operand" "")
1313 (match_operand 1))
1f7b8028
CJW		 1314 (clobber (reg:SI LP_REGNUM))
1315 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1316 ""
1317 ""
1318)
1319
1320(define_insn "*call_register"
1321 [(parallel [(call (mem (match_operand:SI 0 "register_operand" "r, r"))
1322 (match_operand 1))
1f7b8028
CJW		 1323 (clobber (reg:SI LP_REGNUM))
1324 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1325 ""
1326 "@
1327 jral5\t%0
1328 jral\t%0"
1329 [(set_attr "type" "branch,branch")
1330 (set_attr "length" " 2, 4")])
1331
1332(define_insn "*call_immediate"
1333 [(parallel [(call (mem (match_operand:SI 0 "immediate_operand" "i"))
1334 (match_operand 1))
1f7b8028
CJW		 1335 (clobber (reg:SI LP_REGNUM))
1336 (clobber (reg:SI TA_REGNUM))])]
9304f876 1337 ""
1f7b8028
CJW		 1338{
1339 if (TARGET_CMODEL_LARGE)
1340 return "bal\t%0";
1341 else
1342 return "jal\t%0";
1343}
9304f876 1344 [(set_attr "type" "branch")
1f7b8028
CJW		 1345 (set (attr "length")
1346 (if_then_else (match_test "TARGET_CMODEL_LARGE")
1347 (const_int 12)
1348 (const_int 4)))])
9304f876
CJW		 1349
1350
1351;; Subroutine call instruction returning a value.
1352;; operands[0]: It is the hard regiser in which the value is returned.
1353;; The rest three operands are the same as the
1354;; three operands of the 'call' instruction.
1355;; (but with numbers increased by one)
1356
1357(define_expand "call_value"
1358 [(parallel [(set (match_operand 0)
1359 (call (match_operand 1 "memory_operand" "")
1360 (match_operand 2)))
1f7b8028
CJW		 1361 (clobber (reg:SI LP_REGNUM))
1362 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1363 ""
1364 ""
1365)
1366
1367(define_insn "*call_value_register"
1368 [(parallel [(set (match_operand 0)
1369 (call (mem (match_operand:SI 1 "register_operand" "r, r"))
1370 (match_operand 2)))
1f7b8028
CJW		 1371 (clobber (reg:SI LP_REGNUM))
1372 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1373 ""
1374 "@
1375 jral5\t%1
1376 jral\t%1"
1377 [(set_attr "type" "branch,branch")
1378 (set_attr "length" " 2, 4")])
1379
1380(define_insn "*call_value_immediate"
1381 [(parallel [(set (match_operand 0)
1382 (call (mem (match_operand:SI 1 "immediate_operand" "i"))
1383 (match_operand 2)))
1f7b8028
CJW		 1384 (clobber (reg:SI LP_REGNUM))
1385 (clobber (reg:SI TA_REGNUM))])]
9304f876 1386 ""
1f7b8028
CJW		 1387{
1388 if (TARGET_CMODEL_LARGE)
1389 return "bal\t%1";
1390 else
1391 return "jal\t%1";
1392}
9304f876 1393 [(set_attr "type" "branch")
1f7b8028
CJW		 1394 (set (attr "length")
1395 (if_then_else (match_test "TARGET_CMODEL_LARGE")
1396 (const_int 12)
1397 (const_int 4)))])
9304f876
CJW		 1398
1399
d6529176
CJW		 1400;; ----------------------------------------------------------------------------
1401
1402;; The sibcall patterns.
1403
1404;; sibcall
cc48a87f 1405;; sibcall_internal
d6529176
CJW		 1406
1407(define_expand "sibcall"
1408 [(parallel [(call (match_operand 0 "memory_operand" "")
1409 (const_int 0))
1410 (clobber (reg:SI TA_REGNUM))
1411 (return)])]
cc48a87f 1412 "")
d6529176 1413
cc48a87f
CJW		 1414(define_insn "sibcall_internal"
1415 [(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, i"))
d6529176
CJW		 1416 (match_operand 1))
1417 (clobber (reg:SI TA_REGNUM))
1418 (return)])]
1419 ""
1420{
cc48a87f
CJW		 1421 switch (which_alternative)
1422 {
1423 case 0:
1424 if (TARGET_16_BIT)
1425 return "jr5\t%0";
1426 else
1427 return "jr\t%0";
1428 case 1:
1429 if (nds32_long_call_p (operands[0]))
1430 return "b\t%0";
1431 else
1432 return "j\t%0";
1433 default:
1434 gcc_unreachable ();
1435 }
d6529176 1436}
30feb954 1437 [(set_attr "enabled" "yes")
cc48a87f
CJW		 1438 (set_attr "type" "branch")
1439 (set_attr_alternative "length"
1440 [
1441 ;; Alternative 0
1442 (if_then_else (match_test "TARGET_16_BIT")
1443 (const_int 2)
1444 (const_int 4))
1445 ;; Alternative 1
1446 (if_then_else (match_test "nds32_long_call_p (operands[0])")
1447 (const_int 12)
1448 (const_int 4))
1449 ])]
1450)
d6529176
CJW		 1451
1452;; sibcall_value
cc48a87f 1453;; sibcall_value_internal
d6529176
CJW		 1454;; sibcall_value_immediate
1455
1456(define_expand "sibcall_value"
1457 [(parallel [(set (match_operand 0)
1458 (call (match_operand 1 "memory_operand" "")
1459 (const_int 0)))
1460 (clobber (reg:SI TA_REGNUM))
1461 (return)])]
cc48a87f 1462 "")
d6529176 1463
cc48a87f 1464(define_insn "sibcall_value_internal"
d6529176 1465 [(parallel [(set (match_operand 0)
cc48a87f 1466 (call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, i"))
d6529176
CJW		 1467 (match_operand 2)))
1468 (clobber (reg:SI TA_REGNUM))
1469 (return)])]
1470 ""
1471{
cc48a87f
CJW		 1472 switch (which_alternative)
1473 {
1474 case 0:
1475 if (TARGET_16_BIT)
1476 return "jr5\t%1";
1477 else
1478 return "jr\t%1";
1479 case 1:
1480 if (nds32_long_call_p (operands[1]))
1481 return "b\t%1";
1482 else
1483 return "j\t%1";
1484 default:
1485 gcc_unreachable ();
1486 }
d6529176 1487}
30feb954 1488 [(set_attr "enabled" "yes")
cc48a87f
CJW		 1489 (set_attr "type" "branch")
1490 (set_attr_alternative "length"
1491 [
1492 ;; Alternative 0
1493 (if_then_else (match_test "TARGET_16_BIT")
1494 (const_int 2)
1495 (const_int 4))
1496 ;; Alternative 1
1497 (if_then_else (match_test "nds32_long_call_p (operands[1])")
1498 (const_int 12)
1499 (const_int 4))
1500 ])]
1501)
d6529176
CJW		 1502
1503;; ----------------------------------------------------------------------------
1504
9304f876
CJW		 1505;; prologue and epilogue.
1506
1507(define_expand "prologue" [(const_int 0)]
1508 ""
1509{
2da1e7c0 1510 /* Note that only under V3/V3M ISA, we could use v3push prologue.
a6c7e777
MC		 1511 In addition, we need to check if v3push is indeed available. */
1512 if (NDS32_V3PUSH_AVAILABLE_P)
9304f876
CJW		 1513 nds32_expand_prologue_v3push ();
1514 else
1515 nds32_expand_prologue ();
1516 DONE;
1517})
1518
1519(define_expand "epilogue" [(const_int 0)]
1520 ""
1521{
2da1e7c0 1522 /* Note that only under V3/V3M ISA, we could use v3pop epilogue.
a6c7e777
MC		 1523 In addition, we need to check if v3push is indeed available. */
1524 if (NDS32_V3PUSH_AVAILABLE_P)
d6529176
CJW		 1525 nds32_expand_epilogue_v3pop (false);
1526 else
1527 nds32_expand_epilogue (false);
1528 DONE;
1529})
1530
1531(define_expand "sibcall_epilogue" [(const_int 0)]
1532 ""
1533{
1534 /* Pass true to indicate that this is sibcall epilogue and
1535 exit from a function without the final branch back to the
1536 calling function. */
a6c7e777 1537 nds32_expand_epilogue (true);
d6529176 1538
9304f876
CJW		 1539 DONE;
1540})
1541
1542
1543;; nop instruction.
1544
1545(define_insn "nop"
1546 [(const_int 0)]
1547 ""
1548{
1549 if (TARGET_16_BIT)
1550 return "nop16";
1551 else
1552 return "nop";
1553}
1554 [(set_attr "type" "misc")
30feb954 1555 (set_attr "enabled" "yes")
9304f876
CJW		 1556 (set (attr "length")
1557 (if_then_else (match_test "TARGET_16_BIT")
1558 (const_int 2)
1559 (const_int 4)))])
1560
1561
1562;; ----------------------------------------------------------------------------
1563;; Stack push/pop operations
1564;; ----------------------------------------------------------------------------
1565
1566;; The pattern for stack push.
1567;; Both stack_push_multiple and stack_v3push use the following pattern.
1568;; So we need to use TARGET_V3PUSH to determine the instruction length.
1569(define_insn "*stack_push"
1570 [(match_parallel 0 "nds32_stack_push_operation"
1571 [(set (mem:SI (plus:SI (reg:SI SP_REGNUM)
1572 (match_operand:SI 1 "const_int_operand" "")))
1573 (match_operand:SI 2 "register_operand" ""))
1574 ])]
1575 ""
1576{
6f3d3f9c 1577 return nds32_output_stack_push (operands[0]);
9304f876 1578}
264159d2
KC		 1579 [(set_attr "type" "store_multiple")
1580 (set_attr "combo" "12")
30feb954 1581 (set_attr "enabled" "yes")
9304f876 1582 (set (attr "length")
6f3d3f9c
CJW		 1583 (if_then_else (match_test "TARGET_V3PUSH
1584 && !nds32_isr_function_p (cfun->decl)
1585 && (cfun->machine->va_args_size == 0)")
9304f876
CJW		 1586 (const_int 2)
1587 (const_int 4)))])
1588
1589
1590;; The pattern for stack pop.
1591;; Both stack_pop_multiple and stack_v3pop use the following pattern.
1592;; So we need to use TARGET_V3PUSH to determine the instruction length.
1593(define_insn "*stack_pop"
1594 [(match_parallel 0 "nds32_stack_pop_operation"
1595 [(set (match_operand:SI 1 "register_operand" "")
1596 (mem:SI (reg:SI SP_REGNUM)))
1597 ])]
1598 ""
1599{
6f3d3f9c 1600 return nds32_output_stack_pop (operands[0]);
9304f876 1601}
264159d2
KC		 1602 [(set_attr "type" "load_multiple")
1603 (set_attr "combo" "12")
30feb954 1604 (set_attr "enabled" "yes")
9304f876 1605 (set (attr "length")
6f3d3f9c
CJW		 1606 (if_then_else (match_test "TARGET_V3PUSH
1607 && !nds32_isr_function_p (cfun->decl)
1608 && (cfun->machine->va_args_size == 0)")
9304f876
CJW		 1609 (const_int 2)
1610 (const_int 4)))])
1611
1612
1613;; ----------------------------------------------------------------------------
03390cda 1614;; Return operation patterns
9304f876
CJW		 1615;; ----------------------------------------------------------------------------
1616
03390cda
CJW		 1617;; Use this pattern to expand a return instruction
1618;; with simple_return rtx if no epilogue is required.
1619(define_expand "return"
1620 [(simple_return)]
1621 "nds32_can_use_return_insn ()"
1622 ""
1623)
9304f876 1624
03390cda
CJW		 1625;; This pattern is expanded only by the shrink-wrapping optimization
1626;; on paths where the function prologue has not been executed.
1627(define_expand "simple_return"
1628 [(simple_return)]
1629 ""
1630 ""
1631)
1632
1633(define_insn "return_internal"
1634 [(simple_return)]
9304f876
CJW		 1635 ""
1636{
1637 if (TARGET_16_BIT)
1638 return "ret5";
1639 else
1640 return "ret";
1641}
03390cda 1642 [(set_attr "type" "branch")
30feb954 1643 (set_attr "enabled" "yes")
9304f876
CJW		 1644 (set (attr "length")
1645 (if_then_else (match_test "TARGET_16_BIT")
1646 (const_int 2)
1647 (const_int 4)))])
1648
1649
1650;; ----------------------------------------------------------------------------
1651;; Jump Table patterns
1652;; ----------------------------------------------------------------------------
1653;; Need to implement ASM_OUTPUT_ADDR_VEC_ELT (for normal jump table)
1654;; or ASM_OUTPUT_ADDR_DIFF_ELT (for pc relative jump table) as well.
1655;;
1656;; operands[0]: The index to dispatch on.
1657;; operands[1]: The lower bound for indices in the table.
1658;; operands[2]: The total range of indices int the table.
1659;; i.e. The largest index minus the smallest one.
1660;; operands[3]: A label that precedes the table itself.
1661;; operands[4]: A label to jump to if the index has a value outside the bounds.
1662;;
1663;; We need to create following sequences for jump table code generation:
1664;; A) k <-- (plus (operands[0]) (-operands[1]))
1665;; B) if (gtu k operands[2]) then goto operands[4]
1666;; C) t <-- operands[3]
1667;; D) z <-- (mem (plus (k << 0 or 1 or 2) t))
1668;; E) z <-- t + z (NOTE: This is only required for pc relative jump table.)
1669;; F) jump to target with register t or z
1670;;
1671;; The steps C, D, E, and F are performed by casesi_internal pattern.
1672(define_expand "casesi"
1673 [(match_operand:SI 0 "register_operand" "r") ; index to jump on
1674 (match_operand:SI 1 "immediate_operand" "i") ; lower bound
1675 (match_operand:SI 2 "immediate_operand" "i") ; total range
1676 (match_operand:SI 3 "" "") ; table label
1677 (match_operand:SI 4 "" "")] ; Out of range label
1678 ""
1679{
1680 rtx add_tmp;
1681 rtx reg, test;
1682
1683 /* Step A: "k <-- (plus (operands[0]) (-operands[1]))". */
1684 if (operands[1] != const0_rtx)
1685 {
1686 reg = gen_reg_rtx (SImode);
1687 add_tmp = gen_int_mode (-INTVAL (operands[1]), SImode);
1688
1689 /* If the integer value is not in the range of imm15s,
8a498f99
CJW		 1690 we need to force register first because our addsi3 pattern
1691 only accept nds32_rimm15s_operand predicate. */
9304f876
CJW		 1692 add_tmp = force_reg (SImode, add_tmp);
1693
1694 emit_insn (gen_addsi3 (reg, operands[0], add_tmp));
1695 operands[0] = reg;
1696 }
1697
1698 /* Step B: "if (gtu k operands[2]) then goto operands[4]". */
1699 test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
1700 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2],
1701 operands[4]));
1702
9759608c
SB		 1703 /* Step C, D, E, and F, using another temporary register. */
1704 rtx tmp = gen_reg_rtx (SImode);
1705 emit_jump_insn (gen_casesi_internal (operands[0], operands[3], tmp));
9304f876
CJW		 1706 DONE;
1707})
1708
1709;; We are receiving operands from casesi pattern:
1710;;
1711;; operands[0]: The index that have been substracted with lower bound.
1712;; operands[1]: A label that precedes the table itself.
1713;; operands[2]: A temporary register to retrieve value in table.
1714;;
1715;; We need to perform steps C, D, E, and F:
1716;;
1717;; C) t <-- operands[1]
1718;; D) z <-- (mem (plus (operands[0] << m) t))
1719;; m is 2 for normal jump table.
1720;; m is 0, 1, or 2 for pc relative jump table based on diff size.
1721;; E) t <-- z + t (NOTE: This is only required for pc relative jump table.)
1722;; F) Jump to target with register t or z.
1723;;
1724;; The USE in this pattern is needed to tell flow analysis that this is
1725;; a CASESI insn. It has no other purpose.
1726(define_insn "casesi_internal"
1727 [(parallel [(set (pc)
1728 (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "r")
1729 (const_int 4))
1730 (label_ref (match_operand 1 "" "")))))
1731 (use (label_ref (match_dup 1)))
24f036fb 1732 (clobber (match_operand:SI 2 "register_operand" "=r"))
9304f876
CJW		 1733 (clobber (reg:SI TA_REGNUM))])]
1734 ""
1735{
1736 if (CASE_VECTOR_PC_RELATIVE)
1737 return nds32_output_casesi_pc_relative (operands);
1738 else
1739 return nds32_output_casesi (operands);
1740}
1741 [(set_attr "length" "20")
5ba6d585 1742 (set_attr "type" "branch")])
9304f876
CJW		 1743
1744;; ----------------------------------------------------------------------------
1745
1746;; Performance Extension
1747
1748(define_insn "clzsi2"
1749 [(set (match_operand:SI 0 "register_operand" "=r")
1750 (clz:SI (match_operand:SI 1 "register_operand" " r")))]
aa4b851c 1751 "TARGET_EXT_PERF"
9304f876
CJW		 1752 "clz\t%0, %1"
1753 [(set_attr "type" "alu")
1754 (set_attr "length" "4")])
1755
1756(define_insn "smaxsi3"
1757 [(set (match_operand:SI 0 "register_operand" "=r")
1758 (smax:SI (match_operand:SI 1 "register_operand" " r")
1759 (match_operand:SI 2 "register_operand" " r")))]
aa4b851c 1760 "TARGET_EXT_PERF"
9304f876
CJW		 1761 "max\t%0, %1, %2"
1762 [(set_attr "type" "alu")
1763 (set_attr "length" "4")])
1764
1765(define_insn "sminsi3"
1766 [(set (match_operand:SI 0 "register_operand" "=r")
1767 (smin:SI (match_operand:SI 1 "register_operand" " r")
1768 (match_operand:SI 2 "register_operand" " r")))]
aa4b851c 1769 "TARGET_EXT_PERF"
9304f876
CJW		 1770 "min\t%0, %1, %2"
1771 [(set_attr "type" "alu")
1772 (set_attr "length" "4")])
1773
1774(define_insn "*btst"
1775 [(set (match_operand:SI 0 "register_operand" "= r")
1776 (zero_extract:SI (match_operand:SI 1 "register_operand" " r")
1777 (const_int 1)
1778 (match_operand:SI 2 "immediate_operand" " Iu05")))]
aa4b851c 1779 "TARGET_EXT_PERF"
9304f876
CJW		 1780 "btst\t%0, %1, %2"
1781 [(set_attr "type" "alu")
1782 (set_attr "length" "4")])
1783
1784;; ----------------------------------------------------------------------------
aa2642ef
CJW		 1785
1786;; Pseudo NOPs
1787
c4d8d050
CJW		 1788(define_insn "relax_group"
1789 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_RELAX_GROUP)]
1790 ""
1791 ".relax_hint %0"
1792 [(set_attr "length" "0")]
1793)
1794
aa2642ef
CJW		 1795(define_insn "pop25return"
1796 [(return)
1797 (unspec_volatile:SI [(reg:SI LP_REGNUM)] UNSPEC_VOLATILE_POP25_RETURN)]
1798 ""
1799 "! return for pop 25"
1800 [(set_attr "length" "0")]
1801)
1802
1803;; ----------------------------------------------------------------------------
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