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[NDS32] Add new instruction attribute: feature.
[thirdparty/gcc.git] / gcc / config / nds32 / nds32.md
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9304f876 1;; Machine description of Andes NDS32 cpu for GNU compiler
85ec4feb 2;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
9304f876
CJW		 3;; Contributed by Andes Technology Corporation.
4;;
5;; This file is part of GCC.
6;;
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11;;
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15;; License for more details.
16;;
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
22
23;; Include predicates definition.
24(include "predicates.md")
25
26;; Include constraints definition.
27(include "constraints.md")
28
29;; Include iterators definition.
30(include "iterators.md")
31
32;; Include pipelines definition.
33(include "pipelines.md")
34
35
36;; Include constants definition.
37(include "constants.md")
38
39
40;; Include intrinsic functions definition.
41(include "nds32-intrinsic.md")
42
43;; Include block move for nds32 multiple load/store behavior.
44(include "nds32-multiple.md")
45
46;; Include DImode/DFmode operations.
47(include "nds32-doubleword.md")
48
49;; Include peephole patterns.
50(include "nds32-peephole2.md")
51
52
53;; Insn type, it is used to default other attribute values.
54(define_attr "type"
5ba6d585 55 "unknown,load,store,load_multiple,store_multiple,alu,alu_shift,mul,mac,div,branch,call,misc"
9304f876
CJW		 56 (const_string "unknown"))
57
0aa683b3
CJW		 58;; Insn sub-type
59(define_attr "subtype"
60 "simple,shift"
61 (const_string "simple"))
62
9304f876
CJW		 63;; Length, in bytes, default is 4-bytes.
64(define_attr "length" "" (const_int 4))
65
264159d2
KC		 66;; Indicate the amount of micro instructions.
67(define_attr "combo"
68 "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25"
69 (const_string "1"))
9304f876 70
9be6885b
KC		 71;; Insn in which feature set, it is used to enable/disable insn alternatives.
72;; v1 : Baseline Instructions
73;; v2 : Baseline Version 2 Instructions
74;; v3m : Baseline Version 3m Instructions
75;; v3 : Baseline Version 3 Instructions
76;; pe1 : Performance Extension Instructions
77;; pe2 : Performance Extension Version 2 Instructions
78;; se : String Extension instructions
79(define_attr "feature"
80 "v1,v2,v3m,v3,pe1,pe2,se"
81 (const_string "v1"))
82
9304f876
CJW		 83;; Enabled, which is used to enable/disable insn alternatives.
84;; Note that we use length and TARGET_16_BIT here as criteria.
9be6885b
KC		 85;; If the instruction pattern already check TARGET_16_BIT to determine
86;; the length by itself, its enabled attribute should be customized to
87;; avoid the conflict between length attribute and this default setting.
30feb954 88(define_attr "enabled" "no,yes"
9be6885b
KC		 89 (if_then_else
90 (and (eq_attr "length" "2")
91 (match_test "!TARGET_16_BIT"))
92 (const_string "no")
93 (cond [(eq_attr "feature" "v1") (const_string "yes")
94 (eq_attr "feature" "v2") (if_then_else (match_test "TARGET_ISA_V2 || TARGET_ISA_V3 || TARGET_ISA_V3M")
95 (const_string "yes")
96 (const_string "no"))
97 (eq_attr "feature" "v3") (if_then_else (match_test "TARGET_ISA_V3")
98 (const_string "yes")
99 (const_string "no"))
100 (eq_attr "feature" "v3m") (if_then_else (match_test "TARGET_ISA_V3 || TARGET_ISA_V3M")
101 (const_string "yes")
102 (const_string "no"))
103 (eq_attr "feature" "pe1") (if_then_else (match_test "TARGET_EXT_PERF")
104 (const_string "yes")
105 (const_string "no"))
106 (eq_attr "feature" "pe2") (if_then_else (match_test "TARGET_EXT_PERF2")
107 (const_string "yes")
108 (const_string "no"))
109 (eq_attr "feature" "se") (if_then_else (match_test "TARGET_EXT_STRING")
110 (const_string "yes")
111 (const_string "no"))]
112 (const_string "yes"))))
9304f876
CJW		 113
114
115;; ----------------------------------------------------------------------------
116
117
118;; Move instructions.
119
120;; For QImode and HImode, the immediate value can be fit in imm20s.
121;; So there is no need to split rtx for QI and HI patterns.
122
76dc9cb5
CJW		 123(define_expand "mov<mode>"
124 [(set (match_operand:QIHI 0 "general_operand" "")
125 (match_operand:QIHI 1 "general_operand" ""))]
9304f876
CJW		 126 ""
127{
128 /* Need to force register if mem <- !reg. */
129 if (MEM_P (operands[0]) && !REG_P (operands[1]))
76dc9cb5 130 operands[1] = force_reg (<MODE>mode, operands[1]);
9304f876 131
76dc9cb5
CJW		 132 if (MEM_P (operands[1]) && optimize > 0)
133 {
134 rtx reg = gen_reg_rtx (SImode);
135
136 emit_insn (gen_zero_extend<mode>si2 (reg, operands[1]));
137 operands[1] = gen_lowpart (<MODE>mode, reg);
138 }
9304f876
CJW		 139})
140
2cf09a99
KC		 141(define_expand "movmisalign<mode>"
142 [(set (match_operand:SIDI 0 "general_operand" "")
143 (match_operand:SIDI 1 "general_operand" ""))]
144 ""
145{
146 rtx addr;
147 if (MEM_P (operands[0]) && !REG_P (operands[1]))
148 operands[1] = force_reg (<MODE>mode, operands[1]);
149
150 if (MEM_P (operands[0]))
151 {
152 addr = force_reg (Pmode, XEXP (operands[0], 0));
153 emit_insn (gen_unaligned_store<mode> (addr, operands[1]));
154 }
155 else
156 {
157 addr = force_reg (Pmode, XEXP (operands[1], 0));
158 emit_insn (gen_unaligned_load<mode> (operands[0], addr));
159 }
160 DONE;
161})
76dc9cb5 162
9304f876
CJW		 163(define_expand "movsi"
164 [(set (match_operand:SI 0 "general_operand" "")
165 (match_operand:SI 1 "general_operand" ""))]
166 ""
167{
168 /* Need to force register if mem <- !reg. */
169 if (MEM_P (operands[0]) && !REG_P (operands[1]))
170 operands[1] = force_reg (SImode, operands[1]);
171
172 /* If operands[1] is a large constant and cannot be performed
173 by a single instruction, we need to split it. */
174 if (CONST_INT_P (operands[1])
175 && !satisfies_constraint_Is20 (operands[1])
176 && !satisfies_constraint_Ihig (operands[1]))
177 {
178 rtx high20_rtx;
179 HOST_WIDE_INT low12_int;
180 rtx tmp_rtx;
181
182 tmp_rtx = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
183
184 high20_rtx = gen_int_mode ((INTVAL (operands[1]) >> 12) << 12, SImode);
185 low12_int = INTVAL (operands[1]) & 0xfff;
186
187 emit_move_insn (tmp_rtx, high20_rtx);
188 emit_move_insn (operands[0], plus_constant (SImode,
189 tmp_rtx,
190 low12_int));
191 DONE;
192 }
193})
194
195(define_insn "*mov<mode>"
196 [(set (match_operand:QIHISI 0 "nonimmediate_operand" "=r, r, U45, U33, U37, U45, m, l, l, l, d, r, d, r, r, r")
197 (match_operand:QIHISI 1 "nds32_move_operand" " r, r, l, l, l, d, r, U45, U33, U37, U45, m, Ip05, Is05, Is20, Ihig"))]
b4350271
KC		 198 "register_operand(operands[0], <MODE>mode)
199 || register_operand(operands[1], <MODE>mode)"
9304f876
CJW		 200{
201 switch (which_alternative)
202 {
203 case 0:
204 return "mov55\t%0, %1";
205 case 1:
206 return "ori\t%0, %1, 0";
207 case 2:
208 case 3:
209 case 4:
210 case 5:
211 return nds32_output_16bit_store (operands, <byte>);
212 case 6:
213 return nds32_output_32bit_store (operands, <byte>);
214 case 7:
215 case 8:
216 case 9:
217 case 10:
218 return nds32_output_16bit_load (operands, <byte>);
219 case 11:
220 return nds32_output_32bit_load (operands, <byte>);
221 case 12:
222 return "movpi45\t%0, %1";
223 case 13:
224 return "movi55\t%0, %1";
225 case 14:
226 return "movi\t%0, %1";
227 case 15:
228 return "sethi\t%0, hi20(%1)";
229 default:
230 gcc_unreachable ();
231 }
232}
233 [(set_attr "type" "alu,alu,store,store,store,store,store,load,load,load,load,load,alu,alu,alu,alu")
234 (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2, 2, 4, 2, 2, 4, 4")])
235
236
237;; We use nds32_symbolic_operand to limit that only CONST/SYMBOL_REF/LABEL_REF
238;; are able to match such instruction template.
c4d8d050 239(define_insn "move_addr"
9304f876
CJW		 240 [(set (match_operand:SI 0 "register_operand" "=l, r")
241 (match_operand:SI 1 "nds32_symbolic_operand" " i, i"))]
242 ""
243 "la\t%0, %1"
5ba6d585 244 [(set_attr "type" "alu")
9304f876
CJW		 245 (set_attr "length" "8")])
246
247
c4d8d050 248(define_insn "sethi"
9304f876
CJW		 249 [(set (match_operand:SI 0 "register_operand" "=r")
250 (high:SI (match_operand:SI 1 "nds32_symbolic_operand" " i")))]
251 ""
252 "sethi\t%0, hi20(%1)"
253 [(set_attr "type" "alu")
254 (set_attr "length" "4")])
255
256
c4d8d050 257(define_insn "lo_sum"
9304f876
CJW		 258 [(set (match_operand:SI 0 "register_operand" "=r")
259 (lo_sum:SI (match_operand:SI 1 "register_operand" " r")
260 (match_operand:SI 2 "nds32_symbolic_operand" " i")))]
261 ""
262 "ori\t%0, %1, lo12(%2)"
263 [(set_attr "type" "alu")
264 (set_attr "length" "4")])
265
266
267;; ----------------------------------------------------------------------------
268
269;; Zero extension instructions.
270
271(define_insn "zero_extend<mode>si2"
272 [(set (match_operand:SI 0 "register_operand" "=l, r, l, *r")
273 (zero_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, U33, m")))]
274 ""
275{
276 switch (which_alternative)
277 {
278 case 0:
279 return "ze<size>33\t%0, %1";
280 case 1:
281 return "ze<size>\t%0, %1";
282 case 2:
283 return nds32_output_16bit_load (operands, <byte>);
284 case 3:
285 return nds32_output_32bit_load (operands, <byte>);
286
287 default:
288 gcc_unreachable ();
289 }
290}
291 [(set_attr "type" "alu,alu,load,load")
292 (set_attr "length" " 2, 4, 2, 4")])
293
294
295;; Sign extension instructions.
296
297(define_insn "extend<mode>si2"
298 [(set (match_operand:SI 0 "register_operand" "=l, r, r")
299 (sign_extend:SI (match_operand:QIHI 1 "nonimmediate_operand" " l, r, m")))]
300 ""
301{
302 switch (which_alternative)
303 {
304 case 0:
305 return "se<size>33\t%0, %1";
306 case 1:
307 return "se<size>\t%0, %1";
308 case 2:
309 return nds32_output_32bit_load_s (operands, <byte>);
310
311 default:
312 gcc_unreachable ();
313 }
314}
315 [(set_attr "type" "alu,alu,load")
316 (set_attr "length" " 2, 4, 4")])
317
318
319;; ----------------------------------------------------------------------------
320
321;; Arithmetic instructions.
322
323(define_insn "add<mode>3"
324 [(set (match_operand:QIHISI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r")
73f793e3 325 (plus:QIHISI (match_operand:QIHISI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r")
9304f876
CJW		 326 (match_operand:QIHISI 2 "nds32_rimm15s_operand" " In05, In03, Iu05, Iu03, r, l, Is10, Iu06, Is15, r")))]
327 ""
328{
329 switch (which_alternative)
330 {
331 case 0:
332 /* addi Rt4,Rt4,-x ==> subi45 Rt4,x
8a498f99 333 where 0 <= x <= 31 */
9304f876
CJW		 334 operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
335 return "subi45\t%0, %2";
336 case 1:
337 /* addi Rt3,Ra3,-x ==> subi333 Rt3,Ra3,x
8a498f99 338 where 0 <= x <= 7 */
9304f876
CJW		 339 operands[2] = gen_int_mode (-INTVAL (operands[2]), SImode);
340 return "subi333\t%0, %1, %2";
341 case 2:
342 return "addi45\t%0, %2";
343 case 3:
344 return "addi333\t%0, %1, %2";
345 case 4:
346 return "add45\t%0, %2";
347 case 5:
348 return "add333\t%0, %1, %2";
349 case 6:
350 return "addi10.sp\t%2";
351 case 7:
352 return "addri36.sp\t%0, %2";
353 case 8:
354 return "addi\t%0, %1, %2";
355 case 9:
356 return "add\t%0, %1, %2";
357
358 default:
359 gcc_unreachable ();
360 }
361}
9be6885b
KC		 362 [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
363 (set_attr "length" " 2, 2, 2, 2, 2, 2, 2, 2, 4, 4")
364 (set_attr "feature" " v1, v1, v1, v1, v1, v1, v2, v1, v1, v1")])
9304f876
CJW		 365
366(define_insn "sub<mode>3"
367 [(set (match_operand:QIHISI 0 "register_operand" "=d, l, r, r")
368 (minus:QIHISI (match_operand:QIHISI 1 "nds32_rimm15s_operand" " 0, l, Is15, r")
369 (match_operand:QIHISI 2 "register_operand" " r, l, r, r")))]
370 ""
371 "@
372 sub45\t%0, %2
373 sub333\t%0, %1, %2
374 subri\t%0, %2, %1
375 sub\t%0, %1, %2"
376 [(set_attr "type" "alu,alu,alu,alu")
377 (set_attr "length" " 2, 2, 4, 4")])
378
379
380;; GCC intends to simplify (plus (ashift ...) (reg))
381;; into (plus (mult ...) (reg)), so our matching pattern takes 'mult'
382;; and needs to ensure it is exact_log2 value.
383(define_insn "*add_slli"
384 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99 385 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
9304f876
CJW		 386 (match_operand:SI 2 "immediate_operand" " i"))
387 (match_operand:SI 3 "register_operand" " r")))]
388 "TARGET_ISA_V3
389 && (exact_log2 (INTVAL (operands[2])) != -1)
390 && (exact_log2 (INTVAL (operands[2])) <= 31)"
391{
392 /* Get floor_log2 of the immediate value
393 so that we can generate 'add_slli' instruction. */
394 operands[2] = GEN_INT (floor_log2 (INTVAL (operands[2])));
395
396 return "add_slli\t%0, %3, %1, %2";
397}
5ba6d585
KC		 398 [(set_attr "type" "alu_shift")
399 (set_attr "combo" "2")
400 (set_attr "length" "4")])
9304f876
CJW		 401
402(define_insn "*add_srli"
403 [(set (match_operand:SI 0 "register_operand" "= r")
404 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
405 (match_operand:SI 2 "immediate_operand" " Iu05"))
406 (match_operand:SI 3 "register_operand" " r")))]
407 "TARGET_ISA_V3"
408 "add_srli\t%0, %3, %1, %2"
5ba6d585
KC		 409 [(set_attr "type" "alu_shift")
410 (set_attr "combo" "2")
411 (set_attr "length" "4")])
9304f876
CJW		 412
413
414;; GCC intends to simplify (minus (reg) (ashift ...))
415;; into (minus (reg) (mult ...)), so our matching pattern takes 'mult'
416;; and needs to ensure it is exact_log2 value.
417(define_insn "*sub_slli"
418 [(set (match_operand:SI 0 "register_operand" "=r")
419 (minus:SI (match_operand:SI 1 "register_operand" " r")
420 (mult:SI (match_operand:SI 2 "register_operand" " r")
421 (match_operand:SI 3 "immediate_operand" " i"))))]
422 "TARGET_ISA_V3
423 && (exact_log2 (INTVAL (operands[3])) != -1)
424 && (exact_log2 (INTVAL (operands[3])) <= 31)"
425{
426 /* Get floor_log2 of the immediate value
427 so that we can generate 'sub_slli' instruction. */
428 operands[3] = GEN_INT (floor_log2 (INTVAL (operands[3])));
429
430 return "sub_slli\t%0, %1, %2, %3";
431}
5ba6d585
KC		 432 [(set_attr "type" "alu_shift")
433 (set_attr "combo" "2")
434 (set_attr "length" "4")])
9304f876
CJW		 435
436(define_insn "*sub_srli"
437 [(set (match_operand:SI 0 "register_operand" "= r")
438 (minus:SI (match_operand:SI 1 "register_operand" " r")
439 (lshiftrt:SI (match_operand:SI 2 "register_operand" " r")
440 (match_operand:SI 3 "immediate_operand" " Iu05"))))]
441 "TARGET_ISA_V3"
442 "sub_srli\t%0, %1, %2, %3"
5ba6d585
KC		 443 [(set_attr "type" "alu_shift")
444 (set_attr "combo" "2")
445 (set_attr "length" "4")])
9304f876
CJW		 446
447
448;; Multiplication instructions.
449
450(define_insn "mulsi3"
73f793e3
RS		 451 [(set (match_operand:SI 0 "register_operand" "=w, r")
452 (mult:SI (match_operand:SI 1 "register_operand" "%0, r")
453 (match_operand:SI 2 "register_operand" " w, r")))]
9304f876
CJW		 454 ""
455 "@
456 mul33\t%0, %2
457 mul\t%0, %1, %2"
5ba6d585 458 [(set_attr "type" "mul,mul")
9be6885b
KC		 459 (set_attr "length" " 2, 4")
460 (set_attr "feature" "v3m, v1")])
9304f876
CJW		 461
462(define_insn "mulsidi3"
463 [(set (match_operand:DI 0 "register_operand" "=r")
464 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
465 (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
466 "TARGET_ISA_V2 || TARGET_ISA_V3"
467 "mulsr64\t%0, %1, %2"
5ba6d585 468 [(set_attr "type" "mul")
9304f876
CJW		 469 (set_attr "length" "4")])
470
471(define_insn "umulsidi3"
472 [(set (match_operand:DI 0 "register_operand" "=r")
473 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " r"))
474 (zero_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
475 "TARGET_ISA_V2 || TARGET_ISA_V3"
476 "mulr64\t%0, %1, %2"
5ba6d585 477 [(set_attr "type" "mul")
9304f876
CJW		 478 (set_attr "length" "4")])
479
480
481;; Multiply-accumulate instructions.
482
483(define_insn "*maddr32_0"
484 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 485 (plus:SI (match_operand:SI 3 "register_operand" " 0")
486 (mult:SI (match_operand:SI 1 "register_operand" " r")
487 (match_operand:SI 2 "register_operand" " r"))))]
9304f876
CJW		 488 ""
489 "maddr32\t%0, %1, %2"
5ba6d585 490 [(set_attr "type" "mac")
9304f876
CJW		 491 (set_attr "length" "4")])
492
493(define_insn "*maddr32_1"
494 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 495 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
496 (match_operand:SI 2 "register_operand" " r"))
497 (match_operand:SI 3 "register_operand" " 0")))]
9304f876
CJW		 498 ""
499 "maddr32\t%0, %1, %2"
5ba6d585 500 [(set_attr "type" "mac")
9304f876
CJW		 501 (set_attr "length" "4")])
502
503(define_insn "*msubr32"
504 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 505 (minus:SI (match_operand:SI 3 "register_operand" " 0")
506 (mult:SI (match_operand:SI 1 "register_operand" " r")
507 (match_operand:SI 2 "register_operand" " r"))))]
9304f876
CJW		 508 ""
509 "msubr32\t%0, %1, %2"
5ba6d585 510 [(set_attr "type" "mac")
9304f876
CJW		 511 (set_attr "length" "4")])
512
513
514;; Div Instructions.
515
516(define_insn "divmodsi4"
517 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 518 (div:SI (match_operand:SI 1 "register_operand" " r")
519 (match_operand:SI 2 "register_operand" " r")))
9304f876 520 (set (match_operand:SI 3 "register_operand" "=r")
8a498f99 521 (mod:SI (match_dup 1) (match_dup 2)))]
9304f876
CJW		 522 ""
523 "divsr\t%0, %3, %1, %2"
5ba6d585 524 [(set_attr "type" "div")
9304f876
CJW		 525 (set_attr "length" "4")])
526
527(define_insn "udivmodsi4"
528 [(set (match_operand:SI 0 "register_operand" "=r")
8a498f99
CJW		 529 (udiv:SI (match_operand:SI 1 "register_operand" " r")
530 (match_operand:SI 2 "register_operand" " r")))
9304f876 531 (set (match_operand:SI 3 "register_operand" "=r")
8a498f99 532 (umod:SI (match_dup 1) (match_dup 2)))]
9304f876
CJW		 533 ""
534 "divr\t%0, %3, %1, %2"
5ba6d585 535 [(set_attr "type" "div")
9304f876
CJW		 536 (set_attr "length" "4")])
537
538
539;; ----------------------------------------------------------------------------
540
541;; Boolean instructions.
542;; Note: We define the DImode versions in nds32-doubleword.md.
543
544;; ----------------------------------------------------------------------------
545;; 'AND' operation
546;; ----------------------------------------------------------------------------
547
548(define_insn "bitc"
549 [(set (match_operand:SI 0 "register_operand" "=r")
550 (and:SI (not:SI (match_operand:SI 1 "register_operand" " r"))
551 (match_operand:SI 2 "register_operand" " r")))]
552 "TARGET_ISA_V3"
553 "bitc\t%0, %2, %1"
554 [(set_attr "type" "alu")
555 (set_attr "length" "4")]
556)
557
558(define_insn "andsi3"
73f793e3
RS		 559 [(set (match_operand:SI 0 "register_operand" "=w, r, l, l, l, l, l, l, r, r, r, r, r")
560 (and:SI (match_operand:SI 1 "register_operand" "%0, r, l, l, l, l, 0, 0, r, r, r, r, r")
561 (match_operand:SI 2 "general_operand" " w, r, Izeb, Izeh, Ixls, Ix11, Ibms, Ifex, Izeb, Izeh, Iu15, Ii15, Ic15")))]
9304f876
CJW		 562 ""
563{
564 HOST_WIDE_INT mask = INTVAL (operands[2]);
565 int zero_position;
566
567 /* 16-bit andi instructions:
568 andi Rt3,Ra3,0xff -> zeb33 Rt3,Ra3
569 andi Rt3,Ra3,0xffff -> zeh33 Rt3,Ra3
570 andi Rt3,Ra3,0x01 -> xlsb33 Rt3,Ra3
571 andi Rt3,Ra3,0x7ff -> x11b33 Rt3,Ra3
572 andi Rt3,Rt3,2^imm3u -> bmski33 Rt3,imm3u
573 andi Rt3,Rt3,(2^(imm3u+1))-1 -> fexti33 Rt3,imm3u. */
574
575 switch (which_alternative)
576 {
577 case 0:
578 return "and33\t%0, %2";
579 case 1:
580 return "and\t%0, %1, %2";
581 case 2:
582 return "zeb33\t%0, %1";
583 case 3:
584 return "zeh33\t%0, %1";
585 case 4:
586 return "xlsb33\t%0, %1";
587 case 5:
588 return "x11b33\t%0, %1";
589 case 6:
590 operands[2] = GEN_INT (floor_log2 (mask));
591 return "bmski33\t%0, %2";
592 case 7:
593 operands[2] = GEN_INT (floor_log2 (mask + 1) - 1);
594 return "fexti33\t%0, %2";
595 case 8:
596 return "zeb\t%0, %1";
597 case 9:
598 return "zeh\t%0, %1";
599 case 10:
600 return "andi\t%0, %1, %2";
601 case 11:
602 operands[2] = GEN_INT (~mask);
603 return "bitci\t%0, %1, %2";
604 case 12:
605 /* If we reach this alternative,
606 it must pass the nds32_can_use_bclr_p() test,
607 so that we can guarantee there is only one 0-bit
608 within the immediate value. */
609 for (zero_position = 31; zero_position >= 0; zero_position--)
610 {
611 if ((INTVAL (operands[2]) & (1 << zero_position)) == 0)
612 {
613 /* Found the 0-bit position. */
614 operands[2] = GEN_INT (zero_position);
615 break;
616 }
617 }
618 return "bclr\t%0, %1, %2";
619
620 default:
621 gcc_unreachable ();
622 }
623}
9be6885b
KC		 624 [(set_attr "type" "alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu,alu")
625 (set_attr "length" " 2, 4, 2, 2, 2, 2, 2, 2, 4, 4, 4, 4, 4")
626 (set_attr "feature" "v3m, v1, v1, v1, v1, v1,v3m,v3m, v1, v1, v1, v3,pe1")])
9304f876
CJW		 627
628(define_insn "*and_slli"
629 [(set (match_operand:SI 0 "register_operand" "= r")
630 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
631 (match_operand:SI 2 "immediate_operand" " Iu05"))
632 (match_operand:SI 3 "register_operand" " r")))]
633 "TARGET_ISA_V3"
634 "and_slli\t%0, %3, %1, %2"
5ba6d585
KC		 635 [(set_attr "type" "alu_shift")
636 (set_attr "length" "4")])
9304f876
CJW		 637
638(define_insn "*and_srli"
639 [(set (match_operand:SI 0 "register_operand" "= r")
640 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
641 (match_operand:SI 2 "immediate_operand" " Iu05"))
642 (match_operand:SI 3 "register_operand" " r")))]
643 "TARGET_ISA_V3"
644 "and_srli\t%0, %3, %1, %2"
5ba6d585
KC		 645 [(set_attr "type" "alu_shift")
646 (set_attr "length" "4")])
9304f876
CJW		 647
648
649;; ----------------------------------------------------------------------------
650;; 'OR' operation
651;; ----------------------------------------------------------------------------
652
653;; For V3/V3M ISA, we have 'or33' instruction.
654;; So we can identify 'or Rt3,Rt3,Ra3' case and set its length to be 2.
655(define_insn "iorsi3"
73f793e3
RS		 656 [(set (match_operand:SI 0 "register_operand" "=w, r, r, r")
657 (ior:SI (match_operand:SI 1 "register_operand" "%0, r, r, r")
658 (match_operand:SI 2 "general_operand" " w, r, Iu15, Ie15")))]
9304f876
CJW		 659 ""
660{
661 int one_position;
662
663 switch (which_alternative)
664 {
665 case 0:
666 return "or33\t%0, %2";
667 case 1:
668 return "or\t%0, %1, %2";
669 case 2:
670 return "ori\t%0, %1, %2";
671 case 3:
672 /* If we reach this alternative,
673 it must pass the nds32_can_use_bset_p() test,
674 so that we can guarantee there is only one 1-bit
675 within the immediate value. */
676 /* Use exact_log2() to search the 1-bit position. */
677 one_position = exact_log2 (INTVAL (operands[2]));
678 operands[2] = GEN_INT (one_position);
679 return "bset\t%0, %1, %2";
680
681 default:
682 gcc_unreachable ();
683 }
684}
685 [(set_attr "type" "alu,alu,alu,alu")
686 (set_attr "length" " 2, 4, 4, 4")])
687
688(define_insn "*or_slli"
689 [(set (match_operand:SI 0 "register_operand" "= r")
690 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
691 (match_operand:SI 2 "immediate_operand" " Iu05"))
692 (match_operand:SI 3 "register_operand" " r")))]
693 "TARGET_ISA_V3"
694 "or_slli\t%0, %3, %1, %2"
5ba6d585
KC		 695 [(set_attr "type" "alu_shift")
696 (set_attr "length" "4")])
9304f876
CJW		 697
698(define_insn "*or_srli"
699 [(set (match_operand:SI 0 "register_operand" "= r")
700 (ior:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
701 (match_operand:SI 2 "immediate_operand" " Iu05"))
702 (match_operand:SI 3 "register_operand" " r")))]
703 "TARGET_ISA_V3"
704 "or_srli\t%0, %3, %1, %2"
5ba6d585
KC		 705 [(set_attr "type" "alu_shift")
706 (set_attr "length" "4")])
9304f876
CJW		 707
708
709;; ----------------------------------------------------------------------------
710;; 'XOR' operation
711;; ----------------------------------------------------------------------------
712
713;; For V3/V3M ISA, we have 'xor33' instruction.
714;; So we can identify 'xor Rt3,Rt3,Ra3' case and set its length to be 2.
715(define_insn "xorsi3"
73f793e3
RS		 716 [(set (match_operand:SI 0 "register_operand" "=w, r, r, r")
717 (xor:SI (match_operand:SI 1 "register_operand" "%0, r, r, r")
718 (match_operand:SI 2 "general_operand" " w, r, Iu15, It15")))]
9304f876
CJW		 719 ""
720{
721 int one_position;
722
723 switch (which_alternative)
724 {
725 case 0:
726 return "xor33\t%0, %2";
727 case 1:
728 return "xor\t%0, %1, %2";
729 case 2:
730 return "xori\t%0, %1, %2";
731 case 3:
732 /* If we reach this alternative,
733 it must pass the nds32_can_use_btgl_p() test,
734 so that we can guarantee there is only one 1-bit
735 within the immediate value. */
736 /* Use exact_log2() to search the 1-bit position. */
737 one_position = exact_log2 (INTVAL (operands[2]));
738 operands[2] = GEN_INT (one_position);
739 return "btgl\t%0, %1, %2";
740
741 default:
742 gcc_unreachable ();
743 }
744}
9be6885b
KC		 745 [(set_attr "type" "alu,alu,alu,alu")
746 (set_attr "length" " 2, 4, 4, 4")
747 (set_attr "feature" "v3m, v1, v1,pe1")])
9304f876
CJW		 748
749(define_insn "*xor_slli"
750 [(set (match_operand:SI 0 "register_operand" "= r")
751 (xor:SI (ashift:SI (match_operand:SI 1 "register_operand" " r")
752 (match_operand:SI 2 "immediate_operand" " Iu05"))
753 (match_operand:SI 3 "register_operand" " r")))]
754 "TARGET_ISA_V3"
755 "xor_slli\t%0, %3, %1, %2"
5ba6d585
KC		 756 [(set_attr "type" "alu_shift")
757 (set_attr "length" "4")])
9304f876
CJW		 758
759(define_insn "*xor_srli"
760 [(set (match_operand:SI 0 "register_operand" "= r")
761 (xor:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" " r")
762 (match_operand:SI 2 "immediate_operand" " Iu05"))
763 (match_operand:SI 3 "register_operand" " r")))]
764 "TARGET_ISA_V3"
765 "xor_srli\t%0, %3, %1, %2"
5ba6d585
KC		 766 [(set_attr "type" "alu_shift")
767 (set_attr "length" "4")])
9304f876
CJW		 768
769;; Rotate Right Instructions.
770
771(define_insn "rotrsi3"
772 [(set (match_operand:SI 0 "register_operand" "= r, r")
773 (rotatert:SI (match_operand:SI 1 "register_operand" " r, r")
774 (match_operand:SI 2 "nonmemory_operand" " Iu05, r")))]
775 ""
776 "@
777 rotri\t%0, %1, %2
778 rotr\t%0, %1, %2"
5ba6d585 779 [(set_attr "type" " alu, alu")
0aa683b3 780 (set_attr "subtype" "shift,shift")
5ba6d585 781 (set_attr "length" " 4, 4")])
9304f876
CJW		 782
783
784;; ----------------------------------------------------------------------------
785;; 'NEG' operation
786;; ----------------------------------------------------------------------------
787
788;; For V3/V3M ISA, we have 'neg33' instruction.
789;; So we can identify 'xor Rt3,Ra3' case and set its length to be 2.
790;; And for V2 ISA, there is NO 'neg33' instruction.
791;; The only option is to use 'subri A,B,0' (its semantic is 'A = 0 - B').
792(define_insn "negsi2"
793 [(set (match_operand:SI 0 "register_operand" "=w, r")
794 (neg:SI (match_operand:SI 1 "register_operand" " w, r")))]
795 ""
796 "@
797 neg33\t%0, %1
798 subri\t%0, %1, 0"
799 [(set_attr "type" "alu,alu")
800 (set_attr "length" " 2, 4")])
801
802
803;; ----------------------------------------------------------------------------
804;; 'ONE_COMPLIMENT' operation
805;; ----------------------------------------------------------------------------
806
807;; For V3/V3M ISA, we have 'not33' instruction.
808;; So we can identify 'not Rt3,Ra3' case and set its length to be 2.
809(define_insn "one_cmplsi2"
810 [(set (match_operand:SI 0 "register_operand" "=w, r")
811 (not:SI (match_operand:SI 1 "register_operand" " w, r")))]
812 ""
813 "@
814 not33\t%0, %1
815 nor\t%0, %1, %1"
9be6885b
KC		 816 [(set_attr "type" "alu,alu")
817 (set_attr "length" " 2, 4")
818 (set_attr "feature" "v3m, v1")])
9304f876
CJW		 819
820
821;; ----------------------------------------------------------------------------
822
823;; Shift instructions.
824
825(define_insn "ashlsi3"
826 [(set (match_operand:SI 0 "register_operand" "= l, r, r")
827 (ashift:SI (match_operand:SI 1 "register_operand" " l, r, r")
828 (match_operand:SI 2 "nonmemory_operand" " Iu03, Iu05, r")))]
829 ""
830 "@
831 slli333\t%0, %1, %2
832 slli\t%0, %1, %2
833 sll\t%0, %1, %2"
0aa683b3
CJW		 834 [(set_attr "type" " alu, alu, alu")
835 (set_attr "subtype" "shift,shift,shift")
836 (set_attr "length" " 2, 4, 4")])
9304f876
CJW		 837(define_insn "ashrsi3"
838 [(set (match_operand:SI 0 "register_operand" "= d, r, r")
839 (ashiftrt:SI (match_operand:SI 1 "register_operand" " 0, r, r")
840 (match_operand:SI 2 "nonmemory_operand" " Iu05, Iu05, r")))]
841 ""
842 "@
843 srai45\t%0, %2
844 srai\t%0, %1, %2
845 sra\t%0, %1, %2"
0aa683b3
CJW		 846 [(set_attr "type" " alu, alu, alu")
847 (set_attr "subtype" "shift,shift,shift")
848 (set_attr "length" " 2, 4, 4")])
9304f876
CJW		 849
850(define_insn "lshrsi3"
851 [(set (match_operand:SI 0 "register_operand" "= d, r, r")
852 (lshiftrt:SI (match_operand:SI 1 "register_operand" " 0, r, r")
853 (match_operand:SI 2 "nonmemory_operand" " Iu05, Iu05, r")))]
854 ""
855 "@
856 srli45\t%0, %2
857 srli\t%0, %1, %2
858 srl\t%0, %1, %2"
0aa683b3
CJW		 859 [(set_attr "type" " alu, alu, alu")
860 (set_attr "subtype" "shift,shift,shift")
861 (set_attr "length" " 2, 4, 4")])
9304f876
CJW		 862
863
864;; ----------------------------------------------------------------------------
865
866;; ----------------------------------------------------------------------------
867;; Conditional Move patterns
868;; ----------------------------------------------------------------------------
869
6e9ca932
CJW		 870(define_expand "mov<mode>cc"
871 [(set (match_operand:QIHISI 0 "register_operand" "")
872 (if_then_else:QIHISI (match_operand 1 "nds32_movecc_comparison_operator" "")
873 (match_operand:QIHISI 2 "register_operand" "")
874 (match_operand:QIHISI 3 "register_operand" "")))]
875 "TARGET_CMOV && !optimize_size"
9304f876 876{
6e9ca932
CJW		 877 enum nds32_expand_result_type result = nds32_expand_movcc (operands);
878 switch (result)
9304f876 879 {
6e9ca932
CJW		 880 case EXPAND_DONE:
881 DONE;
882 break;
883 case EXPAND_FAIL:
884 FAIL;
885 break;
886 case EXPAND_CREATE_TEMPLATE:
887 break;
888 default:
889 gcc_unreachable ();
9304f876 890 }
9304f876
CJW		 891})
892
6e9ca932
CJW		 893(define_insn "cmovz<mode>"
894 [(set (match_operand:QIHISI 0 "register_operand" "=r, r")
895 (if_then_else:QIHISI (eq (match_operand:SI 1 "register_operand" " r, r")
9304f876 896 (const_int 0))
6e9ca932
CJW		 897 (match_operand:QIHISI 2 "register_operand" " r, 0")
898 (match_operand:QIHISI 3 "register_operand" " 0, r")))]
9304f876
CJW		 899 "TARGET_CMOV"
900 "@
901 cmovz\t%0, %2, %1
902 cmovn\t%0, %3, %1"
5ba6d585 903 [(set_attr "type" "alu")
9304f876
CJW		 904 (set_attr "length" "4")])
905
6e9ca932
CJW		 906(define_insn "cmovn<mode>"
907 [(set (match_operand:QIHISI 0 "register_operand" "=r, r")
908 (if_then_else:QIHISI (ne (match_operand:SI 1 "register_operand" " r, r")
9304f876 909 (const_int 0))
6e9ca932
CJW		 910 (match_operand:QIHISI 2 "register_operand" " r, 0")
911 (match_operand:QIHISI 3 "register_operand" " 0, r")))]
9304f876
CJW		 912 "TARGET_CMOV"
913 "@
914 cmovn\t%0, %2, %1
915 cmovz\t%0, %3, %1"
5ba6d585 916 [(set_attr "type" "alu")
9304f876
CJW		 917 (set_attr "length" "4")])
918
6e9ca932
CJW		 919;; A hotfix to help RTL combiner to merge a cmovn insn and a zero_extend insn.
920;; It should be removed once after we change the expansion form of the cmovn.
921(define_insn "*cmovn_simplified_<mode>"
922 [(set (match_operand:QIHISI 0 "register_operand" "=r")
923 (if_then_else:QIHISI (match_operand:SI 1 "register_operand" "r")
924 (match_operand:QIHISI 2 "register_operand" "r")
925 (match_operand:QIHISI 3 "register_operand" "0")))]
926 ""
927 "cmovn\t%0, %2, %1"
928 [(set_attr "type" "alu")])
9304f876
CJW		 929
930;; ----------------------------------------------------------------------------
931;; Conditional Branch patterns
932;; ----------------------------------------------------------------------------
933
934(define_expand "cbranchsi4"
935 [(set (pc)
936 (if_then_else (match_operator 0 "comparison_operator"
937 [(match_operand:SI 1 "register_operand" "")
938 (match_operand:SI 2 "nds32_reg_constant_operand" "")])
939 (label_ref (match_operand 3 "" ""))
940 (pc)))]
941 ""
942{
6e9ca932
CJW		 943 enum nds32_expand_result_type result = nds32_expand_cbranch (operands);
944 switch (result)
9304f876 945 {
6e9ca932 946 case EXPAND_DONE:
9304f876 947 DONE;
6e9ca932
CJW		 948 break;
949 case EXPAND_FAIL:
9304f876 950 FAIL;
6e9ca932
CJW		 951 break;
952 case EXPAND_CREATE_TEMPLATE:
953 break;
954 default:
955 gcc_unreachable ();
9304f876 956 }
9304f876
CJW		 957})
958
959
6e9ca932 960(define_insn "cbranchsi4_equality_zero"
9304f876
CJW		 961 [(set (pc)
962 (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
6e9ca932 963 [(match_operand:SI 1 "register_operand" "t,l, r")
9304f876
CJW		 964 (const_int 0)])
965 (label_ref (match_operand 2 "" ""))
966 (pc)))]
967 ""
968{
6e9ca932 969 return nds32_output_cbranchsi4_equality_zero (insn, operands);
9304f876
CJW		 970}
971 [(set_attr "type" "branch")
6e9ca932
CJW		 972 (set_attr_alternative "enabled"
973 [
974 ;; Alternative 0
975 (if_then_else (match_test "TARGET_16_BIT")
976 (const_string "yes")
977 (const_string "no"))
978 ;; Alternative 1
979 (if_then_else (match_test "TARGET_16_BIT")
980 (const_string "yes")
981 (const_string "no"))
982 ;; Alternative 2
983 (const_string "yes")
984 ])
9304f876
CJW		 985 (set_attr_alternative "length"
986 [
987 ;; Alternative 0
6e9ca932
CJW		 988 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
989 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
990 (le (minus (match_dup 2) (pc)) (const_int 250)))
9304f876 991 (if_then_else (match_test "TARGET_16_BIT")
6e9ca932
CJW		 992 (const_int 2)
993 (const_int 4))
994 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
995 (le (minus (match_dup 2) (pc)) (const_int 65500)))
996 (const_int 4)
997 (if_then_else (match_test "TARGET_16_BIT")
998 (const_int 8)
999 (const_int 10))))
1000 (const_int 10))
9304f876 1001 ;; Alternative 1
6e9ca932
CJW		 1002 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1003 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -250))
1004 (le (minus (match_dup 2) (pc)) (const_int 250)))
1005 (if_then_else (match_test "TARGET_16_BIT")
1006 (const_int 2)
1007 (const_int 4))
1008 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
1009 (le (minus (match_dup 2) (pc)) (const_int 65500)))
1010 (const_int 4)
1011 (if_then_else (match_test "TARGET_16_BIT")
1012 (const_int 8)
1013 (const_int 10))))
1014 (const_int 10))
1015 ;; Alternative 2
1016 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
9304f876
CJW		 1017 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
1018 (le (minus (match_dup 2) (pc)) (const_int 65500)))
1019 (const_int 4)
6e9ca932
CJW		 1020 (const_int 10))
1021 (const_int 10))
9304f876
CJW		 1022 ])])
1023
1024
1025;; This pattern is dedicated to V2 ISA,
1026;; because V2 DOES NOT HAVE beqc/bnec instruction.
6e9ca932 1027(define_insn "cbranchsi4_equality_reg"
9304f876
CJW		 1028 [(set (pc)
1029 (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
6e9ca932
CJW		 1030 [(match_operand:SI 1 "register_operand" "v, r")
1031 (match_operand:SI 2 "register_operand" "l, r")])
9304f876
CJW		 1032 (label_ref (match_operand 3 "" ""))
1033 (pc)))]
1034 "TARGET_ISA_V2"
1035{
6e9ca932 1036 return nds32_output_cbranchsi4_equality_reg (insn, operands);
9304f876
CJW		 1037}
1038 [(set_attr "type" "branch")
6e9ca932
CJW		 1039 (set_attr_alternative "enabled"
1040 [
1041 ;; Alternative 0
1042 (if_then_else (match_test "TARGET_16_BIT")
1043 (const_string "yes")
1044 (const_string "no"))
1045 ;; Alternative 1
1046 (const_string "yes")
1047 ])
1048 (set_attr_alternative "length"
1049 [
1050 ;; Alternative 0
1051 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1052 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
1053 (le (minus (match_dup 3) (pc)) (const_int 250)))
1054 (const_int 2)
1055 (if_then_else (and (ge (minus (match_dup 3) (pc))
1056 (const_int -16350))
1057 (le (minus (match_dup 3) (pc))
1058 (const_int 16350)))
1059 (const_int 4)
1060 (const_int 8)))
1061 (const_int 8))
1062 ;; Alternative 1
1063 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1064 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
1065 (le (minus (match_dup 3) (pc)) (const_int 16350)))
1066 (const_int 4)
1067 (const_int 10))
1068 (const_int 10))
1069 ])])
9304f876
CJW		 1070
1071
1072;; This pattern is dedicated to V3/V3M,
1073;; because V3/V3M DO HAVE beqc/bnec instruction.
6e9ca932 1074(define_insn "cbranchsi4_equality_reg_or_const_int"
9304f876
CJW		 1075 [(set (pc)
1076 (if_then_else (match_operator 0 "nds32_equality_comparison_operator"
6e9ca932
CJW		 1077 [(match_operand:SI 1 "register_operand" "v, r, r")
1078 (match_operand:SI 2 "nds32_rimm11s_operand" "l, r, Is11")])
9304f876
CJW		 1079 (label_ref (match_operand 3 "" ""))
1080 (pc)))]
1081 "TARGET_ISA_V3 || TARGET_ISA_V3M"
1082{
6e9ca932 1083 return nds32_output_cbranchsi4_equality_reg_or_const_int (insn, operands);
9304f876
CJW		 1084}
1085 [(set_attr "type" "branch")
6e9ca932
CJW		 1086 (set_attr_alternative "enabled"
1087 [
1088 ;; Alternative 0
1089 (if_then_else (match_test "TARGET_16_BIT")
1090 (const_string "yes")
1091 (const_string "no"))
1092 ;; Alternative 1
1093 (const_string "yes")
1094 ;; Alternative 2
1095 (const_string "yes")
1096 ])
9304f876
CJW		 1097 (set_attr_alternative "length"
1098 [
1099 ;; Alternative 0
6e9ca932
CJW		 1100 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1101 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
1102 (le (minus (match_dup 3) (pc)) (const_int 250)))
1103 (const_int 2)
1104 (if_then_else (and (ge (minus (match_dup 3) (pc))
1105 (const_int -16350))
1106 (le (minus (match_dup 3) (pc))
1107 (const_int 16350)))
1108 (const_int 4)
1109 (const_int 8)))
1110 (const_int 8))
9304f876 1111 ;; Alternative 1
6e9ca932
CJW		 1112 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1113 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -16350))
1114 (le (minus (match_dup 3) (pc)) (const_int 16350)))
1115 (const_int 4)
1116 (const_int 10))
1117 (const_int 10))
1118 ;; Alternative 2
1119 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1120 (if_then_else (and (ge (minus (match_dup 3) (pc)) (const_int -250))
1121 (le (minus (match_dup 3) (pc)) (const_int 250)))
1122 (const_int 4)
1123 (const_int 10))
1124 (const_int 10))
9304f876
CJW		 1125 ])])
1126
1127
1128(define_insn "*cbranchsi4_greater_less_zero"
1129 [(set (pc)
1130 (if_then_else (match_operator 0 "nds32_greater_less_comparison_operator"
1131 [(match_operand:SI 1 "register_operand" "r")
1132 (const_int 0)])
1133 (label_ref (match_operand 2 "" ""))
1134 (pc)))]
1135 ""
1136{
6e9ca932 1137 return nds32_output_cbranchsi4_greater_less_zero (insn, operands);
9304f876
CJW		 1138}
1139 [(set_attr "type" "branch")
1140 (set (attr "length")
6e9ca932
CJW		 1141 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1142 (if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -65500))
1143 (le (minus (match_dup 2) (pc)) (const_int 65500)))
1144 (const_int 4)
1145 (const_int 10))
1146 (const_int 10)))])
9304f876
CJW		 1147
1148
1149(define_expand "cstoresi4"
1150 [(set (match_operand:SI 0 "register_operand" "")
1151 (match_operator:SI 1 "comparison_operator"
1152 [(match_operand:SI 2 "register_operand" "")
1153 (match_operand:SI 3 "nonmemory_operand" "")]))]
1154 ""
1155{
6e9ca932
CJW		 1156 enum nds32_expand_result_type result = nds32_expand_cstore (operands);
1157 switch (result)
9304f876 1158 {
6e9ca932 1159 case EXPAND_DONE:
9304f876 1160 DONE;
6e9ca932
CJW		 1161 break;
1162 case EXPAND_FAIL:
1163 FAIL;
1164 break;
1165 case EXPAND_CREATE_TEMPLATE:
1166 break;
9304f876
CJW		 1167 default:
1168 gcc_unreachable ();
1169 }
1170})
1171
1172
6e9ca932
CJW		 1173(define_expand "slts_compare"
1174 [(set (match_operand:SI 0 "register_operand" "")
1175 (lt:SI (match_operand:SI 1 "general_operand" "")
1176 (match_operand:SI 2 "general_operand" "")))]
1177 ""
1178{
1179 if (!REG_P (operands[1]))
1180 operands[1] = force_reg (SImode, operands[1]);
1181
1182 if (!REG_P (operands[2]) && !satisfies_constraint_Is15 (operands[2]))
1183 operands[2] = force_reg (SImode, operands[2]);
1184})
1185
1186(define_insn "slts_compare_impl"
1187 [(set (match_operand:SI 0 "register_operand" "=t, t, r, r")
1188 (lt:SI (match_operand:SI 1 "register_operand" " d, d, r, r")
1189 (match_operand:SI 2 "nds32_rimm15s_operand" " r,Iu05, r, Is15")))]
9304f876
CJW		 1190 ""
1191 "@
1192 slts45\t%1, %2
1193 sltsi45\t%1, %2
1194 slts\t%0, %1, %2
1195 sltsi\t%0, %1, %2"
6e9ca932
CJW		 1196 [(set_attr "type" "alu, alu, alu, alu")
1197 (set_attr "length" " 2, 2, 4, 4")])
1198
1199(define_insn "slt_eq0"
1200 [(set (match_operand:SI 0 "register_operand" "=t, r")
1201 (eq:SI (match_operand:SI 1 "register_operand" " d, r")
1202 (const_int 0)))]
1203 ""
1204 "@
1205 slti45\t%1, 1
1206 slti\t%0, %1, 1"
1207 [(set_attr "type" "alu, alu")
1208 (set_attr "length" " 2, 4")])
1209
1210(define_expand "slt_compare"
1211 [(set (match_operand:SI 0 "register_operand" "")
1212 (ltu:SI (match_operand:SI 1 "general_operand" "")
1213 (match_operand:SI 2 "general_operand" "")))]
1214 ""
1215{
1216 if (!REG_P (operands[1]))
1217 operands[1] = force_reg (SImode, operands[1]);
1218
1219 if (!REG_P (operands[2]) && !satisfies_constraint_Is15 (operands[2]))
1220 operands[2] = force_reg (SImode, operands[2]);
1221})
9304f876 1222
6e9ca932
CJW		 1223(define_insn "slt_compare_impl"
1224 [(set (match_operand:SI 0 "register_operand" "=t, t, r, r")
1225 (ltu:SI (match_operand:SI 1 "register_operand" " d, d, r, r")
1226 (match_operand:SI 2 "nds32_rimm15s_operand" " r, Iu05, r, Is15")))]
9304f876
CJW		 1227 ""
1228 "@
1229 slt45\t%1, %2
1230 slti45\t%1, %2
1231 slt\t%0, %1, %2
1232 slti\t%0, %1, %2"
5ba6d585
KC		 1233 [(set_attr "type" "alu, alu, alu, alu")
1234 (set_attr "length" " 2, 2, 4, 4")])
9304f876
CJW		 1235
1236
1237;; ----------------------------------------------------------------------------
1238
1239;; Unconditional and other jump instructions.
1240
1241(define_insn "jump"
1242 [(set (pc) (label_ref (match_operand 0 "" "")))]
1243 ""
1244{
1245 /* This unconditional jump has two forms:
1246 32-bit instruction => j imm24s << 1
1247 16-bit instruction => j8 imm8s << 1
1248
1249 For 32-bit case,
1250 we assume it is always reachable.
1251 For 16-bit case,
1252 it must satisfy { 255 >= (label - pc) >= -256 } condition.
1253 However, since the $pc for nds32 is at the beginning of the instruction,
1254 we should leave some length space for current insn.
1255 So we use range -250 ~ 250. */
1256 switch (get_attr_length (insn))
1257 {
1258 case 2:
1259 return "j8\t%0";
1260 case 4:
1261 return "j\t%0";
1262 default:
1263 gcc_unreachable ();
1264 }
1265}
1266 [(set_attr "type" "branch")
30feb954 1267 (set_attr "enabled" "yes")
9304f876 1268 (set (attr "length")
6e9ca932
CJW		 1269 (if_then_else (match_test "!CROSSING_JUMP_P (insn)")
1270 (if_then_else (and (ge (minus (match_dup 0) (pc)) (const_int -250))
1271 (le (minus (match_dup 0) (pc)) (const_int 250)))
1272 (if_then_else (match_test "TARGET_16_BIT")
1273 (const_int 2)
1274 (const_int 4))
9304f876
CJW		 1275 (const_int 4))
1276 (const_int 4)))])
1277
1278(define_insn "indirect_jump"
1279 [(set (pc) (match_operand:SI 0 "register_operand" "r, r"))]
1280 ""
1281 "@
1282 jr5\t%0
1283 jr\t%0"
1284 [(set_attr "type" "branch,branch")
1285 (set_attr "length" " 2, 4")])
1286
1287;; Subroutine call instruction returning no value.
1288;; operands[0]: It should be a mem RTX whose address is
026c3cfd 1289;; the address of the function.
9304f876
CJW		 1290;; operands[1]: It is the number of bytes of arguments pushed as a const_int.
1291;; operands[2]: It is the number of registers used as operands.
1292
1293(define_expand "call"
1294 [(parallel [(call (match_operand 0 "memory_operand" "")
1295 (match_operand 1))
1f7b8028
CJW		 1296 (clobber (reg:SI LP_REGNUM))
1297 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1298 ""
1299 ""
1300)
1301
1302(define_insn "*call_register"
1303 [(parallel [(call (mem (match_operand:SI 0 "register_operand" "r, r"))
1304 (match_operand 1))
1f7b8028
CJW		 1305 (clobber (reg:SI LP_REGNUM))
1306 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1307 ""
1308 "@
1309 jral5\t%0
1310 jral\t%0"
1311 [(set_attr "type" "branch,branch")
1312 (set_attr "length" " 2, 4")])
1313
1314(define_insn "*call_immediate"
1315 [(parallel [(call (mem (match_operand:SI 0 "immediate_operand" "i"))
1316 (match_operand 1))
1f7b8028
CJW		 1317 (clobber (reg:SI LP_REGNUM))
1318 (clobber (reg:SI TA_REGNUM))])]
9304f876 1319 ""
1f7b8028
CJW		 1320{
1321 if (TARGET_CMODEL_LARGE)
1322 return "bal\t%0";
1323 else
1324 return "jal\t%0";
1325}
9304f876 1326 [(set_attr "type" "branch")
1f7b8028
CJW		 1327 (set (attr "length")
1328 (if_then_else (match_test "TARGET_CMODEL_LARGE")
1329 (const_int 12)
1330 (const_int 4)))])
9304f876
CJW		 1331
1332
1333;; Subroutine call instruction returning a value.
1334;; operands[0]: It is the hard regiser in which the value is returned.
1335;; The rest three operands are the same as the
1336;; three operands of the 'call' instruction.
1337;; (but with numbers increased by one)
1338
1339(define_expand "call_value"
1340 [(parallel [(set (match_operand 0)
1341 (call (match_operand 1 "memory_operand" "")
1342 (match_operand 2)))
1f7b8028
CJW		 1343 (clobber (reg:SI LP_REGNUM))
1344 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1345 ""
1346 ""
1347)
1348
1349(define_insn "*call_value_register"
1350 [(parallel [(set (match_operand 0)
1351 (call (mem (match_operand:SI 1 "register_operand" "r, r"))
1352 (match_operand 2)))
1f7b8028
CJW		 1353 (clobber (reg:SI LP_REGNUM))
1354 (clobber (reg:SI TA_REGNUM))])]
9304f876
CJW		 1355 ""
1356 "@
1357 jral5\t%1
1358 jral\t%1"
1359 [(set_attr "type" "branch,branch")
1360 (set_attr "length" " 2, 4")])
1361
1362(define_insn "*call_value_immediate"
1363 [(parallel [(set (match_operand 0)
1364 (call (mem (match_operand:SI 1 "immediate_operand" "i"))
1365 (match_operand 2)))
1f7b8028
CJW		 1366 (clobber (reg:SI LP_REGNUM))
1367 (clobber (reg:SI TA_REGNUM))])]
9304f876 1368 ""
1f7b8028
CJW		 1369{
1370 if (TARGET_CMODEL_LARGE)
1371 return "bal\t%1";
1372 else
1373 return "jal\t%1";
1374}
9304f876 1375 [(set_attr "type" "branch")
1f7b8028
CJW		 1376 (set (attr "length")
1377 (if_then_else (match_test "TARGET_CMODEL_LARGE")
1378 (const_int 12)
1379 (const_int 4)))])
9304f876
CJW		 1380
1381
d6529176
CJW		 1382;; ----------------------------------------------------------------------------
1383
1384;; The sibcall patterns.
1385
1386;; sibcall
cc48a87f 1387;; sibcall_internal
d6529176
CJW		 1388
1389(define_expand "sibcall"
1390 [(parallel [(call (match_operand 0 "memory_operand" "")
1391 (const_int 0))
1392 (clobber (reg:SI TA_REGNUM))
1393 (return)])]
cc48a87f 1394 "")
d6529176 1395
cc48a87f
CJW		 1396(define_insn "sibcall_internal"
1397 [(parallel [(call (mem (match_operand:SI 0 "nds32_call_address_operand" "r, i"))
d6529176
CJW		 1398 (match_operand 1))
1399 (clobber (reg:SI TA_REGNUM))
1400 (return)])]
1401 ""
1402{
cc48a87f
CJW		 1403 switch (which_alternative)
1404 {
1405 case 0:
1406 if (TARGET_16_BIT)
1407 return "jr5\t%0";
1408 else
1409 return "jr\t%0";
1410 case 1:
1411 if (nds32_long_call_p (operands[0]))
1412 return "b\t%0";
1413 else
1414 return "j\t%0";
1415 default:
1416 gcc_unreachable ();
1417 }
d6529176 1418}
30feb954 1419 [(set_attr "enabled" "yes")
cc48a87f
CJW		 1420 (set_attr "type" "branch")
1421 (set_attr_alternative "length"
1422 [
1423 ;; Alternative 0
1424 (if_then_else (match_test "TARGET_16_BIT")
1425 (const_int 2)
1426 (const_int 4))
1427 ;; Alternative 1
1428 (if_then_else (match_test "nds32_long_call_p (operands[0])")
1429 (const_int 12)
1430 (const_int 4))
1431 ])]
1432)
d6529176
CJW		 1433
1434;; sibcall_value
cc48a87f 1435;; sibcall_value_internal
d6529176
CJW		 1436;; sibcall_value_immediate
1437
1438(define_expand "sibcall_value"
1439 [(parallel [(set (match_operand 0)
1440 (call (match_operand 1 "memory_operand" "")
1441 (const_int 0)))
1442 (clobber (reg:SI TA_REGNUM))
1443 (return)])]
cc48a87f 1444 "")
d6529176 1445
cc48a87f 1446(define_insn "sibcall_value_internal"
d6529176 1447 [(parallel [(set (match_operand 0)
cc48a87f 1448 (call (mem (match_operand:SI 1 "nds32_call_address_operand" "r, i"))
d6529176
CJW		 1449 (match_operand 2)))
1450 (clobber (reg:SI TA_REGNUM))
1451 (return)])]
1452 ""
1453{
cc48a87f
CJW		 1454 switch (which_alternative)
1455 {
1456 case 0:
1457 if (TARGET_16_BIT)
1458 return "jr5\t%1";
1459 else
1460 return "jr\t%1";
1461 case 1:
1462 if (nds32_long_call_p (operands[1]))
1463 return "b\t%1";
1464 else
1465 return "j\t%1";
1466 default:
1467 gcc_unreachable ();
1468 }
d6529176 1469}
30feb954 1470 [(set_attr "enabled" "yes")
cc48a87f
CJW		 1471 (set_attr "type" "branch")
1472 (set_attr_alternative "length"
1473 [
1474 ;; Alternative 0
1475 (if_then_else (match_test "TARGET_16_BIT")
1476 (const_int 2)
1477 (const_int 4))
1478 ;; Alternative 1
1479 (if_then_else (match_test "nds32_long_call_p (operands[1])")
1480 (const_int 12)
1481 (const_int 4))
1482 ])]
1483)
d6529176
CJW		 1484
1485;; ----------------------------------------------------------------------------
1486
9304f876
CJW		 1487;; prologue and epilogue.
1488
1489(define_expand "prologue" [(const_int 0)]
1490 ""
1491{
2da1e7c0 1492 /* Note that only under V3/V3M ISA, we could use v3push prologue.
a6c7e777
MC		 1493 In addition, we need to check if v3push is indeed available. */
1494 if (NDS32_V3PUSH_AVAILABLE_P)
9304f876
CJW		 1495 nds32_expand_prologue_v3push ();
1496 else
1497 nds32_expand_prologue ();
1498 DONE;
1499})
1500
1501(define_expand "epilogue" [(const_int 0)]
1502 ""
1503{
2da1e7c0 1504 /* Note that only under V3/V3M ISA, we could use v3pop epilogue.
a6c7e777
MC		 1505 In addition, we need to check if v3push is indeed available. */
1506 if (NDS32_V3PUSH_AVAILABLE_P)
d6529176
CJW		 1507 nds32_expand_epilogue_v3pop (false);
1508 else
1509 nds32_expand_epilogue (false);
1510 DONE;
1511})
1512
1513(define_expand "sibcall_epilogue" [(const_int 0)]
1514 ""
1515{
1516 /* Pass true to indicate that this is sibcall epilogue and
1517 exit from a function without the final branch back to the
1518 calling function. */
a6c7e777 1519 nds32_expand_epilogue (true);
d6529176 1520
9304f876
CJW		 1521 DONE;
1522})
1523
1524
1525;; nop instruction.
1526
1527(define_insn "nop"
1528 [(const_int 0)]
1529 ""
1530{
1531 if (TARGET_16_BIT)
1532 return "nop16";
1533 else
1534 return "nop";
1535}
1536 [(set_attr "type" "misc")
30feb954 1537 (set_attr "enabled" "yes")
9304f876
CJW		 1538 (set (attr "length")
1539 (if_then_else (match_test "TARGET_16_BIT")
1540 (const_int 2)
1541 (const_int 4)))])
1542
1543
1544;; ----------------------------------------------------------------------------
1545;; Stack push/pop operations
1546;; ----------------------------------------------------------------------------
1547
1548;; The pattern for stack push.
1549;; Both stack_push_multiple and stack_v3push use the following pattern.
1550;; So we need to use TARGET_V3PUSH to determine the instruction length.
1551(define_insn "*stack_push"
1552 [(match_parallel 0 "nds32_stack_push_operation"
1553 [(set (mem:SI (plus:SI (reg:SI SP_REGNUM)
1554 (match_operand:SI 1 "const_int_operand" "")))
1555 (match_operand:SI 2 "register_operand" ""))
1556 ])]
1557 ""
1558{
6f3d3f9c 1559 return nds32_output_stack_push (operands[0]);
9304f876 1560}
264159d2
KC		 1561 [(set_attr "type" "store_multiple")
1562 (set_attr "combo" "12")
30feb954 1563 (set_attr "enabled" "yes")
9304f876 1564 (set (attr "length")
6f3d3f9c
CJW		 1565 (if_then_else (match_test "TARGET_V3PUSH
1566 && !nds32_isr_function_p (cfun->decl)
1567 && (cfun->machine->va_args_size == 0)")
9304f876
CJW		 1568 (const_int 2)
1569 (const_int 4)))])
1570
1571
1572;; The pattern for stack pop.
1573;; Both stack_pop_multiple and stack_v3pop use the following pattern.
1574;; So we need to use TARGET_V3PUSH to determine the instruction length.
1575(define_insn "*stack_pop"
1576 [(match_parallel 0 "nds32_stack_pop_operation"
1577 [(set (match_operand:SI 1 "register_operand" "")
1578 (mem:SI (reg:SI SP_REGNUM)))
1579 ])]
1580 ""
1581{
6f3d3f9c 1582 return nds32_output_stack_pop (operands[0]);
9304f876 1583}
264159d2
KC		 1584 [(set_attr "type" "load_multiple")
1585 (set_attr "combo" "12")
30feb954 1586 (set_attr "enabled" "yes")
9304f876 1587 (set (attr "length")
6f3d3f9c
CJW		 1588 (if_then_else (match_test "TARGET_V3PUSH
1589 && !nds32_isr_function_p (cfun->decl)
1590 && (cfun->machine->va_args_size == 0)")
9304f876
CJW		 1591 (const_int 2)
1592 (const_int 4)))])
1593
1594
1595;; ----------------------------------------------------------------------------
03390cda 1596;; Return operation patterns
9304f876
CJW		 1597;; ----------------------------------------------------------------------------
1598
03390cda
CJW		 1599;; Use this pattern to expand a return instruction
1600;; with simple_return rtx if no epilogue is required.
1601(define_expand "return"
1602 [(simple_return)]
1603 "nds32_can_use_return_insn ()"
1604 ""
1605)
9304f876 1606
03390cda
CJW		 1607;; This pattern is expanded only by the shrink-wrapping optimization
1608;; on paths where the function prologue has not been executed.
1609(define_expand "simple_return"
1610 [(simple_return)]
1611 ""
1612 ""
1613)
1614
1615(define_insn "return_internal"
1616 [(simple_return)]
9304f876
CJW		 1617 ""
1618{
1619 if (TARGET_16_BIT)
1620 return "ret5";
1621 else
1622 return "ret";
1623}
03390cda 1624 [(set_attr "type" "branch")
30feb954 1625 (set_attr "enabled" "yes")
9304f876
CJW		 1626 (set (attr "length")
1627 (if_then_else (match_test "TARGET_16_BIT")
1628 (const_int 2)
1629 (const_int 4)))])
1630
1631
1632;; ----------------------------------------------------------------------------
1633;; Jump Table patterns
1634;; ----------------------------------------------------------------------------
1635;; Need to implement ASM_OUTPUT_ADDR_VEC_ELT (for normal jump table)
1636;; or ASM_OUTPUT_ADDR_DIFF_ELT (for pc relative jump table) as well.
1637;;
1638;; operands[0]: The index to dispatch on.
1639;; operands[1]: The lower bound for indices in the table.
1640;; operands[2]: The total range of indices int the table.
1641;; i.e. The largest index minus the smallest one.
1642;; operands[3]: A label that precedes the table itself.
1643;; operands[4]: A label to jump to if the index has a value outside the bounds.
1644;;
1645;; We need to create following sequences for jump table code generation:
1646;; A) k <-- (plus (operands[0]) (-operands[1]))
1647;; B) if (gtu k operands[2]) then goto operands[4]
1648;; C) t <-- operands[3]
1649;; D) z <-- (mem (plus (k << 0 or 1 or 2) t))
1650;; E) z <-- t + z (NOTE: This is only required for pc relative jump table.)
1651;; F) jump to target with register t or z
1652;;
1653;; The steps C, D, E, and F are performed by casesi_internal pattern.
1654(define_expand "casesi"
1655 [(match_operand:SI 0 "register_operand" "r") ; index to jump on
1656 (match_operand:SI 1 "immediate_operand" "i") ; lower bound
1657 (match_operand:SI 2 "immediate_operand" "i") ; total range
1658 (match_operand:SI 3 "" "") ; table label
1659 (match_operand:SI 4 "" "")] ; Out of range label
1660 ""
1661{
1662 rtx add_tmp;
1663 rtx reg, test;
1664
1665 /* Step A: "k <-- (plus (operands[0]) (-operands[1]))". */
1666 if (operands[1] != const0_rtx)
1667 {
1668 reg = gen_reg_rtx (SImode);
1669 add_tmp = gen_int_mode (-INTVAL (operands[1]), SImode);
1670
1671 /* If the integer value is not in the range of imm15s,
8a498f99
CJW		 1672 we need to force register first because our addsi3 pattern
1673 only accept nds32_rimm15s_operand predicate. */
9304f876
CJW		 1674 add_tmp = force_reg (SImode, add_tmp);
1675
1676 emit_insn (gen_addsi3 (reg, operands[0], add_tmp));
1677 operands[0] = reg;
1678 }
1679
1680 /* Step B: "if (gtu k operands[2]) then goto operands[4]". */
1681 test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
1682 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2],
1683 operands[4]));
1684
9759608c
SB		 1685 /* Step C, D, E, and F, using another temporary register. */
1686 rtx tmp = gen_reg_rtx (SImode);
1687 emit_jump_insn (gen_casesi_internal (operands[0], operands[3], tmp));
9304f876
CJW		 1688 DONE;
1689})
1690
1691;; We are receiving operands from casesi pattern:
1692;;
1693;; operands[0]: The index that have been substracted with lower bound.
1694;; operands[1]: A label that precedes the table itself.
1695;; operands[2]: A temporary register to retrieve value in table.
1696;;
1697;; We need to perform steps C, D, E, and F:
1698;;
1699;; C) t <-- operands[1]
1700;; D) z <-- (mem (plus (operands[0] << m) t))
1701;; m is 2 for normal jump table.
1702;; m is 0, 1, or 2 for pc relative jump table based on diff size.
1703;; E) t <-- z + t (NOTE: This is only required for pc relative jump table.)
1704;; F) Jump to target with register t or z.
1705;;
1706;; The USE in this pattern is needed to tell flow analysis that this is
1707;; a CASESI insn. It has no other purpose.
1708(define_insn "casesi_internal"
1709 [(parallel [(set (pc)
1710 (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "r")
1711 (const_int 4))
1712 (label_ref (match_operand 1 "" "")))))
1713 (use (label_ref (match_dup 1)))
24f036fb 1714 (clobber (match_operand:SI 2 "register_operand" "=r"))
9304f876
CJW		 1715 (clobber (reg:SI TA_REGNUM))])]
1716 ""
1717{
1718 if (CASE_VECTOR_PC_RELATIVE)
1719 return nds32_output_casesi_pc_relative (operands);
1720 else
1721 return nds32_output_casesi (operands);
1722}
1723 [(set_attr "length" "20")
5ba6d585 1724 (set_attr "type" "branch")])
9304f876
CJW		 1725
1726;; ----------------------------------------------------------------------------
1727
1728;; Performance Extension
1729
1730(define_insn "clzsi2"
1731 [(set (match_operand:SI 0 "register_operand" "=r")
1732 (clz:SI (match_operand:SI 1 "register_operand" " r")))]
aa4b851c 1733 "TARGET_EXT_PERF"
9304f876
CJW		 1734 "clz\t%0, %1"
1735 [(set_attr "type" "alu")
1736 (set_attr "length" "4")])
1737
1738(define_insn "smaxsi3"
1739 [(set (match_operand:SI 0 "register_operand" "=r")
1740 (smax:SI (match_operand:SI 1 "register_operand" " r")
1741 (match_operand:SI 2 "register_operand" " r")))]
aa4b851c 1742 "TARGET_EXT_PERF"
9304f876
CJW		 1743 "max\t%0, %1, %2"
1744 [(set_attr "type" "alu")
1745 (set_attr "length" "4")])
1746
1747(define_insn "sminsi3"
1748 [(set (match_operand:SI 0 "register_operand" "=r")
1749 (smin:SI (match_operand:SI 1 "register_operand" " r")
1750 (match_operand:SI 2 "register_operand" " r")))]
aa4b851c 1751 "TARGET_EXT_PERF"
9304f876
CJW		 1752 "min\t%0, %1, %2"
1753 [(set_attr "type" "alu")
1754 (set_attr "length" "4")])
1755
1756(define_insn "*btst"
1757 [(set (match_operand:SI 0 "register_operand" "= r")
1758 (zero_extract:SI (match_operand:SI 1 "register_operand" " r")
1759 (const_int 1)
1760 (match_operand:SI 2 "immediate_operand" " Iu05")))]
aa4b851c 1761 "TARGET_EXT_PERF"
9304f876
CJW		 1762 "btst\t%0, %1, %2"
1763 [(set_attr "type" "alu")
1764 (set_attr "length" "4")])
1765
1766;; ----------------------------------------------------------------------------
aa2642ef
CJW		 1767
1768;; Pseudo NOPs
1769
c4d8d050
CJW		 1770(define_insn "relax_group"
1771 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "i")] UNSPEC_VOLATILE_RELAX_GROUP)]
1772 ""
1773 ".relax_hint %0"
1774 [(set_attr "length" "0")]
1775)
1776
aa2642ef
CJW		 1777(define_insn "pop25return"
1778 [(return)
1779 (unspec_volatile:SI [(reg:SI LP_REGNUM)] UNSPEC_VOLATILE_POP25_RETURN)]
1780 ""
1781 "! return for pop 25"
1782 [(set_attr "length" "0")]
1783)
1784
1785;; ----------------------------------------------------------------------------
Mirror of https://gcc.gnu.org/git/gcc.git