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e430824f | 1 | ;; Constraint definitions for Altera Nios II. |
7adcbafe | 2 | ;; Copyright (C) 2012-2022 Free Software Foundation, Inc. |
e430824f CLT |
3 | ;; Contributed by Chung-Lin Tang <cltang@codesourcery.com> |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify | |
8 | ;; it under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 3, or (at your option) | |
10 | ;; any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, | |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ;; GNU General Public License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ;; We use the following constraint letters for constants | |
22 | ;; | |
3bbbe009 | 23 | ;; I: -32768 to 32767 |
e430824f CLT |
24 | ;; J: 0 to 65535 |
25 | ;; K: $nnnn0000 for some nnnn | |
3bbbe009 | 26 | ;; P: Under R2, $nnnnffff or $ffffnnnn for some nnnn |
e430824f CLT |
27 | ;; L: 0 to 31 (for shift counts) |
28 | ;; M: 0 | |
29 | ;; N: 0 to 255 (for custom instruction numbers) | |
30 | ;; O: 0 to 31 (for control register numbers) | |
524d2e49 | 31 | ;; U: -32768 to 32767 under R1, -2048 to 2047 under R2 |
e430824f | 32 | ;; |
42e6ab74 SL |
33 | ;; We use the following constraint letters for memory constraints |
34 | ;; | |
524d2e49 | 35 | ;; v: memory operands for R2 load/store exclusive instructions |
42e6ab74 SL |
36 | ;; w: memory operands for load/store IO and cache instructions |
37 | ;; | |
e430824f CLT |
38 | ;; We use the following built-in register classes: |
39 | ;; | |
40 | ;; r: general purpose register (r0..r31) | |
41 | ;; m: memory operand | |
42 | ;; | |
43 | ;; Plus, we define the following constraint strings: | |
44 | ;; | |
45 | ;; S: symbol that is in the "small data" area | |
46 | ||
47 | ;; Register constraints | |
48 | ||
3c8c9f0d CLT |
49 | (define_register_constraint "c" "IJMP_REGS" |
50 | "A register suitable for an indirect jump.") | |
51 | ||
e430824f CLT |
52 | (define_register_constraint "j" "SIB_REGS" |
53 | "A register suitable for an indirect sibcall.") | |
54 | ||
55 | ;; Integer constraints | |
56 | ||
57 | (define_constraint "I" | |
58 | "A signed 16-bit constant (for arithmetic instructions)." | |
59 | (and (match_code "const_int") | |
60 | (match_test "SMALL_INT (ival)"))) | |
61 | ||
62 | (define_constraint "J" | |
63 | "An unsigned 16-bit constant (for logical instructions)." | |
64 | (and (match_code "const_int") | |
65 | (match_test "SMALL_INT_UNSIGNED (ival)"))) | |
66 | ||
67 | (define_constraint "K" | |
68 | "An unsigned 16-bit high constant (for logical instructions)." | |
69 | (and (match_code "const_int") | |
70 | (match_test "UPPER16_INT (ival)"))) | |
71 | ||
72 | (define_constraint "L" | |
73 | "An unsigned 5-bit constant (for shift counts)." | |
74 | (and (match_code "const_int") | |
75 | (match_test "ival >= 0 && ival <= 31"))) | |
76 | ||
77 | (define_constraint "M" | |
78 | "Integer zero." | |
79 | (and (match_code "const_int") | |
80 | (match_test "ival == 0"))) | |
81 | ||
82 | (define_constraint "N" | |
83 | "An unsigned 8-bit constant (for custom instruction codes)." | |
84 | (and (match_code "const_int") | |
85 | (match_test "ival >= 0 && ival <= 255"))) | |
86 | ||
87 | (define_constraint "O" | |
88 | "An unsigned 5-bit constant (for control register numbers)." | |
89 | (and (match_code "const_int") | |
90 | (match_test "ival >= 0 && ival <= 31"))) | |
91 | ||
3bbbe009 SL |
92 | (define_constraint "P" |
93 | "An immediate operand for R2 andchi/andci instructions." | |
94 | (and (match_code "const_int") | |
95 | (match_test "TARGET_ARCH_R2 && ANDCLEAR_INT (ival)"))) | |
96 | ||
e430824f | 97 | (define_constraint "S" |
1cef1159 SL |
98 | "An immediate stored in small data, accessible by GP, or by offset from r0." |
99 | (match_test "gprel_constant_p (op) || r0rel_constant_p (op)")) | |
e430824f CLT |
100 | |
101 | (define_constraint "T" | |
102 | "A constant unspec offset representing a relocation." | |
103 | (match_test "nios2_unspec_reloc_p (op)")) | |
42e6ab74 | 104 | |
524d2e49 SL |
105 | (define_constraint "U" |
106 | "A 12-bit or 16-bit constant (for RDPRS and DCACHE)." | |
107 | (and (match_code "const_int") | |
108 | (if_then_else (match_test "TARGET_ARCH_R2") | |
109 | (match_test "SMALL_INT12 (ival)") | |
110 | (match_test "SMALL_INT (ival)")))) | |
111 | ||
112 | (define_memory_constraint "v" | |
113 | "A memory operand suitable for R2 load/store exclusive instructions." | |
114 | (match_operand 0 "ldstex_memory_operand")) | |
115 | ||
42e6ab74 SL |
116 | (define_memory_constraint "w" |
117 | "A memory operand suitable for load/store IO and cache instructions." | |
118 | (match_operand 0 "ldstio_memory_operand")) |