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3965b35f | 1 | /* Target Definitions for OpenRISC. |
a5544970 | 2 | Copyright (C) 2018-2019 Free Software Foundation, Inc. |
3965b35f SH |
3 | Contributed by Stafford Horne. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it | |
8 | under the terms of the GNU General Public License as published | |
9 | by the Free Software Foundation; either version 3, or (at your | |
10 | option) any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #ifndef GCC_OR1K_H | |
22 | #define GCC_OR1K_H | |
23 | ||
24 | /* Names to predefine in the preprocessor for this target machine. */ | |
25 | #define TARGET_CPU_CPP_BUILTINS() \ | |
26 | do \ | |
27 | { \ | |
28 | builtin_define ("__OR1K__"); \ | |
29 | builtin_define ("__OR1K_DELAY__"); \ | |
30 | builtin_define ("__or1k__"); \ | |
31 | if (TARGET_CMOV) \ | |
32 | builtin_define ("__or1k_cmov__"); \ | |
33 | builtin_assert ("cpu=or1k"); \ | |
34 | builtin_assert ("machine=or1k"); \ | |
35 | } \ | |
36 | while (0) | |
37 | ||
38 | /* Storage layout. */ | |
39 | ||
40 | #define DEFAULT_SIGNED_CHAR 1 | |
41 | #define BITS_BIG_ENDIAN 0 | |
42 | #define BYTES_BIG_ENDIAN 1 | |
43 | #define WORDS_BIG_ENDIAN 1 | |
44 | #define BITS_PER_WORD 32 | |
45 | #define UNITS_PER_WORD 4 | |
46 | #define POINTER_SIZE 32 | |
47 | #define BIGGEST_ALIGNMENT 32 | |
48 | #define STRICT_ALIGNMENT 1 | |
49 | #define FUNCTION_BOUNDARY 32 | |
50 | #define PARM_BOUNDARY 32 | |
51 | #define STACK_BOUNDARY 32 | |
52 | #define PREFERRED_STACK_BOUNDARY 32 | |
53 | #define MAX_FIXED_MODE_SIZE 64 | |
54 | ||
55 | /* Layout of source language data types. */ | |
56 | ||
57 | #define INT_TYPE_SIZE 32 | |
58 | #define SHORT_TYPE_SIZE 16 | |
59 | #define LONG_TYPE_SIZE 32 | |
60 | #define LONG_LONG_TYPE_SIZE 64 | |
61 | #define FLOAT_TYPE_SIZE 32 | |
62 | #define DOUBLE_TYPE_SIZE 64 | |
63 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
64 | #define WCHAR_TYPE_SIZE 32 | |
65 | ||
66 | #undef SIZE_TYPE | |
67 | #define SIZE_TYPE "unsigned int" | |
68 | ||
69 | #undef PTRDIFF_TYPE | |
70 | #define PTRDIFF_TYPE "int" | |
71 | ||
72 | #undef WCHAR_TYPE | |
73 | #define WCHAR_TYPE "unsigned int" | |
74 | ||
75 | /* Describing Relative Costs of Operations. */ | |
76 | #define MOVE_MAX 4 | |
77 | #define SLOW_BYTE_ACCESS 1 | |
78 | ||
79 | /* Register usage, class and contents. */ | |
80 | ||
81 | /* In OpenRISC there are 32 general purpose registers with the following | |
82 | designations: | |
83 | ||
84 | r0 always 0 | |
85 | r1 stack pointer | |
86 | r2 frame pointer (optional) | |
87 | r3 arg 0 | |
88 | r4 arg 1 | |
89 | r5 arg 2 | |
90 | r6 arg 3 | |
91 | r7 arg 4 | |
92 | r8 arg 5 | |
93 | r9 function call return link address | |
94 | r10 thread local storage | |
95 | r11 function return value & static chain | |
96 | r12 function return value high (upper 64-bit) | |
97 | r13 temporary (used in prologue and epilogue) | |
98 | r14 callee saved | |
99 | r15 temporary | |
100 | r16 callee saved & pic base register | |
101 | r17 temporary | |
102 | r18 callee saved | |
103 | r19 temporary | |
104 | r20 callee saved | |
105 | r21 temporary | |
106 | r22 callee saved | |
107 | r23 temporary | |
108 | r24 callee saved | |
109 | r25 temporary | |
110 | r26 callee saved | |
111 | r27 temporary | |
112 | r28 callee saved | |
113 | r29 temporary | |
114 | r30 callee saved | |
115 | r31 temporary | |
116 | ||
117 | r32 soft argument pointer | |
118 | r33 soft frame pointer | |
119 | r34 SR[F] (bit) register | |
120 | ||
121 | This ABI has no adjacent call-saved register, which means that | |
122 | DImode/DFmode pseudos cannot be call-saved and will always be | |
123 | spilled across calls. To solve this without changing the ABI, | |
124 | remap the compiler internal register numbers to place the even | |
125 | call-saved registers r16-r30 in 24-31, and the odd call-clobbered | |
126 | registers r17-r31 in 16-23. */ | |
127 | ||
128 | #define FIRST_PSEUDO_REGISTER 35 | |
129 | ||
130 | #define HW_TO_GCC_REGNO(X) \ | |
131 | ((X) < 16 || (X) > 31 ? (X) \ | |
132 | : (X) & 1 ? ((X) - 16) / 2 + 16 \ | |
133 | : ((X) - 16) / 2 + 24) | |
134 | ||
135 | #define GCC_TO_HW_REGNO(X) \ | |
136 | ((X) < 16 || (X) > 31 ? (X) \ | |
137 | : (X) < 24 ? ((X) - 16) * 2 + 17 \ | |
138 | : ((X) - 24) * 2 + 16) | |
139 | ||
140 | #define DBX_REGISTER_NUMBER(X) GCC_TO_HW_REGNO(X) | |
141 | ||
142 | #define REGISTER_NAMES { \ | |
143 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ | |
144 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
145 | "r17", "r19", "r21", "r23", "r25", "r27", "r29", "r31", \ | |
146 | "r16", "r18", "r20", "r22", "r24", "r26", "r28", "r30", \ | |
147 | "?ap", "?fp", "?sr_f" } | |
148 | ||
149 | #define FIXED_REGISTERS \ | |
150 | { 1, 1, 0, 0, 0, 0, 0, 0, \ | |
151 | 0, 0, 1, 0, 0, 0, 0, 0, \ | |
152 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
153 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
154 | 1, 1, 1 } | |
155 | ||
156 | /* Caller saved/temporary registers + args + fixed */ | |
157 | #define CALL_USED_REGISTERS \ | |
158 | { 1, 1, 0, 1, 1, 1, 1, 1, \ | |
159 | 1, 1, 1, 1, 1, 1, 0, 1, \ | |
160 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
161 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
162 | 1, 1, 1 } | |
163 | ||
164 | /* List the order in which to allocate registers. Each register must | |
165 | be listed once, even those in FIXED_REGISTERS. | |
166 | ||
167 | ??? Note that placing REAL_PIC_OFFSET_TABLE_REGNUM (r16 = 24) first | |
168 | happens to make it most likely selected *as* the pic register when | |
169 | compiling without optimization, simply because the pic pseudo happens | |
170 | to be allocated with the lowest pseudo regno. */ | |
171 | ||
172 | #define REG_ALLOC_ORDER { \ | |
173 | 16, 17, 18, 19, 20, 21, 22, 23, /* r17-r31 (odd), non-saved */ \ | |
174 | 13, 15, /* non-saved */ \ | |
175 | 12, 11, /* non-saved return values */ \ | |
176 | 8, 7, 6, 5, 4, 3, /* non-saved argument regs */ \ | |
177 | 24, /* r16, saved, pic reg */ \ | |
178 | 25, 26, 27, 28, 29, 30, 31, /* r18-r31 (even), saved */ \ | |
179 | 14, /* r14, saved */ \ | |
180 | 2, /* saved hard frame pointer */ \ | |
181 | 9, /* saved return address */ \ | |
182 | 0, /* fixed zero reg */ \ | |
183 | 1, /* fixed stack pointer */ \ | |
184 | 10, /* fixed thread pointer */ \ | |
185 | 32, 33, 34, /* fixed ap, fp, sr[f], */ \ | |
186 | } | |
187 | ||
188 | enum reg_class | |
189 | { | |
190 | NO_REGS, | |
191 | SIBCALL_REGS, | |
192 | GENERAL_REGS, | |
193 | FLAG_REGS, | |
194 | ALL_REGS, | |
195 | LIM_REG_CLASSES | |
196 | }; | |
197 | ||
198 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
199 | ||
200 | #define REG_CLASS_NAMES { \ | |
201 | "NO_REGS", \ | |
202 | "SIBCALL_REGS", \ | |
203 | "GENERAL_REGS", \ | |
204 | "FLAG_REGS", \ | |
205 | "ALL_REGS" } | |
206 | ||
207 | /* The SIBCALL_REGS must be call-clobbered, and not used as a temporary | |
208 | in the epilogue. This excludes R9 (LR), R11 (STATIC_CHAIN), and | |
209 | R13 (PE_TMP_REGNUM). */ | |
210 | #define SIBCALL_REGS_MASK 0x00ff95f8u | |
211 | ||
212 | #define REG_CLASS_CONTENTS \ | |
213 | { { 0x00000000, 0x00000000 }, \ | |
214 | { SIBCALL_REGS_MASK, 0 }, \ | |
215 | { 0xffffffff, 0x00000003 }, \ | |
216 | { 0x00000000, 0x00000004 }, \ | |
217 | { 0xffffffff, 0x00000007 } \ | |
218 | } | |
219 | ||
220 | /* A C expression whose value is a register class containing hard | |
221 | register REGNO. In general there is more that one such class; | |
222 | choose a class which is "minimal", meaning that no smaller class | |
223 | also contains the register. */ | |
224 | #define REGNO_REG_CLASS(REGNO) \ | |
225 | ((REGNO) >= SR_F_REGNUM ? FLAG_REGS \ | |
226 | : (REGNO) < 32 && ((SIBCALL_REGS_MASK >> (REGNO)) & 1) ? SIBCALL_REGS \ | |
227 | : GENERAL_REGS) | |
228 | ||
229 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
230 | do { \ | |
231 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
232 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
233 | (MODE) = word_mode; \ | |
234 | } while (0) | |
235 | ||
236 | /* A macro whose definition is the name of the class to which a valid | |
237 | base register must belong. A base register is one used in an | |
238 | address which is the register value plus a displacement. */ | |
239 | #define BASE_REG_CLASS GENERAL_REGS | |
240 | ||
241 | #define INDEX_REG_CLASS NO_REGS | |
242 | ||
243 | /* Assembly definitions. */ | |
244 | ||
245 | #define ASM_APP_ON "" | |
246 | #define ASM_APP_OFF "" | |
247 | ||
248 | #define ASM_COMMENT_START "# " | |
249 | ||
250 | #define GLOBAL_ASM_OP "\t.global\t" | |
251 | #define TEXT_SECTION_ASM_OP "\t.section\t.text" | |
252 | #define DATA_SECTION_ASM_OP "\t.section\t.data" | |
253 | #define BSS_SECTION_ASM_OP "\t.section\t.bss" | |
254 | #define SBSS_SECTION_ASM_OP "\t.section\t.sbss" | |
255 | ||
256 | /* This is how to output an assembler line | |
257 | that says to advance the location counter | |
258 | to a multiple of 2**LOG bytes. */ | |
259 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
260 | do \ | |
261 | { \ | |
262 | if ((LOG) != 0) \ | |
263 | fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ | |
264 | } \ | |
265 | while (0) | |
266 | ||
267 | /* This is used in crtstuff to create call stubs in the | |
268 | _init() and _fini() functions. Defining this here saves | |
269 | a few bytes created by the dummy call_xxx() functions. */ | |
270 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
271 | asm (SECTION_OP "\n" \ | |
272 | " l.jal " #FUNC "\n" \ | |
273 | " l.nop\n" \ | |
274 | " .previous"); | |
275 | ||
276 | ||
277 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) (code == '#') | |
278 | ||
279 | /* Calling convention definitions. */ | |
280 | #define CUMULATIVE_ARGS int | |
281 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
282 | do { (CUM) = 0; } while (0) | |
283 | ||
284 | ||
285 | /* Trampolines, for nested functions */ | |
286 | #define TRAMPOLINE_SIZE 20 | |
287 | #define TRAMPOLINE_ALIGNMENT 32 | |
288 | ||
289 | /* Pointer mode */ | |
290 | #define Pmode SImode | |
291 | #define FUNCTION_MODE SImode | |
292 | #define STACK_POINTER_REGNUM SP_REGNUM | |
293 | #define FRAME_POINTER_REGNUM SFP_REGNUM | |
294 | #define HARD_FRAME_POINTER_REGNUM HFP_REGNUM | |
295 | #define STATIC_CHAIN_REGNUM RV_REGNUM | |
296 | ||
297 | /* The register number of the arg pointer register, which is used to | |
298 | access the function's argument list. */ | |
299 | #define ARG_POINTER_REGNUM AP_REGNUM | |
300 | ||
301 | /* Position Independent Code. See or1k_init_pic_reg. */ | |
302 | #define REAL_PIC_OFFSET_TABLE_REGNUM HW_TO_GCC_REGNO (16) | |
303 | ||
304 | /* ??? Follow i386 in working around gimple costing estimation, which | |
305 | happens without properly initializing the pic_offset_table pseudo. */ | |
306 | #define PIC_OFFSET_TABLE_REGNUM \ | |
307 | (pic_offset_table_rtx ? INVALID_REGNUM : REAL_PIC_OFFSET_TABLE_REGNUM) | |
308 | ||
309 | /* A C expression that is nonzero if REGNO is the number of a hard | |
310 | register in which function arguments are sometimes passed. */ | |
311 | #define FUNCTION_ARG_REGNO_P(r) (r >= 3 && r <= 8) | |
312 | ||
313 | #define MAX_REGS_PER_ADDRESS 1 | |
314 | ||
315 | /* The ELIMINABLE_REGS macro specifies a table of register pairs used to | |
316 | eliminate unneeded registers that point into the stack frame. Note, | |
317 | the only elimination attempted by the compiler is to replace references | |
318 | to the frame pointer with references to the stack pointer. */ | |
319 | ||
320 | #define ELIMINABLE_REGS \ | |
321 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
322 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
323 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
324 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }} | |
325 | ||
326 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
327 | do { \ | |
328 | (OFFSET) = or1k_initial_elimination_offset ((FROM), (TO)); \ | |
329 | } while (0) | |
330 | ||
331 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 | |
332 | #define REGNO_OK_FOR_BASE_P(REGNO) ((REGNO) <= SFP_REGNUM) | |
333 | ||
334 | /* If defined, the maximum amount of space required for outgoing | |
335 | arguments will be computed and placed into the variable | |
336 | 'crtl->outgoing_args_size'. No space will be pushed | |
337 | onto the stack for each call; instead, the function prologue | |
338 | should increase the stack frame size by this amount. */ | |
339 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
340 | ||
341 | /* Stack layout and stack pointer usage. */ | |
342 | ||
343 | /* This plus ARG_POINTER_REGNUM points to the first word of incoming args. */ | |
344 | #define FIRST_PARM_OFFSET(FNDECL) (0) | |
345 | ||
346 | /* This plus STACK_POINTER_REGNUM points to the first work of outgoing args. */ | |
347 | #define STACK_POINTER_OFFSET (0) | |
348 | ||
349 | /* Define this macro if pushing a word onto the stack moves the stack | |
350 | pointer to a smaller address. */ | |
351 | #define STACK_GROWS_DOWNWARD 1 | |
352 | ||
353 | #define FRAME_GROWS_DOWNWARD 1 | |
354 | ||
355 | /* An alias for a machine mode name. This is the machine mode that | |
356 | elements of a jump-table should have. */ | |
357 | #define CASE_VECTOR_MODE SImode | |
358 | ||
359 | #define STORE_FLAG_VALUE 1 | |
360 | ||
361 | /* Indicates how loads of narrow mode values are loaded into words. */ | |
362 | #define LOAD_EXTEND_OP(MODE) (ZERO_EXTEND) | |
363 | ||
364 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
365 | the stack pointer does not matter. */ | |
366 | #define EXIT_IGNORE_STACK 1 | |
367 | ||
368 | /* Macros related to the access of the stack frame chain. */ | |
369 | #define INITIAL_FRAME_ADDRESS_RTX or1k_initial_frame_addr () | |
370 | #define DYNAMIC_CHAIN_ADDRESS or1k_dynamic_chain_addr | |
371 | #define RETURN_ADDR_RTX or1k_return_addr | |
372 | ||
373 | /* Always pass the SYMBOL_REF for direct calls to the expanders. */ | |
374 | #define NO_FUNCTION_CSE 1 | |
375 | ||
376 | /* Profiling */ | |
377 | #define FUNCTION_PROFILER(FILE,LABELNO) (abort (), 0) | |
378 | ||
379 | /* Dwarf 2 Support */ | |
380 | #define DWARF2_DEBUGGING_INFO 1 | |
381 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) | |
382 | #define DWARF_FRAME_RETURN_COLUMN LR_REGNUM | |
383 | ||
384 | /* Describe how we implement __builtin_eh_return. */ | |
385 | #define EH_RETURN_REGNUM HW_TO_GCC_REGNO (23) | |
386 | /* Use r25, r27, r29 and r31 (clobber regs) for exception data. | |
387 | Recall that these are remapped consecutively. */ | |
388 | #define EH_RETURN_DATA_REGNO(N) \ | |
389 | ((N) < 4 ? HW_TO_GCC_REGNO (25) + (N) : INVALID_REGNUM) | |
390 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM) | |
391 | ||
392 | #endif /* GCC_OR1K_H */ |