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5b281141 JDA |
1 | ;; Constraint definitions for pa |
2 | ;; Copyright (C) 2007 Free Software Foundation, Inc. | |
3 | ||
4 | ;; This file is part of GCC. | |
5 | ||
6 | ;; GCC is free software; you can redistribute it and/or modify it | |
7 | ;; under the terms of the GNU General Public License as published | |
8 | ;; by the Free Software Foundation; either version 2, or (at your | |
9 | ;; option) any later version. | |
10 | ||
11 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
12 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | ;; License for more details. | |
15 | ||
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING. If not, write to | |
18 | ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, | |
19 | ;; Boston, MA 02110-1301, USA. | |
20 | ||
21 | ;;; Unused letters: | |
22 | ;;; ABCDEF H V XY | |
23 | ;;; bcde ghijklmnop stuvw z | |
24 | ||
25 | ;; Register constraints. | |
26 | (define_register_constraint "a" "R1_REGS" | |
27 | "General register 1.") | |
28 | ||
29 | (define_register_constraint "f" "FP_REGS" | |
30 | "Floating-point register.") | |
31 | ||
32 | (define_register_constraint "q" "SHIFT_REGS" | |
33 | "Shift amount register.") | |
34 | ||
35 | ;; Keep 'x' for backward compatibility with user asm. | |
36 | (define_register_constraint "x" "FP_REGS" | |
37 | "Floating-point register.") | |
38 | ||
39 | (define_register_constraint "y" "TARGET_64BIT ? FP_REGS : FPUPPER_REGS" | |
40 | "Upper floating-point register.") | |
41 | ||
42 | (define_register_constraint "Z" "ALL_REGS" | |
43 | "Any register.") | |
44 | ||
45 | ;; Integer constant constraints. | |
46 | (define_constraint "I" | |
47 | "Signed 11-bit integer constant." | |
48 | (and (match_code "const_int") | |
49 | (match_test "VAL_11_BITS_P (ival)"))) | |
50 | ||
51 | (define_constraint "J" | |
52 | "Signed 14-bit integer constant." | |
53 | (and (match_code "const_int") | |
54 | (match_test "VAL_14_BITS_P (ival)"))) | |
55 | ||
56 | (define_constraint "K" | |
57 | "Integer constant that can be deposited with a zdepi instruction." | |
58 | (and (match_code "const_int") | |
59 | (match_test "zdepi_cint_p (ival)"))) | |
60 | ||
61 | (define_constraint "L" | |
62 | "Signed 5-bit integer constant." | |
63 | (and (match_code "const_int") | |
64 | (match_test "VAL_5_BITS_P (ival)"))) | |
65 | ||
66 | (define_constraint "M" | |
67 | "Integer constant 0." | |
68 | (and (match_code "const_int") | |
69 | (match_test "ival == 0"))) | |
70 | ||
71 | (define_constraint "N" | |
72 | "Integer constant that can be loaded with a ldil instruction." | |
73 | (and (match_code "const_int") | |
74 | (match_test "ldil_cint_p (ival)"))) | |
75 | ||
76 | (define_constraint "O" | |
77 | "Integer constant such that ival+1 is a power of 2." | |
78 | (and (match_code "const_int") | |
79 | (match_test "(ival & (ival + 1)) == 0"))) | |
80 | ||
81 | (define_constraint "P" | |
82 | "Integer constant that can be used as an and mask in depi and | |
83 | extru instructions." | |
84 | (and (match_code "const_int") | |
85 | (match_test "and_mask_p (ival)"))) | |
86 | ||
87 | (define_constraint "S" | |
88 | "Integer constant 31." | |
89 | (and (match_code "const_int") | |
90 | (match_test "ival == 31"))) | |
91 | ||
92 | (define_constraint "U" | |
93 | "Integer constant 63." | |
94 | (and (match_code "const_int") | |
95 | (match_test "ival == 63"))) | |
96 | ||
97 | ;; Floating-point constant constraints. | |
98 | (define_constraint "G" | |
99 | "Floating-point constant 0." | |
100 | (and (match_code "const_double") | |
101 | (match_test "GET_MODE_CLASS (mode) == MODE_FLOAT | |
102 | && op == CONST0_RTX (mode)"))) | |
103 | ||
104 | ;; Extra constraints. | |
105 | (define_constraint "A" | |
106 | "A LO_SUM DLT memory operand." | |
107 | (and (match_code "mem") | |
108 | (match_test "IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0))"))) | |
109 | ||
110 | (define_constraint "Q" | |
111 | "A memory operand that can be used as the destination operand of an | |
112 | integer store, or the source operand of an integer load. That is | |
113 | any memory operand that isn't a symbolic, indexed or lo_sum memory | |
114 | operand. Note that an unassigned pseudo register is such a memory | |
115 | operand. We accept unassigned pseudo registers because reload | |
116 | generates them and then doesn't re-recognize the insn, causing | |
117 | constrain_operands to fail." | |
118 | (match_test "integer_store_memory_operand (op, mode)")) | |
119 | ||
120 | (define_constraint "R" | |
121 | "A scaled or unscaled indexed memory operand that can be used as the | |
122 | source address in integer and floating-point loads." | |
123 | (and (match_code "mem") | |
124 | (match_test "IS_INDEX_ADDR_P (XEXP (op, 0))"))) | |
125 | ||
126 | (define_constraint "T" | |
127 | "A memory operand for floating-point loads and stores." | |
128 | (and (match_code "mem") | |
129 | (match_test "!IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0)) | |
130 | && !IS_INDEX_ADDR_P (XEXP (op, 0)) | |
131 | && memory_address_p ((GET_MODE_SIZE (mode) == 4 | |
132 | ? SFmode : DFmode), | |
133 | XEXP (op, 0))"))) | |
134 | ||
135 | ;; We could allow short displacements but GO_IF_LEGITIMATE_ADDRESS | |
136 | ;; can't tell when a long displacement is valid. | |
137 | (define_constraint "W" | |
138 | "A register indirect memory operand." | |
139 | (and (match_code "mem") | |
140 | (match_test "REG_P (XEXP (op, 0)) | |
141 | && REG_OK_FOR_BASE_P (XEXP (op, 0))"))) |