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87ad11b0 | 1 | /* Subroutines for insn-output.c for HPPA. |
a9ac13e4 | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
3 | 2002 Free Software Foundation, Inc. | |
87ad11b0 | 4 | Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c |
5 | ||
6 | This file is part of GNU CC. | |
7 | ||
8 | GNU CC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GNU CC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GNU CC; see the file COPYING. If not, write to | |
01e379d0 | 20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
87ad11b0 | 22 | |
87ad11b0 | 23 | #include "config.h" |
b1ca791d | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
87ad11b0 | 27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
87ad11b0 | 33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "tree.h" | |
9d2d8bd6 | 36 | #include "output.h" |
a584fe8a | 37 | #include "except.h" |
32509e56 | 38 | #include "expr.h" |
d8fc4d0b | 39 | #include "optabs.h" |
40 | #include "libfuncs.h" | |
41 | #include "reload.h" | |
87ad11b0 | 42 | #include "c-tree.h" |
d7e2f694 | 43 | #include "integrate.h" |
0a893c29 | 44 | #include "function.h" |
d6f01525 | 45 | #include "obstack.h" |
b1ca791d | 46 | #include "toplev.h" |
5cb4669a | 47 | #include "ggc.h" |
611a88e1 | 48 | #include "recog.h" |
a584fe8a | 49 | #include "predict.h" |
611a88e1 | 50 | #include "tm_p.h" |
a767736d | 51 | #include "target.h" |
52 | #include "target-def.h" | |
87ad11b0 | 53 | |
bea4bad2 | 54 | static int hppa_use_dfa_pipeline_interface PARAMS ((void)); |
55 | ||
56 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE | |
57 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface | |
58 | ||
59 | static int | |
60 | hppa_use_dfa_pipeline_interface () | |
61 | { | |
62 | return 1; | |
63 | } | |
64 | ||
cde3e16c | 65 | /* Return nonzero if there is a bypass for the output of |
66 | OUT_INSN and the fp store IN_INSN. */ | |
67 | int | |
68 | hppa_fpstore_bypass_p (out_insn, in_insn) | |
69 | rtx out_insn, in_insn; | |
70 | { | |
71 | enum machine_mode store_mode; | |
72 | enum machine_mode other_mode; | |
73 | rtx set; | |
74 | ||
75 | if (recog_memoized (in_insn) < 0 | |
76 | || get_attr_type (in_insn) != TYPE_FPSTORE | |
77 | || recog_memoized (out_insn) < 0) | |
78 | return 0; | |
79 | ||
80 | store_mode = GET_MODE (SET_SRC (PATTERN (in_insn))); | |
81 | ||
82 | set = single_set (out_insn); | |
83 | if (!set) | |
84 | return 0; | |
85 | ||
86 | other_mode = GET_MODE (SET_SRC (set)); | |
87 | ||
88 | return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode)); | |
89 | } | |
90 | ||
91 | ||
cc858176 | 92 | #ifndef DO_FRAME_NOTES |
93 | #ifdef INCOMING_RETURN_ADDR_RTX | |
94 | #define DO_FRAME_NOTES 1 | |
95 | #else | |
96 | #define DO_FRAME_NOTES 0 | |
97 | #endif | |
98 | #endif | |
99 | ||
9840d99d | 100 | static inline rtx force_mode PARAMS ((enum machine_mode, rtx)); |
cc858176 | 101 | static void pa_combine_instructions PARAMS ((rtx)); |
102 | static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx)); | |
103 | static int forward_branch_p PARAMS ((rtx)); | |
104 | static int shadd_constant_p PARAMS ((int)); | |
cc858176 | 105 | static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *)); |
106 | static int compute_movstrsi_length PARAMS ((rtx)); | |
58356836 | 107 | static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int)); |
cc858176 | 108 | static void remove_useless_addtr_insns PARAMS ((rtx, int)); |
6a2c16d6 | 109 | static void store_reg PARAMS ((int, int, int)); |
a584fe8a | 110 | static void store_reg_modify PARAMS ((int, int, int)); |
6a2c16d6 | 111 | static void load_reg PARAMS ((int, int, int)); |
a584fe8a | 112 | static void set_reg_plus_d PARAMS ((int, int, int, int)); |
6988553d | 113 | static void pa_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); |
17d9b0c3 | 114 | static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); |
747af5e7 | 115 | static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int)); |
116 | static int pa_adjust_priority PARAMS ((rtx, int)); | |
117 | static int pa_issue_rate PARAMS ((void)); | |
52470889 | 118 | static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT)) |
119 | ATTRIBUTE_UNUSED; | |
7811991d | 120 | static void pa_encode_section_info PARAMS ((tree, int)); |
7b4a38a6 | 121 | static const char *pa_strip_name_encoding PARAMS ((const char *)); |
805e22b2 | 122 | static bool pa_function_ok_for_sibcall PARAMS ((tree, tree)); |
63b8cd48 | 123 | static void pa_globalize_label PARAMS ((FILE *, const char *)) |
124 | ATTRIBUTE_UNUSED; | |
eb344f43 | 125 | static void pa_asm_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, |
126 | HOST_WIDE_INT, tree)); | |
ece88821 | 127 | static void copy_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED; |
128 | static int length_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED; | |
129 | static struct deferred_plabel *get_plabel PARAMS ((const char *)) | |
130 | ATTRIBUTE_UNUSED; | |
9d3ddb8f | 131 | |
87ad11b0 | 132 | /* Save the operands last given to a compare for use when we |
133 | generate a scc or bcc insn. */ | |
87ad11b0 | 134 | rtx hppa_compare_op0, hppa_compare_op1; |
135 | enum cmp_type hppa_branch_type; | |
136 | ||
134b4858 | 137 | /* Which cpu we are scheduling for. */ |
138 | enum processor_type pa_cpu; | |
139 | ||
140 | /* String to hold which cpu we are scheduling for. */ | |
611a88e1 | 141 | const char *pa_cpu_string; |
134b4858 | 142 | |
4dc42288 | 143 | /* Which architecture we are generating code for. */ |
144 | enum architecture_type pa_arch; | |
145 | ||
146 | /* String to hold which architecture we are generating code for. */ | |
611a88e1 | 147 | const char *pa_arch_string; |
4dc42288 | 148 | |
a9960cdc | 149 | /* Counts for the number of callee-saved general and floating point |
150 | registers which were saved by the current function's prologue. */ | |
151 | static int gr_saved, fr_saved; | |
152 | ||
611a88e1 | 153 | static rtx find_addr_reg PARAMS ((rtx)); |
87ad11b0 | 154 | |
06ddb6f8 | 155 | /* Keep track of the number of bytes we have output in the CODE subspaces |
156 | during this compilation so we'll know when to emit inline long-calls. */ | |
ece88821 | 157 | unsigned long total_code_bytes; |
06ddb6f8 | 158 | |
e3f53689 | 159 | /* Variables to handle plabels that we discover are necessary at assembly |
01cc3b75 | 160 | output time. They are output after the current function. */ |
1f3233d1 | 161 | struct deferred_plabel GTY(()) |
e3f53689 | 162 | { |
163 | rtx internal_label; | |
8d0cec1a | 164 | const char *name; |
1f3233d1 | 165 | }; |
166 | static GTY((length ("n_deferred_plabels"))) struct deferred_plabel * | |
167 | deferred_plabels; | |
e11bd7e5 | 168 | static size_t n_deferred_plabels = 0; |
a767736d | 169 | \f |
170 | /* Initialize the GCC target structure. */ | |
58356836 | 171 | |
172 | #undef TARGET_ASM_ALIGNED_HI_OP | |
173 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
174 | #undef TARGET_ASM_ALIGNED_SI_OP | |
175 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
176 | #undef TARGET_ASM_ALIGNED_DI_OP | |
177 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
178 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
179 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
180 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
181 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
182 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
183 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
184 | #undef TARGET_ASM_INTEGER | |
185 | #define TARGET_ASM_INTEGER pa_assemble_integer | |
186 | ||
17d9b0c3 | 187 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
188 | #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue | |
189 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
190 | #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue | |
e3f53689 | 191 | |
747af5e7 | 192 | #undef TARGET_SCHED_ADJUST_COST |
193 | #define TARGET_SCHED_ADJUST_COST pa_adjust_cost | |
194 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
195 | #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority | |
196 | #undef TARGET_SCHED_ISSUE_RATE | |
197 | #define TARGET_SCHED_ISSUE_RATE pa_issue_rate | |
198 | ||
7811991d | 199 | #undef TARGET_ENCODE_SECTION_INFO |
200 | #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info | |
7b4a38a6 | 201 | #undef TARGET_STRIP_NAME_ENCODING |
202 | #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding | |
7811991d | 203 | |
805e22b2 | 204 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
205 | #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall | |
206 | ||
6988553d | 207 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
208 | #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk | |
eb344f43 | 209 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
210 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
6988553d | 211 | |
57e4bbfb | 212 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 213 | \f |
134b4858 | 214 | void |
215 | override_options () | |
216 | { | |
b3b62da8 | 217 | if (pa_cpu_string == NULL) |
218 | pa_cpu_string = TARGET_SCHED_DEFAULT; | |
219 | ||
220 | if (! strcmp (pa_cpu_string, "8000")) | |
221 | { | |
222 | pa_cpu_string = "8000"; | |
223 | pa_cpu = PROCESSOR_8000; | |
224 | } | |
225 | else if (! strcmp (pa_cpu_string, "7100")) | |
134b4858 | 226 | { |
227 | pa_cpu_string = "7100"; | |
228 | pa_cpu = PROCESSOR_7100; | |
229 | } | |
b3b62da8 | 230 | else if (! strcmp (pa_cpu_string, "700")) |
a87e1e15 | 231 | { |
232 | pa_cpu_string = "700"; | |
233 | pa_cpu = PROCESSOR_700; | |
234 | } | |
b3b62da8 | 235 | else if (! strcmp (pa_cpu_string, "7100LC")) |
134b4858 | 236 | { |
237 | pa_cpu_string = "7100LC"; | |
238 | pa_cpu = PROCESSOR_7100LC; | |
239 | } | |
b3b62da8 | 240 | else if (! strcmp (pa_cpu_string, "7200")) |
b4e0d953 | 241 | { |
242 | pa_cpu_string = "7200"; | |
243 | pa_cpu = PROCESSOR_7200; | |
244 | } | |
b3b62da8 | 245 | else if (! strcmp (pa_cpu_string, "7300")) |
bea4bad2 | 246 | { |
247 | pa_cpu_string = "7300"; | |
248 | pa_cpu = PROCESSOR_7300; | |
249 | } | |
134b4858 | 250 | else |
251 | { | |
bea4bad2 | 252 | warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string); |
134b4858 | 253 | } |
c7a4e712 | 254 | |
4dc42288 | 255 | /* Set the instruction set architecture. */ |
256 | if (pa_arch_string && ! strcmp (pa_arch_string, "1.0")) | |
257 | { | |
258 | pa_arch_string = "1.0"; | |
259 | pa_arch = ARCHITECTURE_10; | |
260 | target_flags &= ~(MASK_PA_11 | MASK_PA_20); | |
261 | } | |
262 | else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1")) | |
263 | { | |
264 | pa_arch_string = "1.1"; | |
265 | pa_arch = ARCHITECTURE_11; | |
266 | target_flags &= ~MASK_PA_20; | |
267 | target_flags |= MASK_PA_11; | |
268 | } | |
269 | else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0")) | |
270 | { | |
271 | pa_arch_string = "2.0"; | |
272 | pa_arch = ARCHITECTURE_20; | |
273 | target_flags |= MASK_PA_11 | MASK_PA_20; | |
274 | } | |
275 | else if (pa_arch_string) | |
276 | { | |
68435912 | 277 | warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string); |
4dc42288 | 278 | } |
279 | ||
7c5101fc | 280 | /* Unconditional branches in the delay slot are not compatible with dwarf2 |
281 | call frame information. There is no benefit in using this optimization | |
282 | on PA8000 and later processors. */ | |
283 | if (pa_cpu >= PROCESSOR_8000 | |
284 | || (! USING_SJLJ_EXCEPTIONS && flag_exceptions) | |
285 | || flag_unwind_tables) | |
286 | target_flags &= ~MASK_JUMP_IN_DELAY; | |
287 | ||
c7a4e712 | 288 | if (flag_pic && TARGET_PORTABLE_RUNTIME) |
289 | { | |
290 | warning ("PIC code generation is not supported in the portable runtime model\n"); | |
291 | } | |
292 | ||
b29897dd | 293 | if (flag_pic && TARGET_FAST_INDIRECT_CALLS) |
c7a4e712 | 294 | { |
ad87de1e | 295 | warning ("PIC code generation is not compatible with fast indirect calls\n"); |
c7a4e712 | 296 | } |
751e64a1 | 297 | |
5bd7b548 | 298 | if (! TARGET_GAS && write_symbols != NO_DEBUG) |
299 | { | |
300 | warning ("-g is only supported when using GAS on this processor,"); | |
68435912 | 301 | warning ("-g option disabled"); |
5bd7b548 | 302 | write_symbols = NO_DEBUG; |
303 | } | |
5cb4669a | 304 | |
fc44315f | 305 | /* We only support the "big PIC" model now. And we always generate PIC |
306 | code when in 64bit mode. */ | |
307 | if (flag_pic == 1 || TARGET_64BIT) | |
5e3c5739 | 308 | flag_pic = 2; |
309 | ||
58356836 | 310 | /* We can't guarantee that .dword is available for 32-bit targets. */ |
311 | if (UNITS_PER_WORD == 4) | |
312 | targetm.asm_out.aligned_op.di = NULL; | |
313 | ||
314 | /* The unaligned ops are only available when using GAS. */ | |
315 | if (!TARGET_GAS) | |
316 | { | |
317 | targetm.asm_out.unaligned_op.hi = NULL; | |
318 | targetm.asm_out.unaligned_op.si = NULL; | |
319 | targetm.asm_out.unaligned_op.di = NULL; | |
320 | } | |
134b4858 | 321 | } |
322 | ||
e911aedf | 323 | /* Return nonzero only if OP is a register of mode MODE, |
891b55b4 | 324 | or CONST0_RTX. */ |
87ad11b0 | 325 | int |
326 | reg_or_0_operand (op, mode) | |
327 | rtx op; | |
328 | enum machine_mode mode; | |
329 | { | |
891b55b4 | 330 | return (op == CONST0_RTX (mode) || register_operand (op, mode)); |
87ad11b0 | 331 | } |
332 | ||
e911aedf | 333 | /* Return nonzero if OP is suitable for use in a call to a named |
575e0eb4 | 334 | function. |
335 | ||
9dc4cbf1 | 336 | For 2.5 try to eliminate either call_operand_address or |
575e0eb4 | 337 | function_label_operand, they perform very similar functions. */ |
87ad11b0 | 338 | int |
339 | call_operand_address (op, mode) | |
340 | rtx op; | |
b1ca791d | 341 | enum machine_mode mode ATTRIBUTE_UNUSED; |
87ad11b0 | 342 | { |
2db59d96 | 343 | return (GET_MODE (op) == word_mode |
344 | && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME); | |
87ad11b0 | 345 | } |
346 | ||
6d36483b | 347 | /* Return 1 if X contains a symbolic expression. We know these |
348 | expressions will have one of a few well defined forms, so | |
347b5848 | 349 | we need only check those forms. */ |
350 | int | |
351 | symbolic_expression_p (x) | |
352 | register rtx x; | |
353 | { | |
354 | ||
6dc3b0d9 | 355 | /* Strip off any HIGH. */ |
347b5848 | 356 | if (GET_CODE (x) == HIGH) |
357 | x = XEXP (x, 0); | |
358 | ||
359 | return (symbolic_operand (x, VOIDmode)); | |
360 | } | |
361 | ||
87ad11b0 | 362 | int |
363 | symbolic_operand (op, mode) | |
364 | register rtx op; | |
b1ca791d | 365 | enum machine_mode mode ATTRIBUTE_UNUSED; |
87ad11b0 | 366 | { |
367 | switch (GET_CODE (op)) | |
368 | { | |
369 | case SYMBOL_REF: | |
370 | case LABEL_REF: | |
371 | return 1; | |
372 | case CONST: | |
373 | op = XEXP (op, 0); | |
374 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
375 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
376 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
377 | default: | |
378 | return 0; | |
379 | } | |
380 | } | |
381 | ||
382 | /* Return truth value of statement that OP is a symbolic memory | |
383 | operand of mode MODE. */ | |
384 | ||
385 | int | |
386 | symbolic_memory_operand (op, mode) | |
387 | rtx op; | |
b1ca791d | 388 | enum machine_mode mode ATTRIBUTE_UNUSED; |
87ad11b0 | 389 | { |
390 | if (GET_CODE (op) == SUBREG) | |
391 | op = SUBREG_REG (op); | |
392 | if (GET_CODE (op) != MEM) | |
393 | return 0; | |
394 | op = XEXP (op, 0); | |
395 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
396 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
397 | } | |
398 | ||
399 | /* Return 1 if the operand is either a register or a memory operand that is | |
400 | not symbolic. */ | |
401 | ||
402 | int | |
403 | reg_or_nonsymb_mem_operand (op, mode) | |
404 | register rtx op; | |
405 | enum machine_mode mode; | |
406 | { | |
407 | if (register_operand (op, mode)) | |
408 | return 1; | |
409 | ||
410 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
411 | return 1; | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
6d36483b | 416 | /* Return 1 if the operand is either a register, zero, or a memory operand |
891b55b4 | 417 | that is not symbolic. */ |
418 | ||
419 | int | |
420 | reg_or_0_or_nonsymb_mem_operand (op, mode) | |
421 | register rtx op; | |
422 | enum machine_mode mode; | |
423 | { | |
424 | if (register_operand (op, mode)) | |
425 | return 1; | |
426 | ||
427 | if (op == CONST0_RTX (mode)) | |
428 | return 1; | |
429 | ||
430 | if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode)) | |
431 | return 1; | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
d3138877 | 436 | /* Return 1 if the operand is a register operand or a non-symbolic memory |
437 | operand after reload. This predicate is used for branch patterns that | |
438 | internally handle register reloading. We need to accept non-symbolic | |
439 | memory operands after reload to ensure that the pattern is still valid | |
440 | if reload didn't find a hard register for the operand. */ | |
441 | ||
442 | int | |
443 | reg_before_reload_operand (op, mode) | |
444 | register rtx op; | |
445 | enum machine_mode mode; | |
446 | { | |
6df54749 | 447 | /* Don't accept a SUBREG since it will need a reload. */ |
448 | if (GET_CODE (op) == SUBREG) | |
449 | return 0; | |
450 | ||
d3138877 | 451 | if (register_operand (op, mode)) |
452 | return 1; | |
453 | ||
454 | if (reload_completed | |
455 | && memory_operand (op, mode) | |
456 | && ! symbolic_memory_operand (op, mode)) | |
457 | return 1; | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
7c4d3047 | 462 | /* Accept any constant that can be moved in one instruction into a |
d9d7c968 | 463 | general register. */ |
6d36483b | 464 | int |
d9d7c968 | 465 | cint_ok_for_move (intval) |
6d36483b | 466 | HOST_WIDE_INT intval; |
d9d7c968 | 467 | { |
468 | /* OK if ldo, ldil, or zdepi, can be used. */ | |
d8d5c4ff | 469 | return (CONST_OK_FOR_LETTER_P (intval, 'J') |
470 | || CONST_OK_FOR_LETTER_P (intval, 'N') | |
471 | || CONST_OK_FOR_LETTER_P (intval, 'K')); | |
d9d7c968 | 472 | } |
473 | ||
6ecdbaa1 | 474 | /* Accept anything that can be moved in one instruction into a general |
475 | register. */ | |
87ad11b0 | 476 | int |
477 | move_operand (op, mode) | |
478 | rtx op; | |
479 | enum machine_mode mode; | |
480 | { | |
481 | if (register_operand (op, mode)) | |
482 | return 1; | |
483 | ||
cc9205b8 | 484 | if (GET_CODE (op) == CONSTANT_P_RTX) |
485 | return 1; | |
486 | ||
42faba01 | 487 | if (GET_CODE (op) == CONST_INT) |
d9d7c968 | 488 | return cint_ok_for_move (INTVAL (op)); |
87ad11b0 | 489 | |
87ad11b0 | 490 | if (GET_CODE (op) == SUBREG) |
491 | op = SUBREG_REG (op); | |
492 | if (GET_CODE (op) != MEM) | |
493 | return 0; | |
494 | ||
495 | op = XEXP (op, 0); | |
27ef382d | 496 | |
2d14b1f0 | 497 | /* We consider a LO_SUM DLT reference a move_operand now since it has |
498 | been merged into the normal movsi/movdi patterns. */ | |
5d7431a3 | 499 | if (GET_CODE (op) == LO_SUM |
500 | && GET_CODE (XEXP (op, 0)) == REG | |
501 | && REG_OK_FOR_BASE_P (XEXP (op, 0)) | |
2d14b1f0 | 502 | && GET_CODE (XEXP (op, 1)) == UNSPEC |
503 | && GET_MODE (op) == Pmode) | |
504 | return 1; | |
5d7431a3 | 505 | |
27ef382d | 506 | /* Since move_operand is only used for source operands, we can always |
507 | allow scaled indexing! */ | |
822c8a6c | 508 | if (! TARGET_DISABLE_INDEXING |
509 | && GET_CODE (op) == PLUS | |
27ef382d | 510 | && ((GET_CODE (XEXP (op, 0)) == MULT |
511 | && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG | |
512 | && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT | |
4ad2b0ae | 513 | && INTVAL (XEXP (XEXP (op, 0), 1)) |
514 | == (HOST_WIDE_INT) GET_MODE_SIZE (mode) | |
27ef382d | 515 | && GET_CODE (XEXP (op, 1)) == REG) |
516 | || (GET_CODE (XEXP (op, 1)) == MULT | |
517 | &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG | |
518 | && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT | |
4ad2b0ae | 519 | && INTVAL (XEXP (XEXP (op, 1), 1)) |
520 | == (HOST_WIDE_INT) GET_MODE_SIZE (mode) | |
27ef382d | 521 | && GET_CODE (XEXP (op, 0)) == REG))) |
522 | return 1; | |
523 | ||
87ad11b0 | 524 | return memory_address_p (mode, op); |
525 | } | |
526 | ||
6ecdbaa1 | 527 | /* Accept REG and any CONST_INT that can be moved in one instruction into a |
528 | general register. */ | |
529 | int | |
530 | reg_or_cint_move_operand (op, mode) | |
531 | rtx op; | |
532 | enum machine_mode mode; | |
533 | { | |
534 | if (register_operand (op, mode)) | |
535 | return 1; | |
536 | ||
537 | if (GET_CODE (op) == CONST_INT) | |
686b848d | 538 | return cint_ok_for_move (INTVAL (op)); |
539 | ||
6ecdbaa1 | 540 | return 0; |
541 | } | |
542 | ||
87ad11b0 | 543 | int |
b4a7bf10 | 544 | pic_label_operand (op, mode) |
87ad11b0 | 545 | rtx op; |
b1ca791d | 546 | enum machine_mode mode ATTRIBUTE_UNUSED; |
87ad11b0 | 547 | { |
b4a7bf10 | 548 | if (!flag_pic) |
549 | return 0; | |
550 | ||
551 | switch (GET_CODE (op)) | |
552 | { | |
553 | case LABEL_REF: | |
554 | return 1; | |
b4a7bf10 | 555 | case CONST: |
556 | op = XEXP (op, 0); | |
3c69dc97 | 557 | return (GET_CODE (XEXP (op, 0)) == LABEL_REF |
b4a7bf10 | 558 | && GET_CODE (XEXP (op, 1)) == CONST_INT); |
559 | default: | |
560 | return 0; | |
561 | } | |
87ad11b0 | 562 | } |
563 | ||
87ad11b0 | 564 | int |
565 | fp_reg_operand (op, mode) | |
566 | rtx op; | |
b1ca791d | 567 | enum machine_mode mode ATTRIBUTE_UNUSED; |
87ad11b0 | 568 | { |
569 | return reg_renumber && FP_REG_P (op); | |
570 | } | |
d6f01525 | 571 | |
87ad11b0 | 572 | \f |
87ad11b0 | 573 | |
87ad11b0 | 574 | /* Return truth value of whether OP can be used as an operand in a |
575 | three operand arithmetic insn that accepts registers of mode MODE | |
576 | or 14-bit signed integers. */ | |
577 | int | |
578 | arith_operand (op, mode) | |
579 | rtx op; | |
580 | enum machine_mode mode; | |
581 | { | |
582 | return (register_operand (op, mode) | |
583 | || (GET_CODE (op) == CONST_INT && INT_14_BITS (op))); | |
584 | } | |
585 | ||
586 | /* Return truth value of whether OP can be used as an operand in a | |
587 | three operand arithmetic insn that accepts registers of mode MODE | |
588 | or 11-bit signed integers. */ | |
589 | int | |
590 | arith11_operand (op, mode) | |
591 | rtx op; | |
592 | enum machine_mode mode; | |
593 | { | |
594 | return (register_operand (op, mode) | |
595 | || (GET_CODE (op) == CONST_INT && INT_11_BITS (op))); | |
596 | } | |
597 | ||
2a91e628 | 598 | /* Return truth value of whether OP can be used as an operand in a |
599 | adddi3 insn. */ | |
600 | int | |
601 | adddi3_operand (op, mode) | |
602 | rtx op; | |
603 | enum machine_mode mode; | |
604 | { | |
605 | return (register_operand (op, mode) | |
606 | || (GET_CODE (op) == CONST_INT | |
607 | && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op)))); | |
608 | } | |
609 | ||
6d36483b | 610 | /* A constant integer suitable for use in a PRE_MODIFY memory |
757d4970 | 611 | reference. */ |
42faba01 | 612 | int |
613 | pre_cint_operand (op, mode) | |
614 | rtx op; | |
b1ca791d | 615 | enum machine_mode mode ATTRIBUTE_UNUSED; |
42faba01 | 616 | { |
617 | return (GET_CODE (op) == CONST_INT | |
618 | && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10); | |
619 | } | |
620 | ||
6d36483b | 621 | /* A constant integer suitable for use in a POST_MODIFY memory |
757d4970 | 622 | reference. */ |
623 | int | |
624 | post_cint_operand (op, mode) | |
625 | rtx op; | |
b1ca791d | 626 | enum machine_mode mode ATTRIBUTE_UNUSED; |
757d4970 | 627 | { |
628 | return (GET_CODE (op) == CONST_INT | |
629 | && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10); | |
630 | } | |
631 | ||
87ad11b0 | 632 | int |
633 | arith_double_operand (op, mode) | |
634 | rtx op; | |
635 | enum machine_mode mode; | |
636 | { | |
637 | return (register_operand (op, mode) | |
638 | || (GET_CODE (op) == CONST_DOUBLE | |
639 | && GET_MODE (op) == mode | |
640 | && VAL_14_BITS_P (CONST_DOUBLE_LOW (op)) | |
1fe9d310 | 641 | && ((CONST_DOUBLE_HIGH (op) >= 0) |
87ad11b0 | 642 | == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); |
643 | } | |
644 | ||
45981c0a | 645 | /* Return truth value of whether OP is an integer which fits the |
546a40bd | 646 | range constraining immediate operands in three-address insns, or |
647 | is an integer register. */ | |
648 | ||
649 | int | |
650 | ireg_or_int5_operand (op, mode) | |
651 | rtx op; | |
b1ca791d | 652 | enum machine_mode mode ATTRIBUTE_UNUSED; |
546a40bd | 653 | { |
654 | return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op)) | |
655 | || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32)); | |
656 | } | |
657 | ||
c7ae93c8 | 658 | /* Return nonzero if OP is an integer register, else return zero. */ |
659 | int | |
660 | ireg_operand (op, mode) | |
661 | rtx op; | |
662 | enum machine_mode mode ATTRIBUTE_UNUSED; | |
663 | { | |
664 | return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32); | |
665 | } | |
666 | ||
45981c0a | 667 | /* Return truth value of whether OP is an integer which fits the |
87ad11b0 | 668 | range constraining immediate operands in three-address insns. */ |
669 | ||
670 | int | |
671 | int5_operand (op, mode) | |
672 | rtx op; | |
b1ca791d | 673 | enum machine_mode mode ATTRIBUTE_UNUSED; |
87ad11b0 | 674 | { |
675 | return (GET_CODE (op) == CONST_INT && INT_5_BITS (op)); | |
676 | } | |
677 | ||
678 | int | |
679 | uint5_operand (op, mode) | |
680 | rtx op; | |
b1ca791d | 681 | enum machine_mode mode ATTRIBUTE_UNUSED; |
87ad11b0 | 682 | { |
683 | return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op)); | |
684 | } | |
685 | ||
87ad11b0 | 686 | int |
687 | int11_operand (op, mode) | |
688 | rtx op; | |
b1ca791d | 689 | enum machine_mode mode ATTRIBUTE_UNUSED; |
87ad11b0 | 690 | { |
6d36483b | 691 | return (GET_CODE (op) == CONST_INT && INT_11_BITS (op)); |
692 | } | |
693 | ||
694 | int | |
695 | uint32_operand (op, mode) | |
696 | rtx op; | |
b1ca791d | 697 | enum machine_mode mode ATTRIBUTE_UNUSED; |
6d36483b | 698 | { |
699 | #if HOST_BITS_PER_WIDE_INT > 32 | |
700 | /* All allowed constants will fit a CONST_INT. */ | |
701 | return (GET_CODE (op) == CONST_INT | |
b7d86581 | 702 | && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32)); |
6d36483b | 703 | #else |
704 | return (GET_CODE (op) == CONST_INT | |
705 | || (GET_CODE (op) == CONST_DOUBLE | |
706 | && CONST_DOUBLE_HIGH (op) == 0)); | |
707 | #endif | |
87ad11b0 | 708 | } |
709 | ||
710 | int | |
711 | arith5_operand (op, mode) | |
712 | rtx op; | |
713 | enum machine_mode mode; | |
714 | { | |
715 | return register_operand (op, mode) || int5_operand (op, mode); | |
716 | } | |
717 | ||
ea52c577 | 718 | /* True iff zdepi can be used to generate this CONST_INT. |
719 | zdepi first sign extends a 5 bit signed number to a given field | |
720 | length, then places this field anywhere in a zero. */ | |
e057641f | 721 | int |
42faba01 | 722 | zdepi_cint_p (x) |
6d36483b | 723 | unsigned HOST_WIDE_INT x; |
fad0b60f | 724 | { |
3745c59b | 725 | unsigned HOST_WIDE_INT lsb_mask, t; |
fad0b60f | 726 | |
727 | /* This might not be obvious, but it's at least fast. | |
01cc3b75 | 728 | This function is critical; we don't have the time loops would take. */ |
42faba01 | 729 | lsb_mask = x & -x; |
730 | t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1); | |
731 | /* Return true iff t is a power of two. */ | |
fad0b60f | 732 | return ((t & (t - 1)) == 0); |
733 | } | |
734 | ||
6d36483b | 735 | /* True iff depi or extru can be used to compute (reg & mask). |
736 | Accept bit pattern like these: | |
737 | 0....01....1 | |
738 | 1....10....0 | |
739 | 1..10..01..1 */ | |
e057641f | 740 | int |
42faba01 | 741 | and_mask_p (mask) |
6d36483b | 742 | unsigned HOST_WIDE_INT mask; |
e057641f | 743 | { |
744 | mask = ~mask; | |
745 | mask += mask & -mask; | |
746 | return (mask & (mask - 1)) == 0; | |
747 | } | |
748 | ||
749 | /* True iff depi or extru can be used to compute (reg & OP). */ | |
750 | int | |
751 | and_operand (op, mode) | |
752 | rtx op; | |
753 | enum machine_mode mode; | |
754 | { | |
755 | return (register_operand (op, mode) | |
42faba01 | 756 | || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op)))); |
e057641f | 757 | } |
758 | ||
759 | /* True iff depi can be used to compute (reg | MASK). */ | |
760 | int | |
761 | ior_mask_p (mask) | |
6d36483b | 762 | unsigned HOST_WIDE_INT mask; |
e057641f | 763 | { |
764 | mask += mask & -mask; | |
765 | return (mask & (mask - 1)) == 0; | |
766 | } | |
767 | ||
768 | /* True iff depi can be used to compute (reg | OP). */ | |
769 | int | |
770 | ior_operand (op, mode) | |
771 | rtx op; | |
b1ca791d | 772 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e057641f | 773 | { |
b744c8cb | 774 | return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op))); |
e057641f | 775 | } |
776 | ||
e5965947 | 777 | int |
778 | lhs_lshift_operand (op, mode) | |
779 | rtx op; | |
780 | enum machine_mode mode; | |
781 | { | |
782 | return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode); | |
783 | } | |
784 | ||
785 | /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx. | |
786 | Such values can be the left hand side x in (x << r), using the zvdepi | |
787 | instruction. */ | |
788 | int | |
789 | lhs_lshift_cint_operand (op, mode) | |
790 | rtx op; | |
b1ca791d | 791 | enum machine_mode mode ATTRIBUTE_UNUSED; |
e5965947 | 792 | { |
3745c59b | 793 | unsigned HOST_WIDE_INT x; |
e5965947 | 794 | if (GET_CODE (op) != CONST_INT) |
795 | return 0; | |
796 | x = INTVAL (op) >> 4; | |
797 | return (x & (x + 1)) == 0; | |
798 | } | |
799 | ||
9c6d4825 | 800 | int |
801 | arith32_operand (op, mode) | |
802 | rtx op; | |
803 | enum machine_mode mode; | |
804 | { | |
805 | return register_operand (op, mode) || GET_CODE (op) == CONST_INT; | |
806 | } | |
ead9285f | 807 | |
808 | int | |
809 | pc_or_label_operand (op, mode) | |
810 | rtx op; | |
b1ca791d | 811 | enum machine_mode mode ATTRIBUTE_UNUSED; |
ead9285f | 812 | { |
813 | return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF); | |
814 | } | |
87ad11b0 | 815 | \f |
816 | /* Legitimize PIC addresses. If the address is already | |
817 | position-independent, we return ORIG. Newly generated | |
818 | position-independent addresses go to REG. If we need more | |
819 | than one register, we lose. */ | |
820 | ||
821 | rtx | |
822 | legitimize_pic_address (orig, mode, reg) | |
823 | rtx orig, reg; | |
611a88e1 | 824 | enum machine_mode mode; |
87ad11b0 | 825 | { |
826 | rtx pic_ref = orig; | |
827 | ||
b090827b | 828 | /* Labels need special handling. */ |
611a88e1 | 829 | if (pic_label_operand (orig, mode)) |
b4a7bf10 | 830 | { |
2536cc16 | 831 | /* We do not want to go through the movXX expanders here since that |
832 | would create recursion. | |
833 | ||
834 | Nor do we really want to call a generator for a named pattern | |
835 | since that requires multiple patterns if we want to support | |
836 | multiple word sizes. | |
837 | ||
838 | So instead we just emit the raw set, which avoids the movXX | |
839 | expanders completely. */ | |
840 | emit_insn (gen_rtx_SET (VOIDmode, reg, orig)); | |
b4a7bf10 | 841 | current_function_uses_pic_offset_table = 1; |
842 | return reg; | |
843 | } | |
87ad11b0 | 844 | if (GET_CODE (orig) == SYMBOL_REF) |
845 | { | |
846 | if (reg == 0) | |
847 | abort (); | |
848 | ||
fc44315f | 849 | emit_move_insn (reg, |
850 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, | |
851 | gen_rtx_HIGH (word_mode, orig))); | |
852 | pic_ref | |
853 | = gen_rtx_MEM (Pmode, | |
854 | gen_rtx_LO_SUM (Pmode, reg, | |
855 | gen_rtx_UNSPEC (Pmode, | |
856 | gen_rtvec (1, orig), | |
857 | 0))); | |
7014838c | 858 | |
87ad11b0 | 859 | current_function_uses_pic_offset_table = 1; |
860 | RTX_UNCHANGING_P (pic_ref) = 1; | |
861 | emit_move_insn (reg, pic_ref); | |
862 | return reg; | |
863 | } | |
864 | else if (GET_CODE (orig) == CONST) | |
865 | { | |
57ed30e5 | 866 | rtx base; |
87ad11b0 | 867 | |
868 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
869 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
870 | return orig; | |
871 | ||
872 | if (reg == 0) | |
873 | abort (); | |
874 | ||
875 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
876 | { | |
877 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
878 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
879 | base == reg ? 0 : reg); | |
880 | } | |
881 | else abort (); | |
882 | if (GET_CODE (orig) == CONST_INT) | |
883 | { | |
42faba01 | 884 | if (INT_14_BITS (orig)) |
b244d4c7 | 885 | return plus_constant (base, INTVAL (orig)); |
87ad11b0 | 886 | orig = force_reg (Pmode, orig); |
887 | } | |
ad851752 | 888 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
87ad11b0 | 889 | /* Likewise, should we set special REG_NOTEs here? */ |
890 | } | |
891 | return pic_ref; | |
892 | } | |
893 | ||
347b5848 | 894 | /* Try machine-dependent ways of modifying an illegitimate address |
895 | to be legitimate. If we find one, return the new, valid address. | |
896 | This macro is used in only one place: `memory_address' in explow.c. | |
897 | ||
898 | OLDX is the address as it was before break_out_memory_refs was called. | |
899 | In some cases it is useful to look at this to decide what needs to be done. | |
900 | ||
901 | MODE and WIN are passed so that this macro can use | |
902 | GO_IF_LEGITIMATE_ADDRESS. | |
903 | ||
904 | It is always safe for this macro to do nothing. It exists to recognize | |
6d36483b | 905 | opportunities to optimize the output. |
347b5848 | 906 | |
907 | For the PA, transform: | |
908 | ||
909 | memory(X + <large int>) | |
910 | ||
911 | into: | |
912 | ||
913 | if (<large int> & mask) >= 16 | |
914 | Y = (<large int> & ~mask) + mask + 1 Round up. | |
915 | else | |
916 | Y = (<large int> & ~mask) Round down. | |
917 | Z = X + Y | |
918 | memory (Z + (<large int> - Y)); | |
919 | ||
6d36483b | 920 | This is for CSE to find several similar references, and only use one Z. |
347b5848 | 921 | |
922 | X can either be a SYMBOL_REF or REG, but because combine can not | |
923 | perform a 4->2 combination we do nothing for SYMBOL_REF + D where | |
924 | D will not fit in 14 bits. | |
925 | ||
926 | MODE_FLOAT references allow displacements which fit in 5 bits, so use | |
6d36483b | 927 | 0x1f as the mask. |
347b5848 | 928 | |
929 | MODE_INT references allow displacements which fit in 14 bits, so use | |
6d36483b | 930 | 0x3fff as the mask. |
347b5848 | 931 | |
932 | This relies on the fact that most mode MODE_FLOAT references will use FP | |
933 | registers and most mode MODE_INT references will use integer registers. | |
934 | (In the rare case of an FP register used in an integer MODE, we depend | |
935 | on secondary reloads to clean things up.) | |
936 | ||
937 | ||
938 | It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special | |
939 | manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed | |
01cc3b75 | 940 | addressing modes to be used). |
347b5848 | 941 | |
942 | Put X and Z into registers. Then put the entire expression into | |
943 | a register. */ | |
944 | ||
945 | rtx | |
946 | hppa_legitimize_address (x, oldx, mode) | |
b1ca791d | 947 | rtx x, oldx ATTRIBUTE_UNUSED; |
347b5848 | 948 | enum machine_mode mode; |
949 | { | |
347b5848 | 950 | rtx orig = x; |
951 | ||
b4a7bf10 | 952 | if (flag_pic) |
953 | return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); | |
954 | ||
6dc3b0d9 | 955 | /* Strip off CONST. */ |
347b5848 | 956 | if (GET_CODE (x) == CONST) |
957 | x = XEXP (x, 0); | |
958 | ||
42819d4e | 959 | /* Special case. Get the SYMBOL_REF into a register and use indexing. |
960 | That should always be safe. */ | |
961 | if (GET_CODE (x) == PLUS | |
962 | && GET_CODE (XEXP (x, 0)) == REG | |
963 | && GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
964 | { | |
440c23df | 965 | rtx reg = force_reg (Pmode, XEXP (x, 1)); |
966 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0))); | |
42819d4e | 967 | } |
968 | ||
166bf021 | 969 | /* Note we must reject symbols which represent function addresses |
970 | since the assembler/linker can't handle arithmetic on plabels. */ | |
347b5848 | 971 | if (GET_CODE (x) == PLUS |
972 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
166bf021 | 973 | && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF |
974 | && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0))) | |
347b5848 | 975 | || GET_CODE (XEXP (x, 0)) == REG)) |
976 | { | |
977 | rtx int_part, ptr_reg; | |
978 | int newoffset; | |
979 | int offset = INTVAL (XEXP (x, 1)); | |
1b6f11e2 | 980 | int mask; |
981 | ||
982 | mask = (GET_MODE_CLASS (mode) == MODE_FLOAT | |
983 | ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff); | |
347b5848 | 984 | |
6d36483b | 985 | /* Choose which way to round the offset. Round up if we |
347b5848 | 986 | are >= halfway to the next boundary. */ |
987 | if ((offset & mask) >= ((mask + 1) / 2)) | |
988 | newoffset = (offset & ~ mask) + mask + 1; | |
989 | else | |
990 | newoffset = (offset & ~ mask); | |
991 | ||
992 | /* If the newoffset will not fit in 14 bits (ldo), then | |
993 | handling this would take 4 or 5 instructions (2 to load | |
994 | the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to | |
995 | add the new offset and the SYMBOL_REF.) Combine can | |
996 | not handle 4->2 or 5->2 combinations, so do not create | |
997 | them. */ | |
998 | if (! VAL_14_BITS_P (newoffset) | |
999 | && GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
1000 | { | |
7014838c | 1001 | rtx const_part = plus_constant (XEXP (x, 0), newoffset); |
347b5848 | 1002 | rtx tmp_reg |
339613b4 | 1003 | = force_reg (Pmode, |
ad851752 | 1004 | gen_rtx_HIGH (Pmode, const_part)); |
347b5848 | 1005 | ptr_reg |
339613b4 | 1006 | = force_reg (Pmode, |
7014838c | 1007 | gen_rtx_LO_SUM (Pmode, |
1008 | tmp_reg, const_part)); | |
347b5848 | 1009 | } |
1010 | else | |
1011 | { | |
1012 | if (! VAL_14_BITS_P (newoffset)) | |
339613b4 | 1013 | int_part = force_reg (Pmode, GEN_INT (newoffset)); |
347b5848 | 1014 | else |
1015 | int_part = GEN_INT (newoffset); | |
1016 | ||
339613b4 | 1017 | ptr_reg = force_reg (Pmode, |
ad851752 | 1018 | gen_rtx_PLUS (Pmode, |
1019 | force_reg (Pmode, XEXP (x, 0)), | |
1020 | int_part)); | |
347b5848 | 1021 | } |
1022 | return plus_constant (ptr_reg, offset - newoffset); | |
1023 | } | |
45f1285a | 1024 | |
5115683e | 1025 | /* Handle (plus (mult (a) (shadd_constant)) (b)). */ |
45f1285a | 1026 | |
347b5848 | 1027 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT |
1028 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
45f1285a | 1029 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))) |
1030 | && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o' | |
1031 | || GET_CODE (XEXP (x, 1)) == SUBREG) | |
1032 | && GET_CODE (XEXP (x, 1)) != CONST) | |
347b5848 | 1033 | { |
1034 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1035 | rtx reg1, reg2; | |
5115683e | 1036 | |
1037 | reg1 = XEXP (x, 1); | |
1038 | if (GET_CODE (reg1) != REG) | |
1039 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1040 | ||
1041 | reg2 = XEXP (XEXP (x, 0), 0); | |
1042 | if (GET_CODE (reg2) != REG) | |
1043 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1044 | ||
ad851752 | 1045 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1046 | gen_rtx_MULT (Pmode, |
1047 | reg2, | |
1048 | GEN_INT (val)), | |
ad851752 | 1049 | reg1)); |
347b5848 | 1050 | } |
45f1285a | 1051 | |
00a87639 | 1052 | /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)). |
1053 | ||
1054 | Only do so for floating point modes since this is more speculative | |
1055 | and we lose if it's an integer store. */ | |
5115683e | 1056 | if (GET_CODE (x) == PLUS |
00a87639 | 1057 | && GET_CODE (XEXP (x, 0)) == PLUS |
1058 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
1059 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
5115683e | 1060 | && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) |
1061 | && (mode == SFmode || mode == DFmode)) | |
00a87639 | 1062 | { |
5115683e | 1063 | |
1064 | /* First, try and figure out what to use as a base register. */ | |
1065 | rtx reg1, reg2, base, idx, orig_base; | |
1066 | ||
1067 | reg1 = XEXP (XEXP (x, 0), 1); | |
1068 | reg2 = XEXP (x, 1); | |
1069 | base = NULL_RTX; | |
1070 | idx = NULL_RTX; | |
1071 | ||
1072 | /* Make sure they're both regs. If one was a SYMBOL_REF [+ const], | |
e61a0a7f | 1073 | then emit_move_sequence will turn on REG_POINTER so we'll know |
1074 | it's a base register below. */ | |
5115683e | 1075 | if (GET_CODE (reg1) != REG) |
1076 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1077 | ||
1078 | if (GET_CODE (reg2) != REG) | |
1079 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1080 | ||
1081 | /* Figure out what the base and index are. */ | |
9840d99d | 1082 | |
5115683e | 1083 | if (GET_CODE (reg1) == REG |
e61a0a7f | 1084 | && REG_POINTER (reg1)) |
5115683e | 1085 | { |
1086 | base = reg1; | |
1087 | orig_base = XEXP (XEXP (x, 0), 1); | |
ad851752 | 1088 | idx = gen_rtx_PLUS (Pmode, |
1089 | gen_rtx_MULT (Pmode, | |
1090 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
1091 | XEXP (XEXP (XEXP (x, 0), 0), 1)), | |
1092 | XEXP (x, 1)); | |
5115683e | 1093 | } |
1094 | else if (GET_CODE (reg2) == REG | |
e61a0a7f | 1095 | && REG_POINTER (reg2)) |
5115683e | 1096 | { |
1097 | base = reg2; | |
1098 | orig_base = XEXP (x, 1); | |
1099 | idx = XEXP (x, 0); | |
1100 | } | |
1101 | ||
1102 | if (base == 0) | |
21f3ee9c | 1103 | return orig; |
5115683e | 1104 | |
1105 | /* If the index adds a large constant, try to scale the | |
1106 | constant so that it can be loaded with only one insn. */ | |
1107 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1108 | && VAL_14_BITS_P (INTVAL (XEXP (idx, 1)) | |
1109 | / INTVAL (XEXP (XEXP (idx, 0), 1))) | |
1110 | && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0) | |
1111 | { | |
1112 | /* Divide the CONST_INT by the scale factor, then add it to A. */ | |
1113 | int val = INTVAL (XEXP (idx, 1)); | |
1114 | ||
1115 | val /= INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1116 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1117 | if (GET_CODE (reg1) != REG) | |
1118 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1119 | ||
ad851752 | 1120 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val))); |
5115683e | 1121 | |
1122 | /* We can now generate a simple scaled indexed address. */ | |
7014838c | 1123 | return |
1124 | force_reg | |
1125 | (Pmode, gen_rtx_PLUS (Pmode, | |
1126 | gen_rtx_MULT (Pmode, reg1, | |
1127 | XEXP (XEXP (idx, 0), 1)), | |
1128 | base)); | |
5115683e | 1129 | } |
1130 | ||
1131 | /* If B + C is still a valid base register, then add them. */ | |
1132 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1133 | && INTVAL (XEXP (idx, 1)) <= 4096 | |
1134 | && INTVAL (XEXP (idx, 1)) >= -4096) | |
1135 | { | |
1136 | int val = INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1137 | rtx reg1, reg2; | |
1138 | ||
ad851752 | 1139 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1))); |
5115683e | 1140 | |
1141 | reg2 = XEXP (XEXP (idx, 0), 0); | |
1142 | if (GET_CODE (reg2) != CONST_INT) | |
1143 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1144 | ||
ad851752 | 1145 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1146 | gen_rtx_MULT (Pmode, |
1147 | reg2, | |
ad851752 | 1148 | GEN_INT (val)), |
1149 | reg1)); | |
5115683e | 1150 | } |
1151 | ||
1152 | /* Get the index into a register, then add the base + index and | |
1153 | return a register holding the result. */ | |
1154 | ||
1155 | /* First get A into a register. */ | |
1156 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1157 | if (GET_CODE (reg1) != REG) | |
1158 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1159 | ||
1160 | /* And get B into a register. */ | |
1161 | reg2 = XEXP (idx, 1); | |
1162 | if (GET_CODE (reg2) != REG) | |
1163 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1164 | ||
ad851752 | 1165 | reg1 = force_reg (Pmode, |
1166 | gen_rtx_PLUS (Pmode, | |
1167 | gen_rtx_MULT (Pmode, reg1, | |
1168 | XEXP (XEXP (idx, 0), 1)), | |
1169 | reg2)); | |
5115683e | 1170 | |
1171 | /* Add the result to our base register and return. */ | |
ad851752 | 1172 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1)); |
9840d99d | 1173 | |
00a87639 | 1174 | } |
1175 | ||
6d36483b | 1176 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
fb5390c1 | 1177 | special handling to avoid creating an indexed memory address |
1178 | with x-100000 as the base. | |
9840d99d | 1179 | |
fb5390c1 | 1180 | If the constant part is small enough, then it's still safe because |
1181 | there is a guard page at the beginning and end of the data segment. | |
1182 | ||
1183 | Scaled references are common enough that we want to try and rearrange the | |
1184 | terms so that we can use indexing for these addresses too. Only | |
00a87639 | 1185 | do the optimization for floatint point modes. */ |
45f1285a | 1186 | |
fb5390c1 | 1187 | if (GET_CODE (x) == PLUS |
1188 | && symbolic_expression_p (XEXP (x, 1))) | |
45f1285a | 1189 | { |
1190 | /* Ugly. We modify things here so that the address offset specified | |
1191 | by the index expression is computed first, then added to x to form | |
fb5390c1 | 1192 | the entire address. */ |
45f1285a | 1193 | |
00a87639 | 1194 | rtx regx1, regx2, regy1, regy2, y; |
45f1285a | 1195 | |
1196 | /* Strip off any CONST. */ | |
1197 | y = XEXP (x, 1); | |
1198 | if (GET_CODE (y) == CONST) | |
1199 | y = XEXP (y, 0); | |
1200 | ||
7ee96d6e | 1201 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1202 | { | |
00a87639 | 1203 | /* See if this looks like |
1204 | (plus (mult (reg) (shadd_const)) | |
1205 | (const (plus (symbol_ref) (const_int)))) | |
1206 | ||
5115683e | 1207 | Where const_int is small. In that case the const |
9840d99d | 1208 | expression is a valid pointer for indexing. |
5115683e | 1209 | |
1210 | If const_int is big, but can be divided evenly by shadd_const | |
1211 | and added to (reg). This allows more scaled indexed addresses. */ | |
1212 | if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1213 | && GET_CODE (XEXP (x, 0)) == MULT | |
00a87639 | 1214 | && GET_CODE (XEXP (y, 1)) == CONST_INT |
5115683e | 1215 | && INTVAL (XEXP (y, 1)) >= -4096 |
1216 | && INTVAL (XEXP (y, 1)) <= 4095 | |
1217 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1218 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
1219 | { | |
1220 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1221 | rtx reg1, reg2; | |
1222 | ||
1223 | reg1 = XEXP (x, 1); | |
1224 | if (GET_CODE (reg1) != REG) | |
1225 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1226 | ||
1227 | reg2 = XEXP (XEXP (x, 0), 0); | |
1228 | if (GET_CODE (reg2) != REG) | |
1229 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1230 | ||
ad851752 | 1231 | return force_reg (Pmode, |
1232 | gen_rtx_PLUS (Pmode, | |
7014838c | 1233 | gen_rtx_MULT (Pmode, |
1234 | reg2, | |
ad851752 | 1235 | GEN_INT (val)), |
7014838c | 1236 | reg1)); |
5115683e | 1237 | } |
1238 | else if ((mode == DFmode || mode == SFmode) | |
1239 | && GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1240 | && GET_CODE (XEXP (x, 0)) == MULT | |
1241 | && GET_CODE (XEXP (y, 1)) == CONST_INT | |
1242 | && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0 | |
1243 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1244 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
00a87639 | 1245 | { |
1246 | regx1 | |
1247 | = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1)) | |
1248 | / INTVAL (XEXP (XEXP (x, 0), 1)))); | |
1249 | regx2 = XEXP (XEXP (x, 0), 0); | |
1250 | if (GET_CODE (regx2) != REG) | |
1251 | regx2 = force_reg (Pmode, force_operand (regx2, 0)); | |
ad851752 | 1252 | regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1253 | regx2, regx1)); | |
7014838c | 1254 | return |
1255 | force_reg (Pmode, | |
1256 | gen_rtx_PLUS (Pmode, | |
1257 | gen_rtx_MULT (Pmode, regx2, | |
1258 | XEXP (XEXP (x, 0), 1)), | |
1259 | force_reg (Pmode, XEXP (y, 0)))); | |
00a87639 | 1260 | } |
fb5390c1 | 1261 | else if (GET_CODE (XEXP (y, 1)) == CONST_INT |
1262 | && INTVAL (XEXP (y, 1)) >= -4096 | |
1263 | && INTVAL (XEXP (y, 1)) <= 4095) | |
1264 | { | |
1265 | /* This is safe because of the guard page at the | |
1266 | beginning and end of the data space. Just | |
1267 | return the original address. */ | |
1268 | return orig; | |
1269 | } | |
00a87639 | 1270 | else |
1271 | { | |
1272 | /* Doesn't look like one we can optimize. */ | |
1273 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1274 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1275 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1276 | regx1 = force_reg (Pmode, | |
ad851752 | 1277 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1278 | regx1, regy2)); | |
1279 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); | |
00a87639 | 1280 | } |
7ee96d6e | 1281 | } |
45f1285a | 1282 | } |
1283 | ||
347b5848 | 1284 | return orig; |
1285 | } | |
1286 | ||
87ad11b0 | 1287 | /* For the HPPA, REG and REG+CONST is cost 0 |
1288 | and addresses involving symbolic constants are cost 2. | |
1289 | ||
1290 | PIC addresses are very expensive. | |
1291 | ||
1292 | It is no coincidence that this has the same structure | |
1293 | as GO_IF_LEGITIMATE_ADDRESS. */ | |
1294 | int | |
1295 | hppa_address_cost (X) | |
1296 | rtx X; | |
1297 | { | |
1298 | if (GET_CODE (X) == PLUS) | |
1299 | return 1; | |
1300 | else if (GET_CODE (X) == LO_SUM) | |
1301 | return 1; | |
1302 | else if (GET_CODE (X) == HIGH) | |
1303 | return 2; | |
1304 | return 4; | |
1305 | } | |
1306 | ||
9840d99d | 1307 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a |
1308 | new rtx with the correct mode. */ | |
1309 | static inline rtx | |
1310 | force_mode (mode, orig) | |
1311 | enum machine_mode mode; | |
1312 | rtx orig; | |
1313 | { | |
1314 | if (mode == GET_MODE (orig)) | |
1315 | return orig; | |
1316 | ||
1317 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
1318 | abort (); | |
1319 | ||
1320 | return gen_rtx_REG (mode, REGNO (orig)); | |
1321 | } | |
1322 | ||
87ad11b0 | 1323 | /* Emit insns to move operands[1] into operands[0]. |
1324 | ||
1325 | Return 1 if we have written out everything that needs to be done to | |
1326 | do the move. Otherwise, return 0 and the caller will emit the move | |
9840d99d | 1327 | normally. |
f756078b | 1328 | |
1329 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
1330 | will be used. This routine is resposible for creating a new copy | |
1331 | of SCRATCH_REG in the proper mode. */ | |
87ad11b0 | 1332 | |
1333 | int | |
d6f01525 | 1334 | emit_move_sequence (operands, mode, scratch_reg) |
87ad11b0 | 1335 | rtx *operands; |
1336 | enum machine_mode mode; | |
d6f01525 | 1337 | rtx scratch_reg; |
87ad11b0 | 1338 | { |
1339 | register rtx operand0 = operands[0]; | |
1340 | register rtx operand1 = operands[1]; | |
4a155b0f | 1341 | register rtx tem; |
87ad11b0 | 1342 | |
2d4dc8d2 | 1343 | if (scratch_reg |
1344 | && reload_in_progress && GET_CODE (operand0) == REG | |
d1e2bb73 | 1345 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) |
1346 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2d4dc8d2 | 1347 | else if (scratch_reg |
1348 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
d1e2bb73 | 1349 | && GET_CODE (SUBREG_REG (operand0)) == REG |
1350 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1351 | { |
701e46d0 | 1352 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1353 | the code which tracks sets/uses for delete_output_reload. */ |
1354 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
1355 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
701e46d0 | 1356 | SUBREG_BYTE (operand0)); |
e00b80b2 | 1357 | operand0 = alter_subreg (&temp); |
a3afad75 | 1358 | } |
d1e2bb73 | 1359 | |
2d4dc8d2 | 1360 | if (scratch_reg |
1361 | && reload_in_progress && GET_CODE (operand1) == REG | |
d1e2bb73 | 1362 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) |
1363 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2d4dc8d2 | 1364 | else if (scratch_reg |
1365 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
d1e2bb73 | 1366 | && GET_CODE (SUBREG_REG (operand1)) == REG |
1367 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1368 | { |
701e46d0 | 1369 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1370 | the code which tracks sets/uses for delete_output_reload. */ |
1371 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
1372 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
701e46d0 | 1373 | SUBREG_BYTE (operand1)); |
e00b80b2 | 1374 | operand1 = alter_subreg (&temp); |
a3afad75 | 1375 | } |
d1e2bb73 | 1376 | |
2d4dc8d2 | 1377 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM |
4a155b0f | 1378 | && ((tem = find_replacement (&XEXP (operand0, 0))) |
1379 | != XEXP (operand0, 0))) | |
ad851752 | 1380 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); |
2d4dc8d2 | 1381 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM |
4a155b0f | 1382 | && ((tem = find_replacement (&XEXP (operand1, 0))) |
1383 | != XEXP (operand1, 0))) | |
ad851752 | 1384 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); |
4a155b0f | 1385 | |
e8fdbafa | 1386 | /* Handle secondary reloads for loads/stores of FP registers from |
9840d99d | 1387 | REG+D addresses where D does not fit in 5 bits, including |
42819d4e | 1388 | (subreg (mem (addr))) cases. */ |
d6f01525 | 1389 | if (fp_reg_operand (operand0, mode) |
6b1c36c2 | 1390 | && ((GET_CODE (operand1) == MEM |
1391 | && ! memory_address_p (DFmode, XEXP (operand1, 0))) | |
1392 | || ((GET_CODE (operand1) == SUBREG | |
1393 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
1394 | && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))) | |
d6f01525 | 1395 | && scratch_reg) |
1396 | { | |
6b1c36c2 | 1397 | if (GET_CODE (operand1) == SUBREG) |
1398 | operand1 = XEXP (operand1, 0); | |
1399 | ||
f756078b | 1400 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1401 | it in WORD_MODE regardless of what mode it was originally given | |
1402 | to us. */ | |
9840d99d | 1403 | scratch_reg = force_mode (word_mode, scratch_reg); |
7ee39d73 | 1404 | |
1405 | /* D might not fit in 14 bits either; for such cases load D into | |
1406 | scratch reg. */ | |
440c23df | 1407 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) |
7ee39d73 | 1408 | { |
1409 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
ad851752 | 1410 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), |
440c23df | 1411 | Pmode, |
ad851752 | 1412 | XEXP (XEXP (operand1, 0), 0), |
1413 | scratch_reg)); | |
7ee39d73 | 1414 | } |
1415 | else | |
1416 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
7014838c | 1417 | emit_insn (gen_rtx_SET (VOIDmode, operand0, |
1418 | gen_rtx_MEM (mode, scratch_reg))); | |
d6f01525 | 1419 | return 1; |
1420 | } | |
1421 | else if (fp_reg_operand (operand1, mode) | |
6b1c36c2 | 1422 | && ((GET_CODE (operand0) == MEM |
1423 | && ! memory_address_p (DFmode, XEXP (operand0, 0))) | |
1424 | || ((GET_CODE (operand0) == SUBREG) | |
1425 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
1426 | && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0)))) | |
d6f01525 | 1427 | && scratch_reg) |
1428 | { | |
6b1c36c2 | 1429 | if (GET_CODE (operand0) == SUBREG) |
1430 | operand0 = XEXP (operand0, 0); | |
1431 | ||
f756078b | 1432 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1433 | it in WORD_MODE regardless of what mode it was originally given | |
1434 | to us. */ | |
9840d99d | 1435 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1436 | |
7ee39d73 | 1437 | /* D might not fit in 14 bits either; for such cases load D into |
1438 | scratch reg. */ | |
440c23df | 1439 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) |
7ee39d73 | 1440 | { |
1441 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
ad851752 | 1442 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, |
1443 | 0)), | |
440c23df | 1444 | Pmode, |
ad851752 | 1445 | XEXP (XEXP (operand0, 0), |
1446 | 0), | |
1447 | scratch_reg)); | |
7ee39d73 | 1448 | } |
1449 | else | |
1450 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
ad851752 | 1451 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), |
1452 | operand1)); | |
d6f01525 | 1453 | return 1; |
1454 | } | |
753bd06a | 1455 | /* Handle secondary reloads for loads of FP registers from constant |
1456 | expressions by forcing the constant into memory. | |
1457 | ||
6d36483b | 1458 | use scratch_reg to hold the address of the memory location. |
753bd06a | 1459 | |
9dc4cbf1 | 1460 | The proper fix is to change PREFERRED_RELOAD_CLASS to return |
87fcb603 | 1461 | NO_REGS when presented with a const_int and a register class |
753bd06a | 1462 | containing only FP registers. Doing so unfortunately creates |
1463 | more problems than it solves. Fix this for 2.5. */ | |
1464 | else if (fp_reg_operand (operand0, mode) | |
1465 | && CONSTANT_P (operand1) | |
1466 | && scratch_reg) | |
1467 | { | |
1468 | rtx xoperands[2]; | |
1469 | ||
f756078b | 1470 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1471 | it in WORD_MODE regardless of what mode it was originally given | |
1472 | to us. */ | |
9840d99d | 1473 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1474 | |
753bd06a | 1475 | /* Force the constant into memory and put the address of the |
1476 | memory location into scratch_reg. */ | |
1477 | xoperands[0] = scratch_reg; | |
1478 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
8f258b49 | 1479 | emit_move_sequence (xoperands, Pmode, 0); |
753bd06a | 1480 | |
1481 | /* Now load the destination register. */ | |
7014838c | 1482 | emit_insn (gen_rtx_SET (mode, operand0, |
1483 | gen_rtx_MEM (mode, scratch_reg))); | |
753bd06a | 1484 | return 1; |
1485 | } | |
e8fdbafa | 1486 | /* Handle secondary reloads for SAR. These occur when trying to load |
2a170404 | 1487 | the SAR from memory, FP register, or with a constant. */ |
e8fdbafa | 1488 | else if (GET_CODE (operand0) == REG |
2a170404 | 1489 | && REGNO (operand0) < FIRST_PSEUDO_REGISTER |
e8fdbafa | 1490 | && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS |
1491 | && (GET_CODE (operand1) == MEM | |
7d43e0f7 | 1492 | || GET_CODE (operand1) == CONST_INT |
e8fdbafa | 1493 | || (GET_CODE (operand1) == REG |
1494 | && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))) | |
1495 | && scratch_reg) | |
1496 | { | |
7eac600c | 1497 | /* D might not fit in 14 bits either; for such cases load D into |
1498 | scratch reg. */ | |
1499 | if (GET_CODE (operand1) == MEM | |
440c23df | 1500 | && !memory_address_p (Pmode, XEXP (operand1, 0))) |
7eac600c | 1501 | { |
fc4d127d | 1502 | /* We are reloading the address into the scratch register, so we |
1503 | want to make sure the scratch register is a full register. */ | |
9840d99d | 1504 | scratch_reg = force_mode (word_mode, scratch_reg); |
fc4d127d | 1505 | |
9840d99d | 1506 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); |
ad851752 | 1507 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, |
1508 | 0)), | |
440c23df | 1509 | Pmode, |
ad851752 | 1510 | XEXP (XEXP (operand1, 0), |
1511 | 0), | |
1512 | scratch_reg)); | |
fc4d127d | 1513 | |
1514 | /* Now we are going to load the scratch register from memory, | |
1515 | we want to load it in the same width as the original MEM, | |
1516 | which must be the same as the width of the ultimate destination, | |
1517 | OPERAND0. */ | |
9840d99d | 1518 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1519 | ||
fc4d127d | 1520 | emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0), |
ad851752 | 1521 | scratch_reg)); |
7eac600c | 1522 | } |
1523 | else | |
fc4d127d | 1524 | { |
1525 | /* We want to load the scratch register using the same mode as | |
1526 | the ultimate destination. */ | |
9840d99d | 1527 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1528 | ||
fc4d127d | 1529 | emit_move_insn (scratch_reg, operand1); |
1530 | } | |
1531 | ||
1532 | /* And emit the insn to set the ultimate destination. We know that | |
1533 | the scratch register has the same mode as the destination at this | |
1534 | point. */ | |
e8fdbafa | 1535 | emit_move_insn (operand0, scratch_reg); |
1536 | return 1; | |
1537 | } | |
d6f01525 | 1538 | /* Handle most common case: storing into a register. */ |
1539 | else if (register_operand (operand0, mode)) | |
87ad11b0 | 1540 | { |
1541 | if (register_operand (operand1, mode) | |
93f6e1c7 | 1542 | || (GET_CODE (operand1) == CONST_INT |
1543 | && cint_ok_for_move (INTVAL (operand1))) | |
891b55b4 | 1544 | || (operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1545 | || (GET_CODE (operand1) == HIGH |
df0651dc | 1546 | && !symbolic_operand (XEXP (operand1, 0), VOIDmode)) |
87ad11b0 | 1547 | /* Only `general_operands' can come here, so MEM is ok. */ |
1548 | || GET_CODE (operand1) == MEM) | |
1549 | { | |
1550 | /* Run this case quickly. */ | |
ad851752 | 1551 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1552 | return 1; |
1553 | } | |
1554 | } | |
1555 | else if (GET_CODE (operand0) == MEM) | |
1556 | { | |
85eb4c6e | 1557 | if (mode == DFmode && operand1 == CONST0_RTX (mode) |
1558 | && !(reload_in_progress || reload_completed)) | |
1559 | { | |
1560 | rtx temp = gen_reg_rtx (DFmode); | |
1561 | ||
ad851752 | 1562 | emit_insn (gen_rtx_SET (VOIDmode, temp, operand1)); |
1563 | emit_insn (gen_rtx_SET (VOIDmode, operand0, temp)); | |
85eb4c6e | 1564 | return 1; |
1565 | } | |
891b55b4 | 1566 | if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1567 | { |
1568 | /* Run this case quickly. */ | |
ad851752 | 1569 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1570 | return 1; |
1571 | } | |
2ff4bf8d | 1572 | if (! (reload_in_progress || reload_completed)) |
87ad11b0 | 1573 | { |
1574 | operands[0] = validize_mem (operand0); | |
1575 | operands[1] = operand1 = force_reg (mode, operand1); | |
1576 | } | |
1577 | } | |
1578 | ||
37a75d53 | 1579 | /* Simplify the source if we need to. |
1580 | Note we do have to handle function labels here, even though we do | |
1581 | not consider them legitimate constants. Loop optimizations can | |
bea60f66 | 1582 | call the emit_move_xxx with one as a source. */ |
57ed30e5 | 1583 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) |
37a75d53 | 1584 | || function_label_operand (operand1, mode) |
2ee034bc | 1585 | || (GET_CODE (operand1) == HIGH |
63882853 | 1586 | && symbolic_operand (XEXP (operand1, 0), mode))) |
87ad11b0 | 1587 | { |
2ee034bc | 1588 | int ishighonly = 0; |
1589 | ||
1590 | if (GET_CODE (operand1) == HIGH) | |
1591 | { | |
1592 | ishighonly = 1; | |
1593 | operand1 = XEXP (operand1, 0); | |
1594 | } | |
87ad11b0 | 1595 | if (symbolic_operand (operand1, mode)) |
1596 | { | |
005a7dd0 | 1597 | /* Argh. The assembler and linker can't handle arithmetic |
81653f9b | 1598 | involving plabels. |
005a7dd0 | 1599 | |
81653f9b | 1600 | So we force the plabel into memory, load operand0 from |
1601 | the memory location, then add in the constant part. */ | |
37a75d53 | 1602 | if ((GET_CODE (operand1) == CONST |
1603 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1604 | && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode)) | |
1605 | || function_label_operand (operand1, mode)) | |
005a7dd0 | 1606 | { |
b3d569a0 | 1607 | rtx temp, const_part; |
81653f9b | 1608 | |
1609 | /* Figure out what (if any) scratch register to use. */ | |
1610 | if (reload_in_progress || reload_completed) | |
f756078b | 1611 | { |
1612 | scratch_reg = scratch_reg ? scratch_reg : operand0; | |
1613 | /* SCRATCH_REG will hold an address and maybe the actual | |
1614 | data. We want it in WORD_MODE regardless of what mode it | |
1615 | was originally given to us. */ | |
9840d99d | 1616 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1617 | } |
81653f9b | 1618 | else if (flag_pic) |
1619 | scratch_reg = gen_reg_rtx (Pmode); | |
1620 | ||
37a75d53 | 1621 | if (GET_CODE (operand1) == CONST) |
1622 | { | |
1623 | /* Save away the constant part of the expression. */ | |
1624 | const_part = XEXP (XEXP (operand1, 0), 1); | |
1625 | if (GET_CODE (const_part) != CONST_INT) | |
1626 | abort (); | |
1627 | ||
1628 | /* Force the function label into memory. */ | |
1629 | temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0)); | |
1630 | } | |
1631 | else | |
1632 | { | |
1633 | /* No constant part. */ | |
1634 | const_part = NULL_RTX; | |
005a7dd0 | 1635 | |
37a75d53 | 1636 | /* Force the function label into memory. */ |
1637 | temp = force_const_mem (mode, operand1); | |
1638 | } | |
9840d99d | 1639 | |
81653f9b | 1640 | |
1641 | /* Get the address of the memory location. PIC-ify it if | |
1642 | necessary. */ | |
1643 | temp = XEXP (temp, 0); | |
1644 | if (flag_pic) | |
1645 | temp = legitimize_pic_address (temp, mode, scratch_reg); | |
1646 | ||
1647 | /* Put the address of the memory location into our destination | |
1648 | register. */ | |
1649 | operands[1] = temp; | |
1650 | emit_move_sequence (operands, mode, scratch_reg); | |
1651 | ||
1652 | /* Now load from the memory location into our destination | |
1653 | register. */ | |
ad851752 | 1654 | operands[1] = gen_rtx_MEM (Pmode, operands[0]); |
81653f9b | 1655 | emit_move_sequence (operands, mode, scratch_reg); |
1656 | ||
1657 | /* And add back in the constant part. */ | |
37a75d53 | 1658 | if (const_part != NULL_RTX) |
1659 | expand_inc (operand0, const_part); | |
81653f9b | 1660 | |
1661 | return 1; | |
005a7dd0 | 1662 | } |
1663 | ||
87ad11b0 | 1664 | if (flag_pic) |
1665 | { | |
2ff4bf8d | 1666 | rtx temp; |
1667 | ||
1668 | if (reload_in_progress || reload_completed) | |
f756078b | 1669 | { |
1670 | temp = scratch_reg ? scratch_reg : operand0; | |
1671 | /* TEMP will hold an address and maybe the actual | |
1672 | data. We want it in WORD_MODE regardless of what mode it | |
1673 | was originally given to us. */ | |
9840d99d | 1674 | temp = force_mode (word_mode, temp); |
f756078b | 1675 | } |
2ff4bf8d | 1676 | else |
1677 | temp = gen_reg_rtx (Pmode); | |
6d36483b | 1678 | |
81653f9b | 1679 | /* (const (plus (symbol) (const_int))) must be forced to |
1680 | memory during/after reload if the const_int will not fit | |
1681 | in 14 bits. */ | |
1682 | if (GET_CODE (operand1) == CONST | |
96b86ab6 | 1683 | && GET_CODE (XEXP (operand1, 0)) == PLUS |
1684 | && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT | |
1685 | && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)) | |
1686 | && (reload_completed || reload_in_progress) | |
1687 | && flag_pic) | |
1688 | { | |
1689 | operands[1] = force_const_mem (mode, operand1); | |
1690 | operands[1] = legitimize_pic_address (XEXP (operands[1], 0), | |
1691 | mode, temp); | |
1692 | emit_move_sequence (operands, mode, temp); | |
1693 | } | |
005a7dd0 | 1694 | else |
1695 | { | |
1696 | operands[1] = legitimize_pic_address (operand1, mode, temp); | |
ad851752 | 1697 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1])); |
005a7dd0 | 1698 | } |
87ad11b0 | 1699 | } |
b4a7bf10 | 1700 | /* On the HPPA, references to data space are supposed to use dp, |
1701 | register 27, but showing it in the RTL inhibits various cse | |
1702 | and loop optimizations. */ | |
6d36483b | 1703 | else |
87ad11b0 | 1704 | { |
005a7dd0 | 1705 | rtx temp, set; |
2ee034bc | 1706 | |
6d36483b | 1707 | if (reload_in_progress || reload_completed) |
f756078b | 1708 | { |
1709 | temp = scratch_reg ? scratch_reg : operand0; | |
1710 | /* TEMP will hold an address and maybe the actual | |
1711 | data. We want it in WORD_MODE regardless of what mode it | |
1712 | was originally given to us. */ | |
9840d99d | 1713 | temp = force_mode (word_mode, temp); |
f756078b | 1714 | } |
2ee034bc | 1715 | else |
1716 | temp = gen_reg_rtx (mode); | |
1717 | ||
42819d4e | 1718 | /* Loading a SYMBOL_REF into a register makes that register |
9840d99d | 1719 | safe to be used as the base in an indexed address. |
42819d4e | 1720 | |
1721 | Don't mark hard registers though. That loses. */ | |
47a61b79 | 1722 | if (GET_CODE (operand0) == REG |
1723 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
e61a0a7f | 1724 | REG_POINTER (operand0) = 1; |
42819d4e | 1725 | if (REGNO (temp) >= FIRST_PSEUDO_REGISTER) |
e61a0a7f | 1726 | REG_POINTER (temp) = 1; |
2ee034bc | 1727 | if (ishighonly) |
ad851752 | 1728 | set = gen_rtx_SET (mode, operand0, temp); |
2ee034bc | 1729 | else |
7014838c | 1730 | set = gen_rtx_SET (VOIDmode, |
1731 | operand0, | |
ad851752 | 1732 | gen_rtx_LO_SUM (mode, temp, operand1)); |
6d36483b | 1733 | |
ad851752 | 1734 | emit_insn (gen_rtx_SET (VOIDmode, |
1735 | temp, | |
1736 | gen_rtx_HIGH (mode, operand1))); | |
d2498717 | 1737 | emit_insn (set); |
166bf021 | 1738 | |
87ad11b0 | 1739 | } |
2ee034bc | 1740 | return 1; |
87ad11b0 | 1741 | } |
42faba01 | 1742 | else if (GET_CODE (operand1) != CONST_INT |
8c8ec4de | 1743 | || ! cint_ok_for_move (INTVAL (operand1))) |
87ad11b0 | 1744 | { |
93f6e1c7 | 1745 | rtx extend = NULL_RTX; |
2ff4bf8d | 1746 | rtx temp; |
5e3c5739 | 1747 | |
1748 | if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT | |
b7d86581 | 1749 | && HOST_BITS_PER_WIDE_INT > 32 |
5e3c5739 | 1750 | && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32) |
1751 | { | |
1752 | HOST_WIDE_INT val = INTVAL (operand1); | |
b7d86581 | 1753 | HOST_WIDE_INT nval; |
5e3c5739 | 1754 | |
93f6e1c7 | 1755 | /* Extract the low order 32 bits of the value and sign extend. |
1756 | If the new value is the same as the original value, we can | |
1757 | can use the original value as-is. If the new value is | |
1758 | different, we use it and insert the most-significant 32-bits | |
1759 | of the original value into the final result. */ | |
b7d86581 | 1760 | nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1)) |
1761 | ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31); | |
5e3c5739 | 1762 | if (val != nval) |
1763 | { | |
93f6e1c7 | 1764 | #if HOST_BITS_PER_WIDE_INT > 32 |
1765 | extend = GEN_INT (val >> 32); | |
1766 | #endif | |
5e3c5739 | 1767 | operand1 = GEN_INT (nval); |
1768 | } | |
1769 | } | |
2ff4bf8d | 1770 | |
1771 | if (reload_in_progress || reload_completed) | |
1772 | temp = operand0; | |
1773 | else | |
1774 | temp = gen_reg_rtx (mode); | |
1775 | ||
7c4d3047 | 1776 | /* We don't directly split DImode constants on 32-bit targets |
1777 | because PLUS uses an 11-bit immediate and the insn sequence | |
1778 | generated is not as efficient as the one using HIGH/LO_SUM. */ | |
1779 | if (GET_CODE (operand1) == CONST_INT | |
1780 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT) | |
93f6e1c7 | 1781 | { |
7c4d3047 | 1782 | /* Directly break constant into high and low parts. This |
93f6e1c7 | 1783 | provides better optimization opportunities because various |
1784 | passes recognize constants split with PLUS but not LO_SUM. | |
1785 | We use a 14-bit signed low part except when the addition | |
1786 | of 0x4000 to the high part might change the sign of the | |
1787 | high part. */ | |
1788 | HOST_WIDE_INT value = INTVAL (operand1); | |
1789 | HOST_WIDE_INT low = value & 0x3fff; | |
1790 | HOST_WIDE_INT high = value & ~ 0x3fff; | |
1791 | ||
1792 | if (low >= 0x2000) | |
1793 | { | |
1794 | if (high == 0x7fffc000 || (mode == HImode && high == 0x4000)) | |
1795 | high += 0x2000; | |
1796 | else | |
1797 | high += 0x4000; | |
1798 | } | |
1799 | ||
1800 | low = value - high; | |
5e3c5739 | 1801 | |
93f6e1c7 | 1802 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high))); |
1803 | operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low)); | |
1804 | } | |
1805 | else | |
5e3c5739 | 1806 | { |
93f6e1c7 | 1807 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
1808 | gen_rtx_HIGH (mode, operand1))); | |
1809 | operands[1] = gen_rtx_LO_SUM (mode, temp, operand1); | |
5e3c5739 | 1810 | } |
9840d99d | 1811 | |
93f6e1c7 | 1812 | emit_move_insn (operands[0], operands[1]); |
1813 | ||
1814 | if (extend != NULL_RTX) | |
1815 | emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx, | |
1816 | extend)); | |
1817 | ||
5e3c5739 | 1818 | return 1; |
87ad11b0 | 1819 | } |
1820 | } | |
1821 | /* Now have insn-emit do whatever it normally does. */ | |
1822 | return 0; | |
1823 | } | |
1824 | ||
1946138e | 1825 | /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning |
bd49d362 | 1826 | it will need a link/runtime reloc). */ |
1946138e | 1827 | |
1828 | int | |
1829 | reloc_needed (exp) | |
1830 | tree exp; | |
1831 | { | |
1832 | int reloc = 0; | |
1833 | ||
1834 | switch (TREE_CODE (exp)) | |
1835 | { | |
1836 | case ADDR_EXPR: | |
1837 | return 1; | |
1838 | ||
1839 | case PLUS_EXPR: | |
1840 | case MINUS_EXPR: | |
1841 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
1842 | reloc |= reloc_needed (TREE_OPERAND (exp, 1)); | |
1843 | break; | |
1844 | ||
1845 | case NOP_EXPR: | |
1846 | case CONVERT_EXPR: | |
1847 | case NON_LVALUE_EXPR: | |
1848 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
1849 | break; | |
1850 | ||
1851 | case CONSTRUCTOR: | |
1852 | { | |
1853 | register tree link; | |
1854 | for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link)) | |
1855 | if (TREE_VALUE (link) != 0) | |
1856 | reloc |= reloc_needed (TREE_VALUE (link)); | |
1857 | } | |
1858 | break; | |
1859 | ||
1860 | case ERROR_MARK: | |
1861 | break; | |
7d27e4c9 | 1862 | |
1863 | default: | |
1864 | break; | |
1946138e | 1865 | } |
1866 | return reloc; | |
1867 | } | |
1868 | ||
7811991d | 1869 | /* Does operand (which is a symbolic_operand) live in text space? |
1870 | If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info, | |
1871 | will be true. */ | |
87ad11b0 | 1872 | |
1873 | int | |
611a88e1 | 1874 | read_only_operand (operand, mode) |
87ad11b0 | 1875 | rtx operand; |
611a88e1 | 1876 | enum machine_mode mode ATTRIBUTE_UNUSED; |
87ad11b0 | 1877 | { |
1878 | if (GET_CODE (operand) == CONST) | |
1879 | operand = XEXP (XEXP (operand, 0), 0); | |
b4a7bf10 | 1880 | if (flag_pic) |
1881 | { | |
1882 | if (GET_CODE (operand) == SYMBOL_REF) | |
1883 | return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand); | |
1884 | } | |
1885 | else | |
1886 | { | |
1887 | if (GET_CODE (operand) == SYMBOL_REF) | |
1888 | return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand); | |
1889 | } | |
87ad11b0 | 1890 | return 1; |
1891 | } | |
6d36483b | 1892 | |
87ad11b0 | 1893 | \f |
1894 | /* Return the best assembler insn template | |
f54b1341 | 1895 | for moving operands[1] into operands[0] as a fullword. */ |
611a88e1 | 1896 | const char * |
87ad11b0 | 1897 | singlemove_string (operands) |
1898 | rtx *operands; | |
1899 | { | |
3745c59b | 1900 | HOST_WIDE_INT intval; |
1901 | ||
87ad11b0 | 1902 | if (GET_CODE (operands[0]) == MEM) |
1903 | return "stw %r1,%0"; | |
3745c59b | 1904 | if (GET_CODE (operands[1]) == MEM) |
87ad11b0 | 1905 | return "ldw %1,%0"; |
3745c59b | 1906 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
9d5108ea | 1907 | { |
3745c59b | 1908 | long i; |
1909 | REAL_VALUE_TYPE d; | |
9d5108ea | 1910 | |
3745c59b | 1911 | if (GET_MODE (operands[1]) != SFmode) |
1912 | abort (); | |
9d5108ea | 1913 | |
3745c59b | 1914 | /* Translate the CONST_DOUBLE to a CONST_INT with the same target |
1915 | bit pattern. */ | |
1916 | REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]); | |
1917 | REAL_VALUE_TO_TARGET_SINGLE (d, i); | |
9d5108ea | 1918 | |
3745c59b | 1919 | operands[1] = GEN_INT (i); |
1920 | /* Fall through to CONST_INT case. */ | |
1921 | } | |
1922 | if (GET_CODE (operands[1]) == CONST_INT) | |
9d5108ea | 1923 | { |
3745c59b | 1924 | intval = INTVAL (operands[1]); |
1925 | ||
1926 | if (VAL_14_BITS_P (intval)) | |
1927 | return "ldi %1,%0"; | |
1928 | else if ((intval & 0x7ff) == 0) | |
1929 | return "ldil L'%1,%0"; | |
1930 | else if (zdepi_cint_p (intval)) | |
e4065f95 | 1931 | return "{zdepi %Z1,%0|depwi,z %Z1,%0}"; |
9d5108ea | 1932 | else |
1933 | return "ldil L'%1,%0\n\tldo R'%1(%0),%0"; | |
1934 | } | |
87ad11b0 | 1935 | return "copy %1,%0"; |
1936 | } | |
1937 | \f | |
1938 | ||
201f01e9 | 1939 | /* Compute position (in OP[1]) and width (in OP[2]) |
1940 | useful for copying IMM to a register using the zdepi | |
1941 | instructions. Store the immediate value to insert in OP[0]. */ | |
611a88e1 | 1942 | static void |
fb22aedc | 1943 | compute_zdepwi_operands (imm, op) |
6d36483b | 1944 | unsigned HOST_WIDE_INT imm; |
42faba01 | 1945 | unsigned *op; |
7e10ba53 | 1946 | { |
e057641f | 1947 | int lsb, len; |
7e10ba53 | 1948 | |
e057641f | 1949 | /* Find the least significant set bit in IMM. */ |
1950 | for (lsb = 0; lsb < 32; lsb++) | |
7e10ba53 | 1951 | { |
e057641f | 1952 | if ((imm & 1) != 0) |
7e10ba53 | 1953 | break; |
e057641f | 1954 | imm >>= 1; |
7e10ba53 | 1955 | } |
1956 | ||
e057641f | 1957 | /* Choose variants based on *sign* of the 5-bit field. */ |
1958 | if ((imm & 0x10) == 0) | |
1959 | len = (lsb <= 28) ? 4 : 32 - lsb; | |
7e10ba53 | 1960 | else |
1961 | { | |
e057641f | 1962 | /* Find the width of the bitstring in IMM. */ |
1963 | for (len = 5; len < 32; len++) | |
7e10ba53 | 1964 | { |
e057641f | 1965 | if ((imm & (1 << len)) == 0) |
7e10ba53 | 1966 | break; |
7e10ba53 | 1967 | } |
1968 | ||
e057641f | 1969 | /* Sign extend IMM as a 5-bit value. */ |
1970 | imm = (imm & 0xf) - 0x10; | |
7e10ba53 | 1971 | } |
1972 | ||
42faba01 | 1973 | op[0] = imm; |
1974 | op[1] = 31 - lsb; | |
1975 | op[2] = len; | |
7e10ba53 | 1976 | } |
1977 | ||
5e3c5739 | 1978 | /* Compute position (in OP[1]) and width (in OP[2]) |
1979 | useful for copying IMM to a register using the depdi,z | |
1980 | instructions. Store the immediate value to insert in OP[0]. */ | |
1981 | void | |
1982 | compute_zdepdi_operands (imm, op) | |
1983 | unsigned HOST_WIDE_INT imm; | |
1984 | unsigned *op; | |
1985 | { | |
1986 | HOST_WIDE_INT lsb, len; | |
1987 | ||
1988 | /* Find the least significant set bit in IMM. */ | |
1989 | for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++) | |
1990 | { | |
1991 | if ((imm & 1) != 0) | |
1992 | break; | |
1993 | imm >>= 1; | |
1994 | } | |
1995 | ||
1996 | /* Choose variants based on *sign* of the 5-bit field. */ | |
1997 | if ((imm & 0x10) == 0) | |
1998 | len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4) | |
1999 | ? 4 : HOST_BITS_PER_WIDE_INT - lsb); | |
2000 | else | |
2001 | { | |
2002 | /* Find the width of the bitstring in IMM. */ | |
2003 | for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++) | |
2004 | { | |
ea52c577 | 2005 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
5e3c5739 | 2006 | break; |
2007 | } | |
2008 | ||
2009 | /* Sign extend IMM as a 5-bit value. */ | |
2010 | imm = (imm & 0xf) - 0x10; | |
2011 | } | |
2012 | ||
2013 | op[0] = imm; | |
2014 | op[1] = 63 - lsb; | |
2015 | op[2] = len; | |
2016 | } | |
2017 | ||
87ad11b0 | 2018 | /* Output assembler code to perform a doubleword move insn |
2019 | with operands OPERANDS. */ | |
2020 | ||
611a88e1 | 2021 | const char * |
87ad11b0 | 2022 | output_move_double (operands) |
2023 | rtx *operands; | |
2024 | { | |
2025 | enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1; | |
2026 | rtx latehalf[2]; | |
2027 | rtx addreg0 = 0, addreg1 = 0; | |
2028 | ||
2029 | /* First classify both operands. */ | |
2030 | ||
2031 | if (REG_P (operands[0])) | |
2032 | optype0 = REGOP; | |
2033 | else if (offsettable_memref_p (operands[0])) | |
2034 | optype0 = OFFSOP; | |
2035 | else if (GET_CODE (operands[0]) == MEM) | |
2036 | optype0 = MEMOP; | |
2037 | else | |
2038 | optype0 = RNDOP; | |
2039 | ||
2040 | if (REG_P (operands[1])) | |
2041 | optype1 = REGOP; | |
2042 | else if (CONSTANT_P (operands[1])) | |
2043 | optype1 = CNSTOP; | |
2044 | else if (offsettable_memref_p (operands[1])) | |
2045 | optype1 = OFFSOP; | |
2046 | else if (GET_CODE (operands[1]) == MEM) | |
2047 | optype1 = MEMOP; | |
2048 | else | |
2049 | optype1 = RNDOP; | |
2050 | ||
2051 | /* Check for the cases that the operand constraints are not | |
2052 | supposed to allow to happen. Abort if we get one, | |
2053 | because generating code for these cases is painful. */ | |
2054 | ||
2055 | if (optype0 != REGOP && optype1 != REGOP) | |
2056 | abort (); | |
2057 | ||
2058 | /* Handle auto decrementing and incrementing loads and stores | |
2059 | specifically, since the structure of the function doesn't work | |
2060 | for them without major modification. Do it better when we learn | |
2061 | this port about the general inc/dec addressing of PA. | |
2062 | (This was written by tege. Chide him if it doesn't work.) */ | |
2063 | ||
2064 | if (optype0 == MEMOP) | |
2065 | { | |
1df0058a | 2066 | /* We have to output the address syntax ourselves, since print_operand |
2067 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2068 | ||
87ad11b0 | 2069 | rtx addr = XEXP (operands[0], 0); |
1df0058a | 2070 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) |
87ad11b0 | 2071 | { |
ad851752 | 2072 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2073 | |
2074 | operands[0] = XEXP (addr, 0); | |
2075 | if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG) | |
2076 | abort (); | |
2077 | ||
2078 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2079 | { | |
2080 | /* No overlap between high target register and address | |
2081 | register. (We do this in a non-obvious way to | |
2082 | save a register file writeback) */ | |
2083 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2084 | return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)"; |
2085 | return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)"; | |
1df0058a | 2086 | } |
2087 | else | |
ea52c577 | 2088 | abort (); |
a3217f65 | 2089 | } |
1df0058a | 2090 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) |
a3217f65 | 2091 | { |
ad851752 | 2092 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2093 | |
2094 | operands[0] = XEXP (addr, 0); | |
2095 | if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG) | |
2096 | abort (); | |
2097 | ||
2098 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2099 | { | |
2100 | /* No overlap between high target register and address | |
2101 | register. (We do this in a non-obvious way to | |
2102 | save a register file writeback) */ | |
2103 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2104 | return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)"; |
2105 | return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)"; | |
1df0058a | 2106 | } |
2107 | else | |
ea52c577 | 2108 | abort (); |
87ad11b0 | 2109 | } |
2110 | } | |
2111 | if (optype1 == MEMOP) | |
2112 | { | |
2113 | /* We have to output the address syntax ourselves, since print_operand | |
2114 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2115 | ||
2116 | rtx addr = XEXP (operands[1], 0); | |
2117 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) | |
2118 | { | |
ad851752 | 2119 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2120 | |
2121 | operands[1] = XEXP (addr, 0); | |
2122 | if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG) | |
2123 | abort (); | |
2124 | ||
2125 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2126 | { | |
2127 | /* No overlap between high target register and address | |
3857fa62 | 2128 | register. (We do this in a non-obvious way to |
87ad11b0 | 2129 | save a register file writeback) */ |
2130 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2131 | return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0"; |
01fd4b49 | 2132 | return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0"; |
87ad11b0 | 2133 | } |
2134 | else | |
2135 | { | |
2136 | /* This is an undefined situation. We should load into the | |
2137 | address register *and* update that register. Probably | |
2138 | we don't need to handle this at all. */ | |
2139 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2140 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0"; |
2141 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0"; | |
87ad11b0 | 2142 | } |
2143 | } | |
2144 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) | |
2145 | { | |
ad851752 | 2146 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2147 | |
2148 | operands[1] = XEXP (addr, 0); | |
2149 | if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG) | |
2150 | abort (); | |
2151 | ||
2152 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2153 | { | |
2154 | /* No overlap between high target register and address | |
3857fa62 | 2155 | register. (We do this in a non-obvious way to |
87ad11b0 | 2156 | save a register file writeback) */ |
2157 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2158 | return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0"; |
2159 | return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0"; | |
87ad11b0 | 2160 | } |
2161 | else | |
2162 | { | |
2163 | /* This is an undefined situation. We should load into the | |
2164 | address register *and* update that register. Probably | |
2165 | we don't need to handle this at all. */ | |
2166 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2167 | return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0"; |
2168 | return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0"; | |
87ad11b0 | 2169 | } |
2170 | } | |
12b02046 | 2171 | else if (GET_CODE (addr) == PLUS |
2172 | && GET_CODE (XEXP (addr, 0)) == MULT) | |
2173 | { | |
ad851752 | 2174 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
12b02046 | 2175 | |
2176 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2177 | { | |
2178 | rtx xoperands[3]; | |
2179 | ||
2180 | xoperands[0] = high_reg; | |
2181 | xoperands[1] = XEXP (addr, 1); | |
2182 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2183 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2184 | output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}", |
2185 | xoperands); | |
34940871 | 2186 | return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; |
12b02046 | 2187 | } |
2188 | else | |
2189 | { | |
2190 | rtx xoperands[3]; | |
2191 | ||
2192 | xoperands[0] = high_reg; | |
2193 | xoperands[1] = XEXP (addr, 1); | |
2194 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2195 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2196 | output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}", |
2197 | xoperands); | |
34940871 | 2198 | return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0"; |
12b02046 | 2199 | } |
12b02046 | 2200 | } |
87ad11b0 | 2201 | } |
2202 | ||
2203 | /* If an operand is an unoffsettable memory ref, find a register | |
2204 | we can increment temporarily to make it refer to the second word. */ | |
2205 | ||
2206 | if (optype0 == MEMOP) | |
2207 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2208 | ||
2209 | if (optype1 == MEMOP) | |
2210 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2211 | ||
2212 | /* Ok, we can do one word at a time. | |
2213 | Normally we do the low-numbered word first. | |
2214 | ||
2215 | In either case, set up in LATEHALF the operands to use | |
2216 | for the high-numbered word and in some cases alter the | |
2217 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2218 | ||
2219 | if (optype0 == REGOP) | |
ad851752 | 2220 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
87ad11b0 | 2221 | else if (optype0 == OFFSOP) |
eafc6604 | 2222 | latehalf[0] = adjust_address (operands[0], SImode, 4); |
87ad11b0 | 2223 | else |
2224 | latehalf[0] = operands[0]; | |
2225 | ||
2226 | if (optype1 == REGOP) | |
ad851752 | 2227 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
87ad11b0 | 2228 | else if (optype1 == OFFSOP) |
eafc6604 | 2229 | latehalf[1] = adjust_address (operands[1], SImode, 4); |
87ad11b0 | 2230 | else if (optype1 == CNSTOP) |
2231 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2232 | else | |
2233 | latehalf[1] = operands[1]; | |
2234 | ||
2235 | /* If the first move would clobber the source of the second one, | |
2236 | do them in the other order. | |
2237 | ||
cf489d53 | 2238 | This can happen in two cases: |
87ad11b0 | 2239 | |
cf489d53 | 2240 | mem -> register where the first half of the destination register |
2241 | is the same register used in the memory's address. Reload | |
2242 | can create such insns. | |
87ad11b0 | 2243 | |
cf489d53 | 2244 | mem in this case will be either register indirect or register |
9840d99d | 2245 | indirect plus a valid offset. |
cf489d53 | 2246 | |
2247 | register -> register move where REGNO(dst) == REGNO(src + 1) | |
9840d99d | 2248 | someone (Tim/Tege?) claimed this can happen for parameter loads. |
cf489d53 | 2249 | |
2250 | Handle mem -> register case first. */ | |
2251 | if (optype0 == REGOP | |
2252 | && (optype1 == MEMOP || optype1 == OFFSOP) | |
2253 | && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2254 | operands[1], 0)) | |
87ad11b0 | 2255 | { |
87ad11b0 | 2256 | /* Do the late half first. */ |
2257 | if (addreg1) | |
6a5d085a | 2258 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2259 | output_asm_insn (singlemove_string (latehalf), latehalf); |
cf489d53 | 2260 | |
2261 | /* Then clobber. */ | |
87ad11b0 | 2262 | if (addreg1) |
6a5d085a | 2263 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2264 | return singlemove_string (operands); |
2265 | } | |
2266 | ||
cf489d53 | 2267 | /* Now handle register -> register case. */ |
c4fa5937 | 2268 | if (optype0 == REGOP && optype1 == REGOP |
2269 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
2270 | { | |
2271 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2272 | return singlemove_string (operands); | |
2273 | } | |
2274 | ||
87ad11b0 | 2275 | /* Normal case: do the two words, low-numbered first. */ |
2276 | ||
2277 | output_asm_insn (singlemove_string (operands), operands); | |
2278 | ||
2279 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2280 | if (addreg0) | |
6a5d085a | 2281 | output_asm_insn ("ldo 4(%0),%0", &addreg0); |
87ad11b0 | 2282 | if (addreg1) |
6a5d085a | 2283 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2284 | |
2285 | /* Do that word. */ | |
2286 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2287 | ||
2288 | /* Undo the adds we just did. */ | |
2289 | if (addreg0) | |
6a5d085a | 2290 | output_asm_insn ("ldo -4(%0),%0", &addreg0); |
87ad11b0 | 2291 | if (addreg1) |
6a5d085a | 2292 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2293 | |
2294 | return ""; | |
2295 | } | |
2296 | \f | |
611a88e1 | 2297 | const char * |
87ad11b0 | 2298 | output_fp_move_double (operands) |
2299 | rtx *operands; | |
2300 | { | |
2301 | if (FP_REG_P (operands[0])) | |
2302 | { | |
6d36483b | 2303 | if (FP_REG_P (operands[1]) |
891b55b4 | 2304 | || operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
c6ae275c | 2305 | output_asm_insn ("fcpy,dbl %f1,%0", operands); |
6d36483b | 2306 | else |
27ef382d | 2307 | output_asm_insn ("fldd%F1 %1,%0", operands); |
87ad11b0 | 2308 | } |
2309 | else if (FP_REG_P (operands[1])) | |
2310 | { | |
27ef382d | 2311 | output_asm_insn ("fstd%F0 %1,%0", operands); |
87ad11b0 | 2312 | } |
891b55b4 | 2313 | else if (operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
2314 | { | |
2315 | if (GET_CODE (operands[0]) == REG) | |
2316 | { | |
2317 | rtx xoperands[2]; | |
ad851752 | 2318 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
891b55b4 | 2319 | xoperands[0] = operands[0]; |
2320 | output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands); | |
2321 | } | |
6d36483b | 2322 | /* This is a pain. You have to be prepared to deal with an |
01cc3b75 | 2323 | arbitrary address here including pre/post increment/decrement. |
891b55b4 | 2324 | |
2325 | so avoid this in the MD. */ | |
2326 | else | |
2327 | abort (); | |
2328 | } | |
87ad11b0 | 2329 | else abort (); |
2330 | return ""; | |
2331 | } | |
2332 | \f | |
2333 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2334 | ADDR can be effectively incremented by incrementing REG. */ | |
2335 | ||
2336 | static rtx | |
2337 | find_addr_reg (addr) | |
2338 | rtx addr; | |
2339 | { | |
2340 | while (GET_CODE (addr) == PLUS) | |
2341 | { | |
2342 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2343 | addr = XEXP (addr, 0); | |
2344 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2345 | addr = XEXP (addr, 1); | |
2346 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2347 | addr = XEXP (addr, 1); | |
2348 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2349 | addr = XEXP (addr, 0); | |
2350 | else | |
2351 | abort (); | |
2352 | } | |
2353 | if (GET_CODE (addr) == REG) | |
2354 | return addr; | |
2355 | abort (); | |
2356 | } | |
2357 | ||
87ad11b0 | 2358 | /* Emit code to perform a block move. |
2359 | ||
87ad11b0 | 2360 | OPERANDS[0] is the destination pointer as a REG, clobbered. |
2361 | OPERANDS[1] is the source pointer as a REG, clobbered. | |
42819d4e | 2362 | OPERANDS[2] is a register for temporary storage. |
2363 | OPERANDS[4] is the size as a CONST_INT | |
87ad11b0 | 2364 | OPERANDS[3] is a register for temporary storage. |
9840d99d | 2365 | OPERANDS[5] is the alignment safe to use, as a CONST_INT. |
ad87de1e | 2366 | OPERANDS[6] is another temporary register. */ |
87ad11b0 | 2367 | |
611a88e1 | 2368 | const char * |
87ad11b0 | 2369 | output_block_move (operands, size_is_constant) |
2370 | rtx *operands; | |
b1ca791d | 2371 | int size_is_constant ATTRIBUTE_UNUSED; |
87ad11b0 | 2372 | { |
2373 | int align = INTVAL (operands[5]); | |
42819d4e | 2374 | unsigned long n_bytes = INTVAL (operands[4]); |
87ad11b0 | 2375 | |
2376 | /* We can't move more than four bytes at a time because the PA | |
2377 | has no longer integer move insns. (Could use fp mem ops?) */ | |
2378 | if (align > 4) | |
2379 | align = 4; | |
2380 | ||
42819d4e | 2381 | /* Note that we know each loop below will execute at least twice |
2382 | (else we would have open-coded the copy). */ | |
2383 | switch (align) | |
87ad11b0 | 2384 | { |
42819d4e | 2385 | case 4: |
2386 | /* Pre-adjust the loop counter. */ | |
2387 | operands[4] = GEN_INT (n_bytes - 8); | |
2388 | output_asm_insn ("ldi %4,%2", operands); | |
2389 | ||
2390 | /* Copying loop. */ | |
e4065f95 | 2391 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
2392 | output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands); | |
2393 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); | |
42819d4e | 2394 | output_asm_insn ("addib,>= -8,%2,.-12", operands); |
e4065f95 | 2395 | output_asm_insn ("{stws|stw},ma %6,4(%0)", operands); |
42819d4e | 2396 | |
2397 | /* Handle the residual. There could be up to 7 bytes of | |
2398 | residual to copy! */ | |
2399 | if (n_bytes % 8 != 0) | |
2400 | { | |
2401 | operands[4] = GEN_INT (n_bytes % 4); | |
2402 | if (n_bytes % 8 >= 4) | |
e4065f95 | 2403 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
42819d4e | 2404 | if (n_bytes % 4 != 0) |
34940871 | 2405 | output_asm_insn ("ldw 0(%1),%6", operands); |
42819d4e | 2406 | if (n_bytes % 8 >= 4) |
e4065f95 | 2407 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); |
42819d4e | 2408 | if (n_bytes % 4 != 0) |
e4065f95 | 2409 | output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands); |
42819d4e | 2410 | } |
2411 | return ""; | |
87ad11b0 | 2412 | |
42819d4e | 2413 | case 2: |
2414 | /* Pre-adjust the loop counter. */ | |
2415 | operands[4] = GEN_INT (n_bytes - 4); | |
2416 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2417 | |
42819d4e | 2418 | /* Copying loop. */ |
e4065f95 | 2419 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
2420 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands); | |
2421 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); | |
42819d4e | 2422 | output_asm_insn ("addib,>= -4,%2,.-12", operands); |
e4065f95 | 2423 | output_asm_insn ("{sths|sth},ma %6,2(%0)", operands); |
87ad11b0 | 2424 | |
42819d4e | 2425 | /* Handle the residual. */ |
2426 | if (n_bytes % 4 != 0) | |
2427 | { | |
2428 | if (n_bytes % 4 >= 2) | |
e4065f95 | 2429 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
42819d4e | 2430 | if (n_bytes % 2 != 0) |
34940871 | 2431 | output_asm_insn ("ldb 0(%1),%6", operands); |
42819d4e | 2432 | if (n_bytes % 4 >= 2) |
e4065f95 | 2433 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); |
42819d4e | 2434 | if (n_bytes % 2 != 0) |
34940871 | 2435 | output_asm_insn ("stb %6,0(%0)", operands); |
42819d4e | 2436 | } |
2437 | return ""; | |
87ad11b0 | 2438 | |
42819d4e | 2439 | case 1: |
2440 | /* Pre-adjust the loop counter. */ | |
2441 | operands[4] = GEN_INT (n_bytes - 2); | |
2442 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2443 | |
42819d4e | 2444 | /* Copying loop. */ |
e4065f95 | 2445 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands); |
2446 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands); | |
2447 | output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands); | |
42819d4e | 2448 | output_asm_insn ("addib,>= -2,%2,.-12", operands); |
e4065f95 | 2449 | output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands); |
87ad11b0 | 2450 | |
42819d4e | 2451 | /* Handle the residual. */ |
2452 | if (n_bytes % 2 != 0) | |
2453 | { | |
34940871 | 2454 | output_asm_insn ("ldb 0(%1),%3", operands); |
2455 | output_asm_insn ("stb %3,0(%0)", operands); | |
42819d4e | 2456 | } |
2457 | return ""; | |
87ad11b0 | 2458 | |
42819d4e | 2459 | default: |
2460 | abort (); | |
87ad11b0 | 2461 | } |
87ad11b0 | 2462 | } |
58e17b0b | 2463 | |
2464 | /* Count the number of insns necessary to handle this block move. | |
2465 | ||
2466 | Basic structure is the same as emit_block_move, except that we | |
2467 | count insns rather than emit them. */ | |
2468 | ||
611a88e1 | 2469 | static int |
58e17b0b | 2470 | compute_movstrsi_length (insn) |
2471 | rtx insn; | |
2472 | { | |
2473 | rtx pat = PATTERN (insn); | |
fc1fb057 | 2474 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0)); |
2475 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0)); | |
42819d4e | 2476 | unsigned int n_insns = 0; |
58e17b0b | 2477 | |
2478 | /* We can't move more than four bytes at a time because the PA | |
2479 | has no longer integer move insns. (Could use fp mem ops?) */ | |
2480 | if (align > 4) | |
2481 | align = 4; | |
2482 | ||
79bfe6ae | 2483 | /* The basic copying loop. */ |
42819d4e | 2484 | n_insns = 6; |
58e17b0b | 2485 | |
42819d4e | 2486 | /* Residuals. */ |
2487 | if (n_bytes % (2 * align) != 0) | |
58e17b0b | 2488 | { |
79bfe6ae | 2489 | if ((n_bytes % (2 * align)) >= align) |
2490 | n_insns += 2; | |
2491 | ||
2492 | if ((n_bytes % align) != 0) | |
2493 | n_insns += 2; | |
58e17b0b | 2494 | } |
42819d4e | 2495 | |
2496 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2497 | return n_insns * 4; | |
58e17b0b | 2498 | } |
87ad11b0 | 2499 | \f |
2500 | ||
611a88e1 | 2501 | const char * |
e057641f | 2502 | output_and (operands) |
2503 | rtx *operands; | |
2504 | { | |
d6f01525 | 2505 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) |
e057641f | 2506 | { |
3745c59b | 2507 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
e057641f | 2508 | int ls0, ls1, ms0, p, len; |
2509 | ||
2510 | for (ls0 = 0; ls0 < 32; ls0++) | |
2511 | if ((mask & (1 << ls0)) == 0) | |
2512 | break; | |
2513 | ||
2514 | for (ls1 = ls0; ls1 < 32; ls1++) | |
2515 | if ((mask & (1 << ls1)) != 0) | |
2516 | break; | |
2517 | ||
2518 | for (ms0 = ls1; ms0 < 32; ms0++) | |
2519 | if ((mask & (1 << ms0)) == 0) | |
2520 | break; | |
2521 | ||
2522 | if (ms0 != 32) | |
ea52c577 | 2523 | abort (); |
e057641f | 2524 | |
2525 | if (ls1 == 32) | |
2526 | { | |
2527 | len = ls0; | |
2528 | ||
2529 | if (len == 0) | |
2530 | abort (); | |
2531 | ||
ef618fe4 | 2532 | operands[2] = GEN_INT (len); |
e4065f95 | 2533 | return "{extru|extrw,u} %1,31,%2,%0"; |
e057641f | 2534 | } |
2535 | else | |
2536 | { | |
2537 | /* We could use this `depi' for the case above as well, but `depi' | |
2538 | requires one more register file access than an `extru'. */ | |
2539 | ||
2540 | p = 31 - ls0; | |
2541 | len = ls1 - ls0; | |
2542 | ||
ef618fe4 | 2543 | operands[2] = GEN_INT (p); |
2544 | operands[3] = GEN_INT (len); | |
e4065f95 | 2545 | return "{depi|depwi} 0,%2,%3,%0"; |
e057641f | 2546 | } |
2547 | } | |
2548 | else | |
2549 | return "and %1,%2,%0"; | |
2550 | } | |
2551 | ||
5e3c5739 | 2552 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] |
2553 | storing the result in operands[0]. */ | |
9aadea62 | 2554 | const char * |
5e3c5739 | 2555 | output_64bit_and (operands) |
2556 | rtx *operands; | |
2557 | { | |
2558 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) | |
2559 | { | |
2560 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 2561 | int ls0, ls1, ms0, p, len; |
5e3c5739 | 2562 | |
2563 | for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++) | |
b7d86581 | 2564 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0) |
5e3c5739 | 2565 | break; |
2566 | ||
2567 | for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++) | |
b7d86581 | 2568 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0) |
5e3c5739 | 2569 | break; |
2570 | ||
2571 | for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++) | |
b7d86581 | 2572 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0) |
5e3c5739 | 2573 | break; |
2574 | ||
2575 | if (ms0 != HOST_BITS_PER_WIDE_INT) | |
b7d86581 | 2576 | abort (); |
5e3c5739 | 2577 | |
2578 | if (ls1 == HOST_BITS_PER_WIDE_INT) | |
2579 | { | |
2580 | len = ls0; | |
2581 | ||
2582 | if (len == 0) | |
2583 | abort (); | |
2584 | ||
2585 | operands[2] = GEN_INT (len); | |
2586 | return "extrd,u %1,63,%2,%0"; | |
2587 | } | |
2588 | else | |
2589 | { | |
2590 | /* We could use this `depi' for the case above as well, but `depi' | |
2591 | requires one more register file access than an `extru'. */ | |
2592 | ||
2593 | p = 63 - ls0; | |
2594 | len = ls1 - ls0; | |
2595 | ||
2596 | operands[2] = GEN_INT (p); | |
2597 | operands[3] = GEN_INT (len); | |
2598 | return "depdi 0,%2,%3,%0"; | |
2599 | } | |
2600 | } | |
2601 | else | |
2602 | return "and %1,%2,%0"; | |
2603 | } | |
2604 | ||
611a88e1 | 2605 | const char * |
e057641f | 2606 | output_ior (operands) |
2607 | rtx *operands; | |
2608 | { | |
3745c59b | 2609 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
57ed30e5 | 2610 | int bs0, bs1, p, len; |
6d36483b | 2611 | |
c9da5f4d | 2612 | if (INTVAL (operands[2]) == 0) |
2613 | return "copy %1,%0"; | |
e057641f | 2614 | |
c9da5f4d | 2615 | for (bs0 = 0; bs0 < 32; bs0++) |
2616 | if ((mask & (1 << bs0)) != 0) | |
2617 | break; | |
e057641f | 2618 | |
c9da5f4d | 2619 | for (bs1 = bs0; bs1 < 32; bs1++) |
2620 | if ((mask & (1 << bs1)) == 0) | |
2621 | break; | |
e057641f | 2622 | |
3745c59b | 2623 | if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask) |
ea52c577 | 2624 | abort (); |
e057641f | 2625 | |
c9da5f4d | 2626 | p = 31 - bs0; |
2627 | len = bs1 - bs0; | |
e057641f | 2628 | |
ef618fe4 | 2629 | operands[2] = GEN_INT (p); |
2630 | operands[3] = GEN_INT (len); | |
e4065f95 | 2631 | return "{depi|depwi} -1,%2,%3,%0"; |
e057641f | 2632 | } |
5e3c5739 | 2633 | |
2634 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] | |
2635 | storing the result in operands[0]. */ | |
9aadea62 | 2636 | const char * |
5e3c5739 | 2637 | output_64bit_ior (operands) |
2638 | rtx *operands; | |
2639 | { | |
2640 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 2641 | int bs0, bs1, p, len; |
5e3c5739 | 2642 | |
2643 | if (INTVAL (operands[2]) == 0) | |
2644 | return "copy %1,%0"; | |
2645 | ||
2646 | for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++) | |
b7d86581 | 2647 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0) |
5e3c5739 | 2648 | break; |
2649 | ||
2650 | for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++) | |
b7d86581 | 2651 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0) |
5e3c5739 | 2652 | break; |
2653 | ||
2654 | if (bs1 != HOST_BITS_PER_WIDE_INT | |
2655 | && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask) | |
b7d86581 | 2656 | abort (); |
5e3c5739 | 2657 | |
2658 | p = 63 - bs0; | |
2659 | len = bs1 - bs0; | |
2660 | ||
2661 | operands[2] = GEN_INT (p); | |
2662 | operands[3] = GEN_INT (len); | |
2663 | return "depdi -1,%2,%3,%0"; | |
2664 | } | |
e057641f | 2665 | \f |
58356836 | 2666 | /* Target hook for assembling integer objects. This code handles |
2667 | aligned SI and DI integers specially, since function references must | |
2668 | be preceded by P%. */ | |
2669 | ||
2670 | static bool | |
2671 | pa_assemble_integer (x, size, aligned_p) | |
2672 | rtx x; | |
2673 | unsigned int size; | |
2674 | int aligned_p; | |
2675 | { | |
2676 | if (size == UNITS_PER_WORD && aligned_p | |
2677 | && function_label_operand (x, VOIDmode)) | |
2678 | { | |
2679 | fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file); | |
2680 | output_addr_const (asm_out_file, x); | |
2681 | fputc ('\n', asm_out_file); | |
2682 | return true; | |
2683 | } | |
2684 | return default_assemble_integer (x, size, aligned_p); | |
2685 | } | |
2686 | \f | |
87ad11b0 | 2687 | /* Output an ascii string. */ |
57ed30e5 | 2688 | void |
87ad11b0 | 2689 | output_ascii (file, p, size) |
2690 | FILE *file; | |
feb9af9f | 2691 | const char *p; |
87ad11b0 | 2692 | int size; |
2693 | { | |
2694 | int i; | |
2695 | int chars_output; | |
2696 | unsigned char partial_output[16]; /* Max space 4 chars can occupy. */ | |
2697 | ||
2698 | /* The HP assembler can only take strings of 256 characters at one | |
2699 | time. This is a limitation on input line length, *not* the | |
2700 | length of the string. Sigh. Even worse, it seems that the | |
2701 | restriction is in number of input characters (see \xnn & | |
2702 | \whatever). So we have to do this very carefully. */ | |
2703 | ||
9c0ac0fd | 2704 | fputs ("\t.STRING \"", file); |
87ad11b0 | 2705 | |
2706 | chars_output = 0; | |
2707 | for (i = 0; i < size; i += 4) | |
2708 | { | |
2709 | int co = 0; | |
2710 | int io = 0; | |
2711 | for (io = 0, co = 0; io < MIN (4, size - i); io++) | |
2712 | { | |
bf8aac3e | 2713 | register unsigned int c = (unsigned char) p[i + io]; |
87ad11b0 | 2714 | |
2715 | if (c == '\"' || c == '\\') | |
2716 | partial_output[co++] = '\\'; | |
2717 | if (c >= ' ' && c < 0177) | |
2718 | partial_output[co++] = c; | |
2719 | else | |
2720 | { | |
2721 | unsigned int hexd; | |
2722 | partial_output[co++] = '\\'; | |
2723 | partial_output[co++] = 'x'; | |
2724 | hexd = c / 16 - 0 + '0'; | |
2725 | if (hexd > '9') | |
2726 | hexd -= '9' - 'a' + 1; | |
2727 | partial_output[co++] = hexd; | |
2728 | hexd = c % 16 - 0 + '0'; | |
2729 | if (hexd > '9') | |
2730 | hexd -= '9' - 'a' + 1; | |
2731 | partial_output[co++] = hexd; | |
2732 | } | |
2733 | } | |
2734 | if (chars_output + co > 243) | |
2735 | { | |
9c0ac0fd | 2736 | fputs ("\"\n\t.STRING \"", file); |
87ad11b0 | 2737 | chars_output = 0; |
2738 | } | |
a584fe8a | 2739 | fwrite (partial_output, 1, (size_t) co, file); |
87ad11b0 | 2740 | chars_output += co; |
2741 | co = 0; | |
2742 | } | |
9c0ac0fd | 2743 | fputs ("\"\n", file); |
87ad11b0 | 2744 | } |
c533da59 | 2745 | |
2746 | /* Try to rewrite floating point comparisons & branches to avoid | |
2747 | useless add,tr insns. | |
2748 | ||
2749 | CHECK_NOTES is nonzero if we should examine REG_DEAD notes | |
2750 | to see if FPCC is dead. CHECK_NOTES is nonzero for the | |
2751 | first attempt to remove useless add,tr insns. It is zero | |
2752 | for the second pass as reorg sometimes leaves bogus REG_DEAD | |
2753 | notes lying around. | |
2754 | ||
2755 | When CHECK_NOTES is zero we can only eliminate add,tr insns | |
2756 | when there's a 1:1 correspondence between fcmp and ftest/fbranch | |
2757 | instructions. */ | |
611a88e1 | 2758 | static void |
c533da59 | 2759 | remove_useless_addtr_insns (insns, check_notes) |
2760 | rtx insns; | |
2761 | int check_notes; | |
2762 | { | |
2763 | rtx insn; | |
c533da59 | 2764 | static int pass = 0; |
2765 | ||
2766 | /* This is fairly cheap, so always run it when optimizing. */ | |
2767 | if (optimize > 0) | |
2768 | { | |
2769 | int fcmp_count = 0; | |
2770 | int fbranch_count = 0; | |
2771 | ||
2772 | /* Walk all the insns in this function looking for fcmp & fbranch | |
2773 | instructions. Keep track of how many of each we find. */ | |
2774 | insns = get_insns (); | |
2775 | for (insn = insns; insn; insn = next_insn (insn)) | |
2776 | { | |
2777 | rtx tmp; | |
2778 | ||
2779 | /* Ignore anything that isn't an INSN or a JUMP_INSN. */ | |
2780 | if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
2781 | continue; | |
2782 | ||
2783 | tmp = PATTERN (insn); | |
2784 | ||
2785 | /* It must be a set. */ | |
2786 | if (GET_CODE (tmp) != SET) | |
2787 | continue; | |
2788 | ||
2789 | /* If the destination is CCFP, then we've found an fcmp insn. */ | |
2790 | tmp = SET_DEST (tmp); | |
2791 | if (GET_CODE (tmp) == REG && REGNO (tmp) == 0) | |
2792 | { | |
2793 | fcmp_count++; | |
2794 | continue; | |
2795 | } | |
9840d99d | 2796 | |
c533da59 | 2797 | tmp = PATTERN (insn); |
2798 | /* If this is an fbranch instruction, bump the fbranch counter. */ | |
2799 | if (GET_CODE (tmp) == SET | |
2800 | && SET_DEST (tmp) == pc_rtx | |
2801 | && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE | |
2802 | && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE | |
2803 | && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG | |
2804 | && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0) | |
2805 | { | |
2806 | fbranch_count++; | |
2807 | continue; | |
2808 | } | |
2809 | } | |
2810 | ||
2811 | ||
2812 | /* Find all floating point compare + branch insns. If possible, | |
2813 | reverse the comparison & the branch to avoid add,tr insns. */ | |
2814 | for (insn = insns; insn; insn = next_insn (insn)) | |
2815 | { | |
2816 | rtx tmp, next; | |
2817 | ||
2818 | /* Ignore anything that isn't an INSN. */ | |
2819 | if (GET_CODE (insn) != INSN) | |
2820 | continue; | |
2821 | ||
2822 | tmp = PATTERN (insn); | |
2823 | ||
2824 | /* It must be a set. */ | |
2825 | if (GET_CODE (tmp) != SET) | |
2826 | continue; | |
2827 | ||
2828 | /* The destination must be CCFP, which is register zero. */ | |
2829 | tmp = SET_DEST (tmp); | |
2830 | if (GET_CODE (tmp) != REG || REGNO (tmp) != 0) | |
2831 | continue; | |
2832 | ||
2833 | /* INSN should be a set of CCFP. | |
2834 | ||
2835 | See if the result of this insn is used in a reversed FP | |
2836 | conditional branch. If so, reverse our condition and | |
2837 | the branch. Doing so avoids useless add,tr insns. */ | |
2838 | next = next_insn (insn); | |
2839 | while (next) | |
2840 | { | |
2841 | /* Jumps, calls and labels stop our search. */ | |
2842 | if (GET_CODE (next) == JUMP_INSN | |
2843 | || GET_CODE (next) == CALL_INSN | |
2844 | || GET_CODE (next) == CODE_LABEL) | |
2845 | break; | |
2846 | ||
2847 | /* As does another fcmp insn. */ | |
2848 | if (GET_CODE (next) == INSN | |
2849 | && GET_CODE (PATTERN (next)) == SET | |
2850 | && GET_CODE (SET_DEST (PATTERN (next))) == REG | |
2851 | && REGNO (SET_DEST (PATTERN (next))) == 0) | |
2852 | break; | |
2853 | ||
2854 | next = next_insn (next); | |
2855 | } | |
2856 | ||
2857 | /* Is NEXT_INSN a branch? */ | |
2858 | if (next | |
2859 | && GET_CODE (next) == JUMP_INSN) | |
2860 | { | |
2861 | rtx pattern = PATTERN (next); | |
2862 | ||
2863 | /* If it a reversed fp conditional branch (eg uses add,tr) | |
2864 | and CCFP dies, then reverse our conditional and the branch | |
2865 | to avoid the add,tr. */ | |
2866 | if (GET_CODE (pattern) == SET | |
2867 | && SET_DEST (pattern) == pc_rtx | |
2868 | && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE | |
2869 | && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE | |
2870 | && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG | |
2871 | && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0 | |
2872 | && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC | |
2873 | && (fcmp_count == fbranch_count | |
2874 | || (check_notes | |
2875 | && find_regno_note (next, REG_DEAD, 0)))) | |
2876 | { | |
2877 | /* Reverse the branch. */ | |
2878 | tmp = XEXP (SET_SRC (pattern), 1); | |
2879 | XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2); | |
2880 | XEXP (SET_SRC (pattern), 2) = tmp; | |
2881 | INSN_CODE (next) = -1; | |
2882 | ||
2883 | /* Reverse our condition. */ | |
2884 | tmp = PATTERN (insn); | |
2885 | PUT_CODE (XEXP (tmp, 1), | |
ea52c577 | 2886 | (reverse_condition_maybe_unordered |
2887 | (GET_CODE (XEXP (tmp, 1))))); | |
c533da59 | 2888 | } |
2889 | } | |
2890 | } | |
2891 | } | |
2892 | ||
2893 | pass = !pass; | |
2894 | ||
2895 | } | |
87ad11b0 | 2896 | \f |
ea52c577 | 2897 | /* You may have trouble believing this, but this is the 32 bit HP-PA |
2898 | stack layout. Wow. | |
87ad11b0 | 2899 | |
2900 | Offset Contents | |
2901 | ||
2902 | Variable arguments (optional; any number may be allocated) | |
2903 | ||
2904 | SP-(4*(N+9)) arg word N | |
2905 | : : | |
2906 | SP-56 arg word 5 | |
2907 | SP-52 arg word 4 | |
2908 | ||
2909 | Fixed arguments (must be allocated; may remain unused) | |
2910 | ||
2911 | SP-48 arg word 3 | |
2912 | SP-44 arg word 2 | |
2913 | SP-40 arg word 1 | |
2914 | SP-36 arg word 0 | |
2915 | ||
2916 | Frame Marker | |
2917 | ||
2918 | SP-32 External Data Pointer (DP) | |
2919 | SP-28 External sr4 | |
2920 | SP-24 External/stub RP (RP') | |
2921 | SP-20 Current RP | |
2922 | SP-16 Static Link | |
2923 | SP-12 Clean up | |
2924 | SP-8 Calling Stub RP (RP'') | |
2925 | SP-4 Previous SP | |
2926 | ||
2927 | Top of Frame | |
2928 | ||
2929 | SP-0 Stack Pointer (points to next available address) | |
2930 | ||
2931 | */ | |
2932 | ||
2933 | /* This function saves registers as follows. Registers marked with ' are | |
2934 | this function's registers (as opposed to the previous function's). | |
2935 | If a frame_pointer isn't needed, r4 is saved as a general register; | |
2936 | the space for the frame pointer is still allocated, though, to keep | |
2937 | things simple. | |
2938 | ||
2939 | ||
2940 | Top of Frame | |
2941 | ||
2942 | SP (FP') Previous FP | |
2943 | SP + 4 Alignment filler (sigh) | |
2944 | SP + 8 Space for locals reserved here. | |
2945 | . | |
2946 | . | |
2947 | . | |
2948 | SP + n All call saved register used. | |
2949 | . | |
2950 | . | |
2951 | . | |
2952 | SP + o All call saved fp registers used. | |
2953 | . | |
2954 | . | |
2955 | . | |
2956 | SP + p (SP') points to next available address. | |
6d36483b | 2957 | |
87ad11b0 | 2958 | */ |
2959 | ||
17d9b0c3 | 2960 | /* Global variables set by output_function_prologue(). */ |
cc858176 | 2961 | /* Size of frame. Need to know this to emit return insns from |
2962 | leaf procedures. */ | |
2963 | static int actual_fsize; | |
2964 | static int local_fsize, save_fregs; | |
2965 | ||
daee63dd | 2966 | /* Emit RTL to store REG at the memory location specified by BASE+DISP. |
359a0be8 | 2967 | Handle case where DISP > 8k by using the add_high_const patterns. |
daee63dd | 2968 | |
2969 | Note in DISP > 8k case, we will leave the high part of the address | |
2970 | in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/ | |
7014838c | 2971 | |
6a2c16d6 | 2972 | static void |
daee63dd | 2973 | store_reg (reg, disp, base) |
2974 | int reg, disp, base; | |
87ad11b0 | 2975 | { |
6a2c16d6 | 2976 | rtx insn, dest, src, basereg; |
cc858176 | 2977 | |
2978 | src = gen_rtx_REG (word_mode, reg); | |
2979 | basereg = gen_rtx_REG (Pmode, base); | |
87ad11b0 | 2980 | if (VAL_14_BITS_P (disp)) |
daee63dd | 2981 | { |
cc858176 | 2982 | dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
6a2c16d6 | 2983 | insn = emit_move_insn (dest, src); |
daee63dd | 2984 | } |
daee63dd | 2985 | else |
2986 | { | |
cc858176 | 2987 | rtx delta = GEN_INT (disp); |
2988 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
2989 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
2990 | emit_move_insn (tmpreg, high); | |
2991 | dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
6a2c16d6 | 2992 | insn = emit_move_insn (dest, src); |
2993 | if (DO_FRAME_NOTES) | |
2994 | { | |
2995 | REG_NOTES (insn) | |
2996 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
2997 | gen_rtx_SET (VOIDmode, | |
2998 | gen_rtx_MEM (word_mode, | |
2999 | gen_rtx_PLUS (word_mode, basereg, | |
3000 | delta)), | |
3001 | src), | |
3002 | REG_NOTES (insn)); | |
3003 | } | |
daee63dd | 3004 | } |
6a2c16d6 | 3005 | |
3006 | if (DO_FRAME_NOTES) | |
3007 | RTX_FRAME_RELATED_P (insn) = 1; | |
daee63dd | 3008 | } |
3009 | ||
a584fe8a | 3010 | /* Emit RTL to store REG at the memory location specified by BASE and then |
3011 | add MOD to BASE. MOD must be <= 8k. */ | |
daee63dd | 3012 | |
a584fe8a | 3013 | static void |
3014 | store_reg_modify (base, reg, mod) | |
3015 | int base, reg, mod; | |
3016 | { | |
3017 | rtx insn, basereg, srcreg, delta; | |
3018 | ||
3019 | if (! VAL_14_BITS_P (mod)) | |
3020 | abort (); | |
3021 | ||
3022 | basereg = gen_rtx_REG (Pmode, base); | |
3023 | srcreg = gen_rtx_REG (word_mode, reg); | |
3024 | delta = GEN_INT (mod); | |
3025 | ||
3026 | insn = emit_insn (gen_post_store (basereg, srcreg, delta)); | |
3027 | if (DO_FRAME_NOTES) | |
3028 | { | |
3029 | RTX_FRAME_RELATED_P (insn) = 1; | |
3030 | ||
3031 | /* RTX_FRAME_RELATED_P must be set on each frame related set | |
3032 | in a parallel with more than one element. Don't set | |
3033 | RTX_FRAME_RELATED_P in the first set if reg is temporary | |
3034 | register 1. The effect of this operation is recorded in | |
3035 | the initial copy. */ | |
3036 | if (reg != 1) | |
3037 | { | |
3038 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1; | |
3039 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; | |
3040 | } | |
3041 | else | |
3042 | { | |
3043 | /* The first element of a PARALLEL is always processed if it is | |
3044 | a SET. Thus, we need an expression list for this case. */ | |
3045 | REG_NOTES (insn) | |
3046 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3047 | gen_rtx_SET (VOIDmode, basereg, | |
3048 | gen_rtx_PLUS (word_mode, basereg, delta)), | |
3049 | REG_NOTES (insn)); | |
3050 | } | |
3051 | } | |
3052 | } | |
3053 | ||
3054 | /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case | |
3055 | where DISP > 8k by using the add_high_const patterns. NOTE indicates | |
3056 | whether to add a frame note or not. | |
3057 | ||
3058 | In the DISP > 8k case, we leave the high part of the address in %r1. | |
3059 | There is code in expand_hppa_{prologue,epilogue} that knows about this. */ | |
7014838c | 3060 | |
6a2c16d6 | 3061 | static void |
a584fe8a | 3062 | set_reg_plus_d (reg, base, disp, note) |
3063 | int reg, base, disp, note; | |
87ad11b0 | 3064 | { |
6a2c16d6 | 3065 | rtx insn; |
cc858176 | 3066 | |
87ad11b0 | 3067 | if (VAL_14_BITS_P (disp)) |
cc858176 | 3068 | { |
6a2c16d6 | 3069 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
3070 | plus_constant (gen_rtx_REG (Pmode, base), disp)); | |
cc858176 | 3071 | } |
87ad11b0 | 3072 | else |
daee63dd | 3073 | { |
6a2c16d6 | 3074 | rtx basereg = gen_rtx_REG (Pmode, base); |
cc858176 | 3075 | rtx delta = GEN_INT (disp); |
6a2c16d6 | 3076 | |
359a0be8 | 3077 | emit_move_insn (gen_rtx_REG (Pmode, 1), |
6a2c16d6 | 3078 | gen_rtx_PLUS (Pmode, basereg, |
cc858176 | 3079 | gen_rtx_HIGH (Pmode, delta))); |
6a2c16d6 | 3080 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
3081 | gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1), | |
3082 | delta)); | |
daee63dd | 3083 | } |
6a2c16d6 | 3084 | |
a584fe8a | 3085 | if (DO_FRAME_NOTES && note) |
6a2c16d6 | 3086 | RTX_FRAME_RELATED_P (insn) = 1; |
87ad11b0 | 3087 | } |
3088 | ||
3089 | int | |
a1ab4fa3 | 3090 | compute_frame_size (size, fregs_live) |
87ad11b0 | 3091 | int size; |
3ddcbb9d | 3092 | int *fregs_live; |
87ad11b0 | 3093 | { |
a1ab4fa3 | 3094 | int i, fsize; |
87ad11b0 | 3095 | |
3a51bad9 | 3096 | /* Space for frame pointer + filler. If any frame is allocated |
3097 | we need to add this in because of STARTING_FRAME_OFFSET. | |
87ad11b0 | 3098 | |
3a51bad9 | 3099 | Similar code also appears in hppa_expand_prologue. Change both |
3100 | of them at the same time. */ | |
3101 | fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0); | |
3102 | ||
a584fe8a | 3103 | /* If the current function calls __builtin_eh_return, then we need |
3104 | to allocate stack space for registers that will hold data for | |
3105 | the exception handler. */ | |
3106 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3107 | { | |
3108 | unsigned int i; | |
3109 | ||
3110 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
3111 | continue; | |
3112 | fsize += i * UNITS_PER_WORD; | |
3113 | } | |
3114 | ||
3a51bad9 | 3115 | /* Account for space used by the callee general register saves. */ |
7f7c4869 | 3116 | for (i = 18; i >= 3; i--) |
3117 | if (regs_ever_live[i]) | |
0e79b5ab | 3118 | fsize += UNITS_PER_WORD; |
002fc5f7 | 3119 | |
7f7c4869 | 3120 | /* Round the stack. */ |
df0651dc | 3121 | fsize = (fsize + 7) & ~7; |
3122 | ||
3a51bad9 | 3123 | /* Account for space used by the callee floating point register saves. */ |
bac38c40 | 3124 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
5e3c5739 | 3125 | if (regs_ever_live[i] |
3126 | || (! TARGET_64BIT && regs_ever_live[i + 1])) | |
df0651dc | 3127 | { |
df0651dc | 3128 | if (fregs_live) |
3129 | *fregs_live = 1; | |
002fc5f7 | 3130 | |
3a51bad9 | 3131 | /* We always save both halves of the FP register, so always |
3132 | increment the frame size by 8 bytes. */ | |
6ec4380b | 3133 | fsize += 8; |
df0651dc | 3134 | } |
3135 | ||
3a51bad9 | 3136 | /* The various ABIs include space for the outgoing parameters in the |
3137 | size of the current function's stack frame. */ | |
a1ab4fa3 | 3138 | fsize += current_function_outgoing_args_size; |
3a51bad9 | 3139 | |
3140 | /* Allocate space for the fixed frame marker. This space must be | |
3141 | allocated for any function that makes calls or otherwise allocates | |
3142 | stack space. */ | |
5e3c5739 | 3143 | if (!current_function_is_leaf || fsize) |
d11dd4f3 | 3144 | fsize += TARGET_64BIT ? 16 : 32; |
5e3c5739 | 3145 | |
fa7b8a1c | 3146 | return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1); |
87ad11b0 | 3147 | } |
6d36483b | 3148 | |
17d9b0c3 | 3149 | /* Generate the assembly code for function entry. FILE is a stdio |
3150 | stream to output the code to. SIZE is an int: how many units of | |
3151 | temporary storage to allocate. | |
3152 | ||
3153 | Refer to the array `regs_ever_live' to determine which registers to | |
3154 | save; `regs_ever_live[I]' is nonzero if register number I is ever | |
3155 | used in the function. This function is responsible for knowing | |
3156 | which registers should not be saved even if used. */ | |
3157 | ||
3158 | /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block | |
3159 | of memory. If any fpu reg is used in the function, we allocate | |
3160 | such a block here, at the bottom of the frame, just in case it's needed. | |
3161 | ||
3162 | If this function is a leaf procedure, then we may choose not | |
3163 | to do a "save" insn. The decision about whether or not | |
3164 | to do this is made in regclass.c. */ | |
3165 | ||
6988553d | 3166 | static void |
17d9b0c3 | 3167 | pa_output_function_prologue (file, size) |
87ad11b0 | 3168 | FILE *file; |
17d9b0c3 | 3169 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
87ad11b0 | 3170 | { |
d151162a | 3171 | /* The function's label and associated .PROC must never be |
3172 | separated and must be output *after* any profiling declarations | |
3173 | to avoid changing spaces/subspaces within a procedure. */ | |
3174 | ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3175 | fputs ("\t.PROC\n", file); | |
3176 | ||
daee63dd | 3177 | /* hppa_expand_prologue does the dirty work now. We just need |
3178 | to output the assembler directives which denote the start | |
3179 | of a function. */ | |
2acd4f33 | 3180 | fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize); |
df6edefa | 3181 | if (regs_ever_live[2]) |
9c0ac0fd | 3182 | fputs (",CALLS,SAVE_RP", file); |
daee63dd | 3183 | else |
9c0ac0fd | 3184 | fputs (",NO_CALLS", file); |
f3ba7709 | 3185 | |
3186 | if (frame_pointer_needed) | |
9c0ac0fd | 3187 | fputs (",SAVE_SP", file); |
f3ba7709 | 3188 | |
a9960cdc | 3189 | /* Pass on information about the number of callee register saves |
9b0c95be | 3190 | performed in the prologue. |
3191 | ||
3192 | The compiler is supposed to pass the highest register number | |
6d36483b | 3193 | saved, the assembler then has to adjust that number before |
9b0c95be | 3194 | entering it into the unwind descriptor (to account for any |
6d36483b | 3195 | caller saved registers with lower register numbers than the |
9b0c95be | 3196 | first callee saved register). */ |
3197 | if (gr_saved) | |
3198 | fprintf (file, ",ENTRY_GR=%d", gr_saved + 2); | |
3199 | ||
3200 | if (fr_saved) | |
3201 | fprintf (file, ",ENTRY_FR=%d", fr_saved + 11); | |
a9960cdc | 3202 | |
9c0ac0fd | 3203 | fputs ("\n\t.ENTRY\n", file); |
daee63dd | 3204 | |
b70ea764 | 3205 | /* If we're using GAS and SOM, and not using the portable runtime model, |
ece88821 | 3206 | or function sections, then we don't need to accumulate the total number |
3207 | of code bytes. */ | |
b70ea764 | 3208 | if ((TARGET_GAS && TARGET_SOM && ! TARGET_PORTABLE_RUNTIME) |
ece88821 | 3209 | || flag_function_sections) |
f9333726 | 3210 | total_code_bytes = 0; |
47fc0706 | 3211 | else if (INSN_ADDRESSES_SET_P ()) |
06ddb6f8 | 3212 | { |
ece88821 | 3213 | unsigned long old_total = total_code_bytes; |
06ddb6f8 | 3214 | |
70545de4 | 3215 | total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_nonnote_insn ())); |
f9333726 | 3216 | total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT; |
06ddb6f8 | 3217 | |
3218 | /* Be prepared to handle overflows. */ | |
4ad2b0ae | 3219 | if (old_total > total_code_bytes) |
3220 | total_code_bytes = -1; | |
06ddb6f8 | 3221 | } |
3222 | else | |
3223 | total_code_bytes = -1; | |
c533da59 | 3224 | |
3225 | remove_useless_addtr_insns (get_insns (), 0); | |
daee63dd | 3226 | } |
3227 | ||
57ed30e5 | 3228 | void |
cc858176 | 3229 | hppa_expand_prologue () |
daee63dd | 3230 | { |
daee63dd | 3231 | int size = get_frame_size (); |
afd7b680 | 3232 | int merge_sp_adjust_with_store = 0; |
daee63dd | 3233 | int i, offset; |
a584fe8a | 3234 | rtx insn, tmpreg; |
daee63dd | 3235 | |
a9960cdc | 3236 | gr_saved = 0; |
3237 | fr_saved = 0; | |
3ddcbb9d | 3238 | save_fregs = 0; |
3a51bad9 | 3239 | |
3240 | /* Allocate space for frame pointer + filler. If any frame is allocated | |
3241 | we need to add this in because of STARTING_FRAME_OFFSET. | |
3242 | ||
3243 | Similar code also appears in compute_frame_size. Change both | |
3244 | of them at the same time. */ | |
3245 | local_fsize = size + (size || frame_pointer_needed | |
3246 | ? STARTING_FRAME_OFFSET : 0); | |
3247 | ||
a1ab4fa3 | 3248 | actual_fsize = compute_frame_size (size, &save_fregs); |
87ad11b0 | 3249 | |
daee63dd | 3250 | /* Compute a few things we will use often. */ |
440c23df | 3251 | tmpreg = gen_rtx_REG (word_mode, 1); |
87ad11b0 | 3252 | |
6d36483b | 3253 | /* Save RP first. The calling conventions manual states RP will |
cc858176 | 3254 | always be stored into the caller's frame at sp - 20 or sp - 16 |
5e3c5739 | 3255 | depending on which ABI is in use. */ |
a584fe8a | 3256 | if (regs_ever_live[2] || current_function_calls_eh_return) |
6a2c16d6 | 3257 | store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM); |
6d36483b | 3258 | |
daee63dd | 3259 | /* Allocate the local frame and set up the frame pointer if needed. */ |
58361f39 | 3260 | if (actual_fsize != 0) |
3261 | { | |
3262 | if (frame_pointer_needed) | |
3263 | { | |
3264 | /* Copy the old frame pointer temporarily into %r1. Set up the | |
3265 | new stack pointer, then store away the saved old frame pointer | |
a584fe8a | 3266 | into the stack at sp and at the same time update the stack |
3267 | pointer by actual_fsize bytes. Two versions, first | |
58361f39 | 3268 | handles small (<8k) frames. The second handles large (>=8k) |
3269 | frames. */ | |
a584fe8a | 3270 | insn = emit_move_insn (tmpreg, frame_pointer_rtx); |
3271 | if (DO_FRAME_NOTES) | |
cc858176 | 3272 | { |
a584fe8a | 3273 | /* We need to record the frame pointer save here since the |
3274 | new frame pointer is set in the following insn. */ | |
3275 | RTX_FRAME_RELATED_P (insn) = 1; | |
3276 | REG_NOTES (insn) | |
3277 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3278 | gen_rtx_SET (VOIDmode, | |
3279 | gen_rtx_MEM (word_mode, stack_pointer_rtx), | |
3280 | frame_pointer_rtx), | |
3281 | REG_NOTES (insn)); | |
cc858176 | 3282 | } |
a584fe8a | 3283 | |
3284 | insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); | |
3285 | if (DO_FRAME_NOTES) | |
3286 | RTX_FRAME_RELATED_P (insn) = 1; | |
3287 | ||
3288 | if (VAL_14_BITS_P (actual_fsize)) | |
3289 | store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize); | |
58361f39 | 3290 | else |
3291 | { | |
3292 | /* It is incorrect to store the saved frame pointer at *sp, | |
3293 | then increment sp (writes beyond the current stack boundary). | |
3294 | ||
3295 | So instead use stwm to store at *sp and post-increment the | |
3296 | stack pointer as an atomic operation. Then increment sp to | |
3297 | finish allocating the new frame. */ | |
3298 | int adjust1 = 8192 - 64; | |
3299 | int adjust2 = actual_fsize - adjust1; | |
cc858176 | 3300 | |
a584fe8a | 3301 | store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1); |
6a2c16d6 | 3302 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3303 | adjust2, 1); |
58361f39 | 3304 | } |
a584fe8a | 3305 | |
58361f39 | 3306 | /* Prevent register spills from being scheduled before the |
3307 | stack pointer is raised. Necessary as we will be storing | |
3308 | registers using the frame pointer as a base register, and | |
9840d99d | 3309 | we happen to set fp before raising sp. */ |
58361f39 | 3310 | emit_insn (gen_blockage ()); |
3311 | } | |
3312 | /* no frame pointer needed. */ | |
3313 | else | |
3314 | { | |
3315 | /* In some cases we can perform the first callee register save | |
3316 | and allocating the stack frame at the same time. If so, just | |
3317 | make a note of it and defer allocating the frame until saving | |
3318 | the callee registers. */ | |
df6edefa | 3319 | if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0) |
58361f39 | 3320 | merge_sp_adjust_with_store = 1; |
3321 | /* Can not optimize. Adjust the stack frame by actual_fsize | |
3322 | bytes. */ | |
3323 | else | |
6a2c16d6 | 3324 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3325 | actual_fsize, 1); |
58361f39 | 3326 | } |
372ef038 | 3327 | } |
3328 | ||
6d36483b | 3329 | /* Normal register save. |
daee63dd | 3330 | |
3331 | Do not save the frame pointer in the frame_pointer_needed case. It | |
3332 | was done earlier. */ | |
87ad11b0 | 3333 | if (frame_pointer_needed) |
3334 | { | |
a584fe8a | 3335 | offset = local_fsize; |
3336 | ||
3337 | /* Saving the EH return data registers in the frame is the simplest | |
3338 | way to get the frame unwind information emitted. We put them | |
3339 | just before the general registers. */ | |
3340 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3341 | { | |
3342 | unsigned int i, regno; | |
3343 | ||
3344 | for (i = 0; ; ++i) | |
3345 | { | |
3346 | regno = EH_RETURN_DATA_REGNO (i); | |
3347 | if (regno == INVALID_REGNUM) | |
3348 | break; | |
3349 | ||
3350 | store_reg (regno, offset, FRAME_POINTER_REGNUM); | |
3351 | offset += UNITS_PER_WORD; | |
3352 | } | |
3353 | } | |
3354 | ||
3355 | for (i = 18; i >= 4; i--) | |
98328a39 | 3356 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3357 | { |
6a2c16d6 | 3358 | store_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 3359 | offset += UNITS_PER_WORD; |
a9960cdc | 3360 | gr_saved++; |
87ad11b0 | 3361 | } |
7f7c4869 | 3362 | /* Account for %r3 which is saved in a special place. */ |
9b0c95be | 3363 | gr_saved++; |
87ad11b0 | 3364 | } |
daee63dd | 3365 | /* No frame pointer needed. */ |
87ad11b0 | 3366 | else |
3367 | { | |
a584fe8a | 3368 | offset = local_fsize - actual_fsize; |
3369 | ||
3370 | /* Saving the EH return data registers in the frame is the simplest | |
3371 | way to get the frame unwind information emitted. */ | |
3372 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3373 | { | |
3374 | unsigned int i, regno; | |
3375 | ||
3376 | for (i = 0; ; ++i) | |
3377 | { | |
3378 | regno = EH_RETURN_DATA_REGNO (i); | |
3379 | if (regno == INVALID_REGNUM) | |
3380 | break; | |
3381 | ||
3382 | /* If merge_sp_adjust_with_store is nonzero, then we can | |
3383 | optimize the first save. */ | |
3384 | if (merge_sp_adjust_with_store) | |
3385 | { | |
3386 | store_reg_modify (STACK_POINTER_REGNUM, regno, -offset); | |
3387 | merge_sp_adjust_with_store = 0; | |
3388 | } | |
3389 | else | |
3390 | store_reg (regno, offset, STACK_POINTER_REGNUM); | |
3391 | offset += UNITS_PER_WORD; | |
3392 | } | |
3393 | } | |
3394 | ||
3395 | for (i = 18; i >= 3; i--) | |
98328a39 | 3396 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3397 | { |
6d36483b | 3398 | /* If merge_sp_adjust_with_store is nonzero, then we can |
afd7b680 | 3399 | optimize the first GR save. */ |
201f01e9 | 3400 | if (merge_sp_adjust_with_store) |
afd7b680 | 3401 | { |
a584fe8a | 3402 | store_reg_modify (STACK_POINTER_REGNUM, i, -offset); |
afd7b680 | 3403 | merge_sp_adjust_with_store = 0; |
afd7b680 | 3404 | } |
3405 | else | |
6a2c16d6 | 3406 | store_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 3407 | offset += UNITS_PER_WORD; |
a9960cdc | 3408 | gr_saved++; |
87ad11b0 | 3409 | } |
daee63dd | 3410 | |
afd7b680 | 3411 | /* If we wanted to merge the SP adjustment with a GR save, but we never |
daee63dd | 3412 | did any GR saves, then just emit the adjustment here. */ |
201f01e9 | 3413 | if (merge_sp_adjust_with_store) |
6a2c16d6 | 3414 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3415 | actual_fsize, 1); |
87ad11b0 | 3416 | } |
6d36483b | 3417 | |
df6edefa | 3418 | /* The hppa calling conventions say that %r19, the pic offset |
3419 | register, is saved at sp - 32 (in this function's frame) | |
3420 | when generating PIC code. FIXME: What is the correct thing | |
3421 | to do for functions which make no calls and allocate no | |
3422 | frame? Do we need to allocate a frame, or can we just omit | |
3423 | the save? For now we'll just omit the save. */ | |
3424 | if (flag_pic && actual_fsize != 0 && !TARGET_64BIT) | |
3425 | store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM); | |
3426 | ||
87ad11b0 | 3427 | /* Align pointer properly (doubleword boundary). */ |
3428 | offset = (offset + 7) & ~7; | |
3429 | ||
3430 | /* Floating point register store. */ | |
3431 | if (save_fregs) | |
87ad11b0 | 3432 | { |
a584fe8a | 3433 | rtx base; |
3434 | ||
daee63dd | 3435 | /* First get the frame or stack pointer to the start of the FP register |
3436 | save area. */ | |
a1ab4fa3 | 3437 | if (frame_pointer_needed) |
a584fe8a | 3438 | { |
3439 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); | |
3440 | base = frame_pointer_rtx; | |
3441 | } | |
a1ab4fa3 | 3442 | else |
a584fe8a | 3443 | { |
3444 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); | |
3445 | base = stack_pointer_rtx; | |
3446 | } | |
daee63dd | 3447 | |
3448 | /* Now actually save the FP registers. */ | |
bac38c40 | 3449 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
7f7c4869 | 3450 | { |
5e3c5739 | 3451 | if (regs_ever_live[i] |
3452 | || (! TARGET_64BIT && regs_ever_live[i + 1])) | |
7f7c4869 | 3453 | { |
6a2c16d6 | 3454 | rtx addr, insn, reg; |
cc858176 | 3455 | addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); |
3456 | reg = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 3457 | insn = emit_move_insn (addr, reg); |
3458 | if (DO_FRAME_NOTES) | |
3459 | { | |
3460 | RTX_FRAME_RELATED_P (insn) = 1; | |
a584fe8a | 3461 | if (TARGET_64BIT) |
3462 | { | |
3463 | rtx mem = gen_rtx_MEM (DFmode, | |
3464 | plus_constant (base, offset)); | |
3465 | REG_NOTES (insn) | |
3466 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3467 | gen_rtx_SET (VOIDmode, mem, reg), | |
3468 | REG_NOTES (insn)); | |
3469 | } | |
3470 | else | |
3471 | { | |
3472 | rtx meml = gen_rtx_MEM (SFmode, | |
3473 | plus_constant (base, offset)); | |
3474 | rtx memr = gen_rtx_MEM (SFmode, | |
3475 | plus_constant (base, offset + 4)); | |
3476 | rtx regl = gen_rtx_REG (SFmode, i); | |
3477 | rtx regr = gen_rtx_REG (SFmode, i + 1); | |
3478 | rtx setl = gen_rtx_SET (VOIDmode, meml, regl); | |
3479 | rtx setr = gen_rtx_SET (VOIDmode, memr, regr); | |
3480 | rtvec vec; | |
3481 | ||
3482 | RTX_FRAME_RELATED_P (setl) = 1; | |
3483 | RTX_FRAME_RELATED_P (setr) = 1; | |
3484 | vec = gen_rtvec (2, setl, setr); | |
3485 | REG_NOTES (insn) | |
3486 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3487 | gen_rtx_SEQUENCE (VOIDmode, vec), | |
3488 | REG_NOTES (insn)); | |
3489 | } | |
6a2c16d6 | 3490 | } |
3491 | offset += GET_MODE_SIZE (DFmode); | |
7f7c4869 | 3492 | fr_saved++; |
3493 | } | |
3494 | } | |
87ad11b0 | 3495 | } |
a584fe8a | 3496 | |
3497 | /* FIXME: expand_call and expand_millicode_call need to be fixed to | |
3498 | prevent insns with frame notes being scheduled in the delay slot | |
3499 | of calls. This causes problems because the dwarf2 output code | |
3500 | processes the insn list serially. For now, limit the migration | |
3501 | of prologue insns with a blockage. */ | |
3502 | if (DO_FRAME_NOTES) | |
3503 | emit_insn (gen_blockage ()); | |
87ad11b0 | 3504 | } |
3505 | ||
cc858176 | 3506 | /* Emit RTL to load REG from the memory location specified by BASE+DISP. |
3507 | Handle case where DISP > 8k by using the add_high_const patterns. */ | |
3508 | ||
6a2c16d6 | 3509 | static void |
cc858176 | 3510 | load_reg (reg, disp, base) |
3511 | int reg, disp, base; | |
3512 | { | |
6a2c16d6 | 3513 | rtx src, dest, basereg; |
cc858176 | 3514 | |
3515 | dest = gen_rtx_REG (word_mode, reg); | |
3516 | basereg = gen_rtx_REG (Pmode, base); | |
3517 | if (VAL_14_BITS_P (disp)) | |
3518 | { | |
3519 | src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); | |
6a2c16d6 | 3520 | emit_move_insn (dest, src); |
cc858176 | 3521 | } |
3522 | else | |
3523 | { | |
3524 | rtx delta = GEN_INT (disp); | |
3525 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3526 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3527 | emit_move_insn (tmpreg, high); | |
3528 | src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
6a2c16d6 | 3529 | emit_move_insn (dest, src); |
cc858176 | 3530 | } |
cc858176 | 3531 | } |
daee63dd | 3532 | |
17d9b0c3 | 3533 | /* This function generates the assembly code for function exit. |
3534 | Args are as for output_function_prologue (). | |
3535 | ||
3536 | The function epilogue should not depend on the current stack | |
3537 | pointer! It should use the frame pointer only. This is mandatory | |
3538 | because of alloca; we also take advantage of it to omit stack | |
6dc3b0d9 | 3539 | adjustments before returning. */ |
17d9b0c3 | 3540 | |
3541 | static void | |
3542 | pa_output_function_epilogue (file, size) | |
87ad11b0 | 3543 | FILE *file; |
17d9b0c3 | 3544 | HOST_WIDE_INT size ATTRIBUTE_UNUSED; |
87ad11b0 | 3545 | { |
3695c664 | 3546 | rtx insn = get_last_insn (); |
3547 | ||
daee63dd | 3548 | /* hppa_expand_epilogue does the dirty work now. We just need |
3549 | to output the assembler directives which denote the end | |
3695c664 | 3550 | of a function. |
3551 | ||
3552 | To make debuggers happy, emit a nop if the epilogue was completely | |
3553 | eliminated due to a volatile call as the last insn in the | |
6d36483b | 3554 | current function. That way the return address (in %r2) will |
3695c664 | 3555 | always point to a valid instruction in the current function. */ |
3556 | ||
3557 | /* Get the last real insn. */ | |
3558 | if (GET_CODE (insn) == NOTE) | |
3559 | insn = prev_real_insn (insn); | |
3560 | ||
3561 | /* If it is a sequence, then look inside. */ | |
3562 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3563 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
3564 | ||
6d36483b | 3565 | /* If insn is a CALL_INSN, then it must be a call to a volatile |
3695c664 | 3566 | function (otherwise there would be epilogue insns). */ |
3567 | if (insn && GET_CODE (insn) == CALL_INSN) | |
9c0ac0fd | 3568 | fputs ("\tnop\n", file); |
6d36483b | 3569 | |
9c0ac0fd | 3570 | fputs ("\t.EXIT\n\t.PROCEND\n", file); |
daee63dd | 3571 | } |
afd7b680 | 3572 | |
daee63dd | 3573 | void |
3695c664 | 3574 | hppa_expand_epilogue () |
daee63dd | 3575 | { |
6d36483b | 3576 | rtx tmpreg; |
58361f39 | 3577 | int offset, i; |
3578 | int merge_sp_adjust_with_load = 0; | |
3579 | int ret_off = 0; | |
daee63dd | 3580 | |
3581 | /* We will use this often. */ | |
440c23df | 3582 | tmpreg = gen_rtx_REG (word_mode, 1); |
daee63dd | 3583 | |
3584 | /* Try to restore RP early to avoid load/use interlocks when | |
3585 | RP gets used in the return (bv) instruction. This appears to still | |
6dc3b0d9 | 3586 | be necessary even when we schedule the prologue and epilogue. */ |
a584fe8a | 3587 | if (regs_ever_live [2] || current_function_calls_eh_return) |
58361f39 | 3588 | { |
3589 | ret_off = TARGET_64BIT ? -16 : -20; | |
3590 | if (frame_pointer_needed) | |
3591 | { | |
6a2c16d6 | 3592 | load_reg (2, ret_off, FRAME_POINTER_REGNUM); |
58361f39 | 3593 | ret_off = 0; |
3594 | } | |
3595 | else | |
3596 | { | |
3597 | /* No frame pointer, and stack is smaller than 8k. */ | |
3598 | if (VAL_14_BITS_P (ret_off - actual_fsize)) | |
3599 | { | |
6a2c16d6 | 3600 | load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM); |
58361f39 | 3601 | ret_off = 0; |
3602 | } | |
3603 | } | |
3604 | } | |
daee63dd | 3605 | |
3606 | /* General register restores. */ | |
87ad11b0 | 3607 | if (frame_pointer_needed) |
3608 | { | |
a584fe8a | 3609 | offset = local_fsize; |
3610 | ||
3611 | /* If the current function calls __builtin_eh_return, then we need | |
3612 | to restore the saved EH data registers. */ | |
3613 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3614 | { | |
3615 | unsigned int i, regno; | |
3616 | ||
3617 | for (i = 0; ; ++i) | |
3618 | { | |
3619 | regno = EH_RETURN_DATA_REGNO (i); | |
3620 | if (regno == INVALID_REGNUM) | |
3621 | break; | |
3622 | ||
3623 | load_reg (regno, offset, FRAME_POINTER_REGNUM); | |
3624 | offset += UNITS_PER_WORD; | |
3625 | } | |
3626 | } | |
3627 | ||
3628 | for (i = 18; i >= 4; i--) | |
98328a39 | 3629 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3630 | { |
6a2c16d6 | 3631 | load_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 3632 | offset += UNITS_PER_WORD; |
87ad11b0 | 3633 | } |
87ad11b0 | 3634 | } |
3635 | else | |
3636 | { | |
a584fe8a | 3637 | offset = local_fsize - actual_fsize; |
3638 | ||
3639 | /* If the current function calls __builtin_eh_return, then we need | |
3640 | to restore the saved EH data registers. */ | |
3641 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3642 | { | |
3643 | unsigned int i, regno; | |
3644 | ||
3645 | for (i = 0; ; ++i) | |
3646 | { | |
3647 | regno = EH_RETURN_DATA_REGNO (i); | |
3648 | if (regno == INVALID_REGNUM) | |
3649 | break; | |
3650 | ||
3651 | /* Only for the first load. | |
3652 | merge_sp_adjust_with_load holds the register load | |
3653 | with which we will merge the sp adjustment. */ | |
3654 | if (merge_sp_adjust_with_load == 0 | |
3655 | && local_fsize == 0 | |
3656 | && VAL_14_BITS_P (-actual_fsize)) | |
3657 | merge_sp_adjust_with_load = regno; | |
3658 | else | |
3659 | load_reg (regno, offset, STACK_POINTER_REGNUM); | |
3660 | offset += UNITS_PER_WORD; | |
3661 | } | |
3662 | } | |
3663 | ||
3664 | for (i = 18; i >= 3; i--) | |
7f7c4869 | 3665 | { |
98328a39 | 3666 | if (regs_ever_live[i] && ! call_used_regs[i]) |
7f7c4869 | 3667 | { |
7f7c4869 | 3668 | /* Only for the first load. |
3669 | merge_sp_adjust_with_load holds the register load | |
3670 | with which we will merge the sp adjustment. */ | |
58361f39 | 3671 | if (merge_sp_adjust_with_load == 0 |
7f7c4869 | 3672 | && local_fsize == 0 |
58361f39 | 3673 | && VAL_14_BITS_P (-actual_fsize)) |
7f7c4869 | 3674 | merge_sp_adjust_with_load = i; |
3675 | else | |
6a2c16d6 | 3676 | load_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 3677 | offset += UNITS_PER_WORD; |
7f7c4869 | 3678 | } |
3679 | } | |
87ad11b0 | 3680 | } |
daee63dd | 3681 | |
87ad11b0 | 3682 | /* Align pointer properly (doubleword boundary). */ |
3683 | offset = (offset + 7) & ~7; | |
3684 | ||
daee63dd | 3685 | /* FP register restores. */ |
87ad11b0 | 3686 | if (save_fregs) |
87ad11b0 | 3687 | { |
daee63dd | 3688 | /* Adjust the register to index off of. */ |
a1ab4fa3 | 3689 | if (frame_pointer_needed) |
a584fe8a | 3690 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); |
a1ab4fa3 | 3691 | else |
a584fe8a | 3692 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); |
daee63dd | 3693 | |
3694 | /* Actually do the restores now. */ | |
bac38c40 | 3695 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
cc858176 | 3696 | if (regs_ever_live[i] |
3697 | || (! TARGET_64BIT && regs_ever_live[i + 1])) | |
3698 | { | |
3699 | rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); | |
3700 | rtx dest = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 3701 | emit_move_insn (dest, src); |
cc858176 | 3702 | } |
87ad11b0 | 3703 | } |
daee63dd | 3704 | |
14660146 | 3705 | /* Emit a blockage insn here to keep these insns from being moved to |
3706 | an earlier spot in the epilogue, or into the main instruction stream. | |
3707 | ||
3708 | This is necessary as we must not cut the stack back before all the | |
3709 | restores are finished. */ | |
3710 | emit_insn (gen_blockage ()); | |
daee63dd | 3711 | |
9840d99d | 3712 | /* Reset stack pointer (and possibly frame pointer). The stack |
42819d4e | 3713 | pointer is initially set to fp + 64 to avoid a race condition. */ |
58361f39 | 3714 | if (frame_pointer_needed) |
87ad11b0 | 3715 | { |
cc858176 | 3716 | rtx delta = GEN_INT (-64); |
a584fe8a | 3717 | |
3718 | set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0); | |
3719 | emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta)); | |
87ad11b0 | 3720 | } |
daee63dd | 3721 | /* If we were deferring a callee register restore, do it now. */ |
58361f39 | 3722 | else if (merge_sp_adjust_with_load) |
3723 | { | |
3724 | rtx delta = GEN_INT (-actual_fsize); | |
cc858176 | 3725 | rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load); |
a584fe8a | 3726 | |
3727 | emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)); | |
58361f39 | 3728 | } |
daee63dd | 3729 | else if (actual_fsize != 0) |
a584fe8a | 3730 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
3731 | - actual_fsize, 0); | |
58361f39 | 3732 | |
3733 | /* If we haven't restored %r2 yet (no frame pointer, and a stack | |
3734 | frame greater than 8k), do so now. */ | |
3735 | if (ret_off != 0) | |
6a2c16d6 | 3736 | load_reg (2, ret_off, STACK_POINTER_REGNUM); |
a584fe8a | 3737 | |
3738 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3739 | { | |
3740 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
3741 | ||
3742 | emit_insn (gen_blockage ()); | |
3743 | emit_insn (TARGET_64BIT | |
3744 | ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa) | |
3745 | : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa)); | |
3746 | } | |
87ad11b0 | 3747 | } |
3748 | ||
d7e2f694 | 3749 | rtx |
3750 | hppa_pic_save_rtx () | |
cf3de5bb | 3751 | { |
d7e2f694 | 3752 | return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM); |
df6edefa | 3753 | } |
3754 | ||
3755 | void | |
3756 | hppa_profile_hook (label_no) | |
b8a21949 | 3757 | int label_no; |
df6edefa | 3758 | { |
a9ac13e4 | 3759 | rtx begin_label_rtx, call_insn; |
3760 | char begin_label_name[16]; | |
df6edefa | 3761 | |
a9ac13e4 | 3762 | ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL, |
b8a21949 | 3763 | label_no); |
a9ac13e4 | 3764 | begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name)); |
df6edefa | 3765 | |
3766 | if (TARGET_64BIT) | |
3767 | emit_move_insn (arg_pointer_rtx, | |
3768 | gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, | |
3769 | GEN_INT (64))); | |
3770 | ||
df6edefa | 3771 | emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2)); |
3772 | ||
3773 | #ifndef NO_PROFILE_COUNTERS | |
3774 | { | |
3775 | rtx count_label_rtx, addr, r24; | |
a9ac13e4 | 3776 | char count_label_name[16]; |
df6edefa | 3777 | |
a9ac13e4 | 3778 | ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no); |
3779 | count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name)); | |
df6edefa | 3780 | |
831a12d9 | 3781 | addr = force_reg (Pmode, count_label_rtx); |
df6edefa | 3782 | r24 = gen_rtx_REG (Pmode, 24); |
3783 | emit_move_insn (r24, addr); | |
3784 | ||
3785 | /* %r25 is set from within the output pattern. */ | |
3786 | call_insn = | |
3787 | emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"), | |
3788 | GEN_INT (TARGET_64BIT ? 24 : 12), | |
a9ac13e4 | 3789 | begin_label_rtx)); |
df6edefa | 3790 | |
3791 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24); | |
3792 | } | |
3793 | #else | |
3794 | /* %r25 is set from within the output pattern. */ | |
3795 | call_insn = | |
3796 | emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"), | |
3797 | GEN_INT (TARGET_64BIT ? 16 : 8), | |
a9ac13e4 | 3798 | begin_label_rtx)); |
df6edefa | 3799 | #endif |
3800 | ||
3801 | /* Indicate the _mcount call cannot throw, nor will it execute a | |
3802 | non-local goto. */ | |
3803 | REG_NOTES (call_insn) | |
3804 | = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn)); | |
3805 | ||
3806 | if (flag_pic) | |
3807 | { | |
3808 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx); | |
3809 | if (TARGET_64BIT) | |
3810 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx); | |
3811 | ||
d7e2f694 | 3812 | emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ()); |
df6edefa | 3813 | } |
cf3de5bb | 3814 | } |
3815 | ||
e07ff380 | 3816 | /* Fetch the return address for the frame COUNT steps up from |
3817 | the current frame, after the prologue. FRAMEADDR is the | |
3818 | frame pointer of the COUNT frame. | |
3819 | ||
f49b2e77 | 3820 | We want to ignore any export stub remnants here. To handle this, |
3821 | we examine the code at the return address, and if it is an export | |
3822 | stub, we return a memory rtx for the stub return address stored | |
3823 | at frame-24. | |
a6c6fd6c | 3824 | |
3825 | The value returned is used in two different ways: | |
3826 | ||
3827 | 1. To find a function's caller. | |
3828 | ||
3829 | 2. To change the return address for a function. | |
3830 | ||
3831 | This function handles most instances of case 1; however, it will | |
3832 | fail if there are two levels of stubs to execute on the return | |
3833 | path. The only way I believe that can happen is if the return value | |
3834 | needs a parameter relocation, which never happens for C code. | |
3835 | ||
3836 | This function handles most instances of case 2; however, it will | |
3837 | fail if we did not originally have stub code on the return path | |
f49b2e77 | 3838 | but will need stub code on the new return path. This can happen if |
a6c6fd6c | 3839 | the caller & callee are both in the main program, but the new |
f49b2e77 | 3840 | return location is in a shared library. */ |
e07ff380 | 3841 | |
3842 | rtx | |
3843 | return_addr_rtx (count, frameaddr) | |
f49b2e77 | 3844 | int count; |
e07ff380 | 3845 | rtx frameaddr; |
3846 | { | |
3847 | rtx label; | |
f49b2e77 | 3848 | rtx rp; |
e07ff380 | 3849 | rtx saved_rp; |
3850 | rtx ins; | |
3851 | ||
f49b2e77 | 3852 | if (count != 0) |
3853 | return NULL_RTX; | |
b29897dd | 3854 | |
f49b2e77 | 3855 | rp = get_hard_reg_initial_val (Pmode, 2); |
e07ff380 | 3856 | |
f49b2e77 | 3857 | if (TARGET_64BIT || TARGET_NO_SPACE_REGS) |
3858 | return rp; | |
e07ff380 | 3859 | |
b29897dd | 3860 | saved_rp = gen_reg_rtx (Pmode); |
f49b2e77 | 3861 | emit_move_insn (saved_rp, rp); |
e07ff380 | 3862 | |
3863 | /* Get pointer to the instruction stream. We have to mask out the | |
3864 | privilege level from the two low order bits of the return address | |
3865 | pointer here so that ins will point to the start of the first | |
3866 | instruction that would have been executed if we returned. */ | |
f49b2e77 | 3867 | ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR)); |
e07ff380 | 3868 | label = gen_label_rtx (); |
3869 | ||
3870 | /* Check the instruction stream at the normal return address for the | |
3871 | export stub: | |
3872 | ||
3873 | 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp | |
3874 | 0x004010a1 | stub+12: ldsid (sr0,rp),r1 | |
3875 | 0x00011820 | stub+16: mtsp r1,sr0 | |
3876 | 0xe0400002 | stub+20: be,n 0(sr0,rp) | |
3877 | ||
3878 | If it is an export stub, than our return address is really in | |
3879 | -24[frameaddr]. */ | |
3880 | ||
e00b80b2 | 3881 | emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE, |
3882 | NULL_RTX, SImode, 1); | |
e07ff380 | 3883 | emit_jump_insn (gen_bne (label)); |
3884 | ||
ad851752 | 3885 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)), |
e00b80b2 | 3886 | GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1); |
e07ff380 | 3887 | emit_jump_insn (gen_bne (label)); |
3888 | ||
ad851752 | 3889 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)), |
e00b80b2 | 3890 | GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1); |
e07ff380 | 3891 | emit_jump_insn (gen_bne (label)); |
3892 | ||
ad851752 | 3893 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)), |
e00b80b2 | 3894 | GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1); |
e07ff380 | 3895 | |
f49b2e77 | 3896 | /* If there is no export stub then just use the value saved from |
3897 | the return pointer register. */ | |
e07ff380 | 3898 | |
3899 | emit_jump_insn (gen_bne (label)); | |
3900 | ||
f49b2e77 | 3901 | /* Here we know that our return address points to an export |
e07ff380 | 3902 | stub. We don't want to return the address of the export stub, |
f49b2e77 | 3903 | but rather the return address of the export stub. That return |
3904 | address is stored at -24[frameaddr]. */ | |
e07ff380 | 3905 | |
f49b2e77 | 3906 | emit_move_insn (saved_rp, |
3907 | gen_rtx_MEM (Pmode, | |
3908 | memory_address (Pmode, | |
3909 | plus_constant (frameaddr, | |
3910 | -24)))); | |
e07ff380 | 3911 | |
3912 | emit_label (label); | |
f49b2e77 | 3913 | return saved_rp; |
e07ff380 | 3914 | } |
3915 | ||
757d4970 | 3916 | /* This is only valid once reload has completed because it depends on |
3917 | knowing exactly how much (if any) frame there is and... | |
3918 | ||
3919 | It's only valid if there is no frame marker to de-allocate and... | |
3920 | ||
3921 | It's only valid if %r2 hasn't been saved into the caller's frame | |
3922 | (we're not profiling and %r2 isn't live anywhere). */ | |
3923 | int | |
3924 | hppa_can_use_return_insn_p () | |
3925 | { | |
3926 | return (reload_completed | |
3927 | && (compute_frame_size (get_frame_size (), 0) ? 0 : 1) | |
757d4970 | 3928 | && ! regs_ever_live[2] |
3929 | && ! frame_pointer_needed); | |
3930 | } | |
3931 | ||
87ad11b0 | 3932 | void |
3933 | emit_bcond_fp (code, operand0) | |
3934 | enum rtx_code code; | |
3935 | rtx operand0; | |
3936 | { | |
ad851752 | 3937 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, |
3938 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
3939 | gen_rtx_fmt_ee (code, | |
3940 | VOIDmode, | |
3941 | gen_rtx_REG (CCFPmode, 0), | |
3942 | const0_rtx), | |
3943 | gen_rtx_LABEL_REF (VOIDmode, operand0), | |
3944 | pc_rtx))); | |
87ad11b0 | 3945 | |
3946 | } | |
3947 | ||
3948 | rtx | |
3949 | gen_cmp_fp (code, operand0, operand1) | |
3950 | enum rtx_code code; | |
3951 | rtx operand0, operand1; | |
3952 | { | |
ad851752 | 3953 | return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0), |
3954 | gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1)); | |
87ad11b0 | 3955 | } |
3956 | ||
8b49b3c7 | 3957 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
3958 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
3959 | ||
747af5e7 | 3960 | static int |
8b49b3c7 | 3961 | pa_adjust_cost (insn, link, dep_insn, cost) |
3962 | rtx insn; | |
3963 | rtx link; | |
3964 | rtx dep_insn; | |
3965 | int cost; | |
3966 | { | |
43048d2c | 3967 | enum attr_type attr_type; |
3968 | ||
cde3e16c | 3969 | /* Don't adjust costs for a pa8000 chip, also do not adjust any |
3970 | true dependencies as they are described with bypasses now. */ | |
3971 | if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0) | |
342aabd9 | 3972 | return cost; |
3973 | ||
d402da4b | 3974 | if (! recog_memoized (insn)) |
3975 | return 0; | |
8b49b3c7 | 3976 | |
43048d2c | 3977 | attr_type = get_attr_type (insn); |
3978 | ||
cde3e16c | 3979 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI) |
8b49b3c7 | 3980 | { |
3981 | /* Anti dependency; DEP_INSN reads a register that INSN writes some | |
3982 | cycles later. */ | |
3983 | ||
43048d2c | 3984 | if (attr_type == TYPE_FPLOAD) |
8b49b3c7 | 3985 | { |
d402da4b | 3986 | rtx pat = PATTERN (insn); |
3987 | rtx dep_pat = PATTERN (dep_insn); | |
3988 | if (GET_CODE (pat) == PARALLEL) | |
3989 | { | |
3990 | /* This happens for the fldXs,mb patterns. */ | |
3991 | pat = XVECEXP (pat, 0, 0); | |
3992 | } | |
3993 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
8b49b3c7 | 3994 | /* If this happens, we have to extend this to schedule |
d402da4b | 3995 | optimally. Return 0 for now. */ |
3996 | return 0; | |
8b49b3c7 | 3997 | |
d402da4b | 3998 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) |
8b49b3c7 | 3999 | { |
d402da4b | 4000 | if (! recog_memoized (dep_insn)) |
4001 | return 0; | |
8b49b3c7 | 4002 | switch (get_attr_type (dep_insn)) |
4003 | { | |
4004 | case TYPE_FPALU: | |
134b4858 | 4005 | case TYPE_FPMULSGL: |
4006 | case TYPE_FPMULDBL: | |
8b49b3c7 | 4007 | case TYPE_FPDIVSGL: |
4008 | case TYPE_FPDIVDBL: | |
4009 | case TYPE_FPSQRTSGL: | |
4010 | case TYPE_FPSQRTDBL: | |
d402da4b | 4011 | /* A fpload can't be issued until one cycle before a |
01cc3b75 | 4012 | preceding arithmetic operation has finished if |
d402da4b | 4013 | the target of the fpload is any of the sources |
4014 | (or destination) of the arithmetic operation. */ | |
cde3e16c | 4015 | return insn_default_latency (dep_insn) - 1; |
134b4858 | 4016 | |
4017 | default: | |
4018 | return 0; | |
4019 | } | |
4020 | } | |
4021 | } | |
43048d2c | 4022 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4023 | { |
4024 | rtx pat = PATTERN (insn); | |
4025 | rtx dep_pat = PATTERN (dep_insn); | |
4026 | if (GET_CODE (pat) == PARALLEL) | |
4027 | { | |
4028 | /* This happens for the fldXs,mb patterns. */ | |
4029 | pat = XVECEXP (pat, 0, 0); | |
4030 | } | |
4031 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4032 | /* If this happens, we have to extend this to schedule | |
4033 | optimally. Return 0 for now. */ | |
4034 | return 0; | |
4035 | ||
4036 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) | |
4037 | { | |
4038 | if (! recog_memoized (dep_insn)) | |
4039 | return 0; | |
4040 | switch (get_attr_type (dep_insn)) | |
4041 | { | |
4042 | case TYPE_FPDIVSGL: | |
4043 | case TYPE_FPDIVDBL: | |
4044 | case TYPE_FPSQRTSGL: | |
4045 | case TYPE_FPSQRTDBL: | |
4046 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4047 | preceding divide or sqrt operation has finished if |
134b4858 | 4048 | the target of the ALU flop is any of the sources |
4049 | (or destination) of the divide or sqrt operation. */ | |
cde3e16c | 4050 | return insn_default_latency (dep_insn) - 2; |
8b49b3c7 | 4051 | |
4052 | default: | |
4053 | return 0; | |
4054 | } | |
4055 | } | |
4056 | } | |
4057 | ||
4058 | /* For other anti dependencies, the cost is 0. */ | |
4059 | return 0; | |
4060 | } | |
134b4858 | 4061 | else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) |
4062 | { | |
4063 | /* Output dependency; DEP_INSN writes a register that INSN writes some | |
4064 | cycles later. */ | |
43048d2c | 4065 | if (attr_type == TYPE_FPLOAD) |
134b4858 | 4066 | { |
4067 | rtx pat = PATTERN (insn); | |
4068 | rtx dep_pat = PATTERN (dep_insn); | |
4069 | if (GET_CODE (pat) == PARALLEL) | |
4070 | { | |
4071 | /* This happens for the fldXs,mb patterns. */ | |
4072 | pat = XVECEXP (pat, 0, 0); | |
4073 | } | |
4074 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4075 | /* If this happens, we have to extend this to schedule | |
4076 | optimally. Return 0 for now. */ | |
4077 | return 0; | |
4078 | ||
4079 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4080 | { | |
4081 | if (! recog_memoized (dep_insn)) | |
4082 | return 0; | |
4083 | switch (get_attr_type (dep_insn)) | |
4084 | { | |
4085 | case TYPE_FPALU: | |
4086 | case TYPE_FPMULSGL: | |
4087 | case TYPE_FPMULDBL: | |
4088 | case TYPE_FPDIVSGL: | |
4089 | case TYPE_FPDIVDBL: | |
4090 | case TYPE_FPSQRTSGL: | |
4091 | case TYPE_FPSQRTDBL: | |
4092 | /* A fpload can't be issued until one cycle before a | |
01cc3b75 | 4093 | preceding arithmetic operation has finished if |
134b4858 | 4094 | the target of the fpload is the destination of the |
bea4bad2 | 4095 | arithmetic operation. |
4096 | ||
4097 | Exception: For PA7100LC, PA7200 and PA7300, the cost | |
4098 | is 3 cycles, unless they bundle together. We also | |
4099 | pay the penalty if the second insn is a fpload. */ | |
cde3e16c | 4100 | return insn_default_latency (dep_insn) - 1; |
8b49b3c7 | 4101 | |
134b4858 | 4102 | default: |
4103 | return 0; | |
4104 | } | |
4105 | } | |
4106 | } | |
43048d2c | 4107 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4108 | { |
4109 | rtx pat = PATTERN (insn); | |
4110 | rtx dep_pat = PATTERN (dep_insn); | |
4111 | if (GET_CODE (pat) == PARALLEL) | |
4112 | { | |
4113 | /* This happens for the fldXs,mb patterns. */ | |
4114 | pat = XVECEXP (pat, 0, 0); | |
4115 | } | |
4116 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4117 | /* If this happens, we have to extend this to schedule | |
4118 | optimally. Return 0 for now. */ | |
4119 | return 0; | |
4120 | ||
4121 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4122 | { | |
4123 | if (! recog_memoized (dep_insn)) | |
4124 | return 0; | |
4125 | switch (get_attr_type (dep_insn)) | |
4126 | { | |
4127 | case TYPE_FPDIVSGL: | |
4128 | case TYPE_FPDIVDBL: | |
4129 | case TYPE_FPSQRTSGL: | |
4130 | case TYPE_FPSQRTDBL: | |
4131 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4132 | preceding divide or sqrt operation has finished if |
134b4858 | 4133 | the target of the ALU flop is also the target of |
3398e91d | 4134 | the divide or sqrt operation. */ |
cde3e16c | 4135 | return insn_default_latency (dep_insn) - 2; |
134b4858 | 4136 | |
4137 | default: | |
4138 | return 0; | |
4139 | } | |
4140 | } | |
4141 | } | |
4142 | ||
4143 | /* For other output dependencies, the cost is 0. */ | |
4144 | return 0; | |
4145 | } | |
4146 | else | |
4147 | abort (); | |
8b49b3c7 | 4148 | } |
87ad11b0 | 4149 | |
747af5e7 | 4150 | /* Adjust scheduling priorities. We use this to try and keep addil |
4151 | and the next use of %r1 close together. */ | |
4152 | static int | |
4153 | pa_adjust_priority (insn, priority) | |
4154 | rtx insn; | |
4155 | int priority; | |
4156 | { | |
4157 | rtx set = single_set (insn); | |
4158 | rtx src, dest; | |
4159 | if (set) | |
4160 | { | |
4161 | src = SET_SRC (set); | |
4162 | dest = SET_DEST (set); | |
4163 | if (GET_CODE (src) == LO_SUM | |
4164 | && symbolic_operand (XEXP (src, 1), VOIDmode) | |
4165 | && ! read_only_operand (XEXP (src, 1), VOIDmode)) | |
4166 | priority >>= 3; | |
4167 | ||
4168 | else if (GET_CODE (src) == MEM | |
4169 | && GET_CODE (XEXP (src, 0)) == LO_SUM | |
4170 | && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode) | |
4171 | && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode)) | |
4172 | priority >>= 1; | |
4173 | ||
4174 | else if (GET_CODE (dest) == MEM | |
4175 | && GET_CODE (XEXP (dest, 0)) == LO_SUM | |
4176 | && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode) | |
4177 | && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)) | |
4178 | priority >>= 3; | |
4179 | } | |
4180 | return priority; | |
4181 | } | |
4182 | ||
4183 | /* The 700 can only issue a single insn at a time. | |
4184 | The 7XXX processors can issue two insns at a time. | |
4185 | The 8000 can issue 4 insns at a time. */ | |
4186 | static int | |
4187 | pa_issue_rate () | |
4188 | { | |
4189 | switch (pa_cpu) | |
4190 | { | |
4191 | case PROCESSOR_700: return 1; | |
4192 | case PROCESSOR_7100: return 2; | |
4193 | case PROCESSOR_7100LC: return 2; | |
4194 | case PROCESSOR_7200: return 2; | |
bea4bad2 | 4195 | case PROCESSOR_7300: return 2; |
747af5e7 | 4196 | case PROCESSOR_8000: return 4; |
4197 | ||
4198 | default: | |
4199 | abort (); | |
4200 | } | |
4201 | } | |
4202 | ||
4203 | ||
4204 | ||
58e17b0b | 4205 | /* Return any length adjustment needed by INSN which already has its length |
6d36483b | 4206 | computed as LENGTH. Return zero if no adjustment is necessary. |
58e17b0b | 4207 | |
5fbd5940 | 4208 | For the PA: function calls, millicode calls, and backwards short |
6d36483b | 4209 | conditional branches with unfilled delay slots need an adjustment by +1 |
5fbd5940 | 4210 | (to account for the NOP which will be inserted into the instruction stream). |
58e17b0b | 4211 | |
4212 | Also compute the length of an inline block move here as it is too | |
5fbd5940 | 4213 | complicated to express as a length attribute in pa.md. */ |
58e17b0b | 4214 | int |
4215 | pa_adjust_insn_length (insn, length) | |
4216 | rtx insn; | |
4217 | int length; | |
4218 | { | |
4219 | rtx pat = PATTERN (insn); | |
4220 | ||
5fbd5940 | 4221 | /* Call insns which are *not* indirect and have unfilled delay slots. */ |
58e17b0b | 4222 | if (GET_CODE (insn) == CALL_INSN) |
5fbd5940 | 4223 | { |
4224 | ||
4225 | if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL | |
4226 | && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF) | |
5a1231ef | 4227 | return 4; |
5fbd5940 | 4228 | else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET |
4229 | && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0)) | |
4230 | == SYMBOL_REF) | |
5a1231ef | 4231 | return 4; |
5fbd5940 | 4232 | else |
4233 | return 0; | |
4234 | } | |
9840d99d | 4235 | /* Jumps inside switch tables which have unfilled delay slots |
3b1e673e | 4236 | also need adjustment. */ |
4237 | else if (GET_CODE (insn) == JUMP_INSN | |
4238 | && simplejump_p (insn) | |
0708e381 | 4239 | && GET_MODE (insn) == SImode) |
3b1e673e | 4240 | return 4; |
58e17b0b | 4241 | /* Millicode insn with an unfilled delay slot. */ |
4242 | else if (GET_CODE (insn) == INSN | |
4243 | && GET_CODE (pat) != SEQUENCE | |
4244 | && GET_CODE (pat) != USE | |
4245 | && GET_CODE (pat) != CLOBBER | |
4246 | && get_attr_type (insn) == TYPE_MILLI) | |
5a1231ef | 4247 | return 4; |
58e17b0b | 4248 | /* Block move pattern. */ |
4249 | else if (GET_CODE (insn) == INSN | |
4250 | && GET_CODE (pat) == PARALLEL | |
f2ebcf32 | 4251 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET |
58e17b0b | 4252 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM |
4253 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM | |
4254 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode | |
4255 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode) | |
5a1231ef | 4256 | return compute_movstrsi_length (insn) - 4; |
58e17b0b | 4257 | /* Conditional branch with an unfilled delay slot. */ |
5fbd5940 | 4258 | else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn)) |
4259 | { | |
4260 | /* Adjust a short backwards conditional with an unfilled delay slot. */ | |
4261 | if (GET_CODE (pat) == SET | |
5a1231ef | 4262 | && length == 4 |
5fbd5940 | 4263 | && ! forward_branch_p (insn)) |
5a1231ef | 4264 | return 4; |
546a40bd | 4265 | else if (GET_CODE (pat) == PARALLEL |
4266 | && get_attr_type (insn) == TYPE_PARALLEL_BRANCH | |
4267 | && length == 4) | |
4268 | return 4; | |
5fbd5940 | 4269 | /* Adjust dbra insn with short backwards conditional branch with |
6d36483b | 4270 | unfilled delay slot -- only for case where counter is in a |
6dc3b0d9 | 4271 | general register register. */ |
5fbd5940 | 4272 | else if (GET_CODE (pat) == PARALLEL |
4273 | && GET_CODE (XVECEXP (pat, 0, 1)) == SET | |
4274 | && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG | |
6d36483b | 4275 | && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0)) |
5a1231ef | 4276 | && length == 4 |
5fbd5940 | 4277 | && ! forward_branch_p (insn)) |
5a1231ef | 4278 | return 4; |
5fbd5940 | 4279 | else |
4280 | return 0; | |
4281 | } | |
546a40bd | 4282 | return 0; |
58e17b0b | 4283 | } |
4284 | ||
87ad11b0 | 4285 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
4286 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
4287 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
4288 | ||
4289 | void | |
4290 | print_operand (file, x, code) | |
4291 | FILE *file; | |
4292 | rtx x; | |
4293 | int code; | |
4294 | { | |
4295 | switch (code) | |
4296 | { | |
4297 | case '#': | |
4298 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
4299 | if (dbr_sequence_length () == 0) | |
4300 | fputs ("\n\tnop", file); | |
4301 | return; | |
4302 | case '*': | |
87fcb603 | 4303 | /* Output a nullification completer if there's nothing for the */ |
6d36483b | 4304 | /* delay slot or nullification is requested. */ |
87ad11b0 | 4305 | if (dbr_sequence_length () == 0 || |
4306 | (final_sequence && | |
4307 | INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))) | |
4308 | fputs (",n", file); | |
4309 | return; | |
4310 | case 'R': | |
4311 | /* Print out the second register name of a register pair. | |
4312 | I.e., R (6) => 7. */ | |
ea52c577 | 4313 | fputs (reg_names[REGNO (x) + 1], file); |
87ad11b0 | 4314 | return; |
4315 | case 'r': | |
6dc3b0d9 | 4316 | /* A register or zero. */ |
891b55b4 | 4317 | if (x == const0_rtx |
4318 | || (x == CONST0_RTX (DFmode)) | |
4319 | || (x == CONST0_RTX (SFmode))) | |
87ad11b0 | 4320 | { |
c6ae275c | 4321 | fputs ("%r0", file); |
4322 | return; | |
4323 | } | |
4324 | else | |
4325 | break; | |
4326 | case 'f': | |
6dc3b0d9 | 4327 | /* A register or zero (floating point). */ |
c6ae275c | 4328 | if (x == const0_rtx |
4329 | || (x == CONST0_RTX (DFmode)) | |
4330 | || (x == CONST0_RTX (SFmode))) | |
4331 | { | |
4332 | fputs ("%fr0", file); | |
87ad11b0 | 4333 | return; |
4334 | } | |
4335 | else | |
4336 | break; | |
2d14b1f0 | 4337 | case 'A': |
4338 | { | |
4339 | rtx xoperands[2]; | |
4340 | ||
4341 | xoperands[0] = XEXP (XEXP (x, 0), 0); | |
4342 | xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0); | |
4343 | output_global_address (file, xoperands[1], 0); | |
4344 | fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]); | |
4345 | return; | |
4346 | } | |
4347 | ||
c8975385 | 4348 | case 'C': /* Plain (C)ondition */ |
87ad11b0 | 4349 | case 'X': |
4350 | switch (GET_CODE (x)) | |
6d36483b | 4351 | { |
87ad11b0 | 4352 | case EQ: |
9c0ac0fd | 4353 | fputs ("=", file); break; |
87ad11b0 | 4354 | case NE: |
9c0ac0fd | 4355 | fputs ("<>", file); break; |
87ad11b0 | 4356 | case GT: |
9c0ac0fd | 4357 | fputs (">", file); break; |
87ad11b0 | 4358 | case GE: |
9c0ac0fd | 4359 | fputs (">=", file); break; |
87ad11b0 | 4360 | case GEU: |
9c0ac0fd | 4361 | fputs (">>=", file); break; |
87ad11b0 | 4362 | case GTU: |
9c0ac0fd | 4363 | fputs (">>", file); break; |
87ad11b0 | 4364 | case LT: |
9c0ac0fd | 4365 | fputs ("<", file); break; |
87ad11b0 | 4366 | case LE: |
9c0ac0fd | 4367 | fputs ("<=", file); break; |
87ad11b0 | 4368 | case LEU: |
9c0ac0fd | 4369 | fputs ("<<=", file); break; |
87ad11b0 | 4370 | case LTU: |
9c0ac0fd | 4371 | fputs ("<<", file); break; |
87ad11b0 | 4372 | default: |
87ad11b0 | 4373 | abort (); |
4374 | } | |
4375 | return; | |
c8975385 | 4376 | case 'N': /* Condition, (N)egated */ |
87ad11b0 | 4377 | switch (GET_CODE (x)) |
4378 | { | |
4379 | case EQ: | |
9c0ac0fd | 4380 | fputs ("<>", file); break; |
87ad11b0 | 4381 | case NE: |
9c0ac0fd | 4382 | fputs ("=", file); break; |
87ad11b0 | 4383 | case GT: |
9c0ac0fd | 4384 | fputs ("<=", file); break; |
87ad11b0 | 4385 | case GE: |
9c0ac0fd | 4386 | fputs ("<", file); break; |
87ad11b0 | 4387 | case GEU: |
9c0ac0fd | 4388 | fputs ("<<", file); break; |
87ad11b0 | 4389 | case GTU: |
9c0ac0fd | 4390 | fputs ("<<=", file); break; |
87ad11b0 | 4391 | case LT: |
9c0ac0fd | 4392 | fputs (">=", file); break; |
87ad11b0 | 4393 | case LE: |
9c0ac0fd | 4394 | fputs (">", file); break; |
87ad11b0 | 4395 | case LEU: |
9c0ac0fd | 4396 | fputs (">>", file); break; |
87ad11b0 | 4397 | case LTU: |
9c0ac0fd | 4398 | fputs (">>=", file); break; |
87ad11b0 | 4399 | default: |
87ad11b0 | 4400 | abort (); |
4401 | } | |
4402 | return; | |
ea52c577 | 4403 | /* For floating point comparisons. Note that the output |
4404 | predicates are the complement of the desired mode. */ | |
61230bc9 | 4405 | case 'Y': |
4406 | switch (GET_CODE (x)) | |
4407 | { | |
4408 | case EQ: | |
9c0ac0fd | 4409 | fputs ("!=", file); break; |
61230bc9 | 4410 | case NE: |
9c0ac0fd | 4411 | fputs ("=", file); break; |
61230bc9 | 4412 | case GT: |
32509e56 | 4413 | fputs ("!>", file); break; |
61230bc9 | 4414 | case GE: |
32509e56 | 4415 | fputs ("!>=", file); break; |
61230bc9 | 4416 | case LT: |
32509e56 | 4417 | fputs ("!<", file); break; |
61230bc9 | 4418 | case LE: |
32509e56 | 4419 | fputs ("!<=", file); break; |
4420 | case LTGT: | |
4421 | fputs ("!<>", file); break; | |
4422 | case UNLE: | |
85837adc | 4423 | fputs (">", file); break; |
32509e56 | 4424 | case UNLT: |
4425 | fputs (">=", file); break; | |
4426 | case UNGE: | |
4427 | fputs ("<", file); break; | |
4428 | case UNGT: | |
4429 | fputs ("<=", file); break; | |
4430 | case UNEQ: | |
4431 | fputs ("<>", file); break; | |
4432 | case UNORDERED: | |
4433 | fputs ("<=>", file); break; | |
4434 | case ORDERED: | |
4435 | fputs ("!<=>", file); break; | |
61230bc9 | 4436 | default: |
61230bc9 | 4437 | abort (); |
4438 | } | |
4439 | return; | |
c8975385 | 4440 | case 'S': /* Condition, operands are (S)wapped. */ |
4441 | switch (GET_CODE (x)) | |
4442 | { | |
4443 | case EQ: | |
9c0ac0fd | 4444 | fputs ("=", file); break; |
c8975385 | 4445 | case NE: |
9c0ac0fd | 4446 | fputs ("<>", file); break; |
c8975385 | 4447 | case GT: |
9c0ac0fd | 4448 | fputs ("<", file); break; |
c8975385 | 4449 | case GE: |
9c0ac0fd | 4450 | fputs ("<=", file); break; |
c8975385 | 4451 | case GEU: |
9c0ac0fd | 4452 | fputs ("<<=", file); break; |
c8975385 | 4453 | case GTU: |
9c0ac0fd | 4454 | fputs ("<<", file); break; |
c8975385 | 4455 | case LT: |
9c0ac0fd | 4456 | fputs (">", file); break; |
c8975385 | 4457 | case LE: |
9c0ac0fd | 4458 | fputs (">=", file); break; |
c8975385 | 4459 | case LEU: |
9c0ac0fd | 4460 | fputs (">>=", file); break; |
c8975385 | 4461 | case LTU: |
9c0ac0fd | 4462 | fputs (">>", file); break; |
c8975385 | 4463 | default: |
c8975385 | 4464 | abort (); |
6d36483b | 4465 | } |
c8975385 | 4466 | return; |
4467 | case 'B': /* Condition, (B)oth swapped and negate. */ | |
4468 | switch (GET_CODE (x)) | |
4469 | { | |
4470 | case EQ: | |
9c0ac0fd | 4471 | fputs ("<>", file); break; |
c8975385 | 4472 | case NE: |
9c0ac0fd | 4473 | fputs ("=", file); break; |
c8975385 | 4474 | case GT: |
9c0ac0fd | 4475 | fputs (">=", file); break; |
c8975385 | 4476 | case GE: |
9c0ac0fd | 4477 | fputs (">", file); break; |
c8975385 | 4478 | case GEU: |
9c0ac0fd | 4479 | fputs (">>", file); break; |
c8975385 | 4480 | case GTU: |
9c0ac0fd | 4481 | fputs (">>=", file); break; |
c8975385 | 4482 | case LT: |
9c0ac0fd | 4483 | fputs ("<=", file); break; |
c8975385 | 4484 | case LE: |
9c0ac0fd | 4485 | fputs ("<", file); break; |
c8975385 | 4486 | case LEU: |
9c0ac0fd | 4487 | fputs ("<<", file); break; |
c8975385 | 4488 | case LTU: |
9c0ac0fd | 4489 | fputs ("<<=", file); break; |
c8975385 | 4490 | default: |
c8975385 | 4491 | abort (); |
6d36483b | 4492 | } |
c8975385 | 4493 | return; |
4494 | case 'k': | |
4495 | if (GET_CODE (x) == CONST_INT) | |
4496 | { | |
96b529f2 | 4497 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x)); |
c8975385 | 4498 | return; |
4499 | } | |
ea52c577 | 4500 | abort (); |
5e3c5739 | 4501 | case 'Q': |
4502 | if (GET_CODE (x) == CONST_INT) | |
4503 | { | |
96b529f2 | 4504 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63)); |
5e3c5739 | 4505 | return; |
4506 | } | |
ea52c577 | 4507 | abort (); |
e5965947 | 4508 | case 'L': |
4509 | if (GET_CODE (x) == CONST_INT) | |
4510 | { | |
96b529f2 | 4511 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31)); |
e5965947 | 4512 | return; |
4513 | } | |
ea52c577 | 4514 | abort (); |
3a16146d | 4515 | case 'O': |
4516 | if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0) | |
4517 | { | |
4518 | fprintf (file, "%d", exact_log2 (INTVAL (x))); | |
4519 | return; | |
4520 | } | |
ea52c577 | 4521 | abort (); |
5e3c5739 | 4522 | case 'p': |
4523 | if (GET_CODE (x) == CONST_INT) | |
4524 | { | |
96b529f2 | 4525 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63)); |
5e3c5739 | 4526 | return; |
4527 | } | |
ea52c577 | 4528 | abort (); |
e5965947 | 4529 | case 'P': |
4530 | if (GET_CODE (x) == CONST_INT) | |
4531 | { | |
96b529f2 | 4532 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31)); |
e5965947 | 4533 | return; |
4534 | } | |
ea52c577 | 4535 | abort (); |
c8975385 | 4536 | case 'I': |
4537 | if (GET_CODE (x) == CONST_INT) | |
4538 | fputs ("i", file); | |
4539 | return; | |
87ad11b0 | 4540 | case 'M': |
27ef382d | 4541 | case 'F': |
87ad11b0 | 4542 | switch (GET_CODE (XEXP (x, 0))) |
4543 | { | |
4544 | case PRE_DEC: | |
4545 | case PRE_INC: | |
e4065f95 | 4546 | if (ASSEMBLER_DIALECT == 0) |
4547 | fputs ("s,mb", file); | |
4548 | else | |
4549 | fputs (",mb", file); | |
87ad11b0 | 4550 | break; |
4551 | case POST_DEC: | |
4552 | case POST_INC: | |
e4065f95 | 4553 | if (ASSEMBLER_DIALECT == 0) |
4554 | fputs ("s,ma", file); | |
4555 | else | |
4556 | fputs (",ma", file); | |
87ad11b0 | 4557 | break; |
27ef382d | 4558 | case PLUS: |
4559 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
4560 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) | |
e4065f95 | 4561 | { |
4562 | if (ASSEMBLER_DIALECT == 0) | |
4563 | fputs ("x,s", file); | |
4564 | else | |
4565 | fputs (",s", file); | |
4566 | } | |
4567 | else if (code == 'F' && ASSEMBLER_DIALECT == 0) | |
27ef382d | 4568 | fputs ("s", file); |
87ad11b0 | 4569 | break; |
4570 | default: | |
e4065f95 | 4571 | if (code == 'F' && ASSEMBLER_DIALECT == 0) |
27ef382d | 4572 | fputs ("s", file); |
87ad11b0 | 4573 | break; |
4574 | } | |
4575 | return; | |
4576 | case 'G': | |
f9333726 | 4577 | output_global_address (file, x, 0); |
4578 | return; | |
4579 | case 'H': | |
4580 | output_global_address (file, x, 1); | |
87ad11b0 | 4581 | return; |
4582 | case 0: /* Don't do anything special */ | |
4583 | break; | |
42faba01 | 4584 | case 'Z': |
4585 | { | |
4586 | unsigned op[3]; | |
fb22aedc | 4587 | compute_zdepwi_operands (INTVAL (x), op); |
42faba01 | 4588 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); |
4589 | return; | |
4590 | } | |
5e3c5739 | 4591 | case 'z': |
4592 | { | |
4593 | unsigned op[3]; | |
4594 | compute_zdepdi_operands (INTVAL (x), op); | |
4595 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); | |
4596 | return; | |
4597 | } | |
c9cc98e1 | 4598 | case 'c': |
4599 | /* We can get here from a .vtable_inherit due to our | |
4600 | CONSTANT_ADDRESS_P rejecting perfectly good constant | |
4601 | addresses. */ | |
4602 | break; | |
87ad11b0 | 4603 | default: |
4604 | abort (); | |
4605 | } | |
4606 | if (GET_CODE (x) == REG) | |
df0651dc | 4607 | { |
35661368 | 4608 | fputs (reg_names [REGNO (x)], file); |
5e3c5739 | 4609 | if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4) |
4610 | { | |
4611 | fputs ("R", file); | |
4612 | return; | |
4613 | } | |
4614 | if (FP_REG_P (x) | |
4615 | && GET_MODE_SIZE (GET_MODE (x)) <= 4 | |
4616 | && (REGNO (x) & 1) == 0) | |
35661368 | 4617 | fputs ("L", file); |
df0651dc | 4618 | } |
87ad11b0 | 4619 | else if (GET_CODE (x) == MEM) |
4620 | { | |
4621 | int size = GET_MODE_SIZE (GET_MODE (x)); | |
f7dff90d | 4622 | rtx base = NULL_RTX; |
87ad11b0 | 4623 | switch (GET_CODE (XEXP (x, 0))) |
4624 | { | |
4625 | case PRE_DEC: | |
4626 | case POST_DEC: | |
5e3c5739 | 4627 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 4628 | fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 4629 | break; |
4630 | case PRE_INC: | |
4631 | case POST_INC: | |
5e3c5739 | 4632 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 4633 | fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 4634 | break; |
4635 | default: | |
27ef382d | 4636 | if (GET_CODE (XEXP (x, 0)) == PLUS |
4637 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT) | |
34940871 | 4638 | fprintf (file, "%s(%s)", |
27ef382d | 4639 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))], |
4640 | reg_names [REGNO (XEXP (XEXP (x, 0), 1))]); | |
4641 | else if (GET_CODE (XEXP (x, 0)) == PLUS | |
4642 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) | |
34940871 | 4643 | fprintf (file, "%s(%s)", |
27ef382d | 4644 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))], |
4645 | reg_names [REGNO (XEXP (XEXP (x, 0), 0))]); | |
4646 | else | |
4647 | output_address (XEXP (x, 0)); | |
87ad11b0 | 4648 | break; |
4649 | } | |
4650 | } | |
87ad11b0 | 4651 | else |
4652 | output_addr_const (file, x); | |
4653 | } | |
4654 | ||
6dc3b0d9 | 4655 | /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */ |
87ad11b0 | 4656 | |
4657 | void | |
f9333726 | 4658 | output_global_address (file, x, round_constant) |
87ad11b0 | 4659 | FILE *file; |
4660 | rtx x; | |
f9333726 | 4661 | int round_constant; |
87ad11b0 | 4662 | { |
2ee034bc | 4663 | |
4664 | /* Imagine (high (const (plus ...))). */ | |
4665 | if (GET_CODE (x) == HIGH) | |
4666 | x = XEXP (x, 0); | |
4667 | ||
611a88e1 | 4668 | if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode)) |
87ad11b0 | 4669 | assemble_name (file, XSTR (x, 0)); |
b4a7bf10 | 4670 | else if (GET_CODE (x) == SYMBOL_REF && !flag_pic) |
87ad11b0 | 4671 | { |
4672 | assemble_name (file, XSTR (x, 0)); | |
9c0ac0fd | 4673 | fputs ("-$global$", file); |
87ad11b0 | 4674 | } |
4675 | else if (GET_CODE (x) == CONST) | |
4676 | { | |
611a88e1 | 4677 | const char *sep = ""; |
87ad11b0 | 4678 | int offset = 0; /* assembler wants -$global$ at end */ |
33ae0dba | 4679 | rtx base = NULL_RTX; |
6d36483b | 4680 | |
87ad11b0 | 4681 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF) |
4682 | { | |
4683 | base = XEXP (XEXP (x, 0), 0); | |
4684 | output_addr_const (file, base); | |
4685 | } | |
4686 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT) | |
4687 | offset = INTVAL (XEXP (XEXP (x, 0), 0)); | |
4688 | else abort (); | |
4689 | ||
4690 | if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF) | |
4691 | { | |
4692 | base = XEXP (XEXP (x, 0), 1); | |
4693 | output_addr_const (file, base); | |
4694 | } | |
4695 | else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
ea52c577 | 4696 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); |
87ad11b0 | 4697 | else abort (); |
4698 | ||
f9333726 | 4699 | /* How bogus. The compiler is apparently responsible for |
4700 | rounding the constant if it uses an LR field selector. | |
4701 | ||
4702 | The linker and/or assembler seem a better place since | |
4703 | they have to do this kind of thing already. | |
4704 | ||
4705 | If we fail to do this, HP's optimizing linker may eliminate | |
4706 | an addil, but not update the ldw/stw/ldo instruction that | |
4707 | uses the result of the addil. */ | |
4708 | if (round_constant) | |
4709 | offset = ((offset + 0x1000) & ~0x1fff); | |
4710 | ||
87ad11b0 | 4711 | if (GET_CODE (XEXP (x, 0)) == PLUS) |
4712 | { | |
4713 | if (offset < 0) | |
4714 | { | |
4715 | offset = -offset; | |
4716 | sep = "-"; | |
4717 | } | |
4718 | else | |
4719 | sep = "+"; | |
4720 | } | |
4721 | else if (GET_CODE (XEXP (x, 0)) == MINUS | |
4722 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) | |
4723 | sep = "-"; | |
4724 | else abort (); | |
4725 | ||
611a88e1 | 4726 | if (!read_only_operand (base, VOIDmode) && !flag_pic) |
9c0ac0fd | 4727 | fputs ("-$global$", file); |
f9333726 | 4728 | if (offset) |
ea52c577 | 4729 | fprintf (file, "%s%d", sep, offset); |
87ad11b0 | 4730 | } |
4731 | else | |
4732 | output_addr_const (file, x); | |
4733 | } | |
4734 | ||
ece88821 | 4735 | static struct deferred_plabel * |
4736 | get_plabel (fname) | |
4737 | const char *fname; | |
4738 | { | |
4739 | size_t i; | |
4740 | ||
4741 | /* See if we have already put this function on the list of deferred | |
4742 | plabels. This list is generally small, so a liner search is not | |
4743 | too ugly. If it proves too slow replace it with something faster. */ | |
4744 | for (i = 0; i < n_deferred_plabels; i++) | |
4745 | if (strcmp (fname, deferred_plabels[i].name) == 0) | |
4746 | break; | |
4747 | ||
4748 | /* If the deferred plabel list is empty, or this entry was not found | |
4749 | on the list, create a new entry on the list. */ | |
4750 | if (deferred_plabels == NULL || i == n_deferred_plabels) | |
4751 | { | |
4752 | const char *real_name; | |
4753 | ||
4754 | if (deferred_plabels == 0) | |
4755 | deferred_plabels = (struct deferred_plabel *) | |
4756 | ggc_alloc (sizeof (struct deferred_plabel)); | |
4757 | else | |
4758 | deferred_plabels = (struct deferred_plabel *) | |
4759 | ggc_realloc (deferred_plabels, | |
4760 | ((n_deferred_plabels + 1) | |
4761 | * sizeof (struct deferred_plabel))); | |
4762 | ||
4763 | i = n_deferred_plabels++; | |
4764 | deferred_plabels[i].internal_label = gen_label_rtx (); | |
4765 | deferred_plabels[i].name = ggc_strdup (fname); | |
4766 | ||
4767 | /* Gross. We have just implicitly taken the address of this function, | |
4768 | mark it as such. */ | |
4769 | real_name = (*targetm.strip_name_encoding) (fname); | |
4770 | TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1; | |
4771 | } | |
4772 | ||
4773 | return &deferred_plabels[i]; | |
4774 | } | |
4775 | ||
5cc6b2bc | 4776 | void |
4777 | output_deferred_plabels (file) | |
4778 | FILE *file; | |
4779 | { | |
e11bd7e5 | 4780 | size_t i; |
5cc6b2bc | 4781 | /* If we have deferred plabels, then we need to switch into the data |
4782 | section and align it to a 4 byte boundary before we output the | |
4783 | deferred plabels. */ | |
4784 | if (n_deferred_plabels) | |
4785 | { | |
4786 | data_section (); | |
ece88821 | 4787 | ASM_OUTPUT_ALIGN (file, TARGET_64BIT ? 3 : 2); |
5cc6b2bc | 4788 | } |
4789 | ||
4790 | /* Now output the deferred plabels. */ | |
4791 | for (i = 0; i < n_deferred_plabels; i++) | |
4792 | { | |
805e22b2 | 4793 | (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label)); |
09d688ff | 4794 | assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name), |
b70ea764 | 4795 | TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1); |
5cc6b2bc | 4796 | } |
4797 | } | |
4798 | ||
87ad11b0 | 4799 | /* HP's millicode routines mean something special to the assembler. |
4800 | Keep track of which ones we have used. */ | |
4801 | ||
c2271c34 | 4802 | enum millicodes { remI, remU, divI, divU, mulI, end1000 }; |
e750712b | 4803 | static void import_milli PARAMS ((enum millicodes)); |
ea52c577 | 4804 | static char imported[(int) end1000]; |
c2271c34 | 4805 | static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"}; |
e99c3a1d | 4806 | static const char import_string[] = ".IMPORT $$....,MILLICODE"; |
87ad11b0 | 4807 | #define MILLI_START 10 |
4808 | ||
57ed30e5 | 4809 | static void |
87ad11b0 | 4810 | import_milli (code) |
4811 | enum millicodes code; | |
4812 | { | |
4813 | char str[sizeof (import_string)]; | |
6d36483b | 4814 | |
ea52c577 | 4815 | if (!imported[(int) code]) |
87ad11b0 | 4816 | { |
ea52c577 | 4817 | imported[(int) code] = 1; |
87ad11b0 | 4818 | strcpy (str, import_string); |
ea52c577 | 4819 | strncpy (str + MILLI_START, milli_names[(int) code], 4); |
87ad11b0 | 4820 | output_asm_insn (str, 0); |
4821 | } | |
4822 | } | |
4823 | ||
6d36483b | 4824 | /* The register constraints have put the operands and return value in |
6dc3b0d9 | 4825 | the proper registers. */ |
87ad11b0 | 4826 | |
611a88e1 | 4827 | const char * |
d6686e21 | 4828 | output_mul_insn (unsignedp, insn) |
b1ca791d | 4829 | int unsignedp ATTRIBUTE_UNUSED; |
d6686e21 | 4830 | rtx insn; |
87ad11b0 | 4831 | { |
d178f670 | 4832 | import_milli (mulI); |
440c23df | 4833 | return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI")); |
87ad11b0 | 4834 | } |
4835 | ||
6dc3b0d9 | 4836 | /* Emit the rtl for doing a division by a constant. */ |
87ad11b0 | 4837 | |
d178f670 | 4838 | /* Do magic division millicodes exist for this value? */ |
e99c3a1d | 4839 | static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, |
4840 | 1, 1}; | |
87ad11b0 | 4841 | |
6d36483b | 4842 | /* We'll use an array to keep track of the magic millicodes and |
87ad11b0 | 4843 | whether or not we've used them already. [n][0] is signed, [n][1] is |
6dc3b0d9 | 4844 | unsigned. */ |
87ad11b0 | 4845 | |
87ad11b0 | 4846 | static int div_milli[16][2]; |
4847 | ||
4848 | int | |
4849 | div_operand (op, mode) | |
4850 | rtx op; | |
4851 | enum machine_mode mode; | |
4852 | { | |
4853 | return (mode == SImode | |
4854 | && ((GET_CODE (op) == REG && REGNO (op) == 25) | |
4855 | || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0 | |
4856 | && INTVAL (op) < 16 && magic_milli[INTVAL (op)]))); | |
4857 | } | |
4858 | ||
4859 | int | |
4860 | emit_hpdiv_const (operands, unsignedp) | |
4861 | rtx *operands; | |
4862 | int unsignedp; | |
4863 | { | |
4864 | if (GET_CODE (operands[2]) == CONST_INT | |
4865 | && INTVAL (operands[2]) > 0 | |
4866 | && INTVAL (operands[2]) < 16 | |
4867 | && magic_milli[INTVAL (operands[2])]) | |
4868 | { | |
2013ddf6 | 4869 | rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31); |
4870 | ||
ad851752 | 4871 | emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]); |
87ad11b0 | 4872 | emit |
4873 | (gen_rtx | |
4874 | (PARALLEL, VOIDmode, | |
c2078db8 | 4875 | gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29), |
ad851752 | 4876 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, |
4877 | SImode, | |
4878 | gen_rtx_REG (SImode, 26), | |
4879 | operands[2])), | |
c2078db8 | 4880 | gen_rtx_CLOBBER (VOIDmode, operands[4]), |
ad851752 | 4881 | gen_rtx_CLOBBER (VOIDmode, operands[3]), |
4882 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)), | |
4883 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)), | |
2013ddf6 | 4884 | gen_rtx_CLOBBER (VOIDmode, ret)))); |
ad851752 | 4885 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 29)); |
87ad11b0 | 4886 | return 1; |
4887 | } | |
4888 | return 0; | |
4889 | } | |
4890 | ||
611a88e1 | 4891 | const char * |
d6686e21 | 4892 | output_div_insn (operands, unsignedp, insn) |
87ad11b0 | 4893 | rtx *operands; |
4894 | int unsignedp; | |
d6686e21 | 4895 | rtx insn; |
87ad11b0 | 4896 | { |
4897 | int divisor; | |
6d36483b | 4898 | |
4899 | /* If the divisor is a constant, try to use one of the special | |
87ad11b0 | 4900 | opcodes .*/ |
4901 | if (GET_CODE (operands[0]) == CONST_INT) | |
4902 | { | |
d6686e21 | 4903 | static char buf[100]; |
87ad11b0 | 4904 | divisor = INTVAL (operands[0]); |
4905 | if (!div_milli[divisor][unsignedp]) | |
4906 | { | |
d6686e21 | 4907 | div_milli[divisor][unsignedp] = 1; |
87ad11b0 | 4908 | if (unsignedp) |
4909 | output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands); | |
4910 | else | |
4911 | output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands); | |
87ad11b0 | 4912 | } |
4913 | if (unsignedp) | |
d6686e21 | 4914 | { |
96b529f2 | 4915 | sprintf (buf, "$$divU_"); |
4916 | sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0])); | |
c7a4e712 | 4917 | return output_millicode_call (insn, |
ad851752 | 4918 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 4919 | } |
4920 | else | |
4921 | { | |
96b529f2 | 4922 | sprintf (buf, "$$divI_"); |
4923 | sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0])); | |
c7a4e712 | 4924 | return output_millicode_call (insn, |
ad851752 | 4925 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 4926 | } |
87ad11b0 | 4927 | } |
6dc3b0d9 | 4928 | /* Divisor isn't a special constant. */ |
87ad11b0 | 4929 | else |
4930 | { | |
4931 | if (unsignedp) | |
4932 | { | |
4933 | import_milli (divU); | |
c7a4e712 | 4934 | return output_millicode_call (insn, |
ad851752 | 4935 | gen_rtx_SYMBOL_REF (SImode, "$$divU")); |
87ad11b0 | 4936 | } |
4937 | else | |
4938 | { | |
4939 | import_milli (divI); | |
c7a4e712 | 4940 | return output_millicode_call (insn, |
ad851752 | 4941 | gen_rtx_SYMBOL_REF (SImode, "$$divI")); |
87ad11b0 | 4942 | } |
4943 | } | |
4944 | } | |
4945 | ||
6dc3b0d9 | 4946 | /* Output a $$rem millicode to do mod. */ |
87ad11b0 | 4947 | |
611a88e1 | 4948 | const char * |
d6686e21 | 4949 | output_mod_insn (unsignedp, insn) |
87ad11b0 | 4950 | int unsignedp; |
d6686e21 | 4951 | rtx insn; |
87ad11b0 | 4952 | { |
4953 | if (unsignedp) | |
4954 | { | |
4955 | import_milli (remU); | |
c7a4e712 | 4956 | return output_millicode_call (insn, |
ad851752 | 4957 | gen_rtx_SYMBOL_REF (SImode, "$$remU")); |
87ad11b0 | 4958 | } |
4959 | else | |
4960 | { | |
4961 | import_milli (remI); | |
c7a4e712 | 4962 | return output_millicode_call (insn, |
ad851752 | 4963 | gen_rtx_SYMBOL_REF (SImode, "$$remI")); |
87ad11b0 | 4964 | } |
4965 | } | |
4966 | ||
4967 | void | |
df0651dc | 4968 | output_arg_descriptor (call_insn) |
4969 | rtx call_insn; | |
87ad11b0 | 4970 | { |
611a88e1 | 4971 | const char *arg_regs[4]; |
87ad11b0 | 4972 | enum machine_mode arg_mode; |
df0651dc | 4973 | rtx link; |
87ad11b0 | 4974 | int i, output_flag = 0; |
4975 | int regno; | |
6d36483b | 4976 | |
5e3c5739 | 4977 | /* We neither need nor want argument location descriptors for the |
5d0619cc | 4978 | 64bit runtime environment or the ELF32 environment. */ |
4979 | if (TARGET_64BIT || TARGET_ELF32) | |
5e3c5739 | 4980 | return; |
4981 | ||
87ad11b0 | 4982 | for (i = 0; i < 4; i++) |
4983 | arg_regs[i] = 0; | |
4984 | ||
738176ab | 4985 | /* Specify explicitly that no argument relocations should take place |
4986 | if using the portable runtime calling conventions. */ | |
4987 | if (TARGET_PORTABLE_RUNTIME) | |
4988 | { | |
9c0ac0fd | 4989 | fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n", |
4990 | asm_out_file); | |
738176ab | 4991 | return; |
4992 | } | |
4993 | ||
df0651dc | 4994 | if (GET_CODE (call_insn) != CALL_INSN) |
4995 | abort (); | |
4996 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1)) | |
87ad11b0 | 4997 | { |
df0651dc | 4998 | rtx use = XEXP (link, 0); |
c12afafd | 4999 | |
df0651dc | 5000 | if (! (GET_CODE (use) == USE |
5001 | && GET_CODE (XEXP (use, 0)) == REG | |
5002 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
c12afafd | 5003 | continue; |
5004 | ||
df0651dc | 5005 | arg_mode = GET_MODE (XEXP (use, 0)); |
5006 | regno = REGNO (XEXP (use, 0)); | |
87ad11b0 | 5007 | if (regno >= 23 && regno <= 26) |
372ef038 | 5008 | { |
5009 | arg_regs[26 - regno] = "GR"; | |
5010 | if (arg_mode == DImode) | |
5011 | arg_regs[25 - regno] = "GR"; | |
5012 | } | |
df0651dc | 5013 | else if (regno >= 32 && regno <= 39) |
87ad11b0 | 5014 | { |
5015 | if (arg_mode == SFmode) | |
df0651dc | 5016 | arg_regs[(regno - 32) / 2] = "FR"; |
e6ba640e | 5017 | else |
87ad11b0 | 5018 | { |
eeec72c0 | 5019 | #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED |
df0651dc | 5020 | arg_regs[(regno - 34) / 2] = "FR"; |
5021 | arg_regs[(regno - 34) / 2 + 1] = "FU"; | |
87ad11b0 | 5022 | #else |
df0651dc | 5023 | arg_regs[(regno - 34) / 2] = "FU"; |
5024 | arg_regs[(regno - 34) / 2 + 1] = "FR"; | |
87ad11b0 | 5025 | #endif |
5026 | } | |
87ad11b0 | 5027 | } |
5028 | } | |
5029 | fputs ("\t.CALL ", asm_out_file); | |
5030 | for (i = 0; i < 4; i++) | |
5031 | { | |
5032 | if (arg_regs[i]) | |
5033 | { | |
5034 | if (output_flag++) | |
5035 | fputc (',', asm_out_file); | |
5036 | fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]); | |
5037 | } | |
5038 | } | |
5039 | fputc ('\n', asm_out_file); | |
5040 | } | |
5041 | \f | |
9c0ac0fd | 5042 | /* Return the class of any secondary reload register that is needed to |
5043 | move IN into a register in class CLASS using mode MODE. | |
5044 | ||
5045 | Profiling has showed this routine and its descendants account for | |
5046 | a significant amount of compile time (~7%). So it has been | |
5047 | optimized to reduce redundant computations and eliminate useless | |
5048 | function calls. | |
5049 | ||
5050 | It might be worthwhile to try and make this a leaf function too. */ | |
87ad11b0 | 5051 | |
5052 | enum reg_class | |
5053 | secondary_reload_class (class, mode, in) | |
5054 | enum reg_class class; | |
5055 | enum machine_mode mode; | |
5056 | rtx in; | |
5057 | { | |
9c0ac0fd | 5058 | int regno, is_symbolic; |
87ad11b0 | 5059 | |
b4a7bf10 | 5060 | /* Trying to load a constant into a FP register during PIC code |
5061 | generation will require %r1 as a scratch register. */ | |
fc44315f | 5062 | if (flag_pic |
b4a7bf10 | 5063 | && GET_MODE_CLASS (mode) == MODE_INT |
5064 | && FP_REG_CLASS_P (class) | |
5065 | && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE)) | |
5066 | return R1_REGS; | |
5067 | ||
9c0ac0fd | 5068 | /* Profiling showed the PA port spends about 1.3% of its compilation |
5069 | time in true_regnum from calls inside secondary_reload_class. */ | |
5070 | ||
5071 | if (GET_CODE (in) == REG) | |
5072 | { | |
5073 | regno = REGNO (in); | |
5074 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5075 | regno = true_regnum (in); | |
5076 | } | |
5077 | else if (GET_CODE (in) == SUBREG) | |
5078 | regno = true_regnum (in); | |
9c0ac0fd | 5079 | else |
5080 | regno = -1; | |
5081 | ||
76a0ced5 | 5082 | /* If we have something like (mem (mem (...)), we can safely assume the |
5083 | inner MEM will end up in a general register after reloading, so there's | |
5084 | no need for a secondary reload. */ | |
5085 | if (GET_CODE (in) == MEM | |
5086 | && GET_CODE (XEXP (in, 0)) == MEM) | |
5087 | return NO_REGS; | |
5088 | ||
5089 | /* Handle out of range displacement for integer mode loads/stores of | |
5090 | FP registers. */ | |
d2498717 | 5091 | if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1) |
6d36483b | 5092 | && GET_MODE_CLASS (mode) == MODE_INT |
5093 | && FP_REG_CLASS_P (class)) | |
d6f01525 | 5094 | || (class == SHIFT_REGS && (regno <= 0 || regno >= 32))) |
9c6d4825 | 5095 | return GENERAL_REGS; |
d2c1d63d | 5096 | |
7c4b32f3 | 5097 | /* A SAR<->FP register copy requires a secondary register (GPR) as |
5098 | well as secondary memory. */ | |
5099 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5100 | && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class)) | |
5101 | || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno))))) | |
5102 | return GENERAL_REGS; | |
5103 | ||
2ee034bc | 5104 | if (GET_CODE (in) == HIGH) |
5105 | in = XEXP (in, 0); | |
5106 | ||
9c0ac0fd | 5107 | /* Profiling has showed GCC spends about 2.6% of its compilation |
5108 | time in symbolic_operand from calls inside secondary_reload_class. | |
5109 | ||
5110 | We use an inline copy and only compute its return value once to avoid | |
5111 | useless work. */ | |
5112 | switch (GET_CODE (in)) | |
5113 | { | |
5114 | rtx tmp; | |
5115 | ||
5116 | case SYMBOL_REF: | |
5117 | case LABEL_REF: | |
5118 | is_symbolic = 1; | |
5119 | break; | |
5120 | case CONST: | |
5121 | tmp = XEXP (in, 0); | |
5122 | is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF | |
5123 | || GET_CODE (XEXP (tmp, 0)) == LABEL_REF) | |
5124 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT); | |
5125 | break; | |
76a0ced5 | 5126 | |
9c0ac0fd | 5127 | default: |
5128 | is_symbolic = 0; | |
5129 | break; | |
5130 | } | |
9840d99d | 5131 | |
b4a7bf10 | 5132 | if (!flag_pic |
9c0ac0fd | 5133 | && is_symbolic |
611a88e1 | 5134 | && read_only_operand (in, VOIDmode)) |
b4a7bf10 | 5135 | return NO_REGS; |
5136 | ||
9c0ac0fd | 5137 | if (class != R1_REGS && is_symbolic) |
2ee034bc | 5138 | return R1_REGS; |
5139 | ||
d2c1d63d | 5140 | return NO_REGS; |
87ad11b0 | 5141 | } |
5142 | ||
5143 | enum direction | |
5144 | function_arg_padding (mode, type) | |
5145 | enum machine_mode mode; | |
5146 | tree type; | |
5147 | { | |
ac965869 | 5148 | if (mode == BLKmode |
5149 | || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type))) | |
5150 | { | |
5151 | /* Return none if justification is not required. */ | |
5152 | if (type | |
5153 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
5154 | && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0) | |
5155 | return none; | |
5156 | ||
5157 | /* The directions set here are ignored when a BLKmode argument larger | |
5158 | than a word is placed in a register. Different code is used for | |
5159 | the stack and registers. This makes it difficult to have a | |
5160 | consistent data representation for both the stack and registers. | |
5161 | For both runtimes, the justification and padding for arguments on | |
5162 | the stack and in registers should be identical. */ | |
5163 | if (TARGET_64BIT) | |
5164 | /* The 64-bit runtime specifies left justification for aggregates. */ | |
5165 | return upward; | |
87ad11b0 | 5166 | else |
ac965869 | 5167 | /* The 32-bit runtime architecture specifies right justification. |
5168 | When the argument is passed on the stack, the argument is padded | |
5169 | with garbage on the left. The HP compiler pads with zeros. */ | |
5170 | return downward; | |
87ad11b0 | 5171 | } |
ac965869 | 5172 | |
5173 | if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
87ad11b0 | 5174 | return downward; |
87ad11b0 | 5175 | else |
5176 | return none; | |
5177 | } | |
5178 | ||
87ad11b0 | 5179 | \f |
55f54832 | 5180 | /* Do what is necessary for `va_start'. We look at the current function |
5181 | to determine if stdargs or varargs is used and fill in an initial | |
5182 | va_list. A pointer to this constructor is returned. */ | |
87ad11b0 | 5183 | |
5184 | struct rtx_def * | |
55f54832 | 5185 | hppa_builtin_saveregs () |
87ad11b0 | 5186 | { |
01251cbc | 5187 | rtx offset, dest; |
87ad11b0 | 5188 | tree fntype = TREE_TYPE (current_function_decl); |
5189 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
5190 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
5191 | != void_type_node))) | |
5192 | ? UNITS_PER_WORD : 0); | |
5193 | ||
5194 | if (argadj) | |
5195 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
5196 | else | |
5197 | offset = current_function_arg_offset_rtx; | |
9c6d4825 | 5198 | |
5e3c5739 | 5199 | if (TARGET_64BIT) |
5200 | { | |
5201 | int i, off; | |
9840d99d | 5202 | |
5e3c5739 | 5203 | /* Adjust for varargs/stdarg differences. */ |
5204 | if (argadj) | |
5205 | offset = plus_constant (current_function_arg_offset_rtx, -argadj); | |
5206 | else | |
5207 | offset = current_function_arg_offset_rtx; | |
5208 | ||
5209 | /* We need to save %r26 .. %r19 inclusive starting at offset -64 | |
5210 | from the incoming arg pointer and growing to larger addresses. */ | |
5211 | for (i = 26, off = -64; i >= 19; i--, off += 8) | |
5212 | emit_move_insn (gen_rtx_MEM (word_mode, | |
5213 | plus_constant (arg_pointer_rtx, off)), | |
5214 | gen_rtx_REG (word_mode, i)); | |
5215 | ||
5216 | /* The incoming args pointer points just beyond the flushback area; | |
8ef587dc | 5217 | normally this is not a serious concern. However, when we are doing |
5e3c5739 | 5218 | varargs/stdargs we want to make the arg pointer point to the start |
5219 | of the incoming argument area. */ | |
5220 | emit_move_insn (virtual_incoming_args_rtx, | |
5221 | plus_constant (arg_pointer_rtx, -64)); | |
5222 | ||
5223 | /* Now return a pointer to the first anonymous argument. */ | |
5224 | return copy_to_reg (expand_binop (Pmode, add_optab, | |
5225 | virtual_incoming_args_rtx, | |
5226 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
5227 | } | |
5228 | ||
6dc3b0d9 | 5229 | /* Store general registers on the stack. */ |
ad851752 | 5230 | dest = gen_rtx_MEM (BLKmode, |
5231 | plus_constant (current_function_internal_arg_pointer, | |
5232 | -16)); | |
ab6ab77e | 5233 | set_mem_alias_set (dest, get_varargs_alias_set ()); |
2a631e19 | 5234 | set_mem_align (dest, BITS_PER_WORD); |
01251cbc | 5235 | move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD); |
5236 | ||
76a0ced5 | 5237 | /* move_block_from_reg will emit code to store the argument registers |
5238 | individually as scalar stores. | |
5239 | ||
5240 | However, other insns may later load from the same addresses for | |
ad87de1e | 5241 | a structure load (passing a struct to a varargs routine). |
76a0ced5 | 5242 | |
5243 | The alias code assumes that such aliasing can never happen, so we | |
5244 | have to keep memory referencing insns from moving up beyond the | |
5245 | last argument register store. So we emit a blockage insn here. */ | |
5246 | emit_insn (gen_blockage ()); | |
5247 | ||
9c6d4825 | 5248 | return copy_to_reg (expand_binop (Pmode, add_optab, |
5249 | current_function_internal_arg_pointer, | |
5250 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
87ad11b0 | 5251 | } |
d6f01525 | 5252 | |
72899a61 | 5253 | void |
7df226a2 | 5254 | hppa_va_start (valist, nextarg) |
72899a61 | 5255 | tree valist; |
5256 | rtx nextarg; | |
5257 | { | |
5258 | nextarg = expand_builtin_saveregs (); | |
7df226a2 | 5259 | std_expand_builtin_va_start (valist, nextarg); |
72899a61 | 5260 | } |
5261 | ||
5262 | rtx | |
5263 | hppa_va_arg (valist, type) | |
5264 | tree valist, type; | |
5265 | { | |
ac965869 | 5266 | HOST_WIDE_INT size = int_size_in_bytes (type); |
5267 | HOST_WIDE_INT ofs; | |
72899a61 | 5268 | tree t, ptr, pptr; |
5269 | ||
5e3c5739 | 5270 | if (TARGET_64BIT) |
5271 | { | |
ac965869 | 5272 | /* Every argument in PA64 is supposed to be passed by value |
5273 | (including large structs). However, as a GCC extension, we | |
5274 | pass zero and variable sized arguments by reference. Empty | |
5275 | structures are a GCC extension not supported by the HP | |
5276 | compilers. Thus, passing them by reference isn't likely | |
5277 | to conflict with the ABI. For variable sized arguments, | |
5278 | GCC doesn't have the infrastructure to allocate these to | |
5279 | registers. */ | |
5280 | ||
5281 | /* Arguments with a size greater than 8 must be aligned 0 MOD 16. */ | |
5e3c5739 | 5282 | |
5e3c5739 | 5283 | if (size > UNITS_PER_WORD) |
5284 | { | |
5285 | t = build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
5286 | build_int_2 (2 * UNITS_PER_WORD - 1, 0)); | |
9840d99d | 5287 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, |
5e3c5739 | 5288 | build_int_2 (-2 * UNITS_PER_WORD, -1)); |
5289 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t); | |
5290 | TREE_SIDE_EFFECTS (t) = 1; | |
ac965869 | 5291 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5e3c5739 | 5292 | } |
72899a61 | 5293 | |
ac965869 | 5294 | if (size > 0) |
5295 | return std_expand_builtin_va_arg (valist, type); | |
5296 | else | |
5297 | { | |
5298 | ptr = build_pointer_type (type); | |
72899a61 | 5299 | |
ac965869 | 5300 | /* Args grow upward. */ |
5301 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
5302 | build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0)); | |
5303 | TREE_SIDE_EFFECTS (t) = 1; | |
72899a61 | 5304 | |
ac965869 | 5305 | pptr = build_pointer_type (ptr); |
5306 | t = build1 (NOP_EXPR, pptr, t); | |
5307 | TREE_SIDE_EFFECTS (t) = 1; | |
72899a61 | 5308 | |
ac965869 | 5309 | t = build1 (INDIRECT_REF, ptr, t); |
5310 | TREE_SIDE_EFFECTS (t) = 1; | |
5311 | } | |
72899a61 | 5312 | } |
ac965869 | 5313 | else /* !TARGET_64BIT */ |
72899a61 | 5314 | { |
ac965869 | 5315 | ptr = build_pointer_type (type); |
72899a61 | 5316 | |
ac965869 | 5317 | /* "Large" and variable sized types are passed by reference. */ |
5318 | if (size > 8 || size <= 0) | |
5319 | { | |
5320 | /* Args grow downward. */ | |
5321 | t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist, | |
5322 | build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0)); | |
5323 | TREE_SIDE_EFFECTS (t) = 1; | |
72899a61 | 5324 | |
ac965869 | 5325 | pptr = build_pointer_type (ptr); |
5326 | t = build1 (NOP_EXPR, pptr, t); | |
5327 | TREE_SIDE_EFFECTS (t) = 1; | |
9840d99d | 5328 | |
ac965869 | 5329 | t = build1 (INDIRECT_REF, ptr, t); |
72899a61 | 5330 | TREE_SIDE_EFFECTS (t) = 1; |
5331 | } | |
ac965869 | 5332 | else |
5333 | { | |
5334 | t = build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
5335 | build_int_2 (-size, -1)); | |
5336 | ||
5337 | /* Copied from va-pa.h, but we probably don't need to align to | |
5338 | word size, since we generate and preserve that invariant. */ | |
5339 | t = build (BIT_AND_EXPR, TREE_TYPE (valist), t, | |
5340 | build_int_2 ((size > 4 ? -8 : -4), -1)); | |
5341 | ||
5342 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t); | |
5343 | TREE_SIDE_EFFECTS (t) = 1; | |
5344 | ||
5345 | ofs = (8 - size) % 4; | |
5346 | if (ofs) | |
5347 | { | |
5348 | t = build (PLUS_EXPR, TREE_TYPE (valist), t, | |
5349 | build_int_2 (ofs, 0)); | |
5350 | TREE_SIDE_EFFECTS (t) = 1; | |
5351 | } | |
72899a61 | 5352 | |
ac965869 | 5353 | t = build1 (NOP_EXPR, ptr, t); |
5354 | TREE_SIDE_EFFECTS (t) = 1; | |
5355 | } | |
72899a61 | 5356 | } |
5357 | ||
5358 | /* Calculate! */ | |
ac965869 | 5359 | return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL); |
72899a61 | 5360 | } |
5361 | ||
5362 | ||
5363 | ||
6d36483b | 5364 | /* This routine handles all the normal conditional branch sequences we |
5365 | might need to generate. It handles compare immediate vs compare | |
5366 | register, nullification of delay slots, varying length branches, | |
0d986529 | 5367 | negated branches, and all combinations of the above. It returns the |
6d36483b | 5368 | output appropriate to emit the branch corresponding to all given |
0d986529 | 5369 | parameters. */ |
5370 | ||
611a88e1 | 5371 | const char * |
0d986529 | 5372 | output_cbranch (operands, nullify, length, negated, insn) |
ece88821 | 5373 | rtx *operands; |
5374 | int nullify, length, negated; | |
5375 | rtx insn; | |
29a4502c | 5376 | { |
0d986529 | 5377 | static char buf[100]; |
5378 | int useskip = 0; | |
5379 | ||
29a4502c | 5380 | /* A conditional branch to the following instruction (eg the delay slot) is |
5381 | asking for a disaster. This can happen when not optimizing. | |
5382 | ||
5383 | In such cases it is safe to emit nothing. */ | |
5384 | ||
db3da815 | 5385 | if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn)) |
29a4502c | 5386 | return ""; |
6d36483b | 5387 | |
5fbd5940 | 5388 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
5389 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 5390 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 5391 | nullify = 1; |
5392 | ||
5393 | /* If this is a short forward conditional branch which did not get | |
5394 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 5395 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 5396 | nullify = forward_branch_p (insn); |
5397 | ||
6d36483b | 5398 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 5399 | comclr instruction. This avoids a single cycle penalty due to |
5400 | mis-predicted branch if we fall through (branch not taken). */ | |
5a1231ef | 5401 | if (length == 4 |
5fbd5940 | 5402 | && next_real_insn (insn) != 0 |
5a1231ef | 5403 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 5404 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 5405 | && nullify) |
5406 | useskip = 1; | |
5407 | ||
5408 | switch (length) | |
5409 | { | |
5fbd5940 | 5410 | /* All short conditional branches except backwards with an unfilled |
5411 | delay slot. */ | |
5a1231ef | 5412 | case 4: |
0d986529 | 5413 | if (useskip) |
e4065f95 | 5414 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
0d986529 | 5415 | else |
e4065f95 | 5416 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 5417 | if (GET_MODE (operands[1]) == DImode) |
5418 | strcat (buf, "*"); | |
0d986529 | 5419 | if (negated) |
5420 | strcat (buf, "%B3"); | |
5421 | else | |
5422 | strcat (buf, "%S3"); | |
5423 | if (useskip) | |
5a811d43 | 5424 | strcat (buf, " %2,%r1,%%r0"); |
0d986529 | 5425 | else if (nullify) |
9e49be0e | 5426 | strcat (buf, ",n %2,%r1,%0"); |
6d36483b | 5427 | else |
9e49be0e | 5428 | strcat (buf, " %2,%r1,%0"); |
0d986529 | 5429 | break; |
5430 | ||
87fcb603 | 5431 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 5432 | unfilled delay slot is treated just like a long backward branch |
5433 | with an unfilled delay slot. */ | |
5a1231ef | 5434 | case 8: |
5fbd5940 | 5435 | /* Handle weird backwards branch with a filled delay slot |
5436 | with is nullified. */ | |
5437 | if (dbr_sequence_length () != 0 | |
5438 | && ! forward_branch_p (insn) | |
5439 | && nullify) | |
5440 | { | |
e4065f95 | 5441 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 5442 | if (GET_MODE (operands[1]) == DImode) |
5443 | strcat (buf, "*"); | |
5fbd5940 | 5444 | if (negated) |
5445 | strcat (buf, "%S3"); | |
5446 | else | |
5447 | strcat (buf, "%B3"); | |
5a811d43 | 5448 | strcat (buf, ",n %2,%r1,.+12\n\tb %0"); |
5fbd5940 | 5449 | } |
43f0c1f2 | 5450 | /* Handle short backwards branch with an unfilled delay slot. |
5451 | Using a comb;nop rather than comiclr;bl saves 1 cycle for both | |
5452 | taken and untaken branches. */ | |
5453 | else if (dbr_sequence_length () == 0 | |
5454 | && ! forward_branch_p (insn) | |
47fc0706 | 5455 | && INSN_ADDRESSES_SET_P () |
5456 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
5457 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 5458 | { |
e4065f95 | 5459 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 5460 | if (GET_MODE (operands[1]) == DImode) |
5461 | strcat (buf, "*"); | |
43f0c1f2 | 5462 | if (negated) |
9e49be0e | 5463 | strcat (buf, "%B3 %2,%r1,%0%#"); |
43f0c1f2 | 5464 | else |
9e49be0e | 5465 | strcat (buf, "%S3 %2,%r1,%0%#"); |
43f0c1f2 | 5466 | } |
0d986529 | 5467 | else |
5fbd5940 | 5468 | { |
e4065f95 | 5469 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
5e3c5739 | 5470 | if (GET_MODE (operands[1]) == DImode) |
5471 | strcat (buf, "*"); | |
5fbd5940 | 5472 | if (negated) |
5473 | strcat (buf, "%S3"); | |
5474 | else | |
5475 | strcat (buf, "%B3"); | |
5476 | if (nullify) | |
5a811d43 | 5477 | strcat (buf, " %2,%r1,%%r0\n\tb,n %0"); |
5fbd5940 | 5478 | else |
5a811d43 | 5479 | strcat (buf, " %2,%r1,%%r0\n\tb %0"); |
5fbd5940 | 5480 | } |
0d986529 | 5481 | break; |
5482 | ||
c8a0e52b | 5483 | case 20: |
5484 | /* Very long branch. Right now we only handle these when not | |
5485 | optimizing. See "jump" pattern in pa.md for details. */ | |
5486 | if (optimize) | |
5487 | abort (); | |
5488 | ||
5489 | /* Create a reversed conditional branch which branches around | |
5490 | the following insns. */ | |
5491 | if (negated) | |
e4065f95 | 5492 | strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}"); |
c8a0e52b | 5493 | else |
e4065f95 | 5494 | strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}"); |
5e3c5739 | 5495 | if (GET_MODE (operands[1]) == DImode) |
5496 | { | |
5497 | if (negated) | |
5498 | strcpy (buf, | |
5499 | "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}"); | |
5500 | else | |
5501 | strcpy (buf, | |
5502 | "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}"); | |
5503 | } | |
c8a0e52b | 5504 | output_asm_insn (buf, operands); |
5505 | ||
5506 | /* Output an insn to save %r1. */ | |
5507 | output_asm_insn ("stw %%r1,-16(%%r30)", operands); | |
5508 | ||
5509 | /* Now output a very long branch to the original target. */ | |
5510 | output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands); | |
5511 | ||
5512 | /* Now restore the value of %r1 in the delay slot. We're not | |
5513 | optimizing so we know nothing else can be in the delay slot. */ | |
5514 | return "ldw -16(%%r30),%%r1"; | |
5515 | ||
5516 | case 28: | |
5517 | /* Very long branch when generating PIC code. Right now we only | |
5518 | handle these when not optimizing. See "jump" pattern in pa.md | |
5519 | for details. */ | |
5520 | if (optimize) | |
5521 | abort (); | |
5522 | ||
5523 | /* Create a reversed conditional branch which branches around | |
5524 | the following insns. */ | |
5525 | if (negated) | |
e4065f95 | 5526 | strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}"); |
c8a0e52b | 5527 | else |
e4065f95 | 5528 | strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}"); |
5e3c5739 | 5529 | if (GET_MODE (operands[1]) == DImode) |
5530 | { | |
5531 | if (negated) | |
5532 | strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}"); | |
5533 | else | |
5534 | strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}"); | |
5535 | } | |
c8a0e52b | 5536 | output_asm_insn (buf, operands); |
5537 | ||
5538 | /* Output an insn to save %r1. */ | |
5539 | output_asm_insn ("stw %%r1,-16(%%r30)", operands); | |
5540 | ||
5541 | /* Now output a very long PIC branch to the original target. */ | |
5542 | { | |
5543 | rtx xoperands[5]; | |
5544 | ||
5545 | xoperands[0] = operands[0]; | |
5546 | xoperands[1] = operands[1]; | |
5547 | xoperands[2] = operands[2]; | |
5548 | xoperands[3] = operands[3]; | |
b70ea764 | 5549 | |
5550 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
ece88821 | 5551 | if (TARGET_SOM || !TARGET_GAS) |
b70ea764 | 5552 | { |
ece88821 | 5553 | xoperands[4] = gen_label_rtx (); |
b70ea764 | 5554 | output_asm_insn ("addil L'%l0-%l4,%%r1", xoperands); |
805e22b2 | 5555 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
b70ea764 | 5556 | CODE_LABEL_NUMBER (xoperands[4])); |
5557 | output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1", xoperands); | |
5558 | } | |
5559 | else | |
5560 | { | |
5561 | output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands); | |
5562 | output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", | |
5563 | xoperands); | |
5564 | } | |
5565 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c8a0e52b | 5566 | } |
5567 | ||
5568 | /* Now restore the value of %r1 in the delay slot. We're not | |
5569 | optimizing so we know nothing else can be in the delay slot. */ | |
5570 | return "ldw -16(%%r30),%%r1"; | |
9840d99d | 5571 | |
0d986529 | 5572 | default: |
ea52c577 | 5573 | abort (); |
5fbd5940 | 5574 | } |
0d986529 | 5575 | return buf; |
5576 | } | |
5577 | ||
6d36483b | 5578 | /* This routine handles all the branch-on-bit conditional branch sequences we |
0d986529 | 5579 | might need to generate. It handles nullification of delay slots, |
5580 | varying length branches, negated branches and all combinations of the | |
5581 | above. it returns the appropriate output template to emit the branch. */ | |
5582 | ||
611a88e1 | 5583 | const char * |
0d986529 | 5584 | output_bb (operands, nullify, length, negated, insn, which) |
ece88821 | 5585 | rtx *operands ATTRIBUTE_UNUSED; |
5586 | int nullify, length, negated; | |
5587 | rtx insn; | |
5588 | int which; | |
29a4502c | 5589 | { |
0d986529 | 5590 | static char buf[100]; |
5591 | int useskip = 0; | |
5592 | ||
29a4502c | 5593 | /* A conditional branch to the following instruction (eg the delay slot) is |
5594 | asking for a disaster. I do not think this can happen as this pattern | |
6d36483b | 5595 | is only used when optimizing; jump optimization should eliminate the |
29a4502c | 5596 | jump. But be prepared just in case. */ |
6d36483b | 5597 | |
db3da815 | 5598 | if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn)) |
29a4502c | 5599 | return ""; |
6d36483b | 5600 | |
5fbd5940 | 5601 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
5602 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 5603 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 5604 | nullify = 1; |
5605 | ||
5606 | /* If this is a short forward conditional branch which did not get | |
5607 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 5608 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 5609 | nullify = forward_branch_p (insn); |
5610 | ||
6d36483b | 5611 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 5612 | extrs instruction. This avoids a single cycle penalty due to |
5613 | mis-predicted branch if we fall through (branch not taken). */ | |
5614 | ||
5a1231ef | 5615 | if (length == 4 |
5fbd5940 | 5616 | && next_real_insn (insn) != 0 |
5a1231ef | 5617 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 5618 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 5619 | && nullify) |
5620 | useskip = 1; | |
5621 | ||
5622 | switch (length) | |
5623 | { | |
5624 | ||
5fbd5940 | 5625 | /* All short conditional branches except backwards with an unfilled |
5626 | delay slot. */ | |
5a1231ef | 5627 | case 4: |
0d986529 | 5628 | if (useskip) |
e4065f95 | 5629 | strcpy (buf, "{extrs,|extrw,s,}"); |
6d36483b | 5630 | else |
0d986529 | 5631 | strcpy (buf, "bb,"); |
5e3c5739 | 5632 | if (useskip && GET_MODE (operands[0]) == DImode) |
5633 | strcpy (buf, "extrd,s,*"); | |
5634 | else if (GET_MODE (operands[0]) == DImode) | |
5635 | strcpy (buf, "bb,*"); | |
0d986529 | 5636 | if ((which == 0 && negated) |
5637 | || (which == 1 && ! negated)) | |
5638 | strcat (buf, ">="); | |
5639 | else | |
5640 | strcat (buf, "<"); | |
5641 | if (useskip) | |
5a811d43 | 5642 | strcat (buf, " %0,%1,1,%%r0"); |
0d986529 | 5643 | else if (nullify && negated) |
5644 | strcat (buf, ",n %0,%1,%3"); | |
5645 | else if (nullify && ! negated) | |
5646 | strcat (buf, ",n %0,%1,%2"); | |
5647 | else if (! nullify && negated) | |
5fbd5940 | 5648 | strcat (buf, "%0,%1,%3"); |
0d986529 | 5649 | else if (! nullify && ! negated) |
5fbd5940 | 5650 | strcat (buf, " %0,%1,%2"); |
0d986529 | 5651 | break; |
5652 | ||
87fcb603 | 5653 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 5654 | unfilled delay slot is treated just like a long backward branch |
5655 | with an unfilled delay slot. */ | |
5a1231ef | 5656 | case 8: |
5fbd5940 | 5657 | /* Handle weird backwards branch with a filled delay slot |
5658 | with is nullified. */ | |
5659 | if (dbr_sequence_length () != 0 | |
5660 | && ! forward_branch_p (insn) | |
5661 | && nullify) | |
5662 | { | |
5663 | strcpy (buf, "bb,"); | |
5e3c5739 | 5664 | if (GET_MODE (operands[0]) == DImode) |
5665 | strcat (buf, "*"); | |
5fbd5940 | 5666 | if ((which == 0 && negated) |
5667 | || (which == 1 && ! negated)) | |
5668 | strcat (buf, "<"); | |
5669 | else | |
5670 | strcat (buf, ">="); | |
5671 | if (negated) | |
5a811d43 | 5672 | strcat (buf, ",n %0,%1,.+12\n\tb %3"); |
5fbd5940 | 5673 | else |
5a811d43 | 5674 | strcat (buf, ",n %0,%1,.+12\n\tb %2"); |
5fbd5940 | 5675 | } |
43f0c1f2 | 5676 | /* Handle short backwards branch with an unfilled delay slot. |
5677 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
5678 | taken and untaken branches. */ | |
5679 | else if (dbr_sequence_length () == 0 | |
5680 | && ! forward_branch_p (insn) | |
47fc0706 | 5681 | && INSN_ADDRESSES_SET_P () |
5682 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
5683 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 5684 | { |
5685 | strcpy (buf, "bb,"); | |
5e3c5739 | 5686 | if (GET_MODE (operands[0]) == DImode) |
5687 | strcat (buf, "*"); | |
43f0c1f2 | 5688 | if ((which == 0 && negated) |
5689 | || (which == 1 && ! negated)) | |
5690 | strcat (buf, ">="); | |
5691 | else | |
5692 | strcat (buf, "<"); | |
5693 | if (negated) | |
5694 | strcat (buf, " %0,%1,%3%#"); | |
5695 | else | |
5696 | strcat (buf, " %0,%1,%2%#"); | |
5697 | } | |
0d986529 | 5698 | else |
5fbd5940 | 5699 | { |
e4065f95 | 5700 | strcpy (buf, "{extrs,|extrw,s,}"); |
5e3c5739 | 5701 | if (GET_MODE (operands[0]) == DImode) |
5702 | strcpy (buf, "extrd,s,*"); | |
5fbd5940 | 5703 | if ((which == 0 && negated) |
5704 | || (which == 1 && ! negated)) | |
5705 | strcat (buf, "<"); | |
5706 | else | |
5707 | strcat (buf, ">="); | |
5708 | if (nullify && negated) | |
c6ae275c | 5709 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %3"); |
5fbd5940 | 5710 | else if (nullify && ! negated) |
c6ae275c | 5711 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %2"); |
5fbd5940 | 5712 | else if (negated) |
5a811d43 | 5713 | strcat (buf, " %0,%1,1,%%r0\n\tb %3"); |
6d36483b | 5714 | else |
5a811d43 | 5715 | strcat (buf, " %0,%1,1,%%r0\n\tb %2"); |
5fbd5940 | 5716 | } |
0d986529 | 5717 | break; |
5718 | ||
5719 | default: | |
ea52c577 | 5720 | abort (); |
5fbd5940 | 5721 | } |
0d986529 | 5722 | return buf; |
5723 | } | |
5724 | ||
c7a4e712 | 5725 | /* This routine handles all the branch-on-variable-bit conditional branch |
5726 | sequences we might need to generate. It handles nullification of delay | |
5727 | slots, varying length branches, negated branches and all combinations | |
5728 | of the above. it returns the appropriate output template to emit the | |
5729 | branch. */ | |
5730 | ||
611a88e1 | 5731 | const char * |
c7a4e712 | 5732 | output_bvb (operands, nullify, length, negated, insn, which) |
ece88821 | 5733 | rtx *operands ATTRIBUTE_UNUSED; |
5734 | int nullify, length, negated; | |
5735 | rtx insn; | |
5736 | int which; | |
c7a4e712 | 5737 | { |
5738 | static char buf[100]; | |
5739 | int useskip = 0; | |
5740 | ||
5741 | /* A conditional branch to the following instruction (eg the delay slot) is | |
5742 | asking for a disaster. I do not think this can happen as this pattern | |
5743 | is only used when optimizing; jump optimization should eliminate the | |
5744 | jump. But be prepared just in case. */ | |
5745 | ||
5746 | if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn)) | |
5747 | return ""; | |
5748 | ||
5749 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
5750 | as it can nullify the delay slot and save a nop. */ | |
5751 | if (length == 8 && dbr_sequence_length () == 0) | |
5752 | nullify = 1; | |
5753 | ||
5754 | /* If this is a short forward conditional branch which did not get | |
5755 | its delay slot filled, the delay slot can still be nullified. */ | |
5756 | if (! nullify && length == 4 && dbr_sequence_length () == 0) | |
5757 | nullify = forward_branch_p (insn); | |
5758 | ||
5759 | /* A forward branch over a single nullified insn can be done with a | |
5760 | extrs instruction. This avoids a single cycle penalty due to | |
5761 | mis-predicted branch if we fall through (branch not taken). */ | |
5762 | ||
5763 | if (length == 4 | |
5764 | && next_real_insn (insn) != 0 | |
5765 | && get_attr_length (next_real_insn (insn)) == 4 | |
5766 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) | |
5767 | && nullify) | |
5768 | useskip = 1; | |
5769 | ||
5770 | switch (length) | |
5771 | { | |
5772 | ||
5773 | /* All short conditional branches except backwards with an unfilled | |
5774 | delay slot. */ | |
5775 | case 4: | |
5776 | if (useskip) | |
e4065f95 | 5777 | strcpy (buf, "{vextrs,|extrw,s,}"); |
c7a4e712 | 5778 | else |
e4065f95 | 5779 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 5780 | if (useskip && GET_MODE (operands[0]) == DImode) |
5781 | strcpy (buf, "extrd,s,*}"); | |
5782 | else if (GET_MODE (operands[0]) == DImode) | |
5783 | strcpy (buf, "bb,*"); | |
c7a4e712 | 5784 | if ((which == 0 && negated) |
5785 | || (which == 1 && ! negated)) | |
5786 | strcat (buf, ">="); | |
5787 | else | |
5788 | strcat (buf, "<"); | |
5789 | if (useskip) | |
e4065f95 | 5790 | strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}"); |
c7a4e712 | 5791 | else if (nullify && negated) |
e4065f95 | 5792 | strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}"); |
c7a4e712 | 5793 | else if (nullify && ! negated) |
e4065f95 | 5794 | strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}"); |
c7a4e712 | 5795 | else if (! nullify && negated) |
e4065f95 | 5796 | strcat (buf, "{%0,%3|%0,%%sar,%3}"); |
c7a4e712 | 5797 | else if (! nullify && ! negated) |
e4065f95 | 5798 | strcat (buf, "{ %0,%2| %0,%%sar,%2}"); |
c7a4e712 | 5799 | break; |
5800 | ||
87fcb603 | 5801 | /* All long conditionals. Note a short backward branch with an |
c7a4e712 | 5802 | unfilled delay slot is treated just like a long backward branch |
5803 | with an unfilled delay slot. */ | |
5804 | case 8: | |
5805 | /* Handle weird backwards branch with a filled delay slot | |
5806 | with is nullified. */ | |
5807 | if (dbr_sequence_length () != 0 | |
5808 | && ! forward_branch_p (insn) | |
5809 | && nullify) | |
5810 | { | |
e4065f95 | 5811 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 5812 | if (GET_MODE (operands[0]) == DImode) |
5813 | strcat (buf, "*"); | |
c7a4e712 | 5814 | if ((which == 0 && negated) |
5815 | || (which == 1 && ! negated)) | |
5816 | strcat (buf, "<"); | |
5817 | else | |
5818 | strcat (buf, ">="); | |
5819 | if (negated) | |
e4065f95 | 5820 | strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}"); |
c7a4e712 | 5821 | else |
e4065f95 | 5822 | strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}"); |
c7a4e712 | 5823 | } |
5824 | /* Handle short backwards branch with an unfilled delay slot. | |
5825 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
5826 | taken and untaken branches. */ | |
5827 | else if (dbr_sequence_length () == 0 | |
5828 | && ! forward_branch_p (insn) | |
47fc0706 | 5829 | && INSN_ADDRESSES_SET_P () |
5830 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
5831 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
c7a4e712 | 5832 | { |
e4065f95 | 5833 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 5834 | if (GET_MODE (operands[0]) == DImode) |
5835 | strcat (buf, "*"); | |
c7a4e712 | 5836 | if ((which == 0 && negated) |
5837 | || (which == 1 && ! negated)) | |
5838 | strcat (buf, ">="); | |
5839 | else | |
5840 | strcat (buf, "<"); | |
5841 | if (negated) | |
e4065f95 | 5842 | strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}"); |
c7a4e712 | 5843 | else |
e4065f95 | 5844 | strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}"); |
c7a4e712 | 5845 | } |
5846 | else | |
5847 | { | |
e4065f95 | 5848 | strcpy (buf, "{vextrs,|extrw,s,}"); |
5e3c5739 | 5849 | if (GET_MODE (operands[0]) == DImode) |
5850 | strcpy (buf, "extrd,s,*"); | |
c7a4e712 | 5851 | if ((which == 0 && negated) |
5852 | || (which == 1 && ! negated)) | |
5853 | strcat (buf, "<"); | |
5854 | else | |
5855 | strcat (buf, ">="); | |
5856 | if (nullify && negated) | |
e4065f95 | 5857 | strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}"); |
c7a4e712 | 5858 | else if (nullify && ! negated) |
e4065f95 | 5859 | strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}"); |
c7a4e712 | 5860 | else if (negated) |
e4065f95 | 5861 | strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}"); |
c7a4e712 | 5862 | else |
e4065f95 | 5863 | strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}"); |
c7a4e712 | 5864 | } |
5865 | break; | |
5866 | ||
5867 | default: | |
ea52c577 | 5868 | abort (); |
c7a4e712 | 5869 | } |
5870 | return buf; | |
5871 | } | |
5872 | ||
29a4502c | 5873 | /* Return the output template for emitting a dbra type insn. |
5874 | ||
5875 | Note it may perform some output operations on its own before | |
5876 | returning the final output string. */ | |
611a88e1 | 5877 | const char * |
29a4502c | 5878 | output_dbra (operands, insn, which_alternative) |
5879 | rtx *operands; | |
5880 | rtx insn; | |
5881 | int which_alternative; | |
5882 | { | |
5883 | ||
5884 | /* A conditional branch to the following instruction (eg the delay slot) is | |
5885 | asking for a disaster. Be prepared! */ | |
5886 | ||
db3da815 | 5887 | if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn)) |
29a4502c | 5888 | { |
5889 | if (which_alternative == 0) | |
5890 | return "ldo %1(%0),%0"; | |
5891 | else if (which_alternative == 1) | |
5892 | { | |
ea52c577 | 5893 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands); |
5894 | output_asm_insn ("ldw -16(%%r30),%4", operands); | |
34940871 | 5895 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
e4065f95 | 5896 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 5897 | } |
5898 | else | |
5899 | { | |
5900 | output_asm_insn ("ldw %0,%4", operands); | |
5901 | return "ldo %1(%4),%4\n\tstw %4,%0"; | |
5902 | } | |
5903 | } | |
5904 | ||
5905 | if (which_alternative == 0) | |
5906 | { | |
5907 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
5908 | int length = get_attr_length (insn); | |
5909 | ||
5910 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
5911 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 5912 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 5913 | nullify = 1; |
5914 | ||
5915 | /* If this is a short forward conditional branch which did not get | |
5916 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 5917 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 5918 | nullify = forward_branch_p (insn); |
5919 | ||
5920 | /* Handle short versions first. */ | |
5a1231ef | 5921 | if (length == 4 && nullify) |
29a4502c | 5922 | return "addib,%C2,n %1,%0,%3"; |
5a1231ef | 5923 | else if (length == 4 && ! nullify) |
29a4502c | 5924 | return "addib,%C2 %1,%0,%3"; |
5a1231ef | 5925 | else if (length == 8) |
29a4502c | 5926 | { |
6d36483b | 5927 | /* Handle weird backwards branch with a fulled delay slot |
29a4502c | 5928 | which is nullified. */ |
5929 | if (dbr_sequence_length () != 0 | |
5930 | && ! forward_branch_p (insn) | |
5931 | && nullify) | |
5a811d43 | 5932 | return "addib,%N2,n %1,%0,.+12\n\tb %3"; |
43f0c1f2 | 5933 | /* Handle short backwards branch with an unfilled delay slot. |
5934 | Using a addb;nop rather than addi;bl saves 1 cycle for both | |
5935 | taken and untaken branches. */ | |
5936 | else if (dbr_sequence_length () == 0 | |
5937 | && ! forward_branch_p (insn) | |
47fc0706 | 5938 | && INSN_ADDRESSES_SET_P () |
5939 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
5940 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 5941 | return "addib,%C2 %1,%0,%3%#"; |
6d36483b | 5942 | |
5943 | /* Handle normal cases. */ | |
29a4502c | 5944 | if (nullify) |
5a811d43 | 5945 | return "addi,%N2 %1,%0,%0\n\tb,n %3"; |
29a4502c | 5946 | else |
5a811d43 | 5947 | return "addi,%N2 %1,%0,%0\n\tb %3"; |
29a4502c | 5948 | } |
5949 | else | |
ea52c577 | 5950 | abort (); |
29a4502c | 5951 | } |
5952 | /* Deal with gross reload from FP register case. */ | |
5953 | else if (which_alternative == 1) | |
5954 | { | |
5955 | /* Move loop counter from FP register to MEM then into a GR, | |
5956 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 5957 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 5958 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4", |
5959 | operands); | |
34940871 | 5960 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
5a1231ef | 5961 | if (get_attr_length (insn) == 24) |
e4065f95 | 5962 | return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 5963 | else |
e4065f95 | 5964 | return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 5965 | } |
5966 | /* Deal with gross reload from memory case. */ | |
5967 | else | |
5968 | { | |
5969 | /* Reload loop counter from memory, the store back to memory | |
5970 | happens in the branch's delay slot. */ | |
5971 | output_asm_insn ("ldw %0,%4", operands); | |
5a1231ef | 5972 | if (get_attr_length (insn) == 12) |
29a4502c | 5973 | return "addib,%C2 %1,%4,%3\n\tstw %4,%0"; |
5974 | else | |
5a811d43 | 5975 | return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0"; |
29a4502c | 5976 | } |
5977 | } | |
5978 | ||
5979 | /* Return the output template for emitting a dbra type insn. | |
5980 | ||
5981 | Note it may perform some output operations on its own before | |
5982 | returning the final output string. */ | |
611a88e1 | 5983 | const char * |
29a4502c | 5984 | output_movb (operands, insn, which_alternative, reverse_comparison) |
5985 | rtx *operands; | |
5986 | rtx insn; | |
5987 | int which_alternative; | |
5988 | int reverse_comparison; | |
5989 | { | |
5990 | ||
5991 | /* A conditional branch to the following instruction (eg the delay slot) is | |
5992 | asking for a disaster. Be prepared! */ | |
5993 | ||
db3da815 | 5994 | if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn)) |
29a4502c | 5995 | { |
5996 | if (which_alternative == 0) | |
5997 | return "copy %1,%0"; | |
5998 | else if (which_alternative == 1) | |
5999 | { | |
ea52c577 | 6000 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
e4065f95 | 6001 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6002 | } |
546a40bd | 6003 | else if (which_alternative == 2) |
29a4502c | 6004 | return "stw %1,%0"; |
546a40bd | 6005 | else |
6006 | return "mtsar %r1"; | |
29a4502c | 6007 | } |
6008 | ||
6009 | /* Support the second variant. */ | |
6010 | if (reverse_comparison) | |
6011 | PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2]))); | |
6012 | ||
6013 | if (which_alternative == 0) | |
6014 | { | |
6015 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
6016 | int length = get_attr_length (insn); | |
6017 | ||
6018 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6019 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6020 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 6021 | nullify = 1; |
6022 | ||
6023 | /* If this is a short forward conditional branch which did not get | |
6024 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6025 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 6026 | nullify = forward_branch_p (insn); |
6027 | ||
6028 | /* Handle short versions first. */ | |
5a1231ef | 6029 | if (length == 4 && nullify) |
29a4502c | 6030 | return "movb,%C2,n %1,%0,%3"; |
5a1231ef | 6031 | else if (length == 4 && ! nullify) |
29a4502c | 6032 | return "movb,%C2 %1,%0,%3"; |
5a1231ef | 6033 | else if (length == 8) |
29a4502c | 6034 | { |
6d36483b | 6035 | /* Handle weird backwards branch with a filled delay slot |
29a4502c | 6036 | which is nullified. */ |
6037 | if (dbr_sequence_length () != 0 | |
6038 | && ! forward_branch_p (insn) | |
6039 | && nullify) | |
5a811d43 | 6040 | return "movb,%N2,n %1,%0,.+12\n\tb %3"; |
6d36483b | 6041 | |
43f0c1f2 | 6042 | /* Handle short backwards branch with an unfilled delay slot. |
6043 | Using a movb;nop rather than or;bl saves 1 cycle for both | |
6044 | taken and untaken branches. */ | |
6045 | else if (dbr_sequence_length () == 0 | |
6046 | && ! forward_branch_p (insn) | |
47fc0706 | 6047 | && INSN_ADDRESSES_SET_P () |
6048 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6049 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6050 | return "movb,%C2 %1,%0,%3%#"; |
6d36483b | 6051 | /* Handle normal cases. */ |
29a4502c | 6052 | if (nullify) |
5a811d43 | 6053 | return "or,%N2 %1,%%r0,%0\n\tb,n %3"; |
29a4502c | 6054 | else |
5a811d43 | 6055 | return "or,%N2 %1,%%r0,%0\n\tb %3"; |
29a4502c | 6056 | } |
6057 | else | |
ea52c577 | 6058 | abort (); |
29a4502c | 6059 | } |
6060 | /* Deal with gross reload from FP register case. */ | |
6061 | else if (which_alternative == 1) | |
6062 | { | |
6063 | /* Move loop counter from FP register to MEM then into a GR, | |
6064 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 6065 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 6066 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
5a1231ef | 6067 | if (get_attr_length (insn) == 12) |
e4065f95 | 6068 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6069 | else |
e4065f95 | 6070 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6071 | } |
6072 | /* Deal with gross reload from memory case. */ | |
546a40bd | 6073 | else if (which_alternative == 2) |
29a4502c | 6074 | { |
6075 | /* Reload loop counter from memory, the store back to memory | |
6076 | happens in the branch's delay slot. */ | |
5a1231ef | 6077 | if (get_attr_length (insn) == 8) |
e4065f95 | 6078 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0"; |
29a4502c | 6079 | else |
e4065f95 | 6080 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0"; |
29a4502c | 6081 | } |
546a40bd | 6082 | /* Handle SAR as a destination. */ |
6083 | else | |
6084 | { | |
6085 | if (get_attr_length (insn) == 8) | |
e4065f95 | 6086 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1"; |
546a40bd | 6087 | else |
e4065f95 | 6088 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1"; |
546a40bd | 6089 | } |
29a4502c | 6090 | } |
6091 | ||
ece88821 | 6092 | /* Copy any FP arguments in INSN into integer registers. */ |
6093 | static void | |
6094 | copy_fp_args (insn) | |
6095 | rtx insn; | |
6096 | { | |
6097 | rtx link; | |
6098 | rtx xoperands[2]; | |
29a4502c | 6099 | |
ece88821 | 6100 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
6101 | { | |
6102 | int arg_mode, regno; | |
6103 | rtx use = XEXP (link, 0); | |
3683f840 | 6104 | |
ece88821 | 6105 | if (! (GET_CODE (use) == USE |
6106 | && GET_CODE (XEXP (use, 0)) == REG | |
6107 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
6108 | continue; | |
d6686e21 | 6109 | |
ece88821 | 6110 | arg_mode = GET_MODE (XEXP (use, 0)); |
6111 | regno = REGNO (XEXP (use, 0)); | |
5e3c5739 | 6112 | |
ece88821 | 6113 | /* Is it a floating point register? */ |
6114 | if (regno >= 32 && regno <= 39) | |
6115 | { | |
6116 | /* Copy the FP register into an integer register via memory. */ | |
6117 | if (arg_mode == SFmode) | |
6118 | { | |
6119 | xoperands[0] = XEXP (use, 0); | |
6120 | xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2); | |
6121 | output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands); | |
6122 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
6123 | } | |
6124 | else | |
6125 | { | |
6126 | xoperands[0] = XEXP (use, 0); | |
6127 | xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2); | |
6128 | output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands); | |
6129 | output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands); | |
6130 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
6131 | } | |
6132 | } | |
06ddb6f8 | 6133 | } |
ece88821 | 6134 | } |
6135 | ||
6136 | /* Compute length of the FP argument copy sequence for INSN. */ | |
6137 | static int | |
6138 | length_fp_args (insn) | |
6139 | rtx insn; | |
6140 | { | |
6141 | int length = 0; | |
6142 | rtx link; | |
06ddb6f8 | 6143 | |
ece88821 | 6144 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
c7a4e712 | 6145 | { |
ece88821 | 6146 | int arg_mode, regno; |
6147 | rtx use = XEXP (link, 0); | |
6148 | ||
6149 | if (! (GET_CODE (use) == USE | |
6150 | && GET_CODE (XEXP (use, 0)) == REG | |
6151 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
6152 | continue; | |
c7a4e712 | 6153 | |
ece88821 | 6154 | arg_mode = GET_MODE (XEXP (use, 0)); |
6155 | regno = REGNO (XEXP (use, 0)); | |
6156 | ||
6157 | /* Is it a floating point register? */ | |
6158 | if (regno >= 32 && regno <= 39) | |
c7a4e712 | 6159 | { |
ece88821 | 6160 | if (arg_mode == SFmode) |
6161 | length += 8; | |
6162 | else | |
6163 | length += 12; | |
c7a4e712 | 6164 | } |
ece88821 | 6165 | } |
c7a4e712 | 6166 | |
ece88821 | 6167 | return length; |
6168 | } | |
b70ea764 | 6169 | |
ece88821 | 6170 | /* We include the delay slot in the returned length as it is better to |
6171 | over estimate the length than to under estimate it. */ | |
b29897dd | 6172 | |
ece88821 | 6173 | int |
6174 | attr_length_millicode_call (insn, length) | |
6175 | rtx insn; | |
6176 | int length; | |
6177 | { | |
6178 | unsigned long distance = total_code_bytes + INSN_ADDRESSES (INSN_UID (insn)); | |
6179 | ||
6180 | if (distance < total_code_bytes) | |
6181 | distance = -1; | |
6182 | ||
6183 | if (TARGET_64BIT) | |
6184 | { | |
6185 | if (!TARGET_LONG_CALLS && distance < 7600000) | |
6186 | return length + 8; | |
6187 | ||
6188 | return length + 20; | |
6189 | } | |
6190 | else if (TARGET_PORTABLE_RUNTIME) | |
6191 | return length + 24; | |
6192 | else | |
6193 | { | |
6194 | if (!TARGET_LONG_CALLS && distance < 240000) | |
6195 | return length + 8; | |
6196 | ||
6197 | if (TARGET_LONG_ABS_CALL && !flag_pic) | |
6198 | return length + 12; | |
6199 | ||
6200 | return length + 24; | |
6201 | } | |
6202 | } | |
6203 | ||
6204 | /* INSN is a function call. It may have an unconditional jump | |
6205 | in its delay slot. | |
b29897dd | 6206 | |
ece88821 | 6207 | CALL_DEST is the routine we are calling. */ |
b29897dd | 6208 | |
ece88821 | 6209 | const char * |
6210 | output_millicode_call (insn, call_dest) | |
6211 | rtx insn; | |
6212 | rtx call_dest; | |
6213 | { | |
6214 | int attr_length = get_attr_length (insn); | |
6215 | int seq_length = dbr_sequence_length (); | |
6216 | int distance; | |
6217 | rtx seq_insn; | |
6218 | rtx xoperands[3]; | |
b29897dd | 6219 | |
ece88821 | 6220 | xoperands[0] = call_dest; |
6221 | xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31); | |
6222 | ||
6223 | /* Handle the common case where we are sure that the branch will | |
6224 | reach the beginning of the $CODE$ subspace. The within reach | |
6225 | form of the $$sh_func_adrs call has a length of 28. Because | |
a8b24921 | 6226 | it has an attribute type of multi, it never has a nonzero |
ece88821 | 6227 | sequence length. The length of the $$sh_func_adrs is the same |
6228 | as certain out of reach PIC calls to other routines. */ | |
6229 | if (!TARGET_LONG_CALLS | |
6230 | && ((seq_length == 0 | |
6231 | && (attr_length == 12 | |
6232 | || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI))) | |
6233 | || (seq_length != 0 && attr_length == 8))) | |
6234 | { | |
6235 | output_asm_insn ("{bl|b,l} %0,%2", xoperands); | |
6236 | } | |
6237 | else | |
6238 | { | |
6239 | if (TARGET_64BIT) | |
6240 | { | |
6241 | /* It might seem that one insn could be saved by accessing | |
6242 | the millicode function using the linkage table. However, | |
6243 | this doesn't work in shared libraries and other dynamically | |
6244 | loaded objects. Using a pc-relative sequence also avoids | |
6245 | problems related to the implicit use of the gp register. */ | |
6246 | output_asm_insn ("b,l .+8,%%r1", xoperands); | |
9bd9af5d | 6247 | |
6248 | if (TARGET_GAS) | |
6249 | { | |
6250 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6251 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6252 | } | |
6253 | else | |
6254 | { | |
6255 | xoperands[1] = gen_label_rtx (); | |
6256 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
805e22b2 | 6257 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
9bd9af5d | 6258 | CODE_LABEL_NUMBER (xoperands[1])); |
6259 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
6260 | } | |
6261 | ||
ece88821 | 6262 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); |
c7a4e712 | 6263 | } |
c7a4e712 | 6264 | else if (TARGET_PORTABLE_RUNTIME) |
6265 | { | |
ece88821 | 6266 | /* Pure portable runtime doesn't allow be/ble; we also don't |
6267 | have PIC support in the assembler/linker, so this sequence | |
6268 | is needed. */ | |
c7a4e712 | 6269 | |
ece88821 | 6270 | /* Get the address of our target into %r1. */ |
6271 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6272 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
c7a4e712 | 6273 | |
ece88821 | 6274 | /* Get our return address into %r31. */ |
6275 | output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands); | |
6276 | output_asm_insn ("addi 8,%%r31,%%r31", xoperands); | |
c7a4e712 | 6277 | |
ece88821 | 6278 | /* Jump to our target address in %r1. */ |
6279 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 6280 | } |
ece88821 | 6281 | else if (!flag_pic) |
c7a4e712 | 6282 | { |
ece88821 | 6283 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
356267e0 | 6284 | if (TARGET_PA_20) |
ece88821 | 6285 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands); |
356267e0 | 6286 | else |
ece88821 | 6287 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); |
c7a4e712 | 6288 | } |
ece88821 | 6289 | else |
c7a4e712 | 6290 | { |
9bd9af5d | 6291 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
6292 | output_asm_insn ("addi 16,%%r1,%%r31", xoperands); | |
6293 | ||
ece88821 | 6294 | if (TARGET_SOM || !TARGET_GAS) |
6295 | { | |
6296 | /* The HP assembler can generate relocations for the | |
6297 | difference of two symbols. GAS can do this for a | |
6298 | millicode symbol but not an arbitrary external | |
6299 | symbol when generating SOM output. */ | |
6300 | xoperands[1] = gen_label_rtx (); | |
805e22b2 | 6301 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
ece88821 | 6302 | CODE_LABEL_NUMBER (xoperands[1])); |
6303 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
6304 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
6305 | } | |
6306 | else | |
6307 | { | |
ece88821 | 6308 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands); |
6309 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1", | |
6310 | xoperands); | |
6311 | } | |
c7a4e712 | 6312 | |
ece88821 | 6313 | /* Jump to our target address in %r1. */ |
6314 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 6315 | } |
c7a4e712 | 6316 | } |
6317 | ||
ece88821 | 6318 | if (seq_length == 0) |
6319 | output_asm_insn ("nop", xoperands); | |
c7a4e712 | 6320 | |
ece88821 | 6321 | /* We are done if there isn't a jump in the delay slot. */ |
6322 | if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
6323 | return ""; | |
c7a4e712 | 6324 | |
ece88821 | 6325 | /* This call has an unconditional jump in its delay slot. */ |
6326 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
c7a4e712 | 6327 | |
ece88821 | 6328 | /* See if the return address can be adjusted. Use the containing |
6329 | sequence insn's address. */ | |
6330 | seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); | |
6331 | distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
6332 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
c7a4e712 | 6333 | |
ece88821 | 6334 | if (VAL_14_BITS_P (distance)) |
c7a4e712 | 6335 | { |
ece88821 | 6336 | xoperands[1] = gen_label_rtx (); |
6337 | output_asm_insn ("ldo %0-%1(%2),%2", xoperands); | |
805e22b2 | 6338 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
2fc8af05 | 6339 | CODE_LABEL_NUMBER (xoperands[1])); |
c7a4e712 | 6340 | } |
ece88821 | 6341 | else |
6342 | /* ??? This branch may not reach its target. */ | |
6343 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 6344 | |
6345 | /* Delete the jump. */ | |
6346 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
6347 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
6348 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
ece88821 | 6349 | |
c7a4e712 | 6350 | return ""; |
6351 | } | |
6352 | ||
ece88821 | 6353 | /* We include the delay slot in the returned length as it is better to |
6354 | over estimate the length than to under estimate it. */ | |
6355 | ||
6356 | int | |
6357 | attr_length_call (insn, sibcall) | |
6358 | rtx insn; | |
6359 | int sibcall; | |
6360 | { | |
6361 | unsigned long distance = total_code_bytes + INSN_ADDRESSES (INSN_UID (insn)); | |
6362 | ||
6363 | if (distance < total_code_bytes) | |
6364 | distance = -1; | |
6365 | ||
6366 | if (TARGET_64BIT) | |
6367 | { | |
6368 | if (!TARGET_LONG_CALLS | |
6369 | && ((!sibcall && distance < 7600000) || distance < 240000)) | |
6370 | return 8; | |
6371 | ||
6372 | return (sibcall ? 28 : 24); | |
6373 | } | |
6374 | else | |
6375 | { | |
6376 | if (!TARGET_LONG_CALLS | |
6377 | && ((TARGET_PA_20 && !sibcall && distance < 7600000) | |
6378 | || distance < 240000)) | |
6379 | return 8; | |
6380 | ||
6381 | if (TARGET_LONG_ABS_CALL && !flag_pic) | |
6382 | return 12; | |
6383 | ||
6384 | if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) | |
6385 | || (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL)) | |
6386 | { | |
6387 | if (TARGET_PA_20) | |
6388 | return 20; | |
6389 | ||
6390 | return 28; | |
6391 | } | |
6392 | else | |
6393 | { | |
6394 | int length = 0; | |
6395 | ||
6396 | if (TARGET_SOM) | |
6397 | length += length_fp_args (insn); | |
6398 | ||
6399 | if (flag_pic) | |
6400 | length += 4; | |
6401 | ||
6402 | if (TARGET_PA_20) | |
6403 | return (length + 32); | |
6404 | ||
6405 | if (!sibcall) | |
6406 | length += 8; | |
6407 | ||
6408 | return (length + 40); | |
6409 | } | |
6410 | } | |
6411 | } | |
6412 | ||
6413 | /* INSN is a function call. It may have an unconditional jump | |
c7a4e712 | 6414 | in its delay slot. |
6415 | ||
6416 | CALL_DEST is the routine we are calling. */ | |
6417 | ||
611a88e1 | 6418 | const char * |
5e3c5739 | 6419 | output_call (insn, call_dest, sibcall) |
ece88821 | 6420 | rtx insn; |
6421 | rtx call_dest; | |
6422 | int sibcall; | |
c7a4e712 | 6423 | { |
ece88821 | 6424 | int delay_insn_deleted = 0; |
6425 | int delay_slot_filled = 0; | |
b70ea764 | 6426 | int attr_length = get_attr_length (insn); |
6427 | int seq_length = dbr_sequence_length (); | |
ece88821 | 6428 | rtx xoperands[2]; |
6429 | ||
6430 | xoperands[0] = call_dest; | |
c7a4e712 | 6431 | |
ece88821 | 6432 | /* Handle the common case where we're sure that the branch will reach |
6433 | the beginning of the $CODE$ subspace. */ | |
6434 | if (!TARGET_LONG_CALLS | |
6435 | && ((seq_length == 0 && attr_length == 12) | |
6436 | || (seq_length != 0 && attr_length == 8))) | |
d6686e21 | 6437 | { |
5e3c5739 | 6438 | xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2); |
ece88821 | 6439 | output_asm_insn ("{bl|b,l} %0,%1", xoperands); |
06ddb6f8 | 6440 | } |
ece88821 | 6441 | else |
06ddb6f8 | 6442 | { |
ece88821 | 6443 | if (TARGET_64BIT) |
3683f840 | 6444 | { |
ece88821 | 6445 | /* ??? As far as I can tell, the HP linker doesn't support the |
6446 | long pc-relative sequence described in the 64-bit runtime | |
6447 | architecture. So, we use a slightly longer indirect call. */ | |
6448 | struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0)); | |
6449 | ||
6450 | xoperands[0] = p->internal_label; | |
6451 | xoperands[1] = gen_label_rtx (); | |
6452 | ||
6453 | /* If this isn't a sibcall, we put the load of %r27 into the | |
6454 | delay slot. We can't do this in a sibcall as we don't | |
6455 | have a second call-clobbered scratch register available. */ | |
6456 | if (seq_length != 0 | |
6457 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
6458 | && !sibcall) | |
6459 | { | |
6460 | final_scan_insn (NEXT_INSN (insn), asm_out_file, | |
6461 | optimize, 0, 0); | |
6462 | ||
6463 | /* Now delete the delay insn. */ | |
6464 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
6465 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
6466 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
6467 | delay_insn_deleted = 1; | |
6468 | } | |
06ddb6f8 | 6469 | |
ece88821 | 6470 | output_asm_insn ("addil LT'%0,%%r27", xoperands); |
6471 | output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands); | |
6472 | output_asm_insn ("ldd 0(%%r1),%%r1", xoperands); | |
06ddb6f8 | 6473 | |
ece88821 | 6474 | if (sibcall) |
06ddb6f8 | 6475 | { |
ece88821 | 6476 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); |
6477 | output_asm_insn ("ldd 16(%%r1),%%r1", xoperands); | |
6478 | output_asm_insn ("bve (%%r1)", xoperands); | |
6479 | } | |
6480 | else | |
6481 | { | |
6482 | output_asm_insn ("ldd 16(%%r1),%%r2", xoperands); | |
6483 | output_asm_insn ("bve,l (%%r2),%%r2", xoperands); | |
6484 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); | |
6485 | delay_slot_filled = 1; | |
06ddb6f8 | 6486 | } |
6487 | } | |
ece88821 | 6488 | else |
e3f53689 | 6489 | { |
ece88821 | 6490 | int indirect_call = 0; |
6491 | ||
6492 | /* Emit a long call. There are several different sequences | |
6493 | of increasing length and complexity. In most cases, | |
6494 | they don't allow an instruction in the delay slot. */ | |
6495 | if (!(TARGET_LONG_ABS_CALL && !flag_pic) | |
6496 | && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) | |
6497 | && !(TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL)) | |
6498 | indirect_call = 1; | |
6499 | ||
6500 | if (seq_length != 0 | |
6501 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
6502 | && !sibcall | |
6503 | && (!TARGET_PA_20 || indirect_call)) | |
5cc6b2bc | 6504 | { |
ece88821 | 6505 | /* A non-jump insn in the delay slot. By definition we can |
6506 | emit this insn before the call (and in fact before argument | |
6507 | relocating. */ | |
6508 | final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0); | |
6509 | ||
6510 | /* Now delete the delay insn. */ | |
6511 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
6512 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
6513 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
6514 | delay_insn_deleted = 1; | |
5cc6b2bc | 6515 | } |
e3f53689 | 6516 | |
ece88821 | 6517 | if (TARGET_LONG_ABS_CALL && !flag_pic) |
5cc6b2bc | 6518 | { |
ece88821 | 6519 | /* This is the best sequence for making long calls in |
6520 | non-pic code. Unfortunately, GNU ld doesn't provide | |
6521 | the stub needed for external calls, and GAS's support | |
6522 | for this with the SOM linker is buggy. */ | |
6523 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6524 | if (sibcall) | |
6525 | output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands); | |
6526 | else | |
6527 | { | |
6528 | if (TARGET_PA_20) | |
6529 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", | |
6530 | xoperands); | |
6531 | else | |
6532 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); | |
c7a4e712 | 6533 | |
ece88821 | 6534 | output_asm_insn ("copy %%r31,%%r2", xoperands); |
6535 | delay_slot_filled = 1; | |
6536 | } | |
6537 | } | |
6538 | else | |
6539 | { | |
6540 | if (TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) | |
b70ea764 | 6541 | { |
ece88821 | 6542 | /* The HP assembler and linker can handle relocations |
6543 | for the difference of two symbols. GAS and the HP | |
6544 | linker can't do this when one of the symbols is | |
6545 | external. */ | |
6546 | xoperands[1] = gen_label_rtx (); | |
6547 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
6548 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
805e22b2 | 6549 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
b70ea764 | 6550 | CODE_LABEL_NUMBER (xoperands[1])); |
ece88821 | 6551 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); |
6552 | } | |
6553 | else if (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL) | |
b70ea764 | 6554 | { |
ece88821 | 6555 | /* GAS currently can't generate the relocations that |
6556 | are needed for the SOM linker under HP-UX using this | |
6557 | sequence. The GNU linker doesn't generate the stubs | |
6558 | that are needed for external calls on TARGET_ELF32 | |
6559 | with this sequence. For now, we have to use a | |
6560 | longer plabel sequence when using GAS. */ | |
6561 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
6562 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", | |
b70ea764 | 6563 | xoperands); |
ece88821 | 6564 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", |
b70ea764 | 6565 | xoperands); |
6566 | } | |
5e3c5739 | 6567 | else |
6568 | { | |
ece88821 | 6569 | /* Emit a long plabel-based call sequence. This is |
6570 | essentially an inline implementation of $$dyncall. | |
6571 | We don't actually try to call $$dyncall as this is | |
6572 | as difficult as calling the function itself. */ | |
6573 | struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0)); | |
6574 | ||
6575 | xoperands[0] = p->internal_label; | |
6576 | xoperands[1] = gen_label_rtx (); | |
6577 | ||
6578 | /* Since the call is indirect, FP arguments in registers | |
6579 | need to be copied to the general registers. Then, the | |
6580 | argument relocation stub will copy them back. */ | |
6581 | if (TARGET_SOM) | |
6582 | copy_fp_args (insn); | |
6583 | ||
6584 | if (flag_pic) | |
6585 | { | |
6586 | output_asm_insn ("addil LT'%0,%%r19", xoperands); | |
6587 | output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands); | |
6588 | output_asm_insn ("ldw 0(%%r1),%%r1", xoperands); | |
6589 | } | |
6590 | else | |
6591 | { | |
6592 | output_asm_insn ("addil LR'%0-$global$,%%r27", | |
6593 | xoperands); | |
6594 | output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1", | |
6595 | xoperands); | |
6596 | } | |
06ddb6f8 | 6597 | |
ece88821 | 6598 | output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands); |
6599 | output_asm_insn ("depi 0,31,2,%%r1", xoperands); | |
6600 | output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands); | |
6601 | output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands); | |
c7a4e712 | 6602 | |
ece88821 | 6603 | if (!sibcall && !TARGET_PA_20) |
6604 | { | |
6605 | output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands); | |
6606 | output_asm_insn ("addi 16,%%r2,%%r2", xoperands); | |
6607 | } | |
6608 | } | |
c7a4e712 | 6609 | |
ece88821 | 6610 | if (TARGET_PA_20) |
5e3c5739 | 6611 | { |
ece88821 | 6612 | if (sibcall) |
6613 | output_asm_insn ("bve (%%r1)", xoperands); | |
6614 | else | |
6615 | { | |
6616 | if (indirect_call) | |
6617 | { | |
6618 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
6619 | output_asm_insn ("stw %%r2,-24(%%sp)", xoperands); | |
6620 | delay_slot_filled = 1; | |
6621 | } | |
6622 | else | |
6623 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
6624 | } | |
5e3c5739 | 6625 | } |
6626 | else | |
6627 | { | |
ece88821 | 6628 | output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0", |
6629 | xoperands); | |
06ddb6f8 | 6630 | |
ece88821 | 6631 | if (sibcall) |
6632 | output_asm_insn ("be 0(%%sr0,%%r1)", xoperands); | |
6633 | else | |
6634 | { | |
6635 | output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands); | |
06ddb6f8 | 6636 | |
ece88821 | 6637 | if (indirect_call) |
6638 | output_asm_insn ("stw %%r31,-24(%%sp)", xoperands); | |
6639 | else | |
6640 | output_asm_insn ("copy %%r31,%%r2", xoperands); | |
6641 | delay_slot_filled = 1; | |
6642 | } | |
6643 | } | |
6644 | } | |
06ddb6f8 | 6645 | } |
d6686e21 | 6646 | } |
6d36483b | 6647 | |
ece88821 | 6648 | if (seq_length == 0 || (delay_insn_deleted && !delay_slot_filled)) |
6649 | output_asm_insn ("nop", xoperands); | |
d6686e21 | 6650 | |
ece88821 | 6651 | /* We are done if there isn't a jump in the delay slot. */ |
6652 | if (seq_length == 0 | |
6653 | || delay_insn_deleted | |
6654 | || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
6655 | return ""; | |
d6686e21 | 6656 | |
ece88821 | 6657 | /* A sibcall should never have a branch in the delay slot. */ |
6658 | if (sibcall) | |
6659 | abort (); | |
d6686e21 | 6660 | |
ece88821 | 6661 | /* This call has an unconditional jump in its delay slot. */ |
6662 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
d6686e21 | 6663 | |
ece88821 | 6664 | if (!delay_slot_filled) |
d6686e21 | 6665 | { |
ece88821 | 6666 | /* See if the return address can be adjusted. Use the containing |
6667 | sequence insn's address. */ | |
6668 | rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); | |
6669 | int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
6670 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
6671 | ||
6672 | if (VAL_14_BITS_P (distance)) | |
6673 | { | |
6674 | xoperands[1] = gen_label_rtx (); | |
6675 | output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands); | |
805e22b2 | 6676 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
6677 | CODE_LABEL_NUMBER (xoperands[1])); | |
ece88821 | 6678 | } |
6679 | else | |
6680 | /* ??? This branch may not reach its target. */ | |
6681 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
d6686e21 | 6682 | } |
ece88821 | 6683 | else |
6684 | /* ??? This branch may not reach its target. */ | |
6685 | output_asm_insn ("b,n %0", xoperands); | |
d6686e21 | 6686 | |
6687 | /* Delete the jump. */ | |
6688 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
6689 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
6690 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
ece88821 | 6691 | |
d6686e21 | 6692 | return ""; |
6693 | } | |
6694 | ||
d6f01525 | 6695 | /* In HPUX 8.0's shared library scheme, special relocations are needed |
6d36483b | 6696 | for function labels if they might be passed to a function |
d6f01525 | 6697 | in a shared library (because shared libraries don't live in code |
44acf429 | 6698 | space), and special magic is needed to construct their address. */ |
d6f01525 | 6699 | |
6700 | void | |
44acf429 | 6701 | hppa_encode_label (sym) |
d6f01525 | 6702 | rtx sym; |
6703 | { | |
611a88e1 | 6704 | const char *str = XSTR (sym, 0); |
cccfb31e | 6705 | int len = strlen (str) + 1; |
6706 | char *newstr, *p; | |
d6f01525 | 6707 | |
cccfb31e | 6708 | p = newstr = alloca (len + 1); |
cccfb31e | 6709 | *p++ = '@'; |
6710 | strcpy (p, str); | |
74d80a9a | 6711 | |
ea52c577 | 6712 | XSTR (sym, 0) = ggc_alloc_string (newstr, len); |
d6f01525 | 6713 | } |
6d36483b | 6714 | |
7811991d | 6715 | static void |
6716 | pa_encode_section_info (decl, first) | |
6717 | tree decl; | |
6718 | int first; | |
6719 | { | |
6720 | if (first && TEXT_SPACE_P (decl)) | |
6721 | { | |
6722 | rtx rtl; | |
6723 | if (TREE_CODE (decl) == FUNCTION_DECL | |
6724 | || TREE_CODE (decl) == VAR_DECL) | |
6725 | rtl = DECL_RTL (decl); | |
6726 | else | |
6727 | rtl = TREE_CST_RTL (decl); | |
6728 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; | |
6729 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
6730 | hppa_encode_label (XEXP (DECL_RTL (decl), 0)); | |
6731 | } | |
6732 | } | |
6733 | ||
7b4a38a6 | 6734 | /* This is sort of inverse to pa_encode_section_info. */ |
6735 | ||
6736 | static const char * | |
6737 | pa_strip_name_encoding (str) | |
6738 | const char *str; | |
6739 | { | |
c0264367 | 6740 | str += (*str == '@'); |
6741 | str += (*str == '*'); | |
6742 | return str; | |
7b4a38a6 | 6743 | } |
6744 | ||
d6f01525 | 6745 | int |
166bf021 | 6746 | function_label_operand (op, mode) |
d6f01525 | 6747 | rtx op; |
b1ca791d | 6748 | enum machine_mode mode ATTRIBUTE_UNUSED; |
d6f01525 | 6749 | { |
c1b3411e | 6750 | return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0)); |
d6f01525 | 6751 | } |
f33e3942 | 6752 | |
166bf021 | 6753 | /* Returns 1 if OP is a function label involved in a simple addition |
6754 | with a constant. Used to keep certain patterns from matching | |
6755 | during instruction combination. */ | |
6756 | int | |
6757 | is_function_label_plus_const (op) | |
6758 | rtx op; | |
6759 | { | |
6760 | /* Strip off any CONST. */ | |
6761 | if (GET_CODE (op) == CONST) | |
6762 | op = XEXP (op, 0); | |
6763 | ||
6764 | return (GET_CODE (op) == PLUS | |
6765 | && function_label_operand (XEXP (op, 0), Pmode) | |
6766 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
6767 | } | |
6768 | ||
f1752b7e | 6769 | /* Output assembly code for a thunk to FUNCTION. */ |
6770 | ||
6988553d | 6771 | static void |
eb344f43 | 6772 | pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) |
f1752b7e | 6773 | FILE *file; |
6774 | tree thunk_fndecl; | |
e11bd7e5 | 6775 | HOST_WIDE_INT delta; |
eb344f43 | 6776 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED; |
f1752b7e | 6777 | tree function; |
6778 | { | |
6779 | const char *target_name = XSTR (XEXP (DECL_RTL (function), 0), 0); | |
6780 | static unsigned int current_thunk_number; | |
6781 | char label[16]; | |
9d2d8bd6 | 6782 | const char *lab; |
f1752b7e | 6783 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number); |
6784 | lab = (*targetm.strip_name_encoding) (label); | |
6785 | target_name = (*targetm.strip_name_encoding) (target_name); | |
6786 | /* FIXME: total_code_bytes is not handled correctly in files with | |
6787 | mi thunks. */ | |
6788 | pa_output_function_prologue (file, 0); | |
6789 | if (VAL_14_BITS_P (delta)) | |
6790 | { | |
6791 | if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic) | |
6792 | { | |
ece88821 | 6793 | fprintf (file, "\taddil LT'%s,%%r19\n", lab); |
6794 | fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab); | |
f1752b7e | 6795 | fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n"); |
6796 | fprintf (file, "\tbb,>=,n %%r22,30,.+16\n"); | |
6797 | fprintf (file, "\tdepi 0,31,2,%%r22\n"); | |
6798 | fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n"); | |
6799 | fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n"); | |
6800 | fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n"); | |
6801 | fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo "); | |
6802 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta); | |
6803 | fprintf (file, "(%%r26),%%r26\n"); | |
6804 | } | |
6805 | else | |
6806 | { | |
6807 | fprintf (file, "\tb %s\n\tldo ", target_name); | |
6808 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta); | |
6809 | fprintf (file, "(%%r26),%%r26\n"); | |
6810 | } | |
6811 | } | |
6812 | else | |
6813 | { | |
6814 | if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic) | |
6815 | { | |
ece88821 | 6816 | fprintf (file, "\taddil L'"); |
f1752b7e | 6817 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta); |
ece88821 | 6818 | fprintf (file, ",%%r26\n\tldo R'"); |
f1752b7e | 6819 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta); |
6820 | fprintf (file, "(%%r1),%%r26\n"); | |
ece88821 | 6821 | fprintf (file, "\taddil LT'%s,%%r19\n", lab); |
6822 | fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab); | |
f1752b7e | 6823 | fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n"); |
6824 | fprintf (file, "\tbb,>=,n %%r22,30,.+16\n"); | |
6825 | fprintf (file, "\tdepi 0,31,2,%%r22\n"); | |
6826 | fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n"); | |
6827 | fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n"); | |
6828 | fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n"); | |
6829 | fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n"); | |
6830 | } | |
6831 | else | |
6832 | { | |
ece88821 | 6833 | fprintf (file, "\taddil L'"); |
f1752b7e | 6834 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta); |
ece88821 | 6835 | fprintf (file, ",%%r26\n\tb %s\n\tldo R'", target_name); |
f1752b7e | 6836 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta); |
6837 | fprintf (file, "(%%r1),%%r26\n"); | |
6838 | } | |
6839 | } | |
6840 | ||
6841 | fprintf (file, "\t.EXIT\n\t.PROCEND\n"); | |
6842 | if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic) | |
6843 | { | |
6844 | data_section (); | |
6845 | fprintf (file, "\t.align 4\n"); | |
805e22b2 | 6846 | (*targetm.asm_out.internal_label) (file, "LTHN", current_thunk_number); |
ece88821 | 6847 | fprintf (file, "\t.word P'%s\n", target_name); |
f1752b7e | 6848 | function_section (thunk_fndecl); |
6849 | } | |
6850 | current_thunk_number++; | |
6851 | } | |
6852 | ||
805e22b2 | 6853 | /* Only direct calls to static functions are allowed to be sibling (tail) |
6854 | call optimized. | |
6855 | ||
6856 | This restriction is necessary because some linker generated stubs will | |
6857 | store return pointers into rp' in some cases which might clobber a | |
6858 | live value already in rp'. | |
6859 | ||
6860 | In a sibcall the current function and the target function share stack | |
6861 | space. Thus if the path to the current function and the path to the | |
6862 | target function save a value in rp', they save the value into the | |
6863 | same stack slot, which has undesirable consequences. | |
6864 | ||
6865 | Because of the deferred binding nature of shared libraries any function | |
6866 | with external scope could be in a different load module and thus require | |
6867 | rp' to be saved when calling that function. So sibcall optimizations | |
6868 | can only be safe for static function. | |
6869 | ||
6870 | Note that GCC never needs return value relocations, so we don't have to | |
6871 | worry about static calls with return value relocations (which require | |
6872 | saving rp'). | |
6873 | ||
6874 | It is safe to perform a sibcall optimization when the target function | |
6875 | will never return. */ | |
6876 | static bool | |
6877 | pa_function_ok_for_sibcall (decl, exp) | |
6878 | tree decl; | |
6879 | tree exp ATTRIBUTE_UNUSED; | |
6880 | { | |
6881 | #ifdef TARGET_HAS_STUBS_AND_ELF_SECTIONS | |
6882 | /* Sibcalls, stubs, and elf sections don't play well. */ | |
6883 | return false; | |
6884 | #endif | |
6885 | return (decl | |
6886 | && ! TARGET_PORTABLE_RUNTIME | |
6887 | && ! TARGET_64BIT | |
6888 | && ! TREE_PUBLIC (decl)); | |
6889 | } | |
6890 | ||
37580c80 | 6891 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
6892 | use in fmpyadd instructions. */ | |
4ed6ee50 | 6893 | int |
df0651dc | 6894 | fmpyaddoperands (operands) |
4ed6ee50 | 6895 | rtx *operands; |
6896 | { | |
201f01e9 | 6897 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 6898 | |
ab449421 | 6899 | /* Must be a floating point mode. */ |
6900 | if (mode != SFmode && mode != DFmode) | |
6901 | return 0; | |
6902 | ||
4ed6ee50 | 6903 | /* All modes must be the same. */ |
201f01e9 | 6904 | if (! (mode == GET_MODE (operands[1]) |
6905 | && mode == GET_MODE (operands[2]) | |
6906 | && mode == GET_MODE (operands[3]) | |
6907 | && mode == GET_MODE (operands[4]) | |
6908 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 6909 | return 0; |
6910 | ||
ab449421 | 6911 | /* All operands must be registers. */ |
6912 | if (! (GET_CODE (operands[1]) == REG | |
6913 | && GET_CODE (operands[2]) == REG | |
6914 | && GET_CODE (operands[3]) == REG | |
6915 | && GET_CODE (operands[4]) == REG | |
6916 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 6917 | return 0; |
6918 | ||
37580c80 | 6919 | /* Only 2 real operands to the addition. One of the input operands must |
6920 | be the same as the output operand. */ | |
4ed6ee50 | 6921 | if (! rtx_equal_p (operands[3], operands[4]) |
6922 | && ! rtx_equal_p (operands[3], operands[5])) | |
6923 | return 0; | |
6924 | ||
6925 | /* Inout operand of add can not conflict with any operands from multiply. */ | |
6926 | if (rtx_equal_p (operands[3], operands[0]) | |
6927 | || rtx_equal_p (operands[3], operands[1]) | |
6928 | || rtx_equal_p (operands[3], operands[2])) | |
6929 | return 0; | |
6930 | ||
6931 | /* multiply can not feed into addition operands. */ | |
6932 | if (rtx_equal_p (operands[4], operands[0]) | |
6933 | || rtx_equal_p (operands[5], operands[0])) | |
6934 | return 0; | |
6935 | ||
ab449421 | 6936 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
6937 | if (mode == SFmode | |
bac38c40 | 6938 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
6939 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
6940 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
6941 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
6942 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
6943 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 6944 | return 0; |
6945 | ||
4ed6ee50 | 6946 | /* Passed. Operands are suitable for fmpyadd. */ |
6947 | return 1; | |
6948 | } | |
6949 | ||
37580c80 | 6950 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
6951 | use in fmpysub instructions. */ | |
4ed6ee50 | 6952 | int |
df0651dc | 6953 | fmpysuboperands (operands) |
4ed6ee50 | 6954 | rtx *operands; |
6955 | { | |
201f01e9 | 6956 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 6957 | |
ab449421 | 6958 | /* Must be a floating point mode. */ |
6959 | if (mode != SFmode && mode != DFmode) | |
6960 | return 0; | |
6961 | ||
4ed6ee50 | 6962 | /* All modes must be the same. */ |
201f01e9 | 6963 | if (! (mode == GET_MODE (operands[1]) |
6964 | && mode == GET_MODE (operands[2]) | |
6965 | && mode == GET_MODE (operands[3]) | |
6966 | && mode == GET_MODE (operands[4]) | |
6967 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 6968 | return 0; |
6969 | ||
ab449421 | 6970 | /* All operands must be registers. */ |
6971 | if (! (GET_CODE (operands[1]) == REG | |
6972 | && GET_CODE (operands[2]) == REG | |
6973 | && GET_CODE (operands[3]) == REG | |
6974 | && GET_CODE (operands[4]) == REG | |
6975 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 6976 | return 0; |
6977 | ||
37580c80 | 6978 | /* Only 2 real operands to the subtraction. Subtraction is not a commutative |
6979 | operation, so operands[4] must be the same as operand[3]. */ | |
4ed6ee50 | 6980 | if (! rtx_equal_p (operands[3], operands[4])) |
6981 | return 0; | |
6982 | ||
6983 | /* multiply can not feed into subtraction. */ | |
37580c80 | 6984 | if (rtx_equal_p (operands[5], operands[0])) |
4ed6ee50 | 6985 | return 0; |
6986 | ||
37580c80 | 6987 | /* Inout operand of sub can not conflict with any operands from multiply. */ |
4ed6ee50 | 6988 | if (rtx_equal_p (operands[3], operands[0]) |
6989 | || rtx_equal_p (operands[3], operands[1]) | |
6990 | || rtx_equal_p (operands[3], operands[2])) | |
6991 | return 0; | |
6992 | ||
ab449421 | 6993 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
6994 | if (mode == SFmode | |
bac38c40 | 6995 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
6996 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
6997 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
6998 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
6999 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
7000 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 7001 | return 0; |
7002 | ||
4ed6ee50 | 7003 | /* Passed. Operands are suitable for fmpysub. */ |
7004 | return 1; | |
7005 | } | |
7006 | ||
89f29d73 | 7007 | int |
7008 | plus_xor_ior_operator (op, mode) | |
7009 | rtx op; | |
b1ca791d | 7010 | enum machine_mode mode ATTRIBUTE_UNUSED; |
89f29d73 | 7011 | { |
7012 | return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR | |
7013 | || GET_CODE (op) == IOR); | |
7014 | } | |
6720f95e | 7015 | |
7016 | /* Return 1 if the given constant is 2, 4, or 8. These are the valid | |
7017 | constants for shadd instructions. */ | |
7d27e4c9 | 7018 | static int |
6720f95e | 7019 | shadd_constant_p (val) |
7020 | int val; | |
7021 | { | |
7022 | if (val == 2 || val == 4 || val == 8) | |
7023 | return 1; | |
7024 | else | |
7025 | return 0; | |
7026 | } | |
3a16146d | 7027 | |
7028 | /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are | |
7029 | the valid constant for shadd instructions. */ | |
7030 | int | |
7031 | shadd_operand (op, mode) | |
7032 | rtx op; | |
b1ca791d | 7033 | enum machine_mode mode ATTRIBUTE_UNUSED; |
3a16146d | 7034 | { |
7035 | return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op))); | |
7036 | } | |
5fbd5940 | 7037 | |
42819d4e | 7038 | /* Return 1 if OP is valid as a base register in a reg + reg address. */ |
7039 | ||
7040 | int | |
7041 | basereg_operand (op, mode) | |
7042 | rtx op; | |
7043 | enum machine_mode mode; | |
7044 | { | |
21f3ee9c | 7045 | /* cse will create some unscaled indexed addresses, however; it |
7046 | generally isn't a win on the PA, so avoid creating unscaled | |
7047 | indexed addresses until after cse is finished. */ | |
7048 | if (!cse_not_expected) | |
7049 | return 0; | |
7050 | ||
e61a0a7f | 7051 | /* Allow any register when TARGET_NO_SPACE_REGS is in effect since |
7052 | we don't have to worry about the braindamaged implicit space | |
7053 | register selection from the basereg. */ | |
7054 | if (TARGET_NO_SPACE_REGS) | |
23a667d0 | 7055 | return (GET_CODE (op) == REG); |
42819d4e | 7056 | |
21f3ee9c | 7057 | /* While it's always safe to index off the frame pointer, it's not |
7058 | always profitable, particularly when the frame pointer is being | |
7059 | eliminated. */ | |
7060 | if (! flag_omit_frame_pointer && op == frame_pointer_rtx) | |
42819d4e | 7061 | return 1; |
7062 | ||
e61a0a7f | 7063 | return (GET_CODE (op) == REG |
90ae5d76 | 7064 | && REG_POINTER (op) |
7065 | && register_operand (op, mode)); | |
42819d4e | 7066 | } |
7067 | ||
51987f90 | 7068 | /* Return 1 if this operand is anything other than a hard register. */ |
7069 | ||
7070 | int | |
7071 | non_hard_reg_operand (op, mode) | |
7072 | rtx op; | |
b1ca791d | 7073 | enum machine_mode mode ATTRIBUTE_UNUSED; |
51987f90 | 7074 | { |
7075 | return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER); | |
7076 | } | |
7077 | ||
5fbd5940 | 7078 | /* Return 1 if INSN branches forward. Should be using insn_addresses |
6dc3b0d9 | 7079 | to avoid walking through all the insns... */ |
7d27e4c9 | 7080 | static int |
5fbd5940 | 7081 | forward_branch_p (insn) |
7082 | rtx insn; | |
7083 | { | |
7084 | rtx label = JUMP_LABEL (insn); | |
7085 | ||
7086 | while (insn) | |
7087 | { | |
7088 | if (insn == label) | |
7089 | break; | |
7090 | else | |
7091 | insn = NEXT_INSN (insn); | |
7092 | } | |
7093 | ||
7094 | return (insn == label); | |
7095 | } | |
7096 | ||
29a4502c | 7097 | /* Return 1 if OP is an equality comparison, else return 0. */ |
7098 | int | |
7099 | eq_neq_comparison_operator (op, mode) | |
7100 | rtx op; | |
b1ca791d | 7101 | enum machine_mode mode ATTRIBUTE_UNUSED; |
29a4502c | 7102 | { |
7103 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
7104 | } | |
7105 | ||
7106 | /* Return 1 if OP is an operator suitable for use in a movb instruction. */ | |
7107 | int | |
7108 | movb_comparison_operator (op, mode) | |
7109 | rtx op; | |
b1ca791d | 7110 | enum machine_mode mode ATTRIBUTE_UNUSED; |
29a4502c | 7111 | { |
7112 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE | |
7113 | || GET_CODE (op) == LT || GET_CODE (op) == GE); | |
7114 | } | |
7115 | ||
d6686e21 | 7116 | /* Return 1 if INSN is in the delay slot of a call instruction. */ |
7117 | int | |
7118 | jump_in_call_delay (insn) | |
7119 | rtx insn; | |
7120 | { | |
7121 | ||
7122 | if (GET_CODE (insn) != JUMP_INSN) | |
7123 | return 0; | |
7124 | ||
7125 | if (PREV_INSN (insn) | |
7126 | && PREV_INSN (PREV_INSN (insn)) | |
7127 | && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN) | |
7128 | { | |
7129 | rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn))); | |
7130 | ||
7131 | return (GET_CODE (PATTERN (test_insn)) == SEQUENCE | |
7132 | && XVECEXP (PATTERN (test_insn), 0, 1) == insn); | |
7133 | ||
7134 | } | |
7135 | else | |
7136 | return 0; | |
7137 | } | |
3b1e673e | 7138 | |
546a40bd | 7139 | /* Output an unconditional move and branch insn. */ |
7140 | ||
611a88e1 | 7141 | const char * |
546a40bd | 7142 | output_parallel_movb (operands, length) |
7143 | rtx *operands; | |
7144 | int length; | |
7145 | { | |
7146 | /* These are the cases in which we win. */ | |
7147 | if (length == 4) | |
7148 | return "mov%I1b,tr %1,%0,%2"; | |
7149 | ||
7150 | /* None of these cases wins, but they don't lose either. */ | |
7151 | if (dbr_sequence_length () == 0) | |
7152 | { | |
7153 | /* Nothing in the delay slot, fake it by putting the combined | |
7154 | insn (the copy or add) in the delay slot of a bl. */ | |
7155 | if (GET_CODE (operands[1]) == CONST_INT) | |
5a811d43 | 7156 | return "b %2\n\tldi %1,%0"; |
546a40bd | 7157 | else |
5a811d43 | 7158 | return "b %2\n\tcopy %1,%0"; |
546a40bd | 7159 | } |
7160 | else | |
7161 | { | |
7162 | /* Something in the delay slot, but we've got a long branch. */ | |
7163 | if (GET_CODE (operands[1]) == CONST_INT) | |
5a811d43 | 7164 | return "ldi %1,%0\n\tb %2"; |
546a40bd | 7165 | else |
5a811d43 | 7166 | return "copy %1,%0\n\tb %2"; |
546a40bd | 7167 | } |
7168 | } | |
7169 | ||
7170 | /* Output an unconditional add and branch insn. */ | |
7171 | ||
611a88e1 | 7172 | const char * |
546a40bd | 7173 | output_parallel_addb (operands, length) |
7174 | rtx *operands; | |
7175 | int length; | |
7176 | { | |
7177 | /* To make life easy we want operand0 to be the shared input/output | |
7178 | operand and operand1 to be the readonly operand. */ | |
7179 | if (operands[0] == operands[1]) | |
7180 | operands[1] = operands[2]; | |
7181 | ||
7182 | /* These are the cases in which we win. */ | |
7183 | if (length == 4) | |
7184 | return "add%I1b,tr %1,%0,%3"; | |
7185 | ||
7186 | /* None of these cases win, but they don't lose either. */ | |
7187 | if (dbr_sequence_length () == 0) | |
7188 | { | |
7189 | /* Nothing in the delay slot, fake it by putting the combined | |
7190 | insn (the copy or add) in the delay slot of a bl. */ | |
5a811d43 | 7191 | return "b %3\n\tadd%I1 %1,%0,%0"; |
546a40bd | 7192 | } |
7193 | else | |
7194 | { | |
7195 | /* Something in the delay slot, but we've got a long branch. */ | |
5a811d43 | 7196 | return "add%I1 %1,%0,%0\n\tb %3"; |
546a40bd | 7197 | } |
7198 | } | |
7199 | ||
7c5101fc | 7200 | /* Return nonzero if INSN (a jump insn) immediately follows a call |
7201 | to a named function. This is used to avoid filling the delay slot | |
7202 | of the jump since it can usually be eliminated by modifying RP in | |
7203 | the delay slot of the call. */ | |
9840d99d | 7204 | |
7d27e4c9 | 7205 | int |
546a40bd | 7206 | following_call (insn) |
7207 | rtx insn; | |
7208 | { | |
ed1b0769 | 7209 | if (! TARGET_JUMP_IN_DELAY) |
1b6f11e2 | 7210 | return 0; |
7211 | ||
546a40bd | 7212 | /* Find the previous real insn, skipping NOTEs. */ |
7213 | insn = PREV_INSN (insn); | |
7214 | while (insn && GET_CODE (insn) == NOTE) | |
7215 | insn = PREV_INSN (insn); | |
7216 | ||
7217 | /* Check for CALL_INSNs and millicode calls. */ | |
7218 | if (insn | |
1d2e016c | 7219 | && ((GET_CODE (insn) == CALL_INSN |
7220 | && get_attr_type (insn) != TYPE_DYNCALL) | |
546a40bd | 7221 | || (GET_CODE (insn) == INSN |
7222 | && GET_CODE (PATTERN (insn)) != SEQUENCE | |
7223 | && GET_CODE (PATTERN (insn)) != USE | |
7224 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
7225 | && get_attr_type (insn) == TYPE_MILLI))) | |
7226 | return 1; | |
7227 | ||
7228 | return 0; | |
7229 | } | |
7230 | ||
3b1e673e | 7231 | /* We use this hook to perform a PA specific optimization which is difficult |
7232 | to do in earlier passes. | |
7233 | ||
7234 | We want the delay slots of branches within jump tables to be filled. | |
7235 | None of the compiler passes at the moment even has the notion that a | |
7236 | PA jump table doesn't contain addresses, but instead contains actual | |
7237 | instructions! | |
7238 | ||
7239 | Because we actually jump into the table, the addresses of each entry | |
01cc3b75 | 7240 | must stay constant in relation to the beginning of the table (which |
3b1e673e | 7241 | itself must stay constant relative to the instruction to jump into |
7242 | it). I don't believe we can guarantee earlier passes of the compiler | |
7243 | will adhere to those rules. | |
7244 | ||
7245 | So, late in the compilation process we find all the jump tables, and | |
7246 | expand them into real code -- eg each entry in the jump table vector | |
7247 | will get an appropriate label followed by a jump to the final target. | |
7248 | ||
7249 | Reorg and the final jump pass can then optimize these branches and | |
7250 | fill their delay slots. We end up with smaller, more efficient code. | |
7251 | ||
9840d99d | 7252 | The jump instructions within the table are special; we must be able |
3b1e673e | 7253 | to identify them during assembly output (if the jumps don't get filled |
7254 | we need to emit a nop rather than nullifying the delay slot)). We | |
9840d99d | 7255 | identify jumps in switch tables by marking the SET with DImode. |
9239127b | 7256 | |
7257 | We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB | |
7258 | insns. This serves two purposes, first it prevents jump.c from | |
7259 | noticing that the last N entries in the table jump to the instruction | |
7260 | immediately after the table and deleting the jumps. Second, those | |
7261 | insns mark where we should emit .begin_brtab and .end_brtab directives | |
7262 | when using GAS (allows for better link time optimizations). */ | |
3b1e673e | 7263 | |
7d27e4c9 | 7264 | void |
3b1e673e | 7265 | pa_reorg (insns) |
7266 | rtx insns; | |
7267 | { | |
7268 | rtx insn; | |
7269 | ||
c533da59 | 7270 | remove_useless_addtr_insns (insns, 1); |
3d457930 | 7271 | |
342aabd9 | 7272 | if (pa_cpu < PROCESSOR_8000) |
7273 | pa_combine_instructions (get_insns ()); | |
7274 | ||
bd49d362 | 7275 | |
3d457930 | 7276 | /* This is fairly cheap, so always run it if optimizing. */ |
a66555b2 | 7277 | if (optimize > 0 && !TARGET_BIG_SWITCH) |
3b1e673e | 7278 | { |
b41266d4 | 7279 | /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */ |
3b1e673e | 7280 | insns = get_insns (); |
7281 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
7282 | { | |
7283 | rtx pattern, tmp, location; | |
7284 | unsigned int length, i; | |
7285 | ||
b41266d4 | 7286 | /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */ |
3b1e673e | 7287 | if (GET_CODE (insn) != JUMP_INSN |
b41266d4 | 7288 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
7289 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
3b1e673e | 7290 | continue; |
7291 | ||
9239127b | 7292 | /* Emit marker for the beginning of the branch table. */ |
7293 | emit_insn_before (gen_begin_brtab (), insn); | |
f9333726 | 7294 | |
3b1e673e | 7295 | pattern = PATTERN (insn); |
7296 | location = PREV_INSN (insn); | |
b41266d4 | 7297 | length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC); |
f9333726 | 7298 | |
3b1e673e | 7299 | for (i = 0; i < length; i++) |
7300 | { | |
a66555b2 | 7301 | /* Emit a label before each jump to keep jump.c from |
7302 | removing this code. */ | |
7303 | tmp = gen_label_rtx (); | |
7304 | LABEL_NUSES (tmp) = 1; | |
7305 | emit_label_after (tmp, location); | |
7306 | location = NEXT_INSN (location); | |
7307 | ||
b41266d4 | 7308 | if (GET_CODE (pattern) == ADDR_VEC) |
7309 | { | |
7310 | /* Emit the jump itself. */ | |
0708e381 | 7311 | tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0)); |
b41266d4 | 7312 | tmp = emit_jump_insn_after (tmp, location); |
7313 | JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0); | |
0708e381 | 7314 | /* It is easy to rely on the branch table markers |
7315 | during assembly output to trigger the correct code | |
7316 | for a switch table jump with an unfilled delay slot, | |
7317 | ||
7318 | However, that requires state and assumes that we look | |
7319 | at insns in order. | |
7320 | ||
7321 | We can't make such assumptions when computing the length | |
7322 | of instructions. Ugh. We could walk the insn chain to | |
7323 | determine if this instruction is in a branch table, but | |
7324 | that can get rather expensive, particularly during the | |
7325 | branch shortening phase of the compiler. | |
7326 | ||
7327 | So instead we mark this jump as being special. This is | |
7328 | far from ideal and knows that no code after this will | |
7329 | muck around with the mode of the JUMP_INSN itself. */ | |
7330 | PUT_MODE (tmp, SImode); | |
b41266d4 | 7331 | LABEL_NUSES (JUMP_LABEL (tmp))++; |
7332 | location = NEXT_INSN (location); | |
7333 | } | |
7334 | else | |
7335 | { | |
7336 | /* Emit the jump itself. */ | |
0708e381 | 7337 | tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0)); |
b41266d4 | 7338 | tmp = emit_jump_insn_after (tmp, location); |
7339 | JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0); | |
0708e381 | 7340 | /* It is easy to rely on the branch table markers |
7341 | during assembly output to trigger the correct code | |
7342 | for a switch table jump with an unfilled delay slot, | |
7343 | ||
7344 | However, that requires state and assumes that we look | |
7345 | at insns in order. | |
7346 | ||
7347 | We can't make such assumptions when computing the length | |
7348 | of instructions. Ugh. We could walk the insn chain to | |
7349 | determine if this instruction is in a branch table, but | |
7350 | that can get rather expensive, particularly during the | |
7351 | branch shortening phase of the compiler. | |
7352 | ||
7353 | So instead we mark this jump as being special. This is | |
7354 | far from ideal and knows that no code after this will | |
7355 | muck around with the mode of the JUMP_INSN itself. */ | |
7356 | PUT_MODE (tmp, SImode); | |
b41266d4 | 7357 | LABEL_NUSES (JUMP_LABEL (tmp))++; |
7358 | location = NEXT_INSN (location); | |
7359 | } | |
3b1e673e | 7360 | |
7361 | /* Emit a BARRIER after the jump. */ | |
3b1e673e | 7362 | emit_barrier_after (location); |
3b1e673e | 7363 | location = NEXT_INSN (location); |
7364 | } | |
f9333726 | 7365 | |
9239127b | 7366 | /* Emit marker for the end of the branch table. */ |
7367 | emit_insn_before (gen_end_brtab (), location); | |
7368 | location = NEXT_INSN (location); | |
7369 | emit_barrier_after (location); | |
a66555b2 | 7370 | |
b41266d4 | 7371 | /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */ |
3b1e673e | 7372 | delete_insn (insn); |
7373 | } | |
7374 | } | |
9239127b | 7375 | else |
f9333726 | 7376 | { |
7377 | /* Sill need an end_brtab insn. */ | |
7378 | insns = get_insns (); | |
7379 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
7380 | { | |
7381 | /* Find an ADDR_VEC insn. */ | |
7382 | if (GET_CODE (insn) != JUMP_INSN | |
b41266d4 | 7383 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
7384 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
f9333726 | 7385 | continue; |
7386 | ||
7387 | /* Now generate markers for the beginning and end of the | |
ad87de1e | 7388 | branch table. */ |
f9333726 | 7389 | emit_insn_before (gen_begin_brtab (), insn); |
7390 | emit_insn_after (gen_end_brtab (), insn); | |
7391 | } | |
7392 | } | |
d3287673 | 7393 | } |
bd49d362 | 7394 | |
7395 | /* The PA has a number of odd instructions which can perform multiple | |
7396 | tasks at once. On first generation PA machines (PA1.0 and PA1.1) | |
7397 | it may be profitable to combine two instructions into one instruction | |
7398 | with two outputs. It's not profitable PA2.0 machines because the | |
7399 | two outputs would take two slots in the reorder buffers. | |
7400 | ||
7401 | This routine finds instructions which can be combined and combines | |
7402 | them. We only support some of the potential combinations, and we | |
7403 | only try common ways to find suitable instructions. | |
7404 | ||
7405 | * addb can add two registers or a register and a small integer | |
7406 | and jump to a nearby (+-8k) location. Normally the jump to the | |
7407 | nearby location is conditional on the result of the add, but by | |
7408 | using the "true" condition we can make the jump unconditional. | |
7409 | Thus addb can perform two independent operations in one insn. | |
7410 | ||
7411 | * movb is similar to addb in that it can perform a reg->reg | |
7412 | or small immediate->reg copy and jump to a nearby (+-8k location). | |
7413 | ||
7414 | * fmpyadd and fmpysub can perform a FP multiply and either an | |
7415 | FP add or FP sub if the operands of the multiply and add/sub are | |
7416 | independent (there are other minor restrictions). Note both | |
7417 | the fmpy and fadd/fsub can in theory move to better spots according | |
7418 | to data dependencies, but for now we require the fmpy stay at a | |
7419 | fixed location. | |
7420 | ||
7421 | * Many of the memory operations can perform pre & post updates | |
7422 | of index registers. GCC's pre/post increment/decrement addressing | |
7423 | is far too simple to take advantage of all the possibilities. This | |
7424 | pass may not be suitable since those insns may not be independent. | |
7425 | ||
7426 | * comclr can compare two ints or an int and a register, nullify | |
7427 | the following instruction and zero some other register. This | |
7428 | is more difficult to use as it's harder to find an insn which | |
7429 | will generate a comclr than finding something like an unconditional | |
7430 | branch. (conditional moves & long branches create comclr insns). | |
7431 | ||
7432 | * Most arithmetic operations can conditionally skip the next | |
7433 | instruction. They can be viewed as "perform this operation | |
7434 | and conditionally jump to this nearby location" (where nearby | |
7435 | is an insns away). These are difficult to use due to the | |
7436 | branch length restrictions. */ | |
7437 | ||
7d27e4c9 | 7438 | static void |
bd49d362 | 7439 | pa_combine_instructions (insns) |
b1ca791d | 7440 | rtx insns ATTRIBUTE_UNUSED; |
bd49d362 | 7441 | { |
7442 | rtx anchor, new; | |
7443 | ||
7444 | /* This can get expensive since the basic algorithm is on the | |
7445 | order of O(n^2) (or worse). Only do it for -O2 or higher | |
ad87de1e | 7446 | levels of optimization. */ |
bd49d362 | 7447 | if (optimize < 2) |
7448 | return; | |
7449 | ||
7450 | /* Walk down the list of insns looking for "anchor" insns which | |
7451 | may be combined with "floating" insns. As the name implies, | |
7452 | "anchor" instructions don't move, while "floating" insns may | |
7453 | move around. */ | |
ad851752 | 7454 | new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX)); |
bd49d362 | 7455 | new = make_insn_raw (new); |
7456 | ||
7457 | for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor)) | |
7458 | { | |
7459 | enum attr_pa_combine_type anchor_attr; | |
7460 | enum attr_pa_combine_type floater_attr; | |
7461 | ||
7462 | /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs. | |
7463 | Also ignore any special USE insns. */ | |
7d27e4c9 | 7464 | if ((GET_CODE (anchor) != INSN |
bd49d362 | 7465 | && GET_CODE (anchor) != JUMP_INSN |
7d27e4c9 | 7466 | && GET_CODE (anchor) != CALL_INSN) |
bd49d362 | 7467 | || GET_CODE (PATTERN (anchor)) == USE |
7468 | || GET_CODE (PATTERN (anchor)) == CLOBBER | |
7469 | || GET_CODE (PATTERN (anchor)) == ADDR_VEC | |
7470 | || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC) | |
7471 | continue; | |
7472 | ||
7473 | anchor_attr = get_attr_pa_combine_type (anchor); | |
7474 | /* See if anchor is an insn suitable for combination. */ | |
7475 | if (anchor_attr == PA_COMBINE_TYPE_FMPY | |
7476 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
7477 | || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
7478 | && ! forward_branch_p (anchor))) | |
7479 | { | |
7480 | rtx floater; | |
7481 | ||
7482 | for (floater = PREV_INSN (anchor); | |
7483 | floater; | |
7484 | floater = PREV_INSN (floater)) | |
7485 | { | |
7486 | if (GET_CODE (floater) == NOTE | |
7487 | || (GET_CODE (floater) == INSN | |
7488 | && (GET_CODE (PATTERN (floater)) == USE | |
7489 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
7490 | continue; | |
7491 | ||
7492 | /* Anything except a regular INSN will stop our search. */ | |
7493 | if (GET_CODE (floater) != INSN | |
7494 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
7495 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
7496 | { | |
7497 | floater = NULL_RTX; | |
7498 | break; | |
7499 | } | |
7500 | ||
7501 | /* See if FLOATER is suitable for combination with the | |
7502 | anchor. */ | |
7503 | floater_attr = get_attr_pa_combine_type (floater); | |
7504 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
7505 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
7506 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
7507 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
7508 | { | |
7509 | /* If ANCHOR and FLOATER can be combined, then we're | |
7510 | done with this pass. */ | |
7511 | if (pa_can_combine_p (new, anchor, floater, 0, | |
7512 | SET_DEST (PATTERN (floater)), | |
7513 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
7514 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
7515 | break; | |
7516 | } | |
7517 | ||
7518 | else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
7519 | && floater_attr == PA_COMBINE_TYPE_ADDMOVE) | |
7520 | { | |
7521 | if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS) | |
7522 | { | |
7523 | if (pa_can_combine_p (new, anchor, floater, 0, | |
7524 | SET_DEST (PATTERN (floater)), | |
7525 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
7526 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
7527 | break; | |
7528 | } | |
7529 | else | |
7530 | { | |
7531 | if (pa_can_combine_p (new, anchor, floater, 0, | |
7532 | SET_DEST (PATTERN (floater)), | |
7533 | SET_SRC (PATTERN (floater)), | |
7534 | SET_SRC (PATTERN (floater)))) | |
7535 | break; | |
7536 | } | |
7537 | } | |
7538 | } | |
7539 | ||
7540 | /* If we didn't find anything on the backwards scan try forwards. */ | |
7541 | if (!floater | |
7542 | && (anchor_attr == PA_COMBINE_TYPE_FMPY | |
7543 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB)) | |
7544 | { | |
7545 | for (floater = anchor; floater; floater = NEXT_INSN (floater)) | |
7546 | { | |
7547 | if (GET_CODE (floater) == NOTE | |
7548 | || (GET_CODE (floater) == INSN | |
7549 | && (GET_CODE (PATTERN (floater)) == USE | |
7550 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
9840d99d | 7551 | |
bd49d362 | 7552 | continue; |
7553 | ||
7554 | /* Anything except a regular INSN will stop our search. */ | |
7555 | if (GET_CODE (floater) != INSN | |
7556 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
7557 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
7558 | { | |
7559 | floater = NULL_RTX; | |
7560 | break; | |
7561 | } | |
7562 | ||
7563 | /* See if FLOATER is suitable for combination with the | |
7564 | anchor. */ | |
7565 | floater_attr = get_attr_pa_combine_type (floater); | |
7566 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
7567 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
7568 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
7569 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
7570 | { | |
7571 | /* If ANCHOR and FLOATER can be combined, then we're | |
7572 | done with this pass. */ | |
7573 | if (pa_can_combine_p (new, anchor, floater, 1, | |
7574 | SET_DEST (PATTERN (floater)), | |
ea52c577 | 7575 | XEXP (SET_SRC (PATTERN (floater)), |
7576 | 0), | |
7577 | XEXP (SET_SRC (PATTERN (floater)), | |
7578 | 1))) | |
bd49d362 | 7579 | break; |
7580 | } | |
7581 | } | |
7582 | } | |
7583 | ||
7584 | /* FLOATER will be nonzero if we found a suitable floating | |
7585 | insn for combination with ANCHOR. */ | |
7586 | if (floater | |
7587 | && (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
7588 | || anchor_attr == PA_COMBINE_TYPE_FMPY)) | |
7589 | { | |
7590 | /* Emit the new instruction and delete the old anchor. */ | |
7014838c | 7591 | emit_insn_before (gen_rtx_PARALLEL |
7592 | (VOIDmode, | |
7593 | gen_rtvec (2, PATTERN (anchor), | |
7594 | PATTERN (floater))), | |
7595 | anchor); | |
7596 | ||
bd49d362 | 7597 | PUT_CODE (anchor, NOTE); |
7598 | NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED; | |
7599 | NOTE_SOURCE_FILE (anchor) = 0; | |
7600 | ||
7601 | /* Emit a special USE insn for FLOATER, then delete | |
7602 | the floating insn. */ | |
ad851752 | 7603 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 7604 | delete_insn (floater); |
7605 | ||
7606 | continue; | |
7607 | } | |
7608 | else if (floater | |
7609 | && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH) | |
7610 | { | |
7611 | rtx temp; | |
7612 | /* Emit the new_jump instruction and delete the old anchor. */ | |
7014838c | 7613 | temp |
7614 | = emit_jump_insn_before (gen_rtx_PARALLEL | |
7615 | (VOIDmode, | |
7616 | gen_rtvec (2, PATTERN (anchor), | |
7617 | PATTERN (floater))), | |
7618 | anchor); | |
7619 | ||
bd49d362 | 7620 | JUMP_LABEL (temp) = JUMP_LABEL (anchor); |
7621 | PUT_CODE (anchor, NOTE); | |
7622 | NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED; | |
7623 | NOTE_SOURCE_FILE (anchor) = 0; | |
7624 | ||
7625 | /* Emit a special USE insn for FLOATER, then delete | |
7626 | the floating insn. */ | |
ad851752 | 7627 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 7628 | delete_insn (floater); |
7629 | continue; | |
7630 | } | |
7631 | } | |
7632 | } | |
7633 | } | |
7634 | ||
9aadea62 | 7635 | static int |
bd49d362 | 7636 | pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2) |
7637 | rtx new, anchor, floater; | |
7638 | int reversed; | |
7639 | rtx dest, src1, src2; | |
7640 | { | |
7641 | int insn_code_number; | |
7642 | rtx start, end; | |
7643 | ||
7644 | /* Create a PARALLEL with the patterns of ANCHOR and | |
7645 | FLOATER, try to recognize it, then test constraints | |
7646 | for the resulting pattern. | |
7647 | ||
7648 | If the pattern doesn't match or the constraints | |
7649 | aren't met keep searching for a suitable floater | |
7650 | insn. */ | |
7651 | XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor); | |
7652 | XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater); | |
7653 | INSN_CODE (new) = -1; | |
7654 | insn_code_number = recog_memoized (new); | |
7655 | if (insn_code_number < 0 | |
bf9fd117 | 7656 | || (extract_insn (new), ! constrain_operands (1))) |
bd49d362 | 7657 | return 0; |
7658 | ||
7659 | if (reversed) | |
7660 | { | |
7661 | start = anchor; | |
7662 | end = floater; | |
7663 | } | |
7664 | else | |
7665 | { | |
7666 | start = floater; | |
7667 | end = anchor; | |
7668 | } | |
7669 | ||
7670 | /* There's up to three operands to consider. One | |
7671 | output and two inputs. | |
7672 | ||
7673 | The output must not be used between FLOATER & ANCHOR | |
7674 | exclusive. The inputs must not be set between | |
7675 | FLOATER and ANCHOR exclusive. */ | |
7676 | ||
7677 | if (reg_used_between_p (dest, start, end)) | |
7678 | return 0; | |
7679 | ||
7680 | if (reg_set_between_p (src1, start, end)) | |
7681 | return 0; | |
7682 | ||
7683 | if (reg_set_between_p (src2, start, end)) | |
7684 | return 0; | |
7685 | ||
7686 | /* If we get here, then everything is good. */ | |
7687 | return 1; | |
7688 | } | |
14d18de3 | 7689 | |
a6582a53 | 7690 | /* Return nonzero if references for INSN are delayed. |
14d18de3 | 7691 | |
7692 | Millicode insns are actually function calls with some special | |
7693 | constraints on arguments and register usage. | |
7694 | ||
7695 | Millicode calls always expect their arguments in the integer argument | |
7696 | registers, and always return their result in %r29 (ret1). They | |
2013ddf6 | 7697 | are expected to clobber their arguments, %r1, %r29, and the return |
7698 | pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else. | |
7699 | ||
7700 | This function tells reorg that the references to arguments and | |
7701 | millicode calls do not appear to happen until after the millicode call. | |
7702 | This allows reorg to put insns which set the argument registers into the | |
7703 | delay slot of the millicode call -- thus they act more like traditional | |
7704 | CALL_INSNs. | |
7705 | ||
7706 | Note we can not consider side effects of the insn to be delayed because | |
7707 | the branch and link insn will clobber the return pointer. If we happened | |
7708 | to use the return pointer in the delay slot of the call, then we lose. | |
14d18de3 | 7709 | |
7710 | get_attr_type will try to recognize the given insn, so make sure to | |
7711 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
7712 | in particular. */ | |
7713 | int | |
a6582a53 | 7714 | insn_refs_are_delayed (insn) |
14d18de3 | 7715 | rtx insn; |
7716 | { | |
9840d99d | 7717 | return ((GET_CODE (insn) == INSN |
14d18de3 | 7718 | && GET_CODE (PATTERN (insn)) != SEQUENCE |
7719 | && GET_CODE (PATTERN (insn)) != USE | |
7720 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
7721 | && get_attr_type (insn) == TYPE_MILLI)); | |
7722 | } | |
5cb4669a | 7723 | |
58a72cce | 7724 | /* On the HP-PA the value is found in register(s) 28(-29), unless |
7725 | the mode is SF or DF. Then the value is returned in fr4 (32). | |
7726 | ||
7727 | This must perform the same promotions as PROMOTE_MODE, else | |
7728 | PROMOTE_FUNCTION_RETURN will not work correctly. | |
7729 | ||
7730 | Small structures must be returned in a PARALLEL on PA64 in order | |
7731 | to match the HP Compiler ABI. */ | |
7732 | ||
7733 | rtx | |
7734 | function_value (valtype, func) | |
7735 | tree valtype; | |
7736 | tree func ATTRIBUTE_UNUSED; | |
7737 | { | |
7738 | enum machine_mode valmode; | |
7739 | ||
7740 | /* Aggregates with a size less than or equal to 128 bits are returned | |
7741 | in GR 28(-29). They are left justified. The pad bits are undefined. | |
7742 | Larger aggregates are returned in memory. */ | |
7743 | if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype)) | |
7744 | { | |
7745 | rtx loc[2]; | |
7746 | int i, offset = 0; | |
7747 | int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2; | |
7748 | ||
7749 | for (i = 0; i < ub; i++) | |
7750 | { | |
7751 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
7752 | gen_rtx_REG (DImode, 28 + i), | |
7753 | GEN_INT (offset)); | |
7754 | offset += 8; | |
7755 | } | |
7756 | ||
7757 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc)); | |
7758 | } | |
7759 | ||
7760 | if ((INTEGRAL_TYPE_P (valtype) | |
7761 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
7762 | || POINTER_TYPE_P (valtype)) | |
7763 | valmode = word_mode; | |
7764 | else | |
7765 | valmode = TYPE_MODE (valtype); | |
7766 | ||
7767 | if (TREE_CODE (valtype) == REAL_TYPE | |
7768 | && TYPE_MODE (valtype) != TFmode | |
7769 | && !TARGET_SOFT_FLOAT) | |
7770 | return gen_rtx_REG (valmode, 32); | |
7771 | ||
7772 | return gen_rtx_REG (valmode, 28); | |
7773 | } | |
7774 | ||
5e3c5739 | 7775 | /* Return the location of a parameter that is passed in a register or NULL |
7776 | if the parameter has any component that is passed in memory. | |
7777 | ||
7778 | This is new code and will be pushed to into the net sources after | |
9840d99d | 7779 | further testing. |
5e3c5739 | 7780 | |
7781 | ??? We might want to restructure this so that it looks more like other | |
7782 | ports. */ | |
7783 | rtx | |
7784 | function_arg (cum, mode, type, named, incoming) | |
7785 | CUMULATIVE_ARGS *cum; | |
7786 | enum machine_mode mode; | |
7787 | tree type; | |
9aadea62 | 7788 | int named ATTRIBUTE_UNUSED; |
5e3c5739 | 7789 | int incoming; |
7790 | { | |
7791 | int max_arg_words = (TARGET_64BIT ? 8 : 4); | |
2a075f91 | 7792 | int alignment = 0; |
ac965869 | 7793 | int arg_size; |
5e3c5739 | 7794 | int fpr_reg_base; |
7795 | int gpr_reg_base; | |
7796 | rtx retval; | |
7797 | ||
ac965869 | 7798 | if (mode == VOIDmode) |
7799 | return NULL_RTX; | |
7800 | ||
7801 | arg_size = FUNCTION_ARG_SIZE (mode, type); | |
7802 | ||
7803 | /* If this arg would be passed partially or totally on the stack, then | |
7804 | this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will | |
7805 | handle arguments which are split between regs and stack slots if | |
7806 | the ABI mandates split arguments. */ | |
5e3c5739 | 7807 | if (! TARGET_64BIT) |
7808 | { | |
ac965869 | 7809 | /* The 32-bit ABI does not split arguments. */ |
7810 | if (cum->words + arg_size > max_arg_words) | |
5e3c5739 | 7811 | return NULL_RTX; |
7812 | } | |
7813 | else | |
7814 | { | |
2a075f91 | 7815 | if (arg_size > 1) |
7816 | alignment = cum->words & 1; | |
ac965869 | 7817 | if (cum->words + alignment >= max_arg_words) |
5e3c5739 | 7818 | return NULL_RTX; |
7819 | } | |
7820 | ||
7821 | /* The 32bit ABIs and the 64bit ABIs are rather different, | |
7822 | particularly in their handling of FP registers. We might | |
7823 | be able to cleverly share code between them, but I'm not | |
9aadea62 | 7824 | going to bother in the hope that splitting them up results |
2a075f91 | 7825 | in code that is more easily understood. */ |
5e3c5739 | 7826 | |
5e3c5739 | 7827 | if (TARGET_64BIT) |
7828 | { | |
7829 | /* Advance the base registers to their current locations. | |
7830 | ||
7831 | Remember, gprs grow towards smaller register numbers while | |
2a075f91 | 7832 | fprs grow to higher register numbers. Also remember that |
7833 | although FP regs are 32-bit addressable, we pretend that | |
7834 | the registers are 64-bits wide. */ | |
5e3c5739 | 7835 | gpr_reg_base = 26 - cum->words; |
7836 | fpr_reg_base = 32 + cum->words; | |
9840d99d | 7837 | |
ac965869 | 7838 | /* Arguments wider than one word and small aggregates need special |
7839 | treatment. */ | |
7840 | if (arg_size > 1 | |
7841 | || mode == BLKmode | |
7842 | || (type && AGGREGATE_TYPE_P (type))) | |
5e3c5739 | 7843 | { |
2a075f91 | 7844 | /* Double-extended precision (80-bit), quad-precision (128-bit) |
7845 | and aggregates including complex numbers are aligned on | |
7846 | 128-bit boundaries. The first eight 64-bit argument slots | |
7847 | are associated one-to-one, with general registers r26 | |
7848 | through r19, and also with floating-point registers fr4 | |
7849 | through fr11. Arguments larger than one word are always | |
ac965869 | 7850 | passed in general registers. |
7851 | ||
7852 | Using a PARALLEL with a word mode register results in left | |
7853 | justified data on a big-endian target. */ | |
2a075f91 | 7854 | |
7855 | rtx loc[8]; | |
7856 | int i, offset = 0, ub = arg_size; | |
7857 | ||
7858 | /* Align the base register. */ | |
7859 | gpr_reg_base -= alignment; | |
7860 | ||
7861 | ub = MIN (ub, max_arg_words - cum->words - alignment); | |
7862 | for (i = 0; i < ub; i++) | |
5e3c5739 | 7863 | { |
2a075f91 | 7864 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, |
7865 | gen_rtx_REG (DImode, gpr_reg_base), | |
7866 | GEN_INT (offset)); | |
7867 | gpr_reg_base -= 1; | |
7868 | offset += 8; | |
5e3c5739 | 7869 | } |
2a075f91 | 7870 | |
7871 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc)); | |
5e3c5739 | 7872 | } |
ac965869 | 7873 | } |
5e3c5739 | 7874 | else |
7875 | { | |
7876 | /* If the argument is larger than a word, then we know precisely | |
7877 | which registers we must use. */ | |
2a075f91 | 7878 | if (arg_size > 1) |
5e3c5739 | 7879 | { |
7880 | if (cum->words) | |
7881 | { | |
7882 | gpr_reg_base = 23; | |
7883 | fpr_reg_base = 38; | |
7884 | } | |
7885 | else | |
7886 | { | |
7887 | gpr_reg_base = 25; | |
7888 | fpr_reg_base = 34; | |
7889 | } | |
ac965869 | 7890 | |
7891 | /* Structures 5 to 8 bytes in size are passed in the general | |
7892 | registers in the same manner as other non floating-point | |
7893 | objects. The data is right-justified and zero-extended | |
7894 | to 64 bits. | |
7895 | ||
7896 | This is magic. Normally, using a PARALLEL results in left | |
7897 | justified data on a big-endian target. However, using a | |
7898 | single double-word register provides the required right | |
7899 | justication for 5 to 8 byte structures. This has nothing | |
7900 | to do with the direction of padding specified for the argument. | |
7901 | It has to do with how the data is widened and shifted into | |
7902 | and from the register. | |
7903 | ||
7904 | Aside from adding load_multiple and store_multiple patterns, | |
7905 | this is the only way that I have found to obtain right | |
7906 | justification of BLKmode data when it has a size greater | |
7907 | than one word. Splitting the operation into two SImode loads | |
7908 | or returning a DImode REG results in left justified data. */ | |
7909 | if (mode == BLKmode) | |
7910 | { | |
58a72cce | 7911 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, |
7912 | gen_rtx_REG (DImode, gpr_reg_base), | |
7913 | const0_rtx); | |
7914 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc)); | |
ac965869 | 7915 | } |
5e3c5739 | 7916 | } |
7917 | else | |
7918 | { | |
7919 | /* We have a single word (32 bits). A simple computation | |
7920 | will get us the register #s we need. */ | |
7921 | gpr_reg_base = 26 - cum->words; | |
7922 | fpr_reg_base = 32 + 2 * cum->words; | |
7923 | } | |
7924 | } | |
7925 | ||
9503b0f7 | 7926 | /* Determine if the argument needs to be passed in both general and |
5e3c5739 | 7927 | floating point registers. */ |
9503b0f7 | 7928 | if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32) |
7929 | /* If we are doing soft-float with portable runtime, then there | |
7930 | is no need to worry about FP regs. */ | |
7931 | && ! TARGET_SOFT_FLOAT | |
7932 | /* The parameter must be some kind of float, else we can just | |
7933 | pass it in integer registers. */ | |
7934 | && FLOAT_MODE_P (mode) | |
7935 | /* The target function must not have a prototype. */ | |
7936 | && cum->nargs_prototype <= 0 | |
7937 | /* libcalls do not need to pass items in both FP and general | |
7938 | registers. */ | |
7939 | && type != NULL_TREE | |
7940 | /* All this hair applies to outgoing args only. */ | |
7941 | && ! incoming) | |
7942 | /* Also pass outgoing floating arguments in both registers in indirect | |
7943 | calls with the 32 bit ABI and the HP assembler since there is no | |
7944 | way to the specify argument locations in static functions. */ | |
7945 | || (! TARGET_64BIT | |
7946 | && ! TARGET_GAS | |
7947 | && ! incoming | |
7948 | && cum->indirect | |
7949 | && FLOAT_MODE_P (mode))) | |
5e3c5739 | 7950 | { |
7951 | retval | |
7952 | = gen_rtx_PARALLEL | |
7953 | (mode, | |
7954 | gen_rtvec (2, | |
7955 | gen_rtx_EXPR_LIST (VOIDmode, | |
7956 | gen_rtx_REG (mode, fpr_reg_base), | |
7957 | const0_rtx), | |
7958 | gen_rtx_EXPR_LIST (VOIDmode, | |
7959 | gen_rtx_REG (mode, gpr_reg_base), | |
7960 | const0_rtx))); | |
7961 | } | |
7962 | else | |
7963 | { | |
7964 | /* See if we should pass this parameter in a general register. */ | |
7965 | if (TARGET_SOFT_FLOAT | |
7966 | /* Indirect calls in the normal 32bit ABI require all arguments | |
7967 | to be passed in general registers. */ | |
7968 | || (!TARGET_PORTABLE_RUNTIME | |
7969 | && !TARGET_64BIT | |
a052da6f | 7970 | && !TARGET_ELF32 |
5e3c5739 | 7971 | && cum->indirect) |
7972 | /* If the parameter is not a floating point parameter, then | |
7973 | it belongs in GPRs. */ | |
7974 | || !FLOAT_MODE_P (mode)) | |
7975 | retval = gen_rtx_REG (mode, gpr_reg_base); | |
7976 | else | |
7977 | retval = gen_rtx_REG (mode, fpr_reg_base); | |
7978 | } | |
7979 | return retval; | |
7980 | } | |
7981 | ||
7982 | ||
7983 | /* If this arg would be passed totally in registers or totally on the stack, | |
7984 | then this routine should return zero. It is currently called only for | |
6dc3b0d9 | 7985 | the 64-bit target. */ |
5e3c5739 | 7986 | int |
7987 | function_arg_partial_nregs (cum, mode, type, named) | |
7988 | CUMULATIVE_ARGS *cum; | |
7989 | enum machine_mode mode; | |
7990 | tree type; | |
9aadea62 | 7991 | int named ATTRIBUTE_UNUSED; |
5e3c5739 | 7992 | { |
b7d86581 | 7993 | unsigned int max_arg_words = 8; |
7994 | unsigned int offset = 0; | |
5e3c5739 | 7995 | |
b7d86581 | 7996 | if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1)) |
5e3c5739 | 7997 | offset = 1; |
7998 | ||
b7d86581 | 7999 | if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words) |
6dc3b0d9 | 8000 | /* Arg fits fully into registers. */ |
5e3c5739 | 8001 | return 0; |
9840d99d | 8002 | else if (cum->words + offset >= max_arg_words) |
6dc3b0d9 | 8003 | /* Arg fully on the stack. */ |
5e3c5739 | 8004 | return 0; |
8005 | else | |
6dc3b0d9 | 8006 | /* Arg is split. */ |
5e3c5739 | 8007 | return max_arg_words - cum->words - offset; |
5e3c5739 | 8008 | } |
8009 | ||
8010 | ||
8011 | /* Return 1 if this is a comparison operator. This allows the use of | |
8012 | MATCH_OPERATOR to recognize all the branch insns. */ | |
8013 | ||
8014 | int | |
8015 | cmpib_comparison_operator (op, mode) | |
8016 | register rtx op; | |
8017 | enum machine_mode mode; | |
8018 | { | |
8019 | return ((mode == VOIDmode || GET_MODE (op) == mode) | |
8020 | && (GET_CODE (op) == EQ | |
8021 | || GET_CODE (op) == NE | |
8022 | || GET_CODE (op) == GT | |
5e3c5739 | 8023 | || GET_CODE (op) == GTU |
32509e56 | 8024 | || GET_CODE (op) == GE |
5e3c5739 | 8025 | || GET_CODE (op) == LT |
8026 | || GET_CODE (op) == LE | |
8027 | || GET_CODE (op) == LEU)); | |
8028 | } | |
8029 | ||
52470889 | 8030 | /* On hpux10, the linker will give an error if we have a reference |
8031 | in the read-only data section to a symbol defined in a shared | |
8032 | library. Therefore, expressions that might require a reloc can | |
8033 | not be placed in the read-only data section. */ | |
8034 | ||
8035 | static void | |
8036 | pa_select_section (exp, reloc, align) | |
8037 | tree exp; | |
8038 | int reloc; | |
8039 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED; | |
8040 | { | |
8041 | if (TREE_CODE (exp) == VAR_DECL | |
8042 | && TREE_READONLY (exp) | |
8043 | && !TREE_THIS_VOLATILE (exp) | |
8044 | && DECL_INITIAL (exp) | |
8045 | && (DECL_INITIAL (exp) == error_mark_node | |
8046 | || TREE_CONSTANT (DECL_INITIAL (exp))) | |
8047 | && !reloc) | |
8048 | readonly_data_section (); | |
8049 | else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c' | |
8050 | && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings) | |
8051 | && !reloc) | |
8052 | readonly_data_section (); | |
8053 | else | |
8054 | data_section (); | |
8055 | } | |
1f3233d1 | 8056 | |
67c1e638 | 8057 | static void |
8058 | pa_globalize_label (stream, name) | |
8059 | FILE *stream; | |
8060 | const char *name; | |
8061 | { | |
8062 | /* We only handle DATA objects here, functions are globalized in | |
8063 | ASM_DECLARE_FUNCTION_NAME. */ | |
8064 | if (! FUNCTION_NAME_P (name)) | |
8065 | { | |
8066 | fputs ("\t.EXPORT ", stream); | |
8067 | assemble_name (stream, name); | |
8068 | fputs (",DATA\n", stream); | |
8069 | } | |
8070 | } | |
1f3233d1 | 8071 | #include "gt-pa.h" |