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87ad11b0 | 1 | /* Subroutines for insn-output.c for HPPA. |
a9ac13e4 | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
ace694ca | 3 | 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
87ad11b0 | 4 | Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c |
5 | ||
5c1d8983 | 6 | This file is part of GCC. |
87ad11b0 | 7 | |
5c1d8983 | 8 | GCC is free software; you can redistribute it and/or modify |
87ad11b0 | 9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
5c1d8983 | 13 | GCC is distributed in the hope that it will be useful, |
87ad11b0 | 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
5c1d8983 | 19 | along with GCC; see the file COPYING. If not, write to |
dbddc6c4 | 20 | the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
87ad11b0 | 22 | |
87ad11b0 | 23 | #include "config.h" |
b1ca791d | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
87ad11b0 | 27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
87ad11b0 | 33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "tree.h" | |
9d2d8bd6 | 36 | #include "output.h" |
a584fe8a | 37 | #include "except.h" |
32509e56 | 38 | #include "expr.h" |
d8fc4d0b | 39 | #include "optabs.h" |
d8fc4d0b | 40 | #include "reload.h" |
d7e2f694 | 41 | #include "integrate.h" |
0a893c29 | 42 | #include "function.h" |
b1ca791d | 43 | #include "toplev.h" |
5cb4669a | 44 | #include "ggc.h" |
611a88e1 | 45 | #include "recog.h" |
a584fe8a | 46 | #include "predict.h" |
611a88e1 | 47 | #include "tm_p.h" |
a767736d | 48 | #include "target.h" |
49 | #include "target-def.h" | |
87ad11b0 | 50 | |
cde3e16c | 51 | /* Return nonzero if there is a bypass for the output of |
52 | OUT_INSN and the fp store IN_INSN. */ | |
53 | int | |
5c1d8983 | 54 | hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn) |
cde3e16c | 55 | { |
56 | enum machine_mode store_mode; | |
57 | enum machine_mode other_mode; | |
58 | rtx set; | |
59 | ||
60 | if (recog_memoized (in_insn) < 0 | |
61 | || get_attr_type (in_insn) != TYPE_FPSTORE | |
62 | || recog_memoized (out_insn) < 0) | |
63 | return 0; | |
64 | ||
65 | store_mode = GET_MODE (SET_SRC (PATTERN (in_insn))); | |
66 | ||
67 | set = single_set (out_insn); | |
68 | if (!set) | |
69 | return 0; | |
70 | ||
71 | other_mode = GET_MODE (SET_SRC (set)); | |
72 | ||
73 | return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode)); | |
74 | } | |
75 | ||
76 | ||
cc858176 | 77 | #ifndef DO_FRAME_NOTES |
78 | #ifdef INCOMING_RETURN_ADDR_RTX | |
79 | #define DO_FRAME_NOTES 1 | |
80 | #else | |
81 | #define DO_FRAME_NOTES 0 | |
82 | #endif | |
83 | #endif | |
84 | ||
dbd3d89d | 85 | static void copy_reg_pointer (rtx, rtx); |
320e1276 | 86 | static void fix_range (const char *); |
bd57250e | 87 | static bool pa_handle_option (size_t, const char *, int); |
5c1d8983 | 88 | static int hppa_address_cost (rtx); |
89 | static bool hppa_rtx_costs (rtx, int, int, int *); | |
90 | static inline rtx force_mode (enum machine_mode, rtx); | |
91 | static void pa_reorg (void); | |
92 | static void pa_combine_instructions (void); | |
93 | static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx); | |
94 | static int forward_branch_p (rtx); | |
5c1d8983 | 95 | static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *); |
008c057d | 96 | static int compute_movmem_length (rtx); |
97 | static int compute_clrmem_length (rtx); | |
5c1d8983 | 98 | static bool pa_assemble_integer (rtx, unsigned int, int); |
99 | static void remove_useless_addtr_insns (int); | |
6bcdc1fb | 100 | static void store_reg (int, HOST_WIDE_INT, int); |
101 | static void store_reg_modify (int, int, HOST_WIDE_INT); | |
102 | static void load_reg (int, HOST_WIDE_INT, int); | |
103 | static void set_reg_plus_d (int, int, HOST_WIDE_INT, int); | |
5c1d8983 | 104 | static void pa_output_function_prologue (FILE *, HOST_WIDE_INT); |
105 | static void update_total_code_bytes (int); | |
106 | static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
107 | static int pa_adjust_cost (rtx, rtx, rtx, int); | |
108 | static int pa_adjust_priority (rtx, int); | |
109 | static int pa_issue_rate (void); | |
110 | static void pa_select_section (tree, int, unsigned HOST_WIDE_INT) | |
52470889 | 111 | ATTRIBUTE_UNUSED; |
5c1d8983 | 112 | static void pa_encode_section_info (tree, rtx, int); |
113 | static const char *pa_strip_name_encoding (const char *); | |
114 | static bool pa_function_ok_for_sibcall (tree, tree); | |
115 | static void pa_globalize_label (FILE *, const char *) | |
63b8cd48 | 116 | ATTRIBUTE_UNUSED; |
5c1d8983 | 117 | static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
118 | HOST_WIDE_INT, tree); | |
de419443 | 119 | #if !defined(USE_COLLECT2) |
5c1d8983 | 120 | static void pa_asm_out_constructor (rtx, int); |
121 | static void pa_asm_out_destructor (rtx, int); | |
de419443 | 122 | #endif |
5c1d8983 | 123 | static void pa_init_builtins (void); |
b8debbe8 | 124 | static rtx hppa_builtin_saveregs (void); |
4c33eb68 | 125 | static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *); |
2b1e7cc3 | 126 | static bool pa_scalar_mode_supported_p (enum machine_mode); |
280566a7 | 127 | static bool pa_commutative_p (rtx x, int outer_code); |
5c1d8983 | 128 | static void copy_fp_args (rtx) ATTRIBUTE_UNUSED; |
129 | static int length_fp_args (rtx) ATTRIBUTE_UNUSED; | |
5f43b4f6 | 130 | static struct deferred_plabel *get_plabel (rtx) ATTRIBUTE_UNUSED; |
5c1d8983 | 131 | static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED; |
132 | static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED; | |
133 | static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED; | |
134 | static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED; | |
135 | static void pa_elf_file_start (void) ATTRIBUTE_UNUSED; | |
136 | static void pa_som_file_start (void) ATTRIBUTE_UNUSED; | |
137 | static void pa_linux_file_start (void) ATTRIBUTE_UNUSED; | |
138 | static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED; | |
139 | static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED; | |
140 | static void output_deferred_plabels (void); | |
5f43b4f6 | 141 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
142 | static void pa_hpux_file_end (void); | |
143 | #endif | |
f2f543a3 | 144 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
145 | static void pa_hpux_init_libfuncs (void); | |
146 | #endif | |
b8debbe8 | 147 | static rtx pa_struct_value_rtx (tree, int); |
f054eb3c | 148 | static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
b981d932 | 149 | tree, bool); |
f054eb3c | 150 | static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
151 | tree, bool); | |
916c9cef | 152 | static struct machine_function * pa_init_machine_status (void); |
b981d932 | 153 | |
9d3ddb8f | 154 | |
87ad11b0 | 155 | /* Save the operands last given to a compare for use when we |
156 | generate a scc or bcc insn. */ | |
87ad11b0 | 157 | rtx hppa_compare_op0, hppa_compare_op1; |
158 | enum cmp_type hppa_branch_type; | |
159 | ||
320e1276 | 160 | /* Which cpu we are scheduling for. */ |
bd57250e | 161 | enum processor_type pa_cpu = TARGET_SCHED_DEFAULT; |
8ab32933 | 162 | |
163 | /* The UNIX standard to use for predefines and linking. */ | |
bd57250e | 164 | int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993; |
8ab32933 | 165 | |
a9960cdc | 166 | /* Counts for the number of callee-saved general and floating point |
167 | registers which were saved by the current function's prologue. */ | |
168 | static int gr_saved, fr_saved; | |
169 | ||
5c1d8983 | 170 | static rtx find_addr_reg (rtx); |
87ad11b0 | 171 | |
2247cc5f | 172 | /* Keep track of the number of bytes we have output in the CODE subspace |
06ddb6f8 | 173 | during this compilation so we'll know when to emit inline long-calls. */ |
ece88821 | 174 | unsigned long total_code_bytes; |
06ddb6f8 | 175 | |
2247cc5f | 176 | /* The last address of the previous function plus the number of bytes in |
177 | associated thunks that have been output. This is used to determine if | |
178 | a thunk can use an IA-relative branch to reach its target function. */ | |
179 | static int last_address; | |
180 | ||
e3f53689 | 181 | /* Variables to handle plabels that we discover are necessary at assembly |
01cc3b75 | 182 | output time. They are output after the current function. */ |
1f3233d1 | 183 | struct deferred_plabel GTY(()) |
e3f53689 | 184 | { |
185 | rtx internal_label; | |
5f43b4f6 | 186 | rtx symbol; |
1f3233d1 | 187 | }; |
188 | static GTY((length ("n_deferred_plabels"))) struct deferred_plabel * | |
189 | deferred_plabels; | |
e11bd7e5 | 190 | static size_t n_deferred_plabels = 0; |
f6940372 | 191 | |
a767736d | 192 | \f |
193 | /* Initialize the GCC target structure. */ | |
58356836 | 194 | |
195 | #undef TARGET_ASM_ALIGNED_HI_OP | |
196 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
197 | #undef TARGET_ASM_ALIGNED_SI_OP | |
198 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
199 | #undef TARGET_ASM_ALIGNED_DI_OP | |
200 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
201 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
202 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
203 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
204 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
205 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
206 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
207 | #undef TARGET_ASM_INTEGER | |
208 | #define TARGET_ASM_INTEGER pa_assemble_integer | |
209 | ||
17d9b0c3 | 210 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
211 | #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue | |
212 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
213 | #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue | |
e3f53689 | 214 | |
747af5e7 | 215 | #undef TARGET_SCHED_ADJUST_COST |
216 | #define TARGET_SCHED_ADJUST_COST pa_adjust_cost | |
217 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
218 | #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority | |
219 | #undef TARGET_SCHED_ISSUE_RATE | |
220 | #define TARGET_SCHED_ISSUE_RATE pa_issue_rate | |
221 | ||
7811991d | 222 | #undef TARGET_ENCODE_SECTION_INFO |
223 | #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info | |
7b4a38a6 | 224 | #undef TARGET_STRIP_NAME_ENCODING |
225 | #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding | |
7811991d | 226 | |
805e22b2 | 227 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
228 | #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall | |
229 | ||
280566a7 | 230 | #undef TARGET_COMMUTATIVE_P |
231 | #define TARGET_COMMUTATIVE_P pa_commutative_p | |
232 | ||
6988553d | 233 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
234 | #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk | |
eb344f43 | 235 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
236 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
6988553d | 237 | |
f6940372 | 238 | #undef TARGET_ASM_FILE_END |
5f43b4f6 | 239 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
240 | #define TARGET_ASM_FILE_END pa_hpux_file_end | |
241 | #else | |
f6940372 | 242 | #define TARGET_ASM_FILE_END output_deferred_plabels |
5f43b4f6 | 243 | #endif |
f6940372 | 244 | |
de419443 | 245 | #if !defined(USE_COLLECT2) |
246 | #undef TARGET_ASM_CONSTRUCTOR | |
247 | #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor | |
248 | #undef TARGET_ASM_DESTRUCTOR | |
249 | #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor | |
250 | #endif | |
251 | ||
bd57250e | 252 | #undef TARGET_DEFAULT_TARGET_FLAGS |
253 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT) | |
254 | #undef TARGET_HANDLE_OPTION | |
255 | #define TARGET_HANDLE_OPTION pa_handle_option | |
256 | ||
ffa8918b | 257 | #undef TARGET_INIT_BUILTINS |
258 | #define TARGET_INIT_BUILTINS pa_init_builtins | |
259 | ||
fab7adbf | 260 | #undef TARGET_RTX_COSTS |
261 | #define TARGET_RTX_COSTS hppa_rtx_costs | |
ec0457a8 | 262 | #undef TARGET_ADDRESS_COST |
263 | #define TARGET_ADDRESS_COST hppa_address_cost | |
fab7adbf | 264 | |
2efea8c0 | 265 | #undef TARGET_MACHINE_DEPENDENT_REORG |
266 | #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg | |
267 | ||
f2f543a3 | 268 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
269 | #undef TARGET_INIT_LIBFUNCS | |
270 | #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs | |
271 | #endif | |
272 | ||
b8debbe8 | 273 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
274 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
275 | #undef TARGET_PROMOTE_PROTOTYPES | |
276 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
277 | ||
278 | #undef TARGET_STRUCT_VALUE_RTX | |
279 | #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx | |
280 | #undef TARGET_RETURN_IN_MEMORY | |
281 | #define TARGET_RETURN_IN_MEMORY pa_return_in_memory | |
0336f0f0 | 282 | #undef TARGET_MUST_PASS_IN_STACK |
283 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
b981d932 | 284 | #undef TARGET_PASS_BY_REFERENCE |
285 | #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference | |
13f08ee7 | 286 | #undef TARGET_CALLEE_COPIES |
287 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
f054eb3c | 288 | #undef TARGET_ARG_PARTIAL_BYTES |
289 | #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes | |
b8debbe8 | 290 | |
291 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
292 | #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs | |
4c33eb68 | 293 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
294 | #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr | |
b8debbe8 | 295 | |
2b1e7cc3 | 296 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
297 | #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p | |
298 | ||
716b2c5a | 299 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
300 | #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p | |
301 | ||
57e4bbfb | 302 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 303 | \f |
320e1276 | 304 | /* Parse the -mfixed-range= option string. */ |
305 | ||
306 | static void | |
307 | fix_range (const char *const_str) | |
308 | { | |
309 | int i, first, last; | |
310 | char *str, *dash, *comma; | |
311 | ||
312 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and | |
313 | REG2 are either register names or register numbers. The effect | |
314 | of this option is to mark the registers in the range from REG1 to | |
315 | REG2 as ``fixed'' so they won't be used by the compiler. This is | |
765cebfc | 316 | used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */ |
320e1276 | 317 | |
318 | i = strlen (const_str); | |
319 | str = (char *) alloca (i + 1); | |
320 | memcpy (str, const_str, i + 1); | |
321 | ||
322 | while (1) | |
323 | { | |
324 | dash = strchr (str, '-'); | |
325 | if (!dash) | |
326 | { | |
c3ceba8e | 327 | warning (0, "value of -mfixed-range must have form REG1-REG2"); |
320e1276 | 328 | return; |
329 | } | |
330 | *dash = '\0'; | |
331 | ||
332 | comma = strchr (dash + 1, ','); | |
333 | if (comma) | |
334 | *comma = '\0'; | |
335 | ||
336 | first = decode_reg_name (str); | |
337 | if (first < 0) | |
338 | { | |
c3ceba8e | 339 | warning (0, "unknown register name: %s", str); |
320e1276 | 340 | return; |
341 | } | |
342 | ||
343 | last = decode_reg_name (dash + 1); | |
344 | if (last < 0) | |
345 | { | |
c3ceba8e | 346 | warning (0, "unknown register name: %s", dash + 1); |
320e1276 | 347 | return; |
348 | } | |
349 | ||
350 | *dash = '-'; | |
351 | ||
352 | if (first > last) | |
353 | { | |
c3ceba8e | 354 | warning (0, "%s-%s is an empty range", str, dash + 1); |
320e1276 | 355 | return; |
356 | } | |
357 | ||
358 | for (i = first; i <= last; ++i) | |
359 | fixed_regs[i] = call_used_regs[i] = 1; | |
360 | ||
361 | if (!comma) | |
362 | break; | |
363 | ||
364 | *comma = ','; | |
365 | str = comma + 1; | |
366 | } | |
367 | ||
368 | /* Check if all floating point registers have been fixed. */ | |
369 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
370 | if (!fixed_regs[i]) | |
371 | break; | |
372 | ||
373 | if (i > FP_REG_LAST) | |
374 | target_flags |= MASK_DISABLE_FPREGS; | |
375 | } | |
376 | ||
bd57250e | 377 | /* Implement TARGET_HANDLE_OPTION. */ |
c7a4e712 | 378 | |
bd57250e | 379 | static bool |
380 | pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
381 | { | |
382 | switch (code) | |
4dc42288 | 383 | { |
bd57250e | 384 | case OPT_mnosnake: |
385 | case OPT_mpa_risc_1_0: | |
386 | case OPT_march_1_0: | |
4dc42288 | 387 | target_flags &= ~(MASK_PA_11 | MASK_PA_20); |
bd57250e | 388 | return true; |
389 | ||
390 | case OPT_msnake: | |
391 | case OPT_mpa_risc_1_1: | |
392 | case OPT_march_1_1: | |
4dc42288 | 393 | target_flags &= ~MASK_PA_20; |
394 | target_flags |= MASK_PA_11; | |
bd57250e | 395 | return true; |
4dc42288 | 396 | |
bd57250e | 397 | case OPT_mpa_risc_2_0: |
398 | case OPT_march_2_0: | |
399 | target_flags |= MASK_PA_11 | MASK_PA_20; | |
400 | return true; | |
401 | ||
402 | case OPT_mschedule_: | |
403 | if (strcmp (arg, "8000") == 0) | |
404 | pa_cpu = PROCESSOR_8000; | |
405 | else if (strcmp (arg, "7100") == 0) | |
406 | pa_cpu = PROCESSOR_7100; | |
407 | else if (strcmp (arg, "700") == 0) | |
408 | pa_cpu = PROCESSOR_700; | |
409 | else if (strcmp (arg, "7100LC") == 0) | |
410 | pa_cpu = PROCESSOR_7100LC; | |
411 | else if (strcmp (arg, "7200") == 0) | |
412 | pa_cpu = PROCESSOR_7200; | |
413 | else if (strcmp (arg, "7300") == 0) | |
414 | pa_cpu = PROCESSOR_7300; | |
8ab32933 | 415 | else |
bd57250e | 416 | return false; |
417 | return true; | |
8ab32933 | 418 | |
bd57250e | 419 | case OPT_mfixed_range_: |
420 | fix_range (arg); | |
421 | return true; | |
320e1276 | 422 | |
bd57250e | 423 | #if TARGET_HPUX |
424 | case OPT_munix_93: | |
425 | flag_pa_unix = 1993; | |
426 | return true; | |
427 | #endif | |
428 | ||
429 | #if TARGET_HPUX_10_10 | |
430 | case OPT_munix_95: | |
431 | flag_pa_unix = 1995; | |
432 | return true; | |
433 | #endif | |
434 | ||
435 | #if TARGET_HPUX_11_11 | |
436 | case OPT_munix_98: | |
437 | flag_pa_unix = 1998; | |
438 | return true; | |
439 | #endif | |
440 | ||
441 | default: | |
442 | return true; | |
443 | } | |
444 | } | |
445 | ||
446 | void | |
447 | override_options (void) | |
448 | { | |
7c5101fc | 449 | /* Unconditional branches in the delay slot are not compatible with dwarf2 |
450 | call frame information. There is no benefit in using this optimization | |
451 | on PA8000 and later processors. */ | |
452 | if (pa_cpu >= PROCESSOR_8000 | |
453 | || (! USING_SJLJ_EXCEPTIONS && flag_exceptions) | |
454 | || flag_unwind_tables) | |
455 | target_flags &= ~MASK_JUMP_IN_DELAY; | |
456 | ||
c7a4e712 | 457 | if (flag_pic && TARGET_PORTABLE_RUNTIME) |
458 | { | |
0a81f5a0 | 459 | warning (0, "PIC code generation is not supported in the portable runtime model"); |
c7a4e712 | 460 | } |
461 | ||
b29897dd | 462 | if (flag_pic && TARGET_FAST_INDIRECT_CALLS) |
c7a4e712 | 463 | { |
0a81f5a0 | 464 | warning (0, "PIC code generation is not compatible with fast indirect calls"); |
c7a4e712 | 465 | } |
751e64a1 | 466 | |
5bd7b548 | 467 | if (! TARGET_GAS && write_symbols != NO_DEBUG) |
468 | { | |
c3ceba8e | 469 | warning (0, "-g is only supported when using GAS on this processor,"); |
470 | warning (0, "-g option disabled"); | |
5bd7b548 | 471 | write_symbols = NO_DEBUG; |
472 | } | |
5cb4669a | 473 | |
fc44315f | 474 | /* We only support the "big PIC" model now. And we always generate PIC |
475 | code when in 64bit mode. */ | |
476 | if (flag_pic == 1 || TARGET_64BIT) | |
5e3c5739 | 477 | flag_pic = 2; |
478 | ||
58356836 | 479 | /* We can't guarantee that .dword is available for 32-bit targets. */ |
480 | if (UNITS_PER_WORD == 4) | |
481 | targetm.asm_out.aligned_op.di = NULL; | |
482 | ||
483 | /* The unaligned ops are only available when using GAS. */ | |
484 | if (!TARGET_GAS) | |
485 | { | |
486 | targetm.asm_out.unaligned_op.hi = NULL; | |
487 | targetm.asm_out.unaligned_op.si = NULL; | |
488 | targetm.asm_out.unaligned_op.di = NULL; | |
489 | } | |
916c9cef | 490 | |
491 | init_machine_status = pa_init_machine_status; | |
134b4858 | 492 | } |
493 | ||
066397a3 | 494 | static void |
5c1d8983 | 495 | pa_init_builtins (void) |
ffa8918b | 496 | { |
497 | #ifdef DONT_HAVE_FPUTC_UNLOCKED | |
498 | built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE; | |
5ddc8fb8 | 499 | implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE; |
ffa8918b | 500 | #endif |
501 | } | |
502 | ||
916c9cef | 503 | /* Function to init struct machine_function. |
504 | This will be called, via a pointer variable, | |
505 | from push_function_context. */ | |
506 | ||
507 | static struct machine_function * | |
508 | pa_init_machine_status (void) | |
509 | { | |
510 | return ggc_alloc_cleared (sizeof (machine_function)); | |
511 | } | |
512 | ||
dbd3d89d | 513 | /* If FROM is a probable pointer register, mark TO as a probable |
514 | pointer register with the same pointer alignment as FROM. */ | |
515 | ||
516 | static void | |
517 | copy_reg_pointer (rtx to, rtx from) | |
518 | { | |
519 | if (REG_POINTER (from)) | |
520 | mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from))); | |
521 | } | |
522 | ||
6d36483b | 523 | /* Return 1 if X contains a symbolic expression. We know these |
524 | expressions will have one of a few well defined forms, so | |
347b5848 | 525 | we need only check those forms. */ |
526 | int | |
5c1d8983 | 527 | symbolic_expression_p (rtx x) |
347b5848 | 528 | { |
529 | ||
6dc3b0d9 | 530 | /* Strip off any HIGH. */ |
347b5848 | 531 | if (GET_CODE (x) == HIGH) |
532 | x = XEXP (x, 0); | |
533 | ||
534 | return (symbolic_operand (x, VOIDmode)); | |
535 | } | |
536 | ||
7c4d3047 | 537 | /* Accept any constant that can be moved in one instruction into a |
d9d7c968 | 538 | general register. */ |
6d36483b | 539 | int |
5c1d8983 | 540 | cint_ok_for_move (HOST_WIDE_INT intval) |
d9d7c968 | 541 | { |
542 | /* OK if ldo, ldil, or zdepi, can be used. */ | |
d8d5c4ff | 543 | return (CONST_OK_FOR_LETTER_P (intval, 'J') |
544 | || CONST_OK_FOR_LETTER_P (intval, 'N') | |
545 | || CONST_OK_FOR_LETTER_P (intval, 'K')); | |
d9d7c968 | 546 | } |
87ad11b0 | 547 | \f |
2a91e628 | 548 | /* Return truth value of whether OP can be used as an operand in a |
549 | adddi3 insn. */ | |
550 | int | |
5c1d8983 | 551 | adddi3_operand (rtx op, enum machine_mode mode) |
2a91e628 | 552 | { |
553 | return (register_operand (op, mode) | |
554 | || (GET_CODE (op) == CONST_INT | |
555 | && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op)))); | |
556 | } | |
557 | ||
ea52c577 | 558 | /* True iff zdepi can be used to generate this CONST_INT. |
559 | zdepi first sign extends a 5 bit signed number to a given field | |
560 | length, then places this field anywhere in a zero. */ | |
e057641f | 561 | int |
5c1d8983 | 562 | zdepi_cint_p (unsigned HOST_WIDE_INT x) |
fad0b60f | 563 | { |
3745c59b | 564 | unsigned HOST_WIDE_INT lsb_mask, t; |
fad0b60f | 565 | |
566 | /* This might not be obvious, but it's at least fast. | |
01cc3b75 | 567 | This function is critical; we don't have the time loops would take. */ |
42faba01 | 568 | lsb_mask = x & -x; |
569 | t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1); | |
570 | /* Return true iff t is a power of two. */ | |
fad0b60f | 571 | return ((t & (t - 1)) == 0); |
572 | } | |
573 | ||
6d36483b | 574 | /* True iff depi or extru can be used to compute (reg & mask). |
575 | Accept bit pattern like these: | |
576 | 0....01....1 | |
577 | 1....10....0 | |
578 | 1..10..01..1 */ | |
e057641f | 579 | int |
5c1d8983 | 580 | and_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 581 | { |
582 | mask = ~mask; | |
583 | mask += mask & -mask; | |
584 | return (mask & (mask - 1)) == 0; | |
585 | } | |
586 | ||
e057641f | 587 | /* True iff depi can be used to compute (reg | MASK). */ |
588 | int | |
5c1d8983 | 589 | ior_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 590 | { |
591 | mask += mask & -mask; | |
592 | return (mask & (mask - 1)) == 0; | |
593 | } | |
87ad11b0 | 594 | \f |
595 | /* Legitimize PIC addresses. If the address is already | |
596 | position-independent, we return ORIG. Newly generated | |
597 | position-independent addresses go to REG. If we need more | |
598 | than one register, we lose. */ | |
599 | ||
600 | rtx | |
5c1d8983 | 601 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
87ad11b0 | 602 | { |
603 | rtx pic_ref = orig; | |
604 | ||
f7229f19 | 605 | gcc_assert (!PA_SYMBOL_REF_TLS_P (orig)); |
716b2c5a | 606 | |
b090827b | 607 | /* Labels need special handling. */ |
611a88e1 | 608 | if (pic_label_operand (orig, mode)) |
b4a7bf10 | 609 | { |
2536cc16 | 610 | /* We do not want to go through the movXX expanders here since that |
611 | would create recursion. | |
612 | ||
613 | Nor do we really want to call a generator for a named pattern | |
614 | since that requires multiple patterns if we want to support | |
615 | multiple word sizes. | |
616 | ||
617 | So instead we just emit the raw set, which avoids the movXX | |
618 | expanders completely. */ | |
dbd3d89d | 619 | mark_reg_pointer (reg, BITS_PER_UNIT); |
2536cc16 | 620 | emit_insn (gen_rtx_SET (VOIDmode, reg, orig)); |
b4a7bf10 | 621 | current_function_uses_pic_offset_table = 1; |
622 | return reg; | |
623 | } | |
87ad11b0 | 624 | if (GET_CODE (orig) == SYMBOL_REF) |
625 | { | |
f9c1ba9d | 626 | rtx insn, tmp_reg; |
627 | ||
ecf2283d | 628 | gcc_assert (reg); |
87ad11b0 | 629 | |
f9c1ba9d | 630 | /* Before reload, allocate a temporary register for the intermediate |
631 | result. This allows the sequence to be deleted when the final | |
632 | result is unused and the insns are trivially dead. */ | |
633 | tmp_reg = ((reload_in_progress || reload_completed) | |
634 | ? reg : gen_reg_rtx (Pmode)); | |
635 | ||
636 | emit_move_insn (tmp_reg, | |
fc44315f | 637 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, |
638 | gen_rtx_HIGH (word_mode, orig))); | |
639 | pic_ref | |
e265a6da | 640 | = gen_const_mem (Pmode, |
641 | gen_rtx_LO_SUM (Pmode, tmp_reg, | |
642 | gen_rtx_UNSPEC (Pmode, | |
643 | gen_rtvec (1, orig), | |
644 | UNSPEC_DLTIND14R))); | |
7014838c | 645 | |
87ad11b0 | 646 | current_function_uses_pic_offset_table = 1; |
dbd3d89d | 647 | mark_reg_pointer (reg, BITS_PER_UNIT); |
f9c1ba9d | 648 | insn = emit_move_insn (reg, pic_ref); |
649 | ||
650 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
651 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn)); | |
652 | ||
87ad11b0 | 653 | return reg; |
654 | } | |
655 | else if (GET_CODE (orig) == CONST) | |
656 | { | |
57ed30e5 | 657 | rtx base; |
87ad11b0 | 658 | |
659 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
660 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
661 | return orig; | |
662 | ||
ecf2283d | 663 | gcc_assert (reg); |
664 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); | |
665 | ||
666 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
667 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
668 | base == reg ? 0 : reg); | |
dbd3d89d | 669 | |
87ad11b0 | 670 | if (GET_CODE (orig) == CONST_INT) |
671 | { | |
42faba01 | 672 | if (INT_14_BITS (orig)) |
b244d4c7 | 673 | return plus_constant (base, INTVAL (orig)); |
87ad11b0 | 674 | orig = force_reg (Pmode, orig); |
675 | } | |
ad851752 | 676 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
87ad11b0 | 677 | /* Likewise, should we set special REG_NOTEs here? */ |
678 | } | |
dbd3d89d | 679 | |
87ad11b0 | 680 | return pic_ref; |
681 | } | |
682 | ||
716b2c5a | 683 | static GTY(()) rtx gen_tls_tga; |
684 | ||
685 | static rtx | |
686 | gen_tls_get_addr (void) | |
687 | { | |
688 | if (!gen_tls_tga) | |
689 | gen_tls_tga = init_one_libfunc ("__tls_get_addr"); | |
690 | return gen_tls_tga; | |
691 | } | |
692 | ||
693 | static rtx | |
694 | hppa_tls_call (rtx arg) | |
695 | { | |
696 | rtx ret; | |
697 | ||
698 | ret = gen_reg_rtx (Pmode); | |
699 | emit_library_call_value (gen_tls_get_addr (), ret, | |
700 | LCT_CONST, Pmode, 1, arg, Pmode); | |
701 | ||
702 | return ret; | |
703 | } | |
704 | ||
705 | static rtx | |
706 | legitimize_tls_address (rtx addr) | |
707 | { | |
708 | rtx ret, insn, tmp, t1, t2, tp; | |
709 | enum tls_model model = SYMBOL_REF_TLS_MODEL (addr); | |
710 | ||
711 | switch (model) | |
712 | { | |
713 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
714 | tmp = gen_reg_rtx (Pmode); | |
715 | emit_insn (gen_tgd_load (tmp, addr)); | |
716 | ret = hppa_tls_call (tmp); | |
717 | break; | |
718 | ||
719 | case TLS_MODEL_LOCAL_DYNAMIC: | |
720 | ret = gen_reg_rtx (Pmode); | |
721 | tmp = gen_reg_rtx (Pmode); | |
722 | start_sequence (); | |
723 | emit_insn (gen_tld_load (tmp, addr)); | |
724 | t1 = hppa_tls_call (tmp); | |
725 | insn = get_insns (); | |
726 | end_sequence (); | |
727 | t2 = gen_reg_rtx (Pmode); | |
728 | emit_libcall_block (insn, t2, t1, | |
729 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
730 | UNSPEC_TLSLDBASE)); | |
731 | emit_insn (gen_tld_offset_load (ret, addr, t2)); | |
732 | break; | |
733 | ||
734 | case TLS_MODEL_INITIAL_EXEC: | |
735 | tp = gen_reg_rtx (Pmode); | |
736 | tmp = gen_reg_rtx (Pmode); | |
737 | ret = gen_reg_rtx (Pmode); | |
738 | emit_insn (gen_tp_load (tp)); | |
739 | emit_insn (gen_tie_load (tmp, addr)); | |
740 | emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp)); | |
741 | break; | |
742 | ||
743 | case TLS_MODEL_LOCAL_EXEC: | |
744 | tp = gen_reg_rtx (Pmode); | |
745 | ret = gen_reg_rtx (Pmode); | |
746 | emit_insn (gen_tp_load (tp)); | |
747 | emit_insn (gen_tle_load (ret, addr, tp)); | |
748 | break; | |
749 | ||
750 | default: | |
f7229f19 | 751 | gcc_unreachable (); |
716b2c5a | 752 | } |
753 | ||
754 | return ret; | |
755 | } | |
756 | ||
347b5848 | 757 | /* Try machine-dependent ways of modifying an illegitimate address |
758 | to be legitimate. If we find one, return the new, valid address. | |
759 | This macro is used in only one place: `memory_address' in explow.c. | |
760 | ||
761 | OLDX is the address as it was before break_out_memory_refs was called. | |
762 | In some cases it is useful to look at this to decide what needs to be done. | |
763 | ||
764 | MODE and WIN are passed so that this macro can use | |
765 | GO_IF_LEGITIMATE_ADDRESS. | |
766 | ||
767 | It is always safe for this macro to do nothing. It exists to recognize | |
6d36483b | 768 | opportunities to optimize the output. |
347b5848 | 769 | |
770 | For the PA, transform: | |
771 | ||
772 | memory(X + <large int>) | |
773 | ||
774 | into: | |
775 | ||
776 | if (<large int> & mask) >= 16 | |
777 | Y = (<large int> & ~mask) + mask + 1 Round up. | |
778 | else | |
779 | Y = (<large int> & ~mask) Round down. | |
780 | Z = X + Y | |
781 | memory (Z + (<large int> - Y)); | |
782 | ||
6d36483b | 783 | This is for CSE to find several similar references, and only use one Z. |
347b5848 | 784 | |
33f88b1c | 785 | X can either be a SYMBOL_REF or REG, but because combine cannot |
347b5848 | 786 | perform a 4->2 combination we do nothing for SYMBOL_REF + D where |
787 | D will not fit in 14 bits. | |
788 | ||
789 | MODE_FLOAT references allow displacements which fit in 5 bits, so use | |
6d36483b | 790 | 0x1f as the mask. |
347b5848 | 791 | |
792 | MODE_INT references allow displacements which fit in 14 bits, so use | |
6d36483b | 793 | 0x3fff as the mask. |
347b5848 | 794 | |
795 | This relies on the fact that most mode MODE_FLOAT references will use FP | |
796 | registers and most mode MODE_INT references will use integer registers. | |
797 | (In the rare case of an FP register used in an integer MODE, we depend | |
798 | on secondary reloads to clean things up.) | |
799 | ||
800 | ||
801 | It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special | |
802 | manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed | |
01cc3b75 | 803 | addressing modes to be used). |
347b5848 | 804 | |
805 | Put X and Z into registers. Then put the entire expression into | |
806 | a register. */ | |
807 | ||
808 | rtx | |
5c1d8983 | 809 | hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
810 | enum machine_mode mode) | |
347b5848 | 811 | { |
347b5848 | 812 | rtx orig = x; |
813 | ||
dbd3d89d | 814 | /* We need to canonicalize the order of operands in unscaled indexed |
815 | addresses since the code that checks if an address is valid doesn't | |
816 | always try both orders. */ | |
817 | if (!TARGET_NO_SPACE_REGS | |
818 | && GET_CODE (x) == PLUS | |
819 | && GET_MODE (x) == Pmode | |
820 | && REG_P (XEXP (x, 0)) | |
821 | && REG_P (XEXP (x, 1)) | |
822 | && REG_POINTER (XEXP (x, 0)) | |
823 | && !REG_POINTER (XEXP (x, 1))) | |
824 | return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0)); | |
825 | ||
716b2c5a | 826 | if (PA_SYMBOL_REF_TLS_P (x)) |
827 | return legitimize_tls_address (x); | |
828 | else if (flag_pic) | |
b4a7bf10 | 829 | return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); |
830 | ||
6dc3b0d9 | 831 | /* Strip off CONST. */ |
347b5848 | 832 | if (GET_CODE (x) == CONST) |
833 | x = XEXP (x, 0); | |
834 | ||
42819d4e | 835 | /* Special case. Get the SYMBOL_REF into a register and use indexing. |
836 | That should always be safe. */ | |
837 | if (GET_CODE (x) == PLUS | |
838 | && GET_CODE (XEXP (x, 0)) == REG | |
839 | && GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
840 | { | |
440c23df | 841 | rtx reg = force_reg (Pmode, XEXP (x, 1)); |
842 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0))); | |
42819d4e | 843 | } |
844 | ||
166bf021 | 845 | /* Note we must reject symbols which represent function addresses |
846 | since the assembler/linker can't handle arithmetic on plabels. */ | |
347b5848 | 847 | if (GET_CODE (x) == PLUS |
848 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
166bf021 | 849 | && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF |
850 | && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0))) | |
347b5848 | 851 | || GET_CODE (XEXP (x, 0)) == REG)) |
852 | { | |
853 | rtx int_part, ptr_reg; | |
854 | int newoffset; | |
855 | int offset = INTVAL (XEXP (x, 1)); | |
1b6f11e2 | 856 | int mask; |
857 | ||
858 | mask = (GET_MODE_CLASS (mode) == MODE_FLOAT | |
859 | ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff); | |
347b5848 | 860 | |
6d36483b | 861 | /* Choose which way to round the offset. Round up if we |
347b5848 | 862 | are >= halfway to the next boundary. */ |
863 | if ((offset & mask) >= ((mask + 1) / 2)) | |
864 | newoffset = (offset & ~ mask) + mask + 1; | |
865 | else | |
866 | newoffset = (offset & ~ mask); | |
867 | ||
868 | /* If the newoffset will not fit in 14 bits (ldo), then | |
869 | handling this would take 4 or 5 instructions (2 to load | |
870 | the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to | |
871 | add the new offset and the SYMBOL_REF.) Combine can | |
872 | not handle 4->2 or 5->2 combinations, so do not create | |
873 | them. */ | |
874 | if (! VAL_14_BITS_P (newoffset) | |
875 | && GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
876 | { | |
7014838c | 877 | rtx const_part = plus_constant (XEXP (x, 0), newoffset); |
347b5848 | 878 | rtx tmp_reg |
339613b4 | 879 | = force_reg (Pmode, |
ad851752 | 880 | gen_rtx_HIGH (Pmode, const_part)); |
347b5848 | 881 | ptr_reg |
339613b4 | 882 | = force_reg (Pmode, |
7014838c | 883 | gen_rtx_LO_SUM (Pmode, |
884 | tmp_reg, const_part)); | |
347b5848 | 885 | } |
886 | else | |
887 | { | |
888 | if (! VAL_14_BITS_P (newoffset)) | |
339613b4 | 889 | int_part = force_reg (Pmode, GEN_INT (newoffset)); |
347b5848 | 890 | else |
891 | int_part = GEN_INT (newoffset); | |
892 | ||
339613b4 | 893 | ptr_reg = force_reg (Pmode, |
ad851752 | 894 | gen_rtx_PLUS (Pmode, |
895 | force_reg (Pmode, XEXP (x, 0)), | |
896 | int_part)); | |
347b5848 | 897 | } |
898 | return plus_constant (ptr_reg, offset - newoffset); | |
899 | } | |
45f1285a | 900 | |
5115683e | 901 | /* Handle (plus (mult (a) (shadd_constant)) (b)). */ |
45f1285a | 902 | |
347b5848 | 903 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT |
904 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
45f1285a | 905 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))) |
6720e96c | 906 | && (OBJECT_P (XEXP (x, 1)) |
45f1285a | 907 | || GET_CODE (XEXP (x, 1)) == SUBREG) |
908 | && GET_CODE (XEXP (x, 1)) != CONST) | |
347b5848 | 909 | { |
910 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
911 | rtx reg1, reg2; | |
5115683e | 912 | |
913 | reg1 = XEXP (x, 1); | |
914 | if (GET_CODE (reg1) != REG) | |
915 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
916 | ||
917 | reg2 = XEXP (XEXP (x, 0), 0); | |
918 | if (GET_CODE (reg2) != REG) | |
919 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
920 | ||
ad851752 | 921 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 922 | gen_rtx_MULT (Pmode, |
923 | reg2, | |
924 | GEN_INT (val)), | |
ad851752 | 925 | reg1)); |
347b5848 | 926 | } |
45f1285a | 927 | |
00a87639 | 928 | /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)). |
929 | ||
930 | Only do so for floating point modes since this is more speculative | |
931 | and we lose if it's an integer store. */ | |
5115683e | 932 | if (GET_CODE (x) == PLUS |
00a87639 | 933 | && GET_CODE (XEXP (x, 0)) == PLUS |
934 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
935 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
5115683e | 936 | && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) |
937 | && (mode == SFmode || mode == DFmode)) | |
00a87639 | 938 | { |
5115683e | 939 | |
940 | /* First, try and figure out what to use as a base register. */ | |
941 | rtx reg1, reg2, base, idx, orig_base; | |
942 | ||
943 | reg1 = XEXP (XEXP (x, 0), 1); | |
944 | reg2 = XEXP (x, 1); | |
945 | base = NULL_RTX; | |
946 | idx = NULL_RTX; | |
947 | ||
948 | /* Make sure they're both regs. If one was a SYMBOL_REF [+ const], | |
e61a0a7f | 949 | then emit_move_sequence will turn on REG_POINTER so we'll know |
950 | it's a base register below. */ | |
5115683e | 951 | if (GET_CODE (reg1) != REG) |
952 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
953 | ||
954 | if (GET_CODE (reg2) != REG) | |
955 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
956 | ||
957 | /* Figure out what the base and index are. */ | |
9840d99d | 958 | |
5115683e | 959 | if (GET_CODE (reg1) == REG |
e61a0a7f | 960 | && REG_POINTER (reg1)) |
5115683e | 961 | { |
962 | base = reg1; | |
963 | orig_base = XEXP (XEXP (x, 0), 1); | |
ad851752 | 964 | idx = gen_rtx_PLUS (Pmode, |
965 | gen_rtx_MULT (Pmode, | |
966 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
967 | XEXP (XEXP (XEXP (x, 0), 0), 1)), | |
968 | XEXP (x, 1)); | |
5115683e | 969 | } |
970 | else if (GET_CODE (reg2) == REG | |
e61a0a7f | 971 | && REG_POINTER (reg2)) |
5115683e | 972 | { |
973 | base = reg2; | |
974 | orig_base = XEXP (x, 1); | |
975 | idx = XEXP (x, 0); | |
976 | } | |
977 | ||
978 | if (base == 0) | |
21f3ee9c | 979 | return orig; |
5115683e | 980 | |
981 | /* If the index adds a large constant, try to scale the | |
982 | constant so that it can be loaded with only one insn. */ | |
983 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
984 | && VAL_14_BITS_P (INTVAL (XEXP (idx, 1)) | |
985 | / INTVAL (XEXP (XEXP (idx, 0), 1))) | |
986 | && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0) | |
987 | { | |
988 | /* Divide the CONST_INT by the scale factor, then add it to A. */ | |
989 | int val = INTVAL (XEXP (idx, 1)); | |
990 | ||
991 | val /= INTVAL (XEXP (XEXP (idx, 0), 1)); | |
992 | reg1 = XEXP (XEXP (idx, 0), 0); | |
993 | if (GET_CODE (reg1) != REG) | |
994 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
995 | ||
ad851752 | 996 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val))); |
5115683e | 997 | |
998 | /* We can now generate a simple scaled indexed address. */ | |
7014838c | 999 | return |
1000 | force_reg | |
1001 | (Pmode, gen_rtx_PLUS (Pmode, | |
1002 | gen_rtx_MULT (Pmode, reg1, | |
1003 | XEXP (XEXP (idx, 0), 1)), | |
1004 | base)); | |
5115683e | 1005 | } |
1006 | ||
1007 | /* If B + C is still a valid base register, then add them. */ | |
1008 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1009 | && INTVAL (XEXP (idx, 1)) <= 4096 | |
1010 | && INTVAL (XEXP (idx, 1)) >= -4096) | |
1011 | { | |
1012 | int val = INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1013 | rtx reg1, reg2; | |
1014 | ||
ad851752 | 1015 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1))); |
5115683e | 1016 | |
1017 | reg2 = XEXP (XEXP (idx, 0), 0); | |
1018 | if (GET_CODE (reg2) != CONST_INT) | |
1019 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1020 | ||
ad851752 | 1021 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1022 | gen_rtx_MULT (Pmode, |
1023 | reg2, | |
ad851752 | 1024 | GEN_INT (val)), |
1025 | reg1)); | |
5115683e | 1026 | } |
1027 | ||
1028 | /* Get the index into a register, then add the base + index and | |
1029 | return a register holding the result. */ | |
1030 | ||
1031 | /* First get A into a register. */ | |
1032 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1033 | if (GET_CODE (reg1) != REG) | |
1034 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1035 | ||
1036 | /* And get B into a register. */ | |
1037 | reg2 = XEXP (idx, 1); | |
1038 | if (GET_CODE (reg2) != REG) | |
1039 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1040 | ||
ad851752 | 1041 | reg1 = force_reg (Pmode, |
1042 | gen_rtx_PLUS (Pmode, | |
1043 | gen_rtx_MULT (Pmode, reg1, | |
1044 | XEXP (XEXP (idx, 0), 1)), | |
1045 | reg2)); | |
5115683e | 1046 | |
1047 | /* Add the result to our base register and return. */ | |
ad851752 | 1048 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1)); |
9840d99d | 1049 | |
00a87639 | 1050 | } |
1051 | ||
6d36483b | 1052 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
fb5390c1 | 1053 | special handling to avoid creating an indexed memory address |
1054 | with x-100000 as the base. | |
9840d99d | 1055 | |
fb5390c1 | 1056 | If the constant part is small enough, then it's still safe because |
1057 | there is a guard page at the beginning and end of the data segment. | |
1058 | ||
1059 | Scaled references are common enough that we want to try and rearrange the | |
1060 | terms so that we can use indexing for these addresses too. Only | |
00a87639 | 1061 | do the optimization for floatint point modes. */ |
45f1285a | 1062 | |
fb5390c1 | 1063 | if (GET_CODE (x) == PLUS |
1064 | && symbolic_expression_p (XEXP (x, 1))) | |
45f1285a | 1065 | { |
1066 | /* Ugly. We modify things here so that the address offset specified | |
1067 | by the index expression is computed first, then added to x to form | |
fb5390c1 | 1068 | the entire address. */ |
45f1285a | 1069 | |
00a87639 | 1070 | rtx regx1, regx2, regy1, regy2, y; |
45f1285a | 1071 | |
1072 | /* Strip off any CONST. */ | |
1073 | y = XEXP (x, 1); | |
1074 | if (GET_CODE (y) == CONST) | |
1075 | y = XEXP (y, 0); | |
1076 | ||
7ee96d6e | 1077 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1078 | { | |
00a87639 | 1079 | /* See if this looks like |
1080 | (plus (mult (reg) (shadd_const)) | |
1081 | (const (plus (symbol_ref) (const_int)))) | |
1082 | ||
5115683e | 1083 | Where const_int is small. In that case the const |
9840d99d | 1084 | expression is a valid pointer for indexing. |
5115683e | 1085 | |
1086 | If const_int is big, but can be divided evenly by shadd_const | |
1087 | and added to (reg). This allows more scaled indexed addresses. */ | |
1088 | if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1089 | && GET_CODE (XEXP (x, 0)) == MULT | |
00a87639 | 1090 | && GET_CODE (XEXP (y, 1)) == CONST_INT |
5115683e | 1091 | && INTVAL (XEXP (y, 1)) >= -4096 |
1092 | && INTVAL (XEXP (y, 1)) <= 4095 | |
1093 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1094 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
1095 | { | |
1096 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1097 | rtx reg1, reg2; | |
1098 | ||
1099 | reg1 = XEXP (x, 1); | |
1100 | if (GET_CODE (reg1) != REG) | |
1101 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1102 | ||
1103 | reg2 = XEXP (XEXP (x, 0), 0); | |
1104 | if (GET_CODE (reg2) != REG) | |
1105 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1106 | ||
ad851752 | 1107 | return force_reg (Pmode, |
1108 | gen_rtx_PLUS (Pmode, | |
7014838c | 1109 | gen_rtx_MULT (Pmode, |
1110 | reg2, | |
ad851752 | 1111 | GEN_INT (val)), |
7014838c | 1112 | reg1)); |
5115683e | 1113 | } |
1114 | else if ((mode == DFmode || mode == SFmode) | |
1115 | && GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1116 | && GET_CODE (XEXP (x, 0)) == MULT | |
1117 | && GET_CODE (XEXP (y, 1)) == CONST_INT | |
1118 | && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0 | |
1119 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1120 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
00a87639 | 1121 | { |
1122 | regx1 | |
1123 | = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1)) | |
1124 | / INTVAL (XEXP (XEXP (x, 0), 1)))); | |
1125 | regx2 = XEXP (XEXP (x, 0), 0); | |
1126 | if (GET_CODE (regx2) != REG) | |
1127 | regx2 = force_reg (Pmode, force_operand (regx2, 0)); | |
ad851752 | 1128 | regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1129 | regx2, regx1)); | |
7014838c | 1130 | return |
1131 | force_reg (Pmode, | |
1132 | gen_rtx_PLUS (Pmode, | |
1133 | gen_rtx_MULT (Pmode, regx2, | |
1134 | XEXP (XEXP (x, 0), 1)), | |
1135 | force_reg (Pmode, XEXP (y, 0)))); | |
00a87639 | 1136 | } |
fb5390c1 | 1137 | else if (GET_CODE (XEXP (y, 1)) == CONST_INT |
1138 | && INTVAL (XEXP (y, 1)) >= -4096 | |
1139 | && INTVAL (XEXP (y, 1)) <= 4095) | |
1140 | { | |
1141 | /* This is safe because of the guard page at the | |
1142 | beginning and end of the data space. Just | |
1143 | return the original address. */ | |
1144 | return orig; | |
1145 | } | |
00a87639 | 1146 | else |
1147 | { | |
1148 | /* Doesn't look like one we can optimize. */ | |
1149 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1150 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1151 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1152 | regx1 = force_reg (Pmode, | |
ad851752 | 1153 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1154 | regx1, regy2)); | |
1155 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); | |
00a87639 | 1156 | } |
7ee96d6e | 1157 | } |
45f1285a | 1158 | } |
1159 | ||
347b5848 | 1160 | return orig; |
1161 | } | |
1162 | ||
87ad11b0 | 1163 | /* For the HPPA, REG and REG+CONST is cost 0 |
1164 | and addresses involving symbolic constants are cost 2. | |
1165 | ||
1166 | PIC addresses are very expensive. | |
1167 | ||
1168 | It is no coincidence that this has the same structure | |
1169 | as GO_IF_LEGITIMATE_ADDRESS. */ | |
ec0457a8 | 1170 | |
1171 | static int | |
5c1d8983 | 1172 | hppa_address_cost (rtx X) |
87ad11b0 | 1173 | { |
ec0457a8 | 1174 | switch (GET_CODE (X)) |
1175 | { | |
1176 | case REG: | |
1177 | case PLUS: | |
1178 | case LO_SUM: | |
87ad11b0 | 1179 | return 1; |
ec0457a8 | 1180 | case HIGH: |
1181 | return 2; | |
1182 | default: | |
1183 | return 4; | |
1184 | } | |
87ad11b0 | 1185 | } |
1186 | ||
fab7adbf | 1187 | /* Compute a (partial) cost for rtx X. Return true if the complete |
1188 | cost has been computed, and false if subexpressions should be | |
1189 | scanned. In either case, *TOTAL contains the cost result. */ | |
1190 | ||
1191 | static bool | |
5c1d8983 | 1192 | hppa_rtx_costs (rtx x, int code, int outer_code, int *total) |
fab7adbf | 1193 | { |
1194 | switch (code) | |
1195 | { | |
1196 | case CONST_INT: | |
1197 | if (INTVAL (x) == 0) | |
1198 | *total = 0; | |
1199 | else if (INT_14_BITS (x)) | |
1200 | *total = 1; | |
1201 | else | |
1202 | *total = 2; | |
1203 | return true; | |
1204 | ||
1205 | case HIGH: | |
1206 | *total = 2; | |
1207 | return true; | |
1208 | ||
1209 | case CONST: | |
1210 | case LABEL_REF: | |
1211 | case SYMBOL_REF: | |
1212 | *total = 4; | |
1213 | return true; | |
1214 | ||
1215 | case CONST_DOUBLE: | |
1216 | if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode)) | |
1217 | && outer_code != SET) | |
1218 | *total = 0; | |
1219 | else | |
1220 | *total = 8; | |
1221 | return true; | |
1222 | ||
1223 | case MULT: | |
1224 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1225 | *total = COSTS_N_INSNS (3); | |
1226 | else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT) | |
1227 | *total = COSTS_N_INSNS (8); | |
1228 | else | |
1229 | *total = COSTS_N_INSNS (20); | |
1230 | return true; | |
1231 | ||
1232 | case DIV: | |
1233 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1234 | { | |
1235 | *total = COSTS_N_INSNS (14); | |
1236 | return true; | |
1237 | } | |
8e262b5e | 1238 | /* FALLTHRU */ |
fab7adbf | 1239 | |
1240 | case UDIV: | |
1241 | case MOD: | |
1242 | case UMOD: | |
1243 | *total = COSTS_N_INSNS (60); | |
1244 | return true; | |
1245 | ||
1246 | case PLUS: /* this includes shNadd insns */ | |
1247 | case MINUS: | |
1248 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1249 | *total = COSTS_N_INSNS (3); | |
1250 | else | |
1251 | *total = COSTS_N_INSNS (1); | |
1252 | return true; | |
1253 | ||
1254 | case ASHIFT: | |
1255 | case ASHIFTRT: | |
1256 | case LSHIFTRT: | |
1257 | *total = COSTS_N_INSNS (1); | |
1258 | return true; | |
1259 | ||
1260 | default: | |
1261 | return false; | |
1262 | } | |
1263 | } | |
1264 | ||
9840d99d | 1265 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a |
1266 | new rtx with the correct mode. */ | |
1267 | static inline rtx | |
5c1d8983 | 1268 | force_mode (enum machine_mode mode, rtx orig) |
9840d99d | 1269 | { |
1270 | if (mode == GET_MODE (orig)) | |
1271 | return orig; | |
1272 | ||
ecf2283d | 1273 | gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER); |
9840d99d | 1274 | |
1275 | return gen_rtx_REG (mode, REGNO (orig)); | |
1276 | } | |
1277 | ||
716b2c5a | 1278 | /* Return 1 if *X is a thread-local symbol. */ |
1279 | ||
1280 | static int | |
1281 | pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
1282 | { | |
1283 | return PA_SYMBOL_REF_TLS_P (*x); | |
1284 | } | |
1285 | ||
1286 | /* Return 1 if X contains a thread-local symbol. */ | |
1287 | ||
1288 | bool | |
1289 | pa_tls_referenced_p (rtx x) | |
1290 | { | |
1291 | if (!TARGET_HAVE_TLS) | |
1292 | return false; | |
1293 | ||
1294 | return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0); | |
1295 | } | |
1296 | ||
87ad11b0 | 1297 | /* Emit insns to move operands[1] into operands[0]. |
1298 | ||
1299 | Return 1 if we have written out everything that needs to be done to | |
1300 | do the move. Otherwise, return 0 and the caller will emit the move | |
9840d99d | 1301 | normally. |
f756078b | 1302 | |
1303 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
2cecd772 | 1304 | will be used. This routine is responsible for creating a new copy |
f756078b | 1305 | of SCRATCH_REG in the proper mode. */ |
87ad11b0 | 1306 | |
1307 | int | |
5c1d8983 | 1308 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) |
87ad11b0 | 1309 | { |
1310 | register rtx operand0 = operands[0]; | |
1311 | register rtx operand1 = operands[1]; | |
4a155b0f | 1312 | register rtx tem; |
87ad11b0 | 1313 | |
dbd3d89d | 1314 | /* We can only handle indexed addresses in the destination operand |
1315 | of floating point stores. Thus, we need to break out indexed | |
1316 | addresses from the destination operand. */ | |
1317 | if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0))) | |
1318 | { | |
1319 | /* This is only safe up to the beginning of life analysis. */ | |
ecf2283d | 1320 | gcc_assert (!no_new_pseudos); |
dbd3d89d | 1321 | |
1322 | tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0)); | |
1323 | operand0 = replace_equiv_address (operand0, tem); | |
1324 | } | |
1325 | ||
1326 | /* On targets with non-equivalent space registers, break out unscaled | |
1327 | indexed addresses from the source operand before the final CSE. | |
1328 | We have to do this because the REG_POINTER flag is not correctly | |
1329 | carried through various optimization passes and CSE may substitute | |
1330 | a pseudo without the pointer set for one with the pointer set. As | |
5aedf60c | 1331 | a result, we loose various opportunities to create insns with |
dbd3d89d | 1332 | unscaled indexed addresses. */ |
1333 | if (!TARGET_NO_SPACE_REGS | |
1334 | && !cse_not_expected | |
1335 | && GET_CODE (operand1) == MEM | |
1336 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1337 | && REG_P (XEXP (XEXP (operand1, 0), 0)) | |
1338 | && REG_P (XEXP (XEXP (operand1, 0), 1))) | |
1339 | operand1 | |
1340 | = replace_equiv_address (operand1, | |
1341 | copy_to_mode_reg (Pmode, XEXP (operand1, 0))); | |
1342 | ||
2d4dc8d2 | 1343 | if (scratch_reg |
1344 | && reload_in_progress && GET_CODE (operand0) == REG | |
d1e2bb73 | 1345 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) |
1346 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2d4dc8d2 | 1347 | else if (scratch_reg |
1348 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
d1e2bb73 | 1349 | && GET_CODE (SUBREG_REG (operand0)) == REG |
1350 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1351 | { |
701e46d0 | 1352 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1353 | the code which tracks sets/uses for delete_output_reload. */ |
1354 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
1355 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
701e46d0 | 1356 | SUBREG_BYTE (operand0)); |
e00b80b2 | 1357 | operand0 = alter_subreg (&temp); |
a3afad75 | 1358 | } |
d1e2bb73 | 1359 | |
2d4dc8d2 | 1360 | if (scratch_reg |
1361 | && reload_in_progress && GET_CODE (operand1) == REG | |
d1e2bb73 | 1362 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) |
1363 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2d4dc8d2 | 1364 | else if (scratch_reg |
1365 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
d1e2bb73 | 1366 | && GET_CODE (SUBREG_REG (operand1)) == REG |
1367 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1368 | { |
701e46d0 | 1369 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1370 | the code which tracks sets/uses for delete_output_reload. */ |
1371 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
1372 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
701e46d0 | 1373 | SUBREG_BYTE (operand1)); |
e00b80b2 | 1374 | operand1 = alter_subreg (&temp); |
a3afad75 | 1375 | } |
d1e2bb73 | 1376 | |
2d4dc8d2 | 1377 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM |
4a155b0f | 1378 | && ((tem = find_replacement (&XEXP (operand0, 0))) |
1379 | != XEXP (operand0, 0))) | |
ed498904 | 1380 | operand0 = replace_equiv_address (operand0, tem); |
dbd3d89d | 1381 | |
2d4dc8d2 | 1382 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM |
4a155b0f | 1383 | && ((tem = find_replacement (&XEXP (operand1, 0))) |
1384 | != XEXP (operand1, 0))) | |
ed498904 | 1385 | operand1 = replace_equiv_address (operand1, tem); |
4a155b0f | 1386 | |
e8fdbafa | 1387 | /* Handle secondary reloads for loads/stores of FP registers from |
047e3121 | 1388 | REG+D addresses where D does not fit in 5 or 14 bits, including |
42819d4e | 1389 | (subreg (mem (addr))) cases. */ |
6bcdc1fb | 1390 | if (scratch_reg |
1391 | && fp_reg_operand (operand0, mode) | |
6b1c36c2 | 1392 | && ((GET_CODE (operand1) == MEM |
047e3121 | 1393 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode), |
1394 | XEXP (operand1, 0))) | |
6b1c36c2 | 1395 | || ((GET_CODE (operand1) == SUBREG |
1396 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
047e3121 | 1397 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1398 | ? SFmode : DFmode), | |
1399 | XEXP (XEXP (operand1, 0), 0)))))) | |
d6f01525 | 1400 | { |
6b1c36c2 | 1401 | if (GET_CODE (operand1) == SUBREG) |
1402 | operand1 = XEXP (operand1, 0); | |
1403 | ||
f756078b | 1404 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1405 | it in WORD_MODE regardless of what mode it was originally given | |
1406 | to us. */ | |
9840d99d | 1407 | scratch_reg = force_mode (word_mode, scratch_reg); |
7ee39d73 | 1408 | |
1409 | /* D might not fit in 14 bits either; for such cases load D into | |
1410 | scratch reg. */ | |
440c23df | 1411 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) |
7ee39d73 | 1412 | { |
1413 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
dbd3d89d | 1414 | emit_move_insn (scratch_reg, |
1415 | gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
1416 | Pmode, | |
1417 | XEXP (XEXP (operand1, 0), 0), | |
1418 | scratch_reg)); | |
7ee39d73 | 1419 | } |
1420 | else | |
1421 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
7014838c | 1422 | emit_insn (gen_rtx_SET (VOIDmode, operand0, |
ed498904 | 1423 | replace_equiv_address (operand1, scratch_reg))); |
d6f01525 | 1424 | return 1; |
1425 | } | |
6bcdc1fb | 1426 | else if (scratch_reg |
1427 | && fp_reg_operand (operand1, mode) | |
6b1c36c2 | 1428 | && ((GET_CODE (operand0) == MEM |
047e3121 | 1429 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1430 | ? SFmode : DFmode), | |
1431 | XEXP (operand0, 0))) | |
6b1c36c2 | 1432 | || ((GET_CODE (operand0) == SUBREG) |
1433 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
047e3121 | 1434 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1435 | ? SFmode : DFmode), | |
6bcdc1fb | 1436 | XEXP (XEXP (operand0, 0), 0))))) |
d6f01525 | 1437 | { |
6b1c36c2 | 1438 | if (GET_CODE (operand0) == SUBREG) |
1439 | operand0 = XEXP (operand0, 0); | |
1440 | ||
f756078b | 1441 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1442 | it in WORD_MODE regardless of what mode it was originally given | |
1443 | to us. */ | |
9840d99d | 1444 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1445 | |
7ee39d73 | 1446 | /* D might not fit in 14 bits either; for such cases load D into |
1447 | scratch reg. */ | |
440c23df | 1448 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) |
7ee39d73 | 1449 | { |
1450 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
ad851752 | 1451 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, |
1452 | 0)), | |
440c23df | 1453 | Pmode, |
ad851752 | 1454 | XEXP (XEXP (operand0, 0), |
1455 | 0), | |
1456 | scratch_reg)); | |
7ee39d73 | 1457 | } |
1458 | else | |
1459 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
ed498904 | 1460 | emit_insn (gen_rtx_SET (VOIDmode, |
1461 | replace_equiv_address (operand0, scratch_reg), | |
ad851752 | 1462 | operand1)); |
d6f01525 | 1463 | return 1; |
1464 | } | |
753bd06a | 1465 | /* Handle secondary reloads for loads of FP registers from constant |
1466 | expressions by forcing the constant into memory. | |
1467 | ||
6bcdc1fb | 1468 | Use scratch_reg to hold the address of the memory location. |
753bd06a | 1469 | |
9dc4cbf1 | 1470 | The proper fix is to change PREFERRED_RELOAD_CLASS to return |
87fcb603 | 1471 | NO_REGS when presented with a const_int and a register class |
753bd06a | 1472 | containing only FP registers. Doing so unfortunately creates |
1473 | more problems than it solves. Fix this for 2.5. */ | |
6bcdc1fb | 1474 | else if (scratch_reg |
753bd06a | 1475 | && CONSTANT_P (operand1) |
6bcdc1fb | 1476 | && fp_reg_operand (operand0, mode)) |
753bd06a | 1477 | { |
ed498904 | 1478 | rtx const_mem, xoperands[2]; |
753bd06a | 1479 | |
f756078b | 1480 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1481 | it in WORD_MODE regardless of what mode it was originally given | |
1482 | to us. */ | |
9840d99d | 1483 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1484 | |
753bd06a | 1485 | /* Force the constant into memory and put the address of the |
1486 | memory location into scratch_reg. */ | |
ed498904 | 1487 | const_mem = force_const_mem (mode, operand1); |
753bd06a | 1488 | xoperands[0] = scratch_reg; |
ed498904 | 1489 | xoperands[1] = XEXP (const_mem, 0); |
8f258b49 | 1490 | emit_move_sequence (xoperands, Pmode, 0); |
753bd06a | 1491 | |
1492 | /* Now load the destination register. */ | |
7014838c | 1493 | emit_insn (gen_rtx_SET (mode, operand0, |
ed498904 | 1494 | replace_equiv_address (const_mem, scratch_reg))); |
753bd06a | 1495 | return 1; |
1496 | } | |
e8fdbafa | 1497 | /* Handle secondary reloads for SAR. These occur when trying to load |
2a170404 | 1498 | the SAR from memory, FP register, or with a constant. */ |
6bcdc1fb | 1499 | else if (scratch_reg |
1500 | && GET_CODE (operand0) == REG | |
2a170404 | 1501 | && REGNO (operand0) < FIRST_PSEUDO_REGISTER |
e8fdbafa | 1502 | && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS |
1503 | && (GET_CODE (operand1) == MEM | |
7d43e0f7 | 1504 | || GET_CODE (operand1) == CONST_INT |
e8fdbafa | 1505 | || (GET_CODE (operand1) == REG |
6bcdc1fb | 1506 | && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))) |
e8fdbafa | 1507 | { |
7eac600c | 1508 | /* D might not fit in 14 bits either; for such cases load D into |
1509 | scratch reg. */ | |
1510 | if (GET_CODE (operand1) == MEM | |
440c23df | 1511 | && !memory_address_p (Pmode, XEXP (operand1, 0))) |
7eac600c | 1512 | { |
fc4d127d | 1513 | /* We are reloading the address into the scratch register, so we |
1514 | want to make sure the scratch register is a full register. */ | |
9840d99d | 1515 | scratch_reg = force_mode (word_mode, scratch_reg); |
fc4d127d | 1516 | |
9840d99d | 1517 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); |
ad851752 | 1518 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, |
1519 | 0)), | |
440c23df | 1520 | Pmode, |
ad851752 | 1521 | XEXP (XEXP (operand1, 0), |
1522 | 0), | |
1523 | scratch_reg)); | |
fc4d127d | 1524 | |
1525 | /* Now we are going to load the scratch register from memory, | |
1526 | we want to load it in the same width as the original MEM, | |
1527 | which must be the same as the width of the ultimate destination, | |
1528 | OPERAND0. */ | |
9840d99d | 1529 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1530 | ||
ed498904 | 1531 | emit_move_insn (scratch_reg, |
1532 | replace_equiv_address (operand1, scratch_reg)); | |
7eac600c | 1533 | } |
1534 | else | |
fc4d127d | 1535 | { |
1536 | /* We want to load the scratch register using the same mode as | |
1537 | the ultimate destination. */ | |
9840d99d | 1538 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1539 | ||
fc4d127d | 1540 | emit_move_insn (scratch_reg, operand1); |
1541 | } | |
1542 | ||
1543 | /* And emit the insn to set the ultimate destination. We know that | |
1544 | the scratch register has the same mode as the destination at this | |
1545 | point. */ | |
e8fdbafa | 1546 | emit_move_insn (operand0, scratch_reg); |
1547 | return 1; | |
1548 | } | |
dbd3d89d | 1549 | /* Handle the most common case: storing into a register. */ |
d6f01525 | 1550 | else if (register_operand (operand0, mode)) |
87ad11b0 | 1551 | { |
1552 | if (register_operand (operand1, mode) | |
93f6e1c7 | 1553 | || (GET_CODE (operand1) == CONST_INT |
1554 | && cint_ok_for_move (INTVAL (operand1))) | |
891b55b4 | 1555 | || (operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1556 | || (GET_CODE (operand1) == HIGH |
df0651dc | 1557 | && !symbolic_operand (XEXP (operand1, 0), VOIDmode)) |
87ad11b0 | 1558 | /* Only `general_operands' can come here, so MEM is ok. */ |
1559 | || GET_CODE (operand1) == MEM) | |
1560 | { | |
dbd3d89d | 1561 | /* Various sets are created during RTL generation which don't |
1562 | have the REG_POINTER flag correctly set. After the CSE pass, | |
1563 | instruction recognition can fail if we don't consistently | |
1564 | set this flag when performing register copies. This should | |
1565 | also improve the opportunities for creating insns that use | |
1566 | unscaled indexing. */ | |
1567 | if (REG_P (operand0) && REG_P (operand1)) | |
1568 | { | |
1569 | if (REG_POINTER (operand1) | |
1570 | && !REG_POINTER (operand0) | |
1571 | && !HARD_REGISTER_P (operand0)) | |
1572 | copy_reg_pointer (operand0, operand1); | |
1573 | else if (REG_POINTER (operand0) | |
1574 | && !REG_POINTER (operand1) | |
1575 | && !HARD_REGISTER_P (operand1)) | |
1576 | copy_reg_pointer (operand1, operand0); | |
1577 | } | |
1578 | ||
1579 | /* When MEMs are broken out, the REG_POINTER flag doesn't | |
1580 | get set. In some cases, we can set the REG_POINTER flag | |
1581 | from the declaration for the MEM. */ | |
1582 | if (REG_P (operand0) | |
1583 | && GET_CODE (operand1) == MEM | |
1584 | && !REG_POINTER (operand0)) | |
1585 | { | |
1586 | tree decl = MEM_EXPR (operand1); | |
1587 | ||
1588 | /* Set the register pointer flag and register alignment | |
1589 | if the declaration for this memory reference is a | |
1590 | pointer type. Fortran indirect argument references | |
1591 | are ignored. */ | |
1592 | if (decl | |
1593 | && !(flag_argument_noalias > 1 | |
1594 | && TREE_CODE (decl) == INDIRECT_REF | |
1595 | && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL)) | |
1596 | { | |
1597 | tree type; | |
1598 | ||
1599 | /* If this is a COMPONENT_REF, use the FIELD_DECL from | |
1600 | tree operand 1. */ | |
1601 | if (TREE_CODE (decl) == COMPONENT_REF) | |
1602 | decl = TREE_OPERAND (decl, 1); | |
1603 | ||
1604 | type = TREE_TYPE (decl); | |
1605 | if (TREE_CODE (type) == ARRAY_TYPE) | |
1606 | type = get_inner_array_type (type); | |
1607 | ||
1608 | if (POINTER_TYPE_P (type)) | |
1609 | { | |
1610 | int align; | |
1611 | ||
1612 | type = TREE_TYPE (type); | |
1613 | /* Using TYPE_ALIGN_OK is rather conservative as | |
1614 | only the ada frontend actually sets it. */ | |
1615 | align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type) | |
1616 | : BITS_PER_UNIT); | |
1617 | mark_reg_pointer (operand0, align); | |
1618 | } | |
1619 | } | |
1620 | } | |
1621 | ||
ad851752 | 1622 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1623 | return 1; |
1624 | } | |
1625 | } | |
1626 | else if (GET_CODE (operand0) == MEM) | |
1627 | { | |
85eb4c6e | 1628 | if (mode == DFmode && operand1 == CONST0_RTX (mode) |
1629 | && !(reload_in_progress || reload_completed)) | |
1630 | { | |
1631 | rtx temp = gen_reg_rtx (DFmode); | |
1632 | ||
ad851752 | 1633 | emit_insn (gen_rtx_SET (VOIDmode, temp, operand1)); |
1634 | emit_insn (gen_rtx_SET (VOIDmode, operand0, temp)); | |
85eb4c6e | 1635 | return 1; |
1636 | } | |
891b55b4 | 1637 | if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1638 | { |
1639 | /* Run this case quickly. */ | |
ad851752 | 1640 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1641 | return 1; |
1642 | } | |
2ff4bf8d | 1643 | if (! (reload_in_progress || reload_completed)) |
87ad11b0 | 1644 | { |
1645 | operands[0] = validize_mem (operand0); | |
1646 | operands[1] = operand1 = force_reg (mode, operand1); | |
1647 | } | |
1648 | } | |
1649 | ||
37a75d53 | 1650 | /* Simplify the source if we need to. |
1651 | Note we do have to handle function labels here, even though we do | |
1652 | not consider them legitimate constants. Loop optimizations can | |
bea60f66 | 1653 | call the emit_move_xxx with one as a source. */ |
57ed30e5 | 1654 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) |
37a75d53 | 1655 | || function_label_operand (operand1, mode) |
2ee034bc | 1656 | || (GET_CODE (operand1) == HIGH |
63882853 | 1657 | && symbolic_operand (XEXP (operand1, 0), mode))) |
87ad11b0 | 1658 | { |
2ee034bc | 1659 | int ishighonly = 0; |
1660 | ||
1661 | if (GET_CODE (operand1) == HIGH) | |
1662 | { | |
1663 | ishighonly = 1; | |
1664 | operand1 = XEXP (operand1, 0); | |
1665 | } | |
87ad11b0 | 1666 | if (symbolic_operand (operand1, mode)) |
1667 | { | |
005a7dd0 | 1668 | /* Argh. The assembler and linker can't handle arithmetic |
81653f9b | 1669 | involving plabels. |
005a7dd0 | 1670 | |
81653f9b | 1671 | So we force the plabel into memory, load operand0 from |
1672 | the memory location, then add in the constant part. */ | |
37a75d53 | 1673 | if ((GET_CODE (operand1) == CONST |
1674 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1675 | && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode)) | |
1676 | || function_label_operand (operand1, mode)) | |
005a7dd0 | 1677 | { |
b3d569a0 | 1678 | rtx temp, const_part; |
81653f9b | 1679 | |
1680 | /* Figure out what (if any) scratch register to use. */ | |
1681 | if (reload_in_progress || reload_completed) | |
f756078b | 1682 | { |
1683 | scratch_reg = scratch_reg ? scratch_reg : operand0; | |
1684 | /* SCRATCH_REG will hold an address and maybe the actual | |
1685 | data. We want it in WORD_MODE regardless of what mode it | |
1686 | was originally given to us. */ | |
9840d99d | 1687 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1688 | } |
81653f9b | 1689 | else if (flag_pic) |
1690 | scratch_reg = gen_reg_rtx (Pmode); | |
1691 | ||
37a75d53 | 1692 | if (GET_CODE (operand1) == CONST) |
1693 | { | |
1694 | /* Save away the constant part of the expression. */ | |
1695 | const_part = XEXP (XEXP (operand1, 0), 1); | |
ecf2283d | 1696 | gcc_assert (GET_CODE (const_part) == CONST_INT); |
37a75d53 | 1697 | |
1698 | /* Force the function label into memory. */ | |
1699 | temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0)); | |
1700 | } | |
1701 | else | |
1702 | { | |
1703 | /* No constant part. */ | |
1704 | const_part = NULL_RTX; | |
005a7dd0 | 1705 | |
37a75d53 | 1706 | /* Force the function label into memory. */ |
1707 | temp = force_const_mem (mode, operand1); | |
1708 | } | |
9840d99d | 1709 | |
81653f9b | 1710 | |
1711 | /* Get the address of the memory location. PIC-ify it if | |
1712 | necessary. */ | |
1713 | temp = XEXP (temp, 0); | |
1714 | if (flag_pic) | |
1715 | temp = legitimize_pic_address (temp, mode, scratch_reg); | |
1716 | ||
1717 | /* Put the address of the memory location into our destination | |
1718 | register. */ | |
1719 | operands[1] = temp; | |
1720 | emit_move_sequence (operands, mode, scratch_reg); | |
1721 | ||
1722 | /* Now load from the memory location into our destination | |
1723 | register. */ | |
ad851752 | 1724 | operands[1] = gen_rtx_MEM (Pmode, operands[0]); |
81653f9b | 1725 | emit_move_sequence (operands, mode, scratch_reg); |
1726 | ||
1727 | /* And add back in the constant part. */ | |
37a75d53 | 1728 | if (const_part != NULL_RTX) |
1729 | expand_inc (operand0, const_part); | |
81653f9b | 1730 | |
1731 | return 1; | |
005a7dd0 | 1732 | } |
1733 | ||
87ad11b0 | 1734 | if (flag_pic) |
1735 | { | |
2ff4bf8d | 1736 | rtx temp; |
1737 | ||
1738 | if (reload_in_progress || reload_completed) | |
f756078b | 1739 | { |
1740 | temp = scratch_reg ? scratch_reg : operand0; | |
1741 | /* TEMP will hold an address and maybe the actual | |
1742 | data. We want it in WORD_MODE regardless of what mode it | |
1743 | was originally given to us. */ | |
9840d99d | 1744 | temp = force_mode (word_mode, temp); |
f756078b | 1745 | } |
2ff4bf8d | 1746 | else |
1747 | temp = gen_reg_rtx (Pmode); | |
6d36483b | 1748 | |
81653f9b | 1749 | /* (const (plus (symbol) (const_int))) must be forced to |
1750 | memory during/after reload if the const_int will not fit | |
1751 | in 14 bits. */ | |
1752 | if (GET_CODE (operand1) == CONST | |
96b86ab6 | 1753 | && GET_CODE (XEXP (operand1, 0)) == PLUS |
1754 | && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT | |
1755 | && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)) | |
1756 | && (reload_completed || reload_in_progress) | |
1757 | && flag_pic) | |
1758 | { | |
ed498904 | 1759 | rtx const_mem = force_const_mem (mode, operand1); |
4109fd6d | 1760 | operands[1] = legitimize_pic_address (XEXP (const_mem, 0), |
96b86ab6 | 1761 | mode, temp); |
ed498904 | 1762 | operands[1] = replace_equiv_address (const_mem, operands[1]); |
96b86ab6 | 1763 | emit_move_sequence (operands, mode, temp); |
1764 | } | |
005a7dd0 | 1765 | else |
1766 | { | |
1767 | operands[1] = legitimize_pic_address (operand1, mode, temp); | |
dbd3d89d | 1768 | if (REG_P (operand0) && REG_P (operands[1])) |
1769 | copy_reg_pointer (operand0, operands[1]); | |
ad851752 | 1770 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1])); |
005a7dd0 | 1771 | } |
87ad11b0 | 1772 | } |
b4a7bf10 | 1773 | /* On the HPPA, references to data space are supposed to use dp, |
1774 | register 27, but showing it in the RTL inhibits various cse | |
1775 | and loop optimizations. */ | |
6d36483b | 1776 | else |
87ad11b0 | 1777 | { |
005a7dd0 | 1778 | rtx temp, set; |
2ee034bc | 1779 | |
6d36483b | 1780 | if (reload_in_progress || reload_completed) |
f756078b | 1781 | { |
1782 | temp = scratch_reg ? scratch_reg : operand0; | |
1783 | /* TEMP will hold an address and maybe the actual | |
1784 | data. We want it in WORD_MODE regardless of what mode it | |
1785 | was originally given to us. */ | |
9840d99d | 1786 | temp = force_mode (word_mode, temp); |
f756078b | 1787 | } |
2ee034bc | 1788 | else |
1789 | temp = gen_reg_rtx (mode); | |
1790 | ||
42819d4e | 1791 | /* Loading a SYMBOL_REF into a register makes that register |
9840d99d | 1792 | safe to be used as the base in an indexed address. |
42819d4e | 1793 | |
1794 | Don't mark hard registers though. That loses. */ | |
47a61b79 | 1795 | if (GET_CODE (operand0) == REG |
1796 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
dbd3d89d | 1797 | mark_reg_pointer (operand0, BITS_PER_UNIT); |
42819d4e | 1798 | if (REGNO (temp) >= FIRST_PSEUDO_REGISTER) |
dbd3d89d | 1799 | mark_reg_pointer (temp, BITS_PER_UNIT); |
1800 | ||
2ee034bc | 1801 | if (ishighonly) |
ad851752 | 1802 | set = gen_rtx_SET (mode, operand0, temp); |
2ee034bc | 1803 | else |
7014838c | 1804 | set = gen_rtx_SET (VOIDmode, |
1805 | operand0, | |
ad851752 | 1806 | gen_rtx_LO_SUM (mode, temp, operand1)); |
6d36483b | 1807 | |
ad851752 | 1808 | emit_insn (gen_rtx_SET (VOIDmode, |
1809 | temp, | |
1810 | gen_rtx_HIGH (mode, operand1))); | |
d2498717 | 1811 | emit_insn (set); |
166bf021 | 1812 | |
87ad11b0 | 1813 | } |
2ee034bc | 1814 | return 1; |
87ad11b0 | 1815 | } |
716b2c5a | 1816 | else if (pa_tls_referenced_p (operand1)) |
1817 | { | |
1818 | rtx tmp = operand1; | |
1819 | rtx addend = NULL; | |
1820 | ||
1821 | if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS) | |
1822 | { | |
1823 | addend = XEXP (XEXP (tmp, 0), 1); | |
1824 | tmp = XEXP (XEXP (tmp, 0), 0); | |
1825 | } | |
1826 | ||
1827 | gcc_assert (GET_CODE (tmp) == SYMBOL_REF); | |
1828 | tmp = legitimize_tls_address (tmp); | |
1829 | if (addend) | |
1830 | { | |
1831 | tmp = gen_rtx_PLUS (mode, tmp, addend); | |
1832 | tmp = force_operand (tmp, operands[0]); | |
1833 | } | |
1834 | operands[1] = tmp; | |
1835 | } | |
42faba01 | 1836 | else if (GET_CODE (operand1) != CONST_INT |
6bcdc1fb | 1837 | || !cint_ok_for_move (INTVAL (operand1))) |
87ad11b0 | 1838 | { |
6bcdc1fb | 1839 | rtx insn, temp; |
1840 | rtx op1 = operand1; | |
6edde44b | 1841 | HOST_WIDE_INT value = 0; |
6bcdc1fb | 1842 | HOST_WIDE_INT insv = 0; |
1843 | int insert = 0; | |
1844 | ||
6edde44b | 1845 | if (GET_CODE (operand1) == CONST_INT) |
1846 | value = INTVAL (operand1); | |
1847 | ||
6bcdc1fb | 1848 | if (TARGET_64BIT |
1849 | && GET_CODE (operand1) == CONST_INT | |
b7d86581 | 1850 | && HOST_BITS_PER_WIDE_INT > 32 |
5e3c5739 | 1851 | && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32) |
1852 | { | |
b7d86581 | 1853 | HOST_WIDE_INT nval; |
5e3c5739 | 1854 | |
93f6e1c7 | 1855 | /* Extract the low order 32 bits of the value and sign extend. |
1856 | If the new value is the same as the original value, we can | |
1857 | can use the original value as-is. If the new value is | |
1858 | different, we use it and insert the most-significant 32-bits | |
1859 | of the original value into the final result. */ | |
6bcdc1fb | 1860 | nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1)) |
b7d86581 | 1861 | ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31); |
6bcdc1fb | 1862 | if (value != nval) |
5e3c5739 | 1863 | { |
93f6e1c7 | 1864 | #if HOST_BITS_PER_WIDE_INT > 32 |
6bcdc1fb | 1865 | insv = value >= 0 ? value >> 32 : ~(~value >> 32); |
93f6e1c7 | 1866 | #endif |
6bcdc1fb | 1867 | insert = 1; |
1868 | value = nval; | |
5e3c5739 | 1869 | operand1 = GEN_INT (nval); |
1870 | } | |
1871 | } | |
2ff4bf8d | 1872 | |
1873 | if (reload_in_progress || reload_completed) | |
6bcdc1fb | 1874 | temp = scratch_reg ? scratch_reg : operand0; |
2ff4bf8d | 1875 | else |
1876 | temp = gen_reg_rtx (mode); | |
1877 | ||
7c4d3047 | 1878 | /* We don't directly split DImode constants on 32-bit targets |
1879 | because PLUS uses an 11-bit immediate and the insn sequence | |
1880 | generated is not as efficient as the one using HIGH/LO_SUM. */ | |
1881 | if (GET_CODE (operand1) == CONST_INT | |
6bcdc1fb | 1882 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
1883 | && !insert) | |
93f6e1c7 | 1884 | { |
7c4d3047 | 1885 | /* Directly break constant into high and low parts. This |
93f6e1c7 | 1886 | provides better optimization opportunities because various |
1887 | passes recognize constants split with PLUS but not LO_SUM. | |
1888 | We use a 14-bit signed low part except when the addition | |
1889 | of 0x4000 to the high part might change the sign of the | |
1890 | high part. */ | |
93f6e1c7 | 1891 | HOST_WIDE_INT low = value & 0x3fff; |
1892 | HOST_WIDE_INT high = value & ~ 0x3fff; | |
1893 | ||
1894 | if (low >= 0x2000) | |
1895 | { | |
1896 | if (high == 0x7fffc000 || (mode == HImode && high == 0x4000)) | |
1897 | high += 0x2000; | |
1898 | else | |
1899 | high += 0x4000; | |
1900 | } | |
1901 | ||
1902 | low = value - high; | |
5e3c5739 | 1903 | |
93f6e1c7 | 1904 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high))); |
1905 | operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low)); | |
1906 | } | |
1907 | else | |
5e3c5739 | 1908 | { |
93f6e1c7 | 1909 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
1910 | gen_rtx_HIGH (mode, operand1))); | |
1911 | operands[1] = gen_rtx_LO_SUM (mode, temp, operand1); | |
5e3c5739 | 1912 | } |
9840d99d | 1913 | |
6bcdc1fb | 1914 | insn = emit_move_insn (operands[0], operands[1]); |
1915 | ||
1916 | /* Now insert the most significant 32 bits of the value | |
1917 | into the register. When we don't have a second register | |
1918 | available, it could take up to nine instructions to load | |
1919 | a 64-bit integer constant. Prior to reload, we force | |
1920 | constants that would take more than three instructions | |
1921 | to load to the constant pool. During and after reload, | |
1922 | we have to handle all possible values. */ | |
1923 | if (insert) | |
1924 | { | |
1925 | /* Use a HIGH/LO_SUM/INSV sequence if we have a second | |
1926 | register and the value to be inserted is outside the | |
1927 | range that can be loaded with three depdi instructions. */ | |
1928 | if (temp != operand0 && (insv >= 16384 || insv < -16384)) | |
1929 | { | |
1930 | operand1 = GEN_INT (insv); | |
1931 | ||
1932 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
1933 | gen_rtx_HIGH (mode, operand1))); | |
1934 | emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1)); | |
1935 | emit_insn (gen_insv (operand0, GEN_INT (32), | |
1936 | const0_rtx, temp)); | |
1937 | } | |
1938 | else | |
1939 | { | |
1940 | int len = 5, pos = 27; | |
1941 | ||
1942 | /* Insert the bits using the depdi instruction. */ | |
1943 | while (pos >= 0) | |
1944 | { | |
1945 | HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16; | |
1946 | HOST_WIDE_INT sign = v5 < 0; | |
1947 | ||
1948 | /* Left extend the insertion. */ | |
1949 | insv = (insv >= 0 ? insv >> len : ~(~insv >> len)); | |
1950 | while (pos > 0 && (insv & 1) == sign) | |
1951 | { | |
1952 | insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1)); | |
1953 | len += 1; | |
1954 | pos -= 1; | |
1955 | } | |
1956 | ||
1957 | emit_insn (gen_insv (operand0, GEN_INT (len), | |
1958 | GEN_INT (pos), GEN_INT (v5))); | |
1959 | ||
1960 | len = pos > 0 && pos < 5 ? pos : 5; | |
1961 | pos -= len; | |
1962 | } | |
1963 | } | |
1964 | } | |
93f6e1c7 | 1965 | |
6bcdc1fb | 1966 | REG_NOTES (insn) |
1967 | = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn)); | |
93f6e1c7 | 1968 | |
5e3c5739 | 1969 | return 1; |
87ad11b0 | 1970 | } |
1971 | } | |
1972 | /* Now have insn-emit do whatever it normally does. */ | |
1973 | return 0; | |
1974 | } | |
1975 | ||
1946138e | 1976 | /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning |
bd49d362 | 1977 | it will need a link/runtime reloc). */ |
1946138e | 1978 | |
1979 | int | |
5c1d8983 | 1980 | reloc_needed (tree exp) |
1946138e | 1981 | { |
1982 | int reloc = 0; | |
1983 | ||
1984 | switch (TREE_CODE (exp)) | |
1985 | { | |
1986 | case ADDR_EXPR: | |
1987 | return 1; | |
1988 | ||
1989 | case PLUS_EXPR: | |
1990 | case MINUS_EXPR: | |
1991 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
1992 | reloc |= reloc_needed (TREE_OPERAND (exp, 1)); | |
1993 | break; | |
1994 | ||
1995 | case NOP_EXPR: | |
1996 | case CONVERT_EXPR: | |
1997 | case NON_LVALUE_EXPR: | |
1998 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
1999 | break; | |
2000 | ||
2001 | case CONSTRUCTOR: | |
2002 | { | |
729d4a82 | 2003 | tree value; |
2004 | unsigned HOST_WIDE_INT ix; | |
2005 | ||
2006 | FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value) | |
2007 | if (value) | |
2008 | reloc |= reloc_needed (value); | |
1946138e | 2009 | } |
2010 | break; | |
2011 | ||
2012 | case ERROR_MARK: | |
2013 | break; | |
7d27e4c9 | 2014 | |
2015 | default: | |
2016 | break; | |
1946138e | 2017 | } |
2018 | return reloc; | |
2019 | } | |
2020 | ||
7811991d | 2021 | /* Does operand (which is a symbolic_operand) live in text space? |
2022 | If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info, | |
2023 | will be true. */ | |
87ad11b0 | 2024 | |
2025 | int | |
5c1d8983 | 2026 | read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 2027 | { |
2028 | if (GET_CODE (operand) == CONST) | |
2029 | operand = XEXP (XEXP (operand, 0), 0); | |
b4a7bf10 | 2030 | if (flag_pic) |
2031 | { | |
2032 | if (GET_CODE (operand) == SYMBOL_REF) | |
2033 | return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand); | |
2034 | } | |
2035 | else | |
2036 | { | |
2037 | if (GET_CODE (operand) == SYMBOL_REF) | |
2038 | return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand); | |
2039 | } | |
87ad11b0 | 2040 | return 1; |
2041 | } | |
6d36483b | 2042 | |
87ad11b0 | 2043 | \f |
2044 | /* Return the best assembler insn template | |
5aedf60c | 2045 | for moving operands[1] into operands[0] as a fullword. */ |
611a88e1 | 2046 | const char * |
5c1d8983 | 2047 | singlemove_string (rtx *operands) |
87ad11b0 | 2048 | { |
3745c59b | 2049 | HOST_WIDE_INT intval; |
2050 | ||
87ad11b0 | 2051 | if (GET_CODE (operands[0]) == MEM) |
2052 | return "stw %r1,%0"; | |
3745c59b | 2053 | if (GET_CODE (operands[1]) == MEM) |
87ad11b0 | 2054 | return "ldw %1,%0"; |
3745c59b | 2055 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
9d5108ea | 2056 | { |
3745c59b | 2057 | long i; |
2058 | REAL_VALUE_TYPE d; | |
9d5108ea | 2059 | |
ecf2283d | 2060 | gcc_assert (GET_MODE (operands[1]) == SFmode); |
9d5108ea | 2061 | |
3745c59b | 2062 | /* Translate the CONST_DOUBLE to a CONST_INT with the same target |
2063 | bit pattern. */ | |
2064 | REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]); | |
2065 | REAL_VALUE_TO_TARGET_SINGLE (d, i); | |
9d5108ea | 2066 | |
3745c59b | 2067 | operands[1] = GEN_INT (i); |
2068 | /* Fall through to CONST_INT case. */ | |
2069 | } | |
2070 | if (GET_CODE (operands[1]) == CONST_INT) | |
9d5108ea | 2071 | { |
3745c59b | 2072 | intval = INTVAL (operands[1]); |
2073 | ||
2074 | if (VAL_14_BITS_P (intval)) | |
2075 | return "ldi %1,%0"; | |
2076 | else if ((intval & 0x7ff) == 0) | |
2077 | return "ldil L'%1,%0"; | |
2078 | else if (zdepi_cint_p (intval)) | |
e4065f95 | 2079 | return "{zdepi %Z1,%0|depwi,z %Z1,%0}"; |
9d5108ea | 2080 | else |
2081 | return "ldil L'%1,%0\n\tldo R'%1(%0),%0"; | |
2082 | } | |
87ad11b0 | 2083 | return "copy %1,%0"; |
2084 | } | |
2085 | \f | |
2086 | ||
201f01e9 | 2087 | /* Compute position (in OP[1]) and width (in OP[2]) |
2088 | useful for copying IMM to a register using the zdepi | |
2089 | instructions. Store the immediate value to insert in OP[0]. */ | |
611a88e1 | 2090 | static void |
5c1d8983 | 2091 | compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
7e10ba53 | 2092 | { |
e057641f | 2093 | int lsb, len; |
7e10ba53 | 2094 | |
e057641f | 2095 | /* Find the least significant set bit in IMM. */ |
2096 | for (lsb = 0; lsb < 32; lsb++) | |
7e10ba53 | 2097 | { |
e057641f | 2098 | if ((imm & 1) != 0) |
7e10ba53 | 2099 | break; |
e057641f | 2100 | imm >>= 1; |
7e10ba53 | 2101 | } |
2102 | ||
e057641f | 2103 | /* Choose variants based on *sign* of the 5-bit field. */ |
2104 | if ((imm & 0x10) == 0) | |
2105 | len = (lsb <= 28) ? 4 : 32 - lsb; | |
7e10ba53 | 2106 | else |
2107 | { | |
e057641f | 2108 | /* Find the width of the bitstring in IMM. */ |
2109 | for (len = 5; len < 32; len++) | |
7e10ba53 | 2110 | { |
e057641f | 2111 | if ((imm & (1 << len)) == 0) |
7e10ba53 | 2112 | break; |
7e10ba53 | 2113 | } |
2114 | ||
e057641f | 2115 | /* Sign extend IMM as a 5-bit value. */ |
2116 | imm = (imm & 0xf) - 0x10; | |
7e10ba53 | 2117 | } |
2118 | ||
42faba01 | 2119 | op[0] = imm; |
2120 | op[1] = 31 - lsb; | |
2121 | op[2] = len; | |
7e10ba53 | 2122 | } |
2123 | ||
5e3c5739 | 2124 | /* Compute position (in OP[1]) and width (in OP[2]) |
2125 | useful for copying IMM to a register using the depdi,z | |
2126 | instructions. Store the immediate value to insert in OP[0]. */ | |
2127 | void | |
5c1d8983 | 2128 | compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
5e3c5739 | 2129 | { |
2130 | HOST_WIDE_INT lsb, len; | |
2131 | ||
2132 | /* Find the least significant set bit in IMM. */ | |
2133 | for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++) | |
2134 | { | |
2135 | if ((imm & 1) != 0) | |
2136 | break; | |
2137 | imm >>= 1; | |
2138 | } | |
2139 | ||
2140 | /* Choose variants based on *sign* of the 5-bit field. */ | |
2141 | if ((imm & 0x10) == 0) | |
2142 | len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4) | |
2143 | ? 4 : HOST_BITS_PER_WIDE_INT - lsb); | |
2144 | else | |
2145 | { | |
2146 | /* Find the width of the bitstring in IMM. */ | |
2147 | for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++) | |
2148 | { | |
ea52c577 | 2149 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
5e3c5739 | 2150 | break; |
2151 | } | |
2152 | ||
2153 | /* Sign extend IMM as a 5-bit value. */ | |
2154 | imm = (imm & 0xf) - 0x10; | |
2155 | } | |
2156 | ||
2157 | op[0] = imm; | |
2158 | op[1] = 63 - lsb; | |
2159 | op[2] = len; | |
2160 | } | |
2161 | ||
87ad11b0 | 2162 | /* Output assembler code to perform a doubleword move insn |
2163 | with operands OPERANDS. */ | |
2164 | ||
611a88e1 | 2165 | const char * |
5c1d8983 | 2166 | output_move_double (rtx *operands) |
87ad11b0 | 2167 | { |
2168 | enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1; | |
2169 | rtx latehalf[2]; | |
2170 | rtx addreg0 = 0, addreg1 = 0; | |
2171 | ||
2172 | /* First classify both operands. */ | |
2173 | ||
2174 | if (REG_P (operands[0])) | |
2175 | optype0 = REGOP; | |
2176 | else if (offsettable_memref_p (operands[0])) | |
2177 | optype0 = OFFSOP; | |
2178 | else if (GET_CODE (operands[0]) == MEM) | |
2179 | optype0 = MEMOP; | |
2180 | else | |
2181 | optype0 = RNDOP; | |
2182 | ||
2183 | if (REG_P (operands[1])) | |
2184 | optype1 = REGOP; | |
2185 | else if (CONSTANT_P (operands[1])) | |
2186 | optype1 = CNSTOP; | |
2187 | else if (offsettable_memref_p (operands[1])) | |
2188 | optype1 = OFFSOP; | |
2189 | else if (GET_CODE (operands[1]) == MEM) | |
2190 | optype1 = MEMOP; | |
2191 | else | |
2192 | optype1 = RNDOP; | |
2193 | ||
2194 | /* Check for the cases that the operand constraints are not | |
ecf2283d | 2195 | supposed to allow to happen. */ |
2196 | gcc_assert (optype0 == REGOP || optype1 == REGOP); | |
87ad11b0 | 2197 | |
2198 | /* Handle auto decrementing and incrementing loads and stores | |
2199 | specifically, since the structure of the function doesn't work | |
2200 | for them without major modification. Do it better when we learn | |
2201 | this port about the general inc/dec addressing of PA. | |
2202 | (This was written by tege. Chide him if it doesn't work.) */ | |
2203 | ||
2204 | if (optype0 == MEMOP) | |
2205 | { | |
1df0058a | 2206 | /* We have to output the address syntax ourselves, since print_operand |
2207 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2208 | ||
87ad11b0 | 2209 | rtx addr = XEXP (operands[0], 0); |
1df0058a | 2210 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) |
87ad11b0 | 2211 | { |
ad851752 | 2212 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2213 | |
2214 | operands[0] = XEXP (addr, 0); | |
ecf2283d | 2215 | gcc_assert (GET_CODE (operands[1]) == REG |
2216 | && GET_CODE (operands[0]) == REG); | |
1df0058a | 2217 | |
ecf2283d | 2218 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); |
2219 | ||
2220 | /* No overlap between high target register and address | |
2221 | register. (We do this in a non-obvious way to | |
2222 | save a register file writeback) */ | |
2223 | if (GET_CODE (addr) == POST_INC) | |
2224 | return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)"; | |
2225 | return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)"; | |
a3217f65 | 2226 | } |
1df0058a | 2227 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) |
a3217f65 | 2228 | { |
ad851752 | 2229 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2230 | |
2231 | operands[0] = XEXP (addr, 0); | |
ecf2283d | 2232 | gcc_assert (GET_CODE (operands[1]) == REG |
2233 | && GET_CODE (operands[0]) == REG); | |
2234 | ||
2235 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); | |
2236 | /* No overlap between high target register and address | |
2237 | register. (We do this in a non-obvious way to save a | |
2238 | register file writeback) */ | |
2239 | if (GET_CODE (addr) == PRE_INC) | |
2240 | return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)"; | |
2241 | return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)"; | |
87ad11b0 | 2242 | } |
2243 | } | |
2244 | if (optype1 == MEMOP) | |
2245 | { | |
2246 | /* We have to output the address syntax ourselves, since print_operand | |
2247 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2248 | ||
2249 | rtx addr = XEXP (operands[1], 0); | |
2250 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) | |
2251 | { | |
ad851752 | 2252 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2253 | |
2254 | operands[1] = XEXP (addr, 0); | |
ecf2283d | 2255 | gcc_assert (GET_CODE (operands[0]) == REG |
2256 | && GET_CODE (operands[1]) == REG); | |
87ad11b0 | 2257 | |
2258 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2259 | { | |
2260 | /* No overlap between high target register and address | |
3857fa62 | 2261 | register. (We do this in a non-obvious way to |
87ad11b0 | 2262 | save a register file writeback) */ |
2263 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2264 | return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0"; |
01fd4b49 | 2265 | return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0"; |
87ad11b0 | 2266 | } |
2267 | else | |
2268 | { | |
2269 | /* This is an undefined situation. We should load into the | |
2270 | address register *and* update that register. Probably | |
2271 | we don't need to handle this at all. */ | |
2272 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2273 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0"; |
2274 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0"; | |
87ad11b0 | 2275 | } |
2276 | } | |
2277 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) | |
2278 | { | |
ad851752 | 2279 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2280 | |
2281 | operands[1] = XEXP (addr, 0); | |
ecf2283d | 2282 | gcc_assert (GET_CODE (operands[0]) == REG |
2283 | && GET_CODE (operands[1]) == REG); | |
87ad11b0 | 2284 | |
2285 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2286 | { | |
2287 | /* No overlap between high target register and address | |
3857fa62 | 2288 | register. (We do this in a non-obvious way to |
87ad11b0 | 2289 | save a register file writeback) */ |
2290 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2291 | return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0"; |
2292 | return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0"; | |
87ad11b0 | 2293 | } |
2294 | else | |
2295 | { | |
2296 | /* This is an undefined situation. We should load into the | |
2297 | address register *and* update that register. Probably | |
2298 | we don't need to handle this at all. */ | |
2299 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2300 | return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0"; |
2301 | return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0"; | |
87ad11b0 | 2302 | } |
2303 | } | |
12b02046 | 2304 | else if (GET_CODE (addr) == PLUS |
2305 | && GET_CODE (XEXP (addr, 0)) == MULT) | |
2306 | { | |
ad851752 | 2307 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
12b02046 | 2308 | |
2309 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2310 | { | |
2311 | rtx xoperands[3]; | |
2312 | ||
2313 | xoperands[0] = high_reg; | |
2314 | xoperands[1] = XEXP (addr, 1); | |
2315 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2316 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2317 | output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}", |
2318 | xoperands); | |
34940871 | 2319 | return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; |
12b02046 | 2320 | } |
2321 | else | |
2322 | { | |
2323 | rtx xoperands[3]; | |
2324 | ||
2325 | xoperands[0] = high_reg; | |
2326 | xoperands[1] = XEXP (addr, 1); | |
2327 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2328 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2329 | output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}", |
2330 | xoperands); | |
34940871 | 2331 | return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0"; |
12b02046 | 2332 | } |
12b02046 | 2333 | } |
87ad11b0 | 2334 | } |
2335 | ||
2336 | /* If an operand is an unoffsettable memory ref, find a register | |
2337 | we can increment temporarily to make it refer to the second word. */ | |
2338 | ||
2339 | if (optype0 == MEMOP) | |
2340 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2341 | ||
2342 | if (optype1 == MEMOP) | |
2343 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2344 | ||
2345 | /* Ok, we can do one word at a time. | |
2346 | Normally we do the low-numbered word first. | |
2347 | ||
2348 | In either case, set up in LATEHALF the operands to use | |
2349 | for the high-numbered word and in some cases alter the | |
2350 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2351 | ||
2352 | if (optype0 == REGOP) | |
ad851752 | 2353 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
87ad11b0 | 2354 | else if (optype0 == OFFSOP) |
eafc6604 | 2355 | latehalf[0] = adjust_address (operands[0], SImode, 4); |
87ad11b0 | 2356 | else |
2357 | latehalf[0] = operands[0]; | |
2358 | ||
2359 | if (optype1 == REGOP) | |
ad851752 | 2360 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
87ad11b0 | 2361 | else if (optype1 == OFFSOP) |
eafc6604 | 2362 | latehalf[1] = adjust_address (operands[1], SImode, 4); |
87ad11b0 | 2363 | else if (optype1 == CNSTOP) |
2364 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2365 | else | |
2366 | latehalf[1] = operands[1]; | |
2367 | ||
2368 | /* If the first move would clobber the source of the second one, | |
2369 | do them in the other order. | |
2370 | ||
cf489d53 | 2371 | This can happen in two cases: |
87ad11b0 | 2372 | |
cf489d53 | 2373 | mem -> register where the first half of the destination register |
2374 | is the same register used in the memory's address. Reload | |
2375 | can create such insns. | |
87ad11b0 | 2376 | |
cf489d53 | 2377 | mem in this case will be either register indirect or register |
9840d99d | 2378 | indirect plus a valid offset. |
cf489d53 | 2379 | |
2380 | register -> register move where REGNO(dst) == REGNO(src + 1) | |
9840d99d | 2381 | someone (Tim/Tege?) claimed this can happen for parameter loads. |
cf489d53 | 2382 | |
2383 | Handle mem -> register case first. */ | |
2384 | if (optype0 == REGOP | |
2385 | && (optype1 == MEMOP || optype1 == OFFSOP) | |
2386 | && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2387 | operands[1], 0)) | |
87ad11b0 | 2388 | { |
87ad11b0 | 2389 | /* Do the late half first. */ |
2390 | if (addreg1) | |
6a5d085a | 2391 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2392 | output_asm_insn (singlemove_string (latehalf), latehalf); |
cf489d53 | 2393 | |
2394 | /* Then clobber. */ | |
87ad11b0 | 2395 | if (addreg1) |
6a5d085a | 2396 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2397 | return singlemove_string (operands); |
2398 | } | |
2399 | ||
cf489d53 | 2400 | /* Now handle register -> register case. */ |
c4fa5937 | 2401 | if (optype0 == REGOP && optype1 == REGOP |
2402 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
2403 | { | |
2404 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2405 | return singlemove_string (operands); | |
2406 | } | |
2407 | ||
87ad11b0 | 2408 | /* Normal case: do the two words, low-numbered first. */ |
2409 | ||
2410 | output_asm_insn (singlemove_string (operands), operands); | |
2411 | ||
2412 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2413 | if (addreg0) | |
6a5d085a | 2414 | output_asm_insn ("ldo 4(%0),%0", &addreg0); |
87ad11b0 | 2415 | if (addreg1) |
6a5d085a | 2416 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2417 | |
2418 | /* Do that word. */ | |
2419 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2420 | ||
2421 | /* Undo the adds we just did. */ | |
2422 | if (addreg0) | |
6a5d085a | 2423 | output_asm_insn ("ldo -4(%0),%0", &addreg0); |
87ad11b0 | 2424 | if (addreg1) |
6a5d085a | 2425 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2426 | |
2427 | return ""; | |
2428 | } | |
2429 | \f | |
611a88e1 | 2430 | const char * |
5c1d8983 | 2431 | output_fp_move_double (rtx *operands) |
87ad11b0 | 2432 | { |
2433 | if (FP_REG_P (operands[0])) | |
2434 | { | |
6d36483b | 2435 | if (FP_REG_P (operands[1]) |
891b55b4 | 2436 | || operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
c6ae275c | 2437 | output_asm_insn ("fcpy,dbl %f1,%0", operands); |
6d36483b | 2438 | else |
27ef382d | 2439 | output_asm_insn ("fldd%F1 %1,%0", operands); |
87ad11b0 | 2440 | } |
2441 | else if (FP_REG_P (operands[1])) | |
2442 | { | |
27ef382d | 2443 | output_asm_insn ("fstd%F0 %1,%0", operands); |
87ad11b0 | 2444 | } |
ecf2283d | 2445 | else |
891b55b4 | 2446 | { |
ecf2283d | 2447 | rtx xoperands[2]; |
2448 | ||
2449 | gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0]))); | |
2450 | ||
6d36483b | 2451 | /* This is a pain. You have to be prepared to deal with an |
01cc3b75 | 2452 | arbitrary address here including pre/post increment/decrement. |
891b55b4 | 2453 | |
2454 | so avoid this in the MD. */ | |
ecf2283d | 2455 | gcc_assert (GET_CODE (operands[0]) == REG); |
2456 | ||
2457 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2458 | xoperands[0] = operands[0]; | |
2459 | output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands); | |
891b55b4 | 2460 | } |
87ad11b0 | 2461 | return ""; |
2462 | } | |
2463 | \f | |
2464 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2465 | ADDR can be effectively incremented by incrementing REG. */ | |
2466 | ||
2467 | static rtx | |
5c1d8983 | 2468 | find_addr_reg (rtx addr) |
87ad11b0 | 2469 | { |
2470 | while (GET_CODE (addr) == PLUS) | |
2471 | { | |
2472 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2473 | addr = XEXP (addr, 0); | |
2474 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2475 | addr = XEXP (addr, 1); | |
2476 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2477 | addr = XEXP (addr, 1); | |
2478 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2479 | addr = XEXP (addr, 0); | |
2480 | else | |
ecf2283d | 2481 | gcc_unreachable (); |
87ad11b0 | 2482 | } |
ecf2283d | 2483 | gcc_assert (GET_CODE (addr) == REG); |
2484 | return addr; | |
87ad11b0 | 2485 | } |
2486 | ||
87ad11b0 | 2487 | /* Emit code to perform a block move. |
2488 | ||
87ad11b0 | 2489 | OPERANDS[0] is the destination pointer as a REG, clobbered. |
2490 | OPERANDS[1] is the source pointer as a REG, clobbered. | |
42819d4e | 2491 | OPERANDS[2] is a register for temporary storage. |
87ad11b0 | 2492 | OPERANDS[3] is a register for temporary storage. |
a7e1bb24 | 2493 | OPERANDS[4] is the size as a CONST_INT |
9840d99d | 2494 | OPERANDS[5] is the alignment safe to use, as a CONST_INT. |
5aedf60c | 2495 | OPERANDS[6] is another temporary register. */ |
87ad11b0 | 2496 | |
611a88e1 | 2497 | const char * |
5c1d8983 | 2498 | output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) |
87ad11b0 | 2499 | { |
2500 | int align = INTVAL (operands[5]); | |
42819d4e | 2501 | unsigned long n_bytes = INTVAL (operands[4]); |
87ad11b0 | 2502 | |
a7e1bb24 | 2503 | /* We can't move more than a word at a time because the PA |
87ad11b0 | 2504 | has no longer integer move insns. (Could use fp mem ops?) */ |
a7e1bb24 | 2505 | if (align > (TARGET_64BIT ? 8 : 4)) |
2506 | align = (TARGET_64BIT ? 8 : 4); | |
87ad11b0 | 2507 | |
42819d4e | 2508 | /* Note that we know each loop below will execute at least twice |
2509 | (else we would have open-coded the copy). */ | |
2510 | switch (align) | |
87ad11b0 | 2511 | { |
a7e1bb24 | 2512 | case 8: |
2513 | /* Pre-adjust the loop counter. */ | |
2514 | operands[4] = GEN_INT (n_bytes - 16); | |
2515 | output_asm_insn ("ldi %4,%2", operands); | |
2516 | ||
2517 | /* Copying loop. */ | |
2518 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2519 | output_asm_insn ("ldd,ma 8(%1),%6", operands); | |
2520 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2521 | output_asm_insn ("addib,>= -16,%2,.-12", operands); | |
2522 | output_asm_insn ("std,ma %6,8(%0)", operands); | |
2523 | ||
2524 | /* Handle the residual. There could be up to 7 bytes of | |
2525 | residual to copy! */ | |
2526 | if (n_bytes % 16 != 0) | |
2527 | { | |
2528 | operands[4] = GEN_INT (n_bytes % 8); | |
2529 | if (n_bytes % 16 >= 8) | |
2530 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2531 | if (n_bytes % 8 != 0) | |
2532 | output_asm_insn ("ldd 0(%1),%6", operands); | |
2533 | if (n_bytes % 16 >= 8) | |
2534 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2535 | if (n_bytes % 8 != 0) | |
2536 | output_asm_insn ("stdby,e %6,%4(%0)", operands); | |
2537 | } | |
2538 | return ""; | |
2539 | ||
42819d4e | 2540 | case 4: |
2541 | /* Pre-adjust the loop counter. */ | |
2542 | operands[4] = GEN_INT (n_bytes - 8); | |
2543 | output_asm_insn ("ldi %4,%2", operands); | |
2544 | ||
2545 | /* Copying loop. */ | |
e4065f95 | 2546 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
2547 | output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands); | |
2548 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); | |
42819d4e | 2549 | output_asm_insn ("addib,>= -8,%2,.-12", operands); |
e4065f95 | 2550 | output_asm_insn ("{stws|stw},ma %6,4(%0)", operands); |
42819d4e | 2551 | |
2552 | /* Handle the residual. There could be up to 7 bytes of | |
2553 | residual to copy! */ | |
2554 | if (n_bytes % 8 != 0) | |
2555 | { | |
2556 | operands[4] = GEN_INT (n_bytes % 4); | |
2557 | if (n_bytes % 8 >= 4) | |
e4065f95 | 2558 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
42819d4e | 2559 | if (n_bytes % 4 != 0) |
34940871 | 2560 | output_asm_insn ("ldw 0(%1),%6", operands); |
42819d4e | 2561 | if (n_bytes % 8 >= 4) |
e4065f95 | 2562 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); |
42819d4e | 2563 | if (n_bytes % 4 != 0) |
e4065f95 | 2564 | output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands); |
42819d4e | 2565 | } |
2566 | return ""; | |
87ad11b0 | 2567 | |
42819d4e | 2568 | case 2: |
2569 | /* Pre-adjust the loop counter. */ | |
2570 | operands[4] = GEN_INT (n_bytes - 4); | |
2571 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2572 | |
42819d4e | 2573 | /* Copying loop. */ |
e4065f95 | 2574 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
2575 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands); | |
2576 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); | |
42819d4e | 2577 | output_asm_insn ("addib,>= -4,%2,.-12", operands); |
e4065f95 | 2578 | output_asm_insn ("{sths|sth},ma %6,2(%0)", operands); |
87ad11b0 | 2579 | |
42819d4e | 2580 | /* Handle the residual. */ |
2581 | if (n_bytes % 4 != 0) | |
2582 | { | |
2583 | if (n_bytes % 4 >= 2) | |
e4065f95 | 2584 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
42819d4e | 2585 | if (n_bytes % 2 != 0) |
34940871 | 2586 | output_asm_insn ("ldb 0(%1),%6", operands); |
42819d4e | 2587 | if (n_bytes % 4 >= 2) |
e4065f95 | 2588 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); |
42819d4e | 2589 | if (n_bytes % 2 != 0) |
34940871 | 2590 | output_asm_insn ("stb %6,0(%0)", operands); |
42819d4e | 2591 | } |
2592 | return ""; | |
87ad11b0 | 2593 | |
42819d4e | 2594 | case 1: |
2595 | /* Pre-adjust the loop counter. */ | |
2596 | operands[4] = GEN_INT (n_bytes - 2); | |
2597 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2598 | |
42819d4e | 2599 | /* Copying loop. */ |
e4065f95 | 2600 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands); |
2601 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands); | |
2602 | output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands); | |
42819d4e | 2603 | output_asm_insn ("addib,>= -2,%2,.-12", operands); |
e4065f95 | 2604 | output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands); |
87ad11b0 | 2605 | |
42819d4e | 2606 | /* Handle the residual. */ |
2607 | if (n_bytes % 2 != 0) | |
2608 | { | |
34940871 | 2609 | output_asm_insn ("ldb 0(%1),%3", operands); |
2610 | output_asm_insn ("stb %3,0(%0)", operands); | |
42819d4e | 2611 | } |
2612 | return ""; | |
87ad11b0 | 2613 | |
42819d4e | 2614 | default: |
ecf2283d | 2615 | gcc_unreachable (); |
87ad11b0 | 2616 | } |
87ad11b0 | 2617 | } |
58e17b0b | 2618 | |
2619 | /* Count the number of insns necessary to handle this block move. | |
2620 | ||
2621 | Basic structure is the same as emit_block_move, except that we | |
2622 | count insns rather than emit them. */ | |
2623 | ||
611a88e1 | 2624 | static int |
008c057d | 2625 | compute_movmem_length (rtx insn) |
58e17b0b | 2626 | { |
2627 | rtx pat = PATTERN (insn); | |
fc1fb057 | 2628 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0)); |
2629 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0)); | |
42819d4e | 2630 | unsigned int n_insns = 0; |
58e17b0b | 2631 | |
2632 | /* We can't move more than four bytes at a time because the PA | |
2633 | has no longer integer move insns. (Could use fp mem ops?) */ | |
a7e1bb24 | 2634 | if (align > (TARGET_64BIT ? 8 : 4)) |
2635 | align = (TARGET_64BIT ? 8 : 4); | |
58e17b0b | 2636 | |
79bfe6ae | 2637 | /* The basic copying loop. */ |
42819d4e | 2638 | n_insns = 6; |
58e17b0b | 2639 | |
42819d4e | 2640 | /* Residuals. */ |
2641 | if (n_bytes % (2 * align) != 0) | |
58e17b0b | 2642 | { |
79bfe6ae | 2643 | if ((n_bytes % (2 * align)) >= align) |
2644 | n_insns += 2; | |
2645 | ||
2646 | if ((n_bytes % align) != 0) | |
2647 | n_insns += 2; | |
58e17b0b | 2648 | } |
42819d4e | 2649 | |
2650 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2651 | return n_insns * 4; | |
58e17b0b | 2652 | } |
a7e1bb24 | 2653 | |
2654 | /* Emit code to perform a block clear. | |
2655 | ||
2656 | OPERANDS[0] is the destination pointer as a REG, clobbered. | |
2657 | OPERANDS[1] is a register for temporary storage. | |
2658 | OPERANDS[2] is the size as a CONST_INT | |
2659 | OPERANDS[3] is the alignment safe to use, as a CONST_INT. */ | |
2660 | ||
2661 | const char * | |
2662 | output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) | |
2663 | { | |
2664 | int align = INTVAL (operands[3]); | |
2665 | unsigned long n_bytes = INTVAL (operands[2]); | |
2666 | ||
2667 | /* We can't clear more than a word at a time because the PA | |
2668 | has no longer integer move insns. */ | |
2669 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2670 | align = (TARGET_64BIT ? 8 : 4); | |
2671 | ||
2672 | /* Note that we know each loop below will execute at least twice | |
2673 | (else we would have open-coded the copy). */ | |
2674 | switch (align) | |
2675 | { | |
2676 | case 8: | |
2677 | /* Pre-adjust the loop counter. */ | |
2678 | operands[2] = GEN_INT (n_bytes - 16); | |
2679 | output_asm_insn ("ldi %2,%1", operands); | |
2680 | ||
2681 | /* Loop. */ | |
2682 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2683 | output_asm_insn ("addib,>= -16,%1,.-4", operands); | |
2684 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2685 | ||
2686 | /* Handle the residual. There could be up to 7 bytes of | |
2687 | residual to copy! */ | |
2688 | if (n_bytes % 16 != 0) | |
2689 | { | |
2690 | operands[2] = GEN_INT (n_bytes % 8); | |
2691 | if (n_bytes % 16 >= 8) | |
2692 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2693 | if (n_bytes % 8 != 0) | |
2694 | output_asm_insn ("stdby,e %%r0,%2(%0)", operands); | |
2695 | } | |
2696 | return ""; | |
2697 | ||
2698 | case 4: | |
2699 | /* Pre-adjust the loop counter. */ | |
2700 | operands[2] = GEN_INT (n_bytes - 8); | |
2701 | output_asm_insn ("ldi %2,%1", operands); | |
2702 | ||
2703 | /* Loop. */ | |
2704 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2705 | output_asm_insn ("addib,>= -8,%1,.-4", operands); | |
2706 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2707 | ||
2708 | /* Handle the residual. There could be up to 7 bytes of | |
2709 | residual to copy! */ | |
2710 | if (n_bytes % 8 != 0) | |
2711 | { | |
2712 | operands[2] = GEN_INT (n_bytes % 4); | |
2713 | if (n_bytes % 8 >= 4) | |
2714 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2715 | if (n_bytes % 4 != 0) | |
2716 | output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands); | |
2717 | } | |
2718 | return ""; | |
2719 | ||
2720 | case 2: | |
2721 | /* Pre-adjust the loop counter. */ | |
2722 | operands[2] = GEN_INT (n_bytes - 4); | |
2723 | output_asm_insn ("ldi %2,%1", operands); | |
2724 | ||
2725 | /* Loop. */ | |
2726 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2727 | output_asm_insn ("addib,>= -4,%1,.-4", operands); | |
2728 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2729 | ||
2730 | /* Handle the residual. */ | |
2731 | if (n_bytes % 4 != 0) | |
2732 | { | |
2733 | if (n_bytes % 4 >= 2) | |
2734 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2735 | if (n_bytes % 2 != 0) | |
2736 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2737 | } | |
2738 | return ""; | |
2739 | ||
2740 | case 1: | |
2741 | /* Pre-adjust the loop counter. */ | |
2742 | operands[2] = GEN_INT (n_bytes - 2); | |
2743 | output_asm_insn ("ldi %2,%1", operands); | |
2744 | ||
2745 | /* Loop. */ | |
2746 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2747 | output_asm_insn ("addib,>= -2,%1,.-4", operands); | |
2748 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2749 | ||
2750 | /* Handle the residual. */ | |
2751 | if (n_bytes % 2 != 0) | |
2752 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2753 | ||
2754 | return ""; | |
2755 | ||
2756 | default: | |
ecf2283d | 2757 | gcc_unreachable (); |
a7e1bb24 | 2758 | } |
2759 | } | |
2760 | ||
2761 | /* Count the number of insns necessary to handle this block move. | |
2762 | ||
2763 | Basic structure is the same as emit_block_move, except that we | |
2764 | count insns rather than emit them. */ | |
2765 | ||
2766 | static int | |
008c057d | 2767 | compute_clrmem_length (rtx insn) |
a7e1bb24 | 2768 | { |
2769 | rtx pat = PATTERN (insn); | |
2770 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0)); | |
2771 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0)); | |
2772 | unsigned int n_insns = 0; | |
2773 | ||
2774 | /* We can't clear more than a word at a time because the PA | |
2775 | has no longer integer move insns. */ | |
2776 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2777 | align = (TARGET_64BIT ? 8 : 4); | |
2778 | ||
2779 | /* The basic loop. */ | |
2780 | n_insns = 4; | |
2781 | ||
2782 | /* Residuals. */ | |
2783 | if (n_bytes % (2 * align) != 0) | |
2784 | { | |
2785 | if ((n_bytes % (2 * align)) >= align) | |
2786 | n_insns++; | |
2787 | ||
2788 | if ((n_bytes % align) != 0) | |
2789 | n_insns++; | |
2790 | } | |
2791 | ||
2792 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2793 | return n_insns * 4; | |
2794 | } | |
87ad11b0 | 2795 | \f |
2796 | ||
611a88e1 | 2797 | const char * |
5c1d8983 | 2798 | output_and (rtx *operands) |
e057641f | 2799 | { |
d6f01525 | 2800 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) |
e057641f | 2801 | { |
3745c59b | 2802 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
e057641f | 2803 | int ls0, ls1, ms0, p, len; |
2804 | ||
2805 | for (ls0 = 0; ls0 < 32; ls0++) | |
2806 | if ((mask & (1 << ls0)) == 0) | |
2807 | break; | |
2808 | ||
2809 | for (ls1 = ls0; ls1 < 32; ls1++) | |
2810 | if ((mask & (1 << ls1)) != 0) | |
2811 | break; | |
2812 | ||
2813 | for (ms0 = ls1; ms0 < 32; ms0++) | |
2814 | if ((mask & (1 << ms0)) == 0) | |
2815 | break; | |
2816 | ||
ecf2283d | 2817 | gcc_assert (ms0 == 32); |
e057641f | 2818 | |
2819 | if (ls1 == 32) | |
2820 | { | |
2821 | len = ls0; | |
2822 | ||
ecf2283d | 2823 | gcc_assert (len); |
e057641f | 2824 | |
ef618fe4 | 2825 | operands[2] = GEN_INT (len); |
e4065f95 | 2826 | return "{extru|extrw,u} %1,31,%2,%0"; |
e057641f | 2827 | } |
2828 | else | |
2829 | { | |
2830 | /* We could use this `depi' for the case above as well, but `depi' | |
2831 | requires one more register file access than an `extru'. */ | |
2832 | ||
2833 | p = 31 - ls0; | |
2834 | len = ls1 - ls0; | |
2835 | ||
ef618fe4 | 2836 | operands[2] = GEN_INT (p); |
2837 | operands[3] = GEN_INT (len); | |
e4065f95 | 2838 | return "{depi|depwi} 0,%2,%3,%0"; |
e057641f | 2839 | } |
2840 | } | |
2841 | else | |
2842 | return "and %1,%2,%0"; | |
2843 | } | |
2844 | ||
5e3c5739 | 2845 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] |
2846 | storing the result in operands[0]. */ | |
9aadea62 | 2847 | const char * |
5c1d8983 | 2848 | output_64bit_and (rtx *operands) |
5e3c5739 | 2849 | { |
2850 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) | |
2851 | { | |
2852 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 2853 | int ls0, ls1, ms0, p, len; |
5e3c5739 | 2854 | |
2855 | for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++) | |
b7d86581 | 2856 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0) |
5e3c5739 | 2857 | break; |
2858 | ||
2859 | for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++) | |
b7d86581 | 2860 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0) |
5e3c5739 | 2861 | break; |
2862 | ||
2863 | for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++) | |
b7d86581 | 2864 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0) |
5e3c5739 | 2865 | break; |
2866 | ||
ecf2283d | 2867 | gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT); |
5e3c5739 | 2868 | |
2869 | if (ls1 == HOST_BITS_PER_WIDE_INT) | |
2870 | { | |
2871 | len = ls0; | |
2872 | ||
ecf2283d | 2873 | gcc_assert (len); |
5e3c5739 | 2874 | |
2875 | operands[2] = GEN_INT (len); | |
2876 | return "extrd,u %1,63,%2,%0"; | |
2877 | } | |
2878 | else | |
2879 | { | |
2880 | /* We could use this `depi' for the case above as well, but `depi' | |
2881 | requires one more register file access than an `extru'. */ | |
2882 | ||
2883 | p = 63 - ls0; | |
2884 | len = ls1 - ls0; | |
2885 | ||
2886 | operands[2] = GEN_INT (p); | |
2887 | operands[3] = GEN_INT (len); | |
2888 | return "depdi 0,%2,%3,%0"; | |
2889 | } | |
2890 | } | |
2891 | else | |
2892 | return "and %1,%2,%0"; | |
2893 | } | |
2894 | ||
611a88e1 | 2895 | const char * |
5c1d8983 | 2896 | output_ior (rtx *operands) |
e057641f | 2897 | { |
3745c59b | 2898 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
57ed30e5 | 2899 | int bs0, bs1, p, len; |
6d36483b | 2900 | |
c9da5f4d | 2901 | if (INTVAL (operands[2]) == 0) |
2902 | return "copy %1,%0"; | |
e057641f | 2903 | |
c9da5f4d | 2904 | for (bs0 = 0; bs0 < 32; bs0++) |
2905 | if ((mask & (1 << bs0)) != 0) | |
2906 | break; | |
e057641f | 2907 | |
c9da5f4d | 2908 | for (bs1 = bs0; bs1 < 32; bs1++) |
2909 | if ((mask & (1 << bs1)) == 0) | |
2910 | break; | |
e057641f | 2911 | |
ecf2283d | 2912 | gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); |
e057641f | 2913 | |
c9da5f4d | 2914 | p = 31 - bs0; |
2915 | len = bs1 - bs0; | |
e057641f | 2916 | |
ef618fe4 | 2917 | operands[2] = GEN_INT (p); |
2918 | operands[3] = GEN_INT (len); | |
e4065f95 | 2919 | return "{depi|depwi} -1,%2,%3,%0"; |
e057641f | 2920 | } |
5e3c5739 | 2921 | |
2922 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] | |
2923 | storing the result in operands[0]. */ | |
9aadea62 | 2924 | const char * |
5c1d8983 | 2925 | output_64bit_ior (rtx *operands) |
5e3c5739 | 2926 | { |
2927 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 2928 | int bs0, bs1, p, len; |
5e3c5739 | 2929 | |
2930 | if (INTVAL (operands[2]) == 0) | |
2931 | return "copy %1,%0"; | |
2932 | ||
2933 | for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++) | |
b7d86581 | 2934 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0) |
5e3c5739 | 2935 | break; |
2936 | ||
2937 | for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++) | |
b7d86581 | 2938 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0) |
5e3c5739 | 2939 | break; |
2940 | ||
ecf2283d | 2941 | gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT |
2942 | || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); | |
5e3c5739 | 2943 | |
2944 | p = 63 - bs0; | |
2945 | len = bs1 - bs0; | |
2946 | ||
2947 | operands[2] = GEN_INT (p); | |
2948 | operands[3] = GEN_INT (len); | |
2949 | return "depdi -1,%2,%3,%0"; | |
2950 | } | |
e057641f | 2951 | \f |
58356836 | 2952 | /* Target hook for assembling integer objects. This code handles |
e678758c | 2953 | aligned SI and DI integers specially since function references |
2954 | must be preceded by P%. */ | |
58356836 | 2955 | |
2956 | static bool | |
5c1d8983 | 2957 | pa_assemble_integer (rtx x, unsigned int size, int aligned_p) |
58356836 | 2958 | { |
e678758c | 2959 | if (size == UNITS_PER_WORD |
2960 | && aligned_p | |
58356836 | 2961 | && function_label_operand (x, VOIDmode)) |
2962 | { | |
2963 | fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file); | |
2964 | output_addr_const (asm_out_file, x); | |
2965 | fputc ('\n', asm_out_file); | |
2966 | return true; | |
2967 | } | |
2968 | return default_assemble_integer (x, size, aligned_p); | |
2969 | } | |
2970 | \f | |
87ad11b0 | 2971 | /* Output an ascii string. */ |
57ed30e5 | 2972 | void |
5c1d8983 | 2973 | output_ascii (FILE *file, const char *p, int size) |
87ad11b0 | 2974 | { |
2975 | int i; | |
2976 | int chars_output; | |
5aedf60c | 2977 | unsigned char partial_output[16]; /* Max space 4 chars can occupy. */ |
87ad11b0 | 2978 | |
2979 | /* The HP assembler can only take strings of 256 characters at one | |
2980 | time. This is a limitation on input line length, *not* the | |
2981 | length of the string. Sigh. Even worse, it seems that the | |
2982 | restriction is in number of input characters (see \xnn & | |
2983 | \whatever). So we have to do this very carefully. */ | |
2984 | ||
9c0ac0fd | 2985 | fputs ("\t.STRING \"", file); |
87ad11b0 | 2986 | |
2987 | chars_output = 0; | |
2988 | for (i = 0; i < size; i += 4) | |
2989 | { | |
2990 | int co = 0; | |
2991 | int io = 0; | |
2992 | for (io = 0, co = 0; io < MIN (4, size - i); io++) | |
2993 | { | |
bf8aac3e | 2994 | register unsigned int c = (unsigned char) p[i + io]; |
87ad11b0 | 2995 | |
2996 | if (c == '\"' || c == '\\') | |
2997 | partial_output[co++] = '\\'; | |
2998 | if (c >= ' ' && c < 0177) | |
2999 | partial_output[co++] = c; | |
3000 | else | |
3001 | { | |
3002 | unsigned int hexd; | |
3003 | partial_output[co++] = '\\'; | |
3004 | partial_output[co++] = 'x'; | |
3005 | hexd = c / 16 - 0 + '0'; | |
3006 | if (hexd > '9') | |
3007 | hexd -= '9' - 'a' + 1; | |
3008 | partial_output[co++] = hexd; | |
3009 | hexd = c % 16 - 0 + '0'; | |
3010 | if (hexd > '9') | |
3011 | hexd -= '9' - 'a' + 1; | |
3012 | partial_output[co++] = hexd; | |
3013 | } | |
3014 | } | |
3015 | if (chars_output + co > 243) | |
3016 | { | |
9c0ac0fd | 3017 | fputs ("\"\n\t.STRING \"", file); |
87ad11b0 | 3018 | chars_output = 0; |
3019 | } | |
a584fe8a | 3020 | fwrite (partial_output, 1, (size_t) co, file); |
87ad11b0 | 3021 | chars_output += co; |
3022 | co = 0; | |
3023 | } | |
9c0ac0fd | 3024 | fputs ("\"\n", file); |
87ad11b0 | 3025 | } |
c533da59 | 3026 | |
3027 | /* Try to rewrite floating point comparisons & branches to avoid | |
3028 | useless add,tr insns. | |
3029 | ||
3030 | CHECK_NOTES is nonzero if we should examine REG_DEAD notes | |
3031 | to see if FPCC is dead. CHECK_NOTES is nonzero for the | |
3032 | first attempt to remove useless add,tr insns. It is zero | |
3033 | for the second pass as reorg sometimes leaves bogus REG_DEAD | |
3034 | notes lying around. | |
3035 | ||
3036 | When CHECK_NOTES is zero we can only eliminate add,tr insns | |
3037 | when there's a 1:1 correspondence between fcmp and ftest/fbranch | |
3038 | instructions. */ | |
611a88e1 | 3039 | static void |
5c1d8983 | 3040 | remove_useless_addtr_insns (int check_notes) |
c533da59 | 3041 | { |
3042 | rtx insn; | |
c533da59 | 3043 | static int pass = 0; |
3044 | ||
3045 | /* This is fairly cheap, so always run it when optimizing. */ | |
3046 | if (optimize > 0) | |
3047 | { | |
3048 | int fcmp_count = 0; | |
3049 | int fbranch_count = 0; | |
3050 | ||
3051 | /* Walk all the insns in this function looking for fcmp & fbranch | |
3052 | instructions. Keep track of how many of each we find. */ | |
2efea8c0 | 3053 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3054 | { |
3055 | rtx tmp; | |
3056 | ||
3057 | /* Ignore anything that isn't an INSN or a JUMP_INSN. */ | |
3058 | if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
3059 | continue; | |
3060 | ||
3061 | tmp = PATTERN (insn); | |
3062 | ||
3063 | /* It must be a set. */ | |
3064 | if (GET_CODE (tmp) != SET) | |
3065 | continue; | |
3066 | ||
3067 | /* If the destination is CCFP, then we've found an fcmp insn. */ | |
3068 | tmp = SET_DEST (tmp); | |
3069 | if (GET_CODE (tmp) == REG && REGNO (tmp) == 0) | |
3070 | { | |
3071 | fcmp_count++; | |
3072 | continue; | |
3073 | } | |
9840d99d | 3074 | |
c533da59 | 3075 | tmp = PATTERN (insn); |
3076 | /* If this is an fbranch instruction, bump the fbranch counter. */ | |
3077 | if (GET_CODE (tmp) == SET | |
3078 | && SET_DEST (tmp) == pc_rtx | |
3079 | && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE | |
3080 | && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE | |
3081 | && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG | |
3082 | && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0) | |
3083 | { | |
3084 | fbranch_count++; | |
3085 | continue; | |
3086 | } | |
3087 | } | |
3088 | ||
3089 | ||
3090 | /* Find all floating point compare + branch insns. If possible, | |
3091 | reverse the comparison & the branch to avoid add,tr insns. */ | |
2efea8c0 | 3092 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3093 | { |
3094 | rtx tmp, next; | |
3095 | ||
3096 | /* Ignore anything that isn't an INSN. */ | |
3097 | if (GET_CODE (insn) != INSN) | |
3098 | continue; | |
3099 | ||
3100 | tmp = PATTERN (insn); | |
3101 | ||
3102 | /* It must be a set. */ | |
3103 | if (GET_CODE (tmp) != SET) | |
3104 | continue; | |
3105 | ||
3106 | /* The destination must be CCFP, which is register zero. */ | |
3107 | tmp = SET_DEST (tmp); | |
3108 | if (GET_CODE (tmp) != REG || REGNO (tmp) != 0) | |
3109 | continue; | |
3110 | ||
3111 | /* INSN should be a set of CCFP. | |
3112 | ||
3113 | See if the result of this insn is used in a reversed FP | |
3114 | conditional branch. If so, reverse our condition and | |
3115 | the branch. Doing so avoids useless add,tr insns. */ | |
3116 | next = next_insn (insn); | |
3117 | while (next) | |
3118 | { | |
3119 | /* Jumps, calls and labels stop our search. */ | |
3120 | if (GET_CODE (next) == JUMP_INSN | |
3121 | || GET_CODE (next) == CALL_INSN | |
3122 | || GET_CODE (next) == CODE_LABEL) | |
3123 | break; | |
3124 | ||
3125 | /* As does another fcmp insn. */ | |
3126 | if (GET_CODE (next) == INSN | |
3127 | && GET_CODE (PATTERN (next)) == SET | |
3128 | && GET_CODE (SET_DEST (PATTERN (next))) == REG | |
3129 | && REGNO (SET_DEST (PATTERN (next))) == 0) | |
3130 | break; | |
3131 | ||
3132 | next = next_insn (next); | |
3133 | } | |
3134 | ||
3135 | /* Is NEXT_INSN a branch? */ | |
3136 | if (next | |
3137 | && GET_CODE (next) == JUMP_INSN) | |
3138 | { | |
3139 | rtx pattern = PATTERN (next); | |
3140 | ||
a361b456 | 3141 | /* If it a reversed fp conditional branch (e.g. uses add,tr) |
c533da59 | 3142 | and CCFP dies, then reverse our conditional and the branch |
3143 | to avoid the add,tr. */ | |
3144 | if (GET_CODE (pattern) == SET | |
3145 | && SET_DEST (pattern) == pc_rtx | |
3146 | && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE | |
3147 | && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE | |
3148 | && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG | |
3149 | && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0 | |
3150 | && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC | |
3151 | && (fcmp_count == fbranch_count | |
3152 | || (check_notes | |
3153 | && find_regno_note (next, REG_DEAD, 0)))) | |
3154 | { | |
3155 | /* Reverse the branch. */ | |
3156 | tmp = XEXP (SET_SRC (pattern), 1); | |
3157 | XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2); | |
3158 | XEXP (SET_SRC (pattern), 2) = tmp; | |
3159 | INSN_CODE (next) = -1; | |
3160 | ||
3161 | /* Reverse our condition. */ | |
3162 | tmp = PATTERN (insn); | |
3163 | PUT_CODE (XEXP (tmp, 1), | |
ea52c577 | 3164 | (reverse_condition_maybe_unordered |
3165 | (GET_CODE (XEXP (tmp, 1))))); | |
c533da59 | 3166 | } |
3167 | } | |
3168 | } | |
3169 | } | |
3170 | ||
3171 | pass = !pass; | |
3172 | ||
3173 | } | |
87ad11b0 | 3174 | \f |
ea52c577 | 3175 | /* You may have trouble believing this, but this is the 32 bit HP-PA |
3176 | stack layout. Wow. | |
87ad11b0 | 3177 | |
3178 | Offset Contents | |
3179 | ||
3180 | Variable arguments (optional; any number may be allocated) | |
3181 | ||
3182 | SP-(4*(N+9)) arg word N | |
3183 | : : | |
3184 | SP-56 arg word 5 | |
3185 | SP-52 arg word 4 | |
3186 | ||
3187 | Fixed arguments (must be allocated; may remain unused) | |
3188 | ||
3189 | SP-48 arg word 3 | |
3190 | SP-44 arg word 2 | |
3191 | SP-40 arg word 1 | |
3192 | SP-36 arg word 0 | |
3193 | ||
3194 | Frame Marker | |
3195 | ||
3196 | SP-32 External Data Pointer (DP) | |
3197 | SP-28 External sr4 | |
3198 | SP-24 External/stub RP (RP') | |
3199 | SP-20 Current RP | |
3200 | SP-16 Static Link | |
3201 | SP-12 Clean up | |
3202 | SP-8 Calling Stub RP (RP'') | |
3203 | SP-4 Previous SP | |
3204 | ||
3205 | Top of Frame | |
3206 | ||
3207 | SP-0 Stack Pointer (points to next available address) | |
3208 | ||
3209 | */ | |
3210 | ||
3211 | /* This function saves registers as follows. Registers marked with ' are | |
3212 | this function's registers (as opposed to the previous function's). | |
3213 | If a frame_pointer isn't needed, r4 is saved as a general register; | |
3214 | the space for the frame pointer is still allocated, though, to keep | |
3215 | things simple. | |
3216 | ||
3217 | ||
3218 | Top of Frame | |
3219 | ||
3220 | SP (FP') Previous FP | |
3221 | SP + 4 Alignment filler (sigh) | |
3222 | SP + 8 Space for locals reserved here. | |
3223 | . | |
3224 | . | |
3225 | . | |
3226 | SP + n All call saved register used. | |
3227 | . | |
3228 | . | |
3229 | . | |
3230 | SP + o All call saved fp registers used. | |
3231 | . | |
3232 | . | |
3233 | . | |
3234 | SP + p (SP') points to next available address. | |
6d36483b | 3235 | |
87ad11b0 | 3236 | */ |
3237 | ||
17d9b0c3 | 3238 | /* Global variables set by output_function_prologue(). */ |
cc858176 | 3239 | /* Size of frame. Need to know this to emit return insns from |
3240 | leaf procedures. */ | |
6bcdc1fb | 3241 | static HOST_WIDE_INT actual_fsize, local_fsize; |
3242 | static int save_fregs; | |
cc858176 | 3243 | |
daee63dd | 3244 | /* Emit RTL to store REG at the memory location specified by BASE+DISP. |
359a0be8 | 3245 | Handle case where DISP > 8k by using the add_high_const patterns. |
daee63dd | 3246 | |
3247 | Note in DISP > 8k case, we will leave the high part of the address | |
3248 | in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/ | |
7014838c | 3249 | |
6a2c16d6 | 3250 | static void |
6bcdc1fb | 3251 | store_reg (int reg, HOST_WIDE_INT disp, int base) |
87ad11b0 | 3252 | { |
6a2c16d6 | 3253 | rtx insn, dest, src, basereg; |
cc858176 | 3254 | |
3255 | src = gen_rtx_REG (word_mode, reg); | |
3256 | basereg = gen_rtx_REG (Pmode, base); | |
87ad11b0 | 3257 | if (VAL_14_BITS_P (disp)) |
daee63dd | 3258 | { |
cc858176 | 3259 | dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
6a2c16d6 | 3260 | insn = emit_move_insn (dest, src); |
daee63dd | 3261 | } |
6bcdc1fb | 3262 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3263 | { | |
3264 | rtx delta = GEN_INT (disp); | |
3265 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3266 | ||
3267 | emit_move_insn (tmpreg, delta); | |
3268 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
3269 | dest = gen_rtx_MEM (word_mode, tmpreg); | |
3270 | insn = emit_move_insn (dest, src); | |
3271 | if (DO_FRAME_NOTES) | |
3272 | { | |
3273 | REG_NOTES (insn) | |
3274 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3275 | gen_rtx_SET (VOIDmode, | |
3276 | gen_rtx_MEM (word_mode, | |
3277 | gen_rtx_PLUS (word_mode, basereg, | |
3278 | delta)), | |
3279 | src), | |
3280 | REG_NOTES (insn)); | |
3281 | } | |
3282 | } | |
daee63dd | 3283 | else |
3284 | { | |
cc858176 | 3285 | rtx delta = GEN_INT (disp); |
3286 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3287 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 3288 | |
cc858176 | 3289 | emit_move_insn (tmpreg, high); |
3290 | dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
6a2c16d6 | 3291 | insn = emit_move_insn (dest, src); |
3292 | if (DO_FRAME_NOTES) | |
3293 | { | |
3294 | REG_NOTES (insn) | |
3295 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3296 | gen_rtx_SET (VOIDmode, | |
3297 | gen_rtx_MEM (word_mode, | |
3298 | gen_rtx_PLUS (word_mode, basereg, | |
3299 | delta)), | |
3300 | src), | |
3301 | REG_NOTES (insn)); | |
3302 | } | |
daee63dd | 3303 | } |
6a2c16d6 | 3304 | |
3305 | if (DO_FRAME_NOTES) | |
3306 | RTX_FRAME_RELATED_P (insn) = 1; | |
daee63dd | 3307 | } |
3308 | ||
a584fe8a | 3309 | /* Emit RTL to store REG at the memory location specified by BASE and then |
3310 | add MOD to BASE. MOD must be <= 8k. */ | |
daee63dd | 3311 | |
a584fe8a | 3312 | static void |
6bcdc1fb | 3313 | store_reg_modify (int base, int reg, HOST_WIDE_INT mod) |
a584fe8a | 3314 | { |
3315 | rtx insn, basereg, srcreg, delta; | |
3316 | ||
ecf2283d | 3317 | gcc_assert (VAL_14_BITS_P (mod)); |
a584fe8a | 3318 | |
3319 | basereg = gen_rtx_REG (Pmode, base); | |
3320 | srcreg = gen_rtx_REG (word_mode, reg); | |
3321 | delta = GEN_INT (mod); | |
3322 | ||
3323 | insn = emit_insn (gen_post_store (basereg, srcreg, delta)); | |
3324 | if (DO_FRAME_NOTES) | |
3325 | { | |
3326 | RTX_FRAME_RELATED_P (insn) = 1; | |
3327 | ||
3328 | /* RTX_FRAME_RELATED_P must be set on each frame related set | |
3329 | in a parallel with more than one element. Don't set | |
3330 | RTX_FRAME_RELATED_P in the first set if reg is temporary | |
3331 | register 1. The effect of this operation is recorded in | |
3332 | the initial copy. */ | |
3333 | if (reg != 1) | |
3334 | { | |
3335 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1; | |
3336 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; | |
3337 | } | |
3338 | else | |
3339 | { | |
3340 | /* The first element of a PARALLEL is always processed if it is | |
3341 | a SET. Thus, we need an expression list for this case. */ | |
3342 | REG_NOTES (insn) | |
3343 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3344 | gen_rtx_SET (VOIDmode, basereg, | |
3345 | gen_rtx_PLUS (word_mode, basereg, delta)), | |
3346 | REG_NOTES (insn)); | |
3347 | } | |
3348 | } | |
3349 | } | |
3350 | ||
3351 | /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case | |
3352 | where DISP > 8k by using the add_high_const patterns. NOTE indicates | |
3353 | whether to add a frame note or not. | |
3354 | ||
3355 | In the DISP > 8k case, we leave the high part of the address in %r1. | |
3356 | There is code in expand_hppa_{prologue,epilogue} that knows about this. */ | |
7014838c | 3357 | |
6a2c16d6 | 3358 | static void |
6bcdc1fb | 3359 | set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note) |
87ad11b0 | 3360 | { |
6a2c16d6 | 3361 | rtx insn; |
cc858176 | 3362 | |
87ad11b0 | 3363 | if (VAL_14_BITS_P (disp)) |
cc858176 | 3364 | { |
6a2c16d6 | 3365 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
3366 | plus_constant (gen_rtx_REG (Pmode, base), disp)); | |
cc858176 | 3367 | } |
6bcdc1fb | 3368 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3369 | { | |
3370 | rtx basereg = gen_rtx_REG (Pmode, base); | |
3371 | rtx delta = GEN_INT (disp); | |
3372 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3373 | ||
3374 | emit_move_insn (tmpreg, delta); | |
3375 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), | |
3376 | gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
3377 | } | |
87ad11b0 | 3378 | else |
daee63dd | 3379 | { |
6a2c16d6 | 3380 | rtx basereg = gen_rtx_REG (Pmode, base); |
cc858176 | 3381 | rtx delta = GEN_INT (disp); |
6bcdc1fb | 3382 | rtx tmpreg = gen_rtx_REG (Pmode, 1); |
6a2c16d6 | 3383 | |
6bcdc1fb | 3384 | emit_move_insn (tmpreg, |
6a2c16d6 | 3385 | gen_rtx_PLUS (Pmode, basereg, |
cc858176 | 3386 | gen_rtx_HIGH (Pmode, delta))); |
6a2c16d6 | 3387 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
6bcdc1fb | 3388 | gen_rtx_LO_SUM (Pmode, tmpreg, delta)); |
daee63dd | 3389 | } |
6a2c16d6 | 3390 | |
a584fe8a | 3391 | if (DO_FRAME_NOTES && note) |
6a2c16d6 | 3392 | RTX_FRAME_RELATED_P (insn) = 1; |
87ad11b0 | 3393 | } |
3394 | ||
6bcdc1fb | 3395 | HOST_WIDE_INT |
3396 | compute_frame_size (HOST_WIDE_INT size, int *fregs_live) | |
87ad11b0 | 3397 | { |
256f9b65 | 3398 | int freg_saved = 0; |
3399 | int i, j; | |
3400 | ||
3401 | /* The code in hppa_expand_prologue and hppa_expand_epilogue must | |
3402 | be consistent with the rounding and size calculation done here. | |
3403 | Change them at the same time. */ | |
3404 | ||
3405 | /* We do our own stack alignment. First, round the size of the | |
3406 | stack locals up to a word boundary. */ | |
3407 | size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3408 | ||
3409 | /* Space for previous frame pointer + filler. If any frame is | |
3410 | allocated, we need to add in the STARTING_FRAME_OFFSET. We | |
3411 | waste some space here for the sake of HP compatibility. The | |
3412 | first slot is only used when the frame pointer is needed. */ | |
3413 | if (size || frame_pointer_needed) | |
3414 | size += STARTING_FRAME_OFFSET; | |
3415 | ||
a584fe8a | 3416 | /* If the current function calls __builtin_eh_return, then we need |
3417 | to allocate stack space for registers that will hold data for | |
3418 | the exception handler. */ | |
3419 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3420 | { | |
3421 | unsigned int i; | |
3422 | ||
3423 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
3424 | continue; | |
256f9b65 | 3425 | size += i * UNITS_PER_WORD; |
a584fe8a | 3426 | } |
3427 | ||
3a51bad9 | 3428 | /* Account for space used by the callee general register saves. */ |
256f9b65 | 3429 | for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--) |
7f7c4869 | 3430 | if (regs_ever_live[i]) |
256f9b65 | 3431 | size += UNITS_PER_WORD; |
df0651dc | 3432 | |
3a51bad9 | 3433 | /* Account for space used by the callee floating point register saves. */ |
bac38c40 | 3434 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
5e3c5739 | 3435 | if (regs_ever_live[i] |
256f9b65 | 3436 | || (!TARGET_64BIT && regs_ever_live[i + 1])) |
df0651dc | 3437 | { |
256f9b65 | 3438 | freg_saved = 1; |
002fc5f7 | 3439 | |
3a51bad9 | 3440 | /* We always save both halves of the FP register, so always |
3441 | increment the frame size by 8 bytes. */ | |
256f9b65 | 3442 | size += 8; |
df0651dc | 3443 | } |
3444 | ||
256f9b65 | 3445 | /* If any of the floating registers are saved, account for the |
3446 | alignment needed for the floating point register save block. */ | |
3447 | if (freg_saved) | |
3448 | { | |
3449 | size = (size + 7) & ~7; | |
3450 | if (fregs_live) | |
3451 | *fregs_live = 1; | |
3452 | } | |
3453 | ||
3a51bad9 | 3454 | /* The various ABIs include space for the outgoing parameters in the |
256f9b65 | 3455 | size of the current function's stack frame. We don't need to align |
3456 | for the outgoing arguments as their alignment is set by the final | |
3457 | rounding for the frame as a whole. */ | |
3458 | size += current_function_outgoing_args_size; | |
3a51bad9 | 3459 | |
3460 | /* Allocate space for the fixed frame marker. This space must be | |
e9ec370e | 3461 | allocated for any function that makes calls or allocates |
3a51bad9 | 3462 | stack space. */ |
256f9b65 | 3463 | if (!current_function_is_leaf || size) |
e9ec370e | 3464 | size += TARGET_64BIT ? 48 : 32; |
5e3c5739 | 3465 | |
256f9b65 | 3466 | /* Finally, round to the preferred stack boundary. */ |
2247cc5f | 3467 | return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1) |
3468 | & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
87ad11b0 | 3469 | } |
6d36483b | 3470 | |
17d9b0c3 | 3471 | /* Generate the assembly code for function entry. FILE is a stdio |
3472 | stream to output the code to. SIZE is an int: how many units of | |
3473 | temporary storage to allocate. | |
3474 | ||
3475 | Refer to the array `regs_ever_live' to determine which registers to | |
3476 | save; `regs_ever_live[I]' is nonzero if register number I is ever | |
3477 | used in the function. This function is responsible for knowing | |
3478 | which registers should not be saved even if used. */ | |
3479 | ||
3480 | /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block | |
3481 | of memory. If any fpu reg is used in the function, we allocate | |
3482 | such a block here, at the bottom of the frame, just in case it's needed. | |
3483 | ||
3484 | If this function is a leaf procedure, then we may choose not | |
3485 | to do a "save" insn. The decision about whether or not | |
3486 | to do this is made in regclass.c. */ | |
3487 | ||
6988553d | 3488 | static void |
5c1d8983 | 3489 | pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 3490 | { |
d151162a | 3491 | /* The function's label and associated .PROC must never be |
3492 | separated and must be output *after* any profiling declarations | |
3493 | to avoid changing spaces/subspaces within a procedure. */ | |
3494 | ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3495 | fputs ("\t.PROC\n", file); | |
3496 | ||
daee63dd | 3497 | /* hppa_expand_prologue does the dirty work now. We just need |
3498 | to output the assembler directives which denote the start | |
3499 | of a function. */ | |
6bcdc1fb | 3500 | fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize); |
df6edefa | 3501 | if (regs_ever_live[2]) |
9c0ac0fd | 3502 | fputs (",CALLS,SAVE_RP", file); |
daee63dd | 3503 | else |
9c0ac0fd | 3504 | fputs (",NO_CALLS", file); |
f3ba7709 | 3505 | |
e9ec370e | 3506 | /* The SAVE_SP flag is used to indicate that register %r3 is stored |
3507 | at the beginning of the frame and that it is used as the frame | |
3508 | pointer for the frame. We do this because our current frame | |
3ce7ff97 | 3509 | layout doesn't conform to that specified in the HP runtime |
e9ec370e | 3510 | documentation and we need a way to indicate to programs such as |
3511 | GDB where %r3 is saved. The SAVE_SP flag was chosen because it | |
3512 | isn't used by HP compilers but is supported by the assembler. | |
3513 | However, SAVE_SP is supposed to indicate that the previous stack | |
3514 | pointer has been saved in the frame marker. */ | |
f3ba7709 | 3515 | if (frame_pointer_needed) |
9c0ac0fd | 3516 | fputs (",SAVE_SP", file); |
f3ba7709 | 3517 | |
a9960cdc | 3518 | /* Pass on information about the number of callee register saves |
9b0c95be | 3519 | performed in the prologue. |
3520 | ||
3521 | The compiler is supposed to pass the highest register number | |
6d36483b | 3522 | saved, the assembler then has to adjust that number before |
9b0c95be | 3523 | entering it into the unwind descriptor (to account for any |
6d36483b | 3524 | caller saved registers with lower register numbers than the |
9b0c95be | 3525 | first callee saved register). */ |
3526 | if (gr_saved) | |
3527 | fprintf (file, ",ENTRY_GR=%d", gr_saved + 2); | |
3528 | ||
3529 | if (fr_saved) | |
3530 | fprintf (file, ",ENTRY_FR=%d", fr_saved + 11); | |
a9960cdc | 3531 | |
9c0ac0fd | 3532 | fputs ("\n\t.ENTRY\n", file); |
daee63dd | 3533 | |
2efea8c0 | 3534 | remove_useless_addtr_insns (0); |
daee63dd | 3535 | } |
3536 | ||
57ed30e5 | 3537 | void |
5c1d8983 | 3538 | hppa_expand_prologue (void) |
daee63dd | 3539 | { |
afd7b680 | 3540 | int merge_sp_adjust_with_store = 0; |
6bcdc1fb | 3541 | HOST_WIDE_INT size = get_frame_size (); |
3542 | HOST_WIDE_INT offset; | |
3543 | int i; | |
a584fe8a | 3544 | rtx insn, tmpreg; |
daee63dd | 3545 | |
a9960cdc | 3546 | gr_saved = 0; |
3547 | fr_saved = 0; | |
3ddcbb9d | 3548 | save_fregs = 0; |
3a51bad9 | 3549 | |
256f9b65 | 3550 | /* Compute total size for frame pointer, filler, locals and rounding to |
3551 | the next word boundary. Similar code appears in compute_frame_size | |
3552 | and must be changed in tandem with this code. */ | |
3553 | local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3554 | if (local_fsize || frame_pointer_needed) | |
3555 | local_fsize += STARTING_FRAME_OFFSET; | |
3a51bad9 | 3556 | |
a1ab4fa3 | 3557 | actual_fsize = compute_frame_size (size, &save_fregs); |
87ad11b0 | 3558 | |
daee63dd | 3559 | /* Compute a few things we will use often. */ |
440c23df | 3560 | tmpreg = gen_rtx_REG (word_mode, 1); |
87ad11b0 | 3561 | |
6d36483b | 3562 | /* Save RP first. The calling conventions manual states RP will |
cc858176 | 3563 | always be stored into the caller's frame at sp - 20 or sp - 16 |
5e3c5739 | 3564 | depending on which ABI is in use. */ |
a584fe8a | 3565 | if (regs_ever_live[2] || current_function_calls_eh_return) |
6a2c16d6 | 3566 | store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM); |
6d36483b | 3567 | |
daee63dd | 3568 | /* Allocate the local frame and set up the frame pointer if needed. */ |
58361f39 | 3569 | if (actual_fsize != 0) |
3570 | { | |
3571 | if (frame_pointer_needed) | |
3572 | { | |
3573 | /* Copy the old frame pointer temporarily into %r1. Set up the | |
3574 | new stack pointer, then store away the saved old frame pointer | |
a584fe8a | 3575 | into the stack at sp and at the same time update the stack |
3576 | pointer by actual_fsize bytes. Two versions, first | |
58361f39 | 3577 | handles small (<8k) frames. The second handles large (>=8k) |
3578 | frames. */ | |
a584fe8a | 3579 | insn = emit_move_insn (tmpreg, frame_pointer_rtx); |
3580 | if (DO_FRAME_NOTES) | |
cc858176 | 3581 | { |
a584fe8a | 3582 | /* We need to record the frame pointer save here since the |
3583 | new frame pointer is set in the following insn. */ | |
3584 | RTX_FRAME_RELATED_P (insn) = 1; | |
3585 | REG_NOTES (insn) | |
3586 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3587 | gen_rtx_SET (VOIDmode, | |
3588 | gen_rtx_MEM (word_mode, stack_pointer_rtx), | |
3589 | frame_pointer_rtx), | |
3590 | REG_NOTES (insn)); | |
cc858176 | 3591 | } |
a584fe8a | 3592 | |
3593 | insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); | |
3594 | if (DO_FRAME_NOTES) | |
3595 | RTX_FRAME_RELATED_P (insn) = 1; | |
3596 | ||
3597 | if (VAL_14_BITS_P (actual_fsize)) | |
3598 | store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize); | |
58361f39 | 3599 | else |
3600 | { | |
3601 | /* It is incorrect to store the saved frame pointer at *sp, | |
3602 | then increment sp (writes beyond the current stack boundary). | |
3603 | ||
3604 | So instead use stwm to store at *sp and post-increment the | |
3605 | stack pointer as an atomic operation. Then increment sp to | |
3606 | finish allocating the new frame. */ | |
6bcdc1fb | 3607 | HOST_WIDE_INT adjust1 = 8192 - 64; |
3608 | HOST_WIDE_INT adjust2 = actual_fsize - adjust1; | |
cc858176 | 3609 | |
a584fe8a | 3610 | store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1); |
6a2c16d6 | 3611 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3612 | adjust2, 1); |
58361f39 | 3613 | } |
a584fe8a | 3614 | |
e9ec370e | 3615 | /* We set SAVE_SP in frames that need a frame pointer. Thus, |
3616 | we need to store the previous stack pointer (frame pointer) | |
3617 | into the frame marker on targets that use the HP unwind | |
3618 | library. This allows the HP unwind library to be used to | |
3619 | unwind GCC frames. However, we are not fully compatible | |
3620 | with the HP library because our frame layout differs from | |
3621 | that specified in the HP runtime specification. | |
3622 | ||
3623 | We don't want a frame note on this instruction as the frame | |
3624 | marker moves during dynamic stack allocation. | |
3625 | ||
3626 | This instruction also serves as a blockage to prevent | |
3627 | register spills from being scheduled before the stack | |
3628 | pointer is raised. This is necessary as we store | |
3629 | registers using the frame pointer as a base register, | |
3630 | and the frame pointer is set before sp is raised. */ | |
3631 | if (TARGET_HPUX_UNWIND_LIBRARY) | |
3632 | { | |
3633 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, | |
3634 | GEN_INT (TARGET_64BIT ? -8 : -4)); | |
3635 | ||
3636 | emit_move_insn (gen_rtx_MEM (word_mode, addr), | |
3637 | frame_pointer_rtx); | |
3638 | } | |
3639 | else | |
3640 | emit_insn (gen_blockage ()); | |
58361f39 | 3641 | } |
3642 | /* no frame pointer needed. */ | |
3643 | else | |
3644 | { | |
3645 | /* In some cases we can perform the first callee register save | |
3646 | and allocating the stack frame at the same time. If so, just | |
3647 | make a note of it and defer allocating the frame until saving | |
3648 | the callee registers. */ | |
df6edefa | 3649 | if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0) |
58361f39 | 3650 | merge_sp_adjust_with_store = 1; |
3651 | /* Can not optimize. Adjust the stack frame by actual_fsize | |
3652 | bytes. */ | |
3653 | else | |
6a2c16d6 | 3654 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3655 | actual_fsize, 1); |
58361f39 | 3656 | } |
372ef038 | 3657 | } |
3658 | ||
6d36483b | 3659 | /* Normal register save. |
daee63dd | 3660 | |
3661 | Do not save the frame pointer in the frame_pointer_needed case. It | |
3662 | was done earlier. */ | |
87ad11b0 | 3663 | if (frame_pointer_needed) |
3664 | { | |
a584fe8a | 3665 | offset = local_fsize; |
3666 | ||
3667 | /* Saving the EH return data registers in the frame is the simplest | |
3668 | way to get the frame unwind information emitted. We put them | |
3669 | just before the general registers. */ | |
3670 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3671 | { | |
3672 | unsigned int i, regno; | |
3673 | ||
3674 | for (i = 0; ; ++i) | |
3675 | { | |
3676 | regno = EH_RETURN_DATA_REGNO (i); | |
3677 | if (regno == INVALID_REGNUM) | |
3678 | break; | |
3679 | ||
3680 | store_reg (regno, offset, FRAME_POINTER_REGNUM); | |
3681 | offset += UNITS_PER_WORD; | |
3682 | } | |
3683 | } | |
3684 | ||
3685 | for (i = 18; i >= 4; i--) | |
98328a39 | 3686 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3687 | { |
6a2c16d6 | 3688 | store_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 3689 | offset += UNITS_PER_WORD; |
a9960cdc | 3690 | gr_saved++; |
87ad11b0 | 3691 | } |
7f7c4869 | 3692 | /* Account for %r3 which is saved in a special place. */ |
9b0c95be | 3693 | gr_saved++; |
87ad11b0 | 3694 | } |
daee63dd | 3695 | /* No frame pointer needed. */ |
87ad11b0 | 3696 | else |
3697 | { | |
a584fe8a | 3698 | offset = local_fsize - actual_fsize; |
3699 | ||
3700 | /* Saving the EH return data registers in the frame is the simplest | |
3701 | way to get the frame unwind information emitted. */ | |
3702 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3703 | { | |
3704 | unsigned int i, regno; | |
3705 | ||
3706 | for (i = 0; ; ++i) | |
3707 | { | |
3708 | regno = EH_RETURN_DATA_REGNO (i); | |
3709 | if (regno == INVALID_REGNUM) | |
3710 | break; | |
3711 | ||
3712 | /* If merge_sp_adjust_with_store is nonzero, then we can | |
3713 | optimize the first save. */ | |
3714 | if (merge_sp_adjust_with_store) | |
3715 | { | |
3716 | store_reg_modify (STACK_POINTER_REGNUM, regno, -offset); | |
3717 | merge_sp_adjust_with_store = 0; | |
3718 | } | |
3719 | else | |
3720 | store_reg (regno, offset, STACK_POINTER_REGNUM); | |
3721 | offset += UNITS_PER_WORD; | |
3722 | } | |
3723 | } | |
3724 | ||
3725 | for (i = 18; i >= 3; i--) | |
98328a39 | 3726 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3727 | { |
6d36483b | 3728 | /* If merge_sp_adjust_with_store is nonzero, then we can |
afd7b680 | 3729 | optimize the first GR save. */ |
201f01e9 | 3730 | if (merge_sp_adjust_with_store) |
afd7b680 | 3731 | { |
a584fe8a | 3732 | store_reg_modify (STACK_POINTER_REGNUM, i, -offset); |
afd7b680 | 3733 | merge_sp_adjust_with_store = 0; |
afd7b680 | 3734 | } |
3735 | else | |
6a2c16d6 | 3736 | store_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 3737 | offset += UNITS_PER_WORD; |
a9960cdc | 3738 | gr_saved++; |
87ad11b0 | 3739 | } |
daee63dd | 3740 | |
afd7b680 | 3741 | /* If we wanted to merge the SP adjustment with a GR save, but we never |
daee63dd | 3742 | did any GR saves, then just emit the adjustment here. */ |
201f01e9 | 3743 | if (merge_sp_adjust_with_store) |
6a2c16d6 | 3744 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3745 | actual_fsize, 1); |
87ad11b0 | 3746 | } |
6d36483b | 3747 | |
df6edefa | 3748 | /* The hppa calling conventions say that %r19, the pic offset |
3749 | register, is saved at sp - 32 (in this function's frame) | |
3750 | when generating PIC code. FIXME: What is the correct thing | |
3751 | to do for functions which make no calls and allocate no | |
3752 | frame? Do we need to allocate a frame, or can we just omit | |
8f177faf | 3753 | the save? For now we'll just omit the save. |
3754 | ||
3755 | We don't want a note on this insn as the frame marker can | |
3756 | move if there is a dynamic stack allocation. */ | |
df6edefa | 3757 | if (flag_pic && actual_fsize != 0 && !TARGET_64BIT) |
8f177faf | 3758 | { |
3759 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32)); | |
3760 | ||
3761 | emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx); | |
3762 | ||
3763 | } | |
df6edefa | 3764 | |
87ad11b0 | 3765 | /* Align pointer properly (doubleword boundary). */ |
3766 | offset = (offset + 7) & ~7; | |
3767 | ||
3768 | /* Floating point register store. */ | |
3769 | if (save_fregs) | |
87ad11b0 | 3770 | { |
a584fe8a | 3771 | rtx base; |
3772 | ||
daee63dd | 3773 | /* First get the frame or stack pointer to the start of the FP register |
3774 | save area. */ | |
a1ab4fa3 | 3775 | if (frame_pointer_needed) |
a584fe8a | 3776 | { |
3777 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); | |
3778 | base = frame_pointer_rtx; | |
3779 | } | |
a1ab4fa3 | 3780 | else |
a584fe8a | 3781 | { |
3782 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); | |
3783 | base = stack_pointer_rtx; | |
3784 | } | |
daee63dd | 3785 | |
3786 | /* Now actually save the FP registers. */ | |
bac38c40 | 3787 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
7f7c4869 | 3788 | { |
5e3c5739 | 3789 | if (regs_ever_live[i] |
3790 | || (! TARGET_64BIT && regs_ever_live[i + 1])) | |
7f7c4869 | 3791 | { |
6a2c16d6 | 3792 | rtx addr, insn, reg; |
cc858176 | 3793 | addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); |
3794 | reg = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 3795 | insn = emit_move_insn (addr, reg); |
3796 | if (DO_FRAME_NOTES) | |
3797 | { | |
3798 | RTX_FRAME_RELATED_P (insn) = 1; | |
a584fe8a | 3799 | if (TARGET_64BIT) |
3800 | { | |
3801 | rtx mem = gen_rtx_MEM (DFmode, | |
3802 | plus_constant (base, offset)); | |
3803 | REG_NOTES (insn) | |
3804 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3805 | gen_rtx_SET (VOIDmode, mem, reg), | |
3806 | REG_NOTES (insn)); | |
3807 | } | |
3808 | else | |
3809 | { | |
3810 | rtx meml = gen_rtx_MEM (SFmode, | |
3811 | plus_constant (base, offset)); | |
3812 | rtx memr = gen_rtx_MEM (SFmode, | |
3813 | plus_constant (base, offset + 4)); | |
3814 | rtx regl = gen_rtx_REG (SFmode, i); | |
3815 | rtx regr = gen_rtx_REG (SFmode, i + 1); | |
3816 | rtx setl = gen_rtx_SET (VOIDmode, meml, regl); | |
3817 | rtx setr = gen_rtx_SET (VOIDmode, memr, regr); | |
3818 | rtvec vec; | |
3819 | ||
3820 | RTX_FRAME_RELATED_P (setl) = 1; | |
3821 | RTX_FRAME_RELATED_P (setr) = 1; | |
3822 | vec = gen_rtvec (2, setl, setr); | |
3823 | REG_NOTES (insn) | |
3824 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3825 | gen_rtx_SEQUENCE (VOIDmode, vec), | |
3826 | REG_NOTES (insn)); | |
3827 | } | |
6a2c16d6 | 3828 | } |
3829 | offset += GET_MODE_SIZE (DFmode); | |
7f7c4869 | 3830 | fr_saved++; |
3831 | } | |
3832 | } | |
87ad11b0 | 3833 | } |
3834 | } | |
3835 | ||
cc858176 | 3836 | /* Emit RTL to load REG from the memory location specified by BASE+DISP. |
3837 | Handle case where DISP > 8k by using the add_high_const patterns. */ | |
3838 | ||
6a2c16d6 | 3839 | static void |
6bcdc1fb | 3840 | load_reg (int reg, HOST_WIDE_INT disp, int base) |
cc858176 | 3841 | { |
6bcdc1fb | 3842 | rtx dest = gen_rtx_REG (word_mode, reg); |
3843 | rtx basereg = gen_rtx_REG (Pmode, base); | |
3844 | rtx src; | |
cc858176 | 3845 | |
cc858176 | 3846 | if (VAL_14_BITS_P (disp)) |
6bcdc1fb | 3847 | src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
3848 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) | |
cc858176 | 3849 | { |
6bcdc1fb | 3850 | rtx delta = GEN_INT (disp); |
3851 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3852 | ||
3853 | emit_move_insn (tmpreg, delta); | |
3854 | if (TARGET_DISABLE_INDEXING) | |
3855 | { | |
3856 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
3857 | src = gen_rtx_MEM (word_mode, tmpreg); | |
3858 | } | |
3859 | else | |
3860 | src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
cc858176 | 3861 | } |
3862 | else | |
3863 | { | |
3864 | rtx delta = GEN_INT (disp); | |
3865 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3866 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 3867 | |
cc858176 | 3868 | emit_move_insn (tmpreg, high); |
3869 | src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
cc858176 | 3870 | } |
6bcdc1fb | 3871 | |
3872 | emit_move_insn (dest, src); | |
cc858176 | 3873 | } |
daee63dd | 3874 | |
2247cc5f | 3875 | /* Update the total code bytes output to the text section. */ |
3876 | ||
3877 | static void | |
5c1d8983 | 3878 | update_total_code_bytes (int nbytes) |
2247cc5f | 3879 | { |
3880 | if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM) | |
8a05c3c2 | 3881 | && !IN_NAMED_SECTION_P (cfun->decl)) |
2247cc5f | 3882 | { |
3883 | if (INSN_ADDRESSES_SET_P ()) | |
3884 | { | |
3885 | unsigned long old_total = total_code_bytes; | |
3886 | ||
3887 | total_code_bytes += nbytes; | |
3888 | ||
3889 | /* Be prepared to handle overflows. */ | |
3890 | if (old_total > total_code_bytes) | |
3891 | total_code_bytes = -1; | |
3892 | } | |
3893 | else | |
3894 | total_code_bytes = -1; | |
3895 | } | |
3896 | } | |
3897 | ||
17d9b0c3 | 3898 | /* This function generates the assembly code for function exit. |
3899 | Args are as for output_function_prologue (). | |
3900 | ||
3901 | The function epilogue should not depend on the current stack | |
3902 | pointer! It should use the frame pointer only. This is mandatory | |
3903 | because of alloca; we also take advantage of it to omit stack | |
6dc3b0d9 | 3904 | adjustments before returning. */ |
17d9b0c3 | 3905 | |
3906 | static void | |
5c1d8983 | 3907 | pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 3908 | { |
3695c664 | 3909 | rtx insn = get_last_insn (); |
3910 | ||
2247cc5f | 3911 | last_address = 0; |
3912 | ||
daee63dd | 3913 | /* hppa_expand_epilogue does the dirty work now. We just need |
3914 | to output the assembler directives which denote the end | |
3695c664 | 3915 | of a function. |
3916 | ||
3917 | To make debuggers happy, emit a nop if the epilogue was completely | |
3918 | eliminated due to a volatile call as the last insn in the | |
6d36483b | 3919 | current function. That way the return address (in %r2) will |
3695c664 | 3920 | always point to a valid instruction in the current function. */ |
3921 | ||
3922 | /* Get the last real insn. */ | |
3923 | if (GET_CODE (insn) == NOTE) | |
3924 | insn = prev_real_insn (insn); | |
3925 | ||
3926 | /* If it is a sequence, then look inside. */ | |
3927 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3928 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
3929 | ||
6d36483b | 3930 | /* If insn is a CALL_INSN, then it must be a call to a volatile |
3695c664 | 3931 | function (otherwise there would be epilogue insns). */ |
3932 | if (insn && GET_CODE (insn) == CALL_INSN) | |
90c41894 | 3933 | { |
3934 | fputs ("\tnop\n", file); | |
3935 | last_address += 4; | |
3936 | } | |
6d36483b | 3937 | |
9c0ac0fd | 3938 | fputs ("\t.EXIT\n\t.PROCEND\n", file); |
90c41894 | 3939 | |
916c9cef | 3940 | if (TARGET_SOM && TARGET_GAS) |
3941 | { | |
3942 | /* We done with this subspace except possibly for some additional | |
3943 | debug information. Forget that we are in this subspace to ensure | |
3944 | that the next function is output in its own subspace. */ | |
3945 | forget_section (); | |
3946 | } | |
3947 | ||
2247cc5f | 3948 | if (INSN_ADDRESSES_SET_P ()) |
90c41894 | 3949 | { |
2247cc5f | 3950 | insn = get_last_nonnote_insn (); |
3951 | last_address += INSN_ADDRESSES (INSN_UID (insn)); | |
3952 | if (INSN_P (insn)) | |
3953 | last_address += insn_default_length (insn); | |
3954 | last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) | |
3955 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
90c41894 | 3956 | } |
2247cc5f | 3957 | |
3958 | /* Finally, update the total number of code bytes output so far. */ | |
3959 | update_total_code_bytes (last_address); | |
daee63dd | 3960 | } |
afd7b680 | 3961 | |
daee63dd | 3962 | void |
5c1d8983 | 3963 | hppa_expand_epilogue (void) |
daee63dd | 3964 | { |
6d36483b | 3965 | rtx tmpreg; |
6bcdc1fb | 3966 | HOST_WIDE_INT offset; |
3967 | HOST_WIDE_INT ret_off = 0; | |
3968 | int i; | |
58361f39 | 3969 | int merge_sp_adjust_with_load = 0; |
daee63dd | 3970 | |
3971 | /* We will use this often. */ | |
440c23df | 3972 | tmpreg = gen_rtx_REG (word_mode, 1); |
daee63dd | 3973 | |
3974 | /* Try to restore RP early to avoid load/use interlocks when | |
3975 | RP gets used in the return (bv) instruction. This appears to still | |
6dc3b0d9 | 3976 | be necessary even when we schedule the prologue and epilogue. */ |
a584fe8a | 3977 | if (regs_ever_live [2] || current_function_calls_eh_return) |
58361f39 | 3978 | { |
3979 | ret_off = TARGET_64BIT ? -16 : -20; | |
3980 | if (frame_pointer_needed) | |
3981 | { | |
6a2c16d6 | 3982 | load_reg (2, ret_off, FRAME_POINTER_REGNUM); |
58361f39 | 3983 | ret_off = 0; |
3984 | } | |
3985 | else | |
3986 | { | |
3987 | /* No frame pointer, and stack is smaller than 8k. */ | |
3988 | if (VAL_14_BITS_P (ret_off - actual_fsize)) | |
3989 | { | |
6a2c16d6 | 3990 | load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM); |
58361f39 | 3991 | ret_off = 0; |
3992 | } | |
3993 | } | |
3994 | } | |
daee63dd | 3995 | |
3996 | /* General register restores. */ | |
87ad11b0 | 3997 | if (frame_pointer_needed) |
3998 | { | |
a584fe8a | 3999 | offset = local_fsize; |
4000 | ||
4001 | /* If the current function calls __builtin_eh_return, then we need | |
4002 | to restore the saved EH data registers. */ | |
4003 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
4004 | { | |
4005 | unsigned int i, regno; | |
4006 | ||
4007 | for (i = 0; ; ++i) | |
4008 | { | |
4009 | regno = EH_RETURN_DATA_REGNO (i); | |
4010 | if (regno == INVALID_REGNUM) | |
4011 | break; | |
4012 | ||
4013 | load_reg (regno, offset, FRAME_POINTER_REGNUM); | |
4014 | offset += UNITS_PER_WORD; | |
4015 | } | |
4016 | } | |
4017 | ||
4018 | for (i = 18; i >= 4; i--) | |
98328a39 | 4019 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 4020 | { |
6a2c16d6 | 4021 | load_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 4022 | offset += UNITS_PER_WORD; |
87ad11b0 | 4023 | } |
87ad11b0 | 4024 | } |
4025 | else | |
4026 | { | |
a584fe8a | 4027 | offset = local_fsize - actual_fsize; |
4028 | ||
4029 | /* If the current function calls __builtin_eh_return, then we need | |
4030 | to restore the saved EH data registers. */ | |
4031 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
4032 | { | |
4033 | unsigned int i, regno; | |
4034 | ||
4035 | for (i = 0; ; ++i) | |
4036 | { | |
4037 | regno = EH_RETURN_DATA_REGNO (i); | |
4038 | if (regno == INVALID_REGNUM) | |
4039 | break; | |
4040 | ||
4041 | /* Only for the first load. | |
4042 | merge_sp_adjust_with_load holds the register load | |
4043 | with which we will merge the sp adjustment. */ | |
4044 | if (merge_sp_adjust_with_load == 0 | |
4045 | && local_fsize == 0 | |
4046 | && VAL_14_BITS_P (-actual_fsize)) | |
4047 | merge_sp_adjust_with_load = regno; | |
4048 | else | |
4049 | load_reg (regno, offset, STACK_POINTER_REGNUM); | |
4050 | offset += UNITS_PER_WORD; | |
4051 | } | |
4052 | } | |
4053 | ||
4054 | for (i = 18; i >= 3; i--) | |
7f7c4869 | 4055 | { |
98328a39 | 4056 | if (regs_ever_live[i] && ! call_used_regs[i]) |
7f7c4869 | 4057 | { |
7f7c4869 | 4058 | /* Only for the first load. |
4059 | merge_sp_adjust_with_load holds the register load | |
4060 | with which we will merge the sp adjustment. */ | |
58361f39 | 4061 | if (merge_sp_adjust_with_load == 0 |
7f7c4869 | 4062 | && local_fsize == 0 |
58361f39 | 4063 | && VAL_14_BITS_P (-actual_fsize)) |
7f7c4869 | 4064 | merge_sp_adjust_with_load = i; |
4065 | else | |
6a2c16d6 | 4066 | load_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 4067 | offset += UNITS_PER_WORD; |
7f7c4869 | 4068 | } |
4069 | } | |
87ad11b0 | 4070 | } |
daee63dd | 4071 | |
87ad11b0 | 4072 | /* Align pointer properly (doubleword boundary). */ |
4073 | offset = (offset + 7) & ~7; | |
4074 | ||
daee63dd | 4075 | /* FP register restores. */ |
87ad11b0 | 4076 | if (save_fregs) |
87ad11b0 | 4077 | { |
daee63dd | 4078 | /* Adjust the register to index off of. */ |
a1ab4fa3 | 4079 | if (frame_pointer_needed) |
a584fe8a | 4080 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); |
a1ab4fa3 | 4081 | else |
a584fe8a | 4082 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); |
daee63dd | 4083 | |
4084 | /* Actually do the restores now. */ | |
bac38c40 | 4085 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
cc858176 | 4086 | if (regs_ever_live[i] |
4087 | || (! TARGET_64BIT && regs_ever_live[i + 1])) | |
4088 | { | |
4089 | rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); | |
4090 | rtx dest = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 4091 | emit_move_insn (dest, src); |
cc858176 | 4092 | } |
87ad11b0 | 4093 | } |
daee63dd | 4094 | |
14660146 | 4095 | /* Emit a blockage insn here to keep these insns from being moved to |
4096 | an earlier spot in the epilogue, or into the main instruction stream. | |
4097 | ||
4098 | This is necessary as we must not cut the stack back before all the | |
4099 | restores are finished. */ | |
4100 | emit_insn (gen_blockage ()); | |
daee63dd | 4101 | |
9840d99d | 4102 | /* Reset stack pointer (and possibly frame pointer). The stack |
42819d4e | 4103 | pointer is initially set to fp + 64 to avoid a race condition. */ |
58361f39 | 4104 | if (frame_pointer_needed) |
87ad11b0 | 4105 | { |
cc858176 | 4106 | rtx delta = GEN_INT (-64); |
a584fe8a | 4107 | |
4108 | set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0); | |
4109 | emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta)); | |
87ad11b0 | 4110 | } |
daee63dd | 4111 | /* If we were deferring a callee register restore, do it now. */ |
58361f39 | 4112 | else if (merge_sp_adjust_with_load) |
4113 | { | |
4114 | rtx delta = GEN_INT (-actual_fsize); | |
cc858176 | 4115 | rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load); |
a584fe8a | 4116 | |
4117 | emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)); | |
58361f39 | 4118 | } |
daee63dd | 4119 | else if (actual_fsize != 0) |
a584fe8a | 4120 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
4121 | - actual_fsize, 0); | |
58361f39 | 4122 | |
4123 | /* If we haven't restored %r2 yet (no frame pointer, and a stack | |
4124 | frame greater than 8k), do so now. */ | |
4125 | if (ret_off != 0) | |
6a2c16d6 | 4126 | load_reg (2, ret_off, STACK_POINTER_REGNUM); |
a584fe8a | 4127 | |
4128 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
4129 | { | |
4130 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
4131 | ||
4132 | emit_insn (gen_blockage ()); | |
4133 | emit_insn (TARGET_64BIT | |
4134 | ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa) | |
4135 | : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa)); | |
4136 | } | |
87ad11b0 | 4137 | } |
4138 | ||
d7e2f694 | 4139 | rtx |
5c1d8983 | 4140 | hppa_pic_save_rtx (void) |
cf3de5bb | 4141 | { |
d7e2f694 | 4142 | return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM); |
df6edefa | 4143 | } |
4144 | ||
4145 | void | |
5c1d8983 | 4146 | hppa_profile_hook (int label_no) |
df6edefa | 4147 | { |
4da37e2f | 4148 | /* We use SImode for the address of the function in both 32 and |
4149 | 64-bit code to avoid having to provide DImode versions of the | |
4150 | lcla2 and load_offset_label_address insn patterns. */ | |
4151 | rtx reg = gen_reg_rtx (SImode); | |
4152 | rtx label_rtx = gen_label_rtx (); | |
a9ac13e4 | 4153 | rtx begin_label_rtx, call_insn; |
4154 | char begin_label_name[16]; | |
df6edefa | 4155 | |
a9ac13e4 | 4156 | ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL, |
b8a21949 | 4157 | label_no); |
4da37e2f | 4158 | begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name)); |
df6edefa | 4159 | |
4160 | if (TARGET_64BIT) | |
4161 | emit_move_insn (arg_pointer_rtx, | |
4162 | gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, | |
4163 | GEN_INT (64))); | |
4164 | ||
df6edefa | 4165 | emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2)); |
4166 | ||
4da37e2f | 4167 | /* The address of the function is loaded into %r25 with a instruction- |
4168 | relative sequence that avoids the use of relocations. The sequence | |
4169 | is split so that the load_offset_label_address instruction can | |
4170 | occupy the delay slot of the call to _mcount. */ | |
4171 | if (TARGET_PA_20) | |
4172 | emit_insn (gen_lcla2 (reg, label_rtx)); | |
4173 | else | |
4174 | emit_insn (gen_lcla1 (reg, label_rtx)); | |
4175 | ||
4176 | emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25), | |
4177 | reg, begin_label_rtx, label_rtx)); | |
4178 | ||
df6edefa | 4179 | #ifndef NO_PROFILE_COUNTERS |
4180 | { | |
4181 | rtx count_label_rtx, addr, r24; | |
a9ac13e4 | 4182 | char count_label_name[16]; |
df6edefa | 4183 | |
a9ac13e4 | 4184 | ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no); |
4185 | count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name)); | |
df6edefa | 4186 | |
831a12d9 | 4187 | addr = force_reg (Pmode, count_label_rtx); |
df6edefa | 4188 | r24 = gen_rtx_REG (Pmode, 24); |
4189 | emit_move_insn (r24, addr); | |
4190 | ||
df6edefa | 4191 | call_insn = |
4da37e2f | 4192 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4193 | gen_rtx_SYMBOL_REF (Pmode, | |
4194 | "_mcount")), | |
4195 | GEN_INT (TARGET_64BIT ? 24 : 12))); | |
df6edefa | 4196 | |
4197 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24); | |
4198 | } | |
4199 | #else | |
4da37e2f | 4200 | |
df6edefa | 4201 | call_insn = |
4da37e2f | 4202 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4203 | gen_rtx_SYMBOL_REF (Pmode, | |
4204 | "_mcount")), | |
4205 | GEN_INT (TARGET_64BIT ? 16 : 8))); | |
4206 | ||
df6edefa | 4207 | #endif |
4208 | ||
4da37e2f | 4209 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25)); |
4210 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26)); | |
4211 | ||
df6edefa | 4212 | /* Indicate the _mcount call cannot throw, nor will it execute a |
4213 | non-local goto. */ | |
4214 | REG_NOTES (call_insn) | |
4215 | = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn)); | |
cf3de5bb | 4216 | } |
4217 | ||
e07ff380 | 4218 | /* Fetch the return address for the frame COUNT steps up from |
4219 | the current frame, after the prologue. FRAMEADDR is the | |
4220 | frame pointer of the COUNT frame. | |
4221 | ||
f49b2e77 | 4222 | We want to ignore any export stub remnants here. To handle this, |
4223 | we examine the code at the return address, and if it is an export | |
4224 | stub, we return a memory rtx for the stub return address stored | |
4225 | at frame-24. | |
a6c6fd6c | 4226 | |
4227 | The value returned is used in two different ways: | |
4228 | ||
4229 | 1. To find a function's caller. | |
4230 | ||
4231 | 2. To change the return address for a function. | |
4232 | ||
4233 | This function handles most instances of case 1; however, it will | |
4234 | fail if there are two levels of stubs to execute on the return | |
4235 | path. The only way I believe that can happen is if the return value | |
4236 | needs a parameter relocation, which never happens for C code. | |
4237 | ||
4238 | This function handles most instances of case 2; however, it will | |
4239 | fail if we did not originally have stub code on the return path | |
f49b2e77 | 4240 | but will need stub code on the new return path. This can happen if |
a6c6fd6c | 4241 | the caller & callee are both in the main program, but the new |
f49b2e77 | 4242 | return location is in a shared library. */ |
e07ff380 | 4243 | |
4244 | rtx | |
5c1d8983 | 4245 | return_addr_rtx (int count, rtx frameaddr) |
e07ff380 | 4246 | { |
4247 | rtx label; | |
f49b2e77 | 4248 | rtx rp; |
e07ff380 | 4249 | rtx saved_rp; |
4250 | rtx ins; | |
4251 | ||
f49b2e77 | 4252 | if (count != 0) |
4253 | return NULL_RTX; | |
b29897dd | 4254 | |
f49b2e77 | 4255 | rp = get_hard_reg_initial_val (Pmode, 2); |
e07ff380 | 4256 | |
f49b2e77 | 4257 | if (TARGET_64BIT || TARGET_NO_SPACE_REGS) |
4258 | return rp; | |
e07ff380 | 4259 | |
b29897dd | 4260 | saved_rp = gen_reg_rtx (Pmode); |
f49b2e77 | 4261 | emit_move_insn (saved_rp, rp); |
e07ff380 | 4262 | |
4263 | /* Get pointer to the instruction stream. We have to mask out the | |
4264 | privilege level from the two low order bits of the return address | |
4265 | pointer here so that ins will point to the start of the first | |
4266 | instruction that would have been executed if we returned. */ | |
f49b2e77 | 4267 | ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR)); |
e07ff380 | 4268 | label = gen_label_rtx (); |
4269 | ||
4270 | /* Check the instruction stream at the normal return address for the | |
4271 | export stub: | |
4272 | ||
4273 | 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp | |
4274 | 0x004010a1 | stub+12: ldsid (sr0,rp),r1 | |
4275 | 0x00011820 | stub+16: mtsp r1,sr0 | |
4276 | 0xe0400002 | stub+20: be,n 0(sr0,rp) | |
4277 | ||
4278 | If it is an export stub, than our return address is really in | |
4279 | -24[frameaddr]. */ | |
4280 | ||
e00b80b2 | 4281 | emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE, |
4282 | NULL_RTX, SImode, 1); | |
e07ff380 | 4283 | emit_jump_insn (gen_bne (label)); |
4284 | ||
ad851752 | 4285 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)), |
e00b80b2 | 4286 | GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4287 | emit_jump_insn (gen_bne (label)); |
4288 | ||
ad851752 | 4289 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)), |
e00b80b2 | 4290 | GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4291 | emit_jump_insn (gen_bne (label)); |
4292 | ||
ad851752 | 4293 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)), |
e00b80b2 | 4294 | GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4295 | |
f49b2e77 | 4296 | /* If there is no export stub then just use the value saved from |
4297 | the return pointer register. */ | |
e07ff380 | 4298 | |
4299 | emit_jump_insn (gen_bne (label)); | |
4300 | ||
f49b2e77 | 4301 | /* Here we know that our return address points to an export |
e07ff380 | 4302 | stub. We don't want to return the address of the export stub, |
f49b2e77 | 4303 | but rather the return address of the export stub. That return |
4304 | address is stored at -24[frameaddr]. */ | |
e07ff380 | 4305 | |
f49b2e77 | 4306 | emit_move_insn (saved_rp, |
4307 | gen_rtx_MEM (Pmode, | |
4308 | memory_address (Pmode, | |
4309 | plus_constant (frameaddr, | |
4310 | -24)))); | |
e07ff380 | 4311 | |
4312 | emit_label (label); | |
f49b2e77 | 4313 | return saved_rp; |
e07ff380 | 4314 | } |
4315 | ||
757d4970 | 4316 | /* This is only valid once reload has completed because it depends on |
4317 | knowing exactly how much (if any) frame there is and... | |
4318 | ||
4319 | It's only valid if there is no frame marker to de-allocate and... | |
4320 | ||
4321 | It's only valid if %r2 hasn't been saved into the caller's frame | |
4322 | (we're not profiling and %r2 isn't live anywhere). */ | |
4323 | int | |
5c1d8983 | 4324 | hppa_can_use_return_insn_p (void) |
757d4970 | 4325 | { |
4326 | return (reload_completed | |
4327 | && (compute_frame_size (get_frame_size (), 0) ? 0 : 1) | |
757d4970 | 4328 | && ! regs_ever_live[2] |
4329 | && ! frame_pointer_needed); | |
4330 | } | |
4331 | ||
87ad11b0 | 4332 | void |
5c1d8983 | 4333 | emit_bcond_fp (enum rtx_code code, rtx operand0) |
87ad11b0 | 4334 | { |
ad851752 | 4335 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, |
4336 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
4337 | gen_rtx_fmt_ee (code, | |
4338 | VOIDmode, | |
4339 | gen_rtx_REG (CCFPmode, 0), | |
4340 | const0_rtx), | |
4341 | gen_rtx_LABEL_REF (VOIDmode, operand0), | |
4342 | pc_rtx))); | |
87ad11b0 | 4343 | |
4344 | } | |
4345 | ||
4346 | rtx | |
5c1d8983 | 4347 | gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1) |
87ad11b0 | 4348 | { |
ad851752 | 4349 | return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0), |
4350 | gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1)); | |
87ad11b0 | 4351 | } |
4352 | ||
8b49b3c7 | 4353 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
4354 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4355 | ||
747af5e7 | 4356 | static int |
5c1d8983 | 4357 | pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
8b49b3c7 | 4358 | { |
43048d2c | 4359 | enum attr_type attr_type; |
4360 | ||
cde3e16c | 4361 | /* Don't adjust costs for a pa8000 chip, also do not adjust any |
4362 | true dependencies as they are described with bypasses now. */ | |
4363 | if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0) | |
342aabd9 | 4364 | return cost; |
4365 | ||
d402da4b | 4366 | if (! recog_memoized (insn)) |
4367 | return 0; | |
8b49b3c7 | 4368 | |
43048d2c | 4369 | attr_type = get_attr_type (insn); |
4370 | ||
ecf2283d | 4371 | switch (REG_NOTE_KIND (link)) |
8b49b3c7 | 4372 | { |
ecf2283d | 4373 | case REG_DEP_ANTI: |
8b49b3c7 | 4374 | /* Anti dependency; DEP_INSN reads a register that INSN writes some |
4375 | cycles later. */ | |
4376 | ||
43048d2c | 4377 | if (attr_type == TYPE_FPLOAD) |
8b49b3c7 | 4378 | { |
d402da4b | 4379 | rtx pat = PATTERN (insn); |
4380 | rtx dep_pat = PATTERN (dep_insn); | |
4381 | if (GET_CODE (pat) == PARALLEL) | |
4382 | { | |
4383 | /* This happens for the fldXs,mb patterns. */ | |
4384 | pat = XVECEXP (pat, 0, 0); | |
4385 | } | |
4386 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
8b49b3c7 | 4387 | /* If this happens, we have to extend this to schedule |
d402da4b | 4388 | optimally. Return 0 for now. */ |
4389 | return 0; | |
8b49b3c7 | 4390 | |
d402da4b | 4391 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) |
8b49b3c7 | 4392 | { |
d402da4b | 4393 | if (! recog_memoized (dep_insn)) |
4394 | return 0; | |
8b49b3c7 | 4395 | switch (get_attr_type (dep_insn)) |
4396 | { | |
4397 | case TYPE_FPALU: | |
134b4858 | 4398 | case TYPE_FPMULSGL: |
4399 | case TYPE_FPMULDBL: | |
8b49b3c7 | 4400 | case TYPE_FPDIVSGL: |
4401 | case TYPE_FPDIVDBL: | |
4402 | case TYPE_FPSQRTSGL: | |
4403 | case TYPE_FPSQRTDBL: | |
d402da4b | 4404 | /* A fpload can't be issued until one cycle before a |
01cc3b75 | 4405 | preceding arithmetic operation has finished if |
d402da4b | 4406 | the target of the fpload is any of the sources |
4407 | (or destination) of the arithmetic operation. */ | |
cde3e16c | 4408 | return insn_default_latency (dep_insn) - 1; |
134b4858 | 4409 | |
4410 | default: | |
4411 | return 0; | |
4412 | } | |
4413 | } | |
4414 | } | |
43048d2c | 4415 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4416 | { |
4417 | rtx pat = PATTERN (insn); | |
4418 | rtx dep_pat = PATTERN (dep_insn); | |
4419 | if (GET_CODE (pat) == PARALLEL) | |
4420 | { | |
4421 | /* This happens for the fldXs,mb patterns. */ | |
4422 | pat = XVECEXP (pat, 0, 0); | |
4423 | } | |
4424 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4425 | /* If this happens, we have to extend this to schedule | |
4426 | optimally. Return 0 for now. */ | |
4427 | return 0; | |
4428 | ||
4429 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) | |
4430 | { | |
4431 | if (! recog_memoized (dep_insn)) | |
4432 | return 0; | |
4433 | switch (get_attr_type (dep_insn)) | |
4434 | { | |
4435 | case TYPE_FPDIVSGL: | |
4436 | case TYPE_FPDIVDBL: | |
4437 | case TYPE_FPSQRTSGL: | |
4438 | case TYPE_FPSQRTDBL: | |
4439 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4440 | preceding divide or sqrt operation has finished if |
134b4858 | 4441 | the target of the ALU flop is any of the sources |
4442 | (or destination) of the divide or sqrt operation. */ | |
cde3e16c | 4443 | return insn_default_latency (dep_insn) - 2; |
8b49b3c7 | 4444 | |
4445 | default: | |
4446 | return 0; | |
4447 | } | |
4448 | } | |
4449 | } | |
4450 | ||
4451 | /* For other anti dependencies, the cost is 0. */ | |
4452 | return 0; | |
ecf2283d | 4453 | |
4454 | case REG_DEP_OUTPUT: | |
134b4858 | 4455 | /* Output dependency; DEP_INSN writes a register that INSN writes some |
4456 | cycles later. */ | |
43048d2c | 4457 | if (attr_type == TYPE_FPLOAD) |
134b4858 | 4458 | { |
4459 | rtx pat = PATTERN (insn); | |
4460 | rtx dep_pat = PATTERN (dep_insn); | |
4461 | if (GET_CODE (pat) == PARALLEL) | |
4462 | { | |
4463 | /* This happens for the fldXs,mb patterns. */ | |
4464 | pat = XVECEXP (pat, 0, 0); | |
4465 | } | |
4466 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4467 | /* If this happens, we have to extend this to schedule | |
4468 | optimally. Return 0 for now. */ | |
4469 | return 0; | |
4470 | ||
4471 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4472 | { | |
4473 | if (! recog_memoized (dep_insn)) | |
4474 | return 0; | |
4475 | switch (get_attr_type (dep_insn)) | |
4476 | { | |
4477 | case TYPE_FPALU: | |
4478 | case TYPE_FPMULSGL: | |
4479 | case TYPE_FPMULDBL: | |
4480 | case TYPE_FPDIVSGL: | |
4481 | case TYPE_FPDIVDBL: | |
4482 | case TYPE_FPSQRTSGL: | |
4483 | case TYPE_FPSQRTDBL: | |
4484 | /* A fpload can't be issued until one cycle before a | |
01cc3b75 | 4485 | preceding arithmetic operation has finished if |
134b4858 | 4486 | the target of the fpload is the destination of the |
bea4bad2 | 4487 | arithmetic operation. |
4488 | ||
4489 | Exception: For PA7100LC, PA7200 and PA7300, the cost | |
4490 | is 3 cycles, unless they bundle together. We also | |
4491 | pay the penalty if the second insn is a fpload. */ | |
cde3e16c | 4492 | return insn_default_latency (dep_insn) - 1; |
8b49b3c7 | 4493 | |
134b4858 | 4494 | default: |
4495 | return 0; | |
4496 | } | |
4497 | } | |
4498 | } | |
43048d2c | 4499 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4500 | { |
4501 | rtx pat = PATTERN (insn); | |
4502 | rtx dep_pat = PATTERN (dep_insn); | |
4503 | if (GET_CODE (pat) == PARALLEL) | |
4504 | { | |
4505 | /* This happens for the fldXs,mb patterns. */ | |
4506 | pat = XVECEXP (pat, 0, 0); | |
4507 | } | |
4508 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4509 | /* If this happens, we have to extend this to schedule | |
4510 | optimally. Return 0 for now. */ | |
4511 | return 0; | |
4512 | ||
4513 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4514 | { | |
4515 | if (! recog_memoized (dep_insn)) | |
4516 | return 0; | |
4517 | switch (get_attr_type (dep_insn)) | |
4518 | { | |
4519 | case TYPE_FPDIVSGL: | |
4520 | case TYPE_FPDIVDBL: | |
4521 | case TYPE_FPSQRTSGL: | |
4522 | case TYPE_FPSQRTDBL: | |
4523 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4524 | preceding divide or sqrt operation has finished if |
134b4858 | 4525 | the target of the ALU flop is also the target of |
3398e91d | 4526 | the divide or sqrt operation. */ |
cde3e16c | 4527 | return insn_default_latency (dep_insn) - 2; |
134b4858 | 4528 | |
4529 | default: | |
4530 | return 0; | |
4531 | } | |
4532 | } | |
4533 | } | |
4534 | ||
4535 | /* For other output dependencies, the cost is 0. */ | |
4536 | return 0; | |
ecf2283d | 4537 | |
4538 | default: | |
4539 | gcc_unreachable (); | |
134b4858 | 4540 | } |
8b49b3c7 | 4541 | } |
87ad11b0 | 4542 | |
747af5e7 | 4543 | /* Adjust scheduling priorities. We use this to try and keep addil |
4544 | and the next use of %r1 close together. */ | |
4545 | static int | |
5c1d8983 | 4546 | pa_adjust_priority (rtx insn, int priority) |
747af5e7 | 4547 | { |
4548 | rtx set = single_set (insn); | |
4549 | rtx src, dest; | |
4550 | if (set) | |
4551 | { | |
4552 | src = SET_SRC (set); | |
4553 | dest = SET_DEST (set); | |
4554 | if (GET_CODE (src) == LO_SUM | |
4555 | && symbolic_operand (XEXP (src, 1), VOIDmode) | |
4556 | && ! read_only_operand (XEXP (src, 1), VOIDmode)) | |
4557 | priority >>= 3; | |
4558 | ||
4559 | else if (GET_CODE (src) == MEM | |
4560 | && GET_CODE (XEXP (src, 0)) == LO_SUM | |
4561 | && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode) | |
4562 | && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode)) | |
4563 | priority >>= 1; | |
4564 | ||
4565 | else if (GET_CODE (dest) == MEM | |
4566 | && GET_CODE (XEXP (dest, 0)) == LO_SUM | |
4567 | && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode) | |
4568 | && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)) | |
4569 | priority >>= 3; | |
4570 | } | |
4571 | return priority; | |
4572 | } | |
4573 | ||
4574 | /* The 700 can only issue a single insn at a time. | |
4575 | The 7XXX processors can issue two insns at a time. | |
4576 | The 8000 can issue 4 insns at a time. */ | |
4577 | static int | |
5c1d8983 | 4578 | pa_issue_rate (void) |
747af5e7 | 4579 | { |
4580 | switch (pa_cpu) | |
4581 | { | |
4582 | case PROCESSOR_700: return 1; | |
4583 | case PROCESSOR_7100: return 2; | |
4584 | case PROCESSOR_7100LC: return 2; | |
4585 | case PROCESSOR_7200: return 2; | |
bea4bad2 | 4586 | case PROCESSOR_7300: return 2; |
747af5e7 | 4587 | case PROCESSOR_8000: return 4; |
4588 | ||
4589 | default: | |
ecf2283d | 4590 | gcc_unreachable (); |
747af5e7 | 4591 | } |
4592 | } | |
4593 | ||
4594 | ||
4595 | ||
58e17b0b | 4596 | /* Return any length adjustment needed by INSN which already has its length |
6d36483b | 4597 | computed as LENGTH. Return zero if no adjustment is necessary. |
58e17b0b | 4598 | |
5fbd5940 | 4599 | For the PA: function calls, millicode calls, and backwards short |
6d36483b | 4600 | conditional branches with unfilled delay slots need an adjustment by +1 |
5fbd5940 | 4601 | (to account for the NOP which will be inserted into the instruction stream). |
58e17b0b | 4602 | |
4603 | Also compute the length of an inline block move here as it is too | |
5fbd5940 | 4604 | complicated to express as a length attribute in pa.md. */ |
58e17b0b | 4605 | int |
5c1d8983 | 4606 | pa_adjust_insn_length (rtx insn, int length) |
58e17b0b | 4607 | { |
4608 | rtx pat = PATTERN (insn); | |
4609 | ||
faf3f8c1 | 4610 | /* Jumps inside switch tables which have unfilled delay slots need |
4611 | adjustment. */ | |
4612 | if (GET_CODE (insn) == JUMP_INSN | |
b932f66c | 4613 | && GET_CODE (pat) == PARALLEL |
4614 | && get_attr_type (insn) == TYPE_BTABLE_BRANCH) | |
3b1e673e | 4615 | return 4; |
58e17b0b | 4616 | /* Millicode insn with an unfilled delay slot. */ |
4617 | else if (GET_CODE (insn) == INSN | |
4618 | && GET_CODE (pat) != SEQUENCE | |
4619 | && GET_CODE (pat) != USE | |
4620 | && GET_CODE (pat) != CLOBBER | |
4621 | && get_attr_type (insn) == TYPE_MILLI) | |
5a1231ef | 4622 | return 4; |
58e17b0b | 4623 | /* Block move pattern. */ |
4624 | else if (GET_CODE (insn) == INSN | |
4625 | && GET_CODE (pat) == PARALLEL | |
f2ebcf32 | 4626 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET |
58e17b0b | 4627 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM |
4628 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM | |
4629 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode | |
4630 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode) | |
008c057d | 4631 | return compute_movmem_length (insn) - 4; |
a7e1bb24 | 4632 | /* Block clear pattern. */ |
4633 | else if (GET_CODE (insn) == INSN | |
4634 | && GET_CODE (pat) == PARALLEL | |
4635 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET | |
4636 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM | |
4637 | && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx | |
4638 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode) | |
008c057d | 4639 | return compute_clrmem_length (insn) - 4; |
58e17b0b | 4640 | /* Conditional branch with an unfilled delay slot. */ |
5fbd5940 | 4641 | else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn)) |
4642 | { | |
4643 | /* Adjust a short backwards conditional with an unfilled delay slot. */ | |
4644 | if (GET_CODE (pat) == SET | |
5a1231ef | 4645 | && length == 4 |
5fbd5940 | 4646 | && ! forward_branch_p (insn)) |
5a1231ef | 4647 | return 4; |
546a40bd | 4648 | else if (GET_CODE (pat) == PARALLEL |
4649 | && get_attr_type (insn) == TYPE_PARALLEL_BRANCH | |
4650 | && length == 4) | |
4651 | return 4; | |
5fbd5940 | 4652 | /* Adjust dbra insn with short backwards conditional branch with |
6d36483b | 4653 | unfilled delay slot -- only for case where counter is in a |
6dc3b0d9 | 4654 | general register register. */ |
5fbd5940 | 4655 | else if (GET_CODE (pat) == PARALLEL |
4656 | && GET_CODE (XVECEXP (pat, 0, 1)) == SET | |
4657 | && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG | |
6d36483b | 4658 | && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0)) |
5a1231ef | 4659 | && length == 4 |
5fbd5940 | 4660 | && ! forward_branch_p (insn)) |
5a1231ef | 4661 | return 4; |
5fbd5940 | 4662 | else |
4663 | return 0; | |
4664 | } | |
546a40bd | 4665 | return 0; |
58e17b0b | 4666 | } |
4667 | ||
87ad11b0 | 4668 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
4669 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
4670 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
4671 | ||
4672 | void | |
5c1d8983 | 4673 | print_operand (FILE *file, rtx x, int code) |
87ad11b0 | 4674 | { |
4675 | switch (code) | |
4676 | { | |
4677 | case '#': | |
4678 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
4679 | if (dbr_sequence_length () == 0) | |
4680 | fputs ("\n\tnop", file); | |
4681 | return; | |
4682 | case '*': | |
87fcb603 | 4683 | /* Output a nullification completer if there's nothing for the */ |
6d36483b | 4684 | /* delay slot or nullification is requested. */ |
87ad11b0 | 4685 | if (dbr_sequence_length () == 0 || |
4686 | (final_sequence && | |
4687 | INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))) | |
4688 | fputs (",n", file); | |
4689 | return; | |
4690 | case 'R': | |
4691 | /* Print out the second register name of a register pair. | |
4692 | I.e., R (6) => 7. */ | |
ea52c577 | 4693 | fputs (reg_names[REGNO (x) + 1], file); |
87ad11b0 | 4694 | return; |
4695 | case 'r': | |
6dc3b0d9 | 4696 | /* A register or zero. */ |
891b55b4 | 4697 | if (x == const0_rtx |
4698 | || (x == CONST0_RTX (DFmode)) | |
4699 | || (x == CONST0_RTX (SFmode))) | |
87ad11b0 | 4700 | { |
c6ae275c | 4701 | fputs ("%r0", file); |
4702 | return; | |
4703 | } | |
4704 | else | |
4705 | break; | |
4706 | case 'f': | |
6dc3b0d9 | 4707 | /* A register or zero (floating point). */ |
c6ae275c | 4708 | if (x == const0_rtx |
4709 | || (x == CONST0_RTX (DFmode)) | |
4710 | || (x == CONST0_RTX (SFmode))) | |
4711 | { | |
4712 | fputs ("%fr0", file); | |
87ad11b0 | 4713 | return; |
4714 | } | |
4715 | else | |
4716 | break; | |
2d14b1f0 | 4717 | case 'A': |
4718 | { | |
4719 | rtx xoperands[2]; | |
4720 | ||
4721 | xoperands[0] = XEXP (XEXP (x, 0), 0); | |
4722 | xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0); | |
4723 | output_global_address (file, xoperands[1], 0); | |
4724 | fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]); | |
4725 | return; | |
4726 | } | |
4727 | ||
c8975385 | 4728 | case 'C': /* Plain (C)ondition */ |
87ad11b0 | 4729 | case 'X': |
4730 | switch (GET_CODE (x)) | |
6d36483b | 4731 | { |
87ad11b0 | 4732 | case EQ: |
9c0ac0fd | 4733 | fputs ("=", file); break; |
87ad11b0 | 4734 | case NE: |
9c0ac0fd | 4735 | fputs ("<>", file); break; |
87ad11b0 | 4736 | case GT: |
9c0ac0fd | 4737 | fputs (">", file); break; |
87ad11b0 | 4738 | case GE: |
9c0ac0fd | 4739 | fputs (">=", file); break; |
87ad11b0 | 4740 | case GEU: |
9c0ac0fd | 4741 | fputs (">>=", file); break; |
87ad11b0 | 4742 | case GTU: |
9c0ac0fd | 4743 | fputs (">>", file); break; |
87ad11b0 | 4744 | case LT: |
9c0ac0fd | 4745 | fputs ("<", file); break; |
87ad11b0 | 4746 | case LE: |
9c0ac0fd | 4747 | fputs ("<=", file); break; |
87ad11b0 | 4748 | case LEU: |
9c0ac0fd | 4749 | fputs ("<<=", file); break; |
87ad11b0 | 4750 | case LTU: |
9c0ac0fd | 4751 | fputs ("<<", file); break; |
87ad11b0 | 4752 | default: |
ecf2283d | 4753 | gcc_unreachable (); |
87ad11b0 | 4754 | } |
4755 | return; | |
c8975385 | 4756 | case 'N': /* Condition, (N)egated */ |
87ad11b0 | 4757 | switch (GET_CODE (x)) |
4758 | { | |
4759 | case EQ: | |
9c0ac0fd | 4760 | fputs ("<>", file); break; |
87ad11b0 | 4761 | case NE: |
9c0ac0fd | 4762 | fputs ("=", file); break; |
87ad11b0 | 4763 | case GT: |
9c0ac0fd | 4764 | fputs ("<=", file); break; |
87ad11b0 | 4765 | case GE: |
9c0ac0fd | 4766 | fputs ("<", file); break; |
87ad11b0 | 4767 | case GEU: |
9c0ac0fd | 4768 | fputs ("<<", file); break; |
87ad11b0 | 4769 | case GTU: |
9c0ac0fd | 4770 | fputs ("<<=", file); break; |
87ad11b0 | 4771 | case LT: |
9c0ac0fd | 4772 | fputs (">=", file); break; |
87ad11b0 | 4773 | case LE: |
9c0ac0fd | 4774 | fputs (">", file); break; |
87ad11b0 | 4775 | case LEU: |
9c0ac0fd | 4776 | fputs (">>", file); break; |
87ad11b0 | 4777 | case LTU: |
9c0ac0fd | 4778 | fputs (">>=", file); break; |
87ad11b0 | 4779 | default: |
ecf2283d | 4780 | gcc_unreachable (); |
87ad11b0 | 4781 | } |
4782 | return; | |
ea52c577 | 4783 | /* For floating point comparisons. Note that the output |
321c1598 | 4784 | predicates are the complement of the desired mode. The |
4785 | conditions for GT, GE, LT, LE and LTGT cause an invalid | |
4786 | operation exception if the result is unordered and this | |
4787 | exception is enabled in the floating-point status register. */ | |
61230bc9 | 4788 | case 'Y': |
4789 | switch (GET_CODE (x)) | |
4790 | { | |
4791 | case EQ: | |
9c0ac0fd | 4792 | fputs ("!=", file); break; |
61230bc9 | 4793 | case NE: |
9c0ac0fd | 4794 | fputs ("=", file); break; |
61230bc9 | 4795 | case GT: |
32509e56 | 4796 | fputs ("!>", file); break; |
61230bc9 | 4797 | case GE: |
32509e56 | 4798 | fputs ("!>=", file); break; |
61230bc9 | 4799 | case LT: |
32509e56 | 4800 | fputs ("!<", file); break; |
61230bc9 | 4801 | case LE: |
32509e56 | 4802 | fputs ("!<=", file); break; |
4803 | case LTGT: | |
4804 | fputs ("!<>", file); break; | |
4805 | case UNLE: | |
321c1598 | 4806 | fputs ("!?<=", file); break; |
32509e56 | 4807 | case UNLT: |
321c1598 | 4808 | fputs ("!?<", file); break; |
32509e56 | 4809 | case UNGE: |
321c1598 | 4810 | fputs ("!?>=", file); break; |
32509e56 | 4811 | case UNGT: |
321c1598 | 4812 | fputs ("!?>", file); break; |
32509e56 | 4813 | case UNEQ: |
321c1598 | 4814 | fputs ("!?=", file); break; |
32509e56 | 4815 | case UNORDERED: |
321c1598 | 4816 | fputs ("!?", file); break; |
32509e56 | 4817 | case ORDERED: |
321c1598 | 4818 | fputs ("?", file); break; |
61230bc9 | 4819 | default: |
ecf2283d | 4820 | gcc_unreachable (); |
61230bc9 | 4821 | } |
4822 | return; | |
c8975385 | 4823 | case 'S': /* Condition, operands are (S)wapped. */ |
4824 | switch (GET_CODE (x)) | |
4825 | { | |
4826 | case EQ: | |
9c0ac0fd | 4827 | fputs ("=", file); break; |
c8975385 | 4828 | case NE: |
9c0ac0fd | 4829 | fputs ("<>", file); break; |
c8975385 | 4830 | case GT: |
9c0ac0fd | 4831 | fputs ("<", file); break; |
c8975385 | 4832 | case GE: |
9c0ac0fd | 4833 | fputs ("<=", file); break; |
c8975385 | 4834 | case GEU: |
9c0ac0fd | 4835 | fputs ("<<=", file); break; |
c8975385 | 4836 | case GTU: |
9c0ac0fd | 4837 | fputs ("<<", file); break; |
c8975385 | 4838 | case LT: |
9c0ac0fd | 4839 | fputs (">", file); break; |
c8975385 | 4840 | case LE: |
9c0ac0fd | 4841 | fputs (">=", file); break; |
c8975385 | 4842 | case LEU: |
9c0ac0fd | 4843 | fputs (">>=", file); break; |
c8975385 | 4844 | case LTU: |
9c0ac0fd | 4845 | fputs (">>", file); break; |
c8975385 | 4846 | default: |
ecf2283d | 4847 | gcc_unreachable (); |
6d36483b | 4848 | } |
c8975385 | 4849 | return; |
4850 | case 'B': /* Condition, (B)oth swapped and negate. */ | |
4851 | switch (GET_CODE (x)) | |
4852 | { | |
4853 | case EQ: | |
9c0ac0fd | 4854 | fputs ("<>", file); break; |
c8975385 | 4855 | case NE: |
9c0ac0fd | 4856 | fputs ("=", file); break; |
c8975385 | 4857 | case GT: |
9c0ac0fd | 4858 | fputs (">=", file); break; |
c8975385 | 4859 | case GE: |
9c0ac0fd | 4860 | fputs (">", file); break; |
c8975385 | 4861 | case GEU: |
9c0ac0fd | 4862 | fputs (">>", file); break; |
c8975385 | 4863 | case GTU: |
9c0ac0fd | 4864 | fputs (">>=", file); break; |
c8975385 | 4865 | case LT: |
9c0ac0fd | 4866 | fputs ("<=", file); break; |
c8975385 | 4867 | case LE: |
9c0ac0fd | 4868 | fputs ("<", file); break; |
c8975385 | 4869 | case LEU: |
9c0ac0fd | 4870 | fputs ("<<", file); break; |
c8975385 | 4871 | case LTU: |
9c0ac0fd | 4872 | fputs ("<<=", file); break; |
c8975385 | 4873 | default: |
ecf2283d | 4874 | gcc_unreachable (); |
6d36483b | 4875 | } |
c8975385 | 4876 | return; |
4877 | case 'k': | |
ecf2283d | 4878 | gcc_assert (GET_CODE (x) == CONST_INT); |
4879 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x)); | |
4880 | return; | |
5e3c5739 | 4881 | case 'Q': |
ecf2283d | 4882 | gcc_assert (GET_CODE (x) == CONST_INT); |
4883 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63)); | |
4884 | return; | |
e5965947 | 4885 | case 'L': |
ecf2283d | 4886 | gcc_assert (GET_CODE (x) == CONST_INT); |
4887 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31)); | |
4888 | return; | |
3a16146d | 4889 | case 'O': |
ecf2283d | 4890 | gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0); |
4891 | fprintf (file, "%d", exact_log2 (INTVAL (x))); | |
4892 | return; | |
5e3c5739 | 4893 | case 'p': |
ecf2283d | 4894 | gcc_assert (GET_CODE (x) == CONST_INT); |
4895 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63)); | |
4896 | return; | |
e5965947 | 4897 | case 'P': |
ecf2283d | 4898 | gcc_assert (GET_CODE (x) == CONST_INT); |
4899 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31)); | |
4900 | return; | |
c8975385 | 4901 | case 'I': |
4902 | if (GET_CODE (x) == CONST_INT) | |
4903 | fputs ("i", file); | |
4904 | return; | |
87ad11b0 | 4905 | case 'M': |
27ef382d | 4906 | case 'F': |
87ad11b0 | 4907 | switch (GET_CODE (XEXP (x, 0))) |
4908 | { | |
4909 | case PRE_DEC: | |
4910 | case PRE_INC: | |
e4065f95 | 4911 | if (ASSEMBLER_DIALECT == 0) |
4912 | fputs ("s,mb", file); | |
4913 | else | |
4914 | fputs (",mb", file); | |
87ad11b0 | 4915 | break; |
4916 | case POST_DEC: | |
4917 | case POST_INC: | |
e4065f95 | 4918 | if (ASSEMBLER_DIALECT == 0) |
4919 | fputs ("s,ma", file); | |
4920 | else | |
4921 | fputs (",ma", file); | |
87ad11b0 | 4922 | break; |
27ef382d | 4923 | case PLUS: |
dbd3d89d | 4924 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
4925 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
4926 | { | |
4927 | if (ASSEMBLER_DIALECT == 0) | |
4928 | fputs ("x", file); | |
4929 | } | |
4930 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
4931 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) | |
e4065f95 | 4932 | { |
4933 | if (ASSEMBLER_DIALECT == 0) | |
4934 | fputs ("x,s", file); | |
4935 | else | |
4936 | fputs (",s", file); | |
4937 | } | |
4938 | else if (code == 'F' && ASSEMBLER_DIALECT == 0) | |
27ef382d | 4939 | fputs ("s", file); |
87ad11b0 | 4940 | break; |
4941 | default: | |
e4065f95 | 4942 | if (code == 'F' && ASSEMBLER_DIALECT == 0) |
27ef382d | 4943 | fputs ("s", file); |
87ad11b0 | 4944 | break; |
4945 | } | |
4946 | return; | |
4947 | case 'G': | |
f9333726 | 4948 | output_global_address (file, x, 0); |
4949 | return; | |
4950 | case 'H': | |
4951 | output_global_address (file, x, 1); | |
87ad11b0 | 4952 | return; |
4953 | case 0: /* Don't do anything special */ | |
4954 | break; | |
42faba01 | 4955 | case 'Z': |
4956 | { | |
4957 | unsigned op[3]; | |
fb22aedc | 4958 | compute_zdepwi_operands (INTVAL (x), op); |
42faba01 | 4959 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); |
4960 | return; | |
4961 | } | |
5e3c5739 | 4962 | case 'z': |
4963 | { | |
4964 | unsigned op[3]; | |
4965 | compute_zdepdi_operands (INTVAL (x), op); | |
4966 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); | |
4967 | return; | |
4968 | } | |
c9cc98e1 | 4969 | case 'c': |
4970 | /* We can get here from a .vtable_inherit due to our | |
4971 | CONSTANT_ADDRESS_P rejecting perfectly good constant | |
4972 | addresses. */ | |
4973 | break; | |
87ad11b0 | 4974 | default: |
ecf2283d | 4975 | gcc_unreachable (); |
87ad11b0 | 4976 | } |
4977 | if (GET_CODE (x) == REG) | |
df0651dc | 4978 | { |
35661368 | 4979 | fputs (reg_names [REGNO (x)], file); |
5e3c5739 | 4980 | if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4) |
4981 | { | |
4982 | fputs ("R", file); | |
4983 | return; | |
4984 | } | |
4985 | if (FP_REG_P (x) | |
4986 | && GET_MODE_SIZE (GET_MODE (x)) <= 4 | |
4987 | && (REGNO (x) & 1) == 0) | |
35661368 | 4988 | fputs ("L", file); |
df0651dc | 4989 | } |
87ad11b0 | 4990 | else if (GET_CODE (x) == MEM) |
4991 | { | |
4992 | int size = GET_MODE_SIZE (GET_MODE (x)); | |
f7dff90d | 4993 | rtx base = NULL_RTX; |
87ad11b0 | 4994 | switch (GET_CODE (XEXP (x, 0))) |
4995 | { | |
4996 | case PRE_DEC: | |
4997 | case POST_DEC: | |
5e3c5739 | 4998 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 4999 | fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5000 | break; |
5001 | case PRE_INC: | |
5002 | case POST_INC: | |
5e3c5739 | 5003 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 5004 | fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5005 | break; |
dbd3d89d | 5006 | case PLUS: |
5007 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT) | |
34940871 | 5008 | fprintf (file, "%s(%s)", |
27ef382d | 5009 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))], |
5010 | reg_names [REGNO (XEXP (XEXP (x, 0), 1))]); | |
dbd3d89d | 5011 | else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) |
34940871 | 5012 | fprintf (file, "%s(%s)", |
27ef382d | 5013 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))], |
5014 | reg_names [REGNO (XEXP (XEXP (x, 0), 0))]); | |
dbd3d89d | 5015 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5016 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5017 | { | |
5018 | /* Because the REG_POINTER flag can get lost during reload, | |
5019 | GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the | |
5020 | index and base registers in the combined move patterns. */ | |
5021 | rtx base = XEXP (XEXP (x, 0), 1); | |
5022 | rtx index = XEXP (XEXP (x, 0), 0); | |
5023 | ||
5024 | fprintf (file, "%s(%s)", | |
5025 | reg_names [REGNO (index)], reg_names [REGNO (base)]); | |
5026 | } | |
27ef382d | 5027 | else |
5028 | output_address (XEXP (x, 0)); | |
87ad11b0 | 5029 | break; |
dbd3d89d | 5030 | default: |
5031 | output_address (XEXP (x, 0)); | |
5032 | break; | |
87ad11b0 | 5033 | } |
5034 | } | |
87ad11b0 | 5035 | else |
5036 | output_addr_const (file, x); | |
5037 | } | |
5038 | ||
6dc3b0d9 | 5039 | /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */ |
87ad11b0 | 5040 | |
5041 | void | |
5c1d8983 | 5042 | output_global_address (FILE *file, rtx x, int round_constant) |
87ad11b0 | 5043 | { |
2ee034bc | 5044 | |
5045 | /* Imagine (high (const (plus ...))). */ | |
5046 | if (GET_CODE (x) == HIGH) | |
5047 | x = XEXP (x, 0); | |
5048 | ||
611a88e1 | 5049 | if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode)) |
5f43b4f6 | 5050 | output_addr_const (file, x); |
b4a7bf10 | 5051 | else if (GET_CODE (x) == SYMBOL_REF && !flag_pic) |
87ad11b0 | 5052 | { |
5f43b4f6 | 5053 | output_addr_const (file, x); |
9c0ac0fd | 5054 | fputs ("-$global$", file); |
87ad11b0 | 5055 | } |
5056 | else if (GET_CODE (x) == CONST) | |
5057 | { | |
611a88e1 | 5058 | const char *sep = ""; |
87ad11b0 | 5059 | int offset = 0; /* assembler wants -$global$ at end */ |
33ae0dba | 5060 | rtx base = NULL_RTX; |
6d36483b | 5061 | |
ecf2283d | 5062 | switch (GET_CODE (XEXP (XEXP (x, 0), 0))) |
87ad11b0 | 5063 | { |
ecf2283d | 5064 | case SYMBOL_REF: |
87ad11b0 | 5065 | base = XEXP (XEXP (x, 0), 0); |
5066 | output_addr_const (file, base); | |
ecf2283d | 5067 | break; |
5068 | case CONST_INT: | |
5069 | offset = INTVAL (XEXP (XEXP (x, 0), 0)); | |
5070 | break; | |
5071 | default: | |
5072 | gcc_unreachable (); | |
87ad11b0 | 5073 | } |
87ad11b0 | 5074 | |
ecf2283d | 5075 | switch (GET_CODE (XEXP (XEXP (x, 0), 1))) |
87ad11b0 | 5076 | { |
ecf2283d | 5077 | case SYMBOL_REF: |
87ad11b0 | 5078 | base = XEXP (XEXP (x, 0), 1); |
5079 | output_addr_const (file, base); | |
ecf2283d | 5080 | break; |
5081 | case CONST_INT: | |
5082 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
5083 | break; | |
5084 | default: | |
5085 | gcc_unreachable (); | |
87ad11b0 | 5086 | } |
87ad11b0 | 5087 | |
f9333726 | 5088 | /* How bogus. The compiler is apparently responsible for |
5089 | rounding the constant if it uses an LR field selector. | |
5090 | ||
5091 | The linker and/or assembler seem a better place since | |
5092 | they have to do this kind of thing already. | |
5093 | ||
5094 | If we fail to do this, HP's optimizing linker may eliminate | |
5095 | an addil, but not update the ldw/stw/ldo instruction that | |
5096 | uses the result of the addil. */ | |
5097 | if (round_constant) | |
5098 | offset = ((offset + 0x1000) & ~0x1fff); | |
5099 | ||
ecf2283d | 5100 | switch (GET_CODE (XEXP (x, 0))) |
87ad11b0 | 5101 | { |
ecf2283d | 5102 | case PLUS: |
87ad11b0 | 5103 | if (offset < 0) |
5104 | { | |
5105 | offset = -offset; | |
5106 | sep = "-"; | |
5107 | } | |
5108 | else | |
5109 | sep = "+"; | |
ecf2283d | 5110 | break; |
5111 | ||
5112 | case MINUS: | |
5113 | gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF); | |
5114 | sep = "-"; | |
5115 | break; | |
87ad11b0 | 5116 | |
ecf2283d | 5117 | default: |
5118 | gcc_unreachable (); | |
5119 | } | |
5120 | ||
611a88e1 | 5121 | if (!read_only_operand (base, VOIDmode) && !flag_pic) |
9c0ac0fd | 5122 | fputs ("-$global$", file); |
f9333726 | 5123 | if (offset) |
ea52c577 | 5124 | fprintf (file, "%s%d", sep, offset); |
87ad11b0 | 5125 | } |
5126 | else | |
5127 | output_addr_const (file, x); | |
5128 | } | |
5129 | ||
92c473b8 | 5130 | /* Output boilerplate text to appear at the beginning of the file. |
5131 | There are several possible versions. */ | |
5132 | #define aputs(x) fputs(x, asm_out_file) | |
5133 | static inline void | |
5c1d8983 | 5134 | pa_file_start_level (void) |
92c473b8 | 5135 | { |
5136 | if (TARGET_64BIT) | |
5137 | aputs ("\t.LEVEL 2.0w\n"); | |
5138 | else if (TARGET_PA_20) | |
5139 | aputs ("\t.LEVEL 2.0\n"); | |
5140 | else if (TARGET_PA_11) | |
5141 | aputs ("\t.LEVEL 1.1\n"); | |
5142 | else | |
5143 | aputs ("\t.LEVEL 1.0\n"); | |
5144 | } | |
5145 | ||
5146 | static inline void | |
5c1d8983 | 5147 | pa_file_start_space (int sortspace) |
92c473b8 | 5148 | { |
5149 | aputs ("\t.SPACE $PRIVATE$"); | |
5150 | if (sortspace) | |
5151 | aputs (",SORT=16"); | |
5152 | aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31" | |
5153 | "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82" | |
5154 | "\n\t.SPACE $TEXT$"); | |
5155 | if (sortspace) | |
5156 | aputs (",SORT=8"); | |
5157 | aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44" | |
5158 | "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n"); | |
5159 | } | |
5160 | ||
5161 | static inline void | |
5c1d8983 | 5162 | pa_file_start_file (int want_version) |
92c473b8 | 5163 | { |
5164 | if (write_symbols != NO_DEBUG) | |
5165 | { | |
5166 | output_file_directive (asm_out_file, main_input_filename); | |
5167 | if (want_version) | |
5168 | aputs ("\t.version\t\"01.01\"\n"); | |
5169 | } | |
5170 | } | |
5171 | ||
5172 | static inline void | |
5c1d8983 | 5173 | pa_file_start_mcount (const char *aswhat) |
92c473b8 | 5174 | { |
5175 | if (profile_flag) | |
5176 | fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat); | |
5177 | } | |
5178 | ||
5179 | static void | |
5c1d8983 | 5180 | pa_elf_file_start (void) |
92c473b8 | 5181 | { |
5182 | pa_file_start_level (); | |
5183 | pa_file_start_mcount ("ENTRY"); | |
5184 | pa_file_start_file (0); | |
5185 | } | |
5186 | ||
5187 | static void | |
5c1d8983 | 5188 | pa_som_file_start (void) |
92c473b8 | 5189 | { |
5190 | pa_file_start_level (); | |
5191 | pa_file_start_space (0); | |
5192 | aputs ("\t.IMPORT $global$,DATA\n" | |
5193 | "\t.IMPORT $$dyncall,MILLICODE\n"); | |
5194 | pa_file_start_mcount ("CODE"); | |
5195 | pa_file_start_file (0); | |
5196 | } | |
5197 | ||
5198 | static void | |
5c1d8983 | 5199 | pa_linux_file_start (void) |
92c473b8 | 5200 | { |
5201 | pa_file_start_file (1); | |
5202 | pa_file_start_level (); | |
5203 | pa_file_start_mcount ("CODE"); | |
5204 | } | |
5205 | ||
5206 | static void | |
5c1d8983 | 5207 | pa_hpux64_gas_file_start (void) |
92c473b8 | 5208 | { |
5209 | pa_file_start_level (); | |
5210 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
5211 | if (profile_flag) | |
5212 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function"); | |
5213 | #endif | |
5214 | pa_file_start_file (1); | |
5215 | } | |
5216 | ||
5217 | static void | |
5c1d8983 | 5218 | pa_hpux64_hpas_file_start (void) |
92c473b8 | 5219 | { |
5220 | pa_file_start_level (); | |
5221 | pa_file_start_space (1); | |
5222 | pa_file_start_mcount ("CODE"); | |
5223 | pa_file_start_file (0); | |
5224 | } | |
5225 | #undef aputs | |
5226 | ||
ece88821 | 5227 | static struct deferred_plabel * |
5f43b4f6 | 5228 | get_plabel (rtx symbol) |
ece88821 | 5229 | { |
5f43b4f6 | 5230 | const char *fname = XSTR (symbol, 0); |
ece88821 | 5231 | size_t i; |
5232 | ||
5233 | /* See if we have already put this function on the list of deferred | |
5234 | plabels. This list is generally small, so a liner search is not | |
5235 | too ugly. If it proves too slow replace it with something faster. */ | |
5236 | for (i = 0; i < n_deferred_plabels; i++) | |
5f43b4f6 | 5237 | if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0) |
ece88821 | 5238 | break; |
5239 | ||
5240 | /* If the deferred plabel list is empty, or this entry was not found | |
5241 | on the list, create a new entry on the list. */ | |
5242 | if (deferred_plabels == NULL || i == n_deferred_plabels) | |
5243 | { | |
5f43b4f6 | 5244 | tree id; |
5245 | ||
ece88821 | 5246 | if (deferred_plabels == 0) |
5247 | deferred_plabels = (struct deferred_plabel *) | |
5248 | ggc_alloc (sizeof (struct deferred_plabel)); | |
5249 | else | |
5250 | deferred_plabels = (struct deferred_plabel *) | |
5251 | ggc_realloc (deferred_plabels, | |
5252 | ((n_deferred_plabels + 1) | |
5253 | * sizeof (struct deferred_plabel))); | |
5254 | ||
5255 | i = n_deferred_plabels++; | |
5256 | deferred_plabels[i].internal_label = gen_label_rtx (); | |
5f43b4f6 | 5257 | deferred_plabels[i].symbol = symbol; |
ece88821 | 5258 | |
5f43b4f6 | 5259 | /* Gross. We have just implicitly taken the address of this |
5260 | function. Mark it in the same manner as assemble_name. */ | |
5261 | id = maybe_get_identifier (targetm.strip_name_encoding (fname)); | |
5262 | if (id) | |
5263 | mark_referenced (id); | |
ece88821 | 5264 | } |
5265 | ||
5266 | return &deferred_plabels[i]; | |
5267 | } | |
5268 | ||
f6940372 | 5269 | static void |
5c1d8983 | 5270 | output_deferred_plabels (void) |
5cc6b2bc | 5271 | { |
e11bd7e5 | 5272 | size_t i; |
5cc6b2bc | 5273 | /* If we have deferred plabels, then we need to switch into the data |
5274 | section and align it to a 4 byte boundary before we output the | |
5275 | deferred plabels. */ | |
5276 | if (n_deferred_plabels) | |
5277 | { | |
5278 | data_section (); | |
f6940372 | 5279 | ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2); |
5cc6b2bc | 5280 | } |
5281 | ||
5282 | /* Now output the deferred plabels. */ | |
5283 | for (i = 0; i < n_deferred_plabels; i++) | |
5284 | { | |
f6940372 | 5285 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
5286 | CODE_LABEL_NUMBER (deferred_plabels[i].internal_label)); | |
5f43b4f6 | 5287 | assemble_integer (deferred_plabels[i].symbol, |
b70ea764 | 5288 | TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1); |
5cc6b2bc | 5289 | } |
5290 | } | |
5291 | ||
f2f543a3 | 5292 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
5293 | /* Initialize optabs to point to HPUX long double emulation routines. */ | |
5294 | static void | |
5295 | pa_hpux_init_libfuncs (void) | |
5296 | { | |
5297 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
5298 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
5299 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
5300 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
5301 | set_optab_libfunc (smin_optab, TFmode, "_U_Qmin"); | |
5302 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
5303 | set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt"); | |
5304 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
5305 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
5306 | ||
c88a6ebd | 5307 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); |
5308 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
5309 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
5310 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
5311 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
5312 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
6b27baea | 5313 | set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord"); |
f2f543a3 | 5314 | |
a7cc195f | 5315 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); |
5316 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
5317 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
5318 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
5319 | ||
5320 | set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT | |
5321 | ? "__U_Qfcnvfxt_quad_to_sgl" | |
5322 | : "_U_Qfcnvfxt_quad_to_sgl"); | |
5323 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl"); | |
5324 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl"); | |
5325 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl"); | |
5326 | ||
5327 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad"); | |
5328 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad"); | |
f2f543a3 | 5329 | } |
5330 | #endif | |
5331 | ||
87ad11b0 | 5332 | /* HP's millicode routines mean something special to the assembler. |
5333 | Keep track of which ones we have used. */ | |
5334 | ||
c2271c34 | 5335 | enum millicodes { remI, remU, divI, divU, mulI, end1000 }; |
5c1d8983 | 5336 | static void import_milli (enum millicodes); |
ea52c577 | 5337 | static char imported[(int) end1000]; |
c2271c34 | 5338 | static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"}; |
e99c3a1d | 5339 | static const char import_string[] = ".IMPORT $$....,MILLICODE"; |
87ad11b0 | 5340 | #define MILLI_START 10 |
5341 | ||
57ed30e5 | 5342 | static void |
5c1d8983 | 5343 | import_milli (enum millicodes code) |
87ad11b0 | 5344 | { |
5345 | char str[sizeof (import_string)]; | |
6d36483b | 5346 | |
ea52c577 | 5347 | if (!imported[(int) code]) |
87ad11b0 | 5348 | { |
ea52c577 | 5349 | imported[(int) code] = 1; |
87ad11b0 | 5350 | strcpy (str, import_string); |
ea52c577 | 5351 | strncpy (str + MILLI_START, milli_names[(int) code], 4); |
87ad11b0 | 5352 | output_asm_insn (str, 0); |
5353 | } | |
5354 | } | |
5355 | ||
6d36483b | 5356 | /* The register constraints have put the operands and return value in |
6dc3b0d9 | 5357 | the proper registers. */ |
87ad11b0 | 5358 | |
611a88e1 | 5359 | const char * |
5c1d8983 | 5360 | output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn) |
87ad11b0 | 5361 | { |
d178f670 | 5362 | import_milli (mulI); |
440c23df | 5363 | return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI")); |
87ad11b0 | 5364 | } |
5365 | ||
6dc3b0d9 | 5366 | /* Emit the rtl for doing a division by a constant. */ |
87ad11b0 | 5367 | |
d178f670 | 5368 | /* Do magic division millicodes exist for this value? */ |
913de4b4 | 5369 | const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1}; |
87ad11b0 | 5370 | |
6d36483b | 5371 | /* We'll use an array to keep track of the magic millicodes and |
87ad11b0 | 5372 | whether or not we've used them already. [n][0] is signed, [n][1] is |
6dc3b0d9 | 5373 | unsigned. */ |
87ad11b0 | 5374 | |
87ad11b0 | 5375 | static int div_milli[16][2]; |
5376 | ||
87ad11b0 | 5377 | int |
5c1d8983 | 5378 | emit_hpdiv_const (rtx *operands, int unsignedp) |
87ad11b0 | 5379 | { |
5380 | if (GET_CODE (operands[2]) == CONST_INT | |
5381 | && INTVAL (operands[2]) > 0 | |
5382 | && INTVAL (operands[2]) < 16 | |
5383 | && magic_milli[INTVAL (operands[2])]) | |
5384 | { | |
2013ddf6 | 5385 | rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31); |
5386 | ||
ad851752 | 5387 | emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]); |
87ad11b0 | 5388 | emit |
75b1a41a | 5389 | (gen_rtx_PARALLEL |
5390 | (VOIDmode, | |
c2078db8 | 5391 | gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29), |
ad851752 | 5392 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, |
5393 | SImode, | |
5394 | gen_rtx_REG (SImode, 26), | |
5395 | operands[2])), | |
c2078db8 | 5396 | gen_rtx_CLOBBER (VOIDmode, operands[4]), |
ad851752 | 5397 | gen_rtx_CLOBBER (VOIDmode, operands[3]), |
5398 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)), | |
5399 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)), | |
2013ddf6 | 5400 | gen_rtx_CLOBBER (VOIDmode, ret)))); |
ad851752 | 5401 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 29)); |
87ad11b0 | 5402 | return 1; |
5403 | } | |
5404 | return 0; | |
5405 | } | |
5406 | ||
611a88e1 | 5407 | const char * |
5c1d8983 | 5408 | output_div_insn (rtx *operands, int unsignedp, rtx insn) |
87ad11b0 | 5409 | { |
5410 | int divisor; | |
6d36483b | 5411 | |
5412 | /* If the divisor is a constant, try to use one of the special | |
87ad11b0 | 5413 | opcodes .*/ |
5414 | if (GET_CODE (operands[0]) == CONST_INT) | |
5415 | { | |
d6686e21 | 5416 | static char buf[100]; |
87ad11b0 | 5417 | divisor = INTVAL (operands[0]); |
5418 | if (!div_milli[divisor][unsignedp]) | |
5419 | { | |
d6686e21 | 5420 | div_milli[divisor][unsignedp] = 1; |
87ad11b0 | 5421 | if (unsignedp) |
5422 | output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands); | |
5423 | else | |
5424 | output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands); | |
87ad11b0 | 5425 | } |
5426 | if (unsignedp) | |
d6686e21 | 5427 | { |
4840a03a | 5428 | sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC, |
5429 | INTVAL (operands[0])); | |
c7a4e712 | 5430 | return output_millicode_call (insn, |
ad851752 | 5431 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5432 | } |
5433 | else | |
5434 | { | |
4840a03a | 5435 | sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC, |
5436 | INTVAL (operands[0])); | |
c7a4e712 | 5437 | return output_millicode_call (insn, |
ad851752 | 5438 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5439 | } |
87ad11b0 | 5440 | } |
6dc3b0d9 | 5441 | /* Divisor isn't a special constant. */ |
87ad11b0 | 5442 | else |
5443 | { | |
5444 | if (unsignedp) | |
5445 | { | |
5446 | import_milli (divU); | |
c7a4e712 | 5447 | return output_millicode_call (insn, |
ad851752 | 5448 | gen_rtx_SYMBOL_REF (SImode, "$$divU")); |
87ad11b0 | 5449 | } |
5450 | else | |
5451 | { | |
5452 | import_milli (divI); | |
c7a4e712 | 5453 | return output_millicode_call (insn, |
ad851752 | 5454 | gen_rtx_SYMBOL_REF (SImode, "$$divI")); |
87ad11b0 | 5455 | } |
5456 | } | |
5457 | } | |
5458 | ||
6dc3b0d9 | 5459 | /* Output a $$rem millicode to do mod. */ |
87ad11b0 | 5460 | |
611a88e1 | 5461 | const char * |
5c1d8983 | 5462 | output_mod_insn (int unsignedp, rtx insn) |
87ad11b0 | 5463 | { |
5464 | if (unsignedp) | |
5465 | { | |
5466 | import_milli (remU); | |
c7a4e712 | 5467 | return output_millicode_call (insn, |
ad851752 | 5468 | gen_rtx_SYMBOL_REF (SImode, "$$remU")); |
87ad11b0 | 5469 | } |
5470 | else | |
5471 | { | |
5472 | import_milli (remI); | |
c7a4e712 | 5473 | return output_millicode_call (insn, |
ad851752 | 5474 | gen_rtx_SYMBOL_REF (SImode, "$$remI")); |
87ad11b0 | 5475 | } |
5476 | } | |
5477 | ||
5478 | void | |
5c1d8983 | 5479 | output_arg_descriptor (rtx call_insn) |
87ad11b0 | 5480 | { |
611a88e1 | 5481 | const char *arg_regs[4]; |
87ad11b0 | 5482 | enum machine_mode arg_mode; |
df0651dc | 5483 | rtx link; |
87ad11b0 | 5484 | int i, output_flag = 0; |
5485 | int regno; | |
6d36483b | 5486 | |
5e3c5739 | 5487 | /* We neither need nor want argument location descriptors for the |
5d0619cc | 5488 | 64bit runtime environment or the ELF32 environment. */ |
5489 | if (TARGET_64BIT || TARGET_ELF32) | |
5e3c5739 | 5490 | return; |
5491 | ||
87ad11b0 | 5492 | for (i = 0; i < 4; i++) |
5493 | arg_regs[i] = 0; | |
5494 | ||
738176ab | 5495 | /* Specify explicitly that no argument relocations should take place |
5496 | if using the portable runtime calling conventions. */ | |
5497 | if (TARGET_PORTABLE_RUNTIME) | |
5498 | { | |
9c0ac0fd | 5499 | fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n", |
5500 | asm_out_file); | |
738176ab | 5501 | return; |
5502 | } | |
5503 | ||
ecf2283d | 5504 | gcc_assert (GET_CODE (call_insn) == CALL_INSN); |
5505 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); | |
5506 | link; link = XEXP (link, 1)) | |
87ad11b0 | 5507 | { |
df0651dc | 5508 | rtx use = XEXP (link, 0); |
c12afafd | 5509 | |
df0651dc | 5510 | if (! (GET_CODE (use) == USE |
5511 | && GET_CODE (XEXP (use, 0)) == REG | |
5512 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
c12afafd | 5513 | continue; |
5514 | ||
df0651dc | 5515 | arg_mode = GET_MODE (XEXP (use, 0)); |
5516 | regno = REGNO (XEXP (use, 0)); | |
87ad11b0 | 5517 | if (regno >= 23 && regno <= 26) |
372ef038 | 5518 | { |
5519 | arg_regs[26 - regno] = "GR"; | |
5520 | if (arg_mode == DImode) | |
5521 | arg_regs[25 - regno] = "GR"; | |
5522 | } | |
df0651dc | 5523 | else if (regno >= 32 && regno <= 39) |
87ad11b0 | 5524 | { |
5525 | if (arg_mode == SFmode) | |
df0651dc | 5526 | arg_regs[(regno - 32) / 2] = "FR"; |
e6ba640e | 5527 | else |
87ad11b0 | 5528 | { |
eeec72c0 | 5529 | #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED |
df0651dc | 5530 | arg_regs[(regno - 34) / 2] = "FR"; |
5531 | arg_regs[(regno - 34) / 2 + 1] = "FU"; | |
87ad11b0 | 5532 | #else |
df0651dc | 5533 | arg_regs[(regno - 34) / 2] = "FU"; |
5534 | arg_regs[(regno - 34) / 2 + 1] = "FR"; | |
87ad11b0 | 5535 | #endif |
5536 | } | |
87ad11b0 | 5537 | } |
5538 | } | |
5539 | fputs ("\t.CALL ", asm_out_file); | |
5540 | for (i = 0; i < 4; i++) | |
5541 | { | |
5542 | if (arg_regs[i]) | |
5543 | { | |
5544 | if (output_flag++) | |
5545 | fputc (',', asm_out_file); | |
5546 | fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]); | |
5547 | } | |
5548 | } | |
5549 | fputc ('\n', asm_out_file); | |
5550 | } | |
5551 | \f | |
9c0ac0fd | 5552 | /* Return the class of any secondary reload register that is needed to |
5553 | move IN into a register in class CLASS using mode MODE. | |
5554 | ||
5555 | Profiling has showed this routine and its descendants account for | |
5556 | a significant amount of compile time (~7%). So it has been | |
5557 | optimized to reduce redundant computations and eliminate useless | |
5558 | function calls. | |
5559 | ||
5560 | It might be worthwhile to try and make this a leaf function too. */ | |
87ad11b0 | 5561 | |
5562 | enum reg_class | |
5c1d8983 | 5563 | secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in) |
87ad11b0 | 5564 | { |
9c0ac0fd | 5565 | int regno, is_symbolic; |
87ad11b0 | 5566 | |
b4a7bf10 | 5567 | /* Trying to load a constant into a FP register during PIC code |
5568 | generation will require %r1 as a scratch register. */ | |
fc44315f | 5569 | if (flag_pic |
b4a7bf10 | 5570 | && GET_MODE_CLASS (mode) == MODE_INT |
5571 | && FP_REG_CLASS_P (class) | |
5572 | && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE)) | |
5573 | return R1_REGS; | |
5574 | ||
9c0ac0fd | 5575 | /* Profiling showed the PA port spends about 1.3% of its compilation |
5576 | time in true_regnum from calls inside secondary_reload_class. */ | |
5577 | ||
5578 | if (GET_CODE (in) == REG) | |
5579 | { | |
5580 | regno = REGNO (in); | |
5581 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5582 | regno = true_regnum (in); | |
5583 | } | |
5584 | else if (GET_CODE (in) == SUBREG) | |
5585 | regno = true_regnum (in); | |
9c0ac0fd | 5586 | else |
5587 | regno = -1; | |
5588 | ||
76a0ced5 | 5589 | /* If we have something like (mem (mem (...)), we can safely assume the |
5590 | inner MEM will end up in a general register after reloading, so there's | |
5591 | no need for a secondary reload. */ | |
5592 | if (GET_CODE (in) == MEM | |
5593 | && GET_CODE (XEXP (in, 0)) == MEM) | |
5594 | return NO_REGS; | |
5595 | ||
5596 | /* Handle out of range displacement for integer mode loads/stores of | |
5597 | FP registers. */ | |
d2498717 | 5598 | if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1) |
6d36483b | 5599 | && GET_MODE_CLASS (mode) == MODE_INT |
5600 | && FP_REG_CLASS_P (class)) | |
d6f01525 | 5601 | || (class == SHIFT_REGS && (regno <= 0 || regno >= 32))) |
9c6d4825 | 5602 | return GENERAL_REGS; |
d2c1d63d | 5603 | |
7c4b32f3 | 5604 | /* A SAR<->FP register copy requires a secondary register (GPR) as |
5605 | well as secondary memory. */ | |
5606 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5607 | && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class)) | |
5608 | || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno))))) | |
5609 | return GENERAL_REGS; | |
5610 | ||
2ee034bc | 5611 | if (GET_CODE (in) == HIGH) |
5612 | in = XEXP (in, 0); | |
5613 | ||
9c0ac0fd | 5614 | /* Profiling has showed GCC spends about 2.6% of its compilation |
5615 | time in symbolic_operand from calls inside secondary_reload_class. | |
5616 | ||
5617 | We use an inline copy and only compute its return value once to avoid | |
5618 | useless work. */ | |
5619 | switch (GET_CODE (in)) | |
5620 | { | |
5621 | rtx tmp; | |
5622 | ||
5623 | case SYMBOL_REF: | |
5624 | case LABEL_REF: | |
5625 | is_symbolic = 1; | |
5626 | break; | |
5627 | case CONST: | |
5628 | tmp = XEXP (in, 0); | |
5629 | is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF | |
5630 | || GET_CODE (XEXP (tmp, 0)) == LABEL_REF) | |
5631 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT); | |
5632 | break; | |
76a0ced5 | 5633 | |
9c0ac0fd | 5634 | default: |
5635 | is_symbolic = 0; | |
5636 | break; | |
5637 | } | |
9840d99d | 5638 | |
b4a7bf10 | 5639 | if (!flag_pic |
9c0ac0fd | 5640 | && is_symbolic |
611a88e1 | 5641 | && read_only_operand (in, VOIDmode)) |
b4a7bf10 | 5642 | return NO_REGS; |
5643 | ||
9c0ac0fd | 5644 | if (class != R1_REGS && is_symbolic) |
2ee034bc | 5645 | return R1_REGS; |
5646 | ||
d2c1d63d | 5647 | return NO_REGS; |
87ad11b0 | 5648 | } |
5649 | ||
b981d932 | 5650 | /* In the 32-bit runtime, arguments larger than eight bytes are passed |
5651 | by invisible reference. As a GCC extension, we also pass anything | |
5652 | with a zero or variable size by reference. | |
5653 | ||
5654 | The 64-bit runtime does not describe passing any types by invisible | |
5655 | reference. The internals of GCC can't currently handle passing | |
5656 | empty structures, and zero or variable length arrays when they are | |
5657 | not passed entirely on the stack or by reference. Thus, as a GCC | |
5658 | extension, we pass these types by reference. The HP compiler doesn't | |
5659 | support these types, so hopefully there shouldn't be any compatibility | |
5660 | issues. This may have to be revisited when HP releases a C99 compiler | |
5661 | or updates the ABI. */ | |
5662 | ||
5663 | static bool | |
5664 | pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, | |
5665 | enum machine_mode mode, tree type, | |
5666 | bool named ATTRIBUTE_UNUSED) | |
5667 | { | |
5668 | HOST_WIDE_INT size; | |
5669 | ||
5670 | if (type) | |
5671 | size = int_size_in_bytes (type); | |
5672 | else | |
5673 | size = GET_MODE_SIZE (mode); | |
5674 | ||
5675 | if (TARGET_64BIT) | |
5676 | return size <= 0; | |
5677 | else | |
5678 | return size <= 0 || size > 8; | |
5679 | } | |
5680 | ||
87ad11b0 | 5681 | enum direction |
5c1d8983 | 5682 | function_arg_padding (enum machine_mode mode, tree type) |
87ad11b0 | 5683 | { |
ac965869 | 5684 | if (mode == BLKmode |
5685 | || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type))) | |
5686 | { | |
5687 | /* Return none if justification is not required. */ | |
5688 | if (type | |
5689 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
5690 | && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0) | |
5691 | return none; | |
5692 | ||
5693 | /* The directions set here are ignored when a BLKmode argument larger | |
5694 | than a word is placed in a register. Different code is used for | |
5695 | the stack and registers. This makes it difficult to have a | |
5696 | consistent data representation for both the stack and registers. | |
5697 | For both runtimes, the justification and padding for arguments on | |
5698 | the stack and in registers should be identical. */ | |
5699 | if (TARGET_64BIT) | |
5700 | /* The 64-bit runtime specifies left justification for aggregates. */ | |
5701 | return upward; | |
87ad11b0 | 5702 | else |
ac965869 | 5703 | /* The 32-bit runtime architecture specifies right justification. |
5704 | When the argument is passed on the stack, the argument is padded | |
5705 | with garbage on the left. The HP compiler pads with zeros. */ | |
5706 | return downward; | |
87ad11b0 | 5707 | } |
ac965869 | 5708 | |
5709 | if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
87ad11b0 | 5710 | return downward; |
87ad11b0 | 5711 | else |
5712 | return none; | |
5713 | } | |
5714 | ||
87ad11b0 | 5715 | \f |
55f54832 | 5716 | /* Do what is necessary for `va_start'. We look at the current function |
5717 | to determine if stdargs or varargs is used and fill in an initial | |
5718 | va_list. A pointer to this constructor is returned. */ | |
87ad11b0 | 5719 | |
b8debbe8 | 5720 | static rtx |
5c1d8983 | 5721 | hppa_builtin_saveregs (void) |
87ad11b0 | 5722 | { |
01251cbc | 5723 | rtx offset, dest; |
87ad11b0 | 5724 | tree fntype = TREE_TYPE (current_function_decl); |
5725 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
5726 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
5727 | != void_type_node))) | |
5728 | ? UNITS_PER_WORD : 0); | |
5729 | ||
5730 | if (argadj) | |
5731 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
5732 | else | |
5733 | offset = current_function_arg_offset_rtx; | |
9c6d4825 | 5734 | |
5e3c5739 | 5735 | if (TARGET_64BIT) |
5736 | { | |
5737 | int i, off; | |
9840d99d | 5738 | |
5e3c5739 | 5739 | /* Adjust for varargs/stdarg differences. */ |
5740 | if (argadj) | |
5741 | offset = plus_constant (current_function_arg_offset_rtx, -argadj); | |
5742 | else | |
5743 | offset = current_function_arg_offset_rtx; | |
5744 | ||
5745 | /* We need to save %r26 .. %r19 inclusive starting at offset -64 | |
5746 | from the incoming arg pointer and growing to larger addresses. */ | |
5747 | for (i = 26, off = -64; i >= 19; i--, off += 8) | |
5748 | emit_move_insn (gen_rtx_MEM (word_mode, | |
5749 | plus_constant (arg_pointer_rtx, off)), | |
5750 | gen_rtx_REG (word_mode, i)); | |
5751 | ||
5752 | /* The incoming args pointer points just beyond the flushback area; | |
8ef587dc | 5753 | normally this is not a serious concern. However, when we are doing |
5e3c5739 | 5754 | varargs/stdargs we want to make the arg pointer point to the start |
5755 | of the incoming argument area. */ | |
5756 | emit_move_insn (virtual_incoming_args_rtx, | |
5757 | plus_constant (arg_pointer_rtx, -64)); | |
5758 | ||
5759 | /* Now return a pointer to the first anonymous argument. */ | |
5760 | return copy_to_reg (expand_binop (Pmode, add_optab, | |
5761 | virtual_incoming_args_rtx, | |
5762 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
5763 | } | |
5764 | ||
6dc3b0d9 | 5765 | /* Store general registers on the stack. */ |
ad851752 | 5766 | dest = gen_rtx_MEM (BLKmode, |
5767 | plus_constant (current_function_internal_arg_pointer, | |
5768 | -16)); | |
ab6ab77e | 5769 | set_mem_alias_set (dest, get_varargs_alias_set ()); |
2a631e19 | 5770 | set_mem_align (dest, BITS_PER_WORD); |
530178a9 | 5771 | move_block_from_reg (23, dest, 4); |
01251cbc | 5772 | |
76a0ced5 | 5773 | /* move_block_from_reg will emit code to store the argument registers |
5774 | individually as scalar stores. | |
5775 | ||
5776 | However, other insns may later load from the same addresses for | |
ad87de1e | 5777 | a structure load (passing a struct to a varargs routine). |
76a0ced5 | 5778 | |
5779 | The alias code assumes that such aliasing can never happen, so we | |
5780 | have to keep memory referencing insns from moving up beyond the | |
5781 | last argument register store. So we emit a blockage insn here. */ | |
5782 | emit_insn (gen_blockage ()); | |
5783 | ||
9c6d4825 | 5784 | return copy_to_reg (expand_binop (Pmode, add_optab, |
5785 | current_function_internal_arg_pointer, | |
5786 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
87ad11b0 | 5787 | } |
d6f01525 | 5788 | |
72899a61 | 5789 | void |
5c1d8983 | 5790 | hppa_va_start (tree valist, rtx nextarg) |
72899a61 | 5791 | { |
5792 | nextarg = expand_builtin_saveregs (); | |
7df226a2 | 5793 | std_expand_builtin_va_start (valist, nextarg); |
72899a61 | 5794 | } |
5795 | ||
4c33eb68 | 5796 | static tree |
5797 | hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p) | |
72899a61 | 5798 | { |
5e3c5739 | 5799 | if (TARGET_64BIT) |
5800 | { | |
4c33eb68 | 5801 | /* Args grow upward. We can use the generic routines. */ |
bef380a4 | 5802 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
72899a61 | 5803 | } |
ac965869 | 5804 | else /* !TARGET_64BIT */ |
72899a61 | 5805 | { |
4c33eb68 | 5806 | tree ptr = build_pointer_type (type); |
5807 | tree valist_type; | |
5808 | tree t, u; | |
5809 | unsigned int size, ofs; | |
bef380a4 | 5810 | bool indirect; |
72899a61 | 5811 | |
bef380a4 | 5812 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0); |
4c33eb68 | 5813 | if (indirect) |
ac965869 | 5814 | { |
4c33eb68 | 5815 | type = ptr; |
5816 | ptr = build_pointer_type (type); | |
72899a61 | 5817 | } |
4c33eb68 | 5818 | size = int_size_in_bytes (type); |
5819 | valist_type = TREE_TYPE (valist); | |
ac965869 | 5820 | |
4c33eb68 | 5821 | /* Args grow down. Not handled by generic routines. */ |
ac965869 | 5822 | |
4c33eb68 | 5823 | u = fold_convert (valist_type, size_in_bytes (type)); |
5824 | t = build (MINUS_EXPR, valist_type, valist, u); | |
ac965869 | 5825 | |
4c33eb68 | 5826 | /* Copied from va-pa.h, but we probably don't need to align to |
5827 | word size, since we generate and preserve that invariant. */ | |
7016c612 | 5828 | u = build_int_cst (valist_type, (size > 4 ? -8 : -4)); |
4c33eb68 | 5829 | t = build (BIT_AND_EXPR, valist_type, t, u); |
5830 | ||
5831 | t = build (MODIFY_EXPR, valist_type, valist, t); | |
72899a61 | 5832 | |
4c33eb68 | 5833 | ofs = (8 - size) % 4; |
5834 | if (ofs != 0) | |
5835 | { | |
5836 | u = fold_convert (valist_type, size_int (ofs)); | |
5837 | t = build (PLUS_EXPR, valist_type, t, u); | |
ac965869 | 5838 | } |
72899a61 | 5839 | |
4c33eb68 | 5840 | t = fold_convert (ptr, t); |
063f5fdd | 5841 | t = build_va_arg_indirect_ref (t); |
72899a61 | 5842 | |
4c33eb68 | 5843 | if (indirect) |
063f5fdd | 5844 | t = build_va_arg_indirect_ref (t); |
72899a61 | 5845 | |
4c33eb68 | 5846 | return t; |
5847 | } | |
5848 | } | |
72899a61 | 5849 | |
2b1e7cc3 | 5850 | /* True if MODE is valid for the target. By "valid", we mean able to |
5851 | be manipulated in non-trivial ways. In particular, this means all | |
5852 | the arithmetic is supported. | |
5853 | ||
5854 | Currently, TImode is not valid as the HP 64-bit runtime documentation | |
5855 | doesn't document the alignment and calling conventions for this type. | |
5856 | Thus, we return false when PRECISION is 2 * BITS_PER_WORD and | |
5857 | 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */ | |
5858 | ||
5859 | static bool | |
5860 | pa_scalar_mode_supported_p (enum machine_mode mode) | |
5861 | { | |
5862 | int precision = GET_MODE_PRECISION (mode); | |
5863 | ||
5864 | switch (GET_MODE_CLASS (mode)) | |
5865 | { | |
5866 | case MODE_PARTIAL_INT: | |
5867 | case MODE_INT: | |
5868 | if (precision == CHAR_TYPE_SIZE) | |
5869 | return true; | |
5870 | if (precision == SHORT_TYPE_SIZE) | |
5871 | return true; | |
5872 | if (precision == INT_TYPE_SIZE) | |
5873 | return true; | |
5874 | if (precision == LONG_TYPE_SIZE) | |
5875 | return true; | |
5876 | if (precision == LONG_LONG_TYPE_SIZE) | |
5877 | return true; | |
5878 | return false; | |
5879 | ||
5880 | case MODE_FLOAT: | |
5881 | if (precision == FLOAT_TYPE_SIZE) | |
5882 | return true; | |
5883 | if (precision == DOUBLE_TYPE_SIZE) | |
5884 | return true; | |
5885 | if (precision == LONG_DOUBLE_TYPE_SIZE) | |
5886 | return true; | |
5887 | return false; | |
5888 | ||
5889 | default: | |
5890 | gcc_unreachable (); | |
5891 | } | |
5892 | } | |
5893 | ||
6d36483b | 5894 | /* This routine handles all the normal conditional branch sequences we |
5895 | might need to generate. It handles compare immediate vs compare | |
5896 | register, nullification of delay slots, varying length branches, | |
0d986529 | 5897 | negated branches, and all combinations of the above. It returns the |
6d36483b | 5898 | output appropriate to emit the branch corresponding to all given |
0d986529 | 5899 | parameters. */ |
5900 | ||
611a88e1 | 5901 | const char * |
5c1d8983 | 5902 | output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn) |
29a4502c | 5903 | { |
0d986529 | 5904 | static char buf[100]; |
5905 | int useskip = 0; | |
e9ec370e | 5906 | rtx xoperands[5]; |
0d986529 | 5907 | |
a361b456 | 5908 | /* A conditional branch to the following instruction (e.g. the delay slot) |
ece0fa59 | 5909 | is asking for a disaster. This can happen when not optimizing and |
5910 | when jump optimization fails. | |
29a4502c | 5911 | |
38efba6c | 5912 | While it is usually safe to emit nothing, this can fail if the |
5913 | preceding instruction is a nullified branch with an empty delay | |
5914 | slot and the same branch target as this branch. We could check | |
5915 | for this but jump optimization should eliminate nop jumps. It | |
5916 | is always safe to emit a nop. */ | |
ece0fa59 | 5917 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
5918 | return "nop"; | |
6d36483b | 5919 | |
22699a7e | 5920 | /* The doubleword form of the cmpib instruction doesn't have the LEU |
5921 | and GTU conditions while the cmpb instruction does. Since we accept | |
5922 | zero for cmpb, we must ensure that we use cmpb for the comparison. */ | |
5923 | if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx) | |
5924 | operands[2] = gen_rtx_REG (DImode, 0); | |
d65b8df8 | 5925 | if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx) |
5926 | operands[1] = gen_rtx_REG (DImode, 0); | |
22699a7e | 5927 | |
5fbd5940 | 5928 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
5929 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 5930 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 5931 | nullify = 1; |
5932 | ||
5933 | /* If this is a short forward conditional branch which did not get | |
5934 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 5935 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 5936 | nullify = forward_branch_p (insn); |
5937 | ||
6d36483b | 5938 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 5939 | comclr instruction. This avoids a single cycle penalty due to |
5940 | mis-predicted branch if we fall through (branch not taken). */ | |
5a1231ef | 5941 | if (length == 4 |
5fbd5940 | 5942 | && next_real_insn (insn) != 0 |
5a1231ef | 5943 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 5944 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 5945 | && nullify) |
5946 | useskip = 1; | |
5947 | ||
5948 | switch (length) | |
5949 | { | |
5fbd5940 | 5950 | /* All short conditional branches except backwards with an unfilled |
5951 | delay slot. */ | |
5a1231ef | 5952 | case 4: |
0d986529 | 5953 | if (useskip) |
e4065f95 | 5954 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
0d986529 | 5955 | else |
e4065f95 | 5956 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 5957 | if (GET_MODE (operands[1]) == DImode) |
5958 | strcat (buf, "*"); | |
0d986529 | 5959 | if (negated) |
5960 | strcat (buf, "%B3"); | |
5961 | else | |
5962 | strcat (buf, "%S3"); | |
5963 | if (useskip) | |
5a811d43 | 5964 | strcat (buf, " %2,%r1,%%r0"); |
0d986529 | 5965 | else if (nullify) |
9e49be0e | 5966 | strcat (buf, ",n %2,%r1,%0"); |
6d36483b | 5967 | else |
9e49be0e | 5968 | strcat (buf, " %2,%r1,%0"); |
0d986529 | 5969 | break; |
5970 | ||
87fcb603 | 5971 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 5972 | unfilled delay slot is treated just like a long backward branch |
5973 | with an unfilled delay slot. */ | |
5a1231ef | 5974 | case 8: |
5fbd5940 | 5975 | /* Handle weird backwards branch with a filled delay slot |
5976 | with is nullified. */ | |
5977 | if (dbr_sequence_length () != 0 | |
5978 | && ! forward_branch_p (insn) | |
5979 | && nullify) | |
5980 | { | |
e4065f95 | 5981 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 5982 | if (GET_MODE (operands[1]) == DImode) |
5983 | strcat (buf, "*"); | |
5fbd5940 | 5984 | if (negated) |
5985 | strcat (buf, "%S3"); | |
5986 | else | |
5987 | strcat (buf, "%B3"); | |
5a811d43 | 5988 | strcat (buf, ",n %2,%r1,.+12\n\tb %0"); |
5fbd5940 | 5989 | } |
43f0c1f2 | 5990 | /* Handle short backwards branch with an unfilled delay slot. |
5991 | Using a comb;nop rather than comiclr;bl saves 1 cycle for both | |
5992 | taken and untaken branches. */ | |
5993 | else if (dbr_sequence_length () == 0 | |
5994 | && ! forward_branch_p (insn) | |
47fc0706 | 5995 | && INSN_ADDRESSES_SET_P () |
5996 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
5997 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 5998 | { |
e4065f95 | 5999 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6000 | if (GET_MODE (operands[1]) == DImode) |
6001 | strcat (buf, "*"); | |
43f0c1f2 | 6002 | if (negated) |
9e49be0e | 6003 | strcat (buf, "%B3 %2,%r1,%0%#"); |
43f0c1f2 | 6004 | else |
9e49be0e | 6005 | strcat (buf, "%S3 %2,%r1,%0%#"); |
43f0c1f2 | 6006 | } |
0d986529 | 6007 | else |
5fbd5940 | 6008 | { |
e4065f95 | 6009 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
5e3c5739 | 6010 | if (GET_MODE (operands[1]) == DImode) |
6011 | strcat (buf, "*"); | |
5fbd5940 | 6012 | if (negated) |
6013 | strcat (buf, "%S3"); | |
6014 | else | |
6015 | strcat (buf, "%B3"); | |
6016 | if (nullify) | |
5a811d43 | 6017 | strcat (buf, " %2,%r1,%%r0\n\tb,n %0"); |
5fbd5940 | 6018 | else |
5a811d43 | 6019 | strcat (buf, " %2,%r1,%%r0\n\tb %0"); |
5fbd5940 | 6020 | } |
0d986529 | 6021 | break; |
6022 | ||
c8a0e52b | 6023 | case 20: |
e9ec370e | 6024 | case 28: |
6025 | xoperands[0] = operands[0]; | |
6026 | xoperands[1] = operands[1]; | |
6027 | xoperands[2] = operands[2]; | |
6028 | xoperands[3] = operands[3]; | |
6029 | ||
6030 | /* The reversed conditional branch must branch over one additional | |
6031 | instruction if the delay slot is filled. If the delay slot | |
6032 | is empty, the instruction after the reversed condition branch | |
6033 | must be nullified. */ | |
6034 | nullify = dbr_sequence_length () == 0; | |
6035 | xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4); | |
c8a0e52b | 6036 | |
6037 | /* Create a reversed conditional branch which branches around | |
6038 | the following insns. */ | |
e9ec370e | 6039 | if (GET_MODE (operands[1]) != DImode) |
6040 | { | |
6041 | if (nullify) | |
6042 | { | |
6043 | if (negated) | |
6044 | strcpy (buf, | |
6045 | "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}"); | |
6046 | else | |
6047 | strcpy (buf, | |
6048 | "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}"); | |
6049 | } | |
6050 | else | |
6051 | { | |
6052 | if (negated) | |
6053 | strcpy (buf, | |
6054 | "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}"); | |
6055 | else | |
6056 | strcpy (buf, | |
6057 | "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}"); | |
6058 | } | |
6059 | } | |
c8a0e52b | 6060 | else |
5e3c5739 | 6061 | { |
e9ec370e | 6062 | if (nullify) |
6063 | { | |
6064 | if (negated) | |
6065 | strcpy (buf, | |
6066 | "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}"); | |
6067 | else | |
6068 | strcpy (buf, | |
6069 | "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}"); | |
6070 | } | |
5e3c5739 | 6071 | else |
e9ec370e | 6072 | { |
6073 | if (negated) | |
6074 | strcpy (buf, | |
6075 | "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}"); | |
6076 | else | |
6077 | strcpy (buf, | |
6078 | "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}"); | |
6079 | } | |
5e3c5739 | 6080 | } |
c8a0e52b | 6081 | |
e9ec370e | 6082 | output_asm_insn (buf, xoperands); |
6083 | return output_lbranch (operands[0], insn); | |
c8a0e52b | 6084 | |
e9ec370e | 6085 | default: |
ecf2283d | 6086 | gcc_unreachable (); |
e9ec370e | 6087 | } |
6088 | return buf; | |
6089 | } | |
c8a0e52b | 6090 | |
e9ec370e | 6091 | /* This routine handles long unconditional branches that exceed the |
6092 | maximum range of a simple branch instruction. */ | |
c8a0e52b | 6093 | |
e9ec370e | 6094 | const char * |
5c1d8983 | 6095 | output_lbranch (rtx dest, rtx insn) |
e9ec370e | 6096 | { |
6097 | rtx xoperands[2]; | |
6098 | ||
6099 | xoperands[0] = dest; | |
c8a0e52b | 6100 | |
e9ec370e | 6101 | /* First, free up the delay slot. */ |
6102 | if (dbr_sequence_length () != 0) | |
6103 | { | |
6104 | /* We can't handle a jump in the delay slot. */ | |
ecf2283d | 6105 | gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN); |
c8a0e52b | 6106 | |
e9ec370e | 6107 | final_scan_insn (NEXT_INSN (insn), asm_out_file, |
4bf029b0 | 6108 | optimize, 0, NULL); |
c8a0e52b | 6109 | |
e9ec370e | 6110 | /* Now delete the delay insn. */ |
6111 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
6112 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
6113 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
6114 | } | |
c8a0e52b | 6115 | |
e9ec370e | 6116 | /* Output an insn to save %r1. The runtime documentation doesn't |
6117 | specify whether the "Clean Up" slot in the callers frame can | |
6118 | be clobbered by the callee. It isn't copied by HP's builtin | |
6119 | alloca, so this suggests that it can be clobbered if necessary. | |
6120 | The "Static Link" location is copied by HP builtin alloca, so | |
6121 | we avoid using it. Using the cleanup slot might be a problem | |
6122 | if we have to interoperate with languages that pass cleanup | |
6123 | information. However, it should be possible to handle these | |
6124 | situations with GCC's asm feature. | |
6125 | ||
6126 | The "Current RP" slot is reserved for the called procedure, so | |
6127 | we try to use it when we don't have a frame of our own. It's | |
6128 | rather unlikely that we won't have a frame when we need to emit | |
6129 | a very long branch. | |
6130 | ||
6131 | Really the way to go long term is a register scavenger; goto | |
6132 | the target of the jump and find a register which we can use | |
6133 | as a scratch to hold the value in %r1. Then, we wouldn't have | |
6134 | to free up the delay slot or clobber a slot that may be needed | |
6135 | for other purposes. */ | |
6136 | if (TARGET_64BIT) | |
6137 | { | |
6138 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6139 | /* Use the return pointer slot in the frame marker. */ | |
6140 | output_asm_insn ("std %%r1,-16(%%r30)", xoperands); | |
6141 | else | |
6142 | /* Use the slot at -40 in the frame marker since HP builtin | |
6143 | alloca doesn't copy it. */ | |
6144 | output_asm_insn ("std %%r1,-40(%%r30)", xoperands); | |
6145 | } | |
6146 | else | |
6147 | { | |
6148 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6149 | /* Use the return pointer slot in the frame marker. */ | |
6150 | output_asm_insn ("stw %%r1,-20(%%r30)", xoperands); | |
6151 | else | |
6152 | /* Use the "Clean Up" slot in the frame marker. In GCC, | |
6153 | the only other use of this location is for copying a | |
6154 | floating point double argument from a floating-point | |
6155 | register to two general registers. The copy is done | |
19ee40ed | 6156 | as an "atomic" operation when outputting a call, so it |
e9ec370e | 6157 | won't interfere with our using the location here. */ |
6158 | output_asm_insn ("stw %%r1,-12(%%r30)", xoperands); | |
6159 | } | |
b70ea764 | 6160 | |
2247cc5f | 6161 | if (TARGET_PORTABLE_RUNTIME) |
6162 | { | |
6163 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6164 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
6165 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6166 | } | |
6167 | else if (flag_pic) | |
e9ec370e | 6168 | { |
6169 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
6170 | if (TARGET_SOM || !TARGET_GAS) | |
6171 | { | |
6172 | xoperands[1] = gen_label_rtx (); | |
6173 | output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands); | |
6174 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
6175 | CODE_LABEL_NUMBER (xoperands[1])); | |
6176 | output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands); | |
c8a0e52b | 6177 | } |
e9ec370e | 6178 | else |
6179 | { | |
6180 | output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6181 | output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6182 | } | |
6183 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6184 | } | |
6185 | else | |
6186 | /* Now output a very long branch to the original target. */ | |
6187 | output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands); | |
c8a0e52b | 6188 | |
e9ec370e | 6189 | /* Now restore the value of %r1 in the delay slot. */ |
6190 | if (TARGET_64BIT) | |
6191 | { | |
6192 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6193 | return "ldd -16(%%r30),%%r1"; | |
6194 | else | |
6195 | return "ldd -40(%%r30),%%r1"; | |
6196 | } | |
6197 | else | |
6198 | { | |
6199 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6200 | return "ldw -20(%%r30),%%r1"; | |
6201 | else | |
6202 | return "ldw -12(%%r30),%%r1"; | |
5fbd5940 | 6203 | } |
0d986529 | 6204 | } |
6205 | ||
6d36483b | 6206 | /* This routine handles all the branch-on-bit conditional branch sequences we |
0d986529 | 6207 | might need to generate. It handles nullification of delay slots, |
6208 | varying length branches, negated branches and all combinations of the | |
6209 | above. it returns the appropriate output template to emit the branch. */ | |
6210 | ||
611a88e1 | 6211 | const char * |
5c1d8983 | 6212 | output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length, |
6213 | int negated, rtx insn, int which) | |
29a4502c | 6214 | { |
0d986529 | 6215 | static char buf[100]; |
6216 | int useskip = 0; | |
6217 | ||
a361b456 | 6218 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 6219 | asking for a disaster. I do not think this can happen as this pattern |
6d36483b | 6220 | is only used when optimizing; jump optimization should eliminate the |
29a4502c | 6221 | jump. But be prepared just in case. */ |
6d36483b | 6222 | |
ece0fa59 | 6223 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6224 | return "nop"; | |
6d36483b | 6225 | |
5fbd5940 | 6226 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6227 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6228 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6229 | nullify = 1; |
6230 | ||
6231 | /* If this is a short forward conditional branch which did not get | |
6232 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6233 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6234 | nullify = forward_branch_p (insn); |
6235 | ||
6d36483b | 6236 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6237 | extrs instruction. This avoids a single cycle penalty due to |
6238 | mis-predicted branch if we fall through (branch not taken). */ | |
6239 | ||
5a1231ef | 6240 | if (length == 4 |
5fbd5940 | 6241 | && next_real_insn (insn) != 0 |
5a1231ef | 6242 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 6243 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 6244 | && nullify) |
6245 | useskip = 1; | |
6246 | ||
6247 | switch (length) | |
6248 | { | |
6249 | ||
5fbd5940 | 6250 | /* All short conditional branches except backwards with an unfilled |
6251 | delay slot. */ | |
5a1231ef | 6252 | case 4: |
0d986529 | 6253 | if (useskip) |
e4065f95 | 6254 | strcpy (buf, "{extrs,|extrw,s,}"); |
6d36483b | 6255 | else |
0d986529 | 6256 | strcpy (buf, "bb,"); |
5e3c5739 | 6257 | if (useskip && GET_MODE (operands[0]) == DImode) |
6258 | strcpy (buf, "extrd,s,*"); | |
6259 | else if (GET_MODE (operands[0]) == DImode) | |
6260 | strcpy (buf, "bb,*"); | |
0d986529 | 6261 | if ((which == 0 && negated) |
6262 | || (which == 1 && ! negated)) | |
6263 | strcat (buf, ">="); | |
6264 | else | |
6265 | strcat (buf, "<"); | |
6266 | if (useskip) | |
5a811d43 | 6267 | strcat (buf, " %0,%1,1,%%r0"); |
0d986529 | 6268 | else if (nullify && negated) |
6269 | strcat (buf, ",n %0,%1,%3"); | |
6270 | else if (nullify && ! negated) | |
6271 | strcat (buf, ",n %0,%1,%2"); | |
6272 | else if (! nullify && negated) | |
5fbd5940 | 6273 | strcat (buf, "%0,%1,%3"); |
0d986529 | 6274 | else if (! nullify && ! negated) |
5fbd5940 | 6275 | strcat (buf, " %0,%1,%2"); |
0d986529 | 6276 | break; |
6277 | ||
87fcb603 | 6278 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6279 | unfilled delay slot is treated just like a long backward branch |
6280 | with an unfilled delay slot. */ | |
5a1231ef | 6281 | case 8: |
5fbd5940 | 6282 | /* Handle weird backwards branch with a filled delay slot |
6283 | with is nullified. */ | |
6284 | if (dbr_sequence_length () != 0 | |
6285 | && ! forward_branch_p (insn) | |
6286 | && nullify) | |
6287 | { | |
6288 | strcpy (buf, "bb,"); | |
5e3c5739 | 6289 | if (GET_MODE (operands[0]) == DImode) |
6290 | strcat (buf, "*"); | |
5fbd5940 | 6291 | if ((which == 0 && negated) |
6292 | || (which == 1 && ! negated)) | |
6293 | strcat (buf, "<"); | |
6294 | else | |
6295 | strcat (buf, ">="); | |
6296 | if (negated) | |
5a811d43 | 6297 | strcat (buf, ",n %0,%1,.+12\n\tb %3"); |
5fbd5940 | 6298 | else |
5a811d43 | 6299 | strcat (buf, ",n %0,%1,.+12\n\tb %2"); |
5fbd5940 | 6300 | } |
43f0c1f2 | 6301 | /* Handle short backwards branch with an unfilled delay slot. |
6302 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6303 | taken and untaken branches. */ | |
6304 | else if (dbr_sequence_length () == 0 | |
6305 | && ! forward_branch_p (insn) | |
47fc0706 | 6306 | && INSN_ADDRESSES_SET_P () |
6307 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6308 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6309 | { |
6310 | strcpy (buf, "bb,"); | |
5e3c5739 | 6311 | if (GET_MODE (operands[0]) == DImode) |
6312 | strcat (buf, "*"); | |
43f0c1f2 | 6313 | if ((which == 0 && negated) |
6314 | || (which == 1 && ! negated)) | |
6315 | strcat (buf, ">="); | |
6316 | else | |
6317 | strcat (buf, "<"); | |
6318 | if (negated) | |
6319 | strcat (buf, " %0,%1,%3%#"); | |
6320 | else | |
6321 | strcat (buf, " %0,%1,%2%#"); | |
6322 | } | |
0d986529 | 6323 | else |
5fbd5940 | 6324 | { |
e4065f95 | 6325 | strcpy (buf, "{extrs,|extrw,s,}"); |
5e3c5739 | 6326 | if (GET_MODE (operands[0]) == DImode) |
6327 | strcpy (buf, "extrd,s,*"); | |
5fbd5940 | 6328 | if ((which == 0 && negated) |
6329 | || (which == 1 && ! negated)) | |
6330 | strcat (buf, "<"); | |
6331 | else | |
6332 | strcat (buf, ">="); | |
6333 | if (nullify && negated) | |
c6ae275c | 6334 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %3"); |
5fbd5940 | 6335 | else if (nullify && ! negated) |
c6ae275c | 6336 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %2"); |
5fbd5940 | 6337 | else if (negated) |
5a811d43 | 6338 | strcat (buf, " %0,%1,1,%%r0\n\tb %3"); |
6d36483b | 6339 | else |
5a811d43 | 6340 | strcat (buf, " %0,%1,1,%%r0\n\tb %2"); |
5fbd5940 | 6341 | } |
0d986529 | 6342 | break; |
6343 | ||
6344 | default: | |
ecf2283d | 6345 | gcc_unreachable (); |
5fbd5940 | 6346 | } |
0d986529 | 6347 | return buf; |
6348 | } | |
6349 | ||
c7a4e712 | 6350 | /* This routine handles all the branch-on-variable-bit conditional branch |
6351 | sequences we might need to generate. It handles nullification of delay | |
6352 | slots, varying length branches, negated branches and all combinations | |
6353 | of the above. it returns the appropriate output template to emit the | |
6354 | branch. */ | |
6355 | ||
611a88e1 | 6356 | const char * |
5c1d8983 | 6357 | output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length, |
6358 | int negated, rtx insn, int which) | |
c7a4e712 | 6359 | { |
6360 | static char buf[100]; | |
6361 | int useskip = 0; | |
6362 | ||
a361b456 | 6363 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
c7a4e712 | 6364 | asking for a disaster. I do not think this can happen as this pattern |
6365 | is only used when optimizing; jump optimization should eliminate the | |
6366 | jump. But be prepared just in case. */ | |
6367 | ||
ece0fa59 | 6368 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6369 | return "nop"; | |
c7a4e712 | 6370 | |
6371 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6372 | as it can nullify the delay slot and save a nop. */ | |
6373 | if (length == 8 && dbr_sequence_length () == 0) | |
6374 | nullify = 1; | |
6375 | ||
6376 | /* If this is a short forward conditional branch which did not get | |
6377 | its delay slot filled, the delay slot can still be nullified. */ | |
6378 | if (! nullify && length == 4 && dbr_sequence_length () == 0) | |
6379 | nullify = forward_branch_p (insn); | |
6380 | ||
6381 | /* A forward branch over a single nullified insn can be done with a | |
6382 | extrs instruction. This avoids a single cycle penalty due to | |
6383 | mis-predicted branch if we fall through (branch not taken). */ | |
6384 | ||
6385 | if (length == 4 | |
6386 | && next_real_insn (insn) != 0 | |
6387 | && get_attr_length (next_real_insn (insn)) == 4 | |
6388 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) | |
6389 | && nullify) | |
6390 | useskip = 1; | |
6391 | ||
6392 | switch (length) | |
6393 | { | |
6394 | ||
6395 | /* All short conditional branches except backwards with an unfilled | |
6396 | delay slot. */ | |
6397 | case 4: | |
6398 | if (useskip) | |
e4065f95 | 6399 | strcpy (buf, "{vextrs,|extrw,s,}"); |
c7a4e712 | 6400 | else |
e4065f95 | 6401 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6402 | if (useskip && GET_MODE (operands[0]) == DImode) |
e75269fd | 6403 | strcpy (buf, "extrd,s,*"); |
5e3c5739 | 6404 | else if (GET_MODE (operands[0]) == DImode) |
6405 | strcpy (buf, "bb,*"); | |
c7a4e712 | 6406 | if ((which == 0 && negated) |
6407 | || (which == 1 && ! negated)) | |
6408 | strcat (buf, ">="); | |
6409 | else | |
6410 | strcat (buf, "<"); | |
6411 | if (useskip) | |
e4065f95 | 6412 | strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}"); |
c7a4e712 | 6413 | else if (nullify && negated) |
e4065f95 | 6414 | strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}"); |
c7a4e712 | 6415 | else if (nullify && ! negated) |
e4065f95 | 6416 | strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}"); |
c7a4e712 | 6417 | else if (! nullify && negated) |
e4065f95 | 6418 | strcat (buf, "{%0,%3|%0,%%sar,%3}"); |
c7a4e712 | 6419 | else if (! nullify && ! negated) |
e4065f95 | 6420 | strcat (buf, "{ %0,%2| %0,%%sar,%2}"); |
c7a4e712 | 6421 | break; |
6422 | ||
87fcb603 | 6423 | /* All long conditionals. Note a short backward branch with an |
c7a4e712 | 6424 | unfilled delay slot is treated just like a long backward branch |
6425 | with an unfilled delay slot. */ | |
6426 | case 8: | |
6427 | /* Handle weird backwards branch with a filled delay slot | |
6428 | with is nullified. */ | |
6429 | if (dbr_sequence_length () != 0 | |
6430 | && ! forward_branch_p (insn) | |
6431 | && nullify) | |
6432 | { | |
e4065f95 | 6433 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6434 | if (GET_MODE (operands[0]) == DImode) |
6435 | strcat (buf, "*"); | |
c7a4e712 | 6436 | if ((which == 0 && negated) |
6437 | || (which == 1 && ! negated)) | |
6438 | strcat (buf, "<"); | |
6439 | else | |
6440 | strcat (buf, ">="); | |
6441 | if (negated) | |
e4065f95 | 6442 | strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}"); |
c7a4e712 | 6443 | else |
e4065f95 | 6444 | strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}"); |
c7a4e712 | 6445 | } |
6446 | /* Handle short backwards branch with an unfilled delay slot. | |
6447 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6448 | taken and untaken branches. */ | |
6449 | else if (dbr_sequence_length () == 0 | |
6450 | && ! forward_branch_p (insn) | |
47fc0706 | 6451 | && INSN_ADDRESSES_SET_P () |
6452 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6453 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
c7a4e712 | 6454 | { |
e4065f95 | 6455 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6456 | if (GET_MODE (operands[0]) == DImode) |
6457 | strcat (buf, "*"); | |
c7a4e712 | 6458 | if ((which == 0 && negated) |
6459 | || (which == 1 && ! negated)) | |
6460 | strcat (buf, ">="); | |
6461 | else | |
6462 | strcat (buf, "<"); | |
6463 | if (negated) | |
e4065f95 | 6464 | strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}"); |
c7a4e712 | 6465 | else |
e4065f95 | 6466 | strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}"); |
c7a4e712 | 6467 | } |
6468 | else | |
6469 | { | |
e4065f95 | 6470 | strcpy (buf, "{vextrs,|extrw,s,}"); |
5e3c5739 | 6471 | if (GET_MODE (operands[0]) == DImode) |
6472 | strcpy (buf, "extrd,s,*"); | |
c7a4e712 | 6473 | if ((which == 0 && negated) |
6474 | || (which == 1 && ! negated)) | |
6475 | strcat (buf, "<"); | |
6476 | else | |
6477 | strcat (buf, ">="); | |
6478 | if (nullify && negated) | |
e4065f95 | 6479 | strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}"); |
c7a4e712 | 6480 | else if (nullify && ! negated) |
e4065f95 | 6481 | strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}"); |
c7a4e712 | 6482 | else if (negated) |
e4065f95 | 6483 | strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}"); |
c7a4e712 | 6484 | else |
e4065f95 | 6485 | strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}"); |
c7a4e712 | 6486 | } |
6487 | break; | |
6488 | ||
6489 | default: | |
ecf2283d | 6490 | gcc_unreachable (); |
c7a4e712 | 6491 | } |
6492 | return buf; | |
6493 | } | |
6494 | ||
29a4502c | 6495 | /* Return the output template for emitting a dbra type insn. |
6496 | ||
6497 | Note it may perform some output operations on its own before | |
6498 | returning the final output string. */ | |
611a88e1 | 6499 | const char * |
5c1d8983 | 6500 | output_dbra (rtx *operands, rtx insn, int which_alternative) |
29a4502c | 6501 | { |
6502 | ||
a361b456 | 6503 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 6504 | asking for a disaster. Be prepared! */ |
6505 | ||
ece0fa59 | 6506 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
29a4502c | 6507 | { |
6508 | if (which_alternative == 0) | |
6509 | return "ldo %1(%0),%0"; | |
6510 | else if (which_alternative == 1) | |
6511 | { | |
ea52c577 | 6512 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands); |
6513 | output_asm_insn ("ldw -16(%%r30),%4", operands); | |
34940871 | 6514 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
e4065f95 | 6515 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6516 | } |
6517 | else | |
6518 | { | |
6519 | output_asm_insn ("ldw %0,%4", operands); | |
6520 | return "ldo %1(%4),%4\n\tstw %4,%0"; | |
6521 | } | |
6522 | } | |
6523 | ||
6524 | if (which_alternative == 0) | |
6525 | { | |
6526 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
6527 | int length = get_attr_length (insn); | |
6528 | ||
6529 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6530 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6531 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 6532 | nullify = 1; |
6533 | ||
6534 | /* If this is a short forward conditional branch which did not get | |
6535 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6536 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 6537 | nullify = forward_branch_p (insn); |
6538 | ||
ecf2283d | 6539 | switch (length) |
29a4502c | 6540 | { |
ecf2283d | 6541 | case 4: |
6542 | if (nullify) | |
6543 | return "addib,%C2,n %1,%0,%3"; | |
6544 | else | |
6545 | return "addib,%C2 %1,%0,%3"; | |
6546 | ||
6547 | case 8: | |
6d36483b | 6548 | /* Handle weird backwards branch with a fulled delay slot |
29a4502c | 6549 | which is nullified. */ |
6550 | if (dbr_sequence_length () != 0 | |
6551 | && ! forward_branch_p (insn) | |
6552 | && nullify) | |
5a811d43 | 6553 | return "addib,%N2,n %1,%0,.+12\n\tb %3"; |
43f0c1f2 | 6554 | /* Handle short backwards branch with an unfilled delay slot. |
6555 | Using a addb;nop rather than addi;bl saves 1 cycle for both | |
6556 | taken and untaken branches. */ | |
6557 | else if (dbr_sequence_length () == 0 | |
6558 | && ! forward_branch_p (insn) | |
47fc0706 | 6559 | && INSN_ADDRESSES_SET_P () |
6560 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6561 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6562 | return "addib,%C2 %1,%0,%3%#"; |
6d36483b | 6563 | |
6564 | /* Handle normal cases. */ | |
29a4502c | 6565 | if (nullify) |
5a811d43 | 6566 | return "addi,%N2 %1,%0,%0\n\tb,n %3"; |
29a4502c | 6567 | else |
5a811d43 | 6568 | return "addi,%N2 %1,%0,%0\n\tb %3"; |
ecf2283d | 6569 | |
6570 | default: | |
6571 | gcc_unreachable (); | |
29a4502c | 6572 | } |
ecf2283d | 6573 | |
29a4502c | 6574 | } |
6575 | /* Deal with gross reload from FP register case. */ | |
6576 | else if (which_alternative == 1) | |
6577 | { | |
6578 | /* Move loop counter from FP register to MEM then into a GR, | |
6579 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 6580 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 6581 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4", |
6582 | operands); | |
34940871 | 6583 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
5a1231ef | 6584 | if (get_attr_length (insn) == 24) |
e4065f95 | 6585 | return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6586 | else |
e4065f95 | 6587 | return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6588 | } |
6589 | /* Deal with gross reload from memory case. */ | |
6590 | else | |
6591 | { | |
6592 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 6593 | happens in the branch's delay slot. */ |
29a4502c | 6594 | output_asm_insn ("ldw %0,%4", operands); |
5a1231ef | 6595 | if (get_attr_length (insn) == 12) |
29a4502c | 6596 | return "addib,%C2 %1,%4,%3\n\tstw %4,%0"; |
6597 | else | |
5a811d43 | 6598 | return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0"; |
29a4502c | 6599 | } |
6600 | } | |
6601 | ||
6602 | /* Return the output template for emitting a dbra type insn. | |
6603 | ||
6604 | Note it may perform some output operations on its own before | |
6605 | returning the final output string. */ | |
611a88e1 | 6606 | const char * |
5c1d8983 | 6607 | output_movb (rtx *operands, rtx insn, int which_alternative, |
6608 | int reverse_comparison) | |
29a4502c | 6609 | { |
6610 | ||
a361b456 | 6611 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 6612 | asking for a disaster. Be prepared! */ |
6613 | ||
ece0fa59 | 6614 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
29a4502c | 6615 | { |
6616 | if (which_alternative == 0) | |
6617 | return "copy %1,%0"; | |
6618 | else if (which_alternative == 1) | |
6619 | { | |
ea52c577 | 6620 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
e4065f95 | 6621 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6622 | } |
546a40bd | 6623 | else if (which_alternative == 2) |
29a4502c | 6624 | return "stw %1,%0"; |
546a40bd | 6625 | else |
6626 | return "mtsar %r1"; | |
29a4502c | 6627 | } |
6628 | ||
6629 | /* Support the second variant. */ | |
6630 | if (reverse_comparison) | |
6631 | PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2]))); | |
6632 | ||
6633 | if (which_alternative == 0) | |
6634 | { | |
6635 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
6636 | int length = get_attr_length (insn); | |
6637 | ||
6638 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6639 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6640 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 6641 | nullify = 1; |
6642 | ||
6643 | /* If this is a short forward conditional branch which did not get | |
6644 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6645 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 6646 | nullify = forward_branch_p (insn); |
6647 | ||
ecf2283d | 6648 | switch (length) |
29a4502c | 6649 | { |
ecf2283d | 6650 | case 4: |
6651 | if (nullify) | |
6652 | return "movb,%C2,n %1,%0,%3"; | |
6653 | else | |
6654 | return "movb,%C2 %1,%0,%3"; | |
6655 | ||
6656 | case 8: | |
6d36483b | 6657 | /* Handle weird backwards branch with a filled delay slot |
29a4502c | 6658 | which is nullified. */ |
6659 | if (dbr_sequence_length () != 0 | |
6660 | && ! forward_branch_p (insn) | |
6661 | && nullify) | |
5a811d43 | 6662 | return "movb,%N2,n %1,%0,.+12\n\tb %3"; |
6d36483b | 6663 | |
43f0c1f2 | 6664 | /* Handle short backwards branch with an unfilled delay slot. |
6665 | Using a movb;nop rather than or;bl saves 1 cycle for both | |
6666 | taken and untaken branches. */ | |
6667 | else if (dbr_sequence_length () == 0 | |
6668 | && ! forward_branch_p (insn) | |
47fc0706 | 6669 | && INSN_ADDRESSES_SET_P () |
6670 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6671 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6672 | return "movb,%C2 %1,%0,%3%#"; |
6d36483b | 6673 | /* Handle normal cases. */ |
29a4502c | 6674 | if (nullify) |
5a811d43 | 6675 | return "or,%N2 %1,%%r0,%0\n\tb,n %3"; |
29a4502c | 6676 | else |
5a811d43 | 6677 | return "or,%N2 %1,%%r0,%0\n\tb %3"; |
ecf2283d | 6678 | |
6679 | default: | |
6680 | gcc_unreachable (); | |
29a4502c | 6681 | } |
29a4502c | 6682 | } |
6683 | /* Deal with gross reload from FP register case. */ | |
6684 | else if (which_alternative == 1) | |
6685 | { | |
6686 | /* Move loop counter from FP register to MEM then into a GR, | |
6687 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 6688 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 6689 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
5a1231ef | 6690 | if (get_attr_length (insn) == 12) |
e4065f95 | 6691 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6692 | else |
e4065f95 | 6693 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6694 | } |
6695 | /* Deal with gross reload from memory case. */ | |
546a40bd | 6696 | else if (which_alternative == 2) |
29a4502c | 6697 | { |
6698 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 6699 | happens in the branch's delay slot. */ |
5a1231ef | 6700 | if (get_attr_length (insn) == 8) |
e4065f95 | 6701 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0"; |
29a4502c | 6702 | else |
e4065f95 | 6703 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0"; |
29a4502c | 6704 | } |
546a40bd | 6705 | /* Handle SAR as a destination. */ |
6706 | else | |
6707 | { | |
6708 | if (get_attr_length (insn) == 8) | |
e4065f95 | 6709 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1"; |
546a40bd | 6710 | else |
be7770ad | 6711 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1"; |
546a40bd | 6712 | } |
29a4502c | 6713 | } |
6714 | ||
ece88821 | 6715 | /* Copy any FP arguments in INSN into integer registers. */ |
6716 | static void | |
5c1d8983 | 6717 | copy_fp_args (rtx insn) |
ece88821 | 6718 | { |
6719 | rtx link; | |
6720 | rtx xoperands[2]; | |
29a4502c | 6721 | |
ece88821 | 6722 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
6723 | { | |
6724 | int arg_mode, regno; | |
6725 | rtx use = XEXP (link, 0); | |
3683f840 | 6726 | |
ece88821 | 6727 | if (! (GET_CODE (use) == USE |
6728 | && GET_CODE (XEXP (use, 0)) == REG | |
6729 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
6730 | continue; | |
d6686e21 | 6731 | |
ece88821 | 6732 | arg_mode = GET_MODE (XEXP (use, 0)); |
6733 | regno = REGNO (XEXP (use, 0)); | |
5e3c5739 | 6734 | |
ece88821 | 6735 | /* Is it a floating point register? */ |
6736 | if (regno >= 32 && regno <= 39) | |
6737 | { | |
6738 | /* Copy the FP register into an integer register via memory. */ | |
6739 | if (arg_mode == SFmode) | |
6740 | { | |
6741 | xoperands[0] = XEXP (use, 0); | |
6742 | xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2); | |
6743 | output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands); | |
6744 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
6745 | } | |
6746 | else | |
6747 | { | |
6748 | xoperands[0] = XEXP (use, 0); | |
6749 | xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2); | |
6750 | output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands); | |
6751 | output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands); | |
6752 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
6753 | } | |
6754 | } | |
06ddb6f8 | 6755 | } |
ece88821 | 6756 | } |
6757 | ||
6758 | /* Compute length of the FP argument copy sequence for INSN. */ | |
6759 | static int | |
5c1d8983 | 6760 | length_fp_args (rtx insn) |
ece88821 | 6761 | { |
6762 | int length = 0; | |
6763 | rtx link; | |
06ddb6f8 | 6764 | |
ece88821 | 6765 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
c7a4e712 | 6766 | { |
ece88821 | 6767 | int arg_mode, regno; |
6768 | rtx use = XEXP (link, 0); | |
6769 | ||
6770 | if (! (GET_CODE (use) == USE | |
6771 | && GET_CODE (XEXP (use, 0)) == REG | |
6772 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
6773 | continue; | |
c7a4e712 | 6774 | |
ece88821 | 6775 | arg_mode = GET_MODE (XEXP (use, 0)); |
6776 | regno = REGNO (XEXP (use, 0)); | |
6777 | ||
6778 | /* Is it a floating point register? */ | |
6779 | if (regno >= 32 && regno <= 39) | |
c7a4e712 | 6780 | { |
ece88821 | 6781 | if (arg_mode == SFmode) |
6782 | length += 8; | |
6783 | else | |
6784 | length += 12; | |
c7a4e712 | 6785 | } |
ece88821 | 6786 | } |
c7a4e712 | 6787 | |
ece88821 | 6788 | return length; |
6789 | } | |
b70ea764 | 6790 | |
cd0dfcc5 | 6791 | /* Return the attribute length for the millicode call instruction INSN. |
6792 | The length must match the code generated by output_millicode_call. | |
6793 | We include the delay slot in the returned length as it is better to | |
ece88821 | 6794 | over estimate the length than to under estimate it. */ |
b29897dd | 6795 | |
ece88821 | 6796 | int |
5c1d8983 | 6797 | attr_length_millicode_call (rtx insn) |
ece88821 | 6798 | { |
cd0dfcc5 | 6799 | unsigned long distance = -1; |
8a05c3c2 | 6800 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
ece88821 | 6801 | |
cd0dfcc5 | 6802 | if (INSN_ADDRESSES_SET_P ()) |
6803 | { | |
2247cc5f | 6804 | distance = (total + insn_current_reference_address (insn)); |
6805 | if (distance < total) | |
cd0dfcc5 | 6806 | distance = -1; |
6807 | } | |
ece88821 | 6808 | |
6809 | if (TARGET_64BIT) | |
6810 | { | |
6811 | if (!TARGET_LONG_CALLS && distance < 7600000) | |
cd0dfcc5 | 6812 | return 8; |
ece88821 | 6813 | |
cd0dfcc5 | 6814 | return 20; |
ece88821 | 6815 | } |
6816 | else if (TARGET_PORTABLE_RUNTIME) | |
cd0dfcc5 | 6817 | return 24; |
ece88821 | 6818 | else |
6819 | { | |
6820 | if (!TARGET_LONG_CALLS && distance < 240000) | |
cd0dfcc5 | 6821 | return 8; |
ece88821 | 6822 | |
6823 | if (TARGET_LONG_ABS_CALL && !flag_pic) | |
cd0dfcc5 | 6824 | return 12; |
ece88821 | 6825 | |
cd0dfcc5 | 6826 | return 24; |
ece88821 | 6827 | } |
6828 | } | |
6829 | ||
6830 | /* INSN is a function call. It may have an unconditional jump | |
6831 | in its delay slot. | |
b29897dd | 6832 | |
ece88821 | 6833 | CALL_DEST is the routine we are calling. */ |
b29897dd | 6834 | |
ece88821 | 6835 | const char * |
5c1d8983 | 6836 | output_millicode_call (rtx insn, rtx call_dest) |
ece88821 | 6837 | { |
6838 | int attr_length = get_attr_length (insn); | |
6839 | int seq_length = dbr_sequence_length (); | |
6840 | int distance; | |
6841 | rtx seq_insn; | |
6842 | rtx xoperands[3]; | |
b29897dd | 6843 | |
ece88821 | 6844 | xoperands[0] = call_dest; |
6845 | xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31); | |
6846 | ||
6847 | /* Handle the common case where we are sure that the branch will | |
6848 | reach the beginning of the $CODE$ subspace. The within reach | |
6849 | form of the $$sh_func_adrs call has a length of 28. Because | |
a8b24921 | 6850 | it has an attribute type of multi, it never has a nonzero |
ece88821 | 6851 | sequence length. The length of the $$sh_func_adrs is the same |
6852 | as certain out of reach PIC calls to other routines. */ | |
6853 | if (!TARGET_LONG_CALLS | |
6854 | && ((seq_length == 0 | |
6855 | && (attr_length == 12 | |
6856 | || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI))) | |
6857 | || (seq_length != 0 && attr_length == 8))) | |
6858 | { | |
6859 | output_asm_insn ("{bl|b,l} %0,%2", xoperands); | |
6860 | } | |
6861 | else | |
6862 | { | |
6863 | if (TARGET_64BIT) | |
6864 | { | |
6865 | /* It might seem that one insn could be saved by accessing | |
6866 | the millicode function using the linkage table. However, | |
6867 | this doesn't work in shared libraries and other dynamically | |
6868 | loaded objects. Using a pc-relative sequence also avoids | |
6869 | problems related to the implicit use of the gp register. */ | |
6870 | output_asm_insn ("b,l .+8,%%r1", xoperands); | |
9bd9af5d | 6871 | |
6872 | if (TARGET_GAS) | |
6873 | { | |
6874 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6875 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6876 | } | |
6877 | else | |
6878 | { | |
6879 | xoperands[1] = gen_label_rtx (); | |
6880 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
805e22b2 | 6881 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
9bd9af5d | 6882 | CODE_LABEL_NUMBER (xoperands[1])); |
6883 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
6884 | } | |
6885 | ||
ece88821 | 6886 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); |
c7a4e712 | 6887 | } |
c7a4e712 | 6888 | else if (TARGET_PORTABLE_RUNTIME) |
6889 | { | |
ece88821 | 6890 | /* Pure portable runtime doesn't allow be/ble; we also don't |
6891 | have PIC support in the assembler/linker, so this sequence | |
6892 | is needed. */ | |
c7a4e712 | 6893 | |
ece88821 | 6894 | /* Get the address of our target into %r1. */ |
6895 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6896 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
c7a4e712 | 6897 | |
ece88821 | 6898 | /* Get our return address into %r31. */ |
6899 | output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands); | |
6900 | output_asm_insn ("addi 8,%%r31,%%r31", xoperands); | |
c7a4e712 | 6901 | |
ece88821 | 6902 | /* Jump to our target address in %r1. */ |
6903 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 6904 | } |
ece88821 | 6905 | else if (!flag_pic) |
c7a4e712 | 6906 | { |
ece88821 | 6907 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
356267e0 | 6908 | if (TARGET_PA_20) |
ece88821 | 6909 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands); |
356267e0 | 6910 | else |
ece88821 | 6911 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); |
c7a4e712 | 6912 | } |
ece88821 | 6913 | else |
c7a4e712 | 6914 | { |
9bd9af5d | 6915 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
6916 | output_asm_insn ("addi 16,%%r1,%%r31", xoperands); | |
6917 | ||
ece88821 | 6918 | if (TARGET_SOM || !TARGET_GAS) |
6919 | { | |
6920 | /* The HP assembler can generate relocations for the | |
6921 | difference of two symbols. GAS can do this for a | |
6922 | millicode symbol but not an arbitrary external | |
6923 | symbol when generating SOM output. */ | |
6924 | xoperands[1] = gen_label_rtx (); | |
805e22b2 | 6925 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
ece88821 | 6926 | CODE_LABEL_NUMBER (xoperands[1])); |
6927 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
6928 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
6929 | } | |
6930 | else | |
6931 | { | |
ece88821 | 6932 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands); |
6933 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1", | |
6934 | xoperands); | |
6935 | } | |
c7a4e712 | 6936 | |
ece88821 | 6937 | /* Jump to our target address in %r1. */ |
6938 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 6939 | } |
c7a4e712 | 6940 | } |
6941 | ||
ece88821 | 6942 | if (seq_length == 0) |
6943 | output_asm_insn ("nop", xoperands); | |
c7a4e712 | 6944 | |
ece88821 | 6945 | /* We are done if there isn't a jump in the delay slot. */ |
6946 | if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
6947 | return ""; | |
c7a4e712 | 6948 | |
ece88821 | 6949 | /* This call has an unconditional jump in its delay slot. */ |
6950 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
c7a4e712 | 6951 | |
ece88821 | 6952 | /* See if the return address can be adjusted. Use the containing |
6953 | sequence insn's address. */ | |
cd0dfcc5 | 6954 | if (INSN_ADDRESSES_SET_P ()) |
c7a4e712 | 6955 | { |
cd0dfcc5 | 6956 | seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); |
6957 | distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
6958 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
6959 | ||
6960 | if (VAL_14_BITS_P (distance)) | |
6961 | { | |
6962 | xoperands[1] = gen_label_rtx (); | |
6963 | output_asm_insn ("ldo %0-%1(%2),%2", xoperands); | |
6964 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
6965 | CODE_LABEL_NUMBER (xoperands[1])); | |
6966 | } | |
6967 | else | |
6968 | /* ??? This branch may not reach its target. */ | |
6969 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 6970 | } |
ece88821 | 6971 | else |
6972 | /* ??? This branch may not reach its target. */ | |
6973 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 6974 | |
6975 | /* Delete the jump. */ | |
6976 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
6977 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
6978 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
ece88821 | 6979 | |
c7a4e712 | 6980 | return ""; |
6981 | } | |
6982 | ||
cd0dfcc5 | 6983 | /* Return the attribute length of the call instruction INSN. The SIBCALL |
6984 | flag indicates whether INSN is a regular call or a sibling call. The | |
faf3f8c1 | 6985 | length returned must be longer than the code actually generated by |
6986 | output_call. Since branch shortening is done before delay branch | |
6987 | sequencing, there is no way to determine whether or not the delay | |
6988 | slot will be filled during branch shortening. Even when the delay | |
6989 | slot is filled, we may have to add a nop if the delay slot contains | |
6990 | a branch that can't reach its target. Thus, we always have to include | |
6991 | the delay slot in the length estimate. This used to be done in | |
6992 | pa_adjust_insn_length but we do it here now as some sequences always | |
6993 | fill the delay slot and we can save four bytes in the estimate for | |
6994 | these sequences. */ | |
ece88821 | 6995 | |
6996 | int | |
5c1d8983 | 6997 | attr_length_call (rtx insn, int sibcall) |
ece88821 | 6998 | { |
faf3f8c1 | 6999 | int local_call; |
7000 | rtx call_dest; | |
7001 | tree call_decl; | |
7002 | int length = 0; | |
7003 | rtx pat = PATTERN (insn); | |
cd0dfcc5 | 7004 | unsigned long distance = -1; |
ece88821 | 7005 | |
cd0dfcc5 | 7006 | if (INSN_ADDRESSES_SET_P ()) |
7007 | { | |
faf3f8c1 | 7008 | unsigned long total; |
7009 | ||
7010 | total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; | |
2247cc5f | 7011 | distance = (total + insn_current_reference_address (insn)); |
7012 | if (distance < total) | |
cd0dfcc5 | 7013 | distance = -1; |
7014 | } | |
ece88821 | 7015 | |
faf3f8c1 | 7016 | /* Determine if this is a local call. */ |
7017 | if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL) | |
7018 | call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0); | |
ece88821 | 7019 | else |
faf3f8c1 | 7020 | call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0); |
ece88821 | 7021 | |
faf3f8c1 | 7022 | call_decl = SYMBOL_REF_DECL (call_dest); |
7023 | local_call = call_decl && (*targetm.binds_local_p) (call_decl); | |
ece88821 | 7024 | |
faf3f8c1 | 7025 | /* pc-relative branch. */ |
7026 | if (!TARGET_LONG_CALLS | |
7027 | && ((TARGET_PA_20 && !sibcall && distance < 7600000) | |
7028 | || distance < 240000)) | |
7029 | length += 8; | |
ece88821 | 7030 | |
faf3f8c1 | 7031 | /* 64-bit plabel sequence. */ |
7032 | else if (TARGET_64BIT && !local_call) | |
7033 | length += sibcall ? 28 : 24; | |
ece88821 | 7034 | |
faf3f8c1 | 7035 | /* non-pic long absolute branch sequence. */ |
7036 | else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) | |
7037 | length += 12; | |
ece88821 | 7038 | |
faf3f8c1 | 7039 | /* long pc-relative branch sequence. */ |
7040 | else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) | |
7041 | || (TARGET_64BIT && !TARGET_GAS) | |
7042 | || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))) | |
7043 | { | |
7044 | length += 20; | |
ece88821 | 7045 | |
faf3f8c1 | 7046 | if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS) |
7047 | length += 8; | |
7048 | } | |
8a05c3c2 | 7049 | |
faf3f8c1 | 7050 | /* 32-bit plabel sequence. */ |
7051 | else | |
7052 | { | |
7053 | length += 32; | |
ece88821 | 7054 | |
faf3f8c1 | 7055 | if (TARGET_SOM) |
7056 | length += length_fp_args (insn); | |
7057 | ||
7058 | if (flag_pic) | |
7059 | length += 4; | |
ee376abe | 7060 | |
faf3f8c1 | 7061 | if (!TARGET_PA_20) |
7062 | { | |
ece88821 | 7063 | if (!sibcall) |
7064 | length += 8; | |
7065 | ||
faf3f8c1 | 7066 | if (!TARGET_NO_SPACE_REGS) |
7067 | length += 8; | |
ece88821 | 7068 | } |
7069 | } | |
faf3f8c1 | 7070 | |
7071 | return length; | |
ece88821 | 7072 | } |
7073 | ||
7074 | /* INSN is a function call. It may have an unconditional jump | |
c7a4e712 | 7075 | in its delay slot. |
7076 | ||
7077 | CALL_DEST is the routine we are calling. */ | |
7078 | ||
611a88e1 | 7079 | const char * |
5c1d8983 | 7080 | output_call (rtx insn, rtx call_dest, int sibcall) |
c7a4e712 | 7081 | { |
ece88821 | 7082 | int delay_insn_deleted = 0; |
7083 | int delay_slot_filled = 0; | |
b70ea764 | 7084 | int seq_length = dbr_sequence_length (); |
2247cc5f | 7085 | tree call_decl = SYMBOL_REF_DECL (call_dest); |
faf3f8c1 | 7086 | int local_call = call_decl && (*targetm.binds_local_p) (call_decl); |
ece88821 | 7087 | rtx xoperands[2]; |
7088 | ||
7089 | xoperands[0] = call_dest; | |
c7a4e712 | 7090 | |
ece88821 | 7091 | /* Handle the common case where we're sure that the branch will reach |
2247cc5f | 7092 | the beginning of the "$CODE$" subspace. This is the beginning of |
7093 | the current function if we are in a named section. */ | |
cd0dfcc5 | 7094 | if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8) |
d6686e21 | 7095 | { |
5e3c5739 | 7096 | xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2); |
ece88821 | 7097 | output_asm_insn ("{bl|b,l} %0,%1", xoperands); |
06ddb6f8 | 7098 | } |
ece88821 | 7099 | else |
06ddb6f8 | 7100 | { |
2247cc5f | 7101 | if (TARGET_64BIT && !local_call) |
3683f840 | 7102 | { |
ece88821 | 7103 | /* ??? As far as I can tell, the HP linker doesn't support the |
7104 | long pc-relative sequence described in the 64-bit runtime | |
7105 | architecture. So, we use a slightly longer indirect call. */ | |
5f43b4f6 | 7106 | struct deferred_plabel *p = get_plabel (call_dest); |
ece88821 | 7107 | |
7108 | xoperands[0] = p->internal_label; | |
7109 | xoperands[1] = gen_label_rtx (); | |
7110 | ||
7111 | /* If this isn't a sibcall, we put the load of %r27 into the | |
7112 | delay slot. We can't do this in a sibcall as we don't | |
7113 | have a second call-clobbered scratch register available. */ | |
7114 | if (seq_length != 0 | |
7115 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7116 | && !sibcall) | |
7117 | { | |
7118 | final_scan_insn (NEXT_INSN (insn), asm_out_file, | |
4bf029b0 | 7119 | optimize, 0, NULL); |
ece88821 | 7120 | |
7121 | /* Now delete the delay insn. */ | |
7122 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7123 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7124 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
7125 | delay_insn_deleted = 1; | |
7126 | } | |
06ddb6f8 | 7127 | |
ece88821 | 7128 | output_asm_insn ("addil LT'%0,%%r27", xoperands); |
7129 | output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands); | |
7130 | output_asm_insn ("ldd 0(%%r1),%%r1", xoperands); | |
06ddb6f8 | 7131 | |
ece88821 | 7132 | if (sibcall) |
06ddb6f8 | 7133 | { |
ece88821 | 7134 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); |
7135 | output_asm_insn ("ldd 16(%%r1),%%r1", xoperands); | |
7136 | output_asm_insn ("bve (%%r1)", xoperands); | |
7137 | } | |
7138 | else | |
7139 | { | |
7140 | output_asm_insn ("ldd 16(%%r1),%%r2", xoperands); | |
7141 | output_asm_insn ("bve,l (%%r2),%%r2", xoperands); | |
7142 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); | |
7143 | delay_slot_filled = 1; | |
06ddb6f8 | 7144 | } |
7145 | } | |
ece88821 | 7146 | else |
e3f53689 | 7147 | { |
ece88821 | 7148 | int indirect_call = 0; |
7149 | ||
7150 | /* Emit a long call. There are several different sequences | |
7151 | of increasing length and complexity. In most cases, | |
7152 | they don't allow an instruction in the delay slot. */ | |
2247cc5f | 7153 | if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
ece88821 | 7154 | && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) |
2247cc5f | 7155 | && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)) |
7156 | && !TARGET_64BIT) | |
ece88821 | 7157 | indirect_call = 1; |
7158 | ||
7159 | if (seq_length != 0 | |
7160 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7161 | && !sibcall | |
7162 | && (!TARGET_PA_20 || indirect_call)) | |
5cc6b2bc | 7163 | { |
ece88821 | 7164 | /* A non-jump insn in the delay slot. By definition we can |
7165 | emit this insn before the call (and in fact before argument | |
7166 | relocating. */ | |
4bf029b0 | 7167 | final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, |
fbf5169c | 7168 | NULL); |
ece88821 | 7169 | |
7170 | /* Now delete the delay insn. */ | |
7171 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7172 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7173 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
7174 | delay_insn_deleted = 1; | |
5cc6b2bc | 7175 | } |
e3f53689 | 7176 | |
2247cc5f | 7177 | if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
5cc6b2bc | 7178 | { |
ece88821 | 7179 | /* This is the best sequence for making long calls in |
7180 | non-pic code. Unfortunately, GNU ld doesn't provide | |
7181 | the stub needed for external calls, and GAS's support | |
2247cc5f | 7182 | for this with the SOM linker is buggy. It is safe |
7183 | to use this for local calls. */ | |
ece88821 | 7184 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
7185 | if (sibcall) | |
7186 | output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands); | |
7187 | else | |
7188 | { | |
7189 | if (TARGET_PA_20) | |
7190 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", | |
7191 | xoperands); | |
7192 | else | |
7193 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); | |
c7a4e712 | 7194 | |
ece88821 | 7195 | output_asm_insn ("copy %%r31,%%r2", xoperands); |
7196 | delay_slot_filled = 1; | |
7197 | } | |
7198 | } | |
7199 | else | |
7200 | { | |
2247cc5f | 7201 | if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) |
7202 | || (TARGET_64BIT && !TARGET_GAS)) | |
b70ea764 | 7203 | { |
ece88821 | 7204 | /* The HP assembler and linker can handle relocations |
7205 | for the difference of two symbols. GAS and the HP | |
7206 | linker can't do this when one of the symbols is | |
7207 | external. */ | |
7208 | xoperands[1] = gen_label_rtx (); | |
7209 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7210 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
805e22b2 | 7211 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
b70ea764 | 7212 | CODE_LABEL_NUMBER (xoperands[1])); |
ece88821 | 7213 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); |
7214 | } | |
2247cc5f | 7215 | else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)) |
b70ea764 | 7216 | { |
ece88821 | 7217 | /* GAS currently can't generate the relocations that |
7218 | are needed for the SOM linker under HP-UX using this | |
7219 | sequence. The GNU linker doesn't generate the stubs | |
7220 | that are needed for external calls on TARGET_ELF32 | |
7221 | with this sequence. For now, we have to use a | |
7222 | longer plabel sequence when using GAS. */ | |
7223 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7224 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", | |
b70ea764 | 7225 | xoperands); |
ece88821 | 7226 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", |
b70ea764 | 7227 | xoperands); |
7228 | } | |
5e3c5739 | 7229 | else |
7230 | { | |
ece88821 | 7231 | /* Emit a long plabel-based call sequence. This is |
7232 | essentially an inline implementation of $$dyncall. | |
7233 | We don't actually try to call $$dyncall as this is | |
7234 | as difficult as calling the function itself. */ | |
5f43b4f6 | 7235 | struct deferred_plabel *p = get_plabel (call_dest); |
ece88821 | 7236 | |
7237 | xoperands[0] = p->internal_label; | |
7238 | xoperands[1] = gen_label_rtx (); | |
7239 | ||
7240 | /* Since the call is indirect, FP arguments in registers | |
7241 | need to be copied to the general registers. Then, the | |
7242 | argument relocation stub will copy them back. */ | |
7243 | if (TARGET_SOM) | |
7244 | copy_fp_args (insn); | |
7245 | ||
7246 | if (flag_pic) | |
7247 | { | |
7248 | output_asm_insn ("addil LT'%0,%%r19", xoperands); | |
7249 | output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands); | |
7250 | output_asm_insn ("ldw 0(%%r1),%%r1", xoperands); | |
7251 | } | |
7252 | else | |
7253 | { | |
7254 | output_asm_insn ("addil LR'%0-$global$,%%r27", | |
7255 | xoperands); | |
7256 | output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1", | |
7257 | xoperands); | |
7258 | } | |
06ddb6f8 | 7259 | |
ece88821 | 7260 | output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands); |
7261 | output_asm_insn ("depi 0,31,2,%%r1", xoperands); | |
7262 | output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands); | |
7263 | output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands); | |
c7a4e712 | 7264 | |
ece88821 | 7265 | if (!sibcall && !TARGET_PA_20) |
7266 | { | |
7267 | output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands); | |
ee376abe | 7268 | if (TARGET_NO_SPACE_REGS) |
7269 | output_asm_insn ("addi 8,%%r2,%%r2", xoperands); | |
7270 | else | |
7271 | output_asm_insn ("addi 16,%%r2,%%r2", xoperands); | |
ece88821 | 7272 | } |
7273 | } | |
c7a4e712 | 7274 | |
ece88821 | 7275 | if (TARGET_PA_20) |
5e3c5739 | 7276 | { |
ece88821 | 7277 | if (sibcall) |
7278 | output_asm_insn ("bve (%%r1)", xoperands); | |
7279 | else | |
7280 | { | |
7281 | if (indirect_call) | |
7282 | { | |
7283 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7284 | output_asm_insn ("stw %%r2,-24(%%sp)", xoperands); | |
7285 | delay_slot_filled = 1; | |
7286 | } | |
7287 | else | |
7288 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7289 | } | |
5e3c5739 | 7290 | } |
7291 | else | |
7292 | { | |
ee376abe | 7293 | if (!TARGET_NO_SPACE_REGS) |
7294 | output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0", | |
7295 | xoperands); | |
06ddb6f8 | 7296 | |
ece88821 | 7297 | if (sibcall) |
ee376abe | 7298 | { |
7299 | if (TARGET_NO_SPACE_REGS) | |
7300 | output_asm_insn ("be 0(%%sr4,%%r1)", xoperands); | |
7301 | else | |
7302 | output_asm_insn ("be 0(%%sr0,%%r1)", xoperands); | |
7303 | } | |
ece88821 | 7304 | else |
7305 | { | |
ee376abe | 7306 | if (TARGET_NO_SPACE_REGS) |
7307 | output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands); | |
7308 | else | |
7309 | output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands); | |
06ddb6f8 | 7310 | |
ece88821 | 7311 | if (indirect_call) |
7312 | output_asm_insn ("stw %%r31,-24(%%sp)", xoperands); | |
7313 | else | |
7314 | output_asm_insn ("copy %%r31,%%r2", xoperands); | |
7315 | delay_slot_filled = 1; | |
7316 | } | |
7317 | } | |
7318 | } | |
06ddb6f8 | 7319 | } |
d6686e21 | 7320 | } |
6d36483b | 7321 | |
8a05c3c2 | 7322 | if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted)) |
ece88821 | 7323 | output_asm_insn ("nop", xoperands); |
d6686e21 | 7324 | |
ece88821 | 7325 | /* We are done if there isn't a jump in the delay slot. */ |
7326 | if (seq_length == 0 | |
7327 | || delay_insn_deleted | |
7328 | || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7329 | return ""; | |
d6686e21 | 7330 | |
ece88821 | 7331 | /* A sibcall should never have a branch in the delay slot. */ |
ecf2283d | 7332 | gcc_assert (!sibcall); |
d6686e21 | 7333 | |
ece88821 | 7334 | /* This call has an unconditional jump in its delay slot. */ |
7335 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
d6686e21 | 7336 | |
cd0dfcc5 | 7337 | if (!delay_slot_filled && INSN_ADDRESSES_SET_P ()) |
d6686e21 | 7338 | { |
ece88821 | 7339 | /* See if the return address can be adjusted. Use the containing |
7340 | sequence insn's address. */ | |
7341 | rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); | |
7342 | int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7343 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7344 | ||
7345 | if (VAL_14_BITS_P (distance)) | |
7346 | { | |
7347 | xoperands[1] = gen_label_rtx (); | |
7348 | output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands); | |
805e22b2 | 7349 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
7350 | CODE_LABEL_NUMBER (xoperands[1])); | |
ece88821 | 7351 | } |
7352 | else | |
ece88821 | 7353 | output_asm_insn ("nop\n\tb,n %0", xoperands); |
d6686e21 | 7354 | } |
ece88821 | 7355 | else |
ece88821 | 7356 | output_asm_insn ("b,n %0", xoperands); |
d6686e21 | 7357 | |
7358 | /* Delete the jump. */ | |
7359 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7360 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7361 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
ece88821 | 7362 | |
d6686e21 | 7363 | return ""; |
7364 | } | |
7365 | ||
cd0dfcc5 | 7366 | /* Return the attribute length of the indirect call instruction INSN. |
7367 | The length must match the code generated by output_indirect call. | |
7368 | The returned length includes the delay slot. Currently, the delay | |
7369 | slot of an indirect call sequence is not exposed and it is used by | |
7370 | the sequence itself. */ | |
7371 | ||
7372 | int | |
5c1d8983 | 7373 | attr_length_indirect_call (rtx insn) |
cd0dfcc5 | 7374 | { |
7375 | unsigned long distance = -1; | |
8a05c3c2 | 7376 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
cd0dfcc5 | 7377 | |
7378 | if (INSN_ADDRESSES_SET_P ()) | |
7379 | { | |
2247cc5f | 7380 | distance = (total + insn_current_reference_address (insn)); |
7381 | if (distance < total) | |
cd0dfcc5 | 7382 | distance = -1; |
7383 | } | |
7384 | ||
7385 | if (TARGET_64BIT) | |
7386 | return 12; | |
7387 | ||
7388 | if (TARGET_FAST_INDIRECT_CALLS | |
7389 | || (!TARGET_PORTABLE_RUNTIME | |
7390 | && ((TARGET_PA_20 && distance < 7600000) || distance < 240000))) | |
7391 | return 8; | |
7392 | ||
7393 | if (flag_pic) | |
7394 | return 24; | |
7395 | ||
7396 | if (TARGET_PORTABLE_RUNTIME) | |
7397 | return 20; | |
7398 | ||
7399 | /* Out of reach, can use ble. */ | |
7400 | return 12; | |
7401 | } | |
7402 | ||
7403 | const char * | |
5c1d8983 | 7404 | output_indirect_call (rtx insn, rtx call_dest) |
cd0dfcc5 | 7405 | { |
7406 | rtx xoperands[1]; | |
7407 | ||
7408 | if (TARGET_64BIT) | |
7409 | { | |
7410 | xoperands[0] = call_dest; | |
7411 | output_asm_insn ("ldd 16(%0),%%r2", xoperands); | |
7412 | output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands); | |
7413 | return ""; | |
7414 | } | |
7415 | ||
7416 | /* First the special case for kernels, level 0 systems, etc. */ | |
7417 | if (TARGET_FAST_INDIRECT_CALLS) | |
7418 | return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2"; | |
7419 | ||
7420 | /* Now the normal case -- we can reach $$dyncall directly or | |
7421 | we're sure that we can get there via a long-branch stub. | |
7422 | ||
7423 | No need to check target flags as the length uniquely identifies | |
7424 | the remaining cases. */ | |
7425 | if (attr_length_indirect_call (insn) == 8) | |
f707acb9 | 7426 | { |
7427 | /* The HP linker substitutes a BLE for millicode calls using | |
7428 | the short PIC PCREL form. Thus, we must use %r31 as the | |
7429 | link register when generating PA 1.x code. */ | |
7430 | if (TARGET_PA_20) | |
7431 | return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31"; | |
7432 | else | |
7433 | return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2"; | |
7434 | } | |
cd0dfcc5 | 7435 | |
7436 | /* Long millicode call, but we are not generating PIC or portable runtime | |
7437 | code. */ | |
7438 | if (attr_length_indirect_call (insn) == 12) | |
7439 | return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2"; | |
7440 | ||
7441 | /* Long millicode call for portable runtime. */ | |
7442 | if (attr_length_indirect_call (insn) == 20) | |
7443 | return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop"; | |
7444 | ||
7445 | /* We need a long PIC call to $$dyncall. */ | |
7446 | xoperands[0] = NULL_RTX; | |
7447 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7448 | if (TARGET_SOM || !TARGET_GAS) | |
7449 | { | |
7450 | xoperands[0] = gen_label_rtx (); | |
7451 | output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands); | |
7452 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
7453 | CODE_LABEL_NUMBER (xoperands[0])); | |
7454 | output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands); | |
7455 | } | |
7456 | else | |
7457 | { | |
7458 | output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands); | |
7459 | output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1", | |
7460 | xoperands); | |
7461 | } | |
7462 | output_asm_insn ("blr %%r0,%%r2", xoperands); | |
7463 | output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands); | |
7464 | return ""; | |
7465 | } | |
7466 | ||
7467 | /* Return the total length of the save and restore instructions needed for | |
7468 | the data linkage table pointer (i.e., the PIC register) across the call | |
7469 | instruction INSN. No-return calls do not require a save and restore. | |
7470 | In addition, we may be able to avoid the save and restore for calls | |
7471 | within the same translation unit. */ | |
7472 | ||
7473 | int | |
5c1d8983 | 7474 | attr_length_save_restore_dltp (rtx insn) |
cd0dfcc5 | 7475 | { |
7476 | if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
7477 | return 0; | |
7478 | ||
7479 | return 8; | |
7480 | } | |
7481 | ||
d6f01525 | 7482 | /* In HPUX 8.0's shared library scheme, special relocations are needed |
6d36483b | 7483 | for function labels if they might be passed to a function |
d6f01525 | 7484 | in a shared library (because shared libraries don't live in code |
44acf429 | 7485 | space), and special magic is needed to construct their address. */ |
d6f01525 | 7486 | |
7487 | void | |
5c1d8983 | 7488 | hppa_encode_label (rtx sym) |
d6f01525 | 7489 | { |
611a88e1 | 7490 | const char *str = XSTR (sym, 0); |
cccfb31e | 7491 | int len = strlen (str) + 1; |
7492 | char *newstr, *p; | |
d6f01525 | 7493 | |
cccfb31e | 7494 | p = newstr = alloca (len + 1); |
cccfb31e | 7495 | *p++ = '@'; |
7496 | strcpy (p, str); | |
74d80a9a | 7497 | |
ea52c577 | 7498 | XSTR (sym, 0) = ggc_alloc_string (newstr, len); |
d6f01525 | 7499 | } |
6d36483b | 7500 | |
7811991d | 7501 | static void |
5c1d8983 | 7502 | pa_encode_section_info (tree decl, rtx rtl, int first) |
7811991d | 7503 | { |
716b2c5a | 7504 | default_encode_section_info (decl, rtl, first); |
7505 | ||
7811991d | 7506 | if (first && TEXT_SPACE_P (decl)) |
7507 | { | |
7811991d | 7508 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
7509 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2c129d70 | 7510 | hppa_encode_label (XEXP (rtl, 0)); |
7811991d | 7511 | } |
7512 | } | |
7513 | ||
7b4a38a6 | 7514 | /* This is sort of inverse to pa_encode_section_info. */ |
7515 | ||
7516 | static const char * | |
5c1d8983 | 7517 | pa_strip_name_encoding (const char *str) |
7b4a38a6 | 7518 | { |
c0264367 | 7519 | str += (*str == '@'); |
7520 | str += (*str == '*'); | |
7521 | return str; | |
7b4a38a6 | 7522 | } |
7523 | ||
d6f01525 | 7524 | int |
5c1d8983 | 7525 | function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d6f01525 | 7526 | { |
c1b3411e | 7527 | return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0)); |
d6f01525 | 7528 | } |
f33e3942 | 7529 | |
166bf021 | 7530 | /* Returns 1 if OP is a function label involved in a simple addition |
7531 | with a constant. Used to keep certain patterns from matching | |
7532 | during instruction combination. */ | |
7533 | int | |
5c1d8983 | 7534 | is_function_label_plus_const (rtx op) |
166bf021 | 7535 | { |
7536 | /* Strip off any CONST. */ | |
7537 | if (GET_CODE (op) == CONST) | |
7538 | op = XEXP (op, 0); | |
7539 | ||
7540 | return (GET_CODE (op) == PLUS | |
7541 | && function_label_operand (XEXP (op, 0), Pmode) | |
7542 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
7543 | } | |
7544 | ||
f1752b7e | 7545 | /* Output assembly code for a thunk to FUNCTION. */ |
7546 | ||
6988553d | 7547 | static void |
5c1d8983 | 7548 | pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, |
7549 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
7550 | tree function) | |
f1752b7e | 7551 | { |
e678758c | 7552 | static unsigned int current_thunk_number; |
2247cc5f | 7553 | int val_14 = VAL_14_BITS_P (delta); |
7554 | int nbytes = 0; | |
f1752b7e | 7555 | char label[16]; |
e678758c | 7556 | rtx xoperands[4]; |
2247cc5f | 7557 | |
e678758c | 7558 | xoperands[0] = XEXP (DECL_RTL (function), 0); |
7559 | xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0); | |
7560 | xoperands[2] = GEN_INT (delta); | |
2247cc5f | 7561 | |
e678758c | 7562 | ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0)); |
7563 | fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); | |
2247cc5f | 7564 | |
7565 | /* Output the thunk. We know that the function is in the same | |
7566 | translation unit (i.e., the same space) as the thunk, and that | |
7567 | thunks are output after their method. Thus, we don't need an | |
7568 | external branch to reach the function. With SOM and GAS, | |
7569 | functions and thunks are effectively in different sections. | |
7570 | Thus, we can always use a IA-relative branch and the linker | |
7571 | will add a long branch stub if necessary. | |
7572 | ||
7573 | However, we have to be careful when generating PIC code on the | |
7574 | SOM port to ensure that the sequence does not transfer to an | |
7575 | import stub for the target function as this could clobber the | |
7576 | return value saved at SP-24. This would also apply to the | |
7577 | 32-bit linux port if the multi-space model is implemented. */ | |
7578 | if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
7579 | && !(flag_pic && TREE_PUBLIC (function)) | |
7580 | && (TARGET_GAS || last_address < 262132)) | |
7581 | || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
7582 | && ((targetm.have_named_sections | |
7583 | && DECL_SECTION_NAME (thunk_fndecl) != NULL | |
7584 | /* The GNU 64-bit linker has rather poor stub management. | |
7585 | So, we use a long branch from thunks that aren't in | |
7586 | the same section as the target function. */ | |
7587 | && ((!TARGET_64BIT | |
7588 | && (DECL_SECTION_NAME (thunk_fndecl) | |
7589 | != DECL_SECTION_NAME (function))) | |
7590 | || ((DECL_SECTION_NAME (thunk_fndecl) | |
7591 | == DECL_SECTION_NAME (function)) | |
7592 | && last_address < 262132))) | |
7593 | || (!targetm.have_named_sections && last_address < 262132)))) | |
7594 | { | |
e678758c | 7595 | if (!val_14) |
7596 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
7597 | ||
7598 | output_asm_insn ("b %0", xoperands); | |
7599 | ||
2247cc5f | 7600 | if (val_14) |
7601 | { | |
e678758c | 7602 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 7603 | nbytes += 8; |
7604 | } | |
7605 | else | |
7606 | { | |
e678758c | 7607 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 7608 | nbytes += 12; |
7609 | } | |
7610 | } | |
7611 | else if (TARGET_64BIT) | |
7612 | { | |
7613 | /* We only have one call-clobbered scratch register, so we can't | |
7614 | make use of the delay slot if delta doesn't fit in 14 bits. */ | |
7615 | if (!val_14) | |
e678758c | 7616 | { |
7617 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
7618 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); | |
7619 | } | |
2247cc5f | 7620 | |
e678758c | 7621 | output_asm_insn ("b,l .+8,%%r1", xoperands); |
2247cc5f | 7622 | |
7623 | if (TARGET_GAS) | |
7624 | { | |
e678758c | 7625 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
7626 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
2247cc5f | 7627 | } |
7628 | else | |
7629 | { | |
e678758c | 7630 | xoperands[3] = GEN_INT (val_14 ? 8 : 16); |
7631 | output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands); | |
2247cc5f | 7632 | } |
7633 | ||
7634 | if (val_14) | |
7635 | { | |
e678758c | 7636 | output_asm_insn ("bv %%r0(%%r1)", xoperands); |
7637 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); | |
2247cc5f | 7638 | nbytes += 20; |
7639 | } | |
7640 | else | |
7641 | { | |
e678758c | 7642 | output_asm_insn ("bv,n %%r0(%%r1)", xoperands); |
2247cc5f | 7643 | nbytes += 24; |
7644 | } | |
7645 | } | |
7646 | else if (TARGET_PORTABLE_RUNTIME) | |
7647 | { | |
e678758c | 7648 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
7649 | output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands); | |
7650 | ||
7651 | if (!val_14) | |
7652 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
7653 | ||
7654 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
2247cc5f | 7655 | |
7656 | if (val_14) | |
7657 | { | |
e678758c | 7658 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 7659 | nbytes += 16; |
7660 | } | |
7661 | else | |
7662 | { | |
e678758c | 7663 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 7664 | nbytes += 20; |
7665 | } | |
7666 | } | |
7667 | else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
7668 | { | |
7669 | /* The function is accessible from outside this module. The only | |
7670 | way to avoid an import stub between the thunk and function is to | |
7671 | call the function directly with an indirect sequence similar to | |
7672 | that used by $$dyncall. This is possible because $$dyncall acts | |
7673 | as the import stub in an indirect call. */ | |
2247cc5f | 7674 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number); |
e678758c | 7675 | xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label); |
7676 | output_asm_insn ("addil LT'%3,%%r19", xoperands); | |
7677 | output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands); | |
7678 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
7679 | output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands); | |
7680 | output_asm_insn ("depi 0,31,2,%%r22", xoperands); | |
7681 | output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands); | |
7682 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
7683 | ||
2247cc5f | 7684 | if (!val_14) |
7685 | { | |
e678758c | 7686 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
2247cc5f | 7687 | nbytes += 4; |
7688 | } | |
e678758c | 7689 | |
2247cc5f | 7690 | if (TARGET_PA_20) |
7691 | { | |
e678758c | 7692 | output_asm_insn ("bve (%%r22)", xoperands); |
7693 | nbytes += 36; | |
7694 | } | |
7695 | else if (TARGET_NO_SPACE_REGS) | |
7696 | { | |
7697 | output_asm_insn ("be 0(%%sr4,%%r22)", xoperands); | |
2247cc5f | 7698 | nbytes += 36; |
7699 | } | |
7700 | else | |
f1752b7e | 7701 | { |
e678758c | 7702 | output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands); |
7703 | output_asm_insn ("mtsp %%r21,%%sr0", xoperands); | |
7704 | output_asm_insn ("be 0(%%sr0,%%r22)", xoperands); | |
7705 | nbytes += 44; | |
2247cc5f | 7706 | } |
7707 | ||
7708 | if (val_14) | |
e678758c | 7709 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 7710 | else |
e678758c | 7711 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 7712 | } |
7713 | else if (flag_pic) | |
7714 | { | |
e678758c | 7715 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
2247cc5f | 7716 | |
7717 | if (TARGET_SOM || !TARGET_GAS) | |
7718 | { | |
e678758c | 7719 | output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands); |
7720 | output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands); | |
2247cc5f | 7721 | } |
7722 | else | |
7723 | { | |
e678758c | 7724 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
7725 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands); | |
2247cc5f | 7726 | } |
7727 | ||
e678758c | 7728 | if (!val_14) |
7729 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
7730 | ||
7731 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
7732 | ||
2247cc5f | 7733 | if (val_14) |
7734 | { | |
e678758c | 7735 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 7736 | nbytes += 20; |
f1752b7e | 7737 | } |
7738 | else | |
2247cc5f | 7739 | { |
e678758c | 7740 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 7741 | nbytes += 24; |
7742 | } | |
f1752b7e | 7743 | } |
7744 | else | |
7745 | { | |
2247cc5f | 7746 | if (!val_14) |
e678758c | 7747 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
2247cc5f | 7748 | |
e678758c | 7749 | output_asm_insn ("ldil L'%0,%%r22", xoperands); |
7750 | output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands); | |
2247cc5f | 7751 | |
7752 | if (val_14) | |
f1752b7e | 7753 | { |
e678758c | 7754 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 7755 | nbytes += 12; |
f1752b7e | 7756 | } |
7757 | else | |
2247cc5f | 7758 | { |
e678758c | 7759 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 7760 | nbytes += 16; |
7761 | } | |
f1752b7e | 7762 | } |
2247cc5f | 7763 | |
f1752b7e | 7764 | fprintf (file, "\t.EXIT\n\t.PROCEND\n"); |
2247cc5f | 7765 | |
7766 | if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
f1752b7e | 7767 | { |
7768 | data_section (); | |
e678758c | 7769 | output_asm_insn (".align 4", xoperands); |
2247cc5f | 7770 | ASM_OUTPUT_LABEL (file, label); |
e678758c | 7771 | output_asm_insn (".word P'%0", xoperands); |
f1752b7e | 7772 | } |
916c9cef | 7773 | else if (TARGET_SOM && TARGET_GAS) |
7774 | forget_section (); | |
2247cc5f | 7775 | |
f1752b7e | 7776 | current_thunk_number++; |
2247cc5f | 7777 | nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) |
7778 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
7779 | last_address += nbytes; | |
7780 | update_total_code_bytes (nbytes); | |
f1752b7e | 7781 | } |
7782 | ||
805e22b2 | 7783 | /* Only direct calls to static functions are allowed to be sibling (tail) |
7784 | call optimized. | |
7785 | ||
7786 | This restriction is necessary because some linker generated stubs will | |
7787 | store return pointers into rp' in some cases which might clobber a | |
7788 | live value already in rp'. | |
7789 | ||
7790 | In a sibcall the current function and the target function share stack | |
7791 | space. Thus if the path to the current function and the path to the | |
7792 | target function save a value in rp', they save the value into the | |
7793 | same stack slot, which has undesirable consequences. | |
7794 | ||
7795 | Because of the deferred binding nature of shared libraries any function | |
7796 | with external scope could be in a different load module and thus require | |
7797 | rp' to be saved when calling that function. So sibcall optimizations | |
7798 | can only be safe for static function. | |
7799 | ||
7800 | Note that GCC never needs return value relocations, so we don't have to | |
7801 | worry about static calls with return value relocations (which require | |
7802 | saving rp'). | |
7803 | ||
7804 | It is safe to perform a sibcall optimization when the target function | |
7805 | will never return. */ | |
7806 | static bool | |
5c1d8983 | 7807 | pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
805e22b2 | 7808 | { |
e11e9ae3 | 7809 | if (TARGET_PORTABLE_RUNTIME) |
7810 | return false; | |
7811 | ||
f62b73b6 | 7812 | /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in |
7813 | single subspace mode and the call is not indirect. As far as I know, | |
7814 | there is no operating system support for the multiple subspace mode. | |
7815 | It might be possible to support indirect calls if we didn't use | |
7816 | $$dyncall (see the indirect sequence generated in output_call). */ | |
7817 | if (TARGET_ELF32) | |
7818 | return (decl != NULL_TREE); | |
7819 | ||
7820 | /* Sibcalls are not ok because the arg pointer register is not a fixed | |
2cecd772 | 7821 | register. This prevents the sibcall optimization from occurring. In |
f62b73b6 | 7822 | addition, there are problems with stub placement using GNU ld. This |
7823 | is because a normal sibcall branch uses a 17-bit relocation while | |
7824 | a regular call branch uses a 22-bit relocation. As a result, more | |
7825 | care needs to be taken in the placement of long-branch stubs. */ | |
7826 | if (TARGET_64BIT) | |
7827 | return false; | |
7828 | ||
e11e9ae3 | 7829 | /* Sibcalls are only ok within a translation unit. */ |
7830 | return (decl && !TREE_PUBLIC (decl)); | |
805e22b2 | 7831 | } |
7832 | ||
280566a7 | 7833 | /* ??? Addition is not commutative on the PA due to the weird implicit |
7834 | space register selection rules for memory addresses. Therefore, we | |
7835 | don't consider a + b == b + a, as this might be inside a MEM. */ | |
7836 | static bool | |
7837 | pa_commutative_p (rtx x, int outer_code) | |
7838 | { | |
7839 | return (COMMUTATIVE_P (x) | |
55e3fa6d | 7840 | && (TARGET_NO_SPACE_REGS |
7841 | || (outer_code != UNKNOWN && outer_code != MEM) | |
280566a7 | 7842 | || GET_CODE (x) != PLUS)); |
7843 | } | |
7844 | ||
37580c80 | 7845 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
7846 | use in fmpyadd instructions. */ | |
4ed6ee50 | 7847 | int |
5c1d8983 | 7848 | fmpyaddoperands (rtx *operands) |
4ed6ee50 | 7849 | { |
201f01e9 | 7850 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 7851 | |
ab449421 | 7852 | /* Must be a floating point mode. */ |
7853 | if (mode != SFmode && mode != DFmode) | |
7854 | return 0; | |
7855 | ||
4ed6ee50 | 7856 | /* All modes must be the same. */ |
201f01e9 | 7857 | if (! (mode == GET_MODE (operands[1]) |
7858 | && mode == GET_MODE (operands[2]) | |
7859 | && mode == GET_MODE (operands[3]) | |
7860 | && mode == GET_MODE (operands[4]) | |
7861 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 7862 | return 0; |
7863 | ||
ab449421 | 7864 | /* All operands must be registers. */ |
7865 | if (! (GET_CODE (operands[1]) == REG | |
7866 | && GET_CODE (operands[2]) == REG | |
7867 | && GET_CODE (operands[3]) == REG | |
7868 | && GET_CODE (operands[4]) == REG | |
7869 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 7870 | return 0; |
7871 | ||
37580c80 | 7872 | /* Only 2 real operands to the addition. One of the input operands must |
7873 | be the same as the output operand. */ | |
4ed6ee50 | 7874 | if (! rtx_equal_p (operands[3], operands[4]) |
7875 | && ! rtx_equal_p (operands[3], operands[5])) | |
7876 | return 0; | |
7877 | ||
33f88b1c | 7878 | /* Inout operand of add cannot conflict with any operands from multiply. */ |
4ed6ee50 | 7879 | if (rtx_equal_p (operands[3], operands[0]) |
7880 | || rtx_equal_p (operands[3], operands[1]) | |
7881 | || rtx_equal_p (operands[3], operands[2])) | |
7882 | return 0; | |
7883 | ||
33f88b1c | 7884 | /* multiply cannot feed into addition operands. */ |
4ed6ee50 | 7885 | if (rtx_equal_p (operands[4], operands[0]) |
7886 | || rtx_equal_p (operands[5], operands[0])) | |
7887 | return 0; | |
7888 | ||
ab449421 | 7889 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
7890 | if (mode == SFmode | |
bac38c40 | 7891 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
7892 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
7893 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
7894 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
7895 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
7896 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 7897 | return 0; |
7898 | ||
4ed6ee50 | 7899 | /* Passed. Operands are suitable for fmpyadd. */ |
7900 | return 1; | |
7901 | } | |
7902 | ||
de419443 | 7903 | #if !defined(USE_COLLECT2) |
7904 | static void | |
5c1d8983 | 7905 | pa_asm_out_constructor (rtx symbol, int priority) |
de419443 | 7906 | { |
7907 | if (!function_label_operand (symbol, VOIDmode)) | |
7908 | hppa_encode_label (symbol); | |
7909 | ||
7910 | #ifdef CTORS_SECTION_ASM_OP | |
7911 | default_ctor_section_asm_out_constructor (symbol, priority); | |
7912 | #else | |
7913 | # ifdef TARGET_ASM_NAMED_SECTION | |
7914 | default_named_section_asm_out_constructor (symbol, priority); | |
7915 | # else | |
7916 | default_stabs_asm_out_constructor (symbol, priority); | |
7917 | # endif | |
7918 | #endif | |
7919 | } | |
7920 | ||
7921 | static void | |
5c1d8983 | 7922 | pa_asm_out_destructor (rtx symbol, int priority) |
de419443 | 7923 | { |
7924 | if (!function_label_operand (symbol, VOIDmode)) | |
7925 | hppa_encode_label (symbol); | |
7926 | ||
7927 | #ifdef DTORS_SECTION_ASM_OP | |
7928 | default_dtor_section_asm_out_destructor (symbol, priority); | |
7929 | #else | |
7930 | # ifdef TARGET_ASM_NAMED_SECTION | |
7931 | default_named_section_asm_out_destructor (symbol, priority); | |
7932 | # else | |
7933 | default_stabs_asm_out_destructor (symbol, priority); | |
7934 | # endif | |
7935 | #endif | |
7936 | } | |
7937 | #endif | |
7938 | ||
ff59d376 | 7939 | /* This function places uninitialized global data in the bss section. |
7940 | The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this | |
7941 | function on the SOM port to prevent uninitialized global data from | |
7942 | being placed in the data section. */ | |
7943 | ||
7944 | void | |
7945 | pa_asm_output_aligned_bss (FILE *stream, | |
7946 | const char *name, | |
7947 | unsigned HOST_WIDE_INT size, | |
7948 | unsigned int align) | |
7949 | { | |
7950 | bss_section (); | |
7951 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); | |
7952 | ||
7953 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
7954 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); | |
7955 | #endif | |
7956 | ||
7957 | #ifdef ASM_OUTPUT_SIZE_DIRECTIVE | |
7958 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
7959 | #endif | |
7960 | ||
7961 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); | |
7962 | ASM_OUTPUT_LABEL (stream, name); | |
7963 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
7964 | } | |
7965 | ||
7966 | /* Both the HP and GNU assemblers under HP-UX provide a .comm directive | |
7967 | that doesn't allow the alignment of global common storage to be directly | |
7968 | specified. The SOM linker aligns common storage based on the rounded | |
7969 | value of the NUM_BYTES parameter in the .comm directive. It's not | |
7970 | possible to use the .align directive as it doesn't affect the alignment | |
7971 | of the label associated with a .comm directive. */ | |
7972 | ||
7973 | void | |
7974 | pa_asm_output_aligned_common (FILE *stream, | |
7975 | const char *name, | |
7976 | unsigned HOST_WIDE_INT size, | |
7977 | unsigned int align) | |
7978 | { | |
33cd7888 | 7979 | unsigned int max_common_align; |
7980 | ||
7981 | max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64); | |
7982 | if (align > max_common_align) | |
7983 | { | |
c3ceba8e | 7984 | warning (0, "alignment (%u) for %s exceeds maximum alignment " |
33cd7888 | 7985 | "for global common data. Using %u", |
7986 | align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT); | |
7987 | align = max_common_align; | |
7988 | } | |
7989 | ||
ff59d376 | 7990 | bss_section (); |
7991 | ||
7992 | assemble_name (stream, name); | |
7993 | fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n", | |
7994 | MAX (size, align / BITS_PER_UNIT)); | |
7995 | } | |
7996 | ||
7997 | /* We can't use .comm for local common storage as the SOM linker effectively | |
7998 | treats the symbol as universal and uses the same storage for local symbols | |
7999 | with the same name in different object files. The .block directive | |
8000 | reserves an uninitialized block of storage. However, it's not common | |
8001 | storage. Fortunately, GCC never requests common storage with the same | |
8002 | name in any given translation unit. */ | |
8003 | ||
8004 | void | |
8005 | pa_asm_output_aligned_local (FILE *stream, | |
8006 | const char *name, | |
8007 | unsigned HOST_WIDE_INT size, | |
8008 | unsigned int align) | |
8009 | { | |
8010 | bss_section (); | |
8011 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); | |
8012 | ||
8013 | #ifdef LOCAL_ASM_OP | |
8014 | fprintf (stream, "%s", LOCAL_ASM_OP); | |
8015 | assemble_name (stream, name); | |
8016 | fprintf (stream, "\n"); | |
8017 | #endif | |
8018 | ||
8019 | ASM_OUTPUT_LABEL (stream, name); | |
8020 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
8021 | } | |
8022 | ||
37580c80 | 8023 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
8024 | use in fmpysub instructions. */ | |
4ed6ee50 | 8025 | int |
5c1d8983 | 8026 | fmpysuboperands (rtx *operands) |
4ed6ee50 | 8027 | { |
201f01e9 | 8028 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 8029 | |
ab449421 | 8030 | /* Must be a floating point mode. */ |
8031 | if (mode != SFmode && mode != DFmode) | |
8032 | return 0; | |
8033 | ||
4ed6ee50 | 8034 | /* All modes must be the same. */ |
201f01e9 | 8035 | if (! (mode == GET_MODE (operands[1]) |
8036 | && mode == GET_MODE (operands[2]) | |
8037 | && mode == GET_MODE (operands[3]) | |
8038 | && mode == GET_MODE (operands[4]) | |
8039 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 8040 | return 0; |
8041 | ||
ab449421 | 8042 | /* All operands must be registers. */ |
8043 | if (! (GET_CODE (operands[1]) == REG | |
8044 | && GET_CODE (operands[2]) == REG | |
8045 | && GET_CODE (operands[3]) == REG | |
8046 | && GET_CODE (operands[4]) == REG | |
8047 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 8048 | return 0; |
8049 | ||
37580c80 | 8050 | /* Only 2 real operands to the subtraction. Subtraction is not a commutative |
8051 | operation, so operands[4] must be the same as operand[3]. */ | |
4ed6ee50 | 8052 | if (! rtx_equal_p (operands[3], operands[4])) |
8053 | return 0; | |
8054 | ||
33f88b1c | 8055 | /* multiply cannot feed into subtraction. */ |
37580c80 | 8056 | if (rtx_equal_p (operands[5], operands[0])) |
4ed6ee50 | 8057 | return 0; |
8058 | ||
33f88b1c | 8059 | /* Inout operand of sub cannot conflict with any operands from multiply. */ |
4ed6ee50 | 8060 | if (rtx_equal_p (operands[3], operands[0]) |
8061 | || rtx_equal_p (operands[3], operands[1]) | |
8062 | || rtx_equal_p (operands[3], operands[2])) | |
8063 | return 0; | |
8064 | ||
ab449421 | 8065 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8066 | if (mode == SFmode | |
bac38c40 | 8067 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8068 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8069 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8070 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8071 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8072 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 8073 | return 0; |
8074 | ||
4ed6ee50 | 8075 | /* Passed. Operands are suitable for fmpysub. */ |
8076 | return 1; | |
8077 | } | |
8078 | ||
6720f95e | 8079 | /* Return 1 if the given constant is 2, 4, or 8. These are the valid |
8080 | constants for shadd instructions. */ | |
913de4b4 | 8081 | int |
5c1d8983 | 8082 | shadd_constant_p (int val) |
6720f95e | 8083 | { |
8084 | if (val == 2 || val == 4 || val == 8) | |
8085 | return 1; | |
8086 | else | |
8087 | return 0; | |
8088 | } | |
3a16146d | 8089 | |
dbd3d89d | 8090 | /* Return 1 if OP is valid as a base or index register in a |
8091 | REG+REG address. */ | |
42819d4e | 8092 | |
8093 | int | |
dbd3d89d | 8094 | borx_reg_operand (rtx op, enum machine_mode mode) |
42819d4e | 8095 | { |
dbd3d89d | 8096 | if (GET_CODE (op) != REG) |
21f3ee9c | 8097 | return 0; |
8098 | ||
dbd3d89d | 8099 | /* We must reject virtual registers as the only expressions that |
8100 | can be instantiated are REG and REG+CONST. */ | |
8101 | if (op == virtual_incoming_args_rtx | |
8102 | || op == virtual_stack_vars_rtx | |
8103 | || op == virtual_stack_dynamic_rtx | |
8104 | || op == virtual_outgoing_args_rtx | |
8105 | || op == virtual_cfa_rtx) | |
8106 | return 0; | |
42819d4e | 8107 | |
21f3ee9c | 8108 | /* While it's always safe to index off the frame pointer, it's not |
dbd3d89d | 8109 | profitable to do so when the frame pointer is being eliminated. */ |
8110 | if (!reload_completed | |
8111 | && flag_omit_frame_pointer | |
8112 | && !current_function_calls_alloca | |
8113 | && op == frame_pointer_rtx) | |
8114 | return 0; | |
42819d4e | 8115 | |
dbd3d89d | 8116 | return register_operand (op, mode); |
42819d4e | 8117 | } |
8118 | ||
51987f90 | 8119 | /* Return 1 if this operand is anything other than a hard register. */ |
8120 | ||
8121 | int | |
5c1d8983 | 8122 | non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
51987f90 | 8123 | { |
8124 | return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER); | |
8125 | } | |
8126 | ||
5fbd5940 | 8127 | /* Return 1 if INSN branches forward. Should be using insn_addresses |
6dc3b0d9 | 8128 | to avoid walking through all the insns... */ |
7d27e4c9 | 8129 | static int |
5c1d8983 | 8130 | forward_branch_p (rtx insn) |
5fbd5940 | 8131 | { |
8132 | rtx label = JUMP_LABEL (insn); | |
8133 | ||
8134 | while (insn) | |
8135 | { | |
8136 | if (insn == label) | |
8137 | break; | |
8138 | else | |
8139 | insn = NEXT_INSN (insn); | |
8140 | } | |
8141 | ||
8142 | return (insn == label); | |
8143 | } | |
8144 | ||
29a4502c | 8145 | /* Return 1 if OP is an equality comparison, else return 0. */ |
8146 | int | |
5c1d8983 | 8147 | eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
29a4502c | 8148 | { |
8149 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
8150 | } | |
8151 | ||
d6686e21 | 8152 | /* Return 1 if INSN is in the delay slot of a call instruction. */ |
8153 | int | |
5c1d8983 | 8154 | jump_in_call_delay (rtx insn) |
d6686e21 | 8155 | { |
8156 | ||
8157 | if (GET_CODE (insn) != JUMP_INSN) | |
8158 | return 0; | |
8159 | ||
8160 | if (PREV_INSN (insn) | |
8161 | && PREV_INSN (PREV_INSN (insn)) | |
ece0fa59 | 8162 | && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN) |
d6686e21 | 8163 | { |
ece0fa59 | 8164 | rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn))); |
d6686e21 | 8165 | |
8166 | return (GET_CODE (PATTERN (test_insn)) == SEQUENCE | |
8167 | && XVECEXP (PATTERN (test_insn), 0, 1) == insn); | |
8168 | ||
8169 | } | |
8170 | else | |
8171 | return 0; | |
8172 | } | |
3b1e673e | 8173 | |
546a40bd | 8174 | /* Output an unconditional move and branch insn. */ |
8175 | ||
611a88e1 | 8176 | const char * |
5c1d8983 | 8177 | output_parallel_movb (rtx *operands, int length) |
546a40bd | 8178 | { |
8179 | /* These are the cases in which we win. */ | |
8180 | if (length == 4) | |
8181 | return "mov%I1b,tr %1,%0,%2"; | |
8182 | ||
8183 | /* None of these cases wins, but they don't lose either. */ | |
8184 | if (dbr_sequence_length () == 0) | |
8185 | { | |
8186 | /* Nothing in the delay slot, fake it by putting the combined | |
8187 | insn (the copy or add) in the delay slot of a bl. */ | |
8188 | if (GET_CODE (operands[1]) == CONST_INT) | |
5a811d43 | 8189 | return "b %2\n\tldi %1,%0"; |
546a40bd | 8190 | else |
5a811d43 | 8191 | return "b %2\n\tcopy %1,%0"; |
546a40bd | 8192 | } |
8193 | else | |
8194 | { | |
8195 | /* Something in the delay slot, but we've got a long branch. */ | |
8196 | if (GET_CODE (operands[1]) == CONST_INT) | |
5a811d43 | 8197 | return "ldi %1,%0\n\tb %2"; |
546a40bd | 8198 | else |
5a811d43 | 8199 | return "copy %1,%0\n\tb %2"; |
546a40bd | 8200 | } |
8201 | } | |
8202 | ||
8203 | /* Output an unconditional add and branch insn. */ | |
8204 | ||
611a88e1 | 8205 | const char * |
5c1d8983 | 8206 | output_parallel_addb (rtx *operands, int length) |
546a40bd | 8207 | { |
8208 | /* To make life easy we want operand0 to be the shared input/output | |
8209 | operand and operand1 to be the readonly operand. */ | |
8210 | if (operands[0] == operands[1]) | |
8211 | operands[1] = operands[2]; | |
8212 | ||
8213 | /* These are the cases in which we win. */ | |
8214 | if (length == 4) | |
8215 | return "add%I1b,tr %1,%0,%3"; | |
8216 | ||
8217 | /* None of these cases win, but they don't lose either. */ | |
8218 | if (dbr_sequence_length () == 0) | |
8219 | { | |
8220 | /* Nothing in the delay slot, fake it by putting the combined | |
8221 | insn (the copy or add) in the delay slot of a bl. */ | |
5a811d43 | 8222 | return "b %3\n\tadd%I1 %1,%0,%0"; |
546a40bd | 8223 | } |
8224 | else | |
8225 | { | |
8226 | /* Something in the delay slot, but we've got a long branch. */ | |
5a811d43 | 8227 | return "add%I1 %1,%0,%0\n\tb %3"; |
546a40bd | 8228 | } |
8229 | } | |
8230 | ||
7c5101fc | 8231 | /* Return nonzero if INSN (a jump insn) immediately follows a call |
8232 | to a named function. This is used to avoid filling the delay slot | |
8233 | of the jump since it can usually be eliminated by modifying RP in | |
8234 | the delay slot of the call. */ | |
9840d99d | 8235 | |
7d27e4c9 | 8236 | int |
5c1d8983 | 8237 | following_call (rtx insn) |
546a40bd | 8238 | { |
ed1b0769 | 8239 | if (! TARGET_JUMP_IN_DELAY) |
1b6f11e2 | 8240 | return 0; |
8241 | ||
546a40bd | 8242 | /* Find the previous real insn, skipping NOTEs. */ |
8243 | insn = PREV_INSN (insn); | |
8244 | while (insn && GET_CODE (insn) == NOTE) | |
8245 | insn = PREV_INSN (insn); | |
8246 | ||
8247 | /* Check for CALL_INSNs and millicode calls. */ | |
8248 | if (insn | |
1d2e016c | 8249 | && ((GET_CODE (insn) == CALL_INSN |
8250 | && get_attr_type (insn) != TYPE_DYNCALL) | |
546a40bd | 8251 | || (GET_CODE (insn) == INSN |
8252 | && GET_CODE (PATTERN (insn)) != SEQUENCE | |
8253 | && GET_CODE (PATTERN (insn)) != USE | |
8254 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8255 | && get_attr_type (insn) == TYPE_MILLI))) | |
8256 | return 1; | |
8257 | ||
8258 | return 0; | |
8259 | } | |
8260 | ||
3b1e673e | 8261 | /* We use this hook to perform a PA specific optimization which is difficult |
8262 | to do in earlier passes. | |
8263 | ||
8264 | We want the delay slots of branches within jump tables to be filled. | |
8265 | None of the compiler passes at the moment even has the notion that a | |
8266 | PA jump table doesn't contain addresses, but instead contains actual | |
8267 | instructions! | |
8268 | ||
8269 | Because we actually jump into the table, the addresses of each entry | |
01cc3b75 | 8270 | must stay constant in relation to the beginning of the table (which |
3b1e673e | 8271 | itself must stay constant relative to the instruction to jump into |
8272 | it). I don't believe we can guarantee earlier passes of the compiler | |
8273 | will adhere to those rules. | |
8274 | ||
8275 | So, late in the compilation process we find all the jump tables, and | |
a361b456 | 8276 | expand them into real code -- e.g. each entry in the jump table vector |
3b1e673e | 8277 | will get an appropriate label followed by a jump to the final target. |
8278 | ||
8279 | Reorg and the final jump pass can then optimize these branches and | |
8280 | fill their delay slots. We end up with smaller, more efficient code. | |
8281 | ||
9840d99d | 8282 | The jump instructions within the table are special; we must be able |
3b1e673e | 8283 | to identify them during assembly output (if the jumps don't get filled |
8284 | we need to emit a nop rather than nullifying the delay slot)). We | |
b932f66c | 8285 | identify jumps in switch tables by using insns with the attribute |
8286 | type TYPE_BTABLE_BRANCH. | |
9239127b | 8287 | |
8288 | We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB | |
8289 | insns. This serves two purposes, first it prevents jump.c from | |
8290 | noticing that the last N entries in the table jump to the instruction | |
8291 | immediately after the table and deleting the jumps. Second, those | |
8292 | insns mark where we should emit .begin_brtab and .end_brtab directives | |
8293 | when using GAS (allows for better link time optimizations). */ | |
3b1e673e | 8294 | |
2efea8c0 | 8295 | static void |
5c1d8983 | 8296 | pa_reorg (void) |
3b1e673e | 8297 | { |
8298 | rtx insn; | |
8299 | ||
2efea8c0 | 8300 | remove_useless_addtr_insns (1); |
3d457930 | 8301 | |
342aabd9 | 8302 | if (pa_cpu < PROCESSOR_8000) |
2efea8c0 | 8303 | pa_combine_instructions (); |
342aabd9 | 8304 | |
bd49d362 | 8305 | |
3d457930 | 8306 | /* This is fairly cheap, so always run it if optimizing. */ |
a66555b2 | 8307 | if (optimize > 0 && !TARGET_BIG_SWITCH) |
3b1e673e | 8308 | { |
b41266d4 | 8309 | /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */ |
2efea8c0 | 8310 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
3b1e673e | 8311 | { |
b932f66c | 8312 | rtx pattern, tmp, location, label; |
3b1e673e | 8313 | unsigned int length, i; |
8314 | ||
b41266d4 | 8315 | /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */ |
3b1e673e | 8316 | if (GET_CODE (insn) != JUMP_INSN |
b41266d4 | 8317 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8318 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
3b1e673e | 8319 | continue; |
8320 | ||
9239127b | 8321 | /* Emit marker for the beginning of the branch table. */ |
8322 | emit_insn_before (gen_begin_brtab (), insn); | |
f9333726 | 8323 | |
3b1e673e | 8324 | pattern = PATTERN (insn); |
8325 | location = PREV_INSN (insn); | |
b41266d4 | 8326 | length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC); |
f9333726 | 8327 | |
3b1e673e | 8328 | for (i = 0; i < length; i++) |
8329 | { | |
a66555b2 | 8330 | /* Emit a label before each jump to keep jump.c from |
8331 | removing this code. */ | |
8332 | tmp = gen_label_rtx (); | |
8333 | LABEL_NUSES (tmp) = 1; | |
8334 | emit_label_after (tmp, location); | |
8335 | location = NEXT_INSN (location); | |
8336 | ||
b41266d4 | 8337 | if (GET_CODE (pattern) == ADDR_VEC) |
b932f66c | 8338 | label = XEXP (XVECEXP (pattern, 0, i), 0); |
b41266d4 | 8339 | else |
b932f66c | 8340 | label = XEXP (XVECEXP (pattern, 1, i), 0); |
8341 | ||
8342 | tmp = gen_short_jump (label); | |
8343 | ||
8344 | /* Emit the jump itself. */ | |
8345 | tmp = emit_jump_insn_after (tmp, location); | |
8346 | JUMP_LABEL (tmp) = label; | |
8347 | LABEL_NUSES (label)++; | |
8348 | location = NEXT_INSN (location); | |
3b1e673e | 8349 | |
8350 | /* Emit a BARRIER after the jump. */ | |
3b1e673e | 8351 | emit_barrier_after (location); |
3b1e673e | 8352 | location = NEXT_INSN (location); |
8353 | } | |
f9333726 | 8354 | |
9239127b | 8355 | /* Emit marker for the end of the branch table. */ |
8356 | emit_insn_before (gen_end_brtab (), location); | |
8357 | location = NEXT_INSN (location); | |
8358 | emit_barrier_after (location); | |
a66555b2 | 8359 | |
b41266d4 | 8360 | /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */ |
3b1e673e | 8361 | delete_insn (insn); |
8362 | } | |
8363 | } | |
9239127b | 8364 | else |
f9333726 | 8365 | { |
b932f66c | 8366 | /* Still need brtab marker insns. FIXME: the presence of these |
8367 | markers disables output of the branch table to readonly memory, | |
8368 | and any alignment directives that might be needed. Possibly, | |
8369 | the begin_brtab insn should be output before the label for the | |
7bd28bba | 8370 | table. This doesn't matter at the moment since the tables are |
b932f66c | 8371 | always output in the text section. */ |
2efea8c0 | 8372 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
f9333726 | 8373 | { |
8374 | /* Find an ADDR_VEC insn. */ | |
8375 | if (GET_CODE (insn) != JUMP_INSN | |
b41266d4 | 8376 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8377 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
f9333726 | 8378 | continue; |
8379 | ||
8380 | /* Now generate markers for the beginning and end of the | |
ad87de1e | 8381 | branch table. */ |
f9333726 | 8382 | emit_insn_before (gen_begin_brtab (), insn); |
8383 | emit_insn_after (gen_end_brtab (), insn); | |
8384 | } | |
8385 | } | |
d3287673 | 8386 | } |
bd49d362 | 8387 | |
8388 | /* The PA has a number of odd instructions which can perform multiple | |
8389 | tasks at once. On first generation PA machines (PA1.0 and PA1.1) | |
8390 | it may be profitable to combine two instructions into one instruction | |
8391 | with two outputs. It's not profitable PA2.0 machines because the | |
8392 | two outputs would take two slots in the reorder buffers. | |
8393 | ||
8394 | This routine finds instructions which can be combined and combines | |
8395 | them. We only support some of the potential combinations, and we | |
8396 | only try common ways to find suitable instructions. | |
8397 | ||
8398 | * addb can add two registers or a register and a small integer | |
8399 | and jump to a nearby (+-8k) location. Normally the jump to the | |
8400 | nearby location is conditional on the result of the add, but by | |
8401 | using the "true" condition we can make the jump unconditional. | |
8402 | Thus addb can perform two independent operations in one insn. | |
8403 | ||
8404 | * movb is similar to addb in that it can perform a reg->reg | |
8405 | or small immediate->reg copy and jump to a nearby (+-8k location). | |
8406 | ||
8407 | * fmpyadd and fmpysub can perform a FP multiply and either an | |
8408 | FP add or FP sub if the operands of the multiply and add/sub are | |
8409 | independent (there are other minor restrictions). Note both | |
8410 | the fmpy and fadd/fsub can in theory move to better spots according | |
8411 | to data dependencies, but for now we require the fmpy stay at a | |
8412 | fixed location. | |
8413 | ||
8414 | * Many of the memory operations can perform pre & post updates | |
8415 | of index registers. GCC's pre/post increment/decrement addressing | |
8416 | is far too simple to take advantage of all the possibilities. This | |
8417 | pass may not be suitable since those insns may not be independent. | |
8418 | ||
8419 | * comclr can compare two ints or an int and a register, nullify | |
8420 | the following instruction and zero some other register. This | |
8421 | is more difficult to use as it's harder to find an insn which | |
8422 | will generate a comclr than finding something like an unconditional | |
8423 | branch. (conditional moves & long branches create comclr insns). | |
8424 | ||
8425 | * Most arithmetic operations can conditionally skip the next | |
8426 | instruction. They can be viewed as "perform this operation | |
8427 | and conditionally jump to this nearby location" (where nearby | |
8428 | is an insns away). These are difficult to use due to the | |
8429 | branch length restrictions. */ | |
8430 | ||
7d27e4c9 | 8431 | static void |
5c1d8983 | 8432 | pa_combine_instructions (void) |
bd49d362 | 8433 | { |
8434 | rtx anchor, new; | |
8435 | ||
8436 | /* This can get expensive since the basic algorithm is on the | |
8437 | order of O(n^2) (or worse). Only do it for -O2 or higher | |
ad87de1e | 8438 | levels of optimization. */ |
bd49d362 | 8439 | if (optimize < 2) |
8440 | return; | |
8441 | ||
8442 | /* Walk down the list of insns looking for "anchor" insns which | |
8443 | may be combined with "floating" insns. As the name implies, | |
8444 | "anchor" instructions don't move, while "floating" insns may | |
8445 | move around. */ | |
ad851752 | 8446 | new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX)); |
bd49d362 | 8447 | new = make_insn_raw (new); |
8448 | ||
8449 | for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor)) | |
8450 | { | |
8451 | enum attr_pa_combine_type anchor_attr; | |
8452 | enum attr_pa_combine_type floater_attr; | |
8453 | ||
8454 | /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs. | |
8455 | Also ignore any special USE insns. */ | |
7d27e4c9 | 8456 | if ((GET_CODE (anchor) != INSN |
bd49d362 | 8457 | && GET_CODE (anchor) != JUMP_INSN |
7d27e4c9 | 8458 | && GET_CODE (anchor) != CALL_INSN) |
bd49d362 | 8459 | || GET_CODE (PATTERN (anchor)) == USE |
8460 | || GET_CODE (PATTERN (anchor)) == CLOBBER | |
8461 | || GET_CODE (PATTERN (anchor)) == ADDR_VEC | |
8462 | || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC) | |
8463 | continue; | |
8464 | ||
8465 | anchor_attr = get_attr_pa_combine_type (anchor); | |
8466 | /* See if anchor is an insn suitable for combination. */ | |
8467 | if (anchor_attr == PA_COMBINE_TYPE_FMPY | |
8468 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8469 | || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
8470 | && ! forward_branch_p (anchor))) | |
8471 | { | |
8472 | rtx floater; | |
8473 | ||
8474 | for (floater = PREV_INSN (anchor); | |
8475 | floater; | |
8476 | floater = PREV_INSN (floater)) | |
8477 | { | |
8478 | if (GET_CODE (floater) == NOTE | |
8479 | || (GET_CODE (floater) == INSN | |
8480 | && (GET_CODE (PATTERN (floater)) == USE | |
8481 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
8482 | continue; | |
8483 | ||
8484 | /* Anything except a regular INSN will stop our search. */ | |
8485 | if (GET_CODE (floater) != INSN | |
8486 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
8487 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
8488 | { | |
8489 | floater = NULL_RTX; | |
8490 | break; | |
8491 | } | |
8492 | ||
8493 | /* See if FLOATER is suitable for combination with the | |
8494 | anchor. */ | |
8495 | floater_attr = get_attr_pa_combine_type (floater); | |
8496 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
8497 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
8498 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8499 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
8500 | { | |
8501 | /* If ANCHOR and FLOATER can be combined, then we're | |
8502 | done with this pass. */ | |
8503 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8504 | SET_DEST (PATTERN (floater)), | |
8505 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
8506 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
8507 | break; | |
8508 | } | |
8509 | ||
8510 | else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
8511 | && floater_attr == PA_COMBINE_TYPE_ADDMOVE) | |
8512 | { | |
8513 | if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS) | |
8514 | { | |
8515 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8516 | SET_DEST (PATTERN (floater)), | |
8517 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
8518 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
8519 | break; | |
8520 | } | |
8521 | else | |
8522 | { | |
8523 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8524 | SET_DEST (PATTERN (floater)), | |
8525 | SET_SRC (PATTERN (floater)), | |
8526 | SET_SRC (PATTERN (floater)))) | |
8527 | break; | |
8528 | } | |
8529 | } | |
8530 | } | |
8531 | ||
8532 | /* If we didn't find anything on the backwards scan try forwards. */ | |
8533 | if (!floater | |
8534 | && (anchor_attr == PA_COMBINE_TYPE_FMPY | |
8535 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB)) | |
8536 | { | |
8537 | for (floater = anchor; floater; floater = NEXT_INSN (floater)) | |
8538 | { | |
8539 | if (GET_CODE (floater) == NOTE | |
8540 | || (GET_CODE (floater) == INSN | |
8541 | && (GET_CODE (PATTERN (floater)) == USE | |
8542 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
9840d99d | 8543 | |
bd49d362 | 8544 | continue; |
8545 | ||
8546 | /* Anything except a regular INSN will stop our search. */ | |
8547 | if (GET_CODE (floater) != INSN | |
8548 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
8549 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
8550 | { | |
8551 | floater = NULL_RTX; | |
8552 | break; | |
8553 | } | |
8554 | ||
8555 | /* See if FLOATER is suitable for combination with the | |
8556 | anchor. */ | |
8557 | floater_attr = get_attr_pa_combine_type (floater); | |
8558 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
8559 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
8560 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8561 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
8562 | { | |
8563 | /* If ANCHOR and FLOATER can be combined, then we're | |
8564 | done with this pass. */ | |
8565 | if (pa_can_combine_p (new, anchor, floater, 1, | |
8566 | SET_DEST (PATTERN (floater)), | |
ea52c577 | 8567 | XEXP (SET_SRC (PATTERN (floater)), |
8568 | 0), | |
8569 | XEXP (SET_SRC (PATTERN (floater)), | |
8570 | 1))) | |
bd49d362 | 8571 | break; |
8572 | } | |
8573 | } | |
8574 | } | |
8575 | ||
8576 | /* FLOATER will be nonzero if we found a suitable floating | |
8577 | insn for combination with ANCHOR. */ | |
8578 | if (floater | |
8579 | && (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8580 | || anchor_attr == PA_COMBINE_TYPE_FMPY)) | |
8581 | { | |
8582 | /* Emit the new instruction and delete the old anchor. */ | |
7014838c | 8583 | emit_insn_before (gen_rtx_PARALLEL |
8584 | (VOIDmode, | |
8585 | gen_rtvec (2, PATTERN (anchor), | |
8586 | PATTERN (floater))), | |
8587 | anchor); | |
8588 | ||
bd49d362 | 8589 | PUT_CODE (anchor, NOTE); |
8590 | NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED; | |
8591 | NOTE_SOURCE_FILE (anchor) = 0; | |
8592 | ||
8593 | /* Emit a special USE insn for FLOATER, then delete | |
8594 | the floating insn. */ | |
ad851752 | 8595 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 8596 | delete_insn (floater); |
8597 | ||
8598 | continue; | |
8599 | } | |
8600 | else if (floater | |
8601 | && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH) | |
8602 | { | |
8603 | rtx temp; | |
8604 | /* Emit the new_jump instruction and delete the old anchor. */ | |
7014838c | 8605 | temp |
8606 | = emit_jump_insn_before (gen_rtx_PARALLEL | |
8607 | (VOIDmode, | |
8608 | gen_rtvec (2, PATTERN (anchor), | |
8609 | PATTERN (floater))), | |
8610 | anchor); | |
8611 | ||
bd49d362 | 8612 | JUMP_LABEL (temp) = JUMP_LABEL (anchor); |
8613 | PUT_CODE (anchor, NOTE); | |
8614 | NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED; | |
8615 | NOTE_SOURCE_FILE (anchor) = 0; | |
8616 | ||
8617 | /* Emit a special USE insn for FLOATER, then delete | |
8618 | the floating insn. */ | |
ad851752 | 8619 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 8620 | delete_insn (floater); |
8621 | continue; | |
8622 | } | |
8623 | } | |
8624 | } | |
8625 | } | |
8626 | ||
9aadea62 | 8627 | static int |
5c1d8983 | 8628 | pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest, |
8629 | rtx src1, rtx src2) | |
bd49d362 | 8630 | { |
8631 | int insn_code_number; | |
8632 | rtx start, end; | |
8633 | ||
8634 | /* Create a PARALLEL with the patterns of ANCHOR and | |
8635 | FLOATER, try to recognize it, then test constraints | |
8636 | for the resulting pattern. | |
8637 | ||
8638 | If the pattern doesn't match or the constraints | |
8639 | aren't met keep searching for a suitable floater | |
8640 | insn. */ | |
8641 | XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor); | |
8642 | XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater); | |
8643 | INSN_CODE (new) = -1; | |
8644 | insn_code_number = recog_memoized (new); | |
8645 | if (insn_code_number < 0 | |
bf9fd117 | 8646 | || (extract_insn (new), ! constrain_operands (1))) |
bd49d362 | 8647 | return 0; |
8648 | ||
8649 | if (reversed) | |
8650 | { | |
8651 | start = anchor; | |
8652 | end = floater; | |
8653 | } | |
8654 | else | |
8655 | { | |
8656 | start = floater; | |
8657 | end = anchor; | |
8658 | } | |
8659 | ||
8660 | /* There's up to three operands to consider. One | |
8661 | output and two inputs. | |
8662 | ||
8663 | The output must not be used between FLOATER & ANCHOR | |
8664 | exclusive. The inputs must not be set between | |
8665 | FLOATER and ANCHOR exclusive. */ | |
8666 | ||
8667 | if (reg_used_between_p (dest, start, end)) | |
8668 | return 0; | |
8669 | ||
8670 | if (reg_set_between_p (src1, start, end)) | |
8671 | return 0; | |
8672 | ||
8673 | if (reg_set_between_p (src2, start, end)) | |
8674 | return 0; | |
8675 | ||
8676 | /* If we get here, then everything is good. */ | |
8677 | return 1; | |
8678 | } | |
14d18de3 | 8679 | |
a6582a53 | 8680 | /* Return nonzero if references for INSN are delayed. |
14d18de3 | 8681 | |
8682 | Millicode insns are actually function calls with some special | |
8683 | constraints on arguments and register usage. | |
8684 | ||
8685 | Millicode calls always expect their arguments in the integer argument | |
8686 | registers, and always return their result in %r29 (ret1). They | |
2013ddf6 | 8687 | are expected to clobber their arguments, %r1, %r29, and the return |
8688 | pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else. | |
8689 | ||
8690 | This function tells reorg that the references to arguments and | |
8691 | millicode calls do not appear to happen until after the millicode call. | |
8692 | This allows reorg to put insns which set the argument registers into the | |
8693 | delay slot of the millicode call -- thus they act more like traditional | |
8694 | CALL_INSNs. | |
8695 | ||
33f88b1c | 8696 | Note we cannot consider side effects of the insn to be delayed because |
2013ddf6 | 8697 | the branch and link insn will clobber the return pointer. If we happened |
8698 | to use the return pointer in the delay slot of the call, then we lose. | |
14d18de3 | 8699 | |
8700 | get_attr_type will try to recognize the given insn, so make sure to | |
8701 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
8702 | in particular. */ | |
8703 | int | |
5c1d8983 | 8704 | insn_refs_are_delayed (rtx insn) |
14d18de3 | 8705 | { |
9840d99d | 8706 | return ((GET_CODE (insn) == INSN |
14d18de3 | 8707 | && GET_CODE (PATTERN (insn)) != SEQUENCE |
8708 | && GET_CODE (PATTERN (insn)) != USE | |
8709 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8710 | && get_attr_type (insn) == TYPE_MILLI)); | |
8711 | } | |
5cb4669a | 8712 | |
58a72cce | 8713 | /* On the HP-PA the value is found in register(s) 28(-29), unless |
8714 | the mode is SF or DF. Then the value is returned in fr4 (32). | |
8715 | ||
8716 | This must perform the same promotions as PROMOTE_MODE, else | |
b8debbe8 | 8717 | TARGET_PROMOTE_FUNCTION_RETURN will not work correctly. |
58a72cce | 8718 | |
8719 | Small structures must be returned in a PARALLEL on PA64 in order | |
8720 | to match the HP Compiler ABI. */ | |
8721 | ||
8722 | rtx | |
5c1d8983 | 8723 | function_value (tree valtype, tree func ATTRIBUTE_UNUSED) |
58a72cce | 8724 | { |
8725 | enum machine_mode valmode; | |
8726 | ||
b105ef41 | 8727 | if (AGGREGATE_TYPE_P (valtype)) |
58a72cce | 8728 | { |
b105ef41 | 8729 | if (TARGET_64BIT) |
8730 | { | |
8731 | /* Aggregates with a size less than or equal to 128 bits are | |
8732 | returned in GR 28(-29). They are left justified. The pad | |
8733 | bits are undefined. Larger aggregates are returned in | |
8734 | memory. */ | |
8735 | rtx loc[2]; | |
8736 | int i, offset = 0; | |
8737 | int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2; | |
8738 | ||
8739 | for (i = 0; i < ub; i++) | |
8740 | { | |
8741 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
8742 | gen_rtx_REG (DImode, 28 + i), | |
8743 | GEN_INT (offset)); | |
8744 | offset += 8; | |
8745 | } | |
58a72cce | 8746 | |
b105ef41 | 8747 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc)); |
8748 | } | |
8749 | else if (int_size_in_bytes (valtype) > UNITS_PER_WORD) | |
58a72cce | 8750 | { |
b105ef41 | 8751 | /* Aggregates 5 to 8 bytes in size are returned in general |
8752 | registers r28-r29 in the same manner as other non | |
8753 | floating-point objects. The data is right-justified and | |
8754 | zero-extended to 64 bits. This is opposite to the normal | |
8755 | justification used on big endian targets and requires | |
8756 | special treatment. */ | |
8757 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, | |
8758 | gen_rtx_REG (DImode, 28), const0_rtx); | |
8759 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc)); | |
58a72cce | 8760 | } |
58a72cce | 8761 | } |
8762 | ||
8763 | if ((INTEGRAL_TYPE_P (valtype) | |
8764 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
8765 | || POINTER_TYPE_P (valtype)) | |
8766 | valmode = word_mode; | |
8767 | else | |
8768 | valmode = TYPE_MODE (valtype); | |
8769 | ||
8770 | if (TREE_CODE (valtype) == REAL_TYPE | |
b105ef41 | 8771 | && !AGGREGATE_TYPE_P (valtype) |
58a72cce | 8772 | && TYPE_MODE (valtype) != TFmode |
8773 | && !TARGET_SOFT_FLOAT) | |
8774 | return gen_rtx_REG (valmode, 32); | |
8775 | ||
8776 | return gen_rtx_REG (valmode, 28); | |
8777 | } | |
8778 | ||
5e3c5739 | 8779 | /* Return the location of a parameter that is passed in a register or NULL |
8780 | if the parameter has any component that is passed in memory. | |
8781 | ||
8782 | This is new code and will be pushed to into the net sources after | |
9840d99d | 8783 | further testing. |
5e3c5739 | 8784 | |
8785 | ??? We might want to restructure this so that it looks more like other | |
8786 | ports. */ | |
8787 | rtx | |
5c1d8983 | 8788 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, |
8789 | int named ATTRIBUTE_UNUSED) | |
5e3c5739 | 8790 | { |
8791 | int max_arg_words = (TARGET_64BIT ? 8 : 4); | |
2a075f91 | 8792 | int alignment = 0; |
ac965869 | 8793 | int arg_size; |
5e3c5739 | 8794 | int fpr_reg_base; |
8795 | int gpr_reg_base; | |
8796 | rtx retval; | |
8797 | ||
ac965869 | 8798 | if (mode == VOIDmode) |
8799 | return NULL_RTX; | |
8800 | ||
8801 | arg_size = FUNCTION_ARG_SIZE (mode, type); | |
8802 | ||
8803 | /* If this arg would be passed partially or totally on the stack, then | |
f054eb3c | 8804 | this routine should return zero. pa_arg_partial_bytes will |
ac965869 | 8805 | handle arguments which are split between regs and stack slots if |
8806 | the ABI mandates split arguments. */ | |
5e3c5739 | 8807 | if (! TARGET_64BIT) |
8808 | { | |
ac965869 | 8809 | /* The 32-bit ABI does not split arguments. */ |
8810 | if (cum->words + arg_size > max_arg_words) | |
5e3c5739 | 8811 | return NULL_RTX; |
8812 | } | |
8813 | else | |
8814 | { | |
2a075f91 | 8815 | if (arg_size > 1) |
8816 | alignment = cum->words & 1; | |
ac965869 | 8817 | if (cum->words + alignment >= max_arg_words) |
5e3c5739 | 8818 | return NULL_RTX; |
8819 | } | |
8820 | ||
8821 | /* The 32bit ABIs and the 64bit ABIs are rather different, | |
8822 | particularly in their handling of FP registers. We might | |
8823 | be able to cleverly share code between them, but I'm not | |
9aadea62 | 8824 | going to bother in the hope that splitting them up results |
2a075f91 | 8825 | in code that is more easily understood. */ |
5e3c5739 | 8826 | |
5e3c5739 | 8827 | if (TARGET_64BIT) |
8828 | { | |
8829 | /* Advance the base registers to their current locations. | |
8830 | ||
8831 | Remember, gprs grow towards smaller register numbers while | |
2a075f91 | 8832 | fprs grow to higher register numbers. Also remember that |
8833 | although FP regs are 32-bit addressable, we pretend that | |
8834 | the registers are 64-bits wide. */ | |
5e3c5739 | 8835 | gpr_reg_base = 26 - cum->words; |
8836 | fpr_reg_base = 32 + cum->words; | |
9840d99d | 8837 | |
ac965869 | 8838 | /* Arguments wider than one word and small aggregates need special |
8839 | treatment. */ | |
8840 | if (arg_size > 1 | |
8841 | || mode == BLKmode | |
8842 | || (type && AGGREGATE_TYPE_P (type))) | |
5e3c5739 | 8843 | { |
2a075f91 | 8844 | /* Double-extended precision (80-bit), quad-precision (128-bit) |
8845 | and aggregates including complex numbers are aligned on | |
8846 | 128-bit boundaries. The first eight 64-bit argument slots | |
8847 | are associated one-to-one, with general registers r26 | |
8848 | through r19, and also with floating-point registers fr4 | |
8849 | through fr11. Arguments larger than one word are always | |
ac965869 | 8850 | passed in general registers. |
8851 | ||
8852 | Using a PARALLEL with a word mode register results in left | |
8853 | justified data on a big-endian target. */ | |
2a075f91 | 8854 | |
8855 | rtx loc[8]; | |
8856 | int i, offset = 0, ub = arg_size; | |
8857 | ||
8858 | /* Align the base register. */ | |
8859 | gpr_reg_base -= alignment; | |
8860 | ||
8861 | ub = MIN (ub, max_arg_words - cum->words - alignment); | |
8862 | for (i = 0; i < ub; i++) | |
5e3c5739 | 8863 | { |
2a075f91 | 8864 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, |
8865 | gen_rtx_REG (DImode, gpr_reg_base), | |
8866 | GEN_INT (offset)); | |
8867 | gpr_reg_base -= 1; | |
8868 | offset += 8; | |
5e3c5739 | 8869 | } |
2a075f91 | 8870 | |
8871 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc)); | |
5e3c5739 | 8872 | } |
ac965869 | 8873 | } |
5e3c5739 | 8874 | else |
8875 | { | |
8876 | /* If the argument is larger than a word, then we know precisely | |
8877 | which registers we must use. */ | |
2a075f91 | 8878 | if (arg_size > 1) |
5e3c5739 | 8879 | { |
8880 | if (cum->words) | |
8881 | { | |
8882 | gpr_reg_base = 23; | |
8883 | fpr_reg_base = 38; | |
8884 | } | |
8885 | else | |
8886 | { | |
8887 | gpr_reg_base = 25; | |
8888 | fpr_reg_base = 34; | |
8889 | } | |
ac965869 | 8890 | |
8891 | /* Structures 5 to 8 bytes in size are passed in the general | |
8892 | registers in the same manner as other non floating-point | |
8893 | objects. The data is right-justified and zero-extended | |
9f0b40a7 | 8894 | to 64 bits. This is opposite to the normal justification |
8895 | used on big endian targets and requires special treatment. | |
8896 | We now define BLOCK_REG_PADDING to pad these objects. */ | |
b105ef41 | 8897 | if (mode == BLKmode || (type && AGGREGATE_TYPE_P (type))) |
ac965869 | 8898 | { |
58a72cce | 8899 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, |
8900 | gen_rtx_REG (DImode, gpr_reg_base), | |
8901 | const0_rtx); | |
b105ef41 | 8902 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc)); |
ac965869 | 8903 | } |
5e3c5739 | 8904 | } |
8905 | else | |
8906 | { | |
8907 | /* We have a single word (32 bits). A simple computation | |
8908 | will get us the register #s we need. */ | |
8909 | gpr_reg_base = 26 - cum->words; | |
8910 | fpr_reg_base = 32 + 2 * cum->words; | |
8911 | } | |
8912 | } | |
8913 | ||
9503b0f7 | 8914 | /* Determine if the argument needs to be passed in both general and |
5e3c5739 | 8915 | floating point registers. */ |
9503b0f7 | 8916 | if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32) |
8917 | /* If we are doing soft-float with portable runtime, then there | |
8918 | is no need to worry about FP regs. */ | |
f336e0bc | 8919 | && !TARGET_SOFT_FLOAT |
9503b0f7 | 8920 | /* The parameter must be some kind of float, else we can just |
8921 | pass it in integer registers. */ | |
8922 | && FLOAT_MODE_P (mode) | |
8923 | /* The target function must not have a prototype. */ | |
8924 | && cum->nargs_prototype <= 0 | |
8925 | /* libcalls do not need to pass items in both FP and general | |
8926 | registers. */ | |
8927 | && type != NULL_TREE | |
f336e0bc | 8928 | /* All this hair applies to "outgoing" args only. This includes |
8929 | sibcall arguments setup with FUNCTION_INCOMING_ARG. */ | |
8930 | && !cum->incoming) | |
9503b0f7 | 8931 | /* Also pass outgoing floating arguments in both registers in indirect |
8932 | calls with the 32 bit ABI and the HP assembler since there is no | |
8933 | way to the specify argument locations in static functions. */ | |
f336e0bc | 8934 | || (!TARGET_64BIT |
8935 | && !TARGET_GAS | |
8936 | && !cum->incoming | |
9503b0f7 | 8937 | && cum->indirect |
8938 | && FLOAT_MODE_P (mode))) | |
5e3c5739 | 8939 | { |
8940 | retval | |
8941 | = gen_rtx_PARALLEL | |
8942 | (mode, | |
8943 | gen_rtvec (2, | |
8944 | gen_rtx_EXPR_LIST (VOIDmode, | |
8945 | gen_rtx_REG (mode, fpr_reg_base), | |
8946 | const0_rtx), | |
8947 | gen_rtx_EXPR_LIST (VOIDmode, | |
8948 | gen_rtx_REG (mode, gpr_reg_base), | |
8949 | const0_rtx))); | |
8950 | } | |
8951 | else | |
8952 | { | |
8953 | /* See if we should pass this parameter in a general register. */ | |
8954 | if (TARGET_SOFT_FLOAT | |
8955 | /* Indirect calls in the normal 32bit ABI require all arguments | |
8956 | to be passed in general registers. */ | |
8957 | || (!TARGET_PORTABLE_RUNTIME | |
8958 | && !TARGET_64BIT | |
a052da6f | 8959 | && !TARGET_ELF32 |
5e3c5739 | 8960 | && cum->indirect) |
8961 | /* If the parameter is not a floating point parameter, then | |
8962 | it belongs in GPRs. */ | |
b105ef41 | 8963 | || !FLOAT_MODE_P (mode) |
8964 | /* Structure with single SFmode field belongs in GPR. */ | |
8965 | || (type && AGGREGATE_TYPE_P (type))) | |
5e3c5739 | 8966 | retval = gen_rtx_REG (mode, gpr_reg_base); |
8967 | else | |
8968 | retval = gen_rtx_REG (mode, fpr_reg_base); | |
8969 | } | |
8970 | return retval; | |
8971 | } | |
8972 | ||
8973 | ||
8974 | /* If this arg would be passed totally in registers or totally on the stack, | |
f054eb3c | 8975 | then this routine should return zero. */ |
8976 | ||
8977 | static int | |
8978 | pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
8979 | tree type, bool named ATTRIBUTE_UNUSED) | |
5e3c5739 | 8980 | { |
b7d86581 | 8981 | unsigned int max_arg_words = 8; |
8982 | unsigned int offset = 0; | |
5e3c5739 | 8983 | |
f054eb3c | 8984 | if (!TARGET_64BIT) |
8985 | return 0; | |
8986 | ||
b7d86581 | 8987 | if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1)) |
5e3c5739 | 8988 | offset = 1; |
8989 | ||
b7d86581 | 8990 | if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words) |
6dc3b0d9 | 8991 | /* Arg fits fully into registers. */ |
5e3c5739 | 8992 | return 0; |
9840d99d | 8993 | else if (cum->words + offset >= max_arg_words) |
6dc3b0d9 | 8994 | /* Arg fully on the stack. */ |
5e3c5739 | 8995 | return 0; |
8996 | else | |
6dc3b0d9 | 8997 | /* Arg is split. */ |
f054eb3c | 8998 | return (max_arg_words - cum->words - offset) * UNITS_PER_WORD; |
5e3c5739 | 8999 | } |
9000 | ||
9001 | ||
99c11254 | 9002 | /* Return a string to output before text in the current function. |
916c9cef | 9003 | |
9004 | This function is only used with SOM. Because we don't support | |
9005 | named subspaces, we can only create a new subspace or switch back | |
99c11254 | 9006 | to the default text subspace. */ |
916c9cef | 9007 | const char * |
9008 | som_text_section_asm_op (void) | |
9009 | { | |
99c11254 | 9010 | if (!TARGET_SOM) |
9011 | return ""; | |
9012 | ||
9013 | if (TARGET_GAS) | |
916c9cef | 9014 | { |
9015 | if (cfun && !cfun->machine->in_nsubspa) | |
9016 | { | |
9017 | /* We only want to emit a .nsubspa directive once at the | |
9018 | start of the function. */ | |
9019 | cfun->machine->in_nsubspa = 1; | |
9020 | ||
9021 | /* Create a new subspace for the text. This provides | |
9022 | better stub placement and one-only functions. */ | |
9023 | if (cfun->decl | |
9024 | && DECL_ONE_ONLY (cfun->decl) | |
9025 | && !DECL_WEAK (cfun->decl)) | |
99c11254 | 9026 | return |
9027 | "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT"; | |
916c9cef | 9028 | |
99c11254 | 9029 | return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$"; |
916c9cef | 9030 | } |
9031 | else | |
9032 | { | |
9033 | /* There isn't a current function or the body of the current | |
9034 | function has been completed. So, we are changing to the | |
9035 | text section to output debugging information. Do this in | |
9036 | the default text section. We need to forget that we are | |
99c11254 | 9037 | in the text section so that the function text_section in |
9038 | varasm.c will call us the next time around. */ | |
916c9cef | 9039 | forget_section (); |
9040 | } | |
9041 | } | |
9042 | ||
99c11254 | 9043 | return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$"; |
916c9cef | 9044 | } |
9045 | ||
52470889 | 9046 | /* On hpux10, the linker will give an error if we have a reference |
9047 | in the read-only data section to a symbol defined in a shared | |
9048 | library. Therefore, expressions that might require a reloc can | |
9049 | not be placed in the read-only data section. */ | |
9050 | ||
9051 | static void | |
b572d1a5 | 9052 | pa_select_section (tree exp, int reloc, |
9053 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
52470889 | 9054 | { |
9055 | if (TREE_CODE (exp) == VAR_DECL | |
9056 | && TREE_READONLY (exp) | |
9057 | && !TREE_THIS_VOLATILE (exp) | |
9058 | && DECL_INITIAL (exp) | |
9059 | && (DECL_INITIAL (exp) == error_mark_node | |
9060 | || TREE_CONSTANT (DECL_INITIAL (exp))) | |
9061 | && !reloc) | |
916c9cef | 9062 | { |
9063 | if (TARGET_SOM | |
9064 | && DECL_ONE_ONLY (exp) | |
9065 | && !DECL_WEAK (exp)) | |
99c11254 | 9066 | som_one_only_readonly_data_section (); |
916c9cef | 9067 | else |
9068 | readonly_data_section (); | |
9069 | } | |
ce45a448 | 9070 | else if (CONSTANT_CLASS_P (exp) && !reloc) |
52470889 | 9071 | readonly_data_section (); |
916c9cef | 9072 | else if (TARGET_SOM |
9073 | && TREE_CODE (exp) == VAR_DECL | |
9074 | && DECL_ONE_ONLY (exp) | |
2455c36b | 9075 | && !DECL_WEAK (exp)) |
99c11254 | 9076 | som_one_only_data_section (); |
52470889 | 9077 | else |
9078 | data_section (); | |
9079 | } | |
1f3233d1 | 9080 | |
67c1e638 | 9081 | static void |
5c1d8983 | 9082 | pa_globalize_label (FILE *stream, const char *name) |
67c1e638 | 9083 | { |
9084 | /* We only handle DATA objects here, functions are globalized in | |
9085 | ASM_DECLARE_FUNCTION_NAME. */ | |
9086 | if (! FUNCTION_NAME_P (name)) | |
9087 | { | |
9088 | fputs ("\t.EXPORT ", stream); | |
9089 | assemble_name (stream, name); | |
9090 | fputs (",DATA\n", stream); | |
9091 | } | |
9092 | } | |
b8debbe8 | 9093 | |
6644435d | 9094 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
9095 | ||
b8debbe8 | 9096 | static rtx |
9097 | pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
9098 | int incoming ATTRIBUTE_UNUSED) | |
9099 | { | |
9100 | return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM); | |
9101 | } | |
9102 | ||
6644435d | 9103 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
9104 | ||
b8debbe8 | 9105 | bool |
9106 | pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
9107 | { | |
9108 | /* SOM ABI says that objects larger than 64 bits are returned in memory. | |
9109 | PA64 ABI says that objects larger than 128 bits are returned in memory. | |
9110 | Note, int_size_in_bytes can return -1 if the size of the object is | |
9111 | variable or larger than the maximum value that can be expressed as | |
9112 | a HOST_WIDE_INT. It can also return zero for an empty type. The | |
9113 | simplest way to handle variable and empty types is to pass them in | |
9114 | memory. This avoids problems in defining the boundaries of argument | |
9115 | slots, allocating registers, etc. */ | |
9116 | return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8) | |
9117 | || int_size_in_bytes (type) <= 0); | |
9118 | } | |
9119 | ||
5f43b4f6 | 9120 | /* Structure to hold declaration and name of external symbols that are |
9121 | emitted by GCC. We generate a vector of these symbols and output them | |
9122 | at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true. | |
9123 | This avoids putting out names that are never really used. */ | |
9124 | ||
046bfc77 | 9125 | typedef struct extern_symbol GTY(()) |
5f43b4f6 | 9126 | { |
9127 | tree decl; | |
9128 | const char *name; | |
046bfc77 | 9129 | } extern_symbol; |
5f43b4f6 | 9130 | |
9131 | /* Define gc'd vector type for extern_symbol. */ | |
046bfc77 | 9132 | DEF_VEC_O(extern_symbol); |
9133 | DEF_VEC_ALLOC_O(extern_symbol,gc); | |
5f43b4f6 | 9134 | |
9135 | /* Vector of extern_symbol pointers. */ | |
046bfc77 | 9136 | static GTY(()) VEC(extern_symbol,gc) *extern_symbols; |
5f43b4f6 | 9137 | |
9138 | #ifdef ASM_OUTPUT_EXTERNAL_REAL | |
9139 | /* Mark DECL (name NAME) as an external reference (assembler output | |
9140 | file FILE). This saves the names to output at the end of the file | |
9141 | if actually referenced. */ | |
9142 | ||
9143 | void | |
9144 | pa_hpux_asm_output_external (FILE *file, tree decl, const char *name) | |
9145 | { | |
046bfc77 | 9146 | extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL); |
5f43b4f6 | 9147 | |
9148 | gcc_assert (file == asm_out_file); | |
9149 | p->decl = decl; | |
9150 | p->name = name; | |
5f43b4f6 | 9151 | } |
9152 | ||
9153 | /* Output text required at the end of an assembler file. | |
9154 | This includes deferred plabels and .import directives for | |
9155 | all external symbols that were actually referenced. */ | |
9156 | ||
9157 | static void | |
9158 | pa_hpux_file_end (void) | |
9159 | { | |
9160 | unsigned int i; | |
046bfc77 | 9161 | extern_symbol *p; |
5f43b4f6 | 9162 | |
9163 | output_deferred_plabels (); | |
9164 | ||
9165 | for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++) | |
9166 | { | |
9167 | tree decl = p->decl; | |
9168 | ||
9169 | if (!TREE_ASM_WRITTEN (decl) | |
9170 | && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0))) | |
9171 | ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name); | |
9172 | } | |
9173 | ||
046bfc77 | 9174 | VEC_free (extern_symbol, gc, extern_symbols); |
5f43b4f6 | 9175 | } |
9176 | #endif | |
9177 | ||
1f3233d1 | 9178 | #include "gt-pa.h" |