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87ad11b0 | 1 | /* Subroutines for insn-output.c for HPPA. |
a9ac13e4 | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
fbf5169c | 3 | 2002, 2003, 2004 Free Software Foundation, Inc. |
87ad11b0 | 4 | Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c |
5 | ||
5c1d8983 | 6 | This file is part of GCC. |
87ad11b0 | 7 | |
5c1d8983 | 8 | GCC is free software; you can redistribute it and/or modify |
87ad11b0 | 9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
5c1d8983 | 13 | GCC is distributed in the hope that it will be useful, |
87ad11b0 | 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
5c1d8983 | 19 | along with GCC; see the file COPYING. If not, write to |
01e379d0 | 20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
87ad11b0 | 22 | |
87ad11b0 | 23 | #include "config.h" |
b1ca791d | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
87ad11b0 | 27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
87ad11b0 | 33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "tree.h" | |
9d2d8bd6 | 36 | #include "output.h" |
a584fe8a | 37 | #include "except.h" |
32509e56 | 38 | #include "expr.h" |
d8fc4d0b | 39 | #include "optabs.h" |
d8fc4d0b | 40 | #include "reload.h" |
d7e2f694 | 41 | #include "integrate.h" |
0a893c29 | 42 | #include "function.h" |
b1ca791d | 43 | #include "toplev.h" |
5cb4669a | 44 | #include "ggc.h" |
611a88e1 | 45 | #include "recog.h" |
a584fe8a | 46 | #include "predict.h" |
611a88e1 | 47 | #include "tm_p.h" |
a767736d | 48 | #include "target.h" |
49 | #include "target-def.h" | |
87ad11b0 | 50 | |
5c1d8983 | 51 | static int hppa_use_dfa_pipeline_interface (void); |
bea4bad2 | 52 | |
53 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE | |
54 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface | |
55 | ||
56 | static int | |
5c1d8983 | 57 | hppa_use_dfa_pipeline_interface (void) |
bea4bad2 | 58 | { |
59 | return 1; | |
60 | } | |
61 | ||
cde3e16c | 62 | /* Return nonzero if there is a bypass for the output of |
63 | OUT_INSN and the fp store IN_INSN. */ | |
64 | int | |
5c1d8983 | 65 | hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn) |
cde3e16c | 66 | { |
67 | enum machine_mode store_mode; | |
68 | enum machine_mode other_mode; | |
69 | rtx set; | |
70 | ||
71 | if (recog_memoized (in_insn) < 0 | |
72 | || get_attr_type (in_insn) != TYPE_FPSTORE | |
73 | || recog_memoized (out_insn) < 0) | |
74 | return 0; | |
75 | ||
76 | store_mode = GET_MODE (SET_SRC (PATTERN (in_insn))); | |
77 | ||
78 | set = single_set (out_insn); | |
79 | if (!set) | |
80 | return 0; | |
81 | ||
82 | other_mode = GET_MODE (SET_SRC (set)); | |
83 | ||
84 | return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode)); | |
85 | } | |
86 | ||
87 | ||
cc858176 | 88 | #ifndef DO_FRAME_NOTES |
89 | #ifdef INCOMING_RETURN_ADDR_RTX | |
90 | #define DO_FRAME_NOTES 1 | |
91 | #else | |
92 | #define DO_FRAME_NOTES 0 | |
93 | #endif | |
94 | #endif | |
95 | ||
dbd3d89d | 96 | static void copy_reg_pointer (rtx, rtx); |
5c1d8983 | 97 | static int hppa_address_cost (rtx); |
98 | static bool hppa_rtx_costs (rtx, int, int, int *); | |
99 | static inline rtx force_mode (enum machine_mode, rtx); | |
100 | static void pa_reorg (void); | |
101 | static void pa_combine_instructions (void); | |
102 | static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx); | |
103 | static int forward_branch_p (rtx); | |
104 | static int shadd_constant_p (int); | |
105 | static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *); | |
a7e1bb24 | 106 | static int compute_movstr_length (rtx); |
107 | static int compute_clrstr_length (rtx); | |
5c1d8983 | 108 | static bool pa_assemble_integer (rtx, unsigned int, int); |
109 | static void remove_useless_addtr_insns (int); | |
6bcdc1fb | 110 | static void store_reg (int, HOST_WIDE_INT, int); |
111 | static void store_reg_modify (int, int, HOST_WIDE_INT); | |
112 | static void load_reg (int, HOST_WIDE_INT, int); | |
113 | static void set_reg_plus_d (int, int, HOST_WIDE_INT, int); | |
5c1d8983 | 114 | static void pa_output_function_prologue (FILE *, HOST_WIDE_INT); |
115 | static void update_total_code_bytes (int); | |
116 | static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
117 | static int pa_adjust_cost (rtx, rtx, rtx, int); | |
118 | static int pa_adjust_priority (rtx, int); | |
119 | static int pa_issue_rate (void); | |
120 | static void pa_select_section (tree, int, unsigned HOST_WIDE_INT) | |
52470889 | 121 | ATTRIBUTE_UNUSED; |
5c1d8983 | 122 | static void pa_encode_section_info (tree, rtx, int); |
123 | static const char *pa_strip_name_encoding (const char *); | |
124 | static bool pa_function_ok_for_sibcall (tree, tree); | |
125 | static void pa_globalize_label (FILE *, const char *) | |
63b8cd48 | 126 | ATTRIBUTE_UNUSED; |
5c1d8983 | 127 | static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
128 | HOST_WIDE_INT, tree); | |
de419443 | 129 | #if !defined(USE_COLLECT2) |
5c1d8983 | 130 | static void pa_asm_out_constructor (rtx, int); |
131 | static void pa_asm_out_destructor (rtx, int); | |
de419443 | 132 | #endif |
5c1d8983 | 133 | static void pa_init_builtins (void); |
b8debbe8 | 134 | static rtx hppa_builtin_saveregs (void); |
5c1d8983 | 135 | static void copy_fp_args (rtx) ATTRIBUTE_UNUSED; |
136 | static int length_fp_args (rtx) ATTRIBUTE_UNUSED; | |
137 | static struct deferred_plabel *get_plabel (const char *) | |
ece88821 | 138 | ATTRIBUTE_UNUSED; |
5c1d8983 | 139 | static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED; |
140 | static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED; | |
141 | static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED; | |
142 | static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED; | |
143 | static void pa_elf_file_start (void) ATTRIBUTE_UNUSED; | |
144 | static void pa_som_file_start (void) ATTRIBUTE_UNUSED; | |
145 | static void pa_linux_file_start (void) ATTRIBUTE_UNUSED; | |
146 | static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED; | |
147 | static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED; | |
148 | static void output_deferred_plabels (void); | |
f2f543a3 | 149 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
150 | static void pa_hpux_init_libfuncs (void); | |
151 | #endif | |
b8debbe8 | 152 | static rtx pa_struct_value_rtx (tree, int); |
9d3ddb8f | 153 | |
87ad11b0 | 154 | /* Save the operands last given to a compare for use when we |
155 | generate a scc or bcc insn. */ | |
87ad11b0 | 156 | rtx hppa_compare_op0, hppa_compare_op1; |
157 | enum cmp_type hppa_branch_type; | |
158 | ||
134b4858 | 159 | /* Which cpu we are scheduling for. */ |
160 | enum processor_type pa_cpu; | |
161 | ||
162 | /* String to hold which cpu we are scheduling for. */ | |
611a88e1 | 163 | const char *pa_cpu_string; |
134b4858 | 164 | |
4dc42288 | 165 | /* Which architecture we are generating code for. */ |
166 | enum architecture_type pa_arch; | |
167 | ||
168 | /* String to hold which architecture we are generating code for. */ | |
611a88e1 | 169 | const char *pa_arch_string; |
4dc42288 | 170 | |
a9960cdc | 171 | /* Counts for the number of callee-saved general and floating point |
172 | registers which were saved by the current function's prologue. */ | |
173 | static int gr_saved, fr_saved; | |
174 | ||
5c1d8983 | 175 | static rtx find_addr_reg (rtx); |
87ad11b0 | 176 | |
2247cc5f | 177 | /* Keep track of the number of bytes we have output in the CODE subspace |
06ddb6f8 | 178 | during this compilation so we'll know when to emit inline long-calls. */ |
ece88821 | 179 | unsigned long total_code_bytes; |
06ddb6f8 | 180 | |
2247cc5f | 181 | /* The last address of the previous function plus the number of bytes in |
182 | associated thunks that have been output. This is used to determine if | |
183 | a thunk can use an IA-relative branch to reach its target function. */ | |
184 | static int last_address; | |
185 | ||
e3f53689 | 186 | /* Variables to handle plabels that we discover are necessary at assembly |
01cc3b75 | 187 | output time. They are output after the current function. */ |
1f3233d1 | 188 | struct deferred_plabel GTY(()) |
e3f53689 | 189 | { |
190 | rtx internal_label; | |
8d0cec1a | 191 | const char *name; |
1f3233d1 | 192 | }; |
193 | static GTY((length ("n_deferred_plabels"))) struct deferred_plabel * | |
194 | deferred_plabels; | |
e11bd7e5 | 195 | static size_t n_deferred_plabels = 0; |
f6940372 | 196 | |
a767736d | 197 | \f |
198 | /* Initialize the GCC target structure. */ | |
58356836 | 199 | |
200 | #undef TARGET_ASM_ALIGNED_HI_OP | |
201 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
202 | #undef TARGET_ASM_ALIGNED_SI_OP | |
203 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
204 | #undef TARGET_ASM_ALIGNED_DI_OP | |
205 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
206 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
207 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
208 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
209 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
210 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
211 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
212 | #undef TARGET_ASM_INTEGER | |
213 | #define TARGET_ASM_INTEGER pa_assemble_integer | |
214 | ||
17d9b0c3 | 215 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
216 | #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue | |
217 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
218 | #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue | |
e3f53689 | 219 | |
747af5e7 | 220 | #undef TARGET_SCHED_ADJUST_COST |
221 | #define TARGET_SCHED_ADJUST_COST pa_adjust_cost | |
222 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
223 | #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority | |
224 | #undef TARGET_SCHED_ISSUE_RATE | |
225 | #define TARGET_SCHED_ISSUE_RATE pa_issue_rate | |
226 | ||
7811991d | 227 | #undef TARGET_ENCODE_SECTION_INFO |
228 | #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info | |
7b4a38a6 | 229 | #undef TARGET_STRIP_NAME_ENCODING |
230 | #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding | |
7811991d | 231 | |
805e22b2 | 232 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
233 | #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall | |
234 | ||
6988553d | 235 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
236 | #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk | |
eb344f43 | 237 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
238 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
6988553d | 239 | |
f6940372 | 240 | #undef TARGET_ASM_FILE_END |
241 | #define TARGET_ASM_FILE_END output_deferred_plabels | |
242 | ||
de419443 | 243 | #if !defined(USE_COLLECT2) |
244 | #undef TARGET_ASM_CONSTRUCTOR | |
245 | #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor | |
246 | #undef TARGET_ASM_DESTRUCTOR | |
247 | #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor | |
248 | #endif | |
249 | ||
ffa8918b | 250 | #undef TARGET_INIT_BUILTINS |
251 | #define TARGET_INIT_BUILTINS pa_init_builtins | |
252 | ||
fab7adbf | 253 | #undef TARGET_RTX_COSTS |
254 | #define TARGET_RTX_COSTS hppa_rtx_costs | |
ec0457a8 | 255 | #undef TARGET_ADDRESS_COST |
256 | #define TARGET_ADDRESS_COST hppa_address_cost | |
fab7adbf | 257 | |
2efea8c0 | 258 | #undef TARGET_MACHINE_DEPENDENT_REORG |
259 | #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg | |
260 | ||
f2f543a3 | 261 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
262 | #undef TARGET_INIT_LIBFUNCS | |
263 | #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs | |
264 | #endif | |
265 | ||
b8debbe8 | 266 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
267 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
268 | #undef TARGET_PROMOTE_PROTOTYPES | |
269 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
270 | ||
271 | #undef TARGET_STRUCT_VALUE_RTX | |
272 | #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx | |
273 | #undef TARGET_RETURN_IN_MEMORY | |
274 | #define TARGET_RETURN_IN_MEMORY pa_return_in_memory | |
275 | ||
276 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
277 | #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs | |
278 | ||
57e4bbfb | 279 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 280 | \f |
134b4858 | 281 | void |
5c1d8983 | 282 | override_options (void) |
134b4858 | 283 | { |
b3b62da8 | 284 | if (pa_cpu_string == NULL) |
285 | pa_cpu_string = TARGET_SCHED_DEFAULT; | |
286 | ||
287 | if (! strcmp (pa_cpu_string, "8000")) | |
288 | { | |
289 | pa_cpu_string = "8000"; | |
290 | pa_cpu = PROCESSOR_8000; | |
291 | } | |
292 | else if (! strcmp (pa_cpu_string, "7100")) | |
134b4858 | 293 | { |
294 | pa_cpu_string = "7100"; | |
295 | pa_cpu = PROCESSOR_7100; | |
296 | } | |
b3b62da8 | 297 | else if (! strcmp (pa_cpu_string, "700")) |
a87e1e15 | 298 | { |
299 | pa_cpu_string = "700"; | |
300 | pa_cpu = PROCESSOR_700; | |
301 | } | |
b3b62da8 | 302 | else if (! strcmp (pa_cpu_string, "7100LC")) |
134b4858 | 303 | { |
304 | pa_cpu_string = "7100LC"; | |
305 | pa_cpu = PROCESSOR_7100LC; | |
306 | } | |
b3b62da8 | 307 | else if (! strcmp (pa_cpu_string, "7200")) |
b4e0d953 | 308 | { |
309 | pa_cpu_string = "7200"; | |
310 | pa_cpu = PROCESSOR_7200; | |
311 | } | |
b3b62da8 | 312 | else if (! strcmp (pa_cpu_string, "7300")) |
bea4bad2 | 313 | { |
314 | pa_cpu_string = "7300"; | |
315 | pa_cpu = PROCESSOR_7300; | |
316 | } | |
134b4858 | 317 | else |
318 | { | |
bea4bad2 | 319 | warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string); |
134b4858 | 320 | } |
c7a4e712 | 321 | |
4dc42288 | 322 | /* Set the instruction set architecture. */ |
323 | if (pa_arch_string && ! strcmp (pa_arch_string, "1.0")) | |
324 | { | |
325 | pa_arch_string = "1.0"; | |
326 | pa_arch = ARCHITECTURE_10; | |
327 | target_flags &= ~(MASK_PA_11 | MASK_PA_20); | |
328 | } | |
329 | else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1")) | |
330 | { | |
331 | pa_arch_string = "1.1"; | |
332 | pa_arch = ARCHITECTURE_11; | |
333 | target_flags &= ~MASK_PA_20; | |
334 | target_flags |= MASK_PA_11; | |
335 | } | |
336 | else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0")) | |
337 | { | |
338 | pa_arch_string = "2.0"; | |
339 | pa_arch = ARCHITECTURE_20; | |
340 | target_flags |= MASK_PA_11 | MASK_PA_20; | |
341 | } | |
342 | else if (pa_arch_string) | |
343 | { | |
68435912 | 344 | warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string); |
4dc42288 | 345 | } |
346 | ||
7c5101fc | 347 | /* Unconditional branches in the delay slot are not compatible with dwarf2 |
348 | call frame information. There is no benefit in using this optimization | |
349 | on PA8000 and later processors. */ | |
350 | if (pa_cpu >= PROCESSOR_8000 | |
351 | || (! USING_SJLJ_EXCEPTIONS && flag_exceptions) | |
352 | || flag_unwind_tables) | |
353 | target_flags &= ~MASK_JUMP_IN_DELAY; | |
354 | ||
c7a4e712 | 355 | if (flag_pic && TARGET_PORTABLE_RUNTIME) |
356 | { | |
357 | warning ("PIC code generation is not supported in the portable runtime model\n"); | |
358 | } | |
359 | ||
b29897dd | 360 | if (flag_pic && TARGET_FAST_INDIRECT_CALLS) |
c7a4e712 | 361 | { |
ad87de1e | 362 | warning ("PIC code generation is not compatible with fast indirect calls\n"); |
c7a4e712 | 363 | } |
751e64a1 | 364 | |
5bd7b548 | 365 | if (! TARGET_GAS && write_symbols != NO_DEBUG) |
366 | { | |
367 | warning ("-g is only supported when using GAS on this processor,"); | |
68435912 | 368 | warning ("-g option disabled"); |
5bd7b548 | 369 | write_symbols = NO_DEBUG; |
370 | } | |
5cb4669a | 371 | |
fc44315f | 372 | /* We only support the "big PIC" model now. And we always generate PIC |
373 | code when in 64bit mode. */ | |
374 | if (flag_pic == 1 || TARGET_64BIT) | |
5e3c5739 | 375 | flag_pic = 2; |
376 | ||
58356836 | 377 | /* We can't guarantee that .dword is available for 32-bit targets. */ |
378 | if (UNITS_PER_WORD == 4) | |
379 | targetm.asm_out.aligned_op.di = NULL; | |
380 | ||
381 | /* The unaligned ops are only available when using GAS. */ | |
382 | if (!TARGET_GAS) | |
383 | { | |
384 | targetm.asm_out.unaligned_op.hi = NULL; | |
385 | targetm.asm_out.unaligned_op.si = NULL; | |
386 | targetm.asm_out.unaligned_op.di = NULL; | |
387 | } | |
134b4858 | 388 | } |
389 | ||
066397a3 | 390 | static void |
5c1d8983 | 391 | pa_init_builtins (void) |
ffa8918b | 392 | { |
393 | #ifdef DONT_HAVE_FPUTC_UNLOCKED | |
394 | built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE; | |
5ddc8fb8 | 395 | implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE; |
ffa8918b | 396 | #endif |
397 | } | |
398 | ||
dbd3d89d | 399 | /* If FROM is a probable pointer register, mark TO as a probable |
400 | pointer register with the same pointer alignment as FROM. */ | |
401 | ||
402 | static void | |
403 | copy_reg_pointer (rtx to, rtx from) | |
404 | { | |
405 | if (REG_POINTER (from)) | |
406 | mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from))); | |
407 | } | |
408 | ||
e911aedf | 409 | /* Return nonzero only if OP is a register of mode MODE, |
891b55b4 | 410 | or CONST0_RTX. */ |
87ad11b0 | 411 | int |
5c1d8983 | 412 | reg_or_0_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 413 | { |
891b55b4 | 414 | return (op == CONST0_RTX (mode) || register_operand (op, mode)); |
87ad11b0 | 415 | } |
416 | ||
e911aedf | 417 | /* Return nonzero if OP is suitable for use in a call to a named |
575e0eb4 | 418 | function. |
419 | ||
9dc4cbf1 | 420 | For 2.5 try to eliminate either call_operand_address or |
575e0eb4 | 421 | function_label_operand, they perform very similar functions. */ |
87ad11b0 | 422 | int |
5c1d8983 | 423 | call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 424 | { |
2db59d96 | 425 | return (GET_MODE (op) == word_mode |
426 | && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME); | |
87ad11b0 | 427 | } |
428 | ||
6d36483b | 429 | /* Return 1 if X contains a symbolic expression. We know these |
430 | expressions will have one of a few well defined forms, so | |
347b5848 | 431 | we need only check those forms. */ |
432 | int | |
5c1d8983 | 433 | symbolic_expression_p (rtx x) |
347b5848 | 434 | { |
435 | ||
6dc3b0d9 | 436 | /* Strip off any HIGH. */ |
347b5848 | 437 | if (GET_CODE (x) == HIGH) |
438 | x = XEXP (x, 0); | |
439 | ||
440 | return (symbolic_operand (x, VOIDmode)); | |
441 | } | |
442 | ||
87ad11b0 | 443 | int |
5c1d8983 | 444 | symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 445 | { |
446 | switch (GET_CODE (op)) | |
447 | { | |
448 | case SYMBOL_REF: | |
449 | case LABEL_REF: | |
450 | return 1; | |
451 | case CONST: | |
452 | op = XEXP (op, 0); | |
453 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
454 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
455 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
456 | default: | |
457 | return 0; | |
458 | } | |
459 | } | |
460 | ||
461 | /* Return truth value of statement that OP is a symbolic memory | |
462 | operand of mode MODE. */ | |
463 | ||
464 | int | |
5c1d8983 | 465 | symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 466 | { |
467 | if (GET_CODE (op) == SUBREG) | |
468 | op = SUBREG_REG (op); | |
469 | if (GET_CODE (op) != MEM) | |
470 | return 0; | |
471 | op = XEXP (op, 0); | |
472 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
473 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
474 | } | |
475 | ||
6d36483b | 476 | /* Return 1 if the operand is either a register, zero, or a memory operand |
891b55b4 | 477 | that is not symbolic. */ |
478 | ||
479 | int | |
5c1d8983 | 480 | reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode) |
891b55b4 | 481 | { |
482 | if (register_operand (op, mode)) | |
483 | return 1; | |
484 | ||
485 | if (op == CONST0_RTX (mode)) | |
486 | return 1; | |
487 | ||
dbd3d89d | 488 | if (GET_CODE (op) == SUBREG) |
489 | op = SUBREG_REG (op); | |
891b55b4 | 490 | |
dbd3d89d | 491 | if (GET_CODE (op) != MEM) |
492 | return 0; | |
493 | ||
494 | /* Until problems with management of the REG_POINTER flag are resolved, | |
495 | we need to delay creating move insns with unscaled indexed addresses | |
496 | until CSE is not expected. */ | |
497 | if (!TARGET_NO_SPACE_REGS | |
498 | && !cse_not_expected | |
499 | && GET_CODE (XEXP (op, 0)) == PLUS | |
500 | && REG_P (XEXP (XEXP (op, 0), 0)) | |
501 | && REG_P (XEXP (XEXP (op, 0), 1))) | |
502 | return 0; | |
503 | ||
504 | return (!symbolic_memory_operand (op, mode) | |
505 | && memory_address_p (mode, XEXP (op, 0))); | |
891b55b4 | 506 | } |
507 | ||
d3138877 | 508 | /* Return 1 if the operand is a register operand or a non-symbolic memory |
509 | operand after reload. This predicate is used for branch patterns that | |
510 | internally handle register reloading. We need to accept non-symbolic | |
511 | memory operands after reload to ensure that the pattern is still valid | |
512 | if reload didn't find a hard register for the operand. */ | |
513 | ||
514 | int | |
5c1d8983 | 515 | reg_before_reload_operand (rtx op, enum machine_mode mode) |
d3138877 | 516 | { |
6df54749 | 517 | /* Don't accept a SUBREG since it will need a reload. */ |
518 | if (GET_CODE (op) == SUBREG) | |
519 | return 0; | |
520 | ||
d3138877 | 521 | if (register_operand (op, mode)) |
522 | return 1; | |
523 | ||
524 | if (reload_completed | |
525 | && memory_operand (op, mode) | |
dbd3d89d | 526 | && !symbolic_memory_operand (op, mode)) |
d3138877 | 527 | return 1; |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
7c4d3047 | 532 | /* Accept any constant that can be moved in one instruction into a |
d9d7c968 | 533 | general register. */ |
6d36483b | 534 | int |
5c1d8983 | 535 | cint_ok_for_move (HOST_WIDE_INT intval) |
d9d7c968 | 536 | { |
537 | /* OK if ldo, ldil, or zdepi, can be used. */ | |
d8d5c4ff | 538 | return (CONST_OK_FOR_LETTER_P (intval, 'J') |
539 | || CONST_OK_FOR_LETTER_P (intval, 'N') | |
540 | || CONST_OK_FOR_LETTER_P (intval, 'K')); | |
d9d7c968 | 541 | } |
542 | ||
dbd3d89d | 543 | /* Return 1 iff OP is an indexed memory operand. */ |
544 | int | |
545 | indexed_memory_operand (rtx op, enum machine_mode mode) | |
546 | { | |
547 | if (GET_MODE (op) != mode) | |
548 | return 0; | |
549 | ||
550 | /* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */ | |
551 | if (reload_completed && GET_CODE (op) == SUBREG) | |
552 | op = SUBREG_REG (op); | |
553 | ||
554 | if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode)) | |
555 | return 0; | |
556 | ||
557 | op = XEXP (op, 0); | |
558 | ||
559 | return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op)); | |
560 | } | |
561 | ||
562 | /* Accept anything that can be used as a destination operand for a | |
563 | move instruction. We don't accept indexed memory operands since | |
564 | they are supported only for floating point stores. */ | |
565 | int | |
566 | move_dest_operand (rtx op, enum machine_mode mode) | |
567 | { | |
568 | if (register_operand (op, mode)) | |
569 | return 1; | |
570 | ||
571 | if (GET_MODE (op) != mode) | |
572 | return 0; | |
573 | ||
574 | if (GET_CODE (op) == SUBREG) | |
575 | op = SUBREG_REG (op); | |
576 | ||
577 | if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode)) | |
578 | return 0; | |
579 | ||
580 | op = XEXP (op, 0); | |
581 | ||
582 | return (memory_address_p (mode, op) | |
583 | && !IS_INDEX_ADDR_P (op) | |
584 | && !IS_LO_SUM_DLT_ADDR_P (op)); | |
585 | } | |
586 | ||
587 | /* Accept anything that can be used as a source operand for a move | |
588 | instruction. */ | |
87ad11b0 | 589 | int |
dbd3d89d | 590 | move_src_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 591 | { |
592 | if (register_operand (op, mode)) | |
593 | return 1; | |
594 | ||
cc9205b8 | 595 | if (GET_CODE (op) == CONSTANT_P_RTX) |
596 | return 1; | |
597 | ||
42faba01 | 598 | if (GET_CODE (op) == CONST_INT) |
d9d7c968 | 599 | return cint_ok_for_move (INTVAL (op)); |
87ad11b0 | 600 | |
dbd3d89d | 601 | if (GET_MODE (op) != mode) |
602 | return 0; | |
603 | ||
87ad11b0 | 604 | if (GET_CODE (op) == SUBREG) |
605 | op = SUBREG_REG (op); | |
dbd3d89d | 606 | |
87ad11b0 | 607 | if (GET_CODE (op) != MEM) |
608 | return 0; | |
609 | ||
dbd3d89d | 610 | /* Until problems with management of the REG_POINTER flag are resolved, |
611 | we need to delay creating move insns with unscaled indexed addresses | |
612 | until CSE is not expected. */ | |
613 | if (!TARGET_NO_SPACE_REGS | |
614 | && !cse_not_expected | |
615 | && GET_CODE (XEXP (op, 0)) == PLUS | |
616 | && REG_P (XEXP (XEXP (op, 0), 0)) | |
617 | && REG_P (XEXP (XEXP (op, 0), 1))) | |
618 | return 0; | |
27ef382d | 619 | |
dbd3d89d | 620 | return memory_address_p (mode, XEXP (op, 0)); |
87ad11b0 | 621 | } |
622 | ||
6ecdbaa1 | 623 | /* Accept REG and any CONST_INT that can be moved in one instruction into a |
624 | general register. */ | |
625 | int | |
5c1d8983 | 626 | reg_or_cint_move_operand (rtx op, enum machine_mode mode) |
6ecdbaa1 | 627 | { |
628 | if (register_operand (op, mode)) | |
629 | return 1; | |
630 | ||
dbd3d89d | 631 | return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op))); |
6ecdbaa1 | 632 | } |
633 | ||
87ad11b0 | 634 | int |
5c1d8983 | 635 | pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 636 | { |
b4a7bf10 | 637 | if (!flag_pic) |
638 | return 0; | |
639 | ||
640 | switch (GET_CODE (op)) | |
641 | { | |
642 | case LABEL_REF: | |
643 | return 1; | |
b4a7bf10 | 644 | case CONST: |
645 | op = XEXP (op, 0); | |
3c69dc97 | 646 | return (GET_CODE (XEXP (op, 0)) == LABEL_REF |
b4a7bf10 | 647 | && GET_CODE (XEXP (op, 1)) == CONST_INT); |
648 | default: | |
649 | return 0; | |
650 | } | |
87ad11b0 | 651 | } |
652 | ||
87ad11b0 | 653 | int |
5c1d8983 | 654 | fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 655 | { |
656 | return reg_renumber && FP_REG_P (op); | |
657 | } | |
d6f01525 | 658 | |
87ad11b0 | 659 | \f |
87ad11b0 | 660 | |
87ad11b0 | 661 | /* Return truth value of whether OP can be used as an operand in a |
662 | three operand arithmetic insn that accepts registers of mode MODE | |
663 | or 14-bit signed integers. */ | |
664 | int | |
5c1d8983 | 665 | arith_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 666 | { |
667 | return (register_operand (op, mode) | |
668 | || (GET_CODE (op) == CONST_INT && INT_14_BITS (op))); | |
669 | } | |
670 | ||
671 | /* Return truth value of whether OP can be used as an operand in a | |
672 | three operand arithmetic insn that accepts registers of mode MODE | |
673 | or 11-bit signed integers. */ | |
674 | int | |
5c1d8983 | 675 | arith11_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 676 | { |
677 | return (register_operand (op, mode) | |
678 | || (GET_CODE (op) == CONST_INT && INT_11_BITS (op))); | |
679 | } | |
680 | ||
2a91e628 | 681 | /* Return truth value of whether OP can be used as an operand in a |
682 | adddi3 insn. */ | |
683 | int | |
5c1d8983 | 684 | adddi3_operand (rtx op, enum machine_mode mode) |
2a91e628 | 685 | { |
686 | return (register_operand (op, mode) | |
687 | || (GET_CODE (op) == CONST_INT | |
688 | && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op)))); | |
689 | } | |
690 | ||
6d36483b | 691 | /* A constant integer suitable for use in a PRE_MODIFY memory |
757d4970 | 692 | reference. */ |
42faba01 | 693 | int |
5c1d8983 | 694 | pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
42faba01 | 695 | { |
696 | return (GET_CODE (op) == CONST_INT | |
697 | && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10); | |
698 | } | |
699 | ||
6d36483b | 700 | /* A constant integer suitable for use in a POST_MODIFY memory |
757d4970 | 701 | reference. */ |
702 | int | |
5c1d8983 | 703 | post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
757d4970 | 704 | { |
705 | return (GET_CODE (op) == CONST_INT | |
706 | && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10); | |
707 | } | |
708 | ||
87ad11b0 | 709 | int |
5c1d8983 | 710 | arith_double_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 711 | { |
712 | return (register_operand (op, mode) | |
713 | || (GET_CODE (op) == CONST_DOUBLE | |
714 | && GET_MODE (op) == mode | |
715 | && VAL_14_BITS_P (CONST_DOUBLE_LOW (op)) | |
1fe9d310 | 716 | && ((CONST_DOUBLE_HIGH (op) >= 0) |
87ad11b0 | 717 | == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); |
718 | } | |
719 | ||
45981c0a | 720 | /* Return truth value of whether OP is an integer which fits the |
546a40bd | 721 | range constraining immediate operands in three-address insns, or |
722 | is an integer register. */ | |
723 | ||
724 | int | |
5c1d8983 | 725 | ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
546a40bd | 726 | { |
727 | return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op)) | |
728 | || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32)); | |
729 | } | |
730 | ||
c7ae93c8 | 731 | /* Return nonzero if OP is an integer register, else return zero. */ |
732 | int | |
5c1d8983 | 733 | ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
c7ae93c8 | 734 | { |
735 | return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32); | |
736 | } | |
737 | ||
45981c0a | 738 | /* Return truth value of whether OP is an integer which fits the |
87ad11b0 | 739 | range constraining immediate operands in three-address insns. */ |
740 | ||
741 | int | |
5c1d8983 | 742 | int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 743 | { |
744 | return (GET_CODE (op) == CONST_INT && INT_5_BITS (op)); | |
745 | } | |
746 | ||
747 | int | |
5c1d8983 | 748 | uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 749 | { |
750 | return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op)); | |
751 | } | |
752 | ||
87ad11b0 | 753 | int |
5c1d8983 | 754 | int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 755 | { |
6d36483b | 756 | return (GET_CODE (op) == CONST_INT && INT_11_BITS (op)); |
757 | } | |
758 | ||
759 | int | |
5c1d8983 | 760 | uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
6d36483b | 761 | { |
762 | #if HOST_BITS_PER_WIDE_INT > 32 | |
763 | /* All allowed constants will fit a CONST_INT. */ | |
764 | return (GET_CODE (op) == CONST_INT | |
b7d86581 | 765 | && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32)); |
6d36483b | 766 | #else |
767 | return (GET_CODE (op) == CONST_INT | |
768 | || (GET_CODE (op) == CONST_DOUBLE | |
769 | && CONST_DOUBLE_HIGH (op) == 0)); | |
770 | #endif | |
87ad11b0 | 771 | } |
772 | ||
773 | int | |
5c1d8983 | 774 | arith5_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 775 | { |
776 | return register_operand (op, mode) || int5_operand (op, mode); | |
777 | } | |
778 | ||
ea52c577 | 779 | /* True iff zdepi can be used to generate this CONST_INT. |
780 | zdepi first sign extends a 5 bit signed number to a given field | |
781 | length, then places this field anywhere in a zero. */ | |
e057641f | 782 | int |
5c1d8983 | 783 | zdepi_cint_p (unsigned HOST_WIDE_INT x) |
fad0b60f | 784 | { |
3745c59b | 785 | unsigned HOST_WIDE_INT lsb_mask, t; |
fad0b60f | 786 | |
787 | /* This might not be obvious, but it's at least fast. | |
01cc3b75 | 788 | This function is critical; we don't have the time loops would take. */ |
42faba01 | 789 | lsb_mask = x & -x; |
790 | t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1); | |
791 | /* Return true iff t is a power of two. */ | |
fad0b60f | 792 | return ((t & (t - 1)) == 0); |
793 | } | |
794 | ||
6d36483b | 795 | /* True iff depi or extru can be used to compute (reg & mask). |
796 | Accept bit pattern like these: | |
797 | 0....01....1 | |
798 | 1....10....0 | |
799 | 1..10..01..1 */ | |
e057641f | 800 | int |
5c1d8983 | 801 | and_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 802 | { |
803 | mask = ~mask; | |
804 | mask += mask & -mask; | |
805 | return (mask & (mask - 1)) == 0; | |
806 | } | |
807 | ||
808 | /* True iff depi or extru can be used to compute (reg & OP). */ | |
809 | int | |
5c1d8983 | 810 | and_operand (rtx op, enum machine_mode mode) |
e057641f | 811 | { |
812 | return (register_operand (op, mode) | |
42faba01 | 813 | || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op)))); |
e057641f | 814 | } |
815 | ||
816 | /* True iff depi can be used to compute (reg | MASK). */ | |
817 | int | |
5c1d8983 | 818 | ior_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 819 | { |
820 | mask += mask & -mask; | |
821 | return (mask & (mask - 1)) == 0; | |
822 | } | |
823 | ||
824 | /* True iff depi can be used to compute (reg | OP). */ | |
825 | int | |
5c1d8983 | 826 | ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e057641f | 827 | { |
b744c8cb | 828 | return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op))); |
e057641f | 829 | } |
830 | ||
e5965947 | 831 | int |
5c1d8983 | 832 | lhs_lshift_operand (rtx op, enum machine_mode mode) |
e5965947 | 833 | { |
834 | return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode); | |
835 | } | |
836 | ||
837 | /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx. | |
838 | Such values can be the left hand side x in (x << r), using the zvdepi | |
839 | instruction. */ | |
840 | int | |
5c1d8983 | 841 | lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e5965947 | 842 | { |
3745c59b | 843 | unsigned HOST_WIDE_INT x; |
e5965947 | 844 | if (GET_CODE (op) != CONST_INT) |
845 | return 0; | |
846 | x = INTVAL (op) >> 4; | |
847 | return (x & (x + 1)) == 0; | |
848 | } | |
849 | ||
9c6d4825 | 850 | int |
5c1d8983 | 851 | arith32_operand (rtx op, enum machine_mode mode) |
9c6d4825 | 852 | { |
853 | return register_operand (op, mode) || GET_CODE (op) == CONST_INT; | |
854 | } | |
ead9285f | 855 | |
856 | int | |
5c1d8983 | 857 | pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ead9285f | 858 | { |
859 | return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF); | |
860 | } | |
87ad11b0 | 861 | \f |
862 | /* Legitimize PIC addresses. If the address is already | |
863 | position-independent, we return ORIG. Newly generated | |
864 | position-independent addresses go to REG. If we need more | |
865 | than one register, we lose. */ | |
866 | ||
867 | rtx | |
5c1d8983 | 868 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
87ad11b0 | 869 | { |
870 | rtx pic_ref = orig; | |
871 | ||
b090827b | 872 | /* Labels need special handling. */ |
611a88e1 | 873 | if (pic_label_operand (orig, mode)) |
b4a7bf10 | 874 | { |
2536cc16 | 875 | /* We do not want to go through the movXX expanders here since that |
876 | would create recursion. | |
877 | ||
878 | Nor do we really want to call a generator for a named pattern | |
879 | since that requires multiple patterns if we want to support | |
880 | multiple word sizes. | |
881 | ||
882 | So instead we just emit the raw set, which avoids the movXX | |
883 | expanders completely. */ | |
dbd3d89d | 884 | mark_reg_pointer (reg, BITS_PER_UNIT); |
2536cc16 | 885 | emit_insn (gen_rtx_SET (VOIDmode, reg, orig)); |
b4a7bf10 | 886 | current_function_uses_pic_offset_table = 1; |
887 | return reg; | |
888 | } | |
87ad11b0 | 889 | if (GET_CODE (orig) == SYMBOL_REF) |
890 | { | |
f9c1ba9d | 891 | rtx insn, tmp_reg; |
892 | ||
87ad11b0 | 893 | if (reg == 0) |
894 | abort (); | |
895 | ||
f9c1ba9d | 896 | /* Before reload, allocate a temporary register for the intermediate |
897 | result. This allows the sequence to be deleted when the final | |
898 | result is unused and the insns are trivially dead. */ | |
899 | tmp_reg = ((reload_in_progress || reload_completed) | |
900 | ? reg : gen_reg_rtx (Pmode)); | |
901 | ||
902 | emit_move_insn (tmp_reg, | |
fc44315f | 903 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, |
904 | gen_rtx_HIGH (word_mode, orig))); | |
905 | pic_ref | |
906 | = gen_rtx_MEM (Pmode, | |
f9c1ba9d | 907 | gen_rtx_LO_SUM (Pmode, tmp_reg, |
fc44315f | 908 | gen_rtx_UNSPEC (Pmode, |
909 | gen_rtvec (1, orig), | |
910 | 0))); | |
7014838c | 911 | |
87ad11b0 | 912 | current_function_uses_pic_offset_table = 1; |
f9c1ba9d | 913 | MEM_NOTRAP_P (pic_ref) = 1; |
87ad11b0 | 914 | RTX_UNCHANGING_P (pic_ref) = 1; |
dbd3d89d | 915 | mark_reg_pointer (reg, BITS_PER_UNIT); |
f9c1ba9d | 916 | insn = emit_move_insn (reg, pic_ref); |
917 | ||
918 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
919 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn)); | |
920 | ||
87ad11b0 | 921 | return reg; |
922 | } | |
923 | else if (GET_CODE (orig) == CONST) | |
924 | { | |
57ed30e5 | 925 | rtx base; |
87ad11b0 | 926 | |
927 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
928 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
929 | return orig; | |
930 | ||
931 | if (reg == 0) | |
932 | abort (); | |
933 | ||
934 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
935 | { | |
936 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
937 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
938 | base == reg ? 0 : reg); | |
939 | } | |
dbd3d89d | 940 | else |
941 | abort (); | |
942 | ||
87ad11b0 | 943 | if (GET_CODE (orig) == CONST_INT) |
944 | { | |
42faba01 | 945 | if (INT_14_BITS (orig)) |
b244d4c7 | 946 | return plus_constant (base, INTVAL (orig)); |
87ad11b0 | 947 | orig = force_reg (Pmode, orig); |
948 | } | |
ad851752 | 949 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
87ad11b0 | 950 | /* Likewise, should we set special REG_NOTEs here? */ |
951 | } | |
dbd3d89d | 952 | |
87ad11b0 | 953 | return pic_ref; |
954 | } | |
955 | ||
347b5848 | 956 | /* Try machine-dependent ways of modifying an illegitimate address |
957 | to be legitimate. If we find one, return the new, valid address. | |
958 | This macro is used in only one place: `memory_address' in explow.c. | |
959 | ||
960 | OLDX is the address as it was before break_out_memory_refs was called. | |
961 | In some cases it is useful to look at this to decide what needs to be done. | |
962 | ||
963 | MODE and WIN are passed so that this macro can use | |
964 | GO_IF_LEGITIMATE_ADDRESS. | |
965 | ||
966 | It is always safe for this macro to do nothing. It exists to recognize | |
6d36483b | 967 | opportunities to optimize the output. |
347b5848 | 968 | |
969 | For the PA, transform: | |
970 | ||
971 | memory(X + <large int>) | |
972 | ||
973 | into: | |
974 | ||
975 | if (<large int> & mask) >= 16 | |
976 | Y = (<large int> & ~mask) + mask + 1 Round up. | |
977 | else | |
978 | Y = (<large int> & ~mask) Round down. | |
979 | Z = X + Y | |
980 | memory (Z + (<large int> - Y)); | |
981 | ||
6d36483b | 982 | This is for CSE to find several similar references, and only use one Z. |
347b5848 | 983 | |
984 | X can either be a SYMBOL_REF or REG, but because combine can not | |
985 | perform a 4->2 combination we do nothing for SYMBOL_REF + D where | |
986 | D will not fit in 14 bits. | |
987 | ||
988 | MODE_FLOAT references allow displacements which fit in 5 bits, so use | |
6d36483b | 989 | 0x1f as the mask. |
347b5848 | 990 | |
991 | MODE_INT references allow displacements which fit in 14 bits, so use | |
6d36483b | 992 | 0x3fff as the mask. |
347b5848 | 993 | |
994 | This relies on the fact that most mode MODE_FLOAT references will use FP | |
995 | registers and most mode MODE_INT references will use integer registers. | |
996 | (In the rare case of an FP register used in an integer MODE, we depend | |
997 | on secondary reloads to clean things up.) | |
998 | ||
999 | ||
1000 | It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special | |
1001 | manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed | |
01cc3b75 | 1002 | addressing modes to be used). |
347b5848 | 1003 | |
1004 | Put X and Z into registers. Then put the entire expression into | |
1005 | a register. */ | |
1006 | ||
1007 | rtx | |
5c1d8983 | 1008 | hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1009 | enum machine_mode mode) | |
347b5848 | 1010 | { |
347b5848 | 1011 | rtx orig = x; |
1012 | ||
dbd3d89d | 1013 | /* We need to canonicalize the order of operands in unscaled indexed |
1014 | addresses since the code that checks if an address is valid doesn't | |
1015 | always try both orders. */ | |
1016 | if (!TARGET_NO_SPACE_REGS | |
1017 | && GET_CODE (x) == PLUS | |
1018 | && GET_MODE (x) == Pmode | |
1019 | && REG_P (XEXP (x, 0)) | |
1020 | && REG_P (XEXP (x, 1)) | |
1021 | && REG_POINTER (XEXP (x, 0)) | |
1022 | && !REG_POINTER (XEXP (x, 1))) | |
1023 | return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0)); | |
1024 | ||
b4a7bf10 | 1025 | if (flag_pic) |
1026 | return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); | |
1027 | ||
6dc3b0d9 | 1028 | /* Strip off CONST. */ |
347b5848 | 1029 | if (GET_CODE (x) == CONST) |
1030 | x = XEXP (x, 0); | |
1031 | ||
42819d4e | 1032 | /* Special case. Get the SYMBOL_REF into a register and use indexing. |
1033 | That should always be safe. */ | |
1034 | if (GET_CODE (x) == PLUS | |
1035 | && GET_CODE (XEXP (x, 0)) == REG | |
1036 | && GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
1037 | { | |
440c23df | 1038 | rtx reg = force_reg (Pmode, XEXP (x, 1)); |
1039 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0))); | |
42819d4e | 1040 | } |
1041 | ||
166bf021 | 1042 | /* Note we must reject symbols which represent function addresses |
1043 | since the assembler/linker can't handle arithmetic on plabels. */ | |
347b5848 | 1044 | if (GET_CODE (x) == PLUS |
1045 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
166bf021 | 1046 | && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF |
1047 | && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0))) | |
347b5848 | 1048 | || GET_CODE (XEXP (x, 0)) == REG)) |
1049 | { | |
1050 | rtx int_part, ptr_reg; | |
1051 | int newoffset; | |
1052 | int offset = INTVAL (XEXP (x, 1)); | |
1b6f11e2 | 1053 | int mask; |
1054 | ||
1055 | mask = (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1056 | ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff); | |
347b5848 | 1057 | |
6d36483b | 1058 | /* Choose which way to round the offset. Round up if we |
347b5848 | 1059 | are >= halfway to the next boundary. */ |
1060 | if ((offset & mask) >= ((mask + 1) / 2)) | |
1061 | newoffset = (offset & ~ mask) + mask + 1; | |
1062 | else | |
1063 | newoffset = (offset & ~ mask); | |
1064 | ||
1065 | /* If the newoffset will not fit in 14 bits (ldo), then | |
1066 | handling this would take 4 or 5 instructions (2 to load | |
1067 | the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to | |
1068 | add the new offset and the SYMBOL_REF.) Combine can | |
1069 | not handle 4->2 or 5->2 combinations, so do not create | |
1070 | them. */ | |
1071 | if (! VAL_14_BITS_P (newoffset) | |
1072 | && GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
1073 | { | |
7014838c | 1074 | rtx const_part = plus_constant (XEXP (x, 0), newoffset); |
347b5848 | 1075 | rtx tmp_reg |
339613b4 | 1076 | = force_reg (Pmode, |
ad851752 | 1077 | gen_rtx_HIGH (Pmode, const_part)); |
347b5848 | 1078 | ptr_reg |
339613b4 | 1079 | = force_reg (Pmode, |
7014838c | 1080 | gen_rtx_LO_SUM (Pmode, |
1081 | tmp_reg, const_part)); | |
347b5848 | 1082 | } |
1083 | else | |
1084 | { | |
1085 | if (! VAL_14_BITS_P (newoffset)) | |
339613b4 | 1086 | int_part = force_reg (Pmode, GEN_INT (newoffset)); |
347b5848 | 1087 | else |
1088 | int_part = GEN_INT (newoffset); | |
1089 | ||
339613b4 | 1090 | ptr_reg = force_reg (Pmode, |
ad851752 | 1091 | gen_rtx_PLUS (Pmode, |
1092 | force_reg (Pmode, XEXP (x, 0)), | |
1093 | int_part)); | |
347b5848 | 1094 | } |
1095 | return plus_constant (ptr_reg, offset - newoffset); | |
1096 | } | |
45f1285a | 1097 | |
5115683e | 1098 | /* Handle (plus (mult (a) (shadd_constant)) (b)). */ |
45f1285a | 1099 | |
347b5848 | 1100 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT |
1101 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
45f1285a | 1102 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))) |
1103 | && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o' | |
1104 | || GET_CODE (XEXP (x, 1)) == SUBREG) | |
1105 | && GET_CODE (XEXP (x, 1)) != CONST) | |
347b5848 | 1106 | { |
1107 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1108 | rtx reg1, reg2; | |
5115683e | 1109 | |
1110 | reg1 = XEXP (x, 1); | |
1111 | if (GET_CODE (reg1) != REG) | |
1112 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1113 | ||
1114 | reg2 = XEXP (XEXP (x, 0), 0); | |
1115 | if (GET_CODE (reg2) != REG) | |
1116 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1117 | ||
ad851752 | 1118 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1119 | gen_rtx_MULT (Pmode, |
1120 | reg2, | |
1121 | GEN_INT (val)), | |
ad851752 | 1122 | reg1)); |
347b5848 | 1123 | } |
45f1285a | 1124 | |
00a87639 | 1125 | /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)). |
1126 | ||
1127 | Only do so for floating point modes since this is more speculative | |
1128 | and we lose if it's an integer store. */ | |
5115683e | 1129 | if (GET_CODE (x) == PLUS |
00a87639 | 1130 | && GET_CODE (XEXP (x, 0)) == PLUS |
1131 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
1132 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
5115683e | 1133 | && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) |
1134 | && (mode == SFmode || mode == DFmode)) | |
00a87639 | 1135 | { |
5115683e | 1136 | |
1137 | /* First, try and figure out what to use as a base register. */ | |
1138 | rtx reg1, reg2, base, idx, orig_base; | |
1139 | ||
1140 | reg1 = XEXP (XEXP (x, 0), 1); | |
1141 | reg2 = XEXP (x, 1); | |
1142 | base = NULL_RTX; | |
1143 | idx = NULL_RTX; | |
1144 | ||
1145 | /* Make sure they're both regs. If one was a SYMBOL_REF [+ const], | |
e61a0a7f | 1146 | then emit_move_sequence will turn on REG_POINTER so we'll know |
1147 | it's a base register below. */ | |
5115683e | 1148 | if (GET_CODE (reg1) != REG) |
1149 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1150 | ||
1151 | if (GET_CODE (reg2) != REG) | |
1152 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1153 | ||
1154 | /* Figure out what the base and index are. */ | |
9840d99d | 1155 | |
5115683e | 1156 | if (GET_CODE (reg1) == REG |
e61a0a7f | 1157 | && REG_POINTER (reg1)) |
5115683e | 1158 | { |
1159 | base = reg1; | |
1160 | orig_base = XEXP (XEXP (x, 0), 1); | |
ad851752 | 1161 | idx = gen_rtx_PLUS (Pmode, |
1162 | gen_rtx_MULT (Pmode, | |
1163 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
1164 | XEXP (XEXP (XEXP (x, 0), 0), 1)), | |
1165 | XEXP (x, 1)); | |
5115683e | 1166 | } |
1167 | else if (GET_CODE (reg2) == REG | |
e61a0a7f | 1168 | && REG_POINTER (reg2)) |
5115683e | 1169 | { |
1170 | base = reg2; | |
1171 | orig_base = XEXP (x, 1); | |
1172 | idx = XEXP (x, 0); | |
1173 | } | |
1174 | ||
1175 | if (base == 0) | |
21f3ee9c | 1176 | return orig; |
5115683e | 1177 | |
1178 | /* If the index adds a large constant, try to scale the | |
1179 | constant so that it can be loaded with only one insn. */ | |
1180 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1181 | && VAL_14_BITS_P (INTVAL (XEXP (idx, 1)) | |
1182 | / INTVAL (XEXP (XEXP (idx, 0), 1))) | |
1183 | && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0) | |
1184 | { | |
1185 | /* Divide the CONST_INT by the scale factor, then add it to A. */ | |
1186 | int val = INTVAL (XEXP (idx, 1)); | |
1187 | ||
1188 | val /= INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1189 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1190 | if (GET_CODE (reg1) != REG) | |
1191 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1192 | ||
ad851752 | 1193 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val))); |
5115683e | 1194 | |
1195 | /* We can now generate a simple scaled indexed address. */ | |
7014838c | 1196 | return |
1197 | force_reg | |
1198 | (Pmode, gen_rtx_PLUS (Pmode, | |
1199 | gen_rtx_MULT (Pmode, reg1, | |
1200 | XEXP (XEXP (idx, 0), 1)), | |
1201 | base)); | |
5115683e | 1202 | } |
1203 | ||
1204 | /* If B + C is still a valid base register, then add them. */ | |
1205 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1206 | && INTVAL (XEXP (idx, 1)) <= 4096 | |
1207 | && INTVAL (XEXP (idx, 1)) >= -4096) | |
1208 | { | |
1209 | int val = INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1210 | rtx reg1, reg2; | |
1211 | ||
ad851752 | 1212 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1))); |
5115683e | 1213 | |
1214 | reg2 = XEXP (XEXP (idx, 0), 0); | |
1215 | if (GET_CODE (reg2) != CONST_INT) | |
1216 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1217 | ||
ad851752 | 1218 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1219 | gen_rtx_MULT (Pmode, |
1220 | reg2, | |
ad851752 | 1221 | GEN_INT (val)), |
1222 | reg1)); | |
5115683e | 1223 | } |
1224 | ||
1225 | /* Get the index into a register, then add the base + index and | |
1226 | return a register holding the result. */ | |
1227 | ||
1228 | /* First get A into a register. */ | |
1229 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1230 | if (GET_CODE (reg1) != REG) | |
1231 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1232 | ||
1233 | /* And get B into a register. */ | |
1234 | reg2 = XEXP (idx, 1); | |
1235 | if (GET_CODE (reg2) != REG) | |
1236 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1237 | ||
ad851752 | 1238 | reg1 = force_reg (Pmode, |
1239 | gen_rtx_PLUS (Pmode, | |
1240 | gen_rtx_MULT (Pmode, reg1, | |
1241 | XEXP (XEXP (idx, 0), 1)), | |
1242 | reg2)); | |
5115683e | 1243 | |
1244 | /* Add the result to our base register and return. */ | |
ad851752 | 1245 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1)); |
9840d99d | 1246 | |
00a87639 | 1247 | } |
1248 | ||
6d36483b | 1249 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
fb5390c1 | 1250 | special handling to avoid creating an indexed memory address |
1251 | with x-100000 as the base. | |
9840d99d | 1252 | |
fb5390c1 | 1253 | If the constant part is small enough, then it's still safe because |
1254 | there is a guard page at the beginning and end of the data segment. | |
1255 | ||
1256 | Scaled references are common enough that we want to try and rearrange the | |
1257 | terms so that we can use indexing for these addresses too. Only | |
00a87639 | 1258 | do the optimization for floatint point modes. */ |
45f1285a | 1259 | |
fb5390c1 | 1260 | if (GET_CODE (x) == PLUS |
1261 | && symbolic_expression_p (XEXP (x, 1))) | |
45f1285a | 1262 | { |
1263 | /* Ugly. We modify things here so that the address offset specified | |
1264 | by the index expression is computed first, then added to x to form | |
fb5390c1 | 1265 | the entire address. */ |
45f1285a | 1266 | |
00a87639 | 1267 | rtx regx1, regx2, regy1, regy2, y; |
45f1285a | 1268 | |
1269 | /* Strip off any CONST. */ | |
1270 | y = XEXP (x, 1); | |
1271 | if (GET_CODE (y) == CONST) | |
1272 | y = XEXP (y, 0); | |
1273 | ||
7ee96d6e | 1274 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1275 | { | |
00a87639 | 1276 | /* See if this looks like |
1277 | (plus (mult (reg) (shadd_const)) | |
1278 | (const (plus (symbol_ref) (const_int)))) | |
1279 | ||
5115683e | 1280 | Where const_int is small. In that case the const |
9840d99d | 1281 | expression is a valid pointer for indexing. |
5115683e | 1282 | |
1283 | If const_int is big, but can be divided evenly by shadd_const | |
1284 | and added to (reg). This allows more scaled indexed addresses. */ | |
1285 | if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1286 | && GET_CODE (XEXP (x, 0)) == MULT | |
00a87639 | 1287 | && GET_CODE (XEXP (y, 1)) == CONST_INT |
5115683e | 1288 | && INTVAL (XEXP (y, 1)) >= -4096 |
1289 | && INTVAL (XEXP (y, 1)) <= 4095 | |
1290 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1291 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
1292 | { | |
1293 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1294 | rtx reg1, reg2; | |
1295 | ||
1296 | reg1 = XEXP (x, 1); | |
1297 | if (GET_CODE (reg1) != REG) | |
1298 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1299 | ||
1300 | reg2 = XEXP (XEXP (x, 0), 0); | |
1301 | if (GET_CODE (reg2) != REG) | |
1302 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1303 | ||
ad851752 | 1304 | return force_reg (Pmode, |
1305 | gen_rtx_PLUS (Pmode, | |
7014838c | 1306 | gen_rtx_MULT (Pmode, |
1307 | reg2, | |
ad851752 | 1308 | GEN_INT (val)), |
7014838c | 1309 | reg1)); |
5115683e | 1310 | } |
1311 | else if ((mode == DFmode || mode == SFmode) | |
1312 | && GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1313 | && GET_CODE (XEXP (x, 0)) == MULT | |
1314 | && GET_CODE (XEXP (y, 1)) == CONST_INT | |
1315 | && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0 | |
1316 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1317 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
00a87639 | 1318 | { |
1319 | regx1 | |
1320 | = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1)) | |
1321 | / INTVAL (XEXP (XEXP (x, 0), 1)))); | |
1322 | regx2 = XEXP (XEXP (x, 0), 0); | |
1323 | if (GET_CODE (regx2) != REG) | |
1324 | regx2 = force_reg (Pmode, force_operand (regx2, 0)); | |
ad851752 | 1325 | regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1326 | regx2, regx1)); | |
7014838c | 1327 | return |
1328 | force_reg (Pmode, | |
1329 | gen_rtx_PLUS (Pmode, | |
1330 | gen_rtx_MULT (Pmode, regx2, | |
1331 | XEXP (XEXP (x, 0), 1)), | |
1332 | force_reg (Pmode, XEXP (y, 0)))); | |
00a87639 | 1333 | } |
fb5390c1 | 1334 | else if (GET_CODE (XEXP (y, 1)) == CONST_INT |
1335 | && INTVAL (XEXP (y, 1)) >= -4096 | |
1336 | && INTVAL (XEXP (y, 1)) <= 4095) | |
1337 | { | |
1338 | /* This is safe because of the guard page at the | |
1339 | beginning and end of the data space. Just | |
1340 | return the original address. */ | |
1341 | return orig; | |
1342 | } | |
00a87639 | 1343 | else |
1344 | { | |
1345 | /* Doesn't look like one we can optimize. */ | |
1346 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1347 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1348 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1349 | regx1 = force_reg (Pmode, | |
ad851752 | 1350 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1351 | regx1, regy2)); | |
1352 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); | |
00a87639 | 1353 | } |
7ee96d6e | 1354 | } |
45f1285a | 1355 | } |
1356 | ||
347b5848 | 1357 | return orig; |
1358 | } | |
1359 | ||
87ad11b0 | 1360 | /* For the HPPA, REG and REG+CONST is cost 0 |
1361 | and addresses involving symbolic constants are cost 2. | |
1362 | ||
1363 | PIC addresses are very expensive. | |
1364 | ||
1365 | It is no coincidence that this has the same structure | |
1366 | as GO_IF_LEGITIMATE_ADDRESS. */ | |
ec0457a8 | 1367 | |
1368 | static int | |
5c1d8983 | 1369 | hppa_address_cost (rtx X) |
87ad11b0 | 1370 | { |
ec0457a8 | 1371 | switch (GET_CODE (X)) |
1372 | { | |
1373 | case REG: | |
1374 | case PLUS: | |
1375 | case LO_SUM: | |
87ad11b0 | 1376 | return 1; |
ec0457a8 | 1377 | case HIGH: |
1378 | return 2; | |
1379 | default: | |
1380 | return 4; | |
1381 | } | |
87ad11b0 | 1382 | } |
1383 | ||
fab7adbf | 1384 | /* Compute a (partial) cost for rtx X. Return true if the complete |
1385 | cost has been computed, and false if subexpressions should be | |
1386 | scanned. In either case, *TOTAL contains the cost result. */ | |
1387 | ||
1388 | static bool | |
5c1d8983 | 1389 | hppa_rtx_costs (rtx x, int code, int outer_code, int *total) |
fab7adbf | 1390 | { |
1391 | switch (code) | |
1392 | { | |
1393 | case CONST_INT: | |
1394 | if (INTVAL (x) == 0) | |
1395 | *total = 0; | |
1396 | else if (INT_14_BITS (x)) | |
1397 | *total = 1; | |
1398 | else | |
1399 | *total = 2; | |
1400 | return true; | |
1401 | ||
1402 | case HIGH: | |
1403 | *total = 2; | |
1404 | return true; | |
1405 | ||
1406 | case CONST: | |
1407 | case LABEL_REF: | |
1408 | case SYMBOL_REF: | |
1409 | *total = 4; | |
1410 | return true; | |
1411 | ||
1412 | case CONST_DOUBLE: | |
1413 | if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode)) | |
1414 | && outer_code != SET) | |
1415 | *total = 0; | |
1416 | else | |
1417 | *total = 8; | |
1418 | return true; | |
1419 | ||
1420 | case MULT: | |
1421 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1422 | *total = COSTS_N_INSNS (3); | |
1423 | else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT) | |
1424 | *total = COSTS_N_INSNS (8); | |
1425 | else | |
1426 | *total = COSTS_N_INSNS (20); | |
1427 | return true; | |
1428 | ||
1429 | case DIV: | |
1430 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1431 | { | |
1432 | *total = COSTS_N_INSNS (14); | |
1433 | return true; | |
1434 | } | |
8e262b5e | 1435 | /* FALLTHRU */ |
fab7adbf | 1436 | |
1437 | case UDIV: | |
1438 | case MOD: | |
1439 | case UMOD: | |
1440 | *total = COSTS_N_INSNS (60); | |
1441 | return true; | |
1442 | ||
1443 | case PLUS: /* this includes shNadd insns */ | |
1444 | case MINUS: | |
1445 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1446 | *total = COSTS_N_INSNS (3); | |
1447 | else | |
1448 | *total = COSTS_N_INSNS (1); | |
1449 | return true; | |
1450 | ||
1451 | case ASHIFT: | |
1452 | case ASHIFTRT: | |
1453 | case LSHIFTRT: | |
1454 | *total = COSTS_N_INSNS (1); | |
1455 | return true; | |
1456 | ||
1457 | default: | |
1458 | return false; | |
1459 | } | |
1460 | } | |
1461 | ||
9840d99d | 1462 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a |
1463 | new rtx with the correct mode. */ | |
1464 | static inline rtx | |
5c1d8983 | 1465 | force_mode (enum machine_mode mode, rtx orig) |
9840d99d | 1466 | { |
1467 | if (mode == GET_MODE (orig)) | |
1468 | return orig; | |
1469 | ||
1470 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
1471 | abort (); | |
1472 | ||
1473 | return gen_rtx_REG (mode, REGNO (orig)); | |
1474 | } | |
1475 | ||
87ad11b0 | 1476 | /* Emit insns to move operands[1] into operands[0]. |
1477 | ||
1478 | Return 1 if we have written out everything that needs to be done to | |
1479 | do the move. Otherwise, return 0 and the caller will emit the move | |
9840d99d | 1480 | normally. |
f756078b | 1481 | |
1482 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
2cecd772 | 1483 | will be used. This routine is responsible for creating a new copy |
f756078b | 1484 | of SCRATCH_REG in the proper mode. */ |
87ad11b0 | 1485 | |
1486 | int | |
5c1d8983 | 1487 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) |
87ad11b0 | 1488 | { |
1489 | register rtx operand0 = operands[0]; | |
1490 | register rtx operand1 = operands[1]; | |
4a155b0f | 1491 | register rtx tem; |
87ad11b0 | 1492 | |
dbd3d89d | 1493 | /* We can only handle indexed addresses in the destination operand |
1494 | of floating point stores. Thus, we need to break out indexed | |
1495 | addresses from the destination operand. */ | |
1496 | if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0))) | |
1497 | { | |
1498 | /* This is only safe up to the beginning of life analysis. */ | |
1499 | if (no_new_pseudos) | |
1500 | abort (); | |
1501 | ||
1502 | tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0)); | |
1503 | operand0 = replace_equiv_address (operand0, tem); | |
1504 | } | |
1505 | ||
1506 | /* On targets with non-equivalent space registers, break out unscaled | |
1507 | indexed addresses from the source operand before the final CSE. | |
1508 | We have to do this because the REG_POINTER flag is not correctly | |
1509 | carried through various optimization passes and CSE may substitute | |
1510 | a pseudo without the pointer set for one with the pointer set. As | |
1511 | a result, we loose various opportunites to create insns with | |
1512 | unscaled indexed addresses. */ | |
1513 | if (!TARGET_NO_SPACE_REGS | |
1514 | && !cse_not_expected | |
1515 | && GET_CODE (operand1) == MEM | |
1516 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1517 | && REG_P (XEXP (XEXP (operand1, 0), 0)) | |
1518 | && REG_P (XEXP (XEXP (operand1, 0), 1))) | |
1519 | operand1 | |
1520 | = replace_equiv_address (operand1, | |
1521 | copy_to_mode_reg (Pmode, XEXP (operand1, 0))); | |
1522 | ||
2d4dc8d2 | 1523 | if (scratch_reg |
1524 | && reload_in_progress && GET_CODE (operand0) == REG | |
d1e2bb73 | 1525 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) |
1526 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2d4dc8d2 | 1527 | else if (scratch_reg |
1528 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
d1e2bb73 | 1529 | && GET_CODE (SUBREG_REG (operand0)) == REG |
1530 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1531 | { |
701e46d0 | 1532 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1533 | the code which tracks sets/uses for delete_output_reload. */ |
1534 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
1535 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
701e46d0 | 1536 | SUBREG_BYTE (operand0)); |
e00b80b2 | 1537 | operand0 = alter_subreg (&temp); |
a3afad75 | 1538 | } |
d1e2bb73 | 1539 | |
2d4dc8d2 | 1540 | if (scratch_reg |
1541 | && reload_in_progress && GET_CODE (operand1) == REG | |
d1e2bb73 | 1542 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) |
1543 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2d4dc8d2 | 1544 | else if (scratch_reg |
1545 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
d1e2bb73 | 1546 | && GET_CODE (SUBREG_REG (operand1)) == REG |
1547 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1548 | { |
701e46d0 | 1549 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1550 | the code which tracks sets/uses for delete_output_reload. */ |
1551 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
1552 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
701e46d0 | 1553 | SUBREG_BYTE (operand1)); |
e00b80b2 | 1554 | operand1 = alter_subreg (&temp); |
a3afad75 | 1555 | } |
d1e2bb73 | 1556 | |
2d4dc8d2 | 1557 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM |
4a155b0f | 1558 | && ((tem = find_replacement (&XEXP (operand0, 0))) |
1559 | != XEXP (operand0, 0))) | |
ad851752 | 1560 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); |
dbd3d89d | 1561 | |
2d4dc8d2 | 1562 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM |
4a155b0f | 1563 | && ((tem = find_replacement (&XEXP (operand1, 0))) |
1564 | != XEXP (operand1, 0))) | |
ad851752 | 1565 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); |
4a155b0f | 1566 | |
e8fdbafa | 1567 | /* Handle secondary reloads for loads/stores of FP registers from |
9840d99d | 1568 | REG+D addresses where D does not fit in 5 bits, including |
42819d4e | 1569 | (subreg (mem (addr))) cases. */ |
6bcdc1fb | 1570 | if (scratch_reg |
1571 | && fp_reg_operand (operand0, mode) | |
6b1c36c2 | 1572 | && ((GET_CODE (operand1) == MEM |
dbd3d89d | 1573 | && !memory_address_p (DFmode, XEXP (operand1, 0))) |
6b1c36c2 | 1574 | || ((GET_CODE (operand1) == SUBREG |
1575 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
6bcdc1fb | 1576 | && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))) |
d6f01525 | 1577 | { |
6b1c36c2 | 1578 | if (GET_CODE (operand1) == SUBREG) |
1579 | operand1 = XEXP (operand1, 0); | |
1580 | ||
f756078b | 1581 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1582 | it in WORD_MODE regardless of what mode it was originally given | |
1583 | to us. */ | |
9840d99d | 1584 | scratch_reg = force_mode (word_mode, scratch_reg); |
7ee39d73 | 1585 | |
1586 | /* D might not fit in 14 bits either; for such cases load D into | |
1587 | scratch reg. */ | |
440c23df | 1588 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) |
7ee39d73 | 1589 | { |
1590 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
dbd3d89d | 1591 | emit_move_insn (scratch_reg, |
1592 | gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
1593 | Pmode, | |
1594 | XEXP (XEXP (operand1, 0), 0), | |
1595 | scratch_reg)); | |
7ee39d73 | 1596 | } |
1597 | else | |
1598 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
7014838c | 1599 | emit_insn (gen_rtx_SET (VOIDmode, operand0, |
1600 | gen_rtx_MEM (mode, scratch_reg))); | |
d6f01525 | 1601 | return 1; |
1602 | } | |
6bcdc1fb | 1603 | else if (scratch_reg |
1604 | && fp_reg_operand (operand1, mode) | |
6b1c36c2 | 1605 | && ((GET_CODE (operand0) == MEM |
1606 | && ! memory_address_p (DFmode, XEXP (operand0, 0))) | |
1607 | || ((GET_CODE (operand0) == SUBREG) | |
1608 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
dbd3d89d | 1609 | && !memory_address_p (DFmode, |
6bcdc1fb | 1610 | XEXP (XEXP (operand0, 0), 0))))) |
d6f01525 | 1611 | { |
6b1c36c2 | 1612 | if (GET_CODE (operand0) == SUBREG) |
1613 | operand0 = XEXP (operand0, 0); | |
1614 | ||
f756078b | 1615 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1616 | it in WORD_MODE regardless of what mode it was originally given | |
1617 | to us. */ | |
9840d99d | 1618 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1619 | |
7ee39d73 | 1620 | /* D might not fit in 14 bits either; for such cases load D into |
1621 | scratch reg. */ | |
440c23df | 1622 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) |
7ee39d73 | 1623 | { |
1624 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
ad851752 | 1625 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, |
1626 | 0)), | |
440c23df | 1627 | Pmode, |
ad851752 | 1628 | XEXP (XEXP (operand0, 0), |
1629 | 0), | |
1630 | scratch_reg)); | |
7ee39d73 | 1631 | } |
1632 | else | |
1633 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
ad851752 | 1634 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), |
1635 | operand1)); | |
d6f01525 | 1636 | return 1; |
1637 | } | |
753bd06a | 1638 | /* Handle secondary reloads for loads of FP registers from constant |
1639 | expressions by forcing the constant into memory. | |
1640 | ||
6bcdc1fb | 1641 | Use scratch_reg to hold the address of the memory location. |
753bd06a | 1642 | |
9dc4cbf1 | 1643 | The proper fix is to change PREFERRED_RELOAD_CLASS to return |
87fcb603 | 1644 | NO_REGS when presented with a const_int and a register class |
753bd06a | 1645 | containing only FP registers. Doing so unfortunately creates |
1646 | more problems than it solves. Fix this for 2.5. */ | |
6bcdc1fb | 1647 | else if (scratch_reg |
753bd06a | 1648 | && CONSTANT_P (operand1) |
6bcdc1fb | 1649 | && fp_reg_operand (operand0, mode)) |
753bd06a | 1650 | { |
1651 | rtx xoperands[2]; | |
1652 | ||
f756078b | 1653 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1654 | it in WORD_MODE regardless of what mode it was originally given | |
1655 | to us. */ | |
9840d99d | 1656 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1657 | |
753bd06a | 1658 | /* Force the constant into memory and put the address of the |
1659 | memory location into scratch_reg. */ | |
1660 | xoperands[0] = scratch_reg; | |
1661 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
8f258b49 | 1662 | emit_move_sequence (xoperands, Pmode, 0); |
753bd06a | 1663 | |
1664 | /* Now load the destination register. */ | |
7014838c | 1665 | emit_insn (gen_rtx_SET (mode, operand0, |
1666 | gen_rtx_MEM (mode, scratch_reg))); | |
753bd06a | 1667 | return 1; |
1668 | } | |
e8fdbafa | 1669 | /* Handle secondary reloads for SAR. These occur when trying to load |
2a170404 | 1670 | the SAR from memory, FP register, or with a constant. */ |
6bcdc1fb | 1671 | else if (scratch_reg |
1672 | && GET_CODE (operand0) == REG | |
2a170404 | 1673 | && REGNO (operand0) < FIRST_PSEUDO_REGISTER |
e8fdbafa | 1674 | && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS |
1675 | && (GET_CODE (operand1) == MEM | |
7d43e0f7 | 1676 | || GET_CODE (operand1) == CONST_INT |
e8fdbafa | 1677 | || (GET_CODE (operand1) == REG |
6bcdc1fb | 1678 | && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))) |
e8fdbafa | 1679 | { |
7eac600c | 1680 | /* D might not fit in 14 bits either; for such cases load D into |
1681 | scratch reg. */ | |
1682 | if (GET_CODE (operand1) == MEM | |
440c23df | 1683 | && !memory_address_p (Pmode, XEXP (operand1, 0))) |
7eac600c | 1684 | { |
fc4d127d | 1685 | /* We are reloading the address into the scratch register, so we |
1686 | want to make sure the scratch register is a full register. */ | |
9840d99d | 1687 | scratch_reg = force_mode (word_mode, scratch_reg); |
fc4d127d | 1688 | |
9840d99d | 1689 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); |
ad851752 | 1690 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, |
1691 | 0)), | |
440c23df | 1692 | Pmode, |
ad851752 | 1693 | XEXP (XEXP (operand1, 0), |
1694 | 0), | |
1695 | scratch_reg)); | |
fc4d127d | 1696 | |
1697 | /* Now we are going to load the scratch register from memory, | |
1698 | we want to load it in the same width as the original MEM, | |
1699 | which must be the same as the width of the ultimate destination, | |
1700 | OPERAND0. */ | |
9840d99d | 1701 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1702 | ||
fc4d127d | 1703 | emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0), |
ad851752 | 1704 | scratch_reg)); |
7eac600c | 1705 | } |
1706 | else | |
fc4d127d | 1707 | { |
1708 | /* We want to load the scratch register using the same mode as | |
1709 | the ultimate destination. */ | |
9840d99d | 1710 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1711 | ||
fc4d127d | 1712 | emit_move_insn (scratch_reg, operand1); |
1713 | } | |
1714 | ||
1715 | /* And emit the insn to set the ultimate destination. We know that | |
1716 | the scratch register has the same mode as the destination at this | |
1717 | point. */ | |
e8fdbafa | 1718 | emit_move_insn (operand0, scratch_reg); |
1719 | return 1; | |
1720 | } | |
dbd3d89d | 1721 | /* Handle the most common case: storing into a register. */ |
d6f01525 | 1722 | else if (register_operand (operand0, mode)) |
87ad11b0 | 1723 | { |
1724 | if (register_operand (operand1, mode) | |
93f6e1c7 | 1725 | || (GET_CODE (operand1) == CONST_INT |
1726 | && cint_ok_for_move (INTVAL (operand1))) | |
891b55b4 | 1727 | || (operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1728 | || (GET_CODE (operand1) == HIGH |
df0651dc | 1729 | && !symbolic_operand (XEXP (operand1, 0), VOIDmode)) |
87ad11b0 | 1730 | /* Only `general_operands' can come here, so MEM is ok. */ |
1731 | || GET_CODE (operand1) == MEM) | |
1732 | { | |
dbd3d89d | 1733 | /* Various sets are created during RTL generation which don't |
1734 | have the REG_POINTER flag correctly set. After the CSE pass, | |
1735 | instruction recognition can fail if we don't consistently | |
1736 | set this flag when performing register copies. This should | |
1737 | also improve the opportunities for creating insns that use | |
1738 | unscaled indexing. */ | |
1739 | if (REG_P (operand0) && REG_P (operand1)) | |
1740 | { | |
1741 | if (REG_POINTER (operand1) | |
1742 | && !REG_POINTER (operand0) | |
1743 | && !HARD_REGISTER_P (operand0)) | |
1744 | copy_reg_pointer (operand0, operand1); | |
1745 | else if (REG_POINTER (operand0) | |
1746 | && !REG_POINTER (operand1) | |
1747 | && !HARD_REGISTER_P (operand1)) | |
1748 | copy_reg_pointer (operand1, operand0); | |
1749 | } | |
1750 | ||
1751 | /* When MEMs are broken out, the REG_POINTER flag doesn't | |
1752 | get set. In some cases, we can set the REG_POINTER flag | |
1753 | from the declaration for the MEM. */ | |
1754 | if (REG_P (operand0) | |
1755 | && GET_CODE (operand1) == MEM | |
1756 | && !REG_POINTER (operand0)) | |
1757 | { | |
1758 | tree decl = MEM_EXPR (operand1); | |
1759 | ||
1760 | /* Set the register pointer flag and register alignment | |
1761 | if the declaration for this memory reference is a | |
1762 | pointer type. Fortran indirect argument references | |
1763 | are ignored. */ | |
1764 | if (decl | |
1765 | && !(flag_argument_noalias > 1 | |
1766 | && TREE_CODE (decl) == INDIRECT_REF | |
1767 | && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL)) | |
1768 | { | |
1769 | tree type; | |
1770 | ||
1771 | /* If this is a COMPONENT_REF, use the FIELD_DECL from | |
1772 | tree operand 1. */ | |
1773 | if (TREE_CODE (decl) == COMPONENT_REF) | |
1774 | decl = TREE_OPERAND (decl, 1); | |
1775 | ||
1776 | type = TREE_TYPE (decl); | |
1777 | if (TREE_CODE (type) == ARRAY_TYPE) | |
1778 | type = get_inner_array_type (type); | |
1779 | ||
1780 | if (POINTER_TYPE_P (type)) | |
1781 | { | |
1782 | int align; | |
1783 | ||
1784 | type = TREE_TYPE (type); | |
1785 | /* Using TYPE_ALIGN_OK is rather conservative as | |
1786 | only the ada frontend actually sets it. */ | |
1787 | align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type) | |
1788 | : BITS_PER_UNIT); | |
1789 | mark_reg_pointer (operand0, align); | |
1790 | } | |
1791 | } | |
1792 | } | |
1793 | ||
ad851752 | 1794 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1795 | return 1; |
1796 | } | |
1797 | } | |
1798 | else if (GET_CODE (operand0) == MEM) | |
1799 | { | |
85eb4c6e | 1800 | if (mode == DFmode && operand1 == CONST0_RTX (mode) |
1801 | && !(reload_in_progress || reload_completed)) | |
1802 | { | |
1803 | rtx temp = gen_reg_rtx (DFmode); | |
1804 | ||
ad851752 | 1805 | emit_insn (gen_rtx_SET (VOIDmode, temp, operand1)); |
1806 | emit_insn (gen_rtx_SET (VOIDmode, operand0, temp)); | |
85eb4c6e | 1807 | return 1; |
1808 | } | |
891b55b4 | 1809 | if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1810 | { |
1811 | /* Run this case quickly. */ | |
ad851752 | 1812 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1813 | return 1; |
1814 | } | |
2ff4bf8d | 1815 | if (! (reload_in_progress || reload_completed)) |
87ad11b0 | 1816 | { |
1817 | operands[0] = validize_mem (operand0); | |
1818 | operands[1] = operand1 = force_reg (mode, operand1); | |
1819 | } | |
1820 | } | |
1821 | ||
37a75d53 | 1822 | /* Simplify the source if we need to. |
1823 | Note we do have to handle function labels here, even though we do | |
1824 | not consider them legitimate constants. Loop optimizations can | |
bea60f66 | 1825 | call the emit_move_xxx with one as a source. */ |
57ed30e5 | 1826 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) |
37a75d53 | 1827 | || function_label_operand (operand1, mode) |
2ee034bc | 1828 | || (GET_CODE (operand1) == HIGH |
63882853 | 1829 | && symbolic_operand (XEXP (operand1, 0), mode))) |
87ad11b0 | 1830 | { |
2ee034bc | 1831 | int ishighonly = 0; |
1832 | ||
1833 | if (GET_CODE (operand1) == HIGH) | |
1834 | { | |
1835 | ishighonly = 1; | |
1836 | operand1 = XEXP (operand1, 0); | |
1837 | } | |
87ad11b0 | 1838 | if (symbolic_operand (operand1, mode)) |
1839 | { | |
005a7dd0 | 1840 | /* Argh. The assembler and linker can't handle arithmetic |
81653f9b | 1841 | involving plabels. |
005a7dd0 | 1842 | |
81653f9b | 1843 | So we force the plabel into memory, load operand0 from |
1844 | the memory location, then add in the constant part. */ | |
37a75d53 | 1845 | if ((GET_CODE (operand1) == CONST |
1846 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1847 | && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode)) | |
1848 | || function_label_operand (operand1, mode)) | |
005a7dd0 | 1849 | { |
b3d569a0 | 1850 | rtx temp, const_part; |
81653f9b | 1851 | |
1852 | /* Figure out what (if any) scratch register to use. */ | |
1853 | if (reload_in_progress || reload_completed) | |
f756078b | 1854 | { |
1855 | scratch_reg = scratch_reg ? scratch_reg : operand0; | |
1856 | /* SCRATCH_REG will hold an address and maybe the actual | |
1857 | data. We want it in WORD_MODE regardless of what mode it | |
1858 | was originally given to us. */ | |
9840d99d | 1859 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1860 | } |
81653f9b | 1861 | else if (flag_pic) |
1862 | scratch_reg = gen_reg_rtx (Pmode); | |
1863 | ||
37a75d53 | 1864 | if (GET_CODE (operand1) == CONST) |
1865 | { | |
1866 | /* Save away the constant part of the expression. */ | |
1867 | const_part = XEXP (XEXP (operand1, 0), 1); | |
1868 | if (GET_CODE (const_part) != CONST_INT) | |
1869 | abort (); | |
1870 | ||
1871 | /* Force the function label into memory. */ | |
1872 | temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0)); | |
1873 | } | |
1874 | else | |
1875 | { | |
1876 | /* No constant part. */ | |
1877 | const_part = NULL_RTX; | |
005a7dd0 | 1878 | |
37a75d53 | 1879 | /* Force the function label into memory. */ |
1880 | temp = force_const_mem (mode, operand1); | |
1881 | } | |
9840d99d | 1882 | |
81653f9b | 1883 | |
1884 | /* Get the address of the memory location. PIC-ify it if | |
1885 | necessary. */ | |
1886 | temp = XEXP (temp, 0); | |
1887 | if (flag_pic) | |
1888 | temp = legitimize_pic_address (temp, mode, scratch_reg); | |
1889 | ||
1890 | /* Put the address of the memory location into our destination | |
1891 | register. */ | |
1892 | operands[1] = temp; | |
1893 | emit_move_sequence (operands, mode, scratch_reg); | |
1894 | ||
1895 | /* Now load from the memory location into our destination | |
1896 | register. */ | |
ad851752 | 1897 | operands[1] = gen_rtx_MEM (Pmode, operands[0]); |
81653f9b | 1898 | emit_move_sequence (operands, mode, scratch_reg); |
1899 | ||
1900 | /* And add back in the constant part. */ | |
37a75d53 | 1901 | if (const_part != NULL_RTX) |
1902 | expand_inc (operand0, const_part); | |
81653f9b | 1903 | |
1904 | return 1; | |
005a7dd0 | 1905 | } |
1906 | ||
87ad11b0 | 1907 | if (flag_pic) |
1908 | { | |
2ff4bf8d | 1909 | rtx temp; |
1910 | ||
1911 | if (reload_in_progress || reload_completed) | |
f756078b | 1912 | { |
1913 | temp = scratch_reg ? scratch_reg : operand0; | |
1914 | /* TEMP will hold an address and maybe the actual | |
1915 | data. We want it in WORD_MODE regardless of what mode it | |
1916 | was originally given to us. */ | |
9840d99d | 1917 | temp = force_mode (word_mode, temp); |
f756078b | 1918 | } |
2ff4bf8d | 1919 | else |
1920 | temp = gen_reg_rtx (Pmode); | |
6d36483b | 1921 | |
81653f9b | 1922 | /* (const (plus (symbol) (const_int))) must be forced to |
1923 | memory during/after reload if the const_int will not fit | |
1924 | in 14 bits. */ | |
1925 | if (GET_CODE (operand1) == CONST | |
96b86ab6 | 1926 | && GET_CODE (XEXP (operand1, 0)) == PLUS |
1927 | && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT | |
1928 | && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)) | |
1929 | && (reload_completed || reload_in_progress) | |
1930 | && flag_pic) | |
1931 | { | |
1932 | operands[1] = force_const_mem (mode, operand1); | |
1933 | operands[1] = legitimize_pic_address (XEXP (operands[1], 0), | |
1934 | mode, temp); | |
1935 | emit_move_sequence (operands, mode, temp); | |
1936 | } | |
005a7dd0 | 1937 | else |
1938 | { | |
1939 | operands[1] = legitimize_pic_address (operand1, mode, temp); | |
dbd3d89d | 1940 | if (REG_P (operand0) && REG_P (operands[1])) |
1941 | copy_reg_pointer (operand0, operands[1]); | |
ad851752 | 1942 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1])); |
005a7dd0 | 1943 | } |
87ad11b0 | 1944 | } |
b4a7bf10 | 1945 | /* On the HPPA, references to data space are supposed to use dp, |
1946 | register 27, but showing it in the RTL inhibits various cse | |
1947 | and loop optimizations. */ | |
6d36483b | 1948 | else |
87ad11b0 | 1949 | { |
005a7dd0 | 1950 | rtx temp, set; |
2ee034bc | 1951 | |
6d36483b | 1952 | if (reload_in_progress || reload_completed) |
f756078b | 1953 | { |
1954 | temp = scratch_reg ? scratch_reg : operand0; | |
1955 | /* TEMP will hold an address and maybe the actual | |
1956 | data. We want it in WORD_MODE regardless of what mode it | |
1957 | was originally given to us. */ | |
9840d99d | 1958 | temp = force_mode (word_mode, temp); |
f756078b | 1959 | } |
2ee034bc | 1960 | else |
1961 | temp = gen_reg_rtx (mode); | |
1962 | ||
42819d4e | 1963 | /* Loading a SYMBOL_REF into a register makes that register |
9840d99d | 1964 | safe to be used as the base in an indexed address. |
42819d4e | 1965 | |
1966 | Don't mark hard registers though. That loses. */ | |
47a61b79 | 1967 | if (GET_CODE (operand0) == REG |
1968 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
dbd3d89d | 1969 | mark_reg_pointer (operand0, BITS_PER_UNIT); |
42819d4e | 1970 | if (REGNO (temp) >= FIRST_PSEUDO_REGISTER) |
dbd3d89d | 1971 | mark_reg_pointer (temp, BITS_PER_UNIT); |
1972 | ||
2ee034bc | 1973 | if (ishighonly) |
ad851752 | 1974 | set = gen_rtx_SET (mode, operand0, temp); |
2ee034bc | 1975 | else |
7014838c | 1976 | set = gen_rtx_SET (VOIDmode, |
1977 | operand0, | |
ad851752 | 1978 | gen_rtx_LO_SUM (mode, temp, operand1)); |
6d36483b | 1979 | |
ad851752 | 1980 | emit_insn (gen_rtx_SET (VOIDmode, |
1981 | temp, | |
1982 | gen_rtx_HIGH (mode, operand1))); | |
d2498717 | 1983 | emit_insn (set); |
166bf021 | 1984 | |
87ad11b0 | 1985 | } |
2ee034bc | 1986 | return 1; |
87ad11b0 | 1987 | } |
42faba01 | 1988 | else if (GET_CODE (operand1) != CONST_INT |
6bcdc1fb | 1989 | || !cint_ok_for_move (INTVAL (operand1))) |
87ad11b0 | 1990 | { |
6bcdc1fb | 1991 | rtx insn, temp; |
1992 | rtx op1 = operand1; | |
6edde44b | 1993 | HOST_WIDE_INT value = 0; |
6bcdc1fb | 1994 | HOST_WIDE_INT insv = 0; |
1995 | int insert = 0; | |
1996 | ||
6edde44b | 1997 | if (GET_CODE (operand1) == CONST_INT) |
1998 | value = INTVAL (operand1); | |
1999 | ||
6bcdc1fb | 2000 | if (TARGET_64BIT |
2001 | && GET_CODE (operand1) == CONST_INT | |
b7d86581 | 2002 | && HOST_BITS_PER_WIDE_INT > 32 |
5e3c5739 | 2003 | && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32) |
2004 | { | |
b7d86581 | 2005 | HOST_WIDE_INT nval; |
5e3c5739 | 2006 | |
93f6e1c7 | 2007 | /* Extract the low order 32 bits of the value and sign extend. |
2008 | If the new value is the same as the original value, we can | |
2009 | can use the original value as-is. If the new value is | |
2010 | different, we use it and insert the most-significant 32-bits | |
2011 | of the original value into the final result. */ | |
6bcdc1fb | 2012 | nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1)) |
b7d86581 | 2013 | ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31); |
6bcdc1fb | 2014 | if (value != nval) |
5e3c5739 | 2015 | { |
93f6e1c7 | 2016 | #if HOST_BITS_PER_WIDE_INT > 32 |
6bcdc1fb | 2017 | insv = value >= 0 ? value >> 32 : ~(~value >> 32); |
93f6e1c7 | 2018 | #endif |
6bcdc1fb | 2019 | insert = 1; |
2020 | value = nval; | |
5e3c5739 | 2021 | operand1 = GEN_INT (nval); |
2022 | } | |
2023 | } | |
2ff4bf8d | 2024 | |
2025 | if (reload_in_progress || reload_completed) | |
6bcdc1fb | 2026 | temp = scratch_reg ? scratch_reg : operand0; |
2ff4bf8d | 2027 | else |
2028 | temp = gen_reg_rtx (mode); | |
2029 | ||
7c4d3047 | 2030 | /* We don't directly split DImode constants on 32-bit targets |
2031 | because PLUS uses an 11-bit immediate and the insn sequence | |
2032 | generated is not as efficient as the one using HIGH/LO_SUM. */ | |
2033 | if (GET_CODE (operand1) == CONST_INT | |
6bcdc1fb | 2034 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
2035 | && !insert) | |
93f6e1c7 | 2036 | { |
7c4d3047 | 2037 | /* Directly break constant into high and low parts. This |
93f6e1c7 | 2038 | provides better optimization opportunities because various |
2039 | passes recognize constants split with PLUS but not LO_SUM. | |
2040 | We use a 14-bit signed low part except when the addition | |
2041 | of 0x4000 to the high part might change the sign of the | |
2042 | high part. */ | |
93f6e1c7 | 2043 | HOST_WIDE_INT low = value & 0x3fff; |
2044 | HOST_WIDE_INT high = value & ~ 0x3fff; | |
2045 | ||
2046 | if (low >= 0x2000) | |
2047 | { | |
2048 | if (high == 0x7fffc000 || (mode == HImode && high == 0x4000)) | |
2049 | high += 0x2000; | |
2050 | else | |
2051 | high += 0x4000; | |
2052 | } | |
2053 | ||
2054 | low = value - high; | |
5e3c5739 | 2055 | |
93f6e1c7 | 2056 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high))); |
2057 | operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low)); | |
2058 | } | |
2059 | else | |
5e3c5739 | 2060 | { |
93f6e1c7 | 2061 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
2062 | gen_rtx_HIGH (mode, operand1))); | |
2063 | operands[1] = gen_rtx_LO_SUM (mode, temp, operand1); | |
5e3c5739 | 2064 | } |
9840d99d | 2065 | |
6bcdc1fb | 2066 | insn = emit_move_insn (operands[0], operands[1]); |
2067 | ||
2068 | /* Now insert the most significant 32 bits of the value | |
2069 | into the register. When we don't have a second register | |
2070 | available, it could take up to nine instructions to load | |
2071 | a 64-bit integer constant. Prior to reload, we force | |
2072 | constants that would take more than three instructions | |
2073 | to load to the constant pool. During and after reload, | |
2074 | we have to handle all possible values. */ | |
2075 | if (insert) | |
2076 | { | |
2077 | /* Use a HIGH/LO_SUM/INSV sequence if we have a second | |
2078 | register and the value to be inserted is outside the | |
2079 | range that can be loaded with three depdi instructions. */ | |
2080 | if (temp != operand0 && (insv >= 16384 || insv < -16384)) | |
2081 | { | |
2082 | operand1 = GEN_INT (insv); | |
2083 | ||
2084 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
2085 | gen_rtx_HIGH (mode, operand1))); | |
2086 | emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1)); | |
2087 | emit_insn (gen_insv (operand0, GEN_INT (32), | |
2088 | const0_rtx, temp)); | |
2089 | } | |
2090 | else | |
2091 | { | |
2092 | int len = 5, pos = 27; | |
2093 | ||
2094 | /* Insert the bits using the depdi instruction. */ | |
2095 | while (pos >= 0) | |
2096 | { | |
2097 | HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16; | |
2098 | HOST_WIDE_INT sign = v5 < 0; | |
2099 | ||
2100 | /* Left extend the insertion. */ | |
2101 | insv = (insv >= 0 ? insv >> len : ~(~insv >> len)); | |
2102 | while (pos > 0 && (insv & 1) == sign) | |
2103 | { | |
2104 | insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1)); | |
2105 | len += 1; | |
2106 | pos -= 1; | |
2107 | } | |
2108 | ||
2109 | emit_insn (gen_insv (operand0, GEN_INT (len), | |
2110 | GEN_INT (pos), GEN_INT (v5))); | |
2111 | ||
2112 | len = pos > 0 && pos < 5 ? pos : 5; | |
2113 | pos -= len; | |
2114 | } | |
2115 | } | |
2116 | } | |
93f6e1c7 | 2117 | |
6bcdc1fb | 2118 | REG_NOTES (insn) |
2119 | = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn)); | |
93f6e1c7 | 2120 | |
5e3c5739 | 2121 | return 1; |
87ad11b0 | 2122 | } |
2123 | } | |
2124 | /* Now have insn-emit do whatever it normally does. */ | |
2125 | return 0; | |
2126 | } | |
2127 | ||
1946138e | 2128 | /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning |
bd49d362 | 2129 | it will need a link/runtime reloc). */ |
1946138e | 2130 | |
2131 | int | |
5c1d8983 | 2132 | reloc_needed (tree exp) |
1946138e | 2133 | { |
2134 | int reloc = 0; | |
2135 | ||
2136 | switch (TREE_CODE (exp)) | |
2137 | { | |
2138 | case ADDR_EXPR: | |
2139 | return 1; | |
2140 | ||
2141 | case PLUS_EXPR: | |
2142 | case MINUS_EXPR: | |
2143 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
2144 | reloc |= reloc_needed (TREE_OPERAND (exp, 1)); | |
2145 | break; | |
2146 | ||
2147 | case NOP_EXPR: | |
2148 | case CONVERT_EXPR: | |
2149 | case NON_LVALUE_EXPR: | |
2150 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
2151 | break; | |
2152 | ||
2153 | case CONSTRUCTOR: | |
2154 | { | |
2155 | register tree link; | |
2156 | for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link)) | |
2157 | if (TREE_VALUE (link) != 0) | |
2158 | reloc |= reloc_needed (TREE_VALUE (link)); | |
2159 | } | |
2160 | break; | |
2161 | ||
2162 | case ERROR_MARK: | |
2163 | break; | |
7d27e4c9 | 2164 | |
2165 | default: | |
2166 | break; | |
1946138e | 2167 | } |
2168 | return reloc; | |
2169 | } | |
2170 | ||
7811991d | 2171 | /* Does operand (which is a symbolic_operand) live in text space? |
2172 | If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info, | |
2173 | will be true. */ | |
87ad11b0 | 2174 | |
2175 | int | |
5c1d8983 | 2176 | read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 2177 | { |
2178 | if (GET_CODE (operand) == CONST) | |
2179 | operand = XEXP (XEXP (operand, 0), 0); | |
b4a7bf10 | 2180 | if (flag_pic) |
2181 | { | |
2182 | if (GET_CODE (operand) == SYMBOL_REF) | |
2183 | return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand); | |
2184 | } | |
2185 | else | |
2186 | { | |
2187 | if (GET_CODE (operand) == SYMBOL_REF) | |
2188 | return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand); | |
2189 | } | |
87ad11b0 | 2190 | return 1; |
2191 | } | |
6d36483b | 2192 | |
87ad11b0 | 2193 | \f |
2194 | /* Return the best assembler insn template | |
f54b1341 | 2195 | for moving operands[1] into operands[0] as a fullword. */ |
611a88e1 | 2196 | const char * |
5c1d8983 | 2197 | singlemove_string (rtx *operands) |
87ad11b0 | 2198 | { |
3745c59b | 2199 | HOST_WIDE_INT intval; |
2200 | ||
87ad11b0 | 2201 | if (GET_CODE (operands[0]) == MEM) |
2202 | return "stw %r1,%0"; | |
3745c59b | 2203 | if (GET_CODE (operands[1]) == MEM) |
87ad11b0 | 2204 | return "ldw %1,%0"; |
3745c59b | 2205 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
9d5108ea | 2206 | { |
3745c59b | 2207 | long i; |
2208 | REAL_VALUE_TYPE d; | |
9d5108ea | 2209 | |
3745c59b | 2210 | if (GET_MODE (operands[1]) != SFmode) |
2211 | abort (); | |
9d5108ea | 2212 | |
3745c59b | 2213 | /* Translate the CONST_DOUBLE to a CONST_INT with the same target |
2214 | bit pattern. */ | |
2215 | REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]); | |
2216 | REAL_VALUE_TO_TARGET_SINGLE (d, i); | |
9d5108ea | 2217 | |
3745c59b | 2218 | operands[1] = GEN_INT (i); |
2219 | /* Fall through to CONST_INT case. */ | |
2220 | } | |
2221 | if (GET_CODE (operands[1]) == CONST_INT) | |
9d5108ea | 2222 | { |
3745c59b | 2223 | intval = INTVAL (operands[1]); |
2224 | ||
2225 | if (VAL_14_BITS_P (intval)) | |
2226 | return "ldi %1,%0"; | |
2227 | else if ((intval & 0x7ff) == 0) | |
2228 | return "ldil L'%1,%0"; | |
2229 | else if (zdepi_cint_p (intval)) | |
e4065f95 | 2230 | return "{zdepi %Z1,%0|depwi,z %Z1,%0}"; |
9d5108ea | 2231 | else |
2232 | return "ldil L'%1,%0\n\tldo R'%1(%0),%0"; | |
2233 | } | |
87ad11b0 | 2234 | return "copy %1,%0"; |
2235 | } | |
2236 | \f | |
2237 | ||
201f01e9 | 2238 | /* Compute position (in OP[1]) and width (in OP[2]) |
2239 | useful for copying IMM to a register using the zdepi | |
2240 | instructions. Store the immediate value to insert in OP[0]. */ | |
611a88e1 | 2241 | static void |
5c1d8983 | 2242 | compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
7e10ba53 | 2243 | { |
e057641f | 2244 | int lsb, len; |
7e10ba53 | 2245 | |
e057641f | 2246 | /* Find the least significant set bit in IMM. */ |
2247 | for (lsb = 0; lsb < 32; lsb++) | |
7e10ba53 | 2248 | { |
e057641f | 2249 | if ((imm & 1) != 0) |
7e10ba53 | 2250 | break; |
e057641f | 2251 | imm >>= 1; |
7e10ba53 | 2252 | } |
2253 | ||
e057641f | 2254 | /* Choose variants based on *sign* of the 5-bit field. */ |
2255 | if ((imm & 0x10) == 0) | |
2256 | len = (lsb <= 28) ? 4 : 32 - lsb; | |
7e10ba53 | 2257 | else |
2258 | { | |
e057641f | 2259 | /* Find the width of the bitstring in IMM. */ |
2260 | for (len = 5; len < 32; len++) | |
7e10ba53 | 2261 | { |
e057641f | 2262 | if ((imm & (1 << len)) == 0) |
7e10ba53 | 2263 | break; |
7e10ba53 | 2264 | } |
2265 | ||
e057641f | 2266 | /* Sign extend IMM as a 5-bit value. */ |
2267 | imm = (imm & 0xf) - 0x10; | |
7e10ba53 | 2268 | } |
2269 | ||
42faba01 | 2270 | op[0] = imm; |
2271 | op[1] = 31 - lsb; | |
2272 | op[2] = len; | |
7e10ba53 | 2273 | } |
2274 | ||
5e3c5739 | 2275 | /* Compute position (in OP[1]) and width (in OP[2]) |
2276 | useful for copying IMM to a register using the depdi,z | |
2277 | instructions. Store the immediate value to insert in OP[0]. */ | |
2278 | void | |
5c1d8983 | 2279 | compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
5e3c5739 | 2280 | { |
2281 | HOST_WIDE_INT lsb, len; | |
2282 | ||
2283 | /* Find the least significant set bit in IMM. */ | |
2284 | for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++) | |
2285 | { | |
2286 | if ((imm & 1) != 0) | |
2287 | break; | |
2288 | imm >>= 1; | |
2289 | } | |
2290 | ||
2291 | /* Choose variants based on *sign* of the 5-bit field. */ | |
2292 | if ((imm & 0x10) == 0) | |
2293 | len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4) | |
2294 | ? 4 : HOST_BITS_PER_WIDE_INT - lsb); | |
2295 | else | |
2296 | { | |
2297 | /* Find the width of the bitstring in IMM. */ | |
2298 | for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++) | |
2299 | { | |
ea52c577 | 2300 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
5e3c5739 | 2301 | break; |
2302 | } | |
2303 | ||
2304 | /* Sign extend IMM as a 5-bit value. */ | |
2305 | imm = (imm & 0xf) - 0x10; | |
2306 | } | |
2307 | ||
2308 | op[0] = imm; | |
2309 | op[1] = 63 - lsb; | |
2310 | op[2] = len; | |
2311 | } | |
2312 | ||
87ad11b0 | 2313 | /* Output assembler code to perform a doubleword move insn |
2314 | with operands OPERANDS. */ | |
2315 | ||
611a88e1 | 2316 | const char * |
5c1d8983 | 2317 | output_move_double (rtx *operands) |
87ad11b0 | 2318 | { |
2319 | enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1; | |
2320 | rtx latehalf[2]; | |
2321 | rtx addreg0 = 0, addreg1 = 0; | |
2322 | ||
2323 | /* First classify both operands. */ | |
2324 | ||
2325 | if (REG_P (operands[0])) | |
2326 | optype0 = REGOP; | |
2327 | else if (offsettable_memref_p (operands[0])) | |
2328 | optype0 = OFFSOP; | |
2329 | else if (GET_CODE (operands[0]) == MEM) | |
2330 | optype0 = MEMOP; | |
2331 | else | |
2332 | optype0 = RNDOP; | |
2333 | ||
2334 | if (REG_P (operands[1])) | |
2335 | optype1 = REGOP; | |
2336 | else if (CONSTANT_P (operands[1])) | |
2337 | optype1 = CNSTOP; | |
2338 | else if (offsettable_memref_p (operands[1])) | |
2339 | optype1 = OFFSOP; | |
2340 | else if (GET_CODE (operands[1]) == MEM) | |
2341 | optype1 = MEMOP; | |
2342 | else | |
2343 | optype1 = RNDOP; | |
2344 | ||
2345 | /* Check for the cases that the operand constraints are not | |
2346 | supposed to allow to happen. Abort if we get one, | |
2347 | because generating code for these cases is painful. */ | |
2348 | ||
2349 | if (optype0 != REGOP && optype1 != REGOP) | |
2350 | abort (); | |
2351 | ||
2352 | /* Handle auto decrementing and incrementing loads and stores | |
2353 | specifically, since the structure of the function doesn't work | |
2354 | for them without major modification. Do it better when we learn | |
2355 | this port about the general inc/dec addressing of PA. | |
2356 | (This was written by tege. Chide him if it doesn't work.) */ | |
2357 | ||
2358 | if (optype0 == MEMOP) | |
2359 | { | |
1df0058a | 2360 | /* We have to output the address syntax ourselves, since print_operand |
2361 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2362 | ||
87ad11b0 | 2363 | rtx addr = XEXP (operands[0], 0); |
1df0058a | 2364 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) |
87ad11b0 | 2365 | { |
ad851752 | 2366 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2367 | |
2368 | operands[0] = XEXP (addr, 0); | |
2369 | if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG) | |
2370 | abort (); | |
2371 | ||
2372 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2373 | { | |
2374 | /* No overlap between high target register and address | |
2375 | register. (We do this in a non-obvious way to | |
2376 | save a register file writeback) */ | |
2377 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2378 | return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)"; |
2379 | return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)"; | |
1df0058a | 2380 | } |
2381 | else | |
ea52c577 | 2382 | abort (); |
a3217f65 | 2383 | } |
1df0058a | 2384 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) |
a3217f65 | 2385 | { |
ad851752 | 2386 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2387 | |
2388 | operands[0] = XEXP (addr, 0); | |
2389 | if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG) | |
2390 | abort (); | |
2391 | ||
2392 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2393 | { | |
2394 | /* No overlap between high target register and address | |
2395 | register. (We do this in a non-obvious way to | |
2396 | save a register file writeback) */ | |
2397 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2398 | return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)"; |
2399 | return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)"; | |
1df0058a | 2400 | } |
2401 | else | |
ea52c577 | 2402 | abort (); |
87ad11b0 | 2403 | } |
2404 | } | |
2405 | if (optype1 == MEMOP) | |
2406 | { | |
2407 | /* We have to output the address syntax ourselves, since print_operand | |
2408 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2409 | ||
2410 | rtx addr = XEXP (operands[1], 0); | |
2411 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) | |
2412 | { | |
ad851752 | 2413 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2414 | |
2415 | operands[1] = XEXP (addr, 0); | |
2416 | if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG) | |
2417 | abort (); | |
2418 | ||
2419 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2420 | { | |
2421 | /* No overlap between high target register and address | |
3857fa62 | 2422 | register. (We do this in a non-obvious way to |
87ad11b0 | 2423 | save a register file writeback) */ |
2424 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2425 | return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0"; |
01fd4b49 | 2426 | return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0"; |
87ad11b0 | 2427 | } |
2428 | else | |
2429 | { | |
2430 | /* This is an undefined situation. We should load into the | |
2431 | address register *and* update that register. Probably | |
2432 | we don't need to handle this at all. */ | |
2433 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2434 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0"; |
2435 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0"; | |
87ad11b0 | 2436 | } |
2437 | } | |
2438 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) | |
2439 | { | |
ad851752 | 2440 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2441 | |
2442 | operands[1] = XEXP (addr, 0); | |
2443 | if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG) | |
2444 | abort (); | |
2445 | ||
2446 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2447 | { | |
2448 | /* No overlap between high target register and address | |
3857fa62 | 2449 | register. (We do this in a non-obvious way to |
87ad11b0 | 2450 | save a register file writeback) */ |
2451 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2452 | return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0"; |
2453 | return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0"; | |
87ad11b0 | 2454 | } |
2455 | else | |
2456 | { | |
2457 | /* This is an undefined situation. We should load into the | |
2458 | address register *and* update that register. Probably | |
2459 | we don't need to handle this at all. */ | |
2460 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2461 | return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0"; |
2462 | return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0"; | |
87ad11b0 | 2463 | } |
2464 | } | |
12b02046 | 2465 | else if (GET_CODE (addr) == PLUS |
2466 | && GET_CODE (XEXP (addr, 0)) == MULT) | |
2467 | { | |
ad851752 | 2468 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
12b02046 | 2469 | |
2470 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2471 | { | |
2472 | rtx xoperands[3]; | |
2473 | ||
2474 | xoperands[0] = high_reg; | |
2475 | xoperands[1] = XEXP (addr, 1); | |
2476 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2477 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2478 | output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}", |
2479 | xoperands); | |
34940871 | 2480 | return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; |
12b02046 | 2481 | } |
2482 | else | |
2483 | { | |
2484 | rtx xoperands[3]; | |
2485 | ||
2486 | xoperands[0] = high_reg; | |
2487 | xoperands[1] = XEXP (addr, 1); | |
2488 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2489 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2490 | output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}", |
2491 | xoperands); | |
34940871 | 2492 | return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0"; |
12b02046 | 2493 | } |
12b02046 | 2494 | } |
87ad11b0 | 2495 | } |
2496 | ||
2497 | /* If an operand is an unoffsettable memory ref, find a register | |
2498 | we can increment temporarily to make it refer to the second word. */ | |
2499 | ||
2500 | if (optype0 == MEMOP) | |
2501 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2502 | ||
2503 | if (optype1 == MEMOP) | |
2504 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2505 | ||
2506 | /* Ok, we can do one word at a time. | |
2507 | Normally we do the low-numbered word first. | |
2508 | ||
2509 | In either case, set up in LATEHALF the operands to use | |
2510 | for the high-numbered word and in some cases alter the | |
2511 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2512 | ||
2513 | if (optype0 == REGOP) | |
ad851752 | 2514 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
87ad11b0 | 2515 | else if (optype0 == OFFSOP) |
eafc6604 | 2516 | latehalf[0] = adjust_address (operands[0], SImode, 4); |
87ad11b0 | 2517 | else |
2518 | latehalf[0] = operands[0]; | |
2519 | ||
2520 | if (optype1 == REGOP) | |
ad851752 | 2521 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
87ad11b0 | 2522 | else if (optype1 == OFFSOP) |
eafc6604 | 2523 | latehalf[1] = adjust_address (operands[1], SImode, 4); |
87ad11b0 | 2524 | else if (optype1 == CNSTOP) |
2525 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2526 | else | |
2527 | latehalf[1] = operands[1]; | |
2528 | ||
2529 | /* If the first move would clobber the source of the second one, | |
2530 | do them in the other order. | |
2531 | ||
cf489d53 | 2532 | This can happen in two cases: |
87ad11b0 | 2533 | |
cf489d53 | 2534 | mem -> register where the first half of the destination register |
2535 | is the same register used in the memory's address. Reload | |
2536 | can create such insns. | |
87ad11b0 | 2537 | |
cf489d53 | 2538 | mem in this case will be either register indirect or register |
9840d99d | 2539 | indirect plus a valid offset. |
cf489d53 | 2540 | |
2541 | register -> register move where REGNO(dst) == REGNO(src + 1) | |
9840d99d | 2542 | someone (Tim/Tege?) claimed this can happen for parameter loads. |
cf489d53 | 2543 | |
2544 | Handle mem -> register case first. */ | |
2545 | if (optype0 == REGOP | |
2546 | && (optype1 == MEMOP || optype1 == OFFSOP) | |
2547 | && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2548 | operands[1], 0)) | |
87ad11b0 | 2549 | { |
87ad11b0 | 2550 | /* Do the late half first. */ |
2551 | if (addreg1) | |
6a5d085a | 2552 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2553 | output_asm_insn (singlemove_string (latehalf), latehalf); |
cf489d53 | 2554 | |
2555 | /* Then clobber. */ | |
87ad11b0 | 2556 | if (addreg1) |
6a5d085a | 2557 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2558 | return singlemove_string (operands); |
2559 | } | |
2560 | ||
cf489d53 | 2561 | /* Now handle register -> register case. */ |
c4fa5937 | 2562 | if (optype0 == REGOP && optype1 == REGOP |
2563 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
2564 | { | |
2565 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2566 | return singlemove_string (operands); | |
2567 | } | |
2568 | ||
87ad11b0 | 2569 | /* Normal case: do the two words, low-numbered first. */ |
2570 | ||
2571 | output_asm_insn (singlemove_string (operands), operands); | |
2572 | ||
2573 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2574 | if (addreg0) | |
6a5d085a | 2575 | output_asm_insn ("ldo 4(%0),%0", &addreg0); |
87ad11b0 | 2576 | if (addreg1) |
6a5d085a | 2577 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2578 | |
2579 | /* Do that word. */ | |
2580 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2581 | ||
2582 | /* Undo the adds we just did. */ | |
2583 | if (addreg0) | |
6a5d085a | 2584 | output_asm_insn ("ldo -4(%0),%0", &addreg0); |
87ad11b0 | 2585 | if (addreg1) |
6a5d085a | 2586 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2587 | |
2588 | return ""; | |
2589 | } | |
2590 | \f | |
611a88e1 | 2591 | const char * |
5c1d8983 | 2592 | output_fp_move_double (rtx *operands) |
87ad11b0 | 2593 | { |
2594 | if (FP_REG_P (operands[0])) | |
2595 | { | |
6d36483b | 2596 | if (FP_REG_P (operands[1]) |
891b55b4 | 2597 | || operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
c6ae275c | 2598 | output_asm_insn ("fcpy,dbl %f1,%0", operands); |
6d36483b | 2599 | else |
27ef382d | 2600 | output_asm_insn ("fldd%F1 %1,%0", operands); |
87ad11b0 | 2601 | } |
2602 | else if (FP_REG_P (operands[1])) | |
2603 | { | |
27ef382d | 2604 | output_asm_insn ("fstd%F0 %1,%0", operands); |
87ad11b0 | 2605 | } |
891b55b4 | 2606 | else if (operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
2607 | { | |
2608 | if (GET_CODE (operands[0]) == REG) | |
2609 | { | |
2610 | rtx xoperands[2]; | |
ad851752 | 2611 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
891b55b4 | 2612 | xoperands[0] = operands[0]; |
2613 | output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands); | |
2614 | } | |
6d36483b | 2615 | /* This is a pain. You have to be prepared to deal with an |
01cc3b75 | 2616 | arbitrary address here including pre/post increment/decrement. |
891b55b4 | 2617 | |
2618 | so avoid this in the MD. */ | |
2619 | else | |
2620 | abort (); | |
2621 | } | |
87ad11b0 | 2622 | else abort (); |
2623 | return ""; | |
2624 | } | |
2625 | \f | |
2626 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2627 | ADDR can be effectively incremented by incrementing REG. */ | |
2628 | ||
2629 | static rtx | |
5c1d8983 | 2630 | find_addr_reg (rtx addr) |
87ad11b0 | 2631 | { |
2632 | while (GET_CODE (addr) == PLUS) | |
2633 | { | |
2634 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2635 | addr = XEXP (addr, 0); | |
2636 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2637 | addr = XEXP (addr, 1); | |
2638 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2639 | addr = XEXP (addr, 1); | |
2640 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2641 | addr = XEXP (addr, 0); | |
2642 | else | |
2643 | abort (); | |
2644 | } | |
2645 | if (GET_CODE (addr) == REG) | |
2646 | return addr; | |
2647 | abort (); | |
2648 | } | |
2649 | ||
87ad11b0 | 2650 | /* Emit code to perform a block move. |
2651 | ||
87ad11b0 | 2652 | OPERANDS[0] is the destination pointer as a REG, clobbered. |
2653 | OPERANDS[1] is the source pointer as a REG, clobbered. | |
42819d4e | 2654 | OPERANDS[2] is a register for temporary storage. |
87ad11b0 | 2655 | OPERANDS[3] is a register for temporary storage. |
a7e1bb24 | 2656 | OPERANDS[4] is the size as a CONST_INT |
9840d99d | 2657 | OPERANDS[5] is the alignment safe to use, as a CONST_INT. |
ad87de1e | 2658 | OPERANDS[6] is another temporary register. */ |
87ad11b0 | 2659 | |
611a88e1 | 2660 | const char * |
5c1d8983 | 2661 | output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) |
87ad11b0 | 2662 | { |
2663 | int align = INTVAL (operands[5]); | |
42819d4e | 2664 | unsigned long n_bytes = INTVAL (operands[4]); |
87ad11b0 | 2665 | |
a7e1bb24 | 2666 | /* We can't move more than a word at a time because the PA |
87ad11b0 | 2667 | has no longer integer move insns. (Could use fp mem ops?) */ |
a7e1bb24 | 2668 | if (align > (TARGET_64BIT ? 8 : 4)) |
2669 | align = (TARGET_64BIT ? 8 : 4); | |
87ad11b0 | 2670 | |
42819d4e | 2671 | /* Note that we know each loop below will execute at least twice |
2672 | (else we would have open-coded the copy). */ | |
2673 | switch (align) | |
87ad11b0 | 2674 | { |
a7e1bb24 | 2675 | case 8: |
2676 | /* Pre-adjust the loop counter. */ | |
2677 | operands[4] = GEN_INT (n_bytes - 16); | |
2678 | output_asm_insn ("ldi %4,%2", operands); | |
2679 | ||
2680 | /* Copying loop. */ | |
2681 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2682 | output_asm_insn ("ldd,ma 8(%1),%6", operands); | |
2683 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2684 | output_asm_insn ("addib,>= -16,%2,.-12", operands); | |
2685 | output_asm_insn ("std,ma %6,8(%0)", operands); | |
2686 | ||
2687 | /* Handle the residual. There could be up to 7 bytes of | |
2688 | residual to copy! */ | |
2689 | if (n_bytes % 16 != 0) | |
2690 | { | |
2691 | operands[4] = GEN_INT (n_bytes % 8); | |
2692 | if (n_bytes % 16 >= 8) | |
2693 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2694 | if (n_bytes % 8 != 0) | |
2695 | output_asm_insn ("ldd 0(%1),%6", operands); | |
2696 | if (n_bytes % 16 >= 8) | |
2697 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2698 | if (n_bytes % 8 != 0) | |
2699 | output_asm_insn ("stdby,e %6,%4(%0)", operands); | |
2700 | } | |
2701 | return ""; | |
2702 | ||
42819d4e | 2703 | case 4: |
2704 | /* Pre-adjust the loop counter. */ | |
2705 | operands[4] = GEN_INT (n_bytes - 8); | |
2706 | output_asm_insn ("ldi %4,%2", operands); | |
2707 | ||
2708 | /* Copying loop. */ | |
e4065f95 | 2709 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
2710 | output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands); | |
2711 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); | |
42819d4e | 2712 | output_asm_insn ("addib,>= -8,%2,.-12", operands); |
e4065f95 | 2713 | output_asm_insn ("{stws|stw},ma %6,4(%0)", operands); |
42819d4e | 2714 | |
2715 | /* Handle the residual. There could be up to 7 bytes of | |
2716 | residual to copy! */ | |
2717 | if (n_bytes % 8 != 0) | |
2718 | { | |
2719 | operands[4] = GEN_INT (n_bytes % 4); | |
2720 | if (n_bytes % 8 >= 4) | |
e4065f95 | 2721 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
42819d4e | 2722 | if (n_bytes % 4 != 0) |
34940871 | 2723 | output_asm_insn ("ldw 0(%1),%6", operands); |
42819d4e | 2724 | if (n_bytes % 8 >= 4) |
e4065f95 | 2725 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); |
42819d4e | 2726 | if (n_bytes % 4 != 0) |
e4065f95 | 2727 | output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands); |
42819d4e | 2728 | } |
2729 | return ""; | |
87ad11b0 | 2730 | |
42819d4e | 2731 | case 2: |
2732 | /* Pre-adjust the loop counter. */ | |
2733 | operands[4] = GEN_INT (n_bytes - 4); | |
2734 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2735 | |
42819d4e | 2736 | /* Copying loop. */ |
e4065f95 | 2737 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
2738 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands); | |
2739 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); | |
42819d4e | 2740 | output_asm_insn ("addib,>= -4,%2,.-12", operands); |
e4065f95 | 2741 | output_asm_insn ("{sths|sth},ma %6,2(%0)", operands); |
87ad11b0 | 2742 | |
42819d4e | 2743 | /* Handle the residual. */ |
2744 | if (n_bytes % 4 != 0) | |
2745 | { | |
2746 | if (n_bytes % 4 >= 2) | |
e4065f95 | 2747 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
42819d4e | 2748 | if (n_bytes % 2 != 0) |
34940871 | 2749 | output_asm_insn ("ldb 0(%1),%6", operands); |
42819d4e | 2750 | if (n_bytes % 4 >= 2) |
e4065f95 | 2751 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); |
42819d4e | 2752 | if (n_bytes % 2 != 0) |
34940871 | 2753 | output_asm_insn ("stb %6,0(%0)", operands); |
42819d4e | 2754 | } |
2755 | return ""; | |
87ad11b0 | 2756 | |
42819d4e | 2757 | case 1: |
2758 | /* Pre-adjust the loop counter. */ | |
2759 | operands[4] = GEN_INT (n_bytes - 2); | |
2760 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2761 | |
42819d4e | 2762 | /* Copying loop. */ |
e4065f95 | 2763 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands); |
2764 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands); | |
2765 | output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands); | |
42819d4e | 2766 | output_asm_insn ("addib,>= -2,%2,.-12", operands); |
e4065f95 | 2767 | output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands); |
87ad11b0 | 2768 | |
42819d4e | 2769 | /* Handle the residual. */ |
2770 | if (n_bytes % 2 != 0) | |
2771 | { | |
34940871 | 2772 | output_asm_insn ("ldb 0(%1),%3", operands); |
2773 | output_asm_insn ("stb %3,0(%0)", operands); | |
42819d4e | 2774 | } |
2775 | return ""; | |
87ad11b0 | 2776 | |
42819d4e | 2777 | default: |
2778 | abort (); | |
87ad11b0 | 2779 | } |
87ad11b0 | 2780 | } |
58e17b0b | 2781 | |
2782 | /* Count the number of insns necessary to handle this block move. | |
2783 | ||
2784 | Basic structure is the same as emit_block_move, except that we | |
2785 | count insns rather than emit them. */ | |
2786 | ||
611a88e1 | 2787 | static int |
a7e1bb24 | 2788 | compute_movstr_length (rtx insn) |
58e17b0b | 2789 | { |
2790 | rtx pat = PATTERN (insn); | |
fc1fb057 | 2791 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0)); |
2792 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0)); | |
42819d4e | 2793 | unsigned int n_insns = 0; |
58e17b0b | 2794 | |
2795 | /* We can't move more than four bytes at a time because the PA | |
2796 | has no longer integer move insns. (Could use fp mem ops?) */ | |
a7e1bb24 | 2797 | if (align > (TARGET_64BIT ? 8 : 4)) |
2798 | align = (TARGET_64BIT ? 8 : 4); | |
58e17b0b | 2799 | |
79bfe6ae | 2800 | /* The basic copying loop. */ |
42819d4e | 2801 | n_insns = 6; |
58e17b0b | 2802 | |
42819d4e | 2803 | /* Residuals. */ |
2804 | if (n_bytes % (2 * align) != 0) | |
58e17b0b | 2805 | { |
79bfe6ae | 2806 | if ((n_bytes % (2 * align)) >= align) |
2807 | n_insns += 2; | |
2808 | ||
2809 | if ((n_bytes % align) != 0) | |
2810 | n_insns += 2; | |
58e17b0b | 2811 | } |
42819d4e | 2812 | |
2813 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2814 | return n_insns * 4; | |
58e17b0b | 2815 | } |
a7e1bb24 | 2816 | |
2817 | /* Emit code to perform a block clear. | |
2818 | ||
2819 | OPERANDS[0] is the destination pointer as a REG, clobbered. | |
2820 | OPERANDS[1] is a register for temporary storage. | |
2821 | OPERANDS[2] is the size as a CONST_INT | |
2822 | OPERANDS[3] is the alignment safe to use, as a CONST_INT. */ | |
2823 | ||
2824 | const char * | |
2825 | output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) | |
2826 | { | |
2827 | int align = INTVAL (operands[3]); | |
2828 | unsigned long n_bytes = INTVAL (operands[2]); | |
2829 | ||
2830 | /* We can't clear more than a word at a time because the PA | |
2831 | has no longer integer move insns. */ | |
2832 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2833 | align = (TARGET_64BIT ? 8 : 4); | |
2834 | ||
2835 | /* Note that we know each loop below will execute at least twice | |
2836 | (else we would have open-coded the copy). */ | |
2837 | switch (align) | |
2838 | { | |
2839 | case 8: | |
2840 | /* Pre-adjust the loop counter. */ | |
2841 | operands[2] = GEN_INT (n_bytes - 16); | |
2842 | output_asm_insn ("ldi %2,%1", operands); | |
2843 | ||
2844 | /* Loop. */ | |
2845 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2846 | output_asm_insn ("addib,>= -16,%1,.-4", operands); | |
2847 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2848 | ||
2849 | /* Handle the residual. There could be up to 7 bytes of | |
2850 | residual to copy! */ | |
2851 | if (n_bytes % 16 != 0) | |
2852 | { | |
2853 | operands[2] = GEN_INT (n_bytes % 8); | |
2854 | if (n_bytes % 16 >= 8) | |
2855 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2856 | if (n_bytes % 8 != 0) | |
2857 | output_asm_insn ("stdby,e %%r0,%2(%0)", operands); | |
2858 | } | |
2859 | return ""; | |
2860 | ||
2861 | case 4: | |
2862 | /* Pre-adjust the loop counter. */ | |
2863 | operands[2] = GEN_INT (n_bytes - 8); | |
2864 | output_asm_insn ("ldi %2,%1", operands); | |
2865 | ||
2866 | /* Loop. */ | |
2867 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2868 | output_asm_insn ("addib,>= -8,%1,.-4", operands); | |
2869 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2870 | ||
2871 | /* Handle the residual. There could be up to 7 bytes of | |
2872 | residual to copy! */ | |
2873 | if (n_bytes % 8 != 0) | |
2874 | { | |
2875 | operands[2] = GEN_INT (n_bytes % 4); | |
2876 | if (n_bytes % 8 >= 4) | |
2877 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2878 | if (n_bytes % 4 != 0) | |
2879 | output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands); | |
2880 | } | |
2881 | return ""; | |
2882 | ||
2883 | case 2: | |
2884 | /* Pre-adjust the loop counter. */ | |
2885 | operands[2] = GEN_INT (n_bytes - 4); | |
2886 | output_asm_insn ("ldi %2,%1", operands); | |
2887 | ||
2888 | /* Loop. */ | |
2889 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2890 | output_asm_insn ("addib,>= -4,%1,.-4", operands); | |
2891 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2892 | ||
2893 | /* Handle the residual. */ | |
2894 | if (n_bytes % 4 != 0) | |
2895 | { | |
2896 | if (n_bytes % 4 >= 2) | |
2897 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2898 | if (n_bytes % 2 != 0) | |
2899 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2900 | } | |
2901 | return ""; | |
2902 | ||
2903 | case 1: | |
2904 | /* Pre-adjust the loop counter. */ | |
2905 | operands[2] = GEN_INT (n_bytes - 2); | |
2906 | output_asm_insn ("ldi %2,%1", operands); | |
2907 | ||
2908 | /* Loop. */ | |
2909 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2910 | output_asm_insn ("addib,>= -2,%1,.-4", operands); | |
2911 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2912 | ||
2913 | /* Handle the residual. */ | |
2914 | if (n_bytes % 2 != 0) | |
2915 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2916 | ||
2917 | return ""; | |
2918 | ||
2919 | default: | |
2920 | abort (); | |
2921 | } | |
2922 | } | |
2923 | ||
2924 | /* Count the number of insns necessary to handle this block move. | |
2925 | ||
2926 | Basic structure is the same as emit_block_move, except that we | |
2927 | count insns rather than emit them. */ | |
2928 | ||
2929 | static int | |
2930 | compute_clrstr_length (rtx insn) | |
2931 | { | |
2932 | rtx pat = PATTERN (insn); | |
2933 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0)); | |
2934 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0)); | |
2935 | unsigned int n_insns = 0; | |
2936 | ||
2937 | /* We can't clear more than a word at a time because the PA | |
2938 | has no longer integer move insns. */ | |
2939 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2940 | align = (TARGET_64BIT ? 8 : 4); | |
2941 | ||
2942 | /* The basic loop. */ | |
2943 | n_insns = 4; | |
2944 | ||
2945 | /* Residuals. */ | |
2946 | if (n_bytes % (2 * align) != 0) | |
2947 | { | |
2948 | if ((n_bytes % (2 * align)) >= align) | |
2949 | n_insns++; | |
2950 | ||
2951 | if ((n_bytes % align) != 0) | |
2952 | n_insns++; | |
2953 | } | |
2954 | ||
2955 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2956 | return n_insns * 4; | |
2957 | } | |
87ad11b0 | 2958 | \f |
2959 | ||
611a88e1 | 2960 | const char * |
5c1d8983 | 2961 | output_and (rtx *operands) |
e057641f | 2962 | { |
d6f01525 | 2963 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) |
e057641f | 2964 | { |
3745c59b | 2965 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
e057641f | 2966 | int ls0, ls1, ms0, p, len; |
2967 | ||
2968 | for (ls0 = 0; ls0 < 32; ls0++) | |
2969 | if ((mask & (1 << ls0)) == 0) | |
2970 | break; | |
2971 | ||
2972 | for (ls1 = ls0; ls1 < 32; ls1++) | |
2973 | if ((mask & (1 << ls1)) != 0) | |
2974 | break; | |
2975 | ||
2976 | for (ms0 = ls1; ms0 < 32; ms0++) | |
2977 | if ((mask & (1 << ms0)) == 0) | |
2978 | break; | |
2979 | ||
2980 | if (ms0 != 32) | |
ea52c577 | 2981 | abort (); |
e057641f | 2982 | |
2983 | if (ls1 == 32) | |
2984 | { | |
2985 | len = ls0; | |
2986 | ||
2987 | if (len == 0) | |
2988 | abort (); | |
2989 | ||
ef618fe4 | 2990 | operands[2] = GEN_INT (len); |
e4065f95 | 2991 | return "{extru|extrw,u} %1,31,%2,%0"; |
e057641f | 2992 | } |
2993 | else | |
2994 | { | |
2995 | /* We could use this `depi' for the case above as well, but `depi' | |
2996 | requires one more register file access than an `extru'. */ | |
2997 | ||
2998 | p = 31 - ls0; | |
2999 | len = ls1 - ls0; | |
3000 | ||
ef618fe4 | 3001 | operands[2] = GEN_INT (p); |
3002 | operands[3] = GEN_INT (len); | |
e4065f95 | 3003 | return "{depi|depwi} 0,%2,%3,%0"; |
e057641f | 3004 | } |
3005 | } | |
3006 | else | |
3007 | return "and %1,%2,%0"; | |
3008 | } | |
3009 | ||
5e3c5739 | 3010 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] |
3011 | storing the result in operands[0]. */ | |
9aadea62 | 3012 | const char * |
5c1d8983 | 3013 | output_64bit_and (rtx *operands) |
5e3c5739 | 3014 | { |
3015 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) | |
3016 | { | |
3017 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 3018 | int ls0, ls1, ms0, p, len; |
5e3c5739 | 3019 | |
3020 | for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++) | |
b7d86581 | 3021 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0) |
5e3c5739 | 3022 | break; |
3023 | ||
3024 | for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++) | |
b7d86581 | 3025 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0) |
5e3c5739 | 3026 | break; |
3027 | ||
3028 | for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++) | |
b7d86581 | 3029 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0) |
5e3c5739 | 3030 | break; |
3031 | ||
3032 | if (ms0 != HOST_BITS_PER_WIDE_INT) | |
b7d86581 | 3033 | abort (); |
5e3c5739 | 3034 | |
3035 | if (ls1 == HOST_BITS_PER_WIDE_INT) | |
3036 | { | |
3037 | len = ls0; | |
3038 | ||
3039 | if (len == 0) | |
3040 | abort (); | |
3041 | ||
3042 | operands[2] = GEN_INT (len); | |
3043 | return "extrd,u %1,63,%2,%0"; | |
3044 | } | |
3045 | else | |
3046 | { | |
3047 | /* We could use this `depi' for the case above as well, but `depi' | |
3048 | requires one more register file access than an `extru'. */ | |
3049 | ||
3050 | p = 63 - ls0; | |
3051 | len = ls1 - ls0; | |
3052 | ||
3053 | operands[2] = GEN_INT (p); | |
3054 | operands[3] = GEN_INT (len); | |
3055 | return "depdi 0,%2,%3,%0"; | |
3056 | } | |
3057 | } | |
3058 | else | |
3059 | return "and %1,%2,%0"; | |
3060 | } | |
3061 | ||
611a88e1 | 3062 | const char * |
5c1d8983 | 3063 | output_ior (rtx *operands) |
e057641f | 3064 | { |
3745c59b | 3065 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
57ed30e5 | 3066 | int bs0, bs1, p, len; |
6d36483b | 3067 | |
c9da5f4d | 3068 | if (INTVAL (operands[2]) == 0) |
3069 | return "copy %1,%0"; | |
e057641f | 3070 | |
c9da5f4d | 3071 | for (bs0 = 0; bs0 < 32; bs0++) |
3072 | if ((mask & (1 << bs0)) != 0) | |
3073 | break; | |
e057641f | 3074 | |
c9da5f4d | 3075 | for (bs1 = bs0; bs1 < 32; bs1++) |
3076 | if ((mask & (1 << bs1)) == 0) | |
3077 | break; | |
e057641f | 3078 | |
3745c59b | 3079 | if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask) |
ea52c577 | 3080 | abort (); |
e057641f | 3081 | |
c9da5f4d | 3082 | p = 31 - bs0; |
3083 | len = bs1 - bs0; | |
e057641f | 3084 | |
ef618fe4 | 3085 | operands[2] = GEN_INT (p); |
3086 | operands[3] = GEN_INT (len); | |
e4065f95 | 3087 | return "{depi|depwi} -1,%2,%3,%0"; |
e057641f | 3088 | } |
5e3c5739 | 3089 | |
3090 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] | |
3091 | storing the result in operands[0]. */ | |
9aadea62 | 3092 | const char * |
5c1d8983 | 3093 | output_64bit_ior (rtx *operands) |
5e3c5739 | 3094 | { |
3095 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 3096 | int bs0, bs1, p, len; |
5e3c5739 | 3097 | |
3098 | if (INTVAL (operands[2]) == 0) | |
3099 | return "copy %1,%0"; | |
3100 | ||
3101 | for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++) | |
b7d86581 | 3102 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0) |
5e3c5739 | 3103 | break; |
3104 | ||
3105 | for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++) | |
b7d86581 | 3106 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0) |
5e3c5739 | 3107 | break; |
3108 | ||
3109 | if (bs1 != HOST_BITS_PER_WIDE_INT | |
3110 | && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask) | |
b7d86581 | 3111 | abort (); |
5e3c5739 | 3112 | |
3113 | p = 63 - bs0; | |
3114 | len = bs1 - bs0; | |
3115 | ||
3116 | operands[2] = GEN_INT (p); | |
3117 | operands[3] = GEN_INT (len); | |
3118 | return "depdi -1,%2,%3,%0"; | |
3119 | } | |
e057641f | 3120 | \f |
58356836 | 3121 | /* Target hook for assembling integer objects. This code handles |
3122 | aligned SI and DI integers specially, since function references must | |
3123 | be preceded by P%. */ | |
3124 | ||
3125 | static bool | |
5c1d8983 | 3126 | pa_assemble_integer (rtx x, unsigned int size, int aligned_p) |
58356836 | 3127 | { |
3128 | if (size == UNITS_PER_WORD && aligned_p | |
3129 | && function_label_operand (x, VOIDmode)) | |
3130 | { | |
3131 | fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file); | |
3132 | output_addr_const (asm_out_file, x); | |
3133 | fputc ('\n', asm_out_file); | |
3134 | return true; | |
3135 | } | |
3136 | return default_assemble_integer (x, size, aligned_p); | |
3137 | } | |
3138 | \f | |
87ad11b0 | 3139 | /* Output an ascii string. */ |
57ed30e5 | 3140 | void |
5c1d8983 | 3141 | output_ascii (FILE *file, const char *p, int size) |
87ad11b0 | 3142 | { |
3143 | int i; | |
3144 | int chars_output; | |
3145 | unsigned char partial_output[16]; /* Max space 4 chars can occupy. */ | |
3146 | ||
3147 | /* The HP assembler can only take strings of 256 characters at one | |
3148 | time. This is a limitation on input line length, *not* the | |
3149 | length of the string. Sigh. Even worse, it seems that the | |
3150 | restriction is in number of input characters (see \xnn & | |
3151 | \whatever). So we have to do this very carefully. */ | |
3152 | ||
9c0ac0fd | 3153 | fputs ("\t.STRING \"", file); |
87ad11b0 | 3154 | |
3155 | chars_output = 0; | |
3156 | for (i = 0; i < size; i += 4) | |
3157 | { | |
3158 | int co = 0; | |
3159 | int io = 0; | |
3160 | for (io = 0, co = 0; io < MIN (4, size - i); io++) | |
3161 | { | |
bf8aac3e | 3162 | register unsigned int c = (unsigned char) p[i + io]; |
87ad11b0 | 3163 | |
3164 | if (c == '\"' || c == '\\') | |
3165 | partial_output[co++] = '\\'; | |
3166 | if (c >= ' ' && c < 0177) | |
3167 | partial_output[co++] = c; | |
3168 | else | |
3169 | { | |
3170 | unsigned int hexd; | |
3171 | partial_output[co++] = '\\'; | |
3172 | partial_output[co++] = 'x'; | |
3173 | hexd = c / 16 - 0 + '0'; | |
3174 | if (hexd > '9') | |
3175 | hexd -= '9' - 'a' + 1; | |
3176 | partial_output[co++] = hexd; | |
3177 | hexd = c % 16 - 0 + '0'; | |
3178 | if (hexd > '9') | |
3179 | hexd -= '9' - 'a' + 1; | |
3180 | partial_output[co++] = hexd; | |
3181 | } | |
3182 | } | |
3183 | if (chars_output + co > 243) | |
3184 | { | |
9c0ac0fd | 3185 | fputs ("\"\n\t.STRING \"", file); |
87ad11b0 | 3186 | chars_output = 0; |
3187 | } | |
a584fe8a | 3188 | fwrite (partial_output, 1, (size_t) co, file); |
87ad11b0 | 3189 | chars_output += co; |
3190 | co = 0; | |
3191 | } | |
9c0ac0fd | 3192 | fputs ("\"\n", file); |
87ad11b0 | 3193 | } |
c533da59 | 3194 | |
3195 | /* Try to rewrite floating point comparisons & branches to avoid | |
3196 | useless add,tr insns. | |
3197 | ||
3198 | CHECK_NOTES is nonzero if we should examine REG_DEAD notes | |
3199 | to see if FPCC is dead. CHECK_NOTES is nonzero for the | |
3200 | first attempt to remove useless add,tr insns. It is zero | |
3201 | for the second pass as reorg sometimes leaves bogus REG_DEAD | |
3202 | notes lying around. | |
3203 | ||
3204 | When CHECK_NOTES is zero we can only eliminate add,tr insns | |
3205 | when there's a 1:1 correspondence between fcmp and ftest/fbranch | |
3206 | instructions. */ | |
611a88e1 | 3207 | static void |
5c1d8983 | 3208 | remove_useless_addtr_insns (int check_notes) |
c533da59 | 3209 | { |
3210 | rtx insn; | |
c533da59 | 3211 | static int pass = 0; |
3212 | ||
3213 | /* This is fairly cheap, so always run it when optimizing. */ | |
3214 | if (optimize > 0) | |
3215 | { | |
3216 | int fcmp_count = 0; | |
3217 | int fbranch_count = 0; | |
3218 | ||
3219 | /* Walk all the insns in this function looking for fcmp & fbranch | |
3220 | instructions. Keep track of how many of each we find. */ | |
2efea8c0 | 3221 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3222 | { |
3223 | rtx tmp; | |
3224 | ||
3225 | /* Ignore anything that isn't an INSN or a JUMP_INSN. */ | |
3226 | if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
3227 | continue; | |
3228 | ||
3229 | tmp = PATTERN (insn); | |
3230 | ||
3231 | /* It must be a set. */ | |
3232 | if (GET_CODE (tmp) != SET) | |
3233 | continue; | |
3234 | ||
3235 | /* If the destination is CCFP, then we've found an fcmp insn. */ | |
3236 | tmp = SET_DEST (tmp); | |
3237 | if (GET_CODE (tmp) == REG && REGNO (tmp) == 0) | |
3238 | { | |
3239 | fcmp_count++; | |
3240 | continue; | |
3241 | } | |
9840d99d | 3242 | |
c533da59 | 3243 | tmp = PATTERN (insn); |
3244 | /* If this is an fbranch instruction, bump the fbranch counter. */ | |
3245 | if (GET_CODE (tmp) == SET | |
3246 | && SET_DEST (tmp) == pc_rtx | |
3247 | && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE | |
3248 | && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE | |
3249 | && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG | |
3250 | && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0) | |
3251 | { | |
3252 | fbranch_count++; | |
3253 | continue; | |
3254 | } | |
3255 | } | |
3256 | ||
3257 | ||
3258 | /* Find all floating point compare + branch insns. If possible, | |
3259 | reverse the comparison & the branch to avoid add,tr insns. */ | |
2efea8c0 | 3260 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3261 | { |
3262 | rtx tmp, next; | |
3263 | ||
3264 | /* Ignore anything that isn't an INSN. */ | |
3265 | if (GET_CODE (insn) != INSN) | |
3266 | continue; | |
3267 | ||
3268 | tmp = PATTERN (insn); | |
3269 | ||
3270 | /* It must be a set. */ | |
3271 | if (GET_CODE (tmp) != SET) | |
3272 | continue; | |
3273 | ||
3274 | /* The destination must be CCFP, which is register zero. */ | |
3275 | tmp = SET_DEST (tmp); | |
3276 | if (GET_CODE (tmp) != REG || REGNO (tmp) != 0) | |
3277 | continue; | |
3278 | ||
3279 | /* INSN should be a set of CCFP. | |
3280 | ||
3281 | See if the result of this insn is used in a reversed FP | |
3282 | conditional branch. If so, reverse our condition and | |
3283 | the branch. Doing so avoids useless add,tr insns. */ | |
3284 | next = next_insn (insn); | |
3285 | while (next) | |
3286 | { | |
3287 | /* Jumps, calls and labels stop our search. */ | |
3288 | if (GET_CODE (next) == JUMP_INSN | |
3289 | || GET_CODE (next) == CALL_INSN | |
3290 | || GET_CODE (next) == CODE_LABEL) | |
3291 | break; | |
3292 | ||
3293 | /* As does another fcmp insn. */ | |
3294 | if (GET_CODE (next) == INSN | |
3295 | && GET_CODE (PATTERN (next)) == SET | |
3296 | && GET_CODE (SET_DEST (PATTERN (next))) == REG | |
3297 | && REGNO (SET_DEST (PATTERN (next))) == 0) | |
3298 | break; | |
3299 | ||
3300 | next = next_insn (next); | |
3301 | } | |
3302 | ||
3303 | /* Is NEXT_INSN a branch? */ | |
3304 | if (next | |
3305 | && GET_CODE (next) == JUMP_INSN) | |
3306 | { | |
3307 | rtx pattern = PATTERN (next); | |
3308 | ||
3309 | /* If it a reversed fp conditional branch (eg uses add,tr) | |
3310 | and CCFP dies, then reverse our conditional and the branch | |
3311 | to avoid the add,tr. */ | |
3312 | if (GET_CODE (pattern) == SET | |
3313 | && SET_DEST (pattern) == pc_rtx | |
3314 | && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE | |
3315 | && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE | |
3316 | && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG | |
3317 | && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0 | |
3318 | && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC | |
3319 | && (fcmp_count == fbranch_count | |
3320 | || (check_notes | |
3321 | && find_regno_note (next, REG_DEAD, 0)))) | |
3322 | { | |
3323 | /* Reverse the branch. */ | |
3324 | tmp = XEXP (SET_SRC (pattern), 1); | |
3325 | XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2); | |
3326 | XEXP (SET_SRC (pattern), 2) = tmp; | |
3327 | INSN_CODE (next) = -1; | |
3328 | ||
3329 | /* Reverse our condition. */ | |
3330 | tmp = PATTERN (insn); | |
3331 | PUT_CODE (XEXP (tmp, 1), | |
ea52c577 | 3332 | (reverse_condition_maybe_unordered |
3333 | (GET_CODE (XEXP (tmp, 1))))); | |
c533da59 | 3334 | } |
3335 | } | |
3336 | } | |
3337 | } | |
3338 | ||
3339 | pass = !pass; | |
3340 | ||
3341 | } | |
87ad11b0 | 3342 | \f |
ea52c577 | 3343 | /* You may have trouble believing this, but this is the 32 bit HP-PA |
3344 | stack layout. Wow. | |
87ad11b0 | 3345 | |
3346 | Offset Contents | |
3347 | ||
3348 | Variable arguments (optional; any number may be allocated) | |
3349 | ||
3350 | SP-(4*(N+9)) arg word N | |
3351 | : : | |
3352 | SP-56 arg word 5 | |
3353 | SP-52 arg word 4 | |
3354 | ||
3355 | Fixed arguments (must be allocated; may remain unused) | |
3356 | ||
3357 | SP-48 arg word 3 | |
3358 | SP-44 arg word 2 | |
3359 | SP-40 arg word 1 | |
3360 | SP-36 arg word 0 | |
3361 | ||
3362 | Frame Marker | |
3363 | ||
3364 | SP-32 External Data Pointer (DP) | |
3365 | SP-28 External sr4 | |
3366 | SP-24 External/stub RP (RP') | |
3367 | SP-20 Current RP | |
3368 | SP-16 Static Link | |
3369 | SP-12 Clean up | |
3370 | SP-8 Calling Stub RP (RP'') | |
3371 | SP-4 Previous SP | |
3372 | ||
3373 | Top of Frame | |
3374 | ||
3375 | SP-0 Stack Pointer (points to next available address) | |
3376 | ||
3377 | */ | |
3378 | ||
3379 | /* This function saves registers as follows. Registers marked with ' are | |
3380 | this function's registers (as opposed to the previous function's). | |
3381 | If a frame_pointer isn't needed, r4 is saved as a general register; | |
3382 | the space for the frame pointer is still allocated, though, to keep | |
3383 | things simple. | |
3384 | ||
3385 | ||
3386 | Top of Frame | |
3387 | ||
3388 | SP (FP') Previous FP | |
3389 | SP + 4 Alignment filler (sigh) | |
3390 | SP + 8 Space for locals reserved here. | |
3391 | . | |
3392 | . | |
3393 | . | |
3394 | SP + n All call saved register used. | |
3395 | . | |
3396 | . | |
3397 | . | |
3398 | SP + o All call saved fp registers used. | |
3399 | . | |
3400 | . | |
3401 | . | |
3402 | SP + p (SP') points to next available address. | |
6d36483b | 3403 | |
87ad11b0 | 3404 | */ |
3405 | ||
17d9b0c3 | 3406 | /* Global variables set by output_function_prologue(). */ |
cc858176 | 3407 | /* Size of frame. Need to know this to emit return insns from |
3408 | leaf procedures. */ | |
6bcdc1fb | 3409 | static HOST_WIDE_INT actual_fsize, local_fsize; |
3410 | static int save_fregs; | |
cc858176 | 3411 | |
daee63dd | 3412 | /* Emit RTL to store REG at the memory location specified by BASE+DISP. |
359a0be8 | 3413 | Handle case where DISP > 8k by using the add_high_const patterns. |
daee63dd | 3414 | |
3415 | Note in DISP > 8k case, we will leave the high part of the address | |
3416 | in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/ | |
7014838c | 3417 | |
6a2c16d6 | 3418 | static void |
6bcdc1fb | 3419 | store_reg (int reg, HOST_WIDE_INT disp, int base) |
87ad11b0 | 3420 | { |
6a2c16d6 | 3421 | rtx insn, dest, src, basereg; |
cc858176 | 3422 | |
3423 | src = gen_rtx_REG (word_mode, reg); | |
3424 | basereg = gen_rtx_REG (Pmode, base); | |
87ad11b0 | 3425 | if (VAL_14_BITS_P (disp)) |
daee63dd | 3426 | { |
cc858176 | 3427 | dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
6a2c16d6 | 3428 | insn = emit_move_insn (dest, src); |
daee63dd | 3429 | } |
6bcdc1fb | 3430 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3431 | { | |
3432 | rtx delta = GEN_INT (disp); | |
3433 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3434 | ||
3435 | emit_move_insn (tmpreg, delta); | |
3436 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
3437 | dest = gen_rtx_MEM (word_mode, tmpreg); | |
3438 | insn = emit_move_insn (dest, src); | |
3439 | if (DO_FRAME_NOTES) | |
3440 | { | |
3441 | REG_NOTES (insn) | |
3442 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3443 | gen_rtx_SET (VOIDmode, | |
3444 | gen_rtx_MEM (word_mode, | |
3445 | gen_rtx_PLUS (word_mode, basereg, | |
3446 | delta)), | |
3447 | src), | |
3448 | REG_NOTES (insn)); | |
3449 | } | |
3450 | } | |
daee63dd | 3451 | else |
3452 | { | |
cc858176 | 3453 | rtx delta = GEN_INT (disp); |
3454 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3455 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 3456 | |
cc858176 | 3457 | emit_move_insn (tmpreg, high); |
3458 | dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
6a2c16d6 | 3459 | insn = emit_move_insn (dest, src); |
3460 | if (DO_FRAME_NOTES) | |
3461 | { | |
3462 | REG_NOTES (insn) | |
3463 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3464 | gen_rtx_SET (VOIDmode, | |
3465 | gen_rtx_MEM (word_mode, | |
3466 | gen_rtx_PLUS (word_mode, basereg, | |
3467 | delta)), | |
3468 | src), | |
3469 | REG_NOTES (insn)); | |
3470 | } | |
daee63dd | 3471 | } |
6a2c16d6 | 3472 | |
3473 | if (DO_FRAME_NOTES) | |
3474 | RTX_FRAME_RELATED_P (insn) = 1; | |
daee63dd | 3475 | } |
3476 | ||
a584fe8a | 3477 | /* Emit RTL to store REG at the memory location specified by BASE and then |
3478 | add MOD to BASE. MOD must be <= 8k. */ | |
daee63dd | 3479 | |
a584fe8a | 3480 | static void |
6bcdc1fb | 3481 | store_reg_modify (int base, int reg, HOST_WIDE_INT mod) |
a584fe8a | 3482 | { |
3483 | rtx insn, basereg, srcreg, delta; | |
3484 | ||
6bcdc1fb | 3485 | if (!VAL_14_BITS_P (mod)) |
a584fe8a | 3486 | abort (); |
3487 | ||
3488 | basereg = gen_rtx_REG (Pmode, base); | |
3489 | srcreg = gen_rtx_REG (word_mode, reg); | |
3490 | delta = GEN_INT (mod); | |
3491 | ||
3492 | insn = emit_insn (gen_post_store (basereg, srcreg, delta)); | |
3493 | if (DO_FRAME_NOTES) | |
3494 | { | |
3495 | RTX_FRAME_RELATED_P (insn) = 1; | |
3496 | ||
3497 | /* RTX_FRAME_RELATED_P must be set on each frame related set | |
3498 | in a parallel with more than one element. Don't set | |
3499 | RTX_FRAME_RELATED_P in the first set if reg is temporary | |
3500 | register 1. The effect of this operation is recorded in | |
3501 | the initial copy. */ | |
3502 | if (reg != 1) | |
3503 | { | |
3504 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1; | |
3505 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; | |
3506 | } | |
3507 | else | |
3508 | { | |
3509 | /* The first element of a PARALLEL is always processed if it is | |
3510 | a SET. Thus, we need an expression list for this case. */ | |
3511 | REG_NOTES (insn) | |
3512 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3513 | gen_rtx_SET (VOIDmode, basereg, | |
3514 | gen_rtx_PLUS (word_mode, basereg, delta)), | |
3515 | REG_NOTES (insn)); | |
3516 | } | |
3517 | } | |
3518 | } | |
3519 | ||
3520 | /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case | |
3521 | where DISP > 8k by using the add_high_const patterns. NOTE indicates | |
3522 | whether to add a frame note or not. | |
3523 | ||
3524 | In the DISP > 8k case, we leave the high part of the address in %r1. | |
3525 | There is code in expand_hppa_{prologue,epilogue} that knows about this. */ | |
7014838c | 3526 | |
6a2c16d6 | 3527 | static void |
6bcdc1fb | 3528 | set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note) |
87ad11b0 | 3529 | { |
6a2c16d6 | 3530 | rtx insn; |
cc858176 | 3531 | |
87ad11b0 | 3532 | if (VAL_14_BITS_P (disp)) |
cc858176 | 3533 | { |
6a2c16d6 | 3534 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
3535 | plus_constant (gen_rtx_REG (Pmode, base), disp)); | |
cc858176 | 3536 | } |
6bcdc1fb | 3537 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3538 | { | |
3539 | rtx basereg = gen_rtx_REG (Pmode, base); | |
3540 | rtx delta = GEN_INT (disp); | |
3541 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3542 | ||
3543 | emit_move_insn (tmpreg, delta); | |
3544 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), | |
3545 | gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
3546 | } | |
87ad11b0 | 3547 | else |
daee63dd | 3548 | { |
6a2c16d6 | 3549 | rtx basereg = gen_rtx_REG (Pmode, base); |
cc858176 | 3550 | rtx delta = GEN_INT (disp); |
6bcdc1fb | 3551 | rtx tmpreg = gen_rtx_REG (Pmode, 1); |
6a2c16d6 | 3552 | |
6bcdc1fb | 3553 | emit_move_insn (tmpreg, |
6a2c16d6 | 3554 | gen_rtx_PLUS (Pmode, basereg, |
cc858176 | 3555 | gen_rtx_HIGH (Pmode, delta))); |
6a2c16d6 | 3556 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
6bcdc1fb | 3557 | gen_rtx_LO_SUM (Pmode, tmpreg, delta)); |
daee63dd | 3558 | } |
6a2c16d6 | 3559 | |
a584fe8a | 3560 | if (DO_FRAME_NOTES && note) |
6a2c16d6 | 3561 | RTX_FRAME_RELATED_P (insn) = 1; |
87ad11b0 | 3562 | } |
3563 | ||
6bcdc1fb | 3564 | HOST_WIDE_INT |
3565 | compute_frame_size (HOST_WIDE_INT size, int *fregs_live) | |
87ad11b0 | 3566 | { |
256f9b65 | 3567 | int freg_saved = 0; |
3568 | int i, j; | |
3569 | ||
3570 | /* The code in hppa_expand_prologue and hppa_expand_epilogue must | |
3571 | be consistent with the rounding and size calculation done here. | |
3572 | Change them at the same time. */ | |
3573 | ||
3574 | /* We do our own stack alignment. First, round the size of the | |
3575 | stack locals up to a word boundary. */ | |
3576 | size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3577 | ||
3578 | /* Space for previous frame pointer + filler. If any frame is | |
3579 | allocated, we need to add in the STARTING_FRAME_OFFSET. We | |
3580 | waste some space here for the sake of HP compatibility. The | |
3581 | first slot is only used when the frame pointer is needed. */ | |
3582 | if (size || frame_pointer_needed) | |
3583 | size += STARTING_FRAME_OFFSET; | |
3584 | ||
a584fe8a | 3585 | /* If the current function calls __builtin_eh_return, then we need |
3586 | to allocate stack space for registers that will hold data for | |
3587 | the exception handler. */ | |
3588 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3589 | { | |
3590 | unsigned int i; | |
3591 | ||
3592 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
3593 | continue; | |
256f9b65 | 3594 | size += i * UNITS_PER_WORD; |
a584fe8a | 3595 | } |
3596 | ||
3a51bad9 | 3597 | /* Account for space used by the callee general register saves. */ |
256f9b65 | 3598 | for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--) |
7f7c4869 | 3599 | if (regs_ever_live[i]) |
256f9b65 | 3600 | size += UNITS_PER_WORD; |
df0651dc | 3601 | |
3a51bad9 | 3602 | /* Account for space used by the callee floating point register saves. */ |
bac38c40 | 3603 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
5e3c5739 | 3604 | if (regs_ever_live[i] |
256f9b65 | 3605 | || (!TARGET_64BIT && regs_ever_live[i + 1])) |
df0651dc | 3606 | { |
256f9b65 | 3607 | freg_saved = 1; |
002fc5f7 | 3608 | |
3a51bad9 | 3609 | /* We always save both halves of the FP register, so always |
3610 | increment the frame size by 8 bytes. */ | |
256f9b65 | 3611 | size += 8; |
df0651dc | 3612 | } |
3613 | ||
256f9b65 | 3614 | /* If any of the floating registers are saved, account for the |
3615 | alignment needed for the floating point register save block. */ | |
3616 | if (freg_saved) | |
3617 | { | |
3618 | size = (size + 7) & ~7; | |
3619 | if (fregs_live) | |
3620 | *fregs_live = 1; | |
3621 | } | |
3622 | ||
3a51bad9 | 3623 | /* The various ABIs include space for the outgoing parameters in the |
256f9b65 | 3624 | size of the current function's stack frame. We don't need to align |
3625 | for the outgoing arguments as their alignment is set by the final | |
3626 | rounding for the frame as a whole. */ | |
3627 | size += current_function_outgoing_args_size; | |
3a51bad9 | 3628 | |
3629 | /* Allocate space for the fixed frame marker. This space must be | |
e9ec370e | 3630 | allocated for any function that makes calls or allocates |
3a51bad9 | 3631 | stack space. */ |
256f9b65 | 3632 | if (!current_function_is_leaf || size) |
e9ec370e | 3633 | size += TARGET_64BIT ? 48 : 32; |
5e3c5739 | 3634 | |
256f9b65 | 3635 | /* Finally, round to the preferred stack boundary. */ |
2247cc5f | 3636 | return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1) |
3637 | & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
87ad11b0 | 3638 | } |
6d36483b | 3639 | |
17d9b0c3 | 3640 | /* Generate the assembly code for function entry. FILE is a stdio |
3641 | stream to output the code to. SIZE is an int: how many units of | |
3642 | temporary storage to allocate. | |
3643 | ||
3644 | Refer to the array `regs_ever_live' to determine which registers to | |
3645 | save; `regs_ever_live[I]' is nonzero if register number I is ever | |
3646 | used in the function. This function is responsible for knowing | |
3647 | which registers should not be saved even if used. */ | |
3648 | ||
3649 | /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block | |
3650 | of memory. If any fpu reg is used in the function, we allocate | |
3651 | such a block here, at the bottom of the frame, just in case it's needed. | |
3652 | ||
3653 | If this function is a leaf procedure, then we may choose not | |
3654 | to do a "save" insn. The decision about whether or not | |
3655 | to do this is made in regclass.c. */ | |
3656 | ||
6988553d | 3657 | static void |
5c1d8983 | 3658 | pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 3659 | { |
d151162a | 3660 | /* The function's label and associated .PROC must never be |
3661 | separated and must be output *after* any profiling declarations | |
3662 | to avoid changing spaces/subspaces within a procedure. */ | |
3663 | ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3664 | fputs ("\t.PROC\n", file); | |
3665 | ||
daee63dd | 3666 | /* hppa_expand_prologue does the dirty work now. We just need |
3667 | to output the assembler directives which denote the start | |
3668 | of a function. */ | |
6bcdc1fb | 3669 | fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize); |
df6edefa | 3670 | if (regs_ever_live[2]) |
9c0ac0fd | 3671 | fputs (",CALLS,SAVE_RP", file); |
daee63dd | 3672 | else |
9c0ac0fd | 3673 | fputs (",NO_CALLS", file); |
f3ba7709 | 3674 | |
e9ec370e | 3675 | /* The SAVE_SP flag is used to indicate that register %r3 is stored |
3676 | at the beginning of the frame and that it is used as the frame | |
3677 | pointer for the frame. We do this because our current frame | |
3678 | layout doesn't conform to that specified in the the HP runtime | |
3679 | documentation and we need a way to indicate to programs such as | |
3680 | GDB where %r3 is saved. The SAVE_SP flag was chosen because it | |
3681 | isn't used by HP compilers but is supported by the assembler. | |
3682 | However, SAVE_SP is supposed to indicate that the previous stack | |
3683 | pointer has been saved in the frame marker. */ | |
f3ba7709 | 3684 | if (frame_pointer_needed) |
9c0ac0fd | 3685 | fputs (",SAVE_SP", file); |
f3ba7709 | 3686 | |
a9960cdc | 3687 | /* Pass on information about the number of callee register saves |
9b0c95be | 3688 | performed in the prologue. |
3689 | ||
3690 | The compiler is supposed to pass the highest register number | |
6d36483b | 3691 | saved, the assembler then has to adjust that number before |
9b0c95be | 3692 | entering it into the unwind descriptor (to account for any |
6d36483b | 3693 | caller saved registers with lower register numbers than the |
9b0c95be | 3694 | first callee saved register). */ |
3695 | if (gr_saved) | |
3696 | fprintf (file, ",ENTRY_GR=%d", gr_saved + 2); | |
3697 | ||
3698 | if (fr_saved) | |
3699 | fprintf (file, ",ENTRY_FR=%d", fr_saved + 11); | |
a9960cdc | 3700 | |
9c0ac0fd | 3701 | fputs ("\n\t.ENTRY\n", file); |
daee63dd | 3702 | |
2efea8c0 | 3703 | remove_useless_addtr_insns (0); |
daee63dd | 3704 | } |
3705 | ||
57ed30e5 | 3706 | void |
5c1d8983 | 3707 | hppa_expand_prologue (void) |
daee63dd | 3708 | { |
afd7b680 | 3709 | int merge_sp_adjust_with_store = 0; |
6bcdc1fb | 3710 | HOST_WIDE_INT size = get_frame_size (); |
3711 | HOST_WIDE_INT offset; | |
3712 | int i; | |
a584fe8a | 3713 | rtx insn, tmpreg; |
daee63dd | 3714 | |
a9960cdc | 3715 | gr_saved = 0; |
3716 | fr_saved = 0; | |
3ddcbb9d | 3717 | save_fregs = 0; |
3a51bad9 | 3718 | |
256f9b65 | 3719 | /* Compute total size for frame pointer, filler, locals and rounding to |
3720 | the next word boundary. Similar code appears in compute_frame_size | |
3721 | and must be changed in tandem with this code. */ | |
3722 | local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3723 | if (local_fsize || frame_pointer_needed) | |
3724 | local_fsize += STARTING_FRAME_OFFSET; | |
3a51bad9 | 3725 | |
a1ab4fa3 | 3726 | actual_fsize = compute_frame_size (size, &save_fregs); |
87ad11b0 | 3727 | |
daee63dd | 3728 | /* Compute a few things we will use often. */ |
440c23df | 3729 | tmpreg = gen_rtx_REG (word_mode, 1); |
87ad11b0 | 3730 | |
6d36483b | 3731 | /* Save RP first. The calling conventions manual states RP will |
cc858176 | 3732 | always be stored into the caller's frame at sp - 20 or sp - 16 |
5e3c5739 | 3733 | depending on which ABI is in use. */ |
a584fe8a | 3734 | if (regs_ever_live[2] || current_function_calls_eh_return) |
6a2c16d6 | 3735 | store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM); |
6d36483b | 3736 | |
daee63dd | 3737 | /* Allocate the local frame and set up the frame pointer if needed. */ |
58361f39 | 3738 | if (actual_fsize != 0) |
3739 | { | |
3740 | if (frame_pointer_needed) | |
3741 | { | |
3742 | /* Copy the old frame pointer temporarily into %r1. Set up the | |
3743 | new stack pointer, then store away the saved old frame pointer | |
a584fe8a | 3744 | into the stack at sp and at the same time update the stack |
3745 | pointer by actual_fsize bytes. Two versions, first | |
58361f39 | 3746 | handles small (<8k) frames. The second handles large (>=8k) |
3747 | frames. */ | |
a584fe8a | 3748 | insn = emit_move_insn (tmpreg, frame_pointer_rtx); |
3749 | if (DO_FRAME_NOTES) | |
cc858176 | 3750 | { |
a584fe8a | 3751 | /* We need to record the frame pointer save here since the |
3752 | new frame pointer is set in the following insn. */ | |
3753 | RTX_FRAME_RELATED_P (insn) = 1; | |
3754 | REG_NOTES (insn) | |
3755 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3756 | gen_rtx_SET (VOIDmode, | |
3757 | gen_rtx_MEM (word_mode, stack_pointer_rtx), | |
3758 | frame_pointer_rtx), | |
3759 | REG_NOTES (insn)); | |
cc858176 | 3760 | } |
a584fe8a | 3761 | |
3762 | insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); | |
3763 | if (DO_FRAME_NOTES) | |
3764 | RTX_FRAME_RELATED_P (insn) = 1; | |
3765 | ||
3766 | if (VAL_14_BITS_P (actual_fsize)) | |
3767 | store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize); | |
58361f39 | 3768 | else |
3769 | { | |
3770 | /* It is incorrect to store the saved frame pointer at *sp, | |
3771 | then increment sp (writes beyond the current stack boundary). | |
3772 | ||
3773 | So instead use stwm to store at *sp and post-increment the | |
3774 | stack pointer as an atomic operation. Then increment sp to | |
3775 | finish allocating the new frame. */ | |
6bcdc1fb | 3776 | HOST_WIDE_INT adjust1 = 8192 - 64; |
3777 | HOST_WIDE_INT adjust2 = actual_fsize - adjust1; | |
cc858176 | 3778 | |
a584fe8a | 3779 | store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1); |
6a2c16d6 | 3780 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3781 | adjust2, 1); |
58361f39 | 3782 | } |
a584fe8a | 3783 | |
e9ec370e | 3784 | /* We set SAVE_SP in frames that need a frame pointer. Thus, |
3785 | we need to store the previous stack pointer (frame pointer) | |
3786 | into the frame marker on targets that use the HP unwind | |
3787 | library. This allows the HP unwind library to be used to | |
3788 | unwind GCC frames. However, we are not fully compatible | |
3789 | with the HP library because our frame layout differs from | |
3790 | that specified in the HP runtime specification. | |
3791 | ||
3792 | We don't want a frame note on this instruction as the frame | |
3793 | marker moves during dynamic stack allocation. | |
3794 | ||
3795 | This instruction also serves as a blockage to prevent | |
3796 | register spills from being scheduled before the stack | |
3797 | pointer is raised. This is necessary as we store | |
3798 | registers using the frame pointer as a base register, | |
3799 | and the frame pointer is set before sp is raised. */ | |
3800 | if (TARGET_HPUX_UNWIND_LIBRARY) | |
3801 | { | |
3802 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, | |
3803 | GEN_INT (TARGET_64BIT ? -8 : -4)); | |
3804 | ||
3805 | emit_move_insn (gen_rtx_MEM (word_mode, addr), | |
3806 | frame_pointer_rtx); | |
3807 | } | |
3808 | else | |
3809 | emit_insn (gen_blockage ()); | |
58361f39 | 3810 | } |
3811 | /* no frame pointer needed. */ | |
3812 | else | |
3813 | { | |
3814 | /* In some cases we can perform the first callee register save | |
3815 | and allocating the stack frame at the same time. If so, just | |
3816 | make a note of it and defer allocating the frame until saving | |
3817 | the callee registers. */ | |
df6edefa | 3818 | if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0) |
58361f39 | 3819 | merge_sp_adjust_with_store = 1; |
3820 | /* Can not optimize. Adjust the stack frame by actual_fsize | |
3821 | bytes. */ | |
3822 | else | |
6a2c16d6 | 3823 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3824 | actual_fsize, 1); |
58361f39 | 3825 | } |
372ef038 | 3826 | } |
3827 | ||
6d36483b | 3828 | /* Normal register save. |
daee63dd | 3829 | |
3830 | Do not save the frame pointer in the frame_pointer_needed case. It | |
3831 | was done earlier. */ | |
87ad11b0 | 3832 | if (frame_pointer_needed) |
3833 | { | |
a584fe8a | 3834 | offset = local_fsize; |
3835 | ||
3836 | /* Saving the EH return data registers in the frame is the simplest | |
3837 | way to get the frame unwind information emitted. We put them | |
3838 | just before the general registers. */ | |
3839 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3840 | { | |
3841 | unsigned int i, regno; | |
3842 | ||
3843 | for (i = 0; ; ++i) | |
3844 | { | |
3845 | regno = EH_RETURN_DATA_REGNO (i); | |
3846 | if (regno == INVALID_REGNUM) | |
3847 | break; | |
3848 | ||
3849 | store_reg (regno, offset, FRAME_POINTER_REGNUM); | |
3850 | offset += UNITS_PER_WORD; | |
3851 | } | |
3852 | } | |
3853 | ||
3854 | for (i = 18; i >= 4; i--) | |
98328a39 | 3855 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3856 | { |
6a2c16d6 | 3857 | store_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 3858 | offset += UNITS_PER_WORD; |
a9960cdc | 3859 | gr_saved++; |
87ad11b0 | 3860 | } |
7f7c4869 | 3861 | /* Account for %r3 which is saved in a special place. */ |
9b0c95be | 3862 | gr_saved++; |
87ad11b0 | 3863 | } |
daee63dd | 3864 | /* No frame pointer needed. */ |
87ad11b0 | 3865 | else |
3866 | { | |
a584fe8a | 3867 | offset = local_fsize - actual_fsize; |
3868 | ||
3869 | /* Saving the EH return data registers in the frame is the simplest | |
3870 | way to get the frame unwind information emitted. */ | |
3871 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3872 | { | |
3873 | unsigned int i, regno; | |
3874 | ||
3875 | for (i = 0; ; ++i) | |
3876 | { | |
3877 | regno = EH_RETURN_DATA_REGNO (i); | |
3878 | if (regno == INVALID_REGNUM) | |
3879 | break; | |
3880 | ||
3881 | /* If merge_sp_adjust_with_store is nonzero, then we can | |
3882 | optimize the first save. */ | |
3883 | if (merge_sp_adjust_with_store) | |
3884 | { | |
3885 | store_reg_modify (STACK_POINTER_REGNUM, regno, -offset); | |
3886 | merge_sp_adjust_with_store = 0; | |
3887 | } | |
3888 | else | |
3889 | store_reg (regno, offset, STACK_POINTER_REGNUM); | |
3890 | offset += UNITS_PER_WORD; | |
3891 | } | |
3892 | } | |
3893 | ||
3894 | for (i = 18; i >= 3; i--) | |
98328a39 | 3895 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3896 | { |
6d36483b | 3897 | /* If merge_sp_adjust_with_store is nonzero, then we can |
afd7b680 | 3898 | optimize the first GR save. */ |
201f01e9 | 3899 | if (merge_sp_adjust_with_store) |
afd7b680 | 3900 | { |
a584fe8a | 3901 | store_reg_modify (STACK_POINTER_REGNUM, i, -offset); |
afd7b680 | 3902 | merge_sp_adjust_with_store = 0; |
afd7b680 | 3903 | } |
3904 | else | |
6a2c16d6 | 3905 | store_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 3906 | offset += UNITS_PER_WORD; |
a9960cdc | 3907 | gr_saved++; |
87ad11b0 | 3908 | } |
daee63dd | 3909 | |
afd7b680 | 3910 | /* If we wanted to merge the SP adjustment with a GR save, but we never |
daee63dd | 3911 | did any GR saves, then just emit the adjustment here. */ |
201f01e9 | 3912 | if (merge_sp_adjust_with_store) |
6a2c16d6 | 3913 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3914 | actual_fsize, 1); |
87ad11b0 | 3915 | } |
6d36483b | 3916 | |
df6edefa | 3917 | /* The hppa calling conventions say that %r19, the pic offset |
3918 | register, is saved at sp - 32 (in this function's frame) | |
3919 | when generating PIC code. FIXME: What is the correct thing | |
3920 | to do for functions which make no calls and allocate no | |
3921 | frame? Do we need to allocate a frame, or can we just omit | |
8f177faf | 3922 | the save? For now we'll just omit the save. |
3923 | ||
3924 | We don't want a note on this insn as the frame marker can | |
3925 | move if there is a dynamic stack allocation. */ | |
df6edefa | 3926 | if (flag_pic && actual_fsize != 0 && !TARGET_64BIT) |
8f177faf | 3927 | { |
3928 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32)); | |
3929 | ||
3930 | emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx); | |
3931 | ||
3932 | } | |
df6edefa | 3933 | |
87ad11b0 | 3934 | /* Align pointer properly (doubleword boundary). */ |
3935 | offset = (offset + 7) & ~7; | |
3936 | ||
3937 | /* Floating point register store. */ | |
3938 | if (save_fregs) | |
87ad11b0 | 3939 | { |
a584fe8a | 3940 | rtx base; |
3941 | ||
daee63dd | 3942 | /* First get the frame or stack pointer to the start of the FP register |
3943 | save area. */ | |
a1ab4fa3 | 3944 | if (frame_pointer_needed) |
a584fe8a | 3945 | { |
3946 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); | |
3947 | base = frame_pointer_rtx; | |
3948 | } | |
a1ab4fa3 | 3949 | else |
a584fe8a | 3950 | { |
3951 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); | |
3952 | base = stack_pointer_rtx; | |
3953 | } | |
daee63dd | 3954 | |
3955 | /* Now actually save the FP registers. */ | |
bac38c40 | 3956 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
7f7c4869 | 3957 | { |
5e3c5739 | 3958 | if (regs_ever_live[i] |
3959 | || (! TARGET_64BIT && regs_ever_live[i + 1])) | |
7f7c4869 | 3960 | { |
6a2c16d6 | 3961 | rtx addr, insn, reg; |
cc858176 | 3962 | addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); |
3963 | reg = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 3964 | insn = emit_move_insn (addr, reg); |
3965 | if (DO_FRAME_NOTES) | |
3966 | { | |
3967 | RTX_FRAME_RELATED_P (insn) = 1; | |
a584fe8a | 3968 | if (TARGET_64BIT) |
3969 | { | |
3970 | rtx mem = gen_rtx_MEM (DFmode, | |
3971 | plus_constant (base, offset)); | |
3972 | REG_NOTES (insn) | |
3973 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3974 | gen_rtx_SET (VOIDmode, mem, reg), | |
3975 | REG_NOTES (insn)); | |
3976 | } | |
3977 | else | |
3978 | { | |
3979 | rtx meml = gen_rtx_MEM (SFmode, | |
3980 | plus_constant (base, offset)); | |
3981 | rtx memr = gen_rtx_MEM (SFmode, | |
3982 | plus_constant (base, offset + 4)); | |
3983 | rtx regl = gen_rtx_REG (SFmode, i); | |
3984 | rtx regr = gen_rtx_REG (SFmode, i + 1); | |
3985 | rtx setl = gen_rtx_SET (VOIDmode, meml, regl); | |
3986 | rtx setr = gen_rtx_SET (VOIDmode, memr, regr); | |
3987 | rtvec vec; | |
3988 | ||
3989 | RTX_FRAME_RELATED_P (setl) = 1; | |
3990 | RTX_FRAME_RELATED_P (setr) = 1; | |
3991 | vec = gen_rtvec (2, setl, setr); | |
3992 | REG_NOTES (insn) | |
3993 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3994 | gen_rtx_SEQUENCE (VOIDmode, vec), | |
3995 | REG_NOTES (insn)); | |
3996 | } | |
6a2c16d6 | 3997 | } |
3998 | offset += GET_MODE_SIZE (DFmode); | |
7f7c4869 | 3999 | fr_saved++; |
4000 | } | |
4001 | } | |
87ad11b0 | 4002 | } |
4003 | } | |
4004 | ||
cc858176 | 4005 | /* Emit RTL to load REG from the memory location specified by BASE+DISP. |
4006 | Handle case where DISP > 8k by using the add_high_const patterns. */ | |
4007 | ||
6a2c16d6 | 4008 | static void |
6bcdc1fb | 4009 | load_reg (int reg, HOST_WIDE_INT disp, int base) |
cc858176 | 4010 | { |
6bcdc1fb | 4011 | rtx dest = gen_rtx_REG (word_mode, reg); |
4012 | rtx basereg = gen_rtx_REG (Pmode, base); | |
4013 | rtx src; | |
cc858176 | 4014 | |
cc858176 | 4015 | if (VAL_14_BITS_P (disp)) |
6bcdc1fb | 4016 | src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
4017 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) | |
cc858176 | 4018 | { |
6bcdc1fb | 4019 | rtx delta = GEN_INT (disp); |
4020 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
4021 | ||
4022 | emit_move_insn (tmpreg, delta); | |
4023 | if (TARGET_DISABLE_INDEXING) | |
4024 | { | |
4025 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
4026 | src = gen_rtx_MEM (word_mode, tmpreg); | |
4027 | } | |
4028 | else | |
4029 | src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
cc858176 | 4030 | } |
4031 | else | |
4032 | { | |
4033 | rtx delta = GEN_INT (disp); | |
4034 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
4035 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 4036 | |
cc858176 | 4037 | emit_move_insn (tmpreg, high); |
4038 | src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
cc858176 | 4039 | } |
6bcdc1fb | 4040 | |
4041 | emit_move_insn (dest, src); | |
cc858176 | 4042 | } |
daee63dd | 4043 | |
2247cc5f | 4044 | /* Update the total code bytes output to the text section. */ |
4045 | ||
4046 | static void | |
5c1d8983 | 4047 | update_total_code_bytes (int nbytes) |
2247cc5f | 4048 | { |
4049 | if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM) | |
8a05c3c2 | 4050 | && !IN_NAMED_SECTION_P (cfun->decl)) |
2247cc5f | 4051 | { |
4052 | if (INSN_ADDRESSES_SET_P ()) | |
4053 | { | |
4054 | unsigned long old_total = total_code_bytes; | |
4055 | ||
4056 | total_code_bytes += nbytes; | |
4057 | ||
4058 | /* Be prepared to handle overflows. */ | |
4059 | if (old_total > total_code_bytes) | |
4060 | total_code_bytes = -1; | |
4061 | } | |
4062 | else | |
4063 | total_code_bytes = -1; | |
4064 | } | |
4065 | } | |
4066 | ||
17d9b0c3 | 4067 | /* This function generates the assembly code for function exit. |
4068 | Args are as for output_function_prologue (). | |
4069 | ||
4070 | The function epilogue should not depend on the current stack | |
4071 | pointer! It should use the frame pointer only. This is mandatory | |
4072 | because of alloca; we also take advantage of it to omit stack | |
6dc3b0d9 | 4073 | adjustments before returning. */ |
17d9b0c3 | 4074 | |
4075 | static void | |
5c1d8983 | 4076 | pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 4077 | { |
3695c664 | 4078 | rtx insn = get_last_insn (); |
4079 | ||
2247cc5f | 4080 | last_address = 0; |
4081 | ||
daee63dd | 4082 | /* hppa_expand_epilogue does the dirty work now. We just need |
4083 | to output the assembler directives which denote the end | |
3695c664 | 4084 | of a function. |
4085 | ||
4086 | To make debuggers happy, emit a nop if the epilogue was completely | |
4087 | eliminated due to a volatile call as the last insn in the | |
6d36483b | 4088 | current function. That way the return address (in %r2) will |
3695c664 | 4089 | always point to a valid instruction in the current function. */ |
4090 | ||
4091 | /* Get the last real insn. */ | |
4092 | if (GET_CODE (insn) == NOTE) | |
4093 | insn = prev_real_insn (insn); | |
4094 | ||
4095 | /* If it is a sequence, then look inside. */ | |
4096 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
4097 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
4098 | ||
6d36483b | 4099 | /* If insn is a CALL_INSN, then it must be a call to a volatile |
3695c664 | 4100 | function (otherwise there would be epilogue insns). */ |
4101 | if (insn && GET_CODE (insn) == CALL_INSN) | |
90c41894 | 4102 | { |
4103 | fputs ("\tnop\n", file); | |
4104 | last_address += 4; | |
4105 | } | |
6d36483b | 4106 | |
9c0ac0fd | 4107 | fputs ("\t.EXIT\n\t.PROCEND\n", file); |
90c41894 | 4108 | |
2247cc5f | 4109 | if (INSN_ADDRESSES_SET_P ()) |
90c41894 | 4110 | { |
2247cc5f | 4111 | insn = get_last_nonnote_insn (); |
4112 | last_address += INSN_ADDRESSES (INSN_UID (insn)); | |
4113 | if (INSN_P (insn)) | |
4114 | last_address += insn_default_length (insn); | |
4115 | last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) | |
4116 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
90c41894 | 4117 | } |
2247cc5f | 4118 | |
4119 | /* Finally, update the total number of code bytes output so far. */ | |
4120 | update_total_code_bytes (last_address); | |
daee63dd | 4121 | } |
afd7b680 | 4122 | |
daee63dd | 4123 | void |
5c1d8983 | 4124 | hppa_expand_epilogue (void) |
daee63dd | 4125 | { |
6d36483b | 4126 | rtx tmpreg; |
6bcdc1fb | 4127 | HOST_WIDE_INT offset; |
4128 | HOST_WIDE_INT ret_off = 0; | |
4129 | int i; | |
58361f39 | 4130 | int merge_sp_adjust_with_load = 0; |
daee63dd | 4131 | |
4132 | /* We will use this often. */ | |
440c23df | 4133 | tmpreg = gen_rtx_REG (word_mode, 1); |
daee63dd | 4134 | |
4135 | /* Try to restore RP early to avoid load/use interlocks when | |
4136 | RP gets used in the return (bv) instruction. This appears to still | |
6dc3b0d9 | 4137 | be necessary even when we schedule the prologue and epilogue. */ |
a584fe8a | 4138 | if (regs_ever_live [2] || current_function_calls_eh_return) |
58361f39 | 4139 | { |
4140 | ret_off = TARGET_64BIT ? -16 : -20; | |
4141 | if (frame_pointer_needed) | |
4142 | { | |
6a2c16d6 | 4143 | load_reg (2, ret_off, FRAME_POINTER_REGNUM); |
58361f39 | 4144 | ret_off = 0; |
4145 | } | |
4146 | else | |
4147 | { | |
4148 | /* No frame pointer, and stack is smaller than 8k. */ | |
4149 | if (VAL_14_BITS_P (ret_off - actual_fsize)) | |
4150 | { | |
6a2c16d6 | 4151 | load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM); |
58361f39 | 4152 | ret_off = 0; |
4153 | } | |
4154 | } | |
4155 | } | |
daee63dd | 4156 | |
4157 | /* General register restores. */ | |
87ad11b0 | 4158 | if (frame_pointer_needed) |
4159 | { | |
a584fe8a | 4160 | offset = local_fsize; |
4161 | ||
4162 | /* If the current function calls __builtin_eh_return, then we need | |
4163 | to restore the saved EH data registers. */ | |
4164 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
4165 | { | |
4166 | unsigned int i, regno; | |
4167 | ||
4168 | for (i = 0; ; ++i) | |
4169 | { | |
4170 | regno = EH_RETURN_DATA_REGNO (i); | |
4171 | if (regno == INVALID_REGNUM) | |
4172 | break; | |
4173 | ||
4174 | load_reg (regno, offset, FRAME_POINTER_REGNUM); | |
4175 | offset += UNITS_PER_WORD; | |
4176 | } | |
4177 | } | |
4178 | ||
4179 | for (i = 18; i >= 4; i--) | |
98328a39 | 4180 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 4181 | { |
6a2c16d6 | 4182 | load_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 4183 | offset += UNITS_PER_WORD; |
87ad11b0 | 4184 | } |
87ad11b0 | 4185 | } |
4186 | else | |
4187 | { | |
a584fe8a | 4188 | offset = local_fsize - actual_fsize; |
4189 | ||
4190 | /* If the current function calls __builtin_eh_return, then we need | |
4191 | to restore the saved EH data registers. */ | |
4192 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
4193 | { | |
4194 | unsigned int i, regno; | |
4195 | ||
4196 | for (i = 0; ; ++i) | |
4197 | { | |
4198 | regno = EH_RETURN_DATA_REGNO (i); | |
4199 | if (regno == INVALID_REGNUM) | |
4200 | break; | |
4201 | ||
4202 | /* Only for the first load. | |
4203 | merge_sp_adjust_with_load holds the register load | |
4204 | with which we will merge the sp adjustment. */ | |
4205 | if (merge_sp_adjust_with_load == 0 | |
4206 | && local_fsize == 0 | |
4207 | && VAL_14_BITS_P (-actual_fsize)) | |
4208 | merge_sp_adjust_with_load = regno; | |
4209 | else | |
4210 | load_reg (regno, offset, STACK_POINTER_REGNUM); | |
4211 | offset += UNITS_PER_WORD; | |
4212 | } | |
4213 | } | |
4214 | ||
4215 | for (i = 18; i >= 3; i--) | |
7f7c4869 | 4216 | { |
98328a39 | 4217 | if (regs_ever_live[i] && ! call_used_regs[i]) |
7f7c4869 | 4218 | { |
7f7c4869 | 4219 | /* Only for the first load. |
4220 | merge_sp_adjust_with_load holds the register load | |
4221 | with which we will merge the sp adjustment. */ | |
58361f39 | 4222 | if (merge_sp_adjust_with_load == 0 |
7f7c4869 | 4223 | && local_fsize == 0 |
58361f39 | 4224 | && VAL_14_BITS_P (-actual_fsize)) |
7f7c4869 | 4225 | merge_sp_adjust_with_load = i; |
4226 | else | |
6a2c16d6 | 4227 | load_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 4228 | offset += UNITS_PER_WORD; |
7f7c4869 | 4229 | } |
4230 | } | |
87ad11b0 | 4231 | } |
daee63dd | 4232 | |
87ad11b0 | 4233 | /* Align pointer properly (doubleword boundary). */ |
4234 | offset = (offset + 7) & ~7; | |
4235 | ||
daee63dd | 4236 | /* FP register restores. */ |
87ad11b0 | 4237 | if (save_fregs) |
87ad11b0 | 4238 | { |
daee63dd | 4239 | /* Adjust the register to index off of. */ |
a1ab4fa3 | 4240 | if (frame_pointer_needed) |
a584fe8a | 4241 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); |
a1ab4fa3 | 4242 | else |
a584fe8a | 4243 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); |
daee63dd | 4244 | |
4245 | /* Actually do the restores now. */ | |
bac38c40 | 4246 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
cc858176 | 4247 | if (regs_ever_live[i] |
4248 | || (! TARGET_64BIT && regs_ever_live[i + 1])) | |
4249 | { | |
4250 | rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); | |
4251 | rtx dest = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 4252 | emit_move_insn (dest, src); |
cc858176 | 4253 | } |
87ad11b0 | 4254 | } |
daee63dd | 4255 | |
14660146 | 4256 | /* Emit a blockage insn here to keep these insns from being moved to |
4257 | an earlier spot in the epilogue, or into the main instruction stream. | |
4258 | ||
4259 | This is necessary as we must not cut the stack back before all the | |
4260 | restores are finished. */ | |
4261 | emit_insn (gen_blockage ()); | |
daee63dd | 4262 | |
9840d99d | 4263 | /* Reset stack pointer (and possibly frame pointer). The stack |
42819d4e | 4264 | pointer is initially set to fp + 64 to avoid a race condition. */ |
58361f39 | 4265 | if (frame_pointer_needed) |
87ad11b0 | 4266 | { |
cc858176 | 4267 | rtx delta = GEN_INT (-64); |
a584fe8a | 4268 | |
4269 | set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0); | |
4270 | emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta)); | |
87ad11b0 | 4271 | } |
daee63dd | 4272 | /* If we were deferring a callee register restore, do it now. */ |
58361f39 | 4273 | else if (merge_sp_adjust_with_load) |
4274 | { | |
4275 | rtx delta = GEN_INT (-actual_fsize); | |
cc858176 | 4276 | rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load); |
a584fe8a | 4277 | |
4278 | emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)); | |
58361f39 | 4279 | } |
daee63dd | 4280 | else if (actual_fsize != 0) |
a584fe8a | 4281 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
4282 | - actual_fsize, 0); | |
58361f39 | 4283 | |
4284 | /* If we haven't restored %r2 yet (no frame pointer, and a stack | |
4285 | frame greater than 8k), do so now. */ | |
4286 | if (ret_off != 0) | |
6a2c16d6 | 4287 | load_reg (2, ret_off, STACK_POINTER_REGNUM); |
a584fe8a | 4288 | |
4289 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
4290 | { | |
4291 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
4292 | ||
4293 | emit_insn (gen_blockage ()); | |
4294 | emit_insn (TARGET_64BIT | |
4295 | ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa) | |
4296 | : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa)); | |
4297 | } | |
87ad11b0 | 4298 | } |
4299 | ||
d7e2f694 | 4300 | rtx |
5c1d8983 | 4301 | hppa_pic_save_rtx (void) |
cf3de5bb | 4302 | { |
d7e2f694 | 4303 | return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM); |
df6edefa | 4304 | } |
4305 | ||
4306 | void | |
5c1d8983 | 4307 | hppa_profile_hook (int label_no) |
df6edefa | 4308 | { |
4da37e2f | 4309 | /* We use SImode for the address of the function in both 32 and |
4310 | 64-bit code to avoid having to provide DImode versions of the | |
4311 | lcla2 and load_offset_label_address insn patterns. */ | |
4312 | rtx reg = gen_reg_rtx (SImode); | |
4313 | rtx label_rtx = gen_label_rtx (); | |
a9ac13e4 | 4314 | rtx begin_label_rtx, call_insn; |
4315 | char begin_label_name[16]; | |
df6edefa | 4316 | |
a9ac13e4 | 4317 | ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL, |
b8a21949 | 4318 | label_no); |
4da37e2f | 4319 | begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name)); |
df6edefa | 4320 | |
4321 | if (TARGET_64BIT) | |
4322 | emit_move_insn (arg_pointer_rtx, | |
4323 | gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, | |
4324 | GEN_INT (64))); | |
4325 | ||
df6edefa | 4326 | emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2)); |
4327 | ||
4da37e2f | 4328 | /* The address of the function is loaded into %r25 with a instruction- |
4329 | relative sequence that avoids the use of relocations. The sequence | |
4330 | is split so that the load_offset_label_address instruction can | |
4331 | occupy the delay slot of the call to _mcount. */ | |
4332 | if (TARGET_PA_20) | |
4333 | emit_insn (gen_lcla2 (reg, label_rtx)); | |
4334 | else | |
4335 | emit_insn (gen_lcla1 (reg, label_rtx)); | |
4336 | ||
4337 | emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25), | |
4338 | reg, begin_label_rtx, label_rtx)); | |
4339 | ||
df6edefa | 4340 | #ifndef NO_PROFILE_COUNTERS |
4341 | { | |
4342 | rtx count_label_rtx, addr, r24; | |
a9ac13e4 | 4343 | char count_label_name[16]; |
df6edefa | 4344 | |
a9ac13e4 | 4345 | ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no); |
4346 | count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name)); | |
df6edefa | 4347 | |
831a12d9 | 4348 | addr = force_reg (Pmode, count_label_rtx); |
df6edefa | 4349 | r24 = gen_rtx_REG (Pmode, 24); |
4350 | emit_move_insn (r24, addr); | |
4351 | ||
df6edefa | 4352 | call_insn = |
4da37e2f | 4353 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4354 | gen_rtx_SYMBOL_REF (Pmode, | |
4355 | "_mcount")), | |
4356 | GEN_INT (TARGET_64BIT ? 24 : 12))); | |
df6edefa | 4357 | |
4358 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24); | |
4359 | } | |
4360 | #else | |
4da37e2f | 4361 | |
df6edefa | 4362 | call_insn = |
4da37e2f | 4363 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4364 | gen_rtx_SYMBOL_REF (Pmode, | |
4365 | "_mcount")), | |
4366 | GEN_INT (TARGET_64BIT ? 16 : 8))); | |
4367 | ||
df6edefa | 4368 | #endif |
4369 | ||
4da37e2f | 4370 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25)); |
4371 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26)); | |
4372 | ||
df6edefa | 4373 | /* Indicate the _mcount call cannot throw, nor will it execute a |
4374 | non-local goto. */ | |
4375 | REG_NOTES (call_insn) | |
4376 | = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn)); | |
cf3de5bb | 4377 | } |
4378 | ||
e07ff380 | 4379 | /* Fetch the return address for the frame COUNT steps up from |
4380 | the current frame, after the prologue. FRAMEADDR is the | |
4381 | frame pointer of the COUNT frame. | |
4382 | ||
f49b2e77 | 4383 | We want to ignore any export stub remnants here. To handle this, |
4384 | we examine the code at the return address, and if it is an export | |
4385 | stub, we return a memory rtx for the stub return address stored | |
4386 | at frame-24. | |
a6c6fd6c | 4387 | |
4388 | The value returned is used in two different ways: | |
4389 | ||
4390 | 1. To find a function's caller. | |
4391 | ||
4392 | 2. To change the return address for a function. | |
4393 | ||
4394 | This function handles most instances of case 1; however, it will | |
4395 | fail if there are two levels of stubs to execute on the return | |
4396 | path. The only way I believe that can happen is if the return value | |
4397 | needs a parameter relocation, which never happens for C code. | |
4398 | ||
4399 | This function handles most instances of case 2; however, it will | |
4400 | fail if we did not originally have stub code on the return path | |
f49b2e77 | 4401 | but will need stub code on the new return path. This can happen if |
a6c6fd6c | 4402 | the caller & callee are both in the main program, but the new |
f49b2e77 | 4403 | return location is in a shared library. */ |
e07ff380 | 4404 | |
4405 | rtx | |
5c1d8983 | 4406 | return_addr_rtx (int count, rtx frameaddr) |
e07ff380 | 4407 | { |
4408 | rtx label; | |
f49b2e77 | 4409 | rtx rp; |
e07ff380 | 4410 | rtx saved_rp; |
4411 | rtx ins; | |
4412 | ||
f49b2e77 | 4413 | if (count != 0) |
4414 | return NULL_RTX; | |
b29897dd | 4415 | |
f49b2e77 | 4416 | rp = get_hard_reg_initial_val (Pmode, 2); |
e07ff380 | 4417 | |
f49b2e77 | 4418 | if (TARGET_64BIT || TARGET_NO_SPACE_REGS) |
4419 | return rp; | |
e07ff380 | 4420 | |
b29897dd | 4421 | saved_rp = gen_reg_rtx (Pmode); |
f49b2e77 | 4422 | emit_move_insn (saved_rp, rp); |
e07ff380 | 4423 | |
4424 | /* Get pointer to the instruction stream. We have to mask out the | |
4425 | privilege level from the two low order bits of the return address | |
4426 | pointer here so that ins will point to the start of the first | |
4427 | instruction that would have been executed if we returned. */ | |
f49b2e77 | 4428 | ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR)); |
e07ff380 | 4429 | label = gen_label_rtx (); |
4430 | ||
4431 | /* Check the instruction stream at the normal return address for the | |
4432 | export stub: | |
4433 | ||
4434 | 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp | |
4435 | 0x004010a1 | stub+12: ldsid (sr0,rp),r1 | |
4436 | 0x00011820 | stub+16: mtsp r1,sr0 | |
4437 | 0xe0400002 | stub+20: be,n 0(sr0,rp) | |
4438 | ||
4439 | If it is an export stub, than our return address is really in | |
4440 | -24[frameaddr]. */ | |
4441 | ||
e00b80b2 | 4442 | emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE, |
4443 | NULL_RTX, SImode, 1); | |
e07ff380 | 4444 | emit_jump_insn (gen_bne (label)); |
4445 | ||
ad851752 | 4446 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)), |
e00b80b2 | 4447 | GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4448 | emit_jump_insn (gen_bne (label)); |
4449 | ||
ad851752 | 4450 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)), |
e00b80b2 | 4451 | GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4452 | emit_jump_insn (gen_bne (label)); |
4453 | ||
ad851752 | 4454 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)), |
e00b80b2 | 4455 | GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4456 | |
f49b2e77 | 4457 | /* If there is no export stub then just use the value saved from |
4458 | the return pointer register. */ | |
e07ff380 | 4459 | |
4460 | emit_jump_insn (gen_bne (label)); | |
4461 | ||
f49b2e77 | 4462 | /* Here we know that our return address points to an export |
e07ff380 | 4463 | stub. We don't want to return the address of the export stub, |
f49b2e77 | 4464 | but rather the return address of the export stub. That return |
4465 | address is stored at -24[frameaddr]. */ | |
e07ff380 | 4466 | |
f49b2e77 | 4467 | emit_move_insn (saved_rp, |
4468 | gen_rtx_MEM (Pmode, | |
4469 | memory_address (Pmode, | |
4470 | plus_constant (frameaddr, | |
4471 | -24)))); | |
e07ff380 | 4472 | |
4473 | emit_label (label); | |
f49b2e77 | 4474 | return saved_rp; |
e07ff380 | 4475 | } |
4476 | ||
757d4970 | 4477 | /* This is only valid once reload has completed because it depends on |
4478 | knowing exactly how much (if any) frame there is and... | |
4479 | ||
4480 | It's only valid if there is no frame marker to de-allocate and... | |
4481 | ||
4482 | It's only valid if %r2 hasn't been saved into the caller's frame | |
4483 | (we're not profiling and %r2 isn't live anywhere). */ | |
4484 | int | |
5c1d8983 | 4485 | hppa_can_use_return_insn_p (void) |
757d4970 | 4486 | { |
4487 | return (reload_completed | |
4488 | && (compute_frame_size (get_frame_size (), 0) ? 0 : 1) | |
757d4970 | 4489 | && ! regs_ever_live[2] |
4490 | && ! frame_pointer_needed); | |
4491 | } | |
4492 | ||
87ad11b0 | 4493 | void |
5c1d8983 | 4494 | emit_bcond_fp (enum rtx_code code, rtx operand0) |
87ad11b0 | 4495 | { |
ad851752 | 4496 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, |
4497 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
4498 | gen_rtx_fmt_ee (code, | |
4499 | VOIDmode, | |
4500 | gen_rtx_REG (CCFPmode, 0), | |
4501 | const0_rtx), | |
4502 | gen_rtx_LABEL_REF (VOIDmode, operand0), | |
4503 | pc_rtx))); | |
87ad11b0 | 4504 | |
4505 | } | |
4506 | ||
4507 | rtx | |
5c1d8983 | 4508 | gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1) |
87ad11b0 | 4509 | { |
ad851752 | 4510 | return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0), |
4511 | gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1)); | |
87ad11b0 | 4512 | } |
4513 | ||
8b49b3c7 | 4514 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
4515 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4516 | ||
747af5e7 | 4517 | static int |
5c1d8983 | 4518 | pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
8b49b3c7 | 4519 | { |
43048d2c | 4520 | enum attr_type attr_type; |
4521 | ||
cde3e16c | 4522 | /* Don't adjust costs for a pa8000 chip, also do not adjust any |
4523 | true dependencies as they are described with bypasses now. */ | |
4524 | if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0) | |
342aabd9 | 4525 | return cost; |
4526 | ||
d402da4b | 4527 | if (! recog_memoized (insn)) |
4528 | return 0; | |
8b49b3c7 | 4529 | |
43048d2c | 4530 | attr_type = get_attr_type (insn); |
4531 | ||
cde3e16c | 4532 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI) |
8b49b3c7 | 4533 | { |
4534 | /* Anti dependency; DEP_INSN reads a register that INSN writes some | |
4535 | cycles later. */ | |
4536 | ||
43048d2c | 4537 | if (attr_type == TYPE_FPLOAD) |
8b49b3c7 | 4538 | { |
d402da4b | 4539 | rtx pat = PATTERN (insn); |
4540 | rtx dep_pat = PATTERN (dep_insn); | |
4541 | if (GET_CODE (pat) == PARALLEL) | |
4542 | { | |
4543 | /* This happens for the fldXs,mb patterns. */ | |
4544 | pat = XVECEXP (pat, 0, 0); | |
4545 | } | |
4546 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
8b49b3c7 | 4547 | /* If this happens, we have to extend this to schedule |
d402da4b | 4548 | optimally. Return 0 for now. */ |
4549 | return 0; | |
8b49b3c7 | 4550 | |
d402da4b | 4551 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) |
8b49b3c7 | 4552 | { |
d402da4b | 4553 | if (! recog_memoized (dep_insn)) |
4554 | return 0; | |
8b49b3c7 | 4555 | switch (get_attr_type (dep_insn)) |
4556 | { | |
4557 | case TYPE_FPALU: | |
134b4858 | 4558 | case TYPE_FPMULSGL: |
4559 | case TYPE_FPMULDBL: | |
8b49b3c7 | 4560 | case TYPE_FPDIVSGL: |
4561 | case TYPE_FPDIVDBL: | |
4562 | case TYPE_FPSQRTSGL: | |
4563 | case TYPE_FPSQRTDBL: | |
d402da4b | 4564 | /* A fpload can't be issued until one cycle before a |
01cc3b75 | 4565 | preceding arithmetic operation has finished if |
d402da4b | 4566 | the target of the fpload is any of the sources |
4567 | (or destination) of the arithmetic operation. */ | |
cde3e16c | 4568 | return insn_default_latency (dep_insn) - 1; |
134b4858 | 4569 | |
4570 | default: | |
4571 | return 0; | |
4572 | } | |
4573 | } | |
4574 | } | |
43048d2c | 4575 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4576 | { |
4577 | rtx pat = PATTERN (insn); | |
4578 | rtx dep_pat = PATTERN (dep_insn); | |
4579 | if (GET_CODE (pat) == PARALLEL) | |
4580 | { | |
4581 | /* This happens for the fldXs,mb patterns. */ | |
4582 | pat = XVECEXP (pat, 0, 0); | |
4583 | } | |
4584 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4585 | /* If this happens, we have to extend this to schedule | |
4586 | optimally. Return 0 for now. */ | |
4587 | return 0; | |
4588 | ||
4589 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) | |
4590 | { | |
4591 | if (! recog_memoized (dep_insn)) | |
4592 | return 0; | |
4593 | switch (get_attr_type (dep_insn)) | |
4594 | { | |
4595 | case TYPE_FPDIVSGL: | |
4596 | case TYPE_FPDIVDBL: | |
4597 | case TYPE_FPSQRTSGL: | |
4598 | case TYPE_FPSQRTDBL: | |
4599 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4600 | preceding divide or sqrt operation has finished if |
134b4858 | 4601 | the target of the ALU flop is any of the sources |
4602 | (or destination) of the divide or sqrt operation. */ | |
cde3e16c | 4603 | return insn_default_latency (dep_insn) - 2; |
8b49b3c7 | 4604 | |
4605 | default: | |
4606 | return 0; | |
4607 | } | |
4608 | } | |
4609 | } | |
4610 | ||
4611 | /* For other anti dependencies, the cost is 0. */ | |
4612 | return 0; | |
4613 | } | |
134b4858 | 4614 | else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) |
4615 | { | |
4616 | /* Output dependency; DEP_INSN writes a register that INSN writes some | |
4617 | cycles later. */ | |
43048d2c | 4618 | if (attr_type == TYPE_FPLOAD) |
134b4858 | 4619 | { |
4620 | rtx pat = PATTERN (insn); | |
4621 | rtx dep_pat = PATTERN (dep_insn); | |
4622 | if (GET_CODE (pat) == PARALLEL) | |
4623 | { | |
4624 | /* This happens for the fldXs,mb patterns. */ | |
4625 | pat = XVECEXP (pat, 0, 0); | |
4626 | } | |
4627 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4628 | /* If this happens, we have to extend this to schedule | |
4629 | optimally. Return 0 for now. */ | |
4630 | return 0; | |
4631 | ||
4632 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4633 | { | |
4634 | if (! recog_memoized (dep_insn)) | |
4635 | return 0; | |
4636 | switch (get_attr_type (dep_insn)) | |
4637 | { | |
4638 | case TYPE_FPALU: | |
4639 | case TYPE_FPMULSGL: | |
4640 | case TYPE_FPMULDBL: | |
4641 | case TYPE_FPDIVSGL: | |
4642 | case TYPE_FPDIVDBL: | |
4643 | case TYPE_FPSQRTSGL: | |
4644 | case TYPE_FPSQRTDBL: | |
4645 | /* A fpload can't be issued until one cycle before a | |
01cc3b75 | 4646 | preceding arithmetic operation has finished if |
134b4858 | 4647 | the target of the fpload is the destination of the |
bea4bad2 | 4648 | arithmetic operation. |
4649 | ||
4650 | Exception: For PA7100LC, PA7200 and PA7300, the cost | |
4651 | is 3 cycles, unless they bundle together. We also | |
4652 | pay the penalty if the second insn is a fpload. */ | |
cde3e16c | 4653 | return insn_default_latency (dep_insn) - 1; |
8b49b3c7 | 4654 | |
134b4858 | 4655 | default: |
4656 | return 0; | |
4657 | } | |
4658 | } | |
4659 | } | |
43048d2c | 4660 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4661 | { |
4662 | rtx pat = PATTERN (insn); | |
4663 | rtx dep_pat = PATTERN (dep_insn); | |
4664 | if (GET_CODE (pat) == PARALLEL) | |
4665 | { | |
4666 | /* This happens for the fldXs,mb patterns. */ | |
4667 | pat = XVECEXP (pat, 0, 0); | |
4668 | } | |
4669 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4670 | /* If this happens, we have to extend this to schedule | |
4671 | optimally. Return 0 for now. */ | |
4672 | return 0; | |
4673 | ||
4674 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4675 | { | |
4676 | if (! recog_memoized (dep_insn)) | |
4677 | return 0; | |
4678 | switch (get_attr_type (dep_insn)) | |
4679 | { | |
4680 | case TYPE_FPDIVSGL: | |
4681 | case TYPE_FPDIVDBL: | |
4682 | case TYPE_FPSQRTSGL: | |
4683 | case TYPE_FPSQRTDBL: | |
4684 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4685 | preceding divide or sqrt operation has finished if |
134b4858 | 4686 | the target of the ALU flop is also the target of |
3398e91d | 4687 | the divide or sqrt operation. */ |
cde3e16c | 4688 | return insn_default_latency (dep_insn) - 2; |
134b4858 | 4689 | |
4690 | default: | |
4691 | return 0; | |
4692 | } | |
4693 | } | |
4694 | } | |
4695 | ||
4696 | /* For other output dependencies, the cost is 0. */ | |
4697 | return 0; | |
4698 | } | |
4699 | else | |
4700 | abort (); | |
8b49b3c7 | 4701 | } |
87ad11b0 | 4702 | |
747af5e7 | 4703 | /* Adjust scheduling priorities. We use this to try and keep addil |
4704 | and the next use of %r1 close together. */ | |
4705 | static int | |
5c1d8983 | 4706 | pa_adjust_priority (rtx insn, int priority) |
747af5e7 | 4707 | { |
4708 | rtx set = single_set (insn); | |
4709 | rtx src, dest; | |
4710 | if (set) | |
4711 | { | |
4712 | src = SET_SRC (set); | |
4713 | dest = SET_DEST (set); | |
4714 | if (GET_CODE (src) == LO_SUM | |
4715 | && symbolic_operand (XEXP (src, 1), VOIDmode) | |
4716 | && ! read_only_operand (XEXP (src, 1), VOIDmode)) | |
4717 | priority >>= 3; | |
4718 | ||
4719 | else if (GET_CODE (src) == MEM | |
4720 | && GET_CODE (XEXP (src, 0)) == LO_SUM | |
4721 | && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode) | |
4722 | && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode)) | |
4723 | priority >>= 1; | |
4724 | ||
4725 | else if (GET_CODE (dest) == MEM | |
4726 | && GET_CODE (XEXP (dest, 0)) == LO_SUM | |
4727 | && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode) | |
4728 | && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)) | |
4729 | priority >>= 3; | |
4730 | } | |
4731 | return priority; | |
4732 | } | |
4733 | ||
4734 | /* The 700 can only issue a single insn at a time. | |
4735 | The 7XXX processors can issue two insns at a time. | |
4736 | The 8000 can issue 4 insns at a time. */ | |
4737 | static int | |
5c1d8983 | 4738 | pa_issue_rate (void) |
747af5e7 | 4739 | { |
4740 | switch (pa_cpu) | |
4741 | { | |
4742 | case PROCESSOR_700: return 1; | |
4743 | case PROCESSOR_7100: return 2; | |
4744 | case PROCESSOR_7100LC: return 2; | |
4745 | case PROCESSOR_7200: return 2; | |
bea4bad2 | 4746 | case PROCESSOR_7300: return 2; |
747af5e7 | 4747 | case PROCESSOR_8000: return 4; |
4748 | ||
4749 | default: | |
4750 | abort (); | |
4751 | } | |
4752 | } | |
4753 | ||
4754 | ||
4755 | ||
58e17b0b | 4756 | /* Return any length adjustment needed by INSN which already has its length |
6d36483b | 4757 | computed as LENGTH. Return zero if no adjustment is necessary. |
58e17b0b | 4758 | |
5fbd5940 | 4759 | For the PA: function calls, millicode calls, and backwards short |
6d36483b | 4760 | conditional branches with unfilled delay slots need an adjustment by +1 |
5fbd5940 | 4761 | (to account for the NOP which will be inserted into the instruction stream). |
58e17b0b | 4762 | |
4763 | Also compute the length of an inline block move here as it is too | |
5fbd5940 | 4764 | complicated to express as a length attribute in pa.md. */ |
58e17b0b | 4765 | int |
5c1d8983 | 4766 | pa_adjust_insn_length (rtx insn, int length) |
58e17b0b | 4767 | { |
4768 | rtx pat = PATTERN (insn); | |
4769 | ||
faf3f8c1 | 4770 | /* Jumps inside switch tables which have unfilled delay slots need |
4771 | adjustment. */ | |
4772 | if (GET_CODE (insn) == JUMP_INSN | |
b932f66c | 4773 | && GET_CODE (pat) == PARALLEL |
4774 | && get_attr_type (insn) == TYPE_BTABLE_BRANCH) | |
3b1e673e | 4775 | return 4; |
58e17b0b | 4776 | /* Millicode insn with an unfilled delay slot. */ |
4777 | else if (GET_CODE (insn) == INSN | |
4778 | && GET_CODE (pat) != SEQUENCE | |
4779 | && GET_CODE (pat) != USE | |
4780 | && GET_CODE (pat) != CLOBBER | |
4781 | && get_attr_type (insn) == TYPE_MILLI) | |
5a1231ef | 4782 | return 4; |
58e17b0b | 4783 | /* Block move pattern. */ |
4784 | else if (GET_CODE (insn) == INSN | |
4785 | && GET_CODE (pat) == PARALLEL | |
f2ebcf32 | 4786 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET |
58e17b0b | 4787 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM |
4788 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM | |
4789 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode | |
4790 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode) | |
a7e1bb24 | 4791 | return compute_movstr_length (insn) - 4; |
4792 | /* Block clear pattern. */ | |
4793 | else if (GET_CODE (insn) == INSN | |
4794 | && GET_CODE (pat) == PARALLEL | |
4795 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET | |
4796 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM | |
4797 | && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx | |
4798 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode) | |
4799 | return compute_clrstr_length (insn) - 4; | |
58e17b0b | 4800 | /* Conditional branch with an unfilled delay slot. */ |
5fbd5940 | 4801 | else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn)) |
4802 | { | |
4803 | /* Adjust a short backwards conditional with an unfilled delay slot. */ | |
4804 | if (GET_CODE (pat) == SET | |
5a1231ef | 4805 | && length == 4 |
5fbd5940 | 4806 | && ! forward_branch_p (insn)) |
5a1231ef | 4807 | return 4; |
546a40bd | 4808 | else if (GET_CODE (pat) == PARALLEL |
4809 | && get_attr_type (insn) == TYPE_PARALLEL_BRANCH | |
4810 | && length == 4) | |
4811 | return 4; | |
5fbd5940 | 4812 | /* Adjust dbra insn with short backwards conditional branch with |
6d36483b | 4813 | unfilled delay slot -- only for case where counter is in a |
6dc3b0d9 | 4814 | general register register. */ |
5fbd5940 | 4815 | else if (GET_CODE (pat) == PARALLEL |
4816 | && GET_CODE (XVECEXP (pat, 0, 1)) == SET | |
4817 | && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG | |
6d36483b | 4818 | && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0)) |
5a1231ef | 4819 | && length == 4 |
5fbd5940 | 4820 | && ! forward_branch_p (insn)) |
5a1231ef | 4821 | return 4; |
5fbd5940 | 4822 | else |
4823 | return 0; | |
4824 | } | |
546a40bd | 4825 | return 0; |
58e17b0b | 4826 | } |
4827 | ||
87ad11b0 | 4828 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
4829 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
4830 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
4831 | ||
4832 | void | |
5c1d8983 | 4833 | print_operand (FILE *file, rtx x, int code) |
87ad11b0 | 4834 | { |
4835 | switch (code) | |
4836 | { | |
4837 | case '#': | |
4838 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
4839 | if (dbr_sequence_length () == 0) | |
4840 | fputs ("\n\tnop", file); | |
4841 | return; | |
4842 | case '*': | |
87fcb603 | 4843 | /* Output a nullification completer if there's nothing for the */ |
6d36483b | 4844 | /* delay slot or nullification is requested. */ |
87ad11b0 | 4845 | if (dbr_sequence_length () == 0 || |
4846 | (final_sequence && | |
4847 | INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))) | |
4848 | fputs (",n", file); | |
4849 | return; | |
4850 | case 'R': | |
4851 | /* Print out the second register name of a register pair. | |
4852 | I.e., R (6) => 7. */ | |
ea52c577 | 4853 | fputs (reg_names[REGNO (x) + 1], file); |
87ad11b0 | 4854 | return; |
4855 | case 'r': | |
6dc3b0d9 | 4856 | /* A register or zero. */ |
891b55b4 | 4857 | if (x == const0_rtx |
4858 | || (x == CONST0_RTX (DFmode)) | |
4859 | || (x == CONST0_RTX (SFmode))) | |
87ad11b0 | 4860 | { |
c6ae275c | 4861 | fputs ("%r0", file); |
4862 | return; | |
4863 | } | |
4864 | else | |
4865 | break; | |
4866 | case 'f': | |
6dc3b0d9 | 4867 | /* A register or zero (floating point). */ |
c6ae275c | 4868 | if (x == const0_rtx |
4869 | || (x == CONST0_RTX (DFmode)) | |
4870 | || (x == CONST0_RTX (SFmode))) | |
4871 | { | |
4872 | fputs ("%fr0", file); | |
87ad11b0 | 4873 | return; |
4874 | } | |
4875 | else | |
4876 | break; | |
2d14b1f0 | 4877 | case 'A': |
4878 | { | |
4879 | rtx xoperands[2]; | |
4880 | ||
4881 | xoperands[0] = XEXP (XEXP (x, 0), 0); | |
4882 | xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0); | |
4883 | output_global_address (file, xoperands[1], 0); | |
4884 | fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]); | |
4885 | return; | |
4886 | } | |
4887 | ||
c8975385 | 4888 | case 'C': /* Plain (C)ondition */ |
87ad11b0 | 4889 | case 'X': |
4890 | switch (GET_CODE (x)) | |
6d36483b | 4891 | { |
87ad11b0 | 4892 | case EQ: |
9c0ac0fd | 4893 | fputs ("=", file); break; |
87ad11b0 | 4894 | case NE: |
9c0ac0fd | 4895 | fputs ("<>", file); break; |
87ad11b0 | 4896 | case GT: |
9c0ac0fd | 4897 | fputs (">", file); break; |
87ad11b0 | 4898 | case GE: |
9c0ac0fd | 4899 | fputs (">=", file); break; |
87ad11b0 | 4900 | case GEU: |
9c0ac0fd | 4901 | fputs (">>=", file); break; |
87ad11b0 | 4902 | case GTU: |
9c0ac0fd | 4903 | fputs (">>", file); break; |
87ad11b0 | 4904 | case LT: |
9c0ac0fd | 4905 | fputs ("<", file); break; |
87ad11b0 | 4906 | case LE: |
9c0ac0fd | 4907 | fputs ("<=", file); break; |
87ad11b0 | 4908 | case LEU: |
9c0ac0fd | 4909 | fputs ("<<=", file); break; |
87ad11b0 | 4910 | case LTU: |
9c0ac0fd | 4911 | fputs ("<<", file); break; |
87ad11b0 | 4912 | default: |
87ad11b0 | 4913 | abort (); |
4914 | } | |
4915 | return; | |
c8975385 | 4916 | case 'N': /* Condition, (N)egated */ |
87ad11b0 | 4917 | switch (GET_CODE (x)) |
4918 | { | |
4919 | case EQ: | |
9c0ac0fd | 4920 | fputs ("<>", file); break; |
87ad11b0 | 4921 | case NE: |
9c0ac0fd | 4922 | fputs ("=", file); break; |
87ad11b0 | 4923 | case GT: |
9c0ac0fd | 4924 | fputs ("<=", file); break; |
87ad11b0 | 4925 | case GE: |
9c0ac0fd | 4926 | fputs ("<", file); break; |
87ad11b0 | 4927 | case GEU: |
9c0ac0fd | 4928 | fputs ("<<", file); break; |
87ad11b0 | 4929 | case GTU: |
9c0ac0fd | 4930 | fputs ("<<=", file); break; |
87ad11b0 | 4931 | case LT: |
9c0ac0fd | 4932 | fputs (">=", file); break; |
87ad11b0 | 4933 | case LE: |
9c0ac0fd | 4934 | fputs (">", file); break; |
87ad11b0 | 4935 | case LEU: |
9c0ac0fd | 4936 | fputs (">>", file); break; |
87ad11b0 | 4937 | case LTU: |
9c0ac0fd | 4938 | fputs (">>=", file); break; |
87ad11b0 | 4939 | default: |
87ad11b0 | 4940 | abort (); |
4941 | } | |
4942 | return; | |
ea52c577 | 4943 | /* For floating point comparisons. Note that the output |
4944 | predicates are the complement of the desired mode. */ | |
61230bc9 | 4945 | case 'Y': |
4946 | switch (GET_CODE (x)) | |
4947 | { | |
4948 | case EQ: | |
9c0ac0fd | 4949 | fputs ("!=", file); break; |
61230bc9 | 4950 | case NE: |
9c0ac0fd | 4951 | fputs ("=", file); break; |
61230bc9 | 4952 | case GT: |
32509e56 | 4953 | fputs ("!>", file); break; |
61230bc9 | 4954 | case GE: |
32509e56 | 4955 | fputs ("!>=", file); break; |
61230bc9 | 4956 | case LT: |
32509e56 | 4957 | fputs ("!<", file); break; |
61230bc9 | 4958 | case LE: |
32509e56 | 4959 | fputs ("!<=", file); break; |
4960 | case LTGT: | |
4961 | fputs ("!<>", file); break; | |
4962 | case UNLE: | |
85837adc | 4963 | fputs (">", file); break; |
32509e56 | 4964 | case UNLT: |
4965 | fputs (">=", file); break; | |
4966 | case UNGE: | |
4967 | fputs ("<", file); break; | |
4968 | case UNGT: | |
4969 | fputs ("<=", file); break; | |
4970 | case UNEQ: | |
4971 | fputs ("<>", file); break; | |
4972 | case UNORDERED: | |
4973 | fputs ("<=>", file); break; | |
4974 | case ORDERED: | |
4975 | fputs ("!<=>", file); break; | |
61230bc9 | 4976 | default: |
61230bc9 | 4977 | abort (); |
4978 | } | |
4979 | return; | |
c8975385 | 4980 | case 'S': /* Condition, operands are (S)wapped. */ |
4981 | switch (GET_CODE (x)) | |
4982 | { | |
4983 | case EQ: | |
9c0ac0fd | 4984 | fputs ("=", file); break; |
c8975385 | 4985 | case NE: |
9c0ac0fd | 4986 | fputs ("<>", file); break; |
c8975385 | 4987 | case GT: |
9c0ac0fd | 4988 | fputs ("<", file); break; |
c8975385 | 4989 | case GE: |
9c0ac0fd | 4990 | fputs ("<=", file); break; |
c8975385 | 4991 | case GEU: |
9c0ac0fd | 4992 | fputs ("<<=", file); break; |
c8975385 | 4993 | case GTU: |
9c0ac0fd | 4994 | fputs ("<<", file); break; |
c8975385 | 4995 | case LT: |
9c0ac0fd | 4996 | fputs (">", file); break; |
c8975385 | 4997 | case LE: |
9c0ac0fd | 4998 | fputs (">=", file); break; |
c8975385 | 4999 | case LEU: |
9c0ac0fd | 5000 | fputs (">>=", file); break; |
c8975385 | 5001 | case LTU: |
9c0ac0fd | 5002 | fputs (">>", file); break; |
c8975385 | 5003 | default: |
c8975385 | 5004 | abort (); |
6d36483b | 5005 | } |
c8975385 | 5006 | return; |
5007 | case 'B': /* Condition, (B)oth swapped and negate. */ | |
5008 | switch (GET_CODE (x)) | |
5009 | { | |
5010 | case EQ: | |
9c0ac0fd | 5011 | fputs ("<>", file); break; |
c8975385 | 5012 | case NE: |
9c0ac0fd | 5013 | fputs ("=", file); break; |
c8975385 | 5014 | case GT: |
9c0ac0fd | 5015 | fputs (">=", file); break; |
c8975385 | 5016 | case GE: |
9c0ac0fd | 5017 | fputs (">", file); break; |
c8975385 | 5018 | case GEU: |
9c0ac0fd | 5019 | fputs (">>", file); break; |
c8975385 | 5020 | case GTU: |
9c0ac0fd | 5021 | fputs (">>=", file); break; |
c8975385 | 5022 | case LT: |
9c0ac0fd | 5023 | fputs ("<=", file); break; |
c8975385 | 5024 | case LE: |
9c0ac0fd | 5025 | fputs ("<", file); break; |
c8975385 | 5026 | case LEU: |
9c0ac0fd | 5027 | fputs ("<<", file); break; |
c8975385 | 5028 | case LTU: |
9c0ac0fd | 5029 | fputs ("<<=", file); break; |
c8975385 | 5030 | default: |
c8975385 | 5031 | abort (); |
6d36483b | 5032 | } |
c8975385 | 5033 | return; |
5034 | case 'k': | |
5035 | if (GET_CODE (x) == CONST_INT) | |
5036 | { | |
96b529f2 | 5037 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x)); |
c8975385 | 5038 | return; |
5039 | } | |
ea52c577 | 5040 | abort (); |
5e3c5739 | 5041 | case 'Q': |
5042 | if (GET_CODE (x) == CONST_INT) | |
5043 | { | |
96b529f2 | 5044 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63)); |
5e3c5739 | 5045 | return; |
5046 | } | |
ea52c577 | 5047 | abort (); |
e5965947 | 5048 | case 'L': |
5049 | if (GET_CODE (x) == CONST_INT) | |
5050 | { | |
96b529f2 | 5051 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31)); |
e5965947 | 5052 | return; |
5053 | } | |
ea52c577 | 5054 | abort (); |
3a16146d | 5055 | case 'O': |
5056 | if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0) | |
5057 | { | |
5058 | fprintf (file, "%d", exact_log2 (INTVAL (x))); | |
5059 | return; | |
5060 | } | |
ea52c577 | 5061 | abort (); |
5e3c5739 | 5062 | case 'p': |
5063 | if (GET_CODE (x) == CONST_INT) | |
5064 | { | |
96b529f2 | 5065 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63)); |
5e3c5739 | 5066 | return; |
5067 | } | |
ea52c577 | 5068 | abort (); |
e5965947 | 5069 | case 'P': |
5070 | if (GET_CODE (x) == CONST_INT) | |
5071 | { | |
96b529f2 | 5072 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31)); |
e5965947 | 5073 | return; |
5074 | } | |
ea52c577 | 5075 | abort (); |
c8975385 | 5076 | case 'I': |
5077 | if (GET_CODE (x) == CONST_INT) | |
5078 | fputs ("i", file); | |
5079 | return; | |
87ad11b0 | 5080 | case 'M': |
27ef382d | 5081 | case 'F': |
87ad11b0 | 5082 | switch (GET_CODE (XEXP (x, 0))) |
5083 | { | |
5084 | case PRE_DEC: | |
5085 | case PRE_INC: | |
e4065f95 | 5086 | if (ASSEMBLER_DIALECT == 0) |
5087 | fputs ("s,mb", file); | |
5088 | else | |
5089 | fputs (",mb", file); | |
87ad11b0 | 5090 | break; |
5091 | case POST_DEC: | |
5092 | case POST_INC: | |
e4065f95 | 5093 | if (ASSEMBLER_DIALECT == 0) |
5094 | fputs ("s,ma", file); | |
5095 | else | |
5096 | fputs (",ma", file); | |
87ad11b0 | 5097 | break; |
27ef382d | 5098 | case PLUS: |
dbd3d89d | 5099 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5100 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5101 | { | |
5102 | if (ASSEMBLER_DIALECT == 0) | |
5103 | fputs ("x", file); | |
5104 | } | |
5105 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
5106 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) | |
e4065f95 | 5107 | { |
5108 | if (ASSEMBLER_DIALECT == 0) | |
5109 | fputs ("x,s", file); | |
5110 | else | |
5111 | fputs (",s", file); | |
5112 | } | |
5113 | else if (code == 'F' && ASSEMBLER_DIALECT == 0) | |
27ef382d | 5114 | fputs ("s", file); |
87ad11b0 | 5115 | break; |
5116 | default: | |
e4065f95 | 5117 | if (code == 'F' && ASSEMBLER_DIALECT == 0) |
27ef382d | 5118 | fputs ("s", file); |
87ad11b0 | 5119 | break; |
5120 | } | |
5121 | return; | |
5122 | case 'G': | |
f9333726 | 5123 | output_global_address (file, x, 0); |
5124 | return; | |
5125 | case 'H': | |
5126 | output_global_address (file, x, 1); | |
87ad11b0 | 5127 | return; |
5128 | case 0: /* Don't do anything special */ | |
5129 | break; | |
42faba01 | 5130 | case 'Z': |
5131 | { | |
5132 | unsigned op[3]; | |
fb22aedc | 5133 | compute_zdepwi_operands (INTVAL (x), op); |
42faba01 | 5134 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); |
5135 | return; | |
5136 | } | |
5e3c5739 | 5137 | case 'z': |
5138 | { | |
5139 | unsigned op[3]; | |
5140 | compute_zdepdi_operands (INTVAL (x), op); | |
5141 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); | |
5142 | return; | |
5143 | } | |
c9cc98e1 | 5144 | case 'c': |
5145 | /* We can get here from a .vtable_inherit due to our | |
5146 | CONSTANT_ADDRESS_P rejecting perfectly good constant | |
5147 | addresses. */ | |
5148 | break; | |
87ad11b0 | 5149 | default: |
5150 | abort (); | |
5151 | } | |
5152 | if (GET_CODE (x) == REG) | |
df0651dc | 5153 | { |
35661368 | 5154 | fputs (reg_names [REGNO (x)], file); |
5e3c5739 | 5155 | if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4) |
5156 | { | |
5157 | fputs ("R", file); | |
5158 | return; | |
5159 | } | |
5160 | if (FP_REG_P (x) | |
5161 | && GET_MODE_SIZE (GET_MODE (x)) <= 4 | |
5162 | && (REGNO (x) & 1) == 0) | |
35661368 | 5163 | fputs ("L", file); |
df0651dc | 5164 | } |
87ad11b0 | 5165 | else if (GET_CODE (x) == MEM) |
5166 | { | |
5167 | int size = GET_MODE_SIZE (GET_MODE (x)); | |
f7dff90d | 5168 | rtx base = NULL_RTX; |
87ad11b0 | 5169 | switch (GET_CODE (XEXP (x, 0))) |
5170 | { | |
5171 | case PRE_DEC: | |
5172 | case POST_DEC: | |
5e3c5739 | 5173 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 5174 | fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5175 | break; |
5176 | case PRE_INC: | |
5177 | case POST_INC: | |
5e3c5739 | 5178 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 5179 | fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5180 | break; |
dbd3d89d | 5181 | case PLUS: |
5182 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT) | |
34940871 | 5183 | fprintf (file, "%s(%s)", |
27ef382d | 5184 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))], |
5185 | reg_names [REGNO (XEXP (XEXP (x, 0), 1))]); | |
dbd3d89d | 5186 | else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) |
34940871 | 5187 | fprintf (file, "%s(%s)", |
27ef382d | 5188 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))], |
5189 | reg_names [REGNO (XEXP (XEXP (x, 0), 0))]); | |
dbd3d89d | 5190 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5191 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5192 | { | |
5193 | /* Because the REG_POINTER flag can get lost during reload, | |
5194 | GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the | |
5195 | index and base registers in the combined move patterns. */ | |
5196 | rtx base = XEXP (XEXP (x, 0), 1); | |
5197 | rtx index = XEXP (XEXP (x, 0), 0); | |
5198 | ||
5199 | fprintf (file, "%s(%s)", | |
5200 | reg_names [REGNO (index)], reg_names [REGNO (base)]); | |
5201 | } | |
27ef382d | 5202 | else |
5203 | output_address (XEXP (x, 0)); | |
87ad11b0 | 5204 | break; |
dbd3d89d | 5205 | default: |
5206 | output_address (XEXP (x, 0)); | |
5207 | break; | |
87ad11b0 | 5208 | } |
5209 | } | |
87ad11b0 | 5210 | else |
5211 | output_addr_const (file, x); | |
5212 | } | |
5213 | ||
6dc3b0d9 | 5214 | /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */ |
87ad11b0 | 5215 | |
5216 | void | |
5c1d8983 | 5217 | output_global_address (FILE *file, rtx x, int round_constant) |
87ad11b0 | 5218 | { |
2ee034bc | 5219 | |
5220 | /* Imagine (high (const (plus ...))). */ | |
5221 | if (GET_CODE (x) == HIGH) | |
5222 | x = XEXP (x, 0); | |
5223 | ||
611a88e1 | 5224 | if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode)) |
87ad11b0 | 5225 | assemble_name (file, XSTR (x, 0)); |
b4a7bf10 | 5226 | else if (GET_CODE (x) == SYMBOL_REF && !flag_pic) |
87ad11b0 | 5227 | { |
5228 | assemble_name (file, XSTR (x, 0)); | |
9c0ac0fd | 5229 | fputs ("-$global$", file); |
87ad11b0 | 5230 | } |
5231 | else if (GET_CODE (x) == CONST) | |
5232 | { | |
611a88e1 | 5233 | const char *sep = ""; |
87ad11b0 | 5234 | int offset = 0; /* assembler wants -$global$ at end */ |
33ae0dba | 5235 | rtx base = NULL_RTX; |
6d36483b | 5236 | |
87ad11b0 | 5237 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF) |
5238 | { | |
5239 | base = XEXP (XEXP (x, 0), 0); | |
5240 | output_addr_const (file, base); | |
5241 | } | |
5242 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT) | |
5243 | offset = INTVAL (XEXP (XEXP (x, 0), 0)); | |
5244 | else abort (); | |
5245 | ||
5246 | if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF) | |
5247 | { | |
5248 | base = XEXP (XEXP (x, 0), 1); | |
5249 | output_addr_const (file, base); | |
5250 | } | |
5251 | else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
ea52c577 | 5252 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); |
87ad11b0 | 5253 | else abort (); |
5254 | ||
f9333726 | 5255 | /* How bogus. The compiler is apparently responsible for |
5256 | rounding the constant if it uses an LR field selector. | |
5257 | ||
5258 | The linker and/or assembler seem a better place since | |
5259 | they have to do this kind of thing already. | |
5260 | ||
5261 | If we fail to do this, HP's optimizing linker may eliminate | |
5262 | an addil, but not update the ldw/stw/ldo instruction that | |
5263 | uses the result of the addil. */ | |
5264 | if (round_constant) | |
5265 | offset = ((offset + 0x1000) & ~0x1fff); | |
5266 | ||
87ad11b0 | 5267 | if (GET_CODE (XEXP (x, 0)) == PLUS) |
5268 | { | |
5269 | if (offset < 0) | |
5270 | { | |
5271 | offset = -offset; | |
5272 | sep = "-"; | |
5273 | } | |
5274 | else | |
5275 | sep = "+"; | |
5276 | } | |
5277 | else if (GET_CODE (XEXP (x, 0)) == MINUS | |
5278 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) | |
5279 | sep = "-"; | |
5280 | else abort (); | |
5281 | ||
611a88e1 | 5282 | if (!read_only_operand (base, VOIDmode) && !flag_pic) |
9c0ac0fd | 5283 | fputs ("-$global$", file); |
f9333726 | 5284 | if (offset) |
ea52c577 | 5285 | fprintf (file, "%s%d", sep, offset); |
87ad11b0 | 5286 | } |
5287 | else | |
5288 | output_addr_const (file, x); | |
5289 | } | |
5290 | ||
92c473b8 | 5291 | /* Output boilerplate text to appear at the beginning of the file. |
5292 | There are several possible versions. */ | |
5293 | #define aputs(x) fputs(x, asm_out_file) | |
5294 | static inline void | |
5c1d8983 | 5295 | pa_file_start_level (void) |
92c473b8 | 5296 | { |
5297 | if (TARGET_64BIT) | |
5298 | aputs ("\t.LEVEL 2.0w\n"); | |
5299 | else if (TARGET_PA_20) | |
5300 | aputs ("\t.LEVEL 2.0\n"); | |
5301 | else if (TARGET_PA_11) | |
5302 | aputs ("\t.LEVEL 1.1\n"); | |
5303 | else | |
5304 | aputs ("\t.LEVEL 1.0\n"); | |
5305 | } | |
5306 | ||
5307 | static inline void | |
5c1d8983 | 5308 | pa_file_start_space (int sortspace) |
92c473b8 | 5309 | { |
5310 | aputs ("\t.SPACE $PRIVATE$"); | |
5311 | if (sortspace) | |
5312 | aputs (",SORT=16"); | |
5313 | aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31" | |
5314 | "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82" | |
5315 | "\n\t.SPACE $TEXT$"); | |
5316 | if (sortspace) | |
5317 | aputs (",SORT=8"); | |
5318 | aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44" | |
5319 | "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n"); | |
5320 | } | |
5321 | ||
5322 | static inline void | |
5c1d8983 | 5323 | pa_file_start_file (int want_version) |
92c473b8 | 5324 | { |
5325 | if (write_symbols != NO_DEBUG) | |
5326 | { | |
5327 | output_file_directive (asm_out_file, main_input_filename); | |
5328 | if (want_version) | |
5329 | aputs ("\t.version\t\"01.01\"\n"); | |
5330 | } | |
5331 | } | |
5332 | ||
5333 | static inline void | |
5c1d8983 | 5334 | pa_file_start_mcount (const char *aswhat) |
92c473b8 | 5335 | { |
5336 | if (profile_flag) | |
5337 | fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat); | |
5338 | } | |
5339 | ||
5340 | static void | |
5c1d8983 | 5341 | pa_elf_file_start (void) |
92c473b8 | 5342 | { |
5343 | pa_file_start_level (); | |
5344 | pa_file_start_mcount ("ENTRY"); | |
5345 | pa_file_start_file (0); | |
5346 | } | |
5347 | ||
5348 | static void | |
5c1d8983 | 5349 | pa_som_file_start (void) |
92c473b8 | 5350 | { |
5351 | pa_file_start_level (); | |
5352 | pa_file_start_space (0); | |
5353 | aputs ("\t.IMPORT $global$,DATA\n" | |
5354 | "\t.IMPORT $$dyncall,MILLICODE\n"); | |
5355 | pa_file_start_mcount ("CODE"); | |
5356 | pa_file_start_file (0); | |
5357 | } | |
5358 | ||
5359 | static void | |
5c1d8983 | 5360 | pa_linux_file_start (void) |
92c473b8 | 5361 | { |
5362 | pa_file_start_file (1); | |
5363 | pa_file_start_level (); | |
5364 | pa_file_start_mcount ("CODE"); | |
5365 | } | |
5366 | ||
5367 | static void | |
5c1d8983 | 5368 | pa_hpux64_gas_file_start (void) |
92c473b8 | 5369 | { |
5370 | pa_file_start_level (); | |
5371 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
5372 | if (profile_flag) | |
5373 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function"); | |
5374 | #endif | |
5375 | pa_file_start_file (1); | |
5376 | } | |
5377 | ||
5378 | static void | |
5c1d8983 | 5379 | pa_hpux64_hpas_file_start (void) |
92c473b8 | 5380 | { |
5381 | pa_file_start_level (); | |
5382 | pa_file_start_space (1); | |
5383 | pa_file_start_mcount ("CODE"); | |
5384 | pa_file_start_file (0); | |
5385 | } | |
5386 | #undef aputs | |
5387 | ||
ece88821 | 5388 | static struct deferred_plabel * |
5c1d8983 | 5389 | get_plabel (const char *fname) |
ece88821 | 5390 | { |
5391 | size_t i; | |
5392 | ||
5393 | /* See if we have already put this function on the list of deferred | |
5394 | plabels. This list is generally small, so a liner search is not | |
5395 | too ugly. If it proves too slow replace it with something faster. */ | |
5396 | for (i = 0; i < n_deferred_plabels; i++) | |
5397 | if (strcmp (fname, deferred_plabels[i].name) == 0) | |
5398 | break; | |
5399 | ||
5400 | /* If the deferred plabel list is empty, or this entry was not found | |
5401 | on the list, create a new entry on the list. */ | |
5402 | if (deferred_plabels == NULL || i == n_deferred_plabels) | |
5403 | { | |
5404 | const char *real_name; | |
5405 | ||
5406 | if (deferred_plabels == 0) | |
5407 | deferred_plabels = (struct deferred_plabel *) | |
5408 | ggc_alloc (sizeof (struct deferred_plabel)); | |
5409 | else | |
5410 | deferred_plabels = (struct deferred_plabel *) | |
5411 | ggc_realloc (deferred_plabels, | |
5412 | ((n_deferred_plabels + 1) | |
5413 | * sizeof (struct deferred_plabel))); | |
5414 | ||
5415 | i = n_deferred_plabels++; | |
5416 | deferred_plabels[i].internal_label = gen_label_rtx (); | |
5417 | deferred_plabels[i].name = ggc_strdup (fname); | |
5418 | ||
5419 | /* Gross. We have just implicitly taken the address of this function, | |
5420 | mark it as such. */ | |
5421 | real_name = (*targetm.strip_name_encoding) (fname); | |
5422 | TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1; | |
5423 | } | |
5424 | ||
5425 | return &deferred_plabels[i]; | |
5426 | } | |
5427 | ||
f6940372 | 5428 | static void |
5c1d8983 | 5429 | output_deferred_plabels (void) |
5cc6b2bc | 5430 | { |
e11bd7e5 | 5431 | size_t i; |
5cc6b2bc | 5432 | /* If we have deferred plabels, then we need to switch into the data |
5433 | section and align it to a 4 byte boundary before we output the | |
5434 | deferred plabels. */ | |
5435 | if (n_deferred_plabels) | |
5436 | { | |
5437 | data_section (); | |
f6940372 | 5438 | ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2); |
5cc6b2bc | 5439 | } |
5440 | ||
5441 | /* Now output the deferred plabels. */ | |
5442 | for (i = 0; i < n_deferred_plabels; i++) | |
5443 | { | |
f6940372 | 5444 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
5445 | CODE_LABEL_NUMBER (deferred_plabels[i].internal_label)); | |
09d688ff | 5446 | assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name), |
b70ea764 | 5447 | TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1); |
5cc6b2bc | 5448 | } |
5449 | } | |
5450 | ||
f2f543a3 | 5451 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
5452 | /* Initialize optabs to point to HPUX long double emulation routines. */ | |
5453 | static void | |
5454 | pa_hpux_init_libfuncs (void) | |
5455 | { | |
5456 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
5457 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
5458 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
5459 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
5460 | set_optab_libfunc (smin_optab, TFmode, "_U_Qmin"); | |
5461 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
5462 | set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt"); | |
5463 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
5464 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
5465 | ||
c88a6ebd | 5466 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); |
5467 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
5468 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
5469 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
5470 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
5471 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
f2f543a3 | 5472 | |
a7cc195f | 5473 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); |
5474 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
5475 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
5476 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
5477 | ||
5478 | set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT | |
5479 | ? "__U_Qfcnvfxt_quad_to_sgl" | |
5480 | : "_U_Qfcnvfxt_quad_to_sgl"); | |
5481 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl"); | |
5482 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl"); | |
5483 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl"); | |
5484 | ||
5485 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad"); | |
5486 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad"); | |
f2f543a3 | 5487 | } |
5488 | #endif | |
5489 | ||
87ad11b0 | 5490 | /* HP's millicode routines mean something special to the assembler. |
5491 | Keep track of which ones we have used. */ | |
5492 | ||
c2271c34 | 5493 | enum millicodes { remI, remU, divI, divU, mulI, end1000 }; |
5c1d8983 | 5494 | static void import_milli (enum millicodes); |
ea52c577 | 5495 | static char imported[(int) end1000]; |
c2271c34 | 5496 | static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"}; |
e99c3a1d | 5497 | static const char import_string[] = ".IMPORT $$....,MILLICODE"; |
87ad11b0 | 5498 | #define MILLI_START 10 |
5499 | ||
57ed30e5 | 5500 | static void |
5c1d8983 | 5501 | import_milli (enum millicodes code) |
87ad11b0 | 5502 | { |
5503 | char str[sizeof (import_string)]; | |
6d36483b | 5504 | |
ea52c577 | 5505 | if (!imported[(int) code]) |
87ad11b0 | 5506 | { |
ea52c577 | 5507 | imported[(int) code] = 1; |
87ad11b0 | 5508 | strcpy (str, import_string); |
ea52c577 | 5509 | strncpy (str + MILLI_START, milli_names[(int) code], 4); |
87ad11b0 | 5510 | output_asm_insn (str, 0); |
5511 | } | |
5512 | } | |
5513 | ||
6d36483b | 5514 | /* The register constraints have put the operands and return value in |
6dc3b0d9 | 5515 | the proper registers. */ |
87ad11b0 | 5516 | |
611a88e1 | 5517 | const char * |
5c1d8983 | 5518 | output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn) |
87ad11b0 | 5519 | { |
d178f670 | 5520 | import_milli (mulI); |
440c23df | 5521 | return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI")); |
87ad11b0 | 5522 | } |
5523 | ||
6dc3b0d9 | 5524 | /* Emit the rtl for doing a division by a constant. */ |
87ad11b0 | 5525 | |
d178f670 | 5526 | /* Do magic division millicodes exist for this value? */ |
e99c3a1d | 5527 | static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, |
5528 | 1, 1}; | |
87ad11b0 | 5529 | |
6d36483b | 5530 | /* We'll use an array to keep track of the magic millicodes and |
87ad11b0 | 5531 | whether or not we've used them already. [n][0] is signed, [n][1] is |
6dc3b0d9 | 5532 | unsigned. */ |
87ad11b0 | 5533 | |
87ad11b0 | 5534 | static int div_milli[16][2]; |
5535 | ||
5536 | int | |
5c1d8983 | 5537 | div_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 5538 | { |
5539 | return (mode == SImode | |
5540 | && ((GET_CODE (op) == REG && REGNO (op) == 25) | |
5541 | || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0 | |
5542 | && INTVAL (op) < 16 && magic_milli[INTVAL (op)]))); | |
5543 | } | |
5544 | ||
5545 | int | |
5c1d8983 | 5546 | emit_hpdiv_const (rtx *operands, int unsignedp) |
87ad11b0 | 5547 | { |
5548 | if (GET_CODE (operands[2]) == CONST_INT | |
5549 | && INTVAL (operands[2]) > 0 | |
5550 | && INTVAL (operands[2]) < 16 | |
5551 | && magic_milli[INTVAL (operands[2])]) | |
5552 | { | |
2013ddf6 | 5553 | rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31); |
5554 | ||
ad851752 | 5555 | emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]); |
87ad11b0 | 5556 | emit |
75b1a41a | 5557 | (gen_rtx_PARALLEL |
5558 | (VOIDmode, | |
c2078db8 | 5559 | gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29), |
ad851752 | 5560 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, |
5561 | SImode, | |
5562 | gen_rtx_REG (SImode, 26), | |
5563 | operands[2])), | |
c2078db8 | 5564 | gen_rtx_CLOBBER (VOIDmode, operands[4]), |
ad851752 | 5565 | gen_rtx_CLOBBER (VOIDmode, operands[3]), |
5566 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)), | |
5567 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)), | |
2013ddf6 | 5568 | gen_rtx_CLOBBER (VOIDmode, ret)))); |
ad851752 | 5569 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 29)); |
87ad11b0 | 5570 | return 1; |
5571 | } | |
5572 | return 0; | |
5573 | } | |
5574 | ||
611a88e1 | 5575 | const char * |
5c1d8983 | 5576 | output_div_insn (rtx *operands, int unsignedp, rtx insn) |
87ad11b0 | 5577 | { |
5578 | int divisor; | |
6d36483b | 5579 | |
5580 | /* If the divisor is a constant, try to use one of the special | |
87ad11b0 | 5581 | opcodes .*/ |
5582 | if (GET_CODE (operands[0]) == CONST_INT) | |
5583 | { | |
d6686e21 | 5584 | static char buf[100]; |
87ad11b0 | 5585 | divisor = INTVAL (operands[0]); |
5586 | if (!div_milli[divisor][unsignedp]) | |
5587 | { | |
d6686e21 | 5588 | div_milli[divisor][unsignedp] = 1; |
87ad11b0 | 5589 | if (unsignedp) |
5590 | output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands); | |
5591 | else | |
5592 | output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands); | |
87ad11b0 | 5593 | } |
5594 | if (unsignedp) | |
d6686e21 | 5595 | { |
4840a03a | 5596 | sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC, |
5597 | INTVAL (operands[0])); | |
c7a4e712 | 5598 | return output_millicode_call (insn, |
ad851752 | 5599 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5600 | } |
5601 | else | |
5602 | { | |
4840a03a | 5603 | sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC, |
5604 | INTVAL (operands[0])); | |
c7a4e712 | 5605 | return output_millicode_call (insn, |
ad851752 | 5606 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5607 | } |
87ad11b0 | 5608 | } |
6dc3b0d9 | 5609 | /* Divisor isn't a special constant. */ |
87ad11b0 | 5610 | else |
5611 | { | |
5612 | if (unsignedp) | |
5613 | { | |
5614 | import_milli (divU); | |
c7a4e712 | 5615 | return output_millicode_call (insn, |
ad851752 | 5616 | gen_rtx_SYMBOL_REF (SImode, "$$divU")); |
87ad11b0 | 5617 | } |
5618 | else | |
5619 | { | |
5620 | import_milli (divI); | |
c7a4e712 | 5621 | return output_millicode_call (insn, |
ad851752 | 5622 | gen_rtx_SYMBOL_REF (SImode, "$$divI")); |
87ad11b0 | 5623 | } |
5624 | } | |
5625 | } | |
5626 | ||
6dc3b0d9 | 5627 | /* Output a $$rem millicode to do mod. */ |
87ad11b0 | 5628 | |
611a88e1 | 5629 | const char * |
5c1d8983 | 5630 | output_mod_insn (int unsignedp, rtx insn) |
87ad11b0 | 5631 | { |
5632 | if (unsignedp) | |
5633 | { | |
5634 | import_milli (remU); | |
c7a4e712 | 5635 | return output_millicode_call (insn, |
ad851752 | 5636 | gen_rtx_SYMBOL_REF (SImode, "$$remU")); |
87ad11b0 | 5637 | } |
5638 | else | |
5639 | { | |
5640 | import_milli (remI); | |
c7a4e712 | 5641 | return output_millicode_call (insn, |
ad851752 | 5642 | gen_rtx_SYMBOL_REF (SImode, "$$remI")); |
87ad11b0 | 5643 | } |
5644 | } | |
5645 | ||
5646 | void | |
5c1d8983 | 5647 | output_arg_descriptor (rtx call_insn) |
87ad11b0 | 5648 | { |
611a88e1 | 5649 | const char *arg_regs[4]; |
87ad11b0 | 5650 | enum machine_mode arg_mode; |
df0651dc | 5651 | rtx link; |
87ad11b0 | 5652 | int i, output_flag = 0; |
5653 | int regno; | |
6d36483b | 5654 | |
5e3c5739 | 5655 | /* We neither need nor want argument location descriptors for the |
5d0619cc | 5656 | 64bit runtime environment or the ELF32 environment. */ |
5657 | if (TARGET_64BIT || TARGET_ELF32) | |
5e3c5739 | 5658 | return; |
5659 | ||
87ad11b0 | 5660 | for (i = 0; i < 4; i++) |
5661 | arg_regs[i] = 0; | |
5662 | ||
738176ab | 5663 | /* Specify explicitly that no argument relocations should take place |
5664 | if using the portable runtime calling conventions. */ | |
5665 | if (TARGET_PORTABLE_RUNTIME) | |
5666 | { | |
9c0ac0fd | 5667 | fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n", |
5668 | asm_out_file); | |
738176ab | 5669 | return; |
5670 | } | |
5671 | ||
df0651dc | 5672 | if (GET_CODE (call_insn) != CALL_INSN) |
5673 | abort (); | |
5674 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1)) | |
87ad11b0 | 5675 | { |
df0651dc | 5676 | rtx use = XEXP (link, 0); |
c12afafd | 5677 | |
df0651dc | 5678 | if (! (GET_CODE (use) == USE |
5679 | && GET_CODE (XEXP (use, 0)) == REG | |
5680 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
c12afafd | 5681 | continue; |
5682 | ||
df0651dc | 5683 | arg_mode = GET_MODE (XEXP (use, 0)); |
5684 | regno = REGNO (XEXP (use, 0)); | |
87ad11b0 | 5685 | if (regno >= 23 && regno <= 26) |
372ef038 | 5686 | { |
5687 | arg_regs[26 - regno] = "GR"; | |
5688 | if (arg_mode == DImode) | |
5689 | arg_regs[25 - regno] = "GR"; | |
5690 | } | |
df0651dc | 5691 | else if (regno >= 32 && regno <= 39) |
87ad11b0 | 5692 | { |
5693 | if (arg_mode == SFmode) | |
df0651dc | 5694 | arg_regs[(regno - 32) / 2] = "FR"; |
e6ba640e | 5695 | else |
87ad11b0 | 5696 | { |
eeec72c0 | 5697 | #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED |
df0651dc | 5698 | arg_regs[(regno - 34) / 2] = "FR"; |
5699 | arg_regs[(regno - 34) / 2 + 1] = "FU"; | |
87ad11b0 | 5700 | #else |
df0651dc | 5701 | arg_regs[(regno - 34) / 2] = "FU"; |
5702 | arg_regs[(regno - 34) / 2 + 1] = "FR"; | |
87ad11b0 | 5703 | #endif |
5704 | } | |
87ad11b0 | 5705 | } |
5706 | } | |
5707 | fputs ("\t.CALL ", asm_out_file); | |
5708 | for (i = 0; i < 4; i++) | |
5709 | { | |
5710 | if (arg_regs[i]) | |
5711 | { | |
5712 | if (output_flag++) | |
5713 | fputc (',', asm_out_file); | |
5714 | fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]); | |
5715 | } | |
5716 | } | |
5717 | fputc ('\n', asm_out_file); | |
5718 | } | |
5719 | \f | |
9c0ac0fd | 5720 | /* Return the class of any secondary reload register that is needed to |
5721 | move IN into a register in class CLASS using mode MODE. | |
5722 | ||
5723 | Profiling has showed this routine and its descendants account for | |
5724 | a significant amount of compile time (~7%). So it has been | |
5725 | optimized to reduce redundant computations and eliminate useless | |
5726 | function calls. | |
5727 | ||
5728 | It might be worthwhile to try and make this a leaf function too. */ | |
87ad11b0 | 5729 | |
5730 | enum reg_class | |
5c1d8983 | 5731 | secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in) |
87ad11b0 | 5732 | { |
9c0ac0fd | 5733 | int regno, is_symbolic; |
87ad11b0 | 5734 | |
b4a7bf10 | 5735 | /* Trying to load a constant into a FP register during PIC code |
5736 | generation will require %r1 as a scratch register. */ | |
fc44315f | 5737 | if (flag_pic |
b4a7bf10 | 5738 | && GET_MODE_CLASS (mode) == MODE_INT |
5739 | && FP_REG_CLASS_P (class) | |
5740 | && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE)) | |
5741 | return R1_REGS; | |
5742 | ||
9c0ac0fd | 5743 | /* Profiling showed the PA port spends about 1.3% of its compilation |
5744 | time in true_regnum from calls inside secondary_reload_class. */ | |
5745 | ||
5746 | if (GET_CODE (in) == REG) | |
5747 | { | |
5748 | regno = REGNO (in); | |
5749 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5750 | regno = true_regnum (in); | |
5751 | } | |
5752 | else if (GET_CODE (in) == SUBREG) | |
5753 | regno = true_regnum (in); | |
9c0ac0fd | 5754 | else |
5755 | regno = -1; | |
5756 | ||
76a0ced5 | 5757 | /* If we have something like (mem (mem (...)), we can safely assume the |
5758 | inner MEM will end up in a general register after reloading, so there's | |
5759 | no need for a secondary reload. */ | |
5760 | if (GET_CODE (in) == MEM | |
5761 | && GET_CODE (XEXP (in, 0)) == MEM) | |
5762 | return NO_REGS; | |
5763 | ||
5764 | /* Handle out of range displacement for integer mode loads/stores of | |
5765 | FP registers. */ | |
d2498717 | 5766 | if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1) |
6d36483b | 5767 | && GET_MODE_CLASS (mode) == MODE_INT |
5768 | && FP_REG_CLASS_P (class)) | |
d6f01525 | 5769 | || (class == SHIFT_REGS && (regno <= 0 || regno >= 32))) |
9c6d4825 | 5770 | return GENERAL_REGS; |
d2c1d63d | 5771 | |
7c4b32f3 | 5772 | /* A SAR<->FP register copy requires a secondary register (GPR) as |
5773 | well as secondary memory. */ | |
5774 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5775 | && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class)) | |
5776 | || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno))))) | |
5777 | return GENERAL_REGS; | |
5778 | ||
2ee034bc | 5779 | if (GET_CODE (in) == HIGH) |
5780 | in = XEXP (in, 0); | |
5781 | ||
9c0ac0fd | 5782 | /* Profiling has showed GCC spends about 2.6% of its compilation |
5783 | time in symbolic_operand from calls inside secondary_reload_class. | |
5784 | ||
5785 | We use an inline copy and only compute its return value once to avoid | |
5786 | useless work. */ | |
5787 | switch (GET_CODE (in)) | |
5788 | { | |
5789 | rtx tmp; | |
5790 | ||
5791 | case SYMBOL_REF: | |
5792 | case LABEL_REF: | |
5793 | is_symbolic = 1; | |
5794 | break; | |
5795 | case CONST: | |
5796 | tmp = XEXP (in, 0); | |
5797 | is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF | |
5798 | || GET_CODE (XEXP (tmp, 0)) == LABEL_REF) | |
5799 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT); | |
5800 | break; | |
76a0ced5 | 5801 | |
9c0ac0fd | 5802 | default: |
5803 | is_symbolic = 0; | |
5804 | break; | |
5805 | } | |
9840d99d | 5806 | |
b4a7bf10 | 5807 | if (!flag_pic |
9c0ac0fd | 5808 | && is_symbolic |
611a88e1 | 5809 | && read_only_operand (in, VOIDmode)) |
b4a7bf10 | 5810 | return NO_REGS; |
5811 | ||
9c0ac0fd | 5812 | if (class != R1_REGS && is_symbolic) |
2ee034bc | 5813 | return R1_REGS; |
5814 | ||
d2c1d63d | 5815 | return NO_REGS; |
87ad11b0 | 5816 | } |
5817 | ||
5818 | enum direction | |
5c1d8983 | 5819 | function_arg_padding (enum machine_mode mode, tree type) |
87ad11b0 | 5820 | { |
ac965869 | 5821 | if (mode == BLKmode |
5822 | || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type))) | |
5823 | { | |
5824 | /* Return none if justification is not required. */ | |
5825 | if (type | |
5826 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
5827 | && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0) | |
5828 | return none; | |
5829 | ||
5830 | /* The directions set here are ignored when a BLKmode argument larger | |
5831 | than a word is placed in a register. Different code is used for | |
5832 | the stack and registers. This makes it difficult to have a | |
5833 | consistent data representation for both the stack and registers. | |
5834 | For both runtimes, the justification and padding for arguments on | |
5835 | the stack and in registers should be identical. */ | |
5836 | if (TARGET_64BIT) | |
5837 | /* The 64-bit runtime specifies left justification for aggregates. */ | |
5838 | return upward; | |
87ad11b0 | 5839 | else |
ac965869 | 5840 | /* The 32-bit runtime architecture specifies right justification. |
5841 | When the argument is passed on the stack, the argument is padded | |
5842 | with garbage on the left. The HP compiler pads with zeros. */ | |
5843 | return downward; | |
87ad11b0 | 5844 | } |
ac965869 | 5845 | |
5846 | if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
87ad11b0 | 5847 | return downward; |
87ad11b0 | 5848 | else |
5849 | return none; | |
5850 | } | |
5851 | ||
87ad11b0 | 5852 | \f |
55f54832 | 5853 | /* Do what is necessary for `va_start'. We look at the current function |
5854 | to determine if stdargs or varargs is used and fill in an initial | |
5855 | va_list. A pointer to this constructor is returned. */ | |
87ad11b0 | 5856 | |
b8debbe8 | 5857 | static rtx |
5c1d8983 | 5858 | hppa_builtin_saveregs (void) |
87ad11b0 | 5859 | { |
01251cbc | 5860 | rtx offset, dest; |
87ad11b0 | 5861 | tree fntype = TREE_TYPE (current_function_decl); |
5862 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
5863 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
5864 | != void_type_node))) | |
5865 | ? UNITS_PER_WORD : 0); | |
5866 | ||
5867 | if (argadj) | |
5868 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
5869 | else | |
5870 | offset = current_function_arg_offset_rtx; | |
9c6d4825 | 5871 | |
5e3c5739 | 5872 | if (TARGET_64BIT) |
5873 | { | |
5874 | int i, off; | |
9840d99d | 5875 | |
5e3c5739 | 5876 | /* Adjust for varargs/stdarg differences. */ |
5877 | if (argadj) | |
5878 | offset = plus_constant (current_function_arg_offset_rtx, -argadj); | |
5879 | else | |
5880 | offset = current_function_arg_offset_rtx; | |
5881 | ||
5882 | /* We need to save %r26 .. %r19 inclusive starting at offset -64 | |
5883 | from the incoming arg pointer and growing to larger addresses. */ | |
5884 | for (i = 26, off = -64; i >= 19; i--, off += 8) | |
5885 | emit_move_insn (gen_rtx_MEM (word_mode, | |
5886 | plus_constant (arg_pointer_rtx, off)), | |
5887 | gen_rtx_REG (word_mode, i)); | |
5888 | ||
5889 | /* The incoming args pointer points just beyond the flushback area; | |
8ef587dc | 5890 | normally this is not a serious concern. However, when we are doing |
5e3c5739 | 5891 | varargs/stdargs we want to make the arg pointer point to the start |
5892 | of the incoming argument area. */ | |
5893 | emit_move_insn (virtual_incoming_args_rtx, | |
5894 | plus_constant (arg_pointer_rtx, -64)); | |
5895 | ||
5896 | /* Now return a pointer to the first anonymous argument. */ | |
5897 | return copy_to_reg (expand_binop (Pmode, add_optab, | |
5898 | virtual_incoming_args_rtx, | |
5899 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
5900 | } | |
5901 | ||
6dc3b0d9 | 5902 | /* Store general registers on the stack. */ |
ad851752 | 5903 | dest = gen_rtx_MEM (BLKmode, |
5904 | plus_constant (current_function_internal_arg_pointer, | |
5905 | -16)); | |
ab6ab77e | 5906 | set_mem_alias_set (dest, get_varargs_alias_set ()); |
2a631e19 | 5907 | set_mem_align (dest, BITS_PER_WORD); |
530178a9 | 5908 | move_block_from_reg (23, dest, 4); |
01251cbc | 5909 | |
76a0ced5 | 5910 | /* move_block_from_reg will emit code to store the argument registers |
5911 | individually as scalar stores. | |
5912 | ||
5913 | However, other insns may later load from the same addresses for | |
ad87de1e | 5914 | a structure load (passing a struct to a varargs routine). |
76a0ced5 | 5915 | |
5916 | The alias code assumes that such aliasing can never happen, so we | |
5917 | have to keep memory referencing insns from moving up beyond the | |
5918 | last argument register store. So we emit a blockage insn here. */ | |
5919 | emit_insn (gen_blockage ()); | |
5920 | ||
9c6d4825 | 5921 | return copy_to_reg (expand_binop (Pmode, add_optab, |
5922 | current_function_internal_arg_pointer, | |
5923 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
87ad11b0 | 5924 | } |
d6f01525 | 5925 | |
72899a61 | 5926 | void |
5c1d8983 | 5927 | hppa_va_start (tree valist, rtx nextarg) |
72899a61 | 5928 | { |
5929 | nextarg = expand_builtin_saveregs (); | |
7df226a2 | 5930 | std_expand_builtin_va_start (valist, nextarg); |
72899a61 | 5931 | } |
5932 | ||
5933 | rtx | |
5c1d8983 | 5934 | hppa_va_arg (tree valist, tree type) |
72899a61 | 5935 | { |
ac965869 | 5936 | HOST_WIDE_INT size = int_size_in_bytes (type); |
5937 | HOST_WIDE_INT ofs; | |
72899a61 | 5938 | tree t, ptr, pptr; |
5939 | ||
5e3c5739 | 5940 | if (TARGET_64BIT) |
5941 | { | |
ac965869 | 5942 | /* Every argument in PA64 is supposed to be passed by value |
5943 | (including large structs). However, as a GCC extension, we | |
5944 | pass zero and variable sized arguments by reference. Empty | |
5945 | structures are a GCC extension not supported by the HP | |
5946 | compilers. Thus, passing them by reference isn't likely | |
5947 | to conflict with the ABI. For variable sized arguments, | |
5948 | GCC doesn't have the infrastructure to allocate these to | |
5949 | registers. */ | |
5950 | ||
5951 | /* Arguments with a size greater than 8 must be aligned 0 MOD 16. */ | |
5e3c5739 | 5952 | |
5e3c5739 | 5953 | if (size > UNITS_PER_WORD) |
5954 | { | |
5955 | t = build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
5956 | build_int_2 (2 * UNITS_PER_WORD - 1, 0)); | |
9840d99d | 5957 | t = build (BIT_AND_EXPR, TREE_TYPE (t), t, |
5e3c5739 | 5958 | build_int_2 (-2 * UNITS_PER_WORD, -1)); |
5959 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t); | |
5960 | TREE_SIDE_EFFECTS (t) = 1; | |
ac965869 | 5961 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5e3c5739 | 5962 | } |
72899a61 | 5963 | |
ac965869 | 5964 | if (size > 0) |
5965 | return std_expand_builtin_va_arg (valist, type); | |
5966 | else | |
5967 | { | |
5968 | ptr = build_pointer_type (type); | |
72899a61 | 5969 | |
ac965869 | 5970 | /* Args grow upward. */ |
5971 | t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, | |
5972 | build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0)); | |
5973 | TREE_SIDE_EFFECTS (t) = 1; | |
72899a61 | 5974 | |
ac965869 | 5975 | pptr = build_pointer_type (ptr); |
5976 | t = build1 (NOP_EXPR, pptr, t); | |
5977 | TREE_SIDE_EFFECTS (t) = 1; | |
72899a61 | 5978 | |
ac965869 | 5979 | t = build1 (INDIRECT_REF, ptr, t); |
5980 | TREE_SIDE_EFFECTS (t) = 1; | |
5981 | } | |
72899a61 | 5982 | } |
ac965869 | 5983 | else /* !TARGET_64BIT */ |
72899a61 | 5984 | { |
ac965869 | 5985 | ptr = build_pointer_type (type); |
72899a61 | 5986 | |
ac965869 | 5987 | /* "Large" and variable sized types are passed by reference. */ |
5988 | if (size > 8 || size <= 0) | |
5989 | { | |
5990 | /* Args grow downward. */ | |
5991 | t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist, | |
5992 | build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0)); | |
5993 | TREE_SIDE_EFFECTS (t) = 1; | |
72899a61 | 5994 | |
ac965869 | 5995 | pptr = build_pointer_type (ptr); |
5996 | t = build1 (NOP_EXPR, pptr, t); | |
5997 | TREE_SIDE_EFFECTS (t) = 1; | |
9840d99d | 5998 | |
ac965869 | 5999 | t = build1 (INDIRECT_REF, ptr, t); |
72899a61 | 6000 | TREE_SIDE_EFFECTS (t) = 1; |
6001 | } | |
ac965869 | 6002 | else |
6003 | { | |
6004 | t = build (PLUS_EXPR, TREE_TYPE (valist), valist, | |
6005 | build_int_2 (-size, -1)); | |
6006 | ||
6007 | /* Copied from va-pa.h, but we probably don't need to align to | |
6008 | word size, since we generate and preserve that invariant. */ | |
6009 | t = build (BIT_AND_EXPR, TREE_TYPE (valist), t, | |
6010 | build_int_2 ((size > 4 ? -8 : -4), -1)); | |
6011 | ||
6012 | t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t); | |
6013 | TREE_SIDE_EFFECTS (t) = 1; | |
6014 | ||
6015 | ofs = (8 - size) % 4; | |
6016 | if (ofs) | |
6017 | { | |
6018 | t = build (PLUS_EXPR, TREE_TYPE (valist), t, | |
6019 | build_int_2 (ofs, 0)); | |
6020 | TREE_SIDE_EFFECTS (t) = 1; | |
6021 | } | |
72899a61 | 6022 | |
ac965869 | 6023 | t = build1 (NOP_EXPR, ptr, t); |
6024 | TREE_SIDE_EFFECTS (t) = 1; | |
6025 | } | |
72899a61 | 6026 | } |
6027 | ||
6028 | /* Calculate! */ | |
ac965869 | 6029 | return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL); |
72899a61 | 6030 | } |
6031 | ||
6032 | ||
6033 | ||
6d36483b | 6034 | /* This routine handles all the normal conditional branch sequences we |
6035 | might need to generate. It handles compare immediate vs compare | |
6036 | register, nullification of delay slots, varying length branches, | |
0d986529 | 6037 | negated branches, and all combinations of the above. It returns the |
6d36483b | 6038 | output appropriate to emit the branch corresponding to all given |
0d986529 | 6039 | parameters. */ |
6040 | ||
611a88e1 | 6041 | const char * |
5c1d8983 | 6042 | output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn) |
29a4502c | 6043 | { |
0d986529 | 6044 | static char buf[100]; |
6045 | int useskip = 0; | |
e9ec370e | 6046 | rtx xoperands[5]; |
0d986529 | 6047 | |
ece0fa59 | 6048 | /* A conditional branch to the following instruction (eg the delay slot) |
6049 | is asking for a disaster. This can happen when not optimizing and | |
6050 | when jump optimization fails. | |
29a4502c | 6051 | |
38efba6c | 6052 | While it is usually safe to emit nothing, this can fail if the |
6053 | preceding instruction is a nullified branch with an empty delay | |
6054 | slot and the same branch target as this branch. We could check | |
6055 | for this but jump optimization should eliminate nop jumps. It | |
6056 | is always safe to emit a nop. */ | |
ece0fa59 | 6057 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6058 | return "nop"; | |
6d36483b | 6059 | |
22699a7e | 6060 | /* The doubleword form of the cmpib instruction doesn't have the LEU |
6061 | and GTU conditions while the cmpb instruction does. Since we accept | |
6062 | zero for cmpb, we must ensure that we use cmpb for the comparison. */ | |
6063 | if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx) | |
6064 | operands[2] = gen_rtx_REG (DImode, 0); | |
6065 | ||
5fbd5940 | 6066 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6067 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6068 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6069 | nullify = 1; |
6070 | ||
6071 | /* If this is a short forward conditional branch which did not get | |
6072 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6073 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6074 | nullify = forward_branch_p (insn); |
6075 | ||
6d36483b | 6076 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6077 | comclr instruction. This avoids a single cycle penalty due to |
6078 | mis-predicted branch if we fall through (branch not taken). */ | |
5a1231ef | 6079 | if (length == 4 |
5fbd5940 | 6080 | && next_real_insn (insn) != 0 |
5a1231ef | 6081 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 6082 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 6083 | && nullify) |
6084 | useskip = 1; | |
6085 | ||
6086 | switch (length) | |
6087 | { | |
5fbd5940 | 6088 | /* All short conditional branches except backwards with an unfilled |
6089 | delay slot. */ | |
5a1231ef | 6090 | case 4: |
0d986529 | 6091 | if (useskip) |
e4065f95 | 6092 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
0d986529 | 6093 | else |
e4065f95 | 6094 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6095 | if (GET_MODE (operands[1]) == DImode) |
6096 | strcat (buf, "*"); | |
0d986529 | 6097 | if (negated) |
6098 | strcat (buf, "%B3"); | |
6099 | else | |
6100 | strcat (buf, "%S3"); | |
6101 | if (useskip) | |
5a811d43 | 6102 | strcat (buf, " %2,%r1,%%r0"); |
0d986529 | 6103 | else if (nullify) |
9e49be0e | 6104 | strcat (buf, ",n %2,%r1,%0"); |
6d36483b | 6105 | else |
9e49be0e | 6106 | strcat (buf, " %2,%r1,%0"); |
0d986529 | 6107 | break; |
6108 | ||
87fcb603 | 6109 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6110 | unfilled delay slot is treated just like a long backward branch |
6111 | with an unfilled delay slot. */ | |
5a1231ef | 6112 | case 8: |
5fbd5940 | 6113 | /* Handle weird backwards branch with a filled delay slot |
6114 | with is nullified. */ | |
6115 | if (dbr_sequence_length () != 0 | |
6116 | && ! forward_branch_p (insn) | |
6117 | && nullify) | |
6118 | { | |
e4065f95 | 6119 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6120 | if (GET_MODE (operands[1]) == DImode) |
6121 | strcat (buf, "*"); | |
5fbd5940 | 6122 | if (negated) |
6123 | strcat (buf, "%S3"); | |
6124 | else | |
6125 | strcat (buf, "%B3"); | |
5a811d43 | 6126 | strcat (buf, ",n %2,%r1,.+12\n\tb %0"); |
5fbd5940 | 6127 | } |
43f0c1f2 | 6128 | /* Handle short backwards branch with an unfilled delay slot. |
6129 | Using a comb;nop rather than comiclr;bl saves 1 cycle for both | |
6130 | taken and untaken branches. */ | |
6131 | else if (dbr_sequence_length () == 0 | |
6132 | && ! forward_branch_p (insn) | |
47fc0706 | 6133 | && INSN_ADDRESSES_SET_P () |
6134 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6135 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6136 | { |
e4065f95 | 6137 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6138 | if (GET_MODE (operands[1]) == DImode) |
6139 | strcat (buf, "*"); | |
43f0c1f2 | 6140 | if (negated) |
9e49be0e | 6141 | strcat (buf, "%B3 %2,%r1,%0%#"); |
43f0c1f2 | 6142 | else |
9e49be0e | 6143 | strcat (buf, "%S3 %2,%r1,%0%#"); |
43f0c1f2 | 6144 | } |
0d986529 | 6145 | else |
5fbd5940 | 6146 | { |
e4065f95 | 6147 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
5e3c5739 | 6148 | if (GET_MODE (operands[1]) == DImode) |
6149 | strcat (buf, "*"); | |
5fbd5940 | 6150 | if (negated) |
6151 | strcat (buf, "%S3"); | |
6152 | else | |
6153 | strcat (buf, "%B3"); | |
6154 | if (nullify) | |
5a811d43 | 6155 | strcat (buf, " %2,%r1,%%r0\n\tb,n %0"); |
5fbd5940 | 6156 | else |
5a811d43 | 6157 | strcat (buf, " %2,%r1,%%r0\n\tb %0"); |
5fbd5940 | 6158 | } |
0d986529 | 6159 | break; |
6160 | ||
c8a0e52b | 6161 | case 20: |
e9ec370e | 6162 | case 28: |
6163 | xoperands[0] = operands[0]; | |
6164 | xoperands[1] = operands[1]; | |
6165 | xoperands[2] = operands[2]; | |
6166 | xoperands[3] = operands[3]; | |
6167 | ||
6168 | /* The reversed conditional branch must branch over one additional | |
6169 | instruction if the delay slot is filled. If the delay slot | |
6170 | is empty, the instruction after the reversed condition branch | |
6171 | must be nullified. */ | |
6172 | nullify = dbr_sequence_length () == 0; | |
6173 | xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4); | |
c8a0e52b | 6174 | |
6175 | /* Create a reversed conditional branch which branches around | |
6176 | the following insns. */ | |
e9ec370e | 6177 | if (GET_MODE (operands[1]) != DImode) |
6178 | { | |
6179 | if (nullify) | |
6180 | { | |
6181 | if (negated) | |
6182 | strcpy (buf, | |
6183 | "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}"); | |
6184 | else | |
6185 | strcpy (buf, | |
6186 | "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}"); | |
6187 | } | |
6188 | else | |
6189 | { | |
6190 | if (negated) | |
6191 | strcpy (buf, | |
6192 | "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}"); | |
6193 | else | |
6194 | strcpy (buf, | |
6195 | "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}"); | |
6196 | } | |
6197 | } | |
c8a0e52b | 6198 | else |
5e3c5739 | 6199 | { |
e9ec370e | 6200 | if (nullify) |
6201 | { | |
6202 | if (negated) | |
6203 | strcpy (buf, | |
6204 | "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}"); | |
6205 | else | |
6206 | strcpy (buf, | |
6207 | "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}"); | |
6208 | } | |
5e3c5739 | 6209 | else |
e9ec370e | 6210 | { |
6211 | if (negated) | |
6212 | strcpy (buf, | |
6213 | "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}"); | |
6214 | else | |
6215 | strcpy (buf, | |
6216 | "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}"); | |
6217 | } | |
5e3c5739 | 6218 | } |
c8a0e52b | 6219 | |
e9ec370e | 6220 | output_asm_insn (buf, xoperands); |
6221 | return output_lbranch (operands[0], insn); | |
c8a0e52b | 6222 | |
e9ec370e | 6223 | default: |
6224 | abort (); | |
6225 | } | |
6226 | return buf; | |
6227 | } | |
c8a0e52b | 6228 | |
e9ec370e | 6229 | /* This routine handles long unconditional branches that exceed the |
6230 | maximum range of a simple branch instruction. */ | |
c8a0e52b | 6231 | |
e9ec370e | 6232 | const char * |
5c1d8983 | 6233 | output_lbranch (rtx dest, rtx insn) |
e9ec370e | 6234 | { |
6235 | rtx xoperands[2]; | |
6236 | ||
6237 | xoperands[0] = dest; | |
c8a0e52b | 6238 | |
e9ec370e | 6239 | /* First, free up the delay slot. */ |
6240 | if (dbr_sequence_length () != 0) | |
6241 | { | |
6242 | /* We can't handle a jump in the delay slot. */ | |
6243 | if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN) | |
6244 | abort (); | |
c8a0e52b | 6245 | |
e9ec370e | 6246 | final_scan_insn (NEXT_INSN (insn), asm_out_file, |
fbf5169c | 6247 | optimize, 0, 0, NULL); |
c8a0e52b | 6248 | |
e9ec370e | 6249 | /* Now delete the delay insn. */ |
6250 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
6251 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
6252 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
6253 | } | |
c8a0e52b | 6254 | |
e9ec370e | 6255 | /* Output an insn to save %r1. The runtime documentation doesn't |
6256 | specify whether the "Clean Up" slot in the callers frame can | |
6257 | be clobbered by the callee. It isn't copied by HP's builtin | |
6258 | alloca, so this suggests that it can be clobbered if necessary. | |
6259 | The "Static Link" location is copied by HP builtin alloca, so | |
6260 | we avoid using it. Using the cleanup slot might be a problem | |
6261 | if we have to interoperate with languages that pass cleanup | |
6262 | information. However, it should be possible to handle these | |
6263 | situations with GCC's asm feature. | |
6264 | ||
6265 | The "Current RP" slot is reserved for the called procedure, so | |
6266 | we try to use it when we don't have a frame of our own. It's | |
6267 | rather unlikely that we won't have a frame when we need to emit | |
6268 | a very long branch. | |
6269 | ||
6270 | Really the way to go long term is a register scavenger; goto | |
6271 | the target of the jump and find a register which we can use | |
6272 | as a scratch to hold the value in %r1. Then, we wouldn't have | |
6273 | to free up the delay slot or clobber a slot that may be needed | |
6274 | for other purposes. */ | |
6275 | if (TARGET_64BIT) | |
6276 | { | |
6277 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6278 | /* Use the return pointer slot in the frame marker. */ | |
6279 | output_asm_insn ("std %%r1,-16(%%r30)", xoperands); | |
6280 | else | |
6281 | /* Use the slot at -40 in the frame marker since HP builtin | |
6282 | alloca doesn't copy it. */ | |
6283 | output_asm_insn ("std %%r1,-40(%%r30)", xoperands); | |
6284 | } | |
6285 | else | |
6286 | { | |
6287 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6288 | /* Use the return pointer slot in the frame marker. */ | |
6289 | output_asm_insn ("stw %%r1,-20(%%r30)", xoperands); | |
6290 | else | |
6291 | /* Use the "Clean Up" slot in the frame marker. In GCC, | |
6292 | the only other use of this location is for copying a | |
6293 | floating point double argument from a floating-point | |
6294 | register to two general registers. The copy is done | |
19ee40ed | 6295 | as an "atomic" operation when outputting a call, so it |
e9ec370e | 6296 | won't interfere with our using the location here. */ |
6297 | output_asm_insn ("stw %%r1,-12(%%r30)", xoperands); | |
6298 | } | |
b70ea764 | 6299 | |
2247cc5f | 6300 | if (TARGET_PORTABLE_RUNTIME) |
6301 | { | |
6302 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6303 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
6304 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6305 | } | |
6306 | else if (flag_pic) | |
e9ec370e | 6307 | { |
6308 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
6309 | if (TARGET_SOM || !TARGET_GAS) | |
6310 | { | |
6311 | xoperands[1] = gen_label_rtx (); | |
6312 | output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands); | |
6313 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
6314 | CODE_LABEL_NUMBER (xoperands[1])); | |
6315 | output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands); | |
c8a0e52b | 6316 | } |
e9ec370e | 6317 | else |
6318 | { | |
6319 | output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6320 | output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6321 | } | |
6322 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6323 | } | |
6324 | else | |
6325 | /* Now output a very long branch to the original target. */ | |
6326 | output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands); | |
c8a0e52b | 6327 | |
e9ec370e | 6328 | /* Now restore the value of %r1 in the delay slot. */ |
6329 | if (TARGET_64BIT) | |
6330 | { | |
6331 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6332 | return "ldd -16(%%r30),%%r1"; | |
6333 | else | |
6334 | return "ldd -40(%%r30),%%r1"; | |
6335 | } | |
6336 | else | |
6337 | { | |
6338 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6339 | return "ldw -20(%%r30),%%r1"; | |
6340 | else | |
6341 | return "ldw -12(%%r30),%%r1"; | |
5fbd5940 | 6342 | } |
0d986529 | 6343 | } |
6344 | ||
6d36483b | 6345 | /* This routine handles all the branch-on-bit conditional branch sequences we |
0d986529 | 6346 | might need to generate. It handles nullification of delay slots, |
6347 | varying length branches, negated branches and all combinations of the | |
6348 | above. it returns the appropriate output template to emit the branch. */ | |
6349 | ||
611a88e1 | 6350 | const char * |
5c1d8983 | 6351 | output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length, |
6352 | int negated, rtx insn, int which) | |
29a4502c | 6353 | { |
0d986529 | 6354 | static char buf[100]; |
6355 | int useskip = 0; | |
6356 | ||
29a4502c | 6357 | /* A conditional branch to the following instruction (eg the delay slot) is |
6358 | asking for a disaster. I do not think this can happen as this pattern | |
6d36483b | 6359 | is only used when optimizing; jump optimization should eliminate the |
29a4502c | 6360 | jump. But be prepared just in case. */ |
6d36483b | 6361 | |
ece0fa59 | 6362 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6363 | return "nop"; | |
6d36483b | 6364 | |
5fbd5940 | 6365 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6366 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6367 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6368 | nullify = 1; |
6369 | ||
6370 | /* If this is a short forward conditional branch which did not get | |
6371 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6372 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6373 | nullify = forward_branch_p (insn); |
6374 | ||
6d36483b | 6375 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6376 | extrs instruction. This avoids a single cycle penalty due to |
6377 | mis-predicted branch if we fall through (branch not taken). */ | |
6378 | ||
5a1231ef | 6379 | if (length == 4 |
5fbd5940 | 6380 | && next_real_insn (insn) != 0 |
5a1231ef | 6381 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 6382 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 6383 | && nullify) |
6384 | useskip = 1; | |
6385 | ||
6386 | switch (length) | |
6387 | { | |
6388 | ||
5fbd5940 | 6389 | /* All short conditional branches except backwards with an unfilled |
6390 | delay slot. */ | |
5a1231ef | 6391 | case 4: |
0d986529 | 6392 | if (useskip) |
e4065f95 | 6393 | strcpy (buf, "{extrs,|extrw,s,}"); |
6d36483b | 6394 | else |
0d986529 | 6395 | strcpy (buf, "bb,"); |
5e3c5739 | 6396 | if (useskip && GET_MODE (operands[0]) == DImode) |
6397 | strcpy (buf, "extrd,s,*"); | |
6398 | else if (GET_MODE (operands[0]) == DImode) | |
6399 | strcpy (buf, "bb,*"); | |
0d986529 | 6400 | if ((which == 0 && negated) |
6401 | || (which == 1 && ! negated)) | |
6402 | strcat (buf, ">="); | |
6403 | else | |
6404 | strcat (buf, "<"); | |
6405 | if (useskip) | |
5a811d43 | 6406 | strcat (buf, " %0,%1,1,%%r0"); |
0d986529 | 6407 | else if (nullify && negated) |
6408 | strcat (buf, ",n %0,%1,%3"); | |
6409 | else if (nullify && ! negated) | |
6410 | strcat (buf, ",n %0,%1,%2"); | |
6411 | else if (! nullify && negated) | |
5fbd5940 | 6412 | strcat (buf, "%0,%1,%3"); |
0d986529 | 6413 | else if (! nullify && ! negated) |
5fbd5940 | 6414 | strcat (buf, " %0,%1,%2"); |
0d986529 | 6415 | break; |
6416 | ||
87fcb603 | 6417 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6418 | unfilled delay slot is treated just like a long backward branch |
6419 | with an unfilled delay slot. */ | |
5a1231ef | 6420 | case 8: |
5fbd5940 | 6421 | /* Handle weird backwards branch with a filled delay slot |
6422 | with is nullified. */ | |
6423 | if (dbr_sequence_length () != 0 | |
6424 | && ! forward_branch_p (insn) | |
6425 | && nullify) | |
6426 | { | |
6427 | strcpy (buf, "bb,"); | |
5e3c5739 | 6428 | if (GET_MODE (operands[0]) == DImode) |
6429 | strcat (buf, "*"); | |
5fbd5940 | 6430 | if ((which == 0 && negated) |
6431 | || (which == 1 && ! negated)) | |
6432 | strcat (buf, "<"); | |
6433 | else | |
6434 | strcat (buf, ">="); | |
6435 | if (negated) | |
5a811d43 | 6436 | strcat (buf, ",n %0,%1,.+12\n\tb %3"); |
5fbd5940 | 6437 | else |
5a811d43 | 6438 | strcat (buf, ",n %0,%1,.+12\n\tb %2"); |
5fbd5940 | 6439 | } |
43f0c1f2 | 6440 | /* Handle short backwards branch with an unfilled delay slot. |
6441 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6442 | taken and untaken branches. */ | |
6443 | else if (dbr_sequence_length () == 0 | |
6444 | && ! forward_branch_p (insn) | |
47fc0706 | 6445 | && INSN_ADDRESSES_SET_P () |
6446 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6447 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6448 | { |
6449 | strcpy (buf, "bb,"); | |
5e3c5739 | 6450 | if (GET_MODE (operands[0]) == DImode) |
6451 | strcat (buf, "*"); | |
43f0c1f2 | 6452 | if ((which == 0 && negated) |
6453 | || (which == 1 && ! negated)) | |
6454 | strcat (buf, ">="); | |
6455 | else | |
6456 | strcat (buf, "<"); | |
6457 | if (negated) | |
6458 | strcat (buf, " %0,%1,%3%#"); | |
6459 | else | |
6460 | strcat (buf, " %0,%1,%2%#"); | |
6461 | } | |
0d986529 | 6462 | else |
5fbd5940 | 6463 | { |
e4065f95 | 6464 | strcpy (buf, "{extrs,|extrw,s,}"); |
5e3c5739 | 6465 | if (GET_MODE (operands[0]) == DImode) |
6466 | strcpy (buf, "extrd,s,*"); | |
5fbd5940 | 6467 | if ((which == 0 && negated) |
6468 | || (which == 1 && ! negated)) | |
6469 | strcat (buf, "<"); | |
6470 | else | |
6471 | strcat (buf, ">="); | |
6472 | if (nullify && negated) | |
c6ae275c | 6473 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %3"); |
5fbd5940 | 6474 | else if (nullify && ! negated) |
c6ae275c | 6475 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %2"); |
5fbd5940 | 6476 | else if (negated) |
5a811d43 | 6477 | strcat (buf, " %0,%1,1,%%r0\n\tb %3"); |
6d36483b | 6478 | else |
5a811d43 | 6479 | strcat (buf, " %0,%1,1,%%r0\n\tb %2"); |
5fbd5940 | 6480 | } |
0d986529 | 6481 | break; |
6482 | ||
6483 | default: | |
ea52c577 | 6484 | abort (); |
5fbd5940 | 6485 | } |
0d986529 | 6486 | return buf; |
6487 | } | |
6488 | ||
c7a4e712 | 6489 | /* This routine handles all the branch-on-variable-bit conditional branch |
6490 | sequences we might need to generate. It handles nullification of delay | |
6491 | slots, varying length branches, negated branches and all combinations | |
6492 | of the above. it returns the appropriate output template to emit the | |
6493 | branch. */ | |
6494 | ||
611a88e1 | 6495 | const char * |
5c1d8983 | 6496 | output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length, |
6497 | int negated, rtx insn, int which) | |
c7a4e712 | 6498 | { |
6499 | static char buf[100]; | |
6500 | int useskip = 0; | |
6501 | ||
6502 | /* A conditional branch to the following instruction (eg the delay slot) is | |
6503 | asking for a disaster. I do not think this can happen as this pattern | |
6504 | is only used when optimizing; jump optimization should eliminate the | |
6505 | jump. But be prepared just in case. */ | |
6506 | ||
ece0fa59 | 6507 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6508 | return "nop"; | |
c7a4e712 | 6509 | |
6510 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6511 | as it can nullify the delay slot and save a nop. */ | |
6512 | if (length == 8 && dbr_sequence_length () == 0) | |
6513 | nullify = 1; | |
6514 | ||
6515 | /* If this is a short forward conditional branch which did not get | |
6516 | its delay slot filled, the delay slot can still be nullified. */ | |
6517 | if (! nullify && length == 4 && dbr_sequence_length () == 0) | |
6518 | nullify = forward_branch_p (insn); | |
6519 | ||
6520 | /* A forward branch over a single nullified insn can be done with a | |
6521 | extrs instruction. This avoids a single cycle penalty due to | |
6522 | mis-predicted branch if we fall through (branch not taken). */ | |
6523 | ||
6524 | if (length == 4 | |
6525 | && next_real_insn (insn) != 0 | |
6526 | && get_attr_length (next_real_insn (insn)) == 4 | |
6527 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) | |
6528 | && nullify) | |
6529 | useskip = 1; | |
6530 | ||
6531 | switch (length) | |
6532 | { | |
6533 | ||
6534 | /* All short conditional branches except backwards with an unfilled | |
6535 | delay slot. */ | |
6536 | case 4: | |
6537 | if (useskip) | |
e4065f95 | 6538 | strcpy (buf, "{vextrs,|extrw,s,}"); |
c7a4e712 | 6539 | else |
e4065f95 | 6540 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6541 | if (useskip && GET_MODE (operands[0]) == DImode) |
e75269fd | 6542 | strcpy (buf, "extrd,s,*"); |
5e3c5739 | 6543 | else if (GET_MODE (operands[0]) == DImode) |
6544 | strcpy (buf, "bb,*"); | |
c7a4e712 | 6545 | if ((which == 0 && negated) |
6546 | || (which == 1 && ! negated)) | |
6547 | strcat (buf, ">="); | |
6548 | else | |
6549 | strcat (buf, "<"); | |
6550 | if (useskip) | |
e4065f95 | 6551 | strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}"); |
c7a4e712 | 6552 | else if (nullify && negated) |
e4065f95 | 6553 | strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}"); |
c7a4e712 | 6554 | else if (nullify && ! negated) |
e4065f95 | 6555 | strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}"); |
c7a4e712 | 6556 | else if (! nullify && negated) |
e4065f95 | 6557 | strcat (buf, "{%0,%3|%0,%%sar,%3}"); |
c7a4e712 | 6558 | else if (! nullify && ! negated) |
e4065f95 | 6559 | strcat (buf, "{ %0,%2| %0,%%sar,%2}"); |
c7a4e712 | 6560 | break; |
6561 | ||
87fcb603 | 6562 | /* All long conditionals. Note a short backward branch with an |
c7a4e712 | 6563 | unfilled delay slot is treated just like a long backward branch |
6564 | with an unfilled delay slot. */ | |
6565 | case 8: | |
6566 | /* Handle weird backwards branch with a filled delay slot | |
6567 | with is nullified. */ | |
6568 | if (dbr_sequence_length () != 0 | |
6569 | && ! forward_branch_p (insn) | |
6570 | && nullify) | |
6571 | { | |
e4065f95 | 6572 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6573 | if (GET_MODE (operands[0]) == DImode) |
6574 | strcat (buf, "*"); | |
c7a4e712 | 6575 | if ((which == 0 && negated) |
6576 | || (which == 1 && ! negated)) | |
6577 | strcat (buf, "<"); | |
6578 | else | |
6579 | strcat (buf, ">="); | |
6580 | if (negated) | |
e4065f95 | 6581 | strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}"); |
c7a4e712 | 6582 | else |
e4065f95 | 6583 | strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}"); |
c7a4e712 | 6584 | } |
6585 | /* Handle short backwards branch with an unfilled delay slot. | |
6586 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6587 | taken and untaken branches. */ | |
6588 | else if (dbr_sequence_length () == 0 | |
6589 | && ! forward_branch_p (insn) | |
47fc0706 | 6590 | && INSN_ADDRESSES_SET_P () |
6591 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6592 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
c7a4e712 | 6593 | { |
e4065f95 | 6594 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6595 | if (GET_MODE (operands[0]) == DImode) |
6596 | strcat (buf, "*"); | |
c7a4e712 | 6597 | if ((which == 0 && negated) |
6598 | || (which == 1 && ! negated)) | |
6599 | strcat (buf, ">="); | |
6600 | else | |
6601 | strcat (buf, "<"); | |
6602 | if (negated) | |
e4065f95 | 6603 | strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}"); |
c7a4e712 | 6604 | else |
e4065f95 | 6605 | strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}"); |
c7a4e712 | 6606 | } |
6607 | else | |
6608 | { | |
e4065f95 | 6609 | strcpy (buf, "{vextrs,|extrw,s,}"); |
5e3c5739 | 6610 | if (GET_MODE (operands[0]) == DImode) |
6611 | strcpy (buf, "extrd,s,*"); | |
c7a4e712 | 6612 | if ((which == 0 && negated) |
6613 | || (which == 1 && ! negated)) | |
6614 | strcat (buf, "<"); | |
6615 | else | |
6616 | strcat (buf, ">="); | |
6617 | if (nullify && negated) | |
e4065f95 | 6618 | strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}"); |
c7a4e712 | 6619 | else if (nullify && ! negated) |
e4065f95 | 6620 | strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}"); |
c7a4e712 | 6621 | else if (negated) |
e4065f95 | 6622 | strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}"); |
c7a4e712 | 6623 | else |
e4065f95 | 6624 | strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}"); |
c7a4e712 | 6625 | } |
6626 | break; | |
6627 | ||
6628 | default: | |
ea52c577 | 6629 | abort (); |
c7a4e712 | 6630 | } |
6631 | return buf; | |
6632 | } | |
6633 | ||
29a4502c | 6634 | /* Return the output template for emitting a dbra type insn. |
6635 | ||
6636 | Note it may perform some output operations on its own before | |
6637 | returning the final output string. */ | |
611a88e1 | 6638 | const char * |
5c1d8983 | 6639 | output_dbra (rtx *operands, rtx insn, int which_alternative) |
29a4502c | 6640 | { |
6641 | ||
6642 | /* A conditional branch to the following instruction (eg the delay slot) is | |
6643 | asking for a disaster. Be prepared! */ | |
6644 | ||
ece0fa59 | 6645 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
29a4502c | 6646 | { |
6647 | if (which_alternative == 0) | |
6648 | return "ldo %1(%0),%0"; | |
6649 | else if (which_alternative == 1) | |
6650 | { | |
ea52c577 | 6651 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands); |
6652 | output_asm_insn ("ldw -16(%%r30),%4", operands); | |
34940871 | 6653 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
e4065f95 | 6654 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6655 | } |
6656 | else | |
6657 | { | |
6658 | output_asm_insn ("ldw %0,%4", operands); | |
6659 | return "ldo %1(%4),%4\n\tstw %4,%0"; | |
6660 | } | |
6661 | } | |
6662 | ||
6663 | if (which_alternative == 0) | |
6664 | { | |
6665 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
6666 | int length = get_attr_length (insn); | |
6667 | ||
6668 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6669 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6670 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 6671 | nullify = 1; |
6672 | ||
6673 | /* If this is a short forward conditional branch which did not get | |
6674 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6675 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 6676 | nullify = forward_branch_p (insn); |
6677 | ||
6678 | /* Handle short versions first. */ | |
5a1231ef | 6679 | if (length == 4 && nullify) |
29a4502c | 6680 | return "addib,%C2,n %1,%0,%3"; |
5a1231ef | 6681 | else if (length == 4 && ! nullify) |
29a4502c | 6682 | return "addib,%C2 %1,%0,%3"; |
5a1231ef | 6683 | else if (length == 8) |
29a4502c | 6684 | { |
6d36483b | 6685 | /* Handle weird backwards branch with a fulled delay slot |
29a4502c | 6686 | which is nullified. */ |
6687 | if (dbr_sequence_length () != 0 | |
6688 | && ! forward_branch_p (insn) | |
6689 | && nullify) | |
5a811d43 | 6690 | return "addib,%N2,n %1,%0,.+12\n\tb %3"; |
43f0c1f2 | 6691 | /* Handle short backwards branch with an unfilled delay slot. |
6692 | Using a addb;nop rather than addi;bl saves 1 cycle for both | |
6693 | taken and untaken branches. */ | |
6694 | else if (dbr_sequence_length () == 0 | |
6695 | && ! forward_branch_p (insn) | |
47fc0706 | 6696 | && INSN_ADDRESSES_SET_P () |
6697 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6698 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6699 | return "addib,%C2 %1,%0,%3%#"; |
6d36483b | 6700 | |
6701 | /* Handle normal cases. */ | |
29a4502c | 6702 | if (nullify) |
5a811d43 | 6703 | return "addi,%N2 %1,%0,%0\n\tb,n %3"; |
29a4502c | 6704 | else |
5a811d43 | 6705 | return "addi,%N2 %1,%0,%0\n\tb %3"; |
29a4502c | 6706 | } |
6707 | else | |
ea52c577 | 6708 | abort (); |
29a4502c | 6709 | } |
6710 | /* Deal with gross reload from FP register case. */ | |
6711 | else if (which_alternative == 1) | |
6712 | { | |
6713 | /* Move loop counter from FP register to MEM then into a GR, | |
6714 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 6715 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 6716 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4", |
6717 | operands); | |
34940871 | 6718 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
5a1231ef | 6719 | if (get_attr_length (insn) == 24) |
e4065f95 | 6720 | return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6721 | else |
e4065f95 | 6722 | return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6723 | } |
6724 | /* Deal with gross reload from memory case. */ | |
6725 | else | |
6726 | { | |
6727 | /* Reload loop counter from memory, the store back to memory | |
6728 | happens in the branch's delay slot. */ | |
6729 | output_asm_insn ("ldw %0,%4", operands); | |
5a1231ef | 6730 | if (get_attr_length (insn) == 12) |
29a4502c | 6731 | return "addib,%C2 %1,%4,%3\n\tstw %4,%0"; |
6732 | else | |
5a811d43 | 6733 | return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0"; |
29a4502c | 6734 | } |
6735 | } | |
6736 | ||
6737 | /* Return the output template for emitting a dbra type insn. | |
6738 | ||
6739 | Note it may perform some output operations on its own before | |
6740 | returning the final output string. */ | |
611a88e1 | 6741 | const char * |
5c1d8983 | 6742 | output_movb (rtx *operands, rtx insn, int which_alternative, |
6743 | int reverse_comparison) | |
29a4502c | 6744 | { |
6745 | ||
6746 | /* A conditional branch to the following instruction (eg the delay slot) is | |
6747 | asking for a disaster. Be prepared! */ | |
6748 | ||
ece0fa59 | 6749 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
29a4502c | 6750 | { |
6751 | if (which_alternative == 0) | |
6752 | return "copy %1,%0"; | |
6753 | else if (which_alternative == 1) | |
6754 | { | |
ea52c577 | 6755 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
e4065f95 | 6756 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6757 | } |
546a40bd | 6758 | else if (which_alternative == 2) |
29a4502c | 6759 | return "stw %1,%0"; |
546a40bd | 6760 | else |
6761 | return "mtsar %r1"; | |
29a4502c | 6762 | } |
6763 | ||
6764 | /* Support the second variant. */ | |
6765 | if (reverse_comparison) | |
6766 | PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2]))); | |
6767 | ||
6768 | if (which_alternative == 0) | |
6769 | { | |
6770 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
6771 | int length = get_attr_length (insn); | |
6772 | ||
6773 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6774 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6775 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 6776 | nullify = 1; |
6777 | ||
6778 | /* If this is a short forward conditional branch which did not get | |
6779 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6780 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 6781 | nullify = forward_branch_p (insn); |
6782 | ||
6783 | /* Handle short versions first. */ | |
5a1231ef | 6784 | if (length == 4 && nullify) |
29a4502c | 6785 | return "movb,%C2,n %1,%0,%3"; |
5a1231ef | 6786 | else if (length == 4 && ! nullify) |
29a4502c | 6787 | return "movb,%C2 %1,%0,%3"; |
5a1231ef | 6788 | else if (length == 8) |
29a4502c | 6789 | { |
6d36483b | 6790 | /* Handle weird backwards branch with a filled delay slot |
29a4502c | 6791 | which is nullified. */ |
6792 | if (dbr_sequence_length () != 0 | |
6793 | && ! forward_branch_p (insn) | |
6794 | && nullify) | |
5a811d43 | 6795 | return "movb,%N2,n %1,%0,.+12\n\tb %3"; |
6d36483b | 6796 | |
43f0c1f2 | 6797 | /* Handle short backwards branch with an unfilled delay slot. |
6798 | Using a movb;nop rather than or;bl saves 1 cycle for both | |
6799 | taken and untaken branches. */ | |
6800 | else if (dbr_sequence_length () == 0 | |
6801 | && ! forward_branch_p (insn) | |
47fc0706 | 6802 | && INSN_ADDRESSES_SET_P () |
6803 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6804 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6805 | return "movb,%C2 %1,%0,%3%#"; |
6d36483b | 6806 | /* Handle normal cases. */ |
29a4502c | 6807 | if (nullify) |
5a811d43 | 6808 | return "or,%N2 %1,%%r0,%0\n\tb,n %3"; |
29a4502c | 6809 | else |
5a811d43 | 6810 | return "or,%N2 %1,%%r0,%0\n\tb %3"; |
29a4502c | 6811 | } |
6812 | else | |
ea52c577 | 6813 | abort (); |
29a4502c | 6814 | } |
6815 | /* Deal with gross reload from FP register case. */ | |
6816 | else if (which_alternative == 1) | |
6817 | { | |
6818 | /* Move loop counter from FP register to MEM then into a GR, | |
6819 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 6820 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 6821 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
5a1231ef | 6822 | if (get_attr_length (insn) == 12) |
e4065f95 | 6823 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6824 | else |
e4065f95 | 6825 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6826 | } |
6827 | /* Deal with gross reload from memory case. */ | |
546a40bd | 6828 | else if (which_alternative == 2) |
29a4502c | 6829 | { |
6830 | /* Reload loop counter from memory, the store back to memory | |
6831 | happens in the branch's delay slot. */ | |
5a1231ef | 6832 | if (get_attr_length (insn) == 8) |
e4065f95 | 6833 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0"; |
29a4502c | 6834 | else |
e4065f95 | 6835 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0"; |
29a4502c | 6836 | } |
546a40bd | 6837 | /* Handle SAR as a destination. */ |
6838 | else | |
6839 | { | |
6840 | if (get_attr_length (insn) == 8) | |
e4065f95 | 6841 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1"; |
546a40bd | 6842 | else |
e4065f95 | 6843 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1"; |
546a40bd | 6844 | } |
29a4502c | 6845 | } |
6846 | ||
ece88821 | 6847 | /* Copy any FP arguments in INSN into integer registers. */ |
6848 | static void | |
5c1d8983 | 6849 | copy_fp_args (rtx insn) |
ece88821 | 6850 | { |
6851 | rtx link; | |
6852 | rtx xoperands[2]; | |
29a4502c | 6853 | |
ece88821 | 6854 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
6855 | { | |
6856 | int arg_mode, regno; | |
6857 | rtx use = XEXP (link, 0); | |
3683f840 | 6858 | |
ece88821 | 6859 | if (! (GET_CODE (use) == USE |
6860 | && GET_CODE (XEXP (use, 0)) == REG | |
6861 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
6862 | continue; | |
d6686e21 | 6863 | |
ece88821 | 6864 | arg_mode = GET_MODE (XEXP (use, 0)); |
6865 | regno = REGNO (XEXP (use, 0)); | |
5e3c5739 | 6866 | |
ece88821 | 6867 | /* Is it a floating point register? */ |
6868 | if (regno >= 32 && regno <= 39) | |
6869 | { | |
6870 | /* Copy the FP register into an integer register via memory. */ | |
6871 | if (arg_mode == SFmode) | |
6872 | { | |
6873 | xoperands[0] = XEXP (use, 0); | |
6874 | xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2); | |
6875 | output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands); | |
6876 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
6877 | } | |
6878 | else | |
6879 | { | |
6880 | xoperands[0] = XEXP (use, 0); | |
6881 | xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2); | |
6882 | output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands); | |
6883 | output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands); | |
6884 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
6885 | } | |
6886 | } | |
06ddb6f8 | 6887 | } |
ece88821 | 6888 | } |
6889 | ||
6890 | /* Compute length of the FP argument copy sequence for INSN. */ | |
6891 | static int | |
5c1d8983 | 6892 | length_fp_args (rtx insn) |
ece88821 | 6893 | { |
6894 | int length = 0; | |
6895 | rtx link; | |
06ddb6f8 | 6896 | |
ece88821 | 6897 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
c7a4e712 | 6898 | { |
ece88821 | 6899 | int arg_mode, regno; |
6900 | rtx use = XEXP (link, 0); | |
6901 | ||
6902 | if (! (GET_CODE (use) == USE | |
6903 | && GET_CODE (XEXP (use, 0)) == REG | |
6904 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
6905 | continue; | |
c7a4e712 | 6906 | |
ece88821 | 6907 | arg_mode = GET_MODE (XEXP (use, 0)); |
6908 | regno = REGNO (XEXP (use, 0)); | |
6909 | ||
6910 | /* Is it a floating point register? */ | |
6911 | if (regno >= 32 && regno <= 39) | |
c7a4e712 | 6912 | { |
ece88821 | 6913 | if (arg_mode == SFmode) |
6914 | length += 8; | |
6915 | else | |
6916 | length += 12; | |
c7a4e712 | 6917 | } |
ece88821 | 6918 | } |
c7a4e712 | 6919 | |
ece88821 | 6920 | return length; |
6921 | } | |
b70ea764 | 6922 | |
cd0dfcc5 | 6923 | /* Return the attribute length for the millicode call instruction INSN. |
6924 | The length must match the code generated by output_millicode_call. | |
6925 | We include the delay slot in the returned length as it is better to | |
ece88821 | 6926 | over estimate the length than to under estimate it. */ |
b29897dd | 6927 | |
ece88821 | 6928 | int |
5c1d8983 | 6929 | attr_length_millicode_call (rtx insn) |
ece88821 | 6930 | { |
cd0dfcc5 | 6931 | unsigned long distance = -1; |
8a05c3c2 | 6932 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
ece88821 | 6933 | |
cd0dfcc5 | 6934 | if (INSN_ADDRESSES_SET_P ()) |
6935 | { | |
2247cc5f | 6936 | distance = (total + insn_current_reference_address (insn)); |
6937 | if (distance < total) | |
cd0dfcc5 | 6938 | distance = -1; |
6939 | } | |
ece88821 | 6940 | |
6941 | if (TARGET_64BIT) | |
6942 | { | |
6943 | if (!TARGET_LONG_CALLS && distance < 7600000) | |
cd0dfcc5 | 6944 | return 8; |
ece88821 | 6945 | |
cd0dfcc5 | 6946 | return 20; |
ece88821 | 6947 | } |
6948 | else if (TARGET_PORTABLE_RUNTIME) | |
cd0dfcc5 | 6949 | return 24; |
ece88821 | 6950 | else |
6951 | { | |
6952 | if (!TARGET_LONG_CALLS && distance < 240000) | |
cd0dfcc5 | 6953 | return 8; |
ece88821 | 6954 | |
6955 | if (TARGET_LONG_ABS_CALL && !flag_pic) | |
cd0dfcc5 | 6956 | return 12; |
ece88821 | 6957 | |
cd0dfcc5 | 6958 | return 24; |
ece88821 | 6959 | } |
6960 | } | |
6961 | ||
6962 | /* INSN is a function call. It may have an unconditional jump | |
6963 | in its delay slot. | |
b29897dd | 6964 | |
ece88821 | 6965 | CALL_DEST is the routine we are calling. */ |
b29897dd | 6966 | |
ece88821 | 6967 | const char * |
5c1d8983 | 6968 | output_millicode_call (rtx insn, rtx call_dest) |
ece88821 | 6969 | { |
6970 | int attr_length = get_attr_length (insn); | |
6971 | int seq_length = dbr_sequence_length (); | |
6972 | int distance; | |
6973 | rtx seq_insn; | |
6974 | rtx xoperands[3]; | |
b29897dd | 6975 | |
ece88821 | 6976 | xoperands[0] = call_dest; |
6977 | xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31); | |
6978 | ||
6979 | /* Handle the common case where we are sure that the branch will | |
6980 | reach the beginning of the $CODE$ subspace. The within reach | |
6981 | form of the $$sh_func_adrs call has a length of 28. Because | |
a8b24921 | 6982 | it has an attribute type of multi, it never has a nonzero |
ece88821 | 6983 | sequence length. The length of the $$sh_func_adrs is the same |
6984 | as certain out of reach PIC calls to other routines. */ | |
6985 | if (!TARGET_LONG_CALLS | |
6986 | && ((seq_length == 0 | |
6987 | && (attr_length == 12 | |
6988 | || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI))) | |
6989 | || (seq_length != 0 && attr_length == 8))) | |
6990 | { | |
6991 | output_asm_insn ("{bl|b,l} %0,%2", xoperands); | |
6992 | } | |
6993 | else | |
6994 | { | |
6995 | if (TARGET_64BIT) | |
6996 | { | |
6997 | /* It might seem that one insn could be saved by accessing | |
6998 | the millicode function using the linkage table. However, | |
6999 | this doesn't work in shared libraries and other dynamically | |
7000 | loaded objects. Using a pc-relative sequence also avoids | |
7001 | problems related to the implicit use of the gp register. */ | |
7002 | output_asm_insn ("b,l .+8,%%r1", xoperands); | |
9bd9af5d | 7003 | |
7004 | if (TARGET_GAS) | |
7005 | { | |
7006 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); | |
7007 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
7008 | } | |
7009 | else | |
7010 | { | |
7011 | xoperands[1] = gen_label_rtx (); | |
7012 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
805e22b2 | 7013 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
9bd9af5d | 7014 | CODE_LABEL_NUMBER (xoperands[1])); |
7015 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
7016 | } | |
7017 | ||
ece88821 | 7018 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); |
c7a4e712 | 7019 | } |
c7a4e712 | 7020 | else if (TARGET_PORTABLE_RUNTIME) |
7021 | { | |
ece88821 | 7022 | /* Pure portable runtime doesn't allow be/ble; we also don't |
7023 | have PIC support in the assembler/linker, so this sequence | |
7024 | is needed. */ | |
c7a4e712 | 7025 | |
ece88821 | 7026 | /* Get the address of our target into %r1. */ |
7027 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
7028 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
c7a4e712 | 7029 | |
ece88821 | 7030 | /* Get our return address into %r31. */ |
7031 | output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands); | |
7032 | output_asm_insn ("addi 8,%%r31,%%r31", xoperands); | |
c7a4e712 | 7033 | |
ece88821 | 7034 | /* Jump to our target address in %r1. */ |
7035 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 7036 | } |
ece88821 | 7037 | else if (!flag_pic) |
c7a4e712 | 7038 | { |
ece88821 | 7039 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
356267e0 | 7040 | if (TARGET_PA_20) |
ece88821 | 7041 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands); |
356267e0 | 7042 | else |
ece88821 | 7043 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); |
c7a4e712 | 7044 | } |
ece88821 | 7045 | else |
c7a4e712 | 7046 | { |
9bd9af5d | 7047 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
7048 | output_asm_insn ("addi 16,%%r1,%%r31", xoperands); | |
7049 | ||
ece88821 | 7050 | if (TARGET_SOM || !TARGET_GAS) |
7051 | { | |
7052 | /* The HP assembler can generate relocations for the | |
7053 | difference of two symbols. GAS can do this for a | |
7054 | millicode symbol but not an arbitrary external | |
7055 | symbol when generating SOM output. */ | |
7056 | xoperands[1] = gen_label_rtx (); | |
805e22b2 | 7057 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
ece88821 | 7058 | CODE_LABEL_NUMBER (xoperands[1])); |
7059 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
7060 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
7061 | } | |
7062 | else | |
7063 | { | |
ece88821 | 7064 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands); |
7065 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1", | |
7066 | xoperands); | |
7067 | } | |
c7a4e712 | 7068 | |
ece88821 | 7069 | /* Jump to our target address in %r1. */ |
7070 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 7071 | } |
c7a4e712 | 7072 | } |
7073 | ||
ece88821 | 7074 | if (seq_length == 0) |
7075 | output_asm_insn ("nop", xoperands); | |
c7a4e712 | 7076 | |
ece88821 | 7077 | /* We are done if there isn't a jump in the delay slot. */ |
7078 | if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7079 | return ""; | |
c7a4e712 | 7080 | |
ece88821 | 7081 | /* This call has an unconditional jump in its delay slot. */ |
7082 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
c7a4e712 | 7083 | |
ece88821 | 7084 | /* See if the return address can be adjusted. Use the containing |
7085 | sequence insn's address. */ | |
cd0dfcc5 | 7086 | if (INSN_ADDRESSES_SET_P ()) |
c7a4e712 | 7087 | { |
cd0dfcc5 | 7088 | seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); |
7089 | distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7090 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7091 | ||
7092 | if (VAL_14_BITS_P (distance)) | |
7093 | { | |
7094 | xoperands[1] = gen_label_rtx (); | |
7095 | output_asm_insn ("ldo %0-%1(%2),%2", xoperands); | |
7096 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
7097 | CODE_LABEL_NUMBER (xoperands[1])); | |
7098 | } | |
7099 | else | |
7100 | /* ??? This branch may not reach its target. */ | |
7101 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 7102 | } |
ece88821 | 7103 | else |
7104 | /* ??? This branch may not reach its target. */ | |
7105 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 7106 | |
7107 | /* Delete the jump. */ | |
7108 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7109 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7110 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
ece88821 | 7111 | |
c7a4e712 | 7112 | return ""; |
7113 | } | |
7114 | ||
cd0dfcc5 | 7115 | /* Return the attribute length of the call instruction INSN. The SIBCALL |
7116 | flag indicates whether INSN is a regular call or a sibling call. The | |
faf3f8c1 | 7117 | length returned must be longer than the code actually generated by |
7118 | output_call. Since branch shortening is done before delay branch | |
7119 | sequencing, there is no way to determine whether or not the delay | |
7120 | slot will be filled during branch shortening. Even when the delay | |
7121 | slot is filled, we may have to add a nop if the delay slot contains | |
7122 | a branch that can't reach its target. Thus, we always have to include | |
7123 | the delay slot in the length estimate. This used to be done in | |
7124 | pa_adjust_insn_length but we do it here now as some sequences always | |
7125 | fill the delay slot and we can save four bytes in the estimate for | |
7126 | these sequences. */ | |
ece88821 | 7127 | |
7128 | int | |
5c1d8983 | 7129 | attr_length_call (rtx insn, int sibcall) |
ece88821 | 7130 | { |
faf3f8c1 | 7131 | int local_call; |
7132 | rtx call_dest; | |
7133 | tree call_decl; | |
7134 | int length = 0; | |
7135 | rtx pat = PATTERN (insn); | |
cd0dfcc5 | 7136 | unsigned long distance = -1; |
ece88821 | 7137 | |
cd0dfcc5 | 7138 | if (INSN_ADDRESSES_SET_P ()) |
7139 | { | |
faf3f8c1 | 7140 | unsigned long total; |
7141 | ||
7142 | total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; | |
2247cc5f | 7143 | distance = (total + insn_current_reference_address (insn)); |
7144 | if (distance < total) | |
cd0dfcc5 | 7145 | distance = -1; |
7146 | } | |
ece88821 | 7147 | |
faf3f8c1 | 7148 | /* Determine if this is a local call. */ |
7149 | if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL) | |
7150 | call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0); | |
ece88821 | 7151 | else |
faf3f8c1 | 7152 | call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0); |
ece88821 | 7153 | |
faf3f8c1 | 7154 | call_decl = SYMBOL_REF_DECL (call_dest); |
7155 | local_call = call_decl && (*targetm.binds_local_p) (call_decl); | |
ece88821 | 7156 | |
faf3f8c1 | 7157 | /* pc-relative branch. */ |
7158 | if (!TARGET_LONG_CALLS | |
7159 | && ((TARGET_PA_20 && !sibcall && distance < 7600000) | |
7160 | || distance < 240000)) | |
7161 | length += 8; | |
ece88821 | 7162 | |
faf3f8c1 | 7163 | /* 64-bit plabel sequence. */ |
7164 | else if (TARGET_64BIT && !local_call) | |
7165 | length += sibcall ? 28 : 24; | |
ece88821 | 7166 | |
faf3f8c1 | 7167 | /* non-pic long absolute branch sequence. */ |
7168 | else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) | |
7169 | length += 12; | |
ece88821 | 7170 | |
faf3f8c1 | 7171 | /* long pc-relative branch sequence. */ |
7172 | else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) | |
7173 | || (TARGET_64BIT && !TARGET_GAS) | |
7174 | || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))) | |
7175 | { | |
7176 | length += 20; | |
ece88821 | 7177 | |
faf3f8c1 | 7178 | if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS) |
7179 | length += 8; | |
7180 | } | |
8a05c3c2 | 7181 | |
faf3f8c1 | 7182 | /* 32-bit plabel sequence. */ |
7183 | else | |
7184 | { | |
7185 | length += 32; | |
ece88821 | 7186 | |
faf3f8c1 | 7187 | if (TARGET_SOM) |
7188 | length += length_fp_args (insn); | |
7189 | ||
7190 | if (flag_pic) | |
7191 | length += 4; | |
ee376abe | 7192 | |
faf3f8c1 | 7193 | if (!TARGET_PA_20) |
7194 | { | |
ece88821 | 7195 | if (!sibcall) |
7196 | length += 8; | |
7197 | ||
faf3f8c1 | 7198 | if (!TARGET_NO_SPACE_REGS) |
7199 | length += 8; | |
ece88821 | 7200 | } |
7201 | } | |
faf3f8c1 | 7202 | |
7203 | return length; | |
ece88821 | 7204 | } |
7205 | ||
7206 | /* INSN is a function call. It may have an unconditional jump | |
c7a4e712 | 7207 | in its delay slot. |
7208 | ||
7209 | CALL_DEST is the routine we are calling. */ | |
7210 | ||
611a88e1 | 7211 | const char * |
5c1d8983 | 7212 | output_call (rtx insn, rtx call_dest, int sibcall) |
c7a4e712 | 7213 | { |
ece88821 | 7214 | int delay_insn_deleted = 0; |
7215 | int delay_slot_filled = 0; | |
b70ea764 | 7216 | int seq_length = dbr_sequence_length (); |
2247cc5f | 7217 | tree call_decl = SYMBOL_REF_DECL (call_dest); |
faf3f8c1 | 7218 | int local_call = call_decl && (*targetm.binds_local_p) (call_decl); |
ece88821 | 7219 | rtx xoperands[2]; |
7220 | ||
7221 | xoperands[0] = call_dest; | |
c7a4e712 | 7222 | |
ece88821 | 7223 | /* Handle the common case where we're sure that the branch will reach |
2247cc5f | 7224 | the beginning of the "$CODE$" subspace. This is the beginning of |
7225 | the current function if we are in a named section. */ | |
cd0dfcc5 | 7226 | if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8) |
d6686e21 | 7227 | { |
5e3c5739 | 7228 | xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2); |
ece88821 | 7229 | output_asm_insn ("{bl|b,l} %0,%1", xoperands); |
06ddb6f8 | 7230 | } |
ece88821 | 7231 | else |
06ddb6f8 | 7232 | { |
2247cc5f | 7233 | if (TARGET_64BIT && !local_call) |
3683f840 | 7234 | { |
ece88821 | 7235 | /* ??? As far as I can tell, the HP linker doesn't support the |
7236 | long pc-relative sequence described in the 64-bit runtime | |
7237 | architecture. So, we use a slightly longer indirect call. */ | |
7238 | struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0)); | |
7239 | ||
7240 | xoperands[0] = p->internal_label; | |
7241 | xoperands[1] = gen_label_rtx (); | |
7242 | ||
7243 | /* If this isn't a sibcall, we put the load of %r27 into the | |
7244 | delay slot. We can't do this in a sibcall as we don't | |
7245 | have a second call-clobbered scratch register available. */ | |
7246 | if (seq_length != 0 | |
7247 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7248 | && !sibcall) | |
7249 | { | |
7250 | final_scan_insn (NEXT_INSN (insn), asm_out_file, | |
fbf5169c | 7251 | optimize, 0, 0, NULL); |
ece88821 | 7252 | |
7253 | /* Now delete the delay insn. */ | |
7254 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7255 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7256 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
7257 | delay_insn_deleted = 1; | |
7258 | } | |
06ddb6f8 | 7259 | |
ece88821 | 7260 | output_asm_insn ("addil LT'%0,%%r27", xoperands); |
7261 | output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands); | |
7262 | output_asm_insn ("ldd 0(%%r1),%%r1", xoperands); | |
06ddb6f8 | 7263 | |
ece88821 | 7264 | if (sibcall) |
06ddb6f8 | 7265 | { |
ece88821 | 7266 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); |
7267 | output_asm_insn ("ldd 16(%%r1),%%r1", xoperands); | |
7268 | output_asm_insn ("bve (%%r1)", xoperands); | |
7269 | } | |
7270 | else | |
7271 | { | |
7272 | output_asm_insn ("ldd 16(%%r1),%%r2", xoperands); | |
7273 | output_asm_insn ("bve,l (%%r2),%%r2", xoperands); | |
7274 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); | |
7275 | delay_slot_filled = 1; | |
06ddb6f8 | 7276 | } |
7277 | } | |
ece88821 | 7278 | else |
e3f53689 | 7279 | { |
ece88821 | 7280 | int indirect_call = 0; |
7281 | ||
7282 | /* Emit a long call. There are several different sequences | |
7283 | of increasing length and complexity. In most cases, | |
7284 | they don't allow an instruction in the delay slot. */ | |
2247cc5f | 7285 | if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
ece88821 | 7286 | && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) |
2247cc5f | 7287 | && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)) |
7288 | && !TARGET_64BIT) | |
ece88821 | 7289 | indirect_call = 1; |
7290 | ||
7291 | if (seq_length != 0 | |
7292 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7293 | && !sibcall | |
7294 | && (!TARGET_PA_20 || indirect_call)) | |
5cc6b2bc | 7295 | { |
ece88821 | 7296 | /* A non-jump insn in the delay slot. By definition we can |
7297 | emit this insn before the call (and in fact before argument | |
7298 | relocating. */ | |
fbf5169c | 7299 | final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0, |
7300 | NULL); | |
ece88821 | 7301 | |
7302 | /* Now delete the delay insn. */ | |
7303 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7304 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7305 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
7306 | delay_insn_deleted = 1; | |
5cc6b2bc | 7307 | } |
e3f53689 | 7308 | |
2247cc5f | 7309 | if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
5cc6b2bc | 7310 | { |
ece88821 | 7311 | /* This is the best sequence for making long calls in |
7312 | non-pic code. Unfortunately, GNU ld doesn't provide | |
7313 | the stub needed for external calls, and GAS's support | |
2247cc5f | 7314 | for this with the SOM linker is buggy. It is safe |
7315 | to use this for local calls. */ | |
ece88821 | 7316 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
7317 | if (sibcall) | |
7318 | output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands); | |
7319 | else | |
7320 | { | |
7321 | if (TARGET_PA_20) | |
7322 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", | |
7323 | xoperands); | |
7324 | else | |
7325 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); | |
c7a4e712 | 7326 | |
ece88821 | 7327 | output_asm_insn ("copy %%r31,%%r2", xoperands); |
7328 | delay_slot_filled = 1; | |
7329 | } | |
7330 | } | |
7331 | else | |
7332 | { | |
2247cc5f | 7333 | if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) |
7334 | || (TARGET_64BIT && !TARGET_GAS)) | |
b70ea764 | 7335 | { |
ece88821 | 7336 | /* The HP assembler and linker can handle relocations |
7337 | for the difference of two symbols. GAS and the HP | |
7338 | linker can't do this when one of the symbols is | |
7339 | external. */ | |
7340 | xoperands[1] = gen_label_rtx (); | |
7341 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7342 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
805e22b2 | 7343 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
b70ea764 | 7344 | CODE_LABEL_NUMBER (xoperands[1])); |
ece88821 | 7345 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); |
7346 | } | |
2247cc5f | 7347 | else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)) |
b70ea764 | 7348 | { |
ece88821 | 7349 | /* GAS currently can't generate the relocations that |
7350 | are needed for the SOM linker under HP-UX using this | |
7351 | sequence. The GNU linker doesn't generate the stubs | |
7352 | that are needed for external calls on TARGET_ELF32 | |
7353 | with this sequence. For now, we have to use a | |
7354 | longer plabel sequence when using GAS. */ | |
7355 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7356 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", | |
b70ea764 | 7357 | xoperands); |
ece88821 | 7358 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", |
b70ea764 | 7359 | xoperands); |
7360 | } | |
5e3c5739 | 7361 | else |
7362 | { | |
ece88821 | 7363 | /* Emit a long plabel-based call sequence. This is |
7364 | essentially an inline implementation of $$dyncall. | |
7365 | We don't actually try to call $$dyncall as this is | |
7366 | as difficult as calling the function itself. */ | |
7367 | struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0)); | |
7368 | ||
7369 | xoperands[0] = p->internal_label; | |
7370 | xoperands[1] = gen_label_rtx (); | |
7371 | ||
7372 | /* Since the call is indirect, FP arguments in registers | |
7373 | need to be copied to the general registers. Then, the | |
7374 | argument relocation stub will copy them back. */ | |
7375 | if (TARGET_SOM) | |
7376 | copy_fp_args (insn); | |
7377 | ||
7378 | if (flag_pic) | |
7379 | { | |
7380 | output_asm_insn ("addil LT'%0,%%r19", xoperands); | |
7381 | output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands); | |
7382 | output_asm_insn ("ldw 0(%%r1),%%r1", xoperands); | |
7383 | } | |
7384 | else | |
7385 | { | |
7386 | output_asm_insn ("addil LR'%0-$global$,%%r27", | |
7387 | xoperands); | |
7388 | output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1", | |
7389 | xoperands); | |
7390 | } | |
06ddb6f8 | 7391 | |
ece88821 | 7392 | output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands); |
7393 | output_asm_insn ("depi 0,31,2,%%r1", xoperands); | |
7394 | output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands); | |
7395 | output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands); | |
c7a4e712 | 7396 | |
ece88821 | 7397 | if (!sibcall && !TARGET_PA_20) |
7398 | { | |
7399 | output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands); | |
ee376abe | 7400 | if (TARGET_NO_SPACE_REGS) |
7401 | output_asm_insn ("addi 8,%%r2,%%r2", xoperands); | |
7402 | else | |
7403 | output_asm_insn ("addi 16,%%r2,%%r2", xoperands); | |
ece88821 | 7404 | } |
7405 | } | |
c7a4e712 | 7406 | |
ece88821 | 7407 | if (TARGET_PA_20) |
5e3c5739 | 7408 | { |
ece88821 | 7409 | if (sibcall) |
7410 | output_asm_insn ("bve (%%r1)", xoperands); | |
7411 | else | |
7412 | { | |
7413 | if (indirect_call) | |
7414 | { | |
7415 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7416 | output_asm_insn ("stw %%r2,-24(%%sp)", xoperands); | |
7417 | delay_slot_filled = 1; | |
7418 | } | |
7419 | else | |
7420 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7421 | } | |
5e3c5739 | 7422 | } |
7423 | else | |
7424 | { | |
ee376abe | 7425 | if (!TARGET_NO_SPACE_REGS) |
7426 | output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0", | |
7427 | xoperands); | |
06ddb6f8 | 7428 | |
ece88821 | 7429 | if (sibcall) |
ee376abe | 7430 | { |
7431 | if (TARGET_NO_SPACE_REGS) | |
7432 | output_asm_insn ("be 0(%%sr4,%%r1)", xoperands); | |
7433 | else | |
7434 | output_asm_insn ("be 0(%%sr0,%%r1)", xoperands); | |
7435 | } | |
ece88821 | 7436 | else |
7437 | { | |
ee376abe | 7438 | if (TARGET_NO_SPACE_REGS) |
7439 | output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands); | |
7440 | else | |
7441 | output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands); | |
06ddb6f8 | 7442 | |
ece88821 | 7443 | if (indirect_call) |
7444 | output_asm_insn ("stw %%r31,-24(%%sp)", xoperands); | |
7445 | else | |
7446 | output_asm_insn ("copy %%r31,%%r2", xoperands); | |
7447 | delay_slot_filled = 1; | |
7448 | } | |
7449 | } | |
7450 | } | |
06ddb6f8 | 7451 | } |
d6686e21 | 7452 | } |
6d36483b | 7453 | |
8a05c3c2 | 7454 | if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted)) |
ece88821 | 7455 | output_asm_insn ("nop", xoperands); |
d6686e21 | 7456 | |
ece88821 | 7457 | /* We are done if there isn't a jump in the delay slot. */ |
7458 | if (seq_length == 0 | |
7459 | || delay_insn_deleted | |
7460 | || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7461 | return ""; | |
d6686e21 | 7462 | |
ece88821 | 7463 | /* A sibcall should never have a branch in the delay slot. */ |
7464 | if (sibcall) | |
7465 | abort (); | |
d6686e21 | 7466 | |
ece88821 | 7467 | /* This call has an unconditional jump in its delay slot. */ |
7468 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
d6686e21 | 7469 | |
cd0dfcc5 | 7470 | if (!delay_slot_filled && INSN_ADDRESSES_SET_P ()) |
d6686e21 | 7471 | { |
ece88821 | 7472 | /* See if the return address can be adjusted. Use the containing |
7473 | sequence insn's address. */ | |
7474 | rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); | |
7475 | int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7476 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7477 | ||
7478 | if (VAL_14_BITS_P (distance)) | |
7479 | { | |
7480 | xoperands[1] = gen_label_rtx (); | |
7481 | output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands); | |
805e22b2 | 7482 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
7483 | CODE_LABEL_NUMBER (xoperands[1])); | |
ece88821 | 7484 | } |
7485 | else | |
ece88821 | 7486 | output_asm_insn ("nop\n\tb,n %0", xoperands); |
d6686e21 | 7487 | } |
ece88821 | 7488 | else |
ece88821 | 7489 | output_asm_insn ("b,n %0", xoperands); |
d6686e21 | 7490 | |
7491 | /* Delete the jump. */ | |
7492 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7493 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7494 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
ece88821 | 7495 | |
d6686e21 | 7496 | return ""; |
7497 | } | |
7498 | ||
cd0dfcc5 | 7499 | /* Return the attribute length of the indirect call instruction INSN. |
7500 | The length must match the code generated by output_indirect call. | |
7501 | The returned length includes the delay slot. Currently, the delay | |
7502 | slot of an indirect call sequence is not exposed and it is used by | |
7503 | the sequence itself. */ | |
7504 | ||
7505 | int | |
5c1d8983 | 7506 | attr_length_indirect_call (rtx insn) |
cd0dfcc5 | 7507 | { |
7508 | unsigned long distance = -1; | |
8a05c3c2 | 7509 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
cd0dfcc5 | 7510 | |
7511 | if (INSN_ADDRESSES_SET_P ()) | |
7512 | { | |
2247cc5f | 7513 | distance = (total + insn_current_reference_address (insn)); |
7514 | if (distance < total) | |
cd0dfcc5 | 7515 | distance = -1; |
7516 | } | |
7517 | ||
7518 | if (TARGET_64BIT) | |
7519 | return 12; | |
7520 | ||
7521 | if (TARGET_FAST_INDIRECT_CALLS | |
7522 | || (!TARGET_PORTABLE_RUNTIME | |
7523 | && ((TARGET_PA_20 && distance < 7600000) || distance < 240000))) | |
7524 | return 8; | |
7525 | ||
7526 | if (flag_pic) | |
7527 | return 24; | |
7528 | ||
7529 | if (TARGET_PORTABLE_RUNTIME) | |
7530 | return 20; | |
7531 | ||
7532 | /* Out of reach, can use ble. */ | |
7533 | return 12; | |
7534 | } | |
7535 | ||
7536 | const char * | |
5c1d8983 | 7537 | output_indirect_call (rtx insn, rtx call_dest) |
cd0dfcc5 | 7538 | { |
7539 | rtx xoperands[1]; | |
7540 | ||
7541 | if (TARGET_64BIT) | |
7542 | { | |
7543 | xoperands[0] = call_dest; | |
7544 | output_asm_insn ("ldd 16(%0),%%r2", xoperands); | |
7545 | output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands); | |
7546 | return ""; | |
7547 | } | |
7548 | ||
7549 | /* First the special case for kernels, level 0 systems, etc. */ | |
7550 | if (TARGET_FAST_INDIRECT_CALLS) | |
7551 | return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2"; | |
7552 | ||
7553 | /* Now the normal case -- we can reach $$dyncall directly or | |
7554 | we're sure that we can get there via a long-branch stub. | |
7555 | ||
7556 | No need to check target flags as the length uniquely identifies | |
7557 | the remaining cases. */ | |
7558 | if (attr_length_indirect_call (insn) == 8) | |
7559 | return ".CALL\tARGW0=GR\n\t{bl|b,l} $$dyncall,%%r31\n\tcopy %%r31,%%r2"; | |
7560 | ||
7561 | /* Long millicode call, but we are not generating PIC or portable runtime | |
7562 | code. */ | |
7563 | if (attr_length_indirect_call (insn) == 12) | |
7564 | return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2"; | |
7565 | ||
7566 | /* Long millicode call for portable runtime. */ | |
7567 | if (attr_length_indirect_call (insn) == 20) | |
7568 | return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop"; | |
7569 | ||
7570 | /* We need a long PIC call to $$dyncall. */ | |
7571 | xoperands[0] = NULL_RTX; | |
7572 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7573 | if (TARGET_SOM || !TARGET_GAS) | |
7574 | { | |
7575 | xoperands[0] = gen_label_rtx (); | |
7576 | output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands); | |
7577 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
7578 | CODE_LABEL_NUMBER (xoperands[0])); | |
7579 | output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands); | |
7580 | } | |
7581 | else | |
7582 | { | |
7583 | output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands); | |
7584 | output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1", | |
7585 | xoperands); | |
7586 | } | |
7587 | output_asm_insn ("blr %%r0,%%r2", xoperands); | |
7588 | output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands); | |
7589 | return ""; | |
7590 | } | |
7591 | ||
7592 | /* Return the total length of the save and restore instructions needed for | |
7593 | the data linkage table pointer (i.e., the PIC register) across the call | |
7594 | instruction INSN. No-return calls do not require a save and restore. | |
7595 | In addition, we may be able to avoid the save and restore for calls | |
7596 | within the same translation unit. */ | |
7597 | ||
7598 | int | |
5c1d8983 | 7599 | attr_length_save_restore_dltp (rtx insn) |
cd0dfcc5 | 7600 | { |
7601 | if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
7602 | return 0; | |
7603 | ||
7604 | return 8; | |
7605 | } | |
7606 | ||
d6f01525 | 7607 | /* In HPUX 8.0's shared library scheme, special relocations are needed |
6d36483b | 7608 | for function labels if they might be passed to a function |
d6f01525 | 7609 | in a shared library (because shared libraries don't live in code |
44acf429 | 7610 | space), and special magic is needed to construct their address. */ |
d6f01525 | 7611 | |
7612 | void | |
5c1d8983 | 7613 | hppa_encode_label (rtx sym) |
d6f01525 | 7614 | { |
611a88e1 | 7615 | const char *str = XSTR (sym, 0); |
cccfb31e | 7616 | int len = strlen (str) + 1; |
7617 | char *newstr, *p; | |
d6f01525 | 7618 | |
cccfb31e | 7619 | p = newstr = alloca (len + 1); |
cccfb31e | 7620 | *p++ = '@'; |
7621 | strcpy (p, str); | |
74d80a9a | 7622 | |
ea52c577 | 7623 | XSTR (sym, 0) = ggc_alloc_string (newstr, len); |
d6f01525 | 7624 | } |
6d36483b | 7625 | |
7811991d | 7626 | static void |
5c1d8983 | 7627 | pa_encode_section_info (tree decl, rtx rtl, int first) |
7811991d | 7628 | { |
7629 | if (first && TEXT_SPACE_P (decl)) | |
7630 | { | |
7811991d | 7631 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
7632 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2c129d70 | 7633 | hppa_encode_label (XEXP (rtl, 0)); |
7811991d | 7634 | } |
7635 | } | |
7636 | ||
7b4a38a6 | 7637 | /* This is sort of inverse to pa_encode_section_info. */ |
7638 | ||
7639 | static const char * | |
5c1d8983 | 7640 | pa_strip_name_encoding (const char *str) |
7b4a38a6 | 7641 | { |
c0264367 | 7642 | str += (*str == '@'); |
7643 | str += (*str == '*'); | |
7644 | return str; | |
7b4a38a6 | 7645 | } |
7646 | ||
d6f01525 | 7647 | int |
5c1d8983 | 7648 | function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d6f01525 | 7649 | { |
c1b3411e | 7650 | return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0)); |
d6f01525 | 7651 | } |
f33e3942 | 7652 | |
166bf021 | 7653 | /* Returns 1 if OP is a function label involved in a simple addition |
7654 | with a constant. Used to keep certain patterns from matching | |
7655 | during instruction combination. */ | |
7656 | int | |
5c1d8983 | 7657 | is_function_label_plus_const (rtx op) |
166bf021 | 7658 | { |
7659 | /* Strip off any CONST. */ | |
7660 | if (GET_CODE (op) == CONST) | |
7661 | op = XEXP (op, 0); | |
7662 | ||
7663 | return (GET_CODE (op) == PLUS | |
7664 | && function_label_operand (XEXP (op, 0), Pmode) | |
7665 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
7666 | } | |
7667 | ||
f1752b7e | 7668 | /* Output assembly code for a thunk to FUNCTION. */ |
7669 | ||
6988553d | 7670 | static void |
5c1d8983 | 7671 | pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, |
7672 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
7673 | tree function) | |
f1752b7e | 7674 | { |
2247cc5f | 7675 | const char *fname = XSTR (XEXP (DECL_RTL (function), 0), 0); |
7676 | const char *tname = XSTR (XEXP (DECL_RTL (thunk_fndecl), 0), 0); | |
7677 | int val_14 = VAL_14_BITS_P (delta); | |
7678 | int nbytes = 0; | |
f1752b7e | 7679 | static unsigned int current_thunk_number; |
7680 | char label[16]; | |
2247cc5f | 7681 | |
7682 | ASM_OUTPUT_LABEL (file, tname); | |
7683 | fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); | |
7684 | ||
7685 | fname = (*targetm.strip_name_encoding) (fname); | |
7686 | tname = (*targetm.strip_name_encoding) (tname); | |
7687 | ||
7688 | /* Output the thunk. We know that the function is in the same | |
7689 | translation unit (i.e., the same space) as the thunk, and that | |
7690 | thunks are output after their method. Thus, we don't need an | |
7691 | external branch to reach the function. With SOM and GAS, | |
7692 | functions and thunks are effectively in different sections. | |
7693 | Thus, we can always use a IA-relative branch and the linker | |
7694 | will add a long branch stub if necessary. | |
7695 | ||
7696 | However, we have to be careful when generating PIC code on the | |
7697 | SOM port to ensure that the sequence does not transfer to an | |
7698 | import stub for the target function as this could clobber the | |
7699 | return value saved at SP-24. This would also apply to the | |
7700 | 32-bit linux port if the multi-space model is implemented. */ | |
7701 | if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
7702 | && !(flag_pic && TREE_PUBLIC (function)) | |
7703 | && (TARGET_GAS || last_address < 262132)) | |
7704 | || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
7705 | && ((targetm.have_named_sections | |
7706 | && DECL_SECTION_NAME (thunk_fndecl) != NULL | |
7707 | /* The GNU 64-bit linker has rather poor stub management. | |
7708 | So, we use a long branch from thunks that aren't in | |
7709 | the same section as the target function. */ | |
7710 | && ((!TARGET_64BIT | |
7711 | && (DECL_SECTION_NAME (thunk_fndecl) | |
7712 | != DECL_SECTION_NAME (function))) | |
7713 | || ((DECL_SECTION_NAME (thunk_fndecl) | |
7714 | == DECL_SECTION_NAME (function)) | |
7715 | && last_address < 262132))) | |
7716 | || (!targetm.have_named_sections && last_address < 262132)))) | |
7717 | { | |
7718 | if (val_14) | |
7719 | { | |
7720 | fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC | |
7721 | "(%%r26),%%r26\n", fname, delta); | |
7722 | nbytes += 8; | |
7723 | } | |
7724 | else | |
7725 | { | |
7726 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC | |
7727 | ",%%r26\n", delta); | |
7728 | fprintf (file, "\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC | |
7729 | "(%%r1),%%r26\n", fname, delta); | |
7730 | nbytes += 12; | |
7731 | } | |
7732 | } | |
7733 | else if (TARGET_64BIT) | |
7734 | { | |
7735 | /* We only have one call-clobbered scratch register, so we can't | |
7736 | make use of the delay slot if delta doesn't fit in 14 bits. */ | |
7737 | if (!val_14) | |
7738 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC | |
7739 | ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC | |
7740 | "(%%r1),%%r26\n", delta, delta); | |
7741 | ||
7742 | fprintf (file, "\tb,l .+8,%%r1\n"); | |
7743 | ||
7744 | if (TARGET_GAS) | |
7745 | { | |
7746 | fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname); | |
7747 | fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r1\n", fname); | |
7748 | } | |
7749 | else | |
7750 | { | |
7751 | int off = val_14 ? 8 : 16; | |
7752 | fprintf (file, "\taddil L'%s-%s-%d,%%r1\n", fname, tname, off); | |
7753 | fprintf (file, "\tldo R'%s-%s-%d(%%r1),%%r1\n", fname, tname, off); | |
7754 | } | |
7755 | ||
7756 | if (val_14) | |
7757 | { | |
7758 | fprintf (file, "\tbv %%r0(%%r1)\n\tldo "); | |
7759 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta); | |
7760 | nbytes += 20; | |
7761 | } | |
7762 | else | |
7763 | { | |
7764 | fprintf (file, "\tbv,n %%r0(%%r1)\n"); | |
7765 | nbytes += 24; | |
7766 | } | |
7767 | } | |
7768 | else if (TARGET_PORTABLE_RUNTIME) | |
7769 | { | |
7770 | fprintf (file, "\tldil L'%s,%%r1\n", fname); | |
7771 | fprintf (file, "\tldo R'%s(%%r1),%%r22\n", fname); | |
7772 | ||
7773 | if (val_14) | |
7774 | { | |
7775 | fprintf (file, "\tbv %%r0(%%r22)\n\tldo "); | |
7776 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta); | |
7777 | nbytes += 16; | |
7778 | } | |
7779 | else | |
7780 | { | |
7781 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC | |
7782 | ",%%r26\n", delta); | |
7783 | fprintf (file, "\tbv %%r0(%%r22)\n\tldo "); | |
7784 | fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta); | |
7785 | nbytes += 20; | |
7786 | } | |
7787 | } | |
7788 | else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
7789 | { | |
7790 | /* The function is accessible from outside this module. The only | |
7791 | way to avoid an import stub between the thunk and function is to | |
7792 | call the function directly with an indirect sequence similar to | |
7793 | that used by $$dyncall. This is possible because $$dyncall acts | |
7794 | as the import stub in an indirect call. */ | |
7795 | const char *lab; | |
7796 | ||
7797 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number); | |
7798 | lab = (*targetm.strip_name_encoding) (label); | |
7799 | ||
7800 | fprintf (file, "\taddil LT'%s,%%r19\n", lab); | |
7801 | fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab); | |
7802 | fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n"); | |
7803 | fprintf (file, "\tbb,>=,n %%r22,30,.+16\n"); | |
7804 | fprintf (file, "\tdepi 0,31,2,%%r22\n"); | |
7805 | fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n"); | |
7806 | fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n"); | |
7807 | if (!val_14) | |
7808 | { | |
7809 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC | |
7810 | ",%%r26\n", delta); | |
7811 | nbytes += 4; | |
7812 | } | |
7813 | if (TARGET_PA_20) | |
7814 | { | |
7815 | fprintf (file, "\tbve (%%r22)\n\tldo "); | |
7816 | nbytes += 36; | |
7817 | } | |
7818 | else | |
f1752b7e | 7819 | { |
ee376abe | 7820 | if (TARGET_NO_SPACE_REGS) |
2247cc5f | 7821 | { |
7822 | fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo "); | |
7823 | nbytes += 36; | |
7824 | } | |
ee376abe | 7825 | else |
7826 | { | |
6454616d | 7827 | fprintf (file, "\tldsid (%%sr0,%%r22),%%r21\n"); |
2247cc5f | 7828 | fprintf (file, "\tmtsp %%r21,%%sr0\n"); |
ee376abe | 7829 | fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo "); |
2247cc5f | 7830 | nbytes += 44; |
ee376abe | 7831 | } |
2247cc5f | 7832 | } |
7833 | ||
7834 | if (val_14) | |
7835 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta); | |
7836 | else | |
7837 | fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta); | |
7838 | } | |
7839 | else if (flag_pic) | |
7840 | { | |
7841 | if (TARGET_PA_20) | |
7842 | fprintf (file, "\tb,l .+8,%%r1\n"); | |
7843 | else | |
7844 | fprintf (file, "\tbl .+8,%%r1\n"); | |
7845 | ||
7846 | if (TARGET_SOM || !TARGET_GAS) | |
7847 | { | |
7848 | fprintf (file, "\taddil L'%s-%s-8,%%r1\n", fname, tname); | |
7849 | fprintf (file, "\tldo R'%s-%s-8(%%r1),%%r22\n", fname, tname); | |
7850 | } | |
7851 | else | |
7852 | { | |
7853 | fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname); | |
7854 | fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r22\n", fname); | |
7855 | } | |
7856 | ||
7857 | if (val_14) | |
7858 | { | |
7859 | fprintf (file, "\tbv %%r0(%%r22)\n\tldo "); | |
4840a03a | 7860 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta); |
2247cc5f | 7861 | nbytes += 20; |
f1752b7e | 7862 | } |
7863 | else | |
2247cc5f | 7864 | { |
7865 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC | |
7866 | ",%%r26\n", delta); | |
7867 | fprintf (file, "\tbv %%r0(%%r22)\n\tldo "); | |
7868 | fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta); | |
7869 | nbytes += 24; | |
7870 | } | |
f1752b7e | 7871 | } |
7872 | else | |
7873 | { | |
2247cc5f | 7874 | if (!val_14) |
7875 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC ",%%r26\n", delta); | |
7876 | ||
7877 | fprintf (file, "\tldil L'%s,%%r22\n", fname); | |
7878 | fprintf (file, "\tbe R'%s(%%sr4,%%r22)\n\tldo ", fname); | |
7879 | ||
7880 | if (val_14) | |
f1752b7e | 7881 | { |
2247cc5f | 7882 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta); |
7883 | nbytes += 12; | |
f1752b7e | 7884 | } |
7885 | else | |
2247cc5f | 7886 | { |
7887 | fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta); | |
7888 | nbytes += 16; | |
7889 | } | |
f1752b7e | 7890 | } |
2247cc5f | 7891 | |
f1752b7e | 7892 | fprintf (file, "\t.EXIT\n\t.PROCEND\n"); |
2247cc5f | 7893 | |
7894 | if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
f1752b7e | 7895 | { |
7896 | data_section (); | |
7897 | fprintf (file, "\t.align 4\n"); | |
2247cc5f | 7898 | ASM_OUTPUT_LABEL (file, label); |
7899 | fprintf (file, "\t.word P'%s\n", fname); | |
f1752b7e | 7900 | function_section (thunk_fndecl); |
7901 | } | |
2247cc5f | 7902 | |
f1752b7e | 7903 | current_thunk_number++; |
2247cc5f | 7904 | nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) |
7905 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
7906 | last_address += nbytes; | |
7907 | update_total_code_bytes (nbytes); | |
f1752b7e | 7908 | } |
7909 | ||
805e22b2 | 7910 | /* Only direct calls to static functions are allowed to be sibling (tail) |
7911 | call optimized. | |
7912 | ||
7913 | This restriction is necessary because some linker generated stubs will | |
7914 | store return pointers into rp' in some cases which might clobber a | |
7915 | live value already in rp'. | |
7916 | ||
7917 | In a sibcall the current function and the target function share stack | |
7918 | space. Thus if the path to the current function and the path to the | |
7919 | target function save a value in rp', they save the value into the | |
7920 | same stack slot, which has undesirable consequences. | |
7921 | ||
7922 | Because of the deferred binding nature of shared libraries any function | |
7923 | with external scope could be in a different load module and thus require | |
7924 | rp' to be saved when calling that function. So sibcall optimizations | |
7925 | can only be safe for static function. | |
7926 | ||
7927 | Note that GCC never needs return value relocations, so we don't have to | |
7928 | worry about static calls with return value relocations (which require | |
7929 | saving rp'). | |
7930 | ||
7931 | It is safe to perform a sibcall optimization when the target function | |
7932 | will never return. */ | |
7933 | static bool | |
5c1d8983 | 7934 | pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
805e22b2 | 7935 | { |
f62b73b6 | 7936 | /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in |
7937 | single subspace mode and the call is not indirect. As far as I know, | |
7938 | there is no operating system support for the multiple subspace mode. | |
7939 | It might be possible to support indirect calls if we didn't use | |
7940 | $$dyncall (see the indirect sequence generated in output_call). */ | |
7941 | if (TARGET_ELF32) | |
7942 | return (decl != NULL_TREE); | |
7943 | ||
7944 | /* Sibcalls are not ok because the arg pointer register is not a fixed | |
2cecd772 | 7945 | register. This prevents the sibcall optimization from occurring. In |
f62b73b6 | 7946 | addition, there are problems with stub placement using GNU ld. This |
7947 | is because a normal sibcall branch uses a 17-bit relocation while | |
7948 | a regular call branch uses a 22-bit relocation. As a result, more | |
7949 | care needs to be taken in the placement of long-branch stubs. */ | |
7950 | if (TARGET_64BIT) | |
7951 | return false; | |
7952 | ||
805e22b2 | 7953 | return (decl |
f62b73b6 | 7954 | && !TARGET_PORTABLE_RUNTIME |
7955 | && !TREE_PUBLIC (decl)); | |
805e22b2 | 7956 | } |
7957 | ||
37580c80 | 7958 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
7959 | use in fmpyadd instructions. */ | |
4ed6ee50 | 7960 | int |
5c1d8983 | 7961 | fmpyaddoperands (rtx *operands) |
4ed6ee50 | 7962 | { |
201f01e9 | 7963 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 7964 | |
ab449421 | 7965 | /* Must be a floating point mode. */ |
7966 | if (mode != SFmode && mode != DFmode) | |
7967 | return 0; | |
7968 | ||
4ed6ee50 | 7969 | /* All modes must be the same. */ |
201f01e9 | 7970 | if (! (mode == GET_MODE (operands[1]) |
7971 | && mode == GET_MODE (operands[2]) | |
7972 | && mode == GET_MODE (operands[3]) | |
7973 | && mode == GET_MODE (operands[4]) | |
7974 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 7975 | return 0; |
7976 | ||
ab449421 | 7977 | /* All operands must be registers. */ |
7978 | if (! (GET_CODE (operands[1]) == REG | |
7979 | && GET_CODE (operands[2]) == REG | |
7980 | && GET_CODE (operands[3]) == REG | |
7981 | && GET_CODE (operands[4]) == REG | |
7982 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 7983 | return 0; |
7984 | ||
37580c80 | 7985 | /* Only 2 real operands to the addition. One of the input operands must |
7986 | be the same as the output operand. */ | |
4ed6ee50 | 7987 | if (! rtx_equal_p (operands[3], operands[4]) |
7988 | && ! rtx_equal_p (operands[3], operands[5])) | |
7989 | return 0; | |
7990 | ||
7991 | /* Inout operand of add can not conflict with any operands from multiply. */ | |
7992 | if (rtx_equal_p (operands[3], operands[0]) | |
7993 | || rtx_equal_p (operands[3], operands[1]) | |
7994 | || rtx_equal_p (operands[3], operands[2])) | |
7995 | return 0; | |
7996 | ||
7997 | /* multiply can not feed into addition operands. */ | |
7998 | if (rtx_equal_p (operands[4], operands[0]) | |
7999 | || rtx_equal_p (operands[5], operands[0])) | |
8000 | return 0; | |
8001 | ||
ab449421 | 8002 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8003 | if (mode == SFmode | |
bac38c40 | 8004 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8005 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8006 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8007 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8008 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8009 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 8010 | return 0; |
8011 | ||
4ed6ee50 | 8012 | /* Passed. Operands are suitable for fmpyadd. */ |
8013 | return 1; | |
8014 | } | |
8015 | ||
de419443 | 8016 | #if !defined(USE_COLLECT2) |
8017 | static void | |
5c1d8983 | 8018 | pa_asm_out_constructor (rtx symbol, int priority) |
de419443 | 8019 | { |
8020 | if (!function_label_operand (symbol, VOIDmode)) | |
8021 | hppa_encode_label (symbol); | |
8022 | ||
8023 | #ifdef CTORS_SECTION_ASM_OP | |
8024 | default_ctor_section_asm_out_constructor (symbol, priority); | |
8025 | #else | |
8026 | # ifdef TARGET_ASM_NAMED_SECTION | |
8027 | default_named_section_asm_out_constructor (symbol, priority); | |
8028 | # else | |
8029 | default_stabs_asm_out_constructor (symbol, priority); | |
8030 | # endif | |
8031 | #endif | |
8032 | } | |
8033 | ||
8034 | static void | |
5c1d8983 | 8035 | pa_asm_out_destructor (rtx symbol, int priority) |
de419443 | 8036 | { |
8037 | if (!function_label_operand (symbol, VOIDmode)) | |
8038 | hppa_encode_label (symbol); | |
8039 | ||
8040 | #ifdef DTORS_SECTION_ASM_OP | |
8041 | default_dtor_section_asm_out_destructor (symbol, priority); | |
8042 | #else | |
8043 | # ifdef TARGET_ASM_NAMED_SECTION | |
8044 | default_named_section_asm_out_destructor (symbol, priority); | |
8045 | # else | |
8046 | default_stabs_asm_out_destructor (symbol, priority); | |
8047 | # endif | |
8048 | #endif | |
8049 | } | |
8050 | #endif | |
8051 | ||
37580c80 | 8052 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
8053 | use in fmpysub instructions. */ | |
4ed6ee50 | 8054 | int |
5c1d8983 | 8055 | fmpysuboperands (rtx *operands) |
4ed6ee50 | 8056 | { |
201f01e9 | 8057 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 8058 | |
ab449421 | 8059 | /* Must be a floating point mode. */ |
8060 | if (mode != SFmode && mode != DFmode) | |
8061 | return 0; | |
8062 | ||
4ed6ee50 | 8063 | /* All modes must be the same. */ |
201f01e9 | 8064 | if (! (mode == GET_MODE (operands[1]) |
8065 | && mode == GET_MODE (operands[2]) | |
8066 | && mode == GET_MODE (operands[3]) | |
8067 | && mode == GET_MODE (operands[4]) | |
8068 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 8069 | return 0; |
8070 | ||
ab449421 | 8071 | /* All operands must be registers. */ |
8072 | if (! (GET_CODE (operands[1]) == REG | |
8073 | && GET_CODE (operands[2]) == REG | |
8074 | && GET_CODE (operands[3]) == REG | |
8075 | && GET_CODE (operands[4]) == REG | |
8076 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 8077 | return 0; |
8078 | ||
37580c80 | 8079 | /* Only 2 real operands to the subtraction. Subtraction is not a commutative |
8080 | operation, so operands[4] must be the same as operand[3]. */ | |
4ed6ee50 | 8081 | if (! rtx_equal_p (operands[3], operands[4])) |
8082 | return 0; | |
8083 | ||
8084 | /* multiply can not feed into subtraction. */ | |
37580c80 | 8085 | if (rtx_equal_p (operands[5], operands[0])) |
4ed6ee50 | 8086 | return 0; |
8087 | ||
37580c80 | 8088 | /* Inout operand of sub can not conflict with any operands from multiply. */ |
4ed6ee50 | 8089 | if (rtx_equal_p (operands[3], operands[0]) |
8090 | || rtx_equal_p (operands[3], operands[1]) | |
8091 | || rtx_equal_p (operands[3], operands[2])) | |
8092 | return 0; | |
8093 | ||
ab449421 | 8094 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8095 | if (mode == SFmode | |
bac38c40 | 8096 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8097 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8098 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8099 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8100 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8101 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 8102 | return 0; |
8103 | ||
4ed6ee50 | 8104 | /* Passed. Operands are suitable for fmpysub. */ |
8105 | return 1; | |
8106 | } | |
8107 | ||
89f29d73 | 8108 | int |
5c1d8983 | 8109 | plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
89f29d73 | 8110 | { |
8111 | return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR | |
8112 | || GET_CODE (op) == IOR); | |
8113 | } | |
6720f95e | 8114 | |
8115 | /* Return 1 if the given constant is 2, 4, or 8. These are the valid | |
8116 | constants for shadd instructions. */ | |
7d27e4c9 | 8117 | static int |
5c1d8983 | 8118 | shadd_constant_p (int val) |
6720f95e | 8119 | { |
8120 | if (val == 2 || val == 4 || val == 8) | |
8121 | return 1; | |
8122 | else | |
8123 | return 0; | |
8124 | } | |
3a16146d | 8125 | |
8126 | /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are | |
8127 | the valid constant for shadd instructions. */ | |
8128 | int | |
5c1d8983 | 8129 | shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
3a16146d | 8130 | { |
8131 | return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op))); | |
8132 | } | |
5fbd5940 | 8133 | |
dbd3d89d | 8134 | /* Return 1 if OP is valid as a base or index register in a |
8135 | REG+REG address. */ | |
42819d4e | 8136 | |
8137 | int | |
dbd3d89d | 8138 | borx_reg_operand (rtx op, enum machine_mode mode) |
42819d4e | 8139 | { |
dbd3d89d | 8140 | if (GET_CODE (op) != REG) |
21f3ee9c | 8141 | return 0; |
8142 | ||
dbd3d89d | 8143 | /* We must reject virtual registers as the only expressions that |
8144 | can be instantiated are REG and REG+CONST. */ | |
8145 | if (op == virtual_incoming_args_rtx | |
8146 | || op == virtual_stack_vars_rtx | |
8147 | || op == virtual_stack_dynamic_rtx | |
8148 | || op == virtual_outgoing_args_rtx | |
8149 | || op == virtual_cfa_rtx) | |
8150 | return 0; | |
42819d4e | 8151 | |
21f3ee9c | 8152 | /* While it's always safe to index off the frame pointer, it's not |
dbd3d89d | 8153 | profitable to do so when the frame pointer is being eliminated. */ |
8154 | if (!reload_completed | |
8155 | && flag_omit_frame_pointer | |
8156 | && !current_function_calls_alloca | |
8157 | && op == frame_pointer_rtx) | |
8158 | return 0; | |
42819d4e | 8159 | |
dbd3d89d | 8160 | return register_operand (op, mode); |
42819d4e | 8161 | } |
8162 | ||
51987f90 | 8163 | /* Return 1 if this operand is anything other than a hard register. */ |
8164 | ||
8165 | int | |
5c1d8983 | 8166 | non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
51987f90 | 8167 | { |
8168 | return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER); | |
8169 | } | |
8170 | ||
5fbd5940 | 8171 | /* Return 1 if INSN branches forward. Should be using insn_addresses |
6dc3b0d9 | 8172 | to avoid walking through all the insns... */ |
7d27e4c9 | 8173 | static int |
5c1d8983 | 8174 | forward_branch_p (rtx insn) |
5fbd5940 | 8175 | { |
8176 | rtx label = JUMP_LABEL (insn); | |
8177 | ||
8178 | while (insn) | |
8179 | { | |
8180 | if (insn == label) | |
8181 | break; | |
8182 | else | |
8183 | insn = NEXT_INSN (insn); | |
8184 | } | |
8185 | ||
8186 | return (insn == label); | |
8187 | } | |
8188 | ||
29a4502c | 8189 | /* Return 1 if OP is an equality comparison, else return 0. */ |
8190 | int | |
5c1d8983 | 8191 | eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
29a4502c | 8192 | { |
8193 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
8194 | } | |
8195 | ||
8196 | /* Return 1 if OP is an operator suitable for use in a movb instruction. */ | |
8197 | int | |
5c1d8983 | 8198 | movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
29a4502c | 8199 | { |
8200 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE | |
8201 | || GET_CODE (op) == LT || GET_CODE (op) == GE); | |
8202 | } | |
8203 | ||
d6686e21 | 8204 | /* Return 1 if INSN is in the delay slot of a call instruction. */ |
8205 | int | |
5c1d8983 | 8206 | jump_in_call_delay (rtx insn) |
d6686e21 | 8207 | { |
8208 | ||
8209 | if (GET_CODE (insn) != JUMP_INSN) | |
8210 | return 0; | |
8211 | ||
8212 | if (PREV_INSN (insn) | |
8213 | && PREV_INSN (PREV_INSN (insn)) | |
ece0fa59 | 8214 | && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN) |
d6686e21 | 8215 | { |
ece0fa59 | 8216 | rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn))); |
d6686e21 | 8217 | |
8218 | return (GET_CODE (PATTERN (test_insn)) == SEQUENCE | |
8219 | && XVECEXP (PATTERN (test_insn), 0, 1) == insn); | |
8220 | ||
8221 | } | |
8222 | else | |
8223 | return 0; | |
8224 | } | |
3b1e673e | 8225 | |
546a40bd | 8226 | /* Output an unconditional move and branch insn. */ |
8227 | ||
611a88e1 | 8228 | const char * |
5c1d8983 | 8229 | output_parallel_movb (rtx *operands, int length) |
546a40bd | 8230 | { |
8231 | /* These are the cases in which we win. */ | |
8232 | if (length == 4) | |
8233 | return "mov%I1b,tr %1,%0,%2"; | |
8234 | ||
8235 | /* None of these cases wins, but they don't lose either. */ | |
8236 | if (dbr_sequence_length () == 0) | |
8237 | { | |
8238 | /* Nothing in the delay slot, fake it by putting the combined | |
8239 | insn (the copy or add) in the delay slot of a bl. */ | |
8240 | if (GET_CODE (operands[1]) == CONST_INT) | |
5a811d43 | 8241 | return "b %2\n\tldi %1,%0"; |
546a40bd | 8242 | else |
5a811d43 | 8243 | return "b %2\n\tcopy %1,%0"; |
546a40bd | 8244 | } |
8245 | else | |
8246 | { | |
8247 | /* Something in the delay slot, but we've got a long branch. */ | |
8248 | if (GET_CODE (operands[1]) == CONST_INT) | |
5a811d43 | 8249 | return "ldi %1,%0\n\tb %2"; |
546a40bd | 8250 | else |
5a811d43 | 8251 | return "copy %1,%0\n\tb %2"; |
546a40bd | 8252 | } |
8253 | } | |
8254 | ||
8255 | /* Output an unconditional add and branch insn. */ | |
8256 | ||
611a88e1 | 8257 | const char * |
5c1d8983 | 8258 | output_parallel_addb (rtx *operands, int length) |
546a40bd | 8259 | { |
8260 | /* To make life easy we want operand0 to be the shared input/output | |
8261 | operand and operand1 to be the readonly operand. */ | |
8262 | if (operands[0] == operands[1]) | |
8263 | operands[1] = operands[2]; | |
8264 | ||
8265 | /* These are the cases in which we win. */ | |
8266 | if (length == 4) | |
8267 | return "add%I1b,tr %1,%0,%3"; | |
8268 | ||
8269 | /* None of these cases win, but they don't lose either. */ | |
8270 | if (dbr_sequence_length () == 0) | |
8271 | { | |
8272 | /* Nothing in the delay slot, fake it by putting the combined | |
8273 | insn (the copy or add) in the delay slot of a bl. */ | |
5a811d43 | 8274 | return "b %3\n\tadd%I1 %1,%0,%0"; |
546a40bd | 8275 | } |
8276 | else | |
8277 | { | |
8278 | /* Something in the delay slot, but we've got a long branch. */ | |
5a811d43 | 8279 | return "add%I1 %1,%0,%0\n\tb %3"; |
546a40bd | 8280 | } |
8281 | } | |
8282 | ||
7c5101fc | 8283 | /* Return nonzero if INSN (a jump insn) immediately follows a call |
8284 | to a named function. This is used to avoid filling the delay slot | |
8285 | of the jump since it can usually be eliminated by modifying RP in | |
8286 | the delay slot of the call. */ | |
9840d99d | 8287 | |
7d27e4c9 | 8288 | int |
5c1d8983 | 8289 | following_call (rtx insn) |
546a40bd | 8290 | { |
ed1b0769 | 8291 | if (! TARGET_JUMP_IN_DELAY) |
1b6f11e2 | 8292 | return 0; |
8293 | ||
546a40bd | 8294 | /* Find the previous real insn, skipping NOTEs. */ |
8295 | insn = PREV_INSN (insn); | |
8296 | while (insn && GET_CODE (insn) == NOTE) | |
8297 | insn = PREV_INSN (insn); | |
8298 | ||
8299 | /* Check for CALL_INSNs and millicode calls. */ | |
8300 | if (insn | |
1d2e016c | 8301 | && ((GET_CODE (insn) == CALL_INSN |
8302 | && get_attr_type (insn) != TYPE_DYNCALL) | |
546a40bd | 8303 | || (GET_CODE (insn) == INSN |
8304 | && GET_CODE (PATTERN (insn)) != SEQUENCE | |
8305 | && GET_CODE (PATTERN (insn)) != USE | |
8306 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8307 | && get_attr_type (insn) == TYPE_MILLI))) | |
8308 | return 1; | |
8309 | ||
8310 | return 0; | |
8311 | } | |
8312 | ||
3b1e673e | 8313 | /* We use this hook to perform a PA specific optimization which is difficult |
8314 | to do in earlier passes. | |
8315 | ||
8316 | We want the delay slots of branches within jump tables to be filled. | |
8317 | None of the compiler passes at the moment even has the notion that a | |
8318 | PA jump table doesn't contain addresses, but instead contains actual | |
8319 | instructions! | |
8320 | ||
8321 | Because we actually jump into the table, the addresses of each entry | |
01cc3b75 | 8322 | must stay constant in relation to the beginning of the table (which |
3b1e673e | 8323 | itself must stay constant relative to the instruction to jump into |
8324 | it). I don't believe we can guarantee earlier passes of the compiler | |
8325 | will adhere to those rules. | |
8326 | ||
8327 | So, late in the compilation process we find all the jump tables, and | |
8328 | expand them into real code -- eg each entry in the jump table vector | |
8329 | will get an appropriate label followed by a jump to the final target. | |
8330 | ||
8331 | Reorg and the final jump pass can then optimize these branches and | |
8332 | fill their delay slots. We end up with smaller, more efficient code. | |
8333 | ||
9840d99d | 8334 | The jump instructions within the table are special; we must be able |
3b1e673e | 8335 | to identify them during assembly output (if the jumps don't get filled |
8336 | we need to emit a nop rather than nullifying the delay slot)). We | |
b932f66c | 8337 | identify jumps in switch tables by using insns with the attribute |
8338 | type TYPE_BTABLE_BRANCH. | |
9239127b | 8339 | |
8340 | We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB | |
8341 | insns. This serves two purposes, first it prevents jump.c from | |
8342 | noticing that the last N entries in the table jump to the instruction | |
8343 | immediately after the table and deleting the jumps. Second, those | |
8344 | insns mark where we should emit .begin_brtab and .end_brtab directives | |
8345 | when using GAS (allows for better link time optimizations). */ | |
3b1e673e | 8346 | |
2efea8c0 | 8347 | static void |
5c1d8983 | 8348 | pa_reorg (void) |
3b1e673e | 8349 | { |
8350 | rtx insn; | |
8351 | ||
2efea8c0 | 8352 | remove_useless_addtr_insns (1); |
3d457930 | 8353 | |
342aabd9 | 8354 | if (pa_cpu < PROCESSOR_8000) |
2efea8c0 | 8355 | pa_combine_instructions (); |
342aabd9 | 8356 | |
bd49d362 | 8357 | |
3d457930 | 8358 | /* This is fairly cheap, so always run it if optimizing. */ |
a66555b2 | 8359 | if (optimize > 0 && !TARGET_BIG_SWITCH) |
3b1e673e | 8360 | { |
b41266d4 | 8361 | /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */ |
2efea8c0 | 8362 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
3b1e673e | 8363 | { |
b932f66c | 8364 | rtx pattern, tmp, location, label; |
3b1e673e | 8365 | unsigned int length, i; |
8366 | ||
b41266d4 | 8367 | /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */ |
3b1e673e | 8368 | if (GET_CODE (insn) != JUMP_INSN |
b41266d4 | 8369 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8370 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
3b1e673e | 8371 | continue; |
8372 | ||
9239127b | 8373 | /* Emit marker for the beginning of the branch table. */ |
8374 | emit_insn_before (gen_begin_brtab (), insn); | |
f9333726 | 8375 | |
3b1e673e | 8376 | pattern = PATTERN (insn); |
8377 | location = PREV_INSN (insn); | |
b41266d4 | 8378 | length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC); |
f9333726 | 8379 | |
3b1e673e | 8380 | for (i = 0; i < length; i++) |
8381 | { | |
a66555b2 | 8382 | /* Emit a label before each jump to keep jump.c from |
8383 | removing this code. */ | |
8384 | tmp = gen_label_rtx (); | |
8385 | LABEL_NUSES (tmp) = 1; | |
8386 | emit_label_after (tmp, location); | |
8387 | location = NEXT_INSN (location); | |
8388 | ||
b41266d4 | 8389 | if (GET_CODE (pattern) == ADDR_VEC) |
b932f66c | 8390 | label = XEXP (XVECEXP (pattern, 0, i), 0); |
b41266d4 | 8391 | else |
b932f66c | 8392 | label = XEXP (XVECEXP (pattern, 1, i), 0); |
8393 | ||
8394 | tmp = gen_short_jump (label); | |
8395 | ||
8396 | /* Emit the jump itself. */ | |
8397 | tmp = emit_jump_insn_after (tmp, location); | |
8398 | JUMP_LABEL (tmp) = label; | |
8399 | LABEL_NUSES (label)++; | |
8400 | location = NEXT_INSN (location); | |
3b1e673e | 8401 | |
8402 | /* Emit a BARRIER after the jump. */ | |
3b1e673e | 8403 | emit_barrier_after (location); |
3b1e673e | 8404 | location = NEXT_INSN (location); |
8405 | } | |
f9333726 | 8406 | |
9239127b | 8407 | /* Emit marker for the end of the branch table. */ |
8408 | emit_insn_before (gen_end_brtab (), location); | |
8409 | location = NEXT_INSN (location); | |
8410 | emit_barrier_after (location); | |
a66555b2 | 8411 | |
b41266d4 | 8412 | /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */ |
3b1e673e | 8413 | delete_insn (insn); |
8414 | } | |
8415 | } | |
9239127b | 8416 | else |
f9333726 | 8417 | { |
b932f66c | 8418 | /* Still need brtab marker insns. FIXME: the presence of these |
8419 | markers disables output of the branch table to readonly memory, | |
8420 | and any alignment directives that might be needed. Possibly, | |
8421 | the begin_brtab insn should be output before the label for the | |
8422 | table. This doesn matter at the moment since the tables are | |
8423 | always output in the text section. */ | |
2efea8c0 | 8424 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
f9333726 | 8425 | { |
8426 | /* Find an ADDR_VEC insn. */ | |
8427 | if (GET_CODE (insn) != JUMP_INSN | |
b41266d4 | 8428 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8429 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
f9333726 | 8430 | continue; |
8431 | ||
8432 | /* Now generate markers for the beginning and end of the | |
ad87de1e | 8433 | branch table. */ |
f9333726 | 8434 | emit_insn_before (gen_begin_brtab (), insn); |
8435 | emit_insn_after (gen_end_brtab (), insn); | |
8436 | } | |
8437 | } | |
d3287673 | 8438 | } |
bd49d362 | 8439 | |
8440 | /* The PA has a number of odd instructions which can perform multiple | |
8441 | tasks at once. On first generation PA machines (PA1.0 and PA1.1) | |
8442 | it may be profitable to combine two instructions into one instruction | |
8443 | with two outputs. It's not profitable PA2.0 machines because the | |
8444 | two outputs would take two slots in the reorder buffers. | |
8445 | ||
8446 | This routine finds instructions which can be combined and combines | |
8447 | them. We only support some of the potential combinations, and we | |
8448 | only try common ways to find suitable instructions. | |
8449 | ||
8450 | * addb can add two registers or a register and a small integer | |
8451 | and jump to a nearby (+-8k) location. Normally the jump to the | |
8452 | nearby location is conditional on the result of the add, but by | |
8453 | using the "true" condition we can make the jump unconditional. | |
8454 | Thus addb can perform two independent operations in one insn. | |
8455 | ||
8456 | * movb is similar to addb in that it can perform a reg->reg | |
8457 | or small immediate->reg copy and jump to a nearby (+-8k location). | |
8458 | ||
8459 | * fmpyadd and fmpysub can perform a FP multiply and either an | |
8460 | FP add or FP sub if the operands of the multiply and add/sub are | |
8461 | independent (there are other minor restrictions). Note both | |
8462 | the fmpy and fadd/fsub can in theory move to better spots according | |
8463 | to data dependencies, but for now we require the fmpy stay at a | |
8464 | fixed location. | |
8465 | ||
8466 | * Many of the memory operations can perform pre & post updates | |
8467 | of index registers. GCC's pre/post increment/decrement addressing | |
8468 | is far too simple to take advantage of all the possibilities. This | |
8469 | pass may not be suitable since those insns may not be independent. | |
8470 | ||
8471 | * comclr can compare two ints or an int and a register, nullify | |
8472 | the following instruction and zero some other register. This | |
8473 | is more difficult to use as it's harder to find an insn which | |
8474 | will generate a comclr than finding something like an unconditional | |
8475 | branch. (conditional moves & long branches create comclr insns). | |
8476 | ||
8477 | * Most arithmetic operations can conditionally skip the next | |
8478 | instruction. They can be viewed as "perform this operation | |
8479 | and conditionally jump to this nearby location" (where nearby | |
8480 | is an insns away). These are difficult to use due to the | |
8481 | branch length restrictions. */ | |
8482 | ||
7d27e4c9 | 8483 | static void |
5c1d8983 | 8484 | pa_combine_instructions (void) |
bd49d362 | 8485 | { |
8486 | rtx anchor, new; | |
8487 | ||
8488 | /* This can get expensive since the basic algorithm is on the | |
8489 | order of O(n^2) (or worse). Only do it for -O2 or higher | |
ad87de1e | 8490 | levels of optimization. */ |
bd49d362 | 8491 | if (optimize < 2) |
8492 | return; | |
8493 | ||
8494 | /* Walk down the list of insns looking for "anchor" insns which | |
8495 | may be combined with "floating" insns. As the name implies, | |
8496 | "anchor" instructions don't move, while "floating" insns may | |
8497 | move around. */ | |
ad851752 | 8498 | new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX)); |
bd49d362 | 8499 | new = make_insn_raw (new); |
8500 | ||
8501 | for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor)) | |
8502 | { | |
8503 | enum attr_pa_combine_type anchor_attr; | |
8504 | enum attr_pa_combine_type floater_attr; | |
8505 | ||
8506 | /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs. | |
8507 | Also ignore any special USE insns. */ | |
7d27e4c9 | 8508 | if ((GET_CODE (anchor) != INSN |
bd49d362 | 8509 | && GET_CODE (anchor) != JUMP_INSN |
7d27e4c9 | 8510 | && GET_CODE (anchor) != CALL_INSN) |
bd49d362 | 8511 | || GET_CODE (PATTERN (anchor)) == USE |
8512 | || GET_CODE (PATTERN (anchor)) == CLOBBER | |
8513 | || GET_CODE (PATTERN (anchor)) == ADDR_VEC | |
8514 | || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC) | |
8515 | continue; | |
8516 | ||
8517 | anchor_attr = get_attr_pa_combine_type (anchor); | |
8518 | /* See if anchor is an insn suitable for combination. */ | |
8519 | if (anchor_attr == PA_COMBINE_TYPE_FMPY | |
8520 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8521 | || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
8522 | && ! forward_branch_p (anchor))) | |
8523 | { | |
8524 | rtx floater; | |
8525 | ||
8526 | for (floater = PREV_INSN (anchor); | |
8527 | floater; | |
8528 | floater = PREV_INSN (floater)) | |
8529 | { | |
8530 | if (GET_CODE (floater) == NOTE | |
8531 | || (GET_CODE (floater) == INSN | |
8532 | && (GET_CODE (PATTERN (floater)) == USE | |
8533 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
8534 | continue; | |
8535 | ||
8536 | /* Anything except a regular INSN will stop our search. */ | |
8537 | if (GET_CODE (floater) != INSN | |
8538 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
8539 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
8540 | { | |
8541 | floater = NULL_RTX; | |
8542 | break; | |
8543 | } | |
8544 | ||
8545 | /* See if FLOATER is suitable for combination with the | |
8546 | anchor. */ | |
8547 | floater_attr = get_attr_pa_combine_type (floater); | |
8548 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
8549 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
8550 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8551 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
8552 | { | |
8553 | /* If ANCHOR and FLOATER can be combined, then we're | |
8554 | done with this pass. */ | |
8555 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8556 | SET_DEST (PATTERN (floater)), | |
8557 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
8558 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
8559 | break; | |
8560 | } | |
8561 | ||
8562 | else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
8563 | && floater_attr == PA_COMBINE_TYPE_ADDMOVE) | |
8564 | { | |
8565 | if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS) | |
8566 | { | |
8567 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8568 | SET_DEST (PATTERN (floater)), | |
8569 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
8570 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
8571 | break; | |
8572 | } | |
8573 | else | |
8574 | { | |
8575 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8576 | SET_DEST (PATTERN (floater)), | |
8577 | SET_SRC (PATTERN (floater)), | |
8578 | SET_SRC (PATTERN (floater)))) | |
8579 | break; | |
8580 | } | |
8581 | } | |
8582 | } | |
8583 | ||
8584 | /* If we didn't find anything on the backwards scan try forwards. */ | |
8585 | if (!floater | |
8586 | && (anchor_attr == PA_COMBINE_TYPE_FMPY | |
8587 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB)) | |
8588 | { | |
8589 | for (floater = anchor; floater; floater = NEXT_INSN (floater)) | |
8590 | { | |
8591 | if (GET_CODE (floater) == NOTE | |
8592 | || (GET_CODE (floater) == INSN | |
8593 | && (GET_CODE (PATTERN (floater)) == USE | |
8594 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
9840d99d | 8595 | |
bd49d362 | 8596 | continue; |
8597 | ||
8598 | /* Anything except a regular INSN will stop our search. */ | |
8599 | if (GET_CODE (floater) != INSN | |
8600 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
8601 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
8602 | { | |
8603 | floater = NULL_RTX; | |
8604 | break; | |
8605 | } | |
8606 | ||
8607 | /* See if FLOATER is suitable for combination with the | |
8608 | anchor. */ | |
8609 | floater_attr = get_attr_pa_combine_type (floater); | |
8610 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
8611 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
8612 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8613 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
8614 | { | |
8615 | /* If ANCHOR and FLOATER can be combined, then we're | |
8616 | done with this pass. */ | |
8617 | if (pa_can_combine_p (new, anchor, floater, 1, | |
8618 | SET_DEST (PATTERN (floater)), | |
ea52c577 | 8619 | XEXP (SET_SRC (PATTERN (floater)), |
8620 | 0), | |
8621 | XEXP (SET_SRC (PATTERN (floater)), | |
8622 | 1))) | |
bd49d362 | 8623 | break; |
8624 | } | |
8625 | } | |
8626 | } | |
8627 | ||
8628 | /* FLOATER will be nonzero if we found a suitable floating | |
8629 | insn for combination with ANCHOR. */ | |
8630 | if (floater | |
8631 | && (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8632 | || anchor_attr == PA_COMBINE_TYPE_FMPY)) | |
8633 | { | |
8634 | /* Emit the new instruction and delete the old anchor. */ | |
7014838c | 8635 | emit_insn_before (gen_rtx_PARALLEL |
8636 | (VOIDmode, | |
8637 | gen_rtvec (2, PATTERN (anchor), | |
8638 | PATTERN (floater))), | |
8639 | anchor); | |
8640 | ||
bd49d362 | 8641 | PUT_CODE (anchor, NOTE); |
8642 | NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED; | |
8643 | NOTE_SOURCE_FILE (anchor) = 0; | |
8644 | ||
8645 | /* Emit a special USE insn for FLOATER, then delete | |
8646 | the floating insn. */ | |
ad851752 | 8647 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 8648 | delete_insn (floater); |
8649 | ||
8650 | continue; | |
8651 | } | |
8652 | else if (floater | |
8653 | && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH) | |
8654 | { | |
8655 | rtx temp; | |
8656 | /* Emit the new_jump instruction and delete the old anchor. */ | |
7014838c | 8657 | temp |
8658 | = emit_jump_insn_before (gen_rtx_PARALLEL | |
8659 | (VOIDmode, | |
8660 | gen_rtvec (2, PATTERN (anchor), | |
8661 | PATTERN (floater))), | |
8662 | anchor); | |
8663 | ||
bd49d362 | 8664 | JUMP_LABEL (temp) = JUMP_LABEL (anchor); |
8665 | PUT_CODE (anchor, NOTE); | |
8666 | NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED; | |
8667 | NOTE_SOURCE_FILE (anchor) = 0; | |
8668 | ||
8669 | /* Emit a special USE insn for FLOATER, then delete | |
8670 | the floating insn. */ | |
ad851752 | 8671 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 8672 | delete_insn (floater); |
8673 | continue; | |
8674 | } | |
8675 | } | |
8676 | } | |
8677 | } | |
8678 | ||
9aadea62 | 8679 | static int |
5c1d8983 | 8680 | pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest, |
8681 | rtx src1, rtx src2) | |
bd49d362 | 8682 | { |
8683 | int insn_code_number; | |
8684 | rtx start, end; | |
8685 | ||
8686 | /* Create a PARALLEL with the patterns of ANCHOR and | |
8687 | FLOATER, try to recognize it, then test constraints | |
8688 | for the resulting pattern. | |
8689 | ||
8690 | If the pattern doesn't match or the constraints | |
8691 | aren't met keep searching for a suitable floater | |
8692 | insn. */ | |
8693 | XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor); | |
8694 | XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater); | |
8695 | INSN_CODE (new) = -1; | |
8696 | insn_code_number = recog_memoized (new); | |
8697 | if (insn_code_number < 0 | |
bf9fd117 | 8698 | || (extract_insn (new), ! constrain_operands (1))) |
bd49d362 | 8699 | return 0; |
8700 | ||
8701 | if (reversed) | |
8702 | { | |
8703 | start = anchor; | |
8704 | end = floater; | |
8705 | } | |
8706 | else | |
8707 | { | |
8708 | start = floater; | |
8709 | end = anchor; | |
8710 | } | |
8711 | ||
8712 | /* There's up to three operands to consider. One | |
8713 | output and two inputs. | |
8714 | ||
8715 | The output must not be used between FLOATER & ANCHOR | |
8716 | exclusive. The inputs must not be set between | |
8717 | FLOATER and ANCHOR exclusive. */ | |
8718 | ||
8719 | if (reg_used_between_p (dest, start, end)) | |
8720 | return 0; | |
8721 | ||
8722 | if (reg_set_between_p (src1, start, end)) | |
8723 | return 0; | |
8724 | ||
8725 | if (reg_set_between_p (src2, start, end)) | |
8726 | return 0; | |
8727 | ||
8728 | /* If we get here, then everything is good. */ | |
8729 | return 1; | |
8730 | } | |
14d18de3 | 8731 | |
a6582a53 | 8732 | /* Return nonzero if references for INSN are delayed. |
14d18de3 | 8733 | |
8734 | Millicode insns are actually function calls with some special | |
8735 | constraints on arguments and register usage. | |
8736 | ||
8737 | Millicode calls always expect their arguments in the integer argument | |
8738 | registers, and always return their result in %r29 (ret1). They | |
2013ddf6 | 8739 | are expected to clobber their arguments, %r1, %r29, and the return |
8740 | pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else. | |
8741 | ||
8742 | This function tells reorg that the references to arguments and | |
8743 | millicode calls do not appear to happen until after the millicode call. | |
8744 | This allows reorg to put insns which set the argument registers into the | |
8745 | delay slot of the millicode call -- thus they act more like traditional | |
8746 | CALL_INSNs. | |
8747 | ||
8748 | Note we can not consider side effects of the insn to be delayed because | |
8749 | the branch and link insn will clobber the return pointer. If we happened | |
8750 | to use the return pointer in the delay slot of the call, then we lose. | |
14d18de3 | 8751 | |
8752 | get_attr_type will try to recognize the given insn, so make sure to | |
8753 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
8754 | in particular. */ | |
8755 | int | |
5c1d8983 | 8756 | insn_refs_are_delayed (rtx insn) |
14d18de3 | 8757 | { |
9840d99d | 8758 | return ((GET_CODE (insn) == INSN |
14d18de3 | 8759 | && GET_CODE (PATTERN (insn)) != SEQUENCE |
8760 | && GET_CODE (PATTERN (insn)) != USE | |
8761 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8762 | && get_attr_type (insn) == TYPE_MILLI)); | |
8763 | } | |
5cb4669a | 8764 | |
58a72cce | 8765 | /* On the HP-PA the value is found in register(s) 28(-29), unless |
8766 | the mode is SF or DF. Then the value is returned in fr4 (32). | |
8767 | ||
8768 | This must perform the same promotions as PROMOTE_MODE, else | |
b8debbe8 | 8769 | TARGET_PROMOTE_FUNCTION_RETURN will not work correctly. |
58a72cce | 8770 | |
8771 | Small structures must be returned in a PARALLEL on PA64 in order | |
8772 | to match the HP Compiler ABI. */ | |
8773 | ||
8774 | rtx | |
5c1d8983 | 8775 | function_value (tree valtype, tree func ATTRIBUTE_UNUSED) |
58a72cce | 8776 | { |
8777 | enum machine_mode valmode; | |
8778 | ||
8779 | /* Aggregates with a size less than or equal to 128 bits are returned | |
8780 | in GR 28(-29). They are left justified. The pad bits are undefined. | |
8781 | Larger aggregates are returned in memory. */ | |
8782 | if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype)) | |
8783 | { | |
8784 | rtx loc[2]; | |
8785 | int i, offset = 0; | |
8786 | int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2; | |
8787 | ||
8788 | for (i = 0; i < ub; i++) | |
8789 | { | |
8790 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
8791 | gen_rtx_REG (DImode, 28 + i), | |
8792 | GEN_INT (offset)); | |
8793 | offset += 8; | |
8794 | } | |
8795 | ||
8796 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc)); | |
8797 | } | |
8798 | ||
8799 | if ((INTEGRAL_TYPE_P (valtype) | |
8800 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
8801 | || POINTER_TYPE_P (valtype)) | |
8802 | valmode = word_mode; | |
8803 | else | |
8804 | valmode = TYPE_MODE (valtype); | |
8805 | ||
8806 | if (TREE_CODE (valtype) == REAL_TYPE | |
8807 | && TYPE_MODE (valtype) != TFmode | |
8808 | && !TARGET_SOFT_FLOAT) | |
8809 | return gen_rtx_REG (valmode, 32); | |
8810 | ||
8811 | return gen_rtx_REG (valmode, 28); | |
8812 | } | |
8813 | ||
5e3c5739 | 8814 | /* Return the location of a parameter that is passed in a register or NULL |
8815 | if the parameter has any component that is passed in memory. | |
8816 | ||
8817 | This is new code and will be pushed to into the net sources after | |
9840d99d | 8818 | further testing. |
5e3c5739 | 8819 | |
8820 | ??? We might want to restructure this so that it looks more like other | |
8821 | ports. */ | |
8822 | rtx | |
5c1d8983 | 8823 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, |
8824 | int named ATTRIBUTE_UNUSED) | |
5e3c5739 | 8825 | { |
8826 | int max_arg_words = (TARGET_64BIT ? 8 : 4); | |
2a075f91 | 8827 | int alignment = 0; |
ac965869 | 8828 | int arg_size; |
5e3c5739 | 8829 | int fpr_reg_base; |
8830 | int gpr_reg_base; | |
8831 | rtx retval; | |
8832 | ||
ac965869 | 8833 | if (mode == VOIDmode) |
8834 | return NULL_RTX; | |
8835 | ||
8836 | arg_size = FUNCTION_ARG_SIZE (mode, type); | |
8837 | ||
8838 | /* If this arg would be passed partially or totally on the stack, then | |
8839 | this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will | |
8840 | handle arguments which are split between regs and stack slots if | |
8841 | the ABI mandates split arguments. */ | |
5e3c5739 | 8842 | if (! TARGET_64BIT) |
8843 | { | |
ac965869 | 8844 | /* The 32-bit ABI does not split arguments. */ |
8845 | if (cum->words + arg_size > max_arg_words) | |
5e3c5739 | 8846 | return NULL_RTX; |
8847 | } | |
8848 | else | |
8849 | { | |
2a075f91 | 8850 | if (arg_size > 1) |
8851 | alignment = cum->words & 1; | |
ac965869 | 8852 | if (cum->words + alignment >= max_arg_words) |
5e3c5739 | 8853 | return NULL_RTX; |
8854 | } | |
8855 | ||
8856 | /* The 32bit ABIs and the 64bit ABIs are rather different, | |
8857 | particularly in their handling of FP registers. We might | |
8858 | be able to cleverly share code between them, but I'm not | |
9aadea62 | 8859 | going to bother in the hope that splitting them up results |
2a075f91 | 8860 | in code that is more easily understood. */ |
5e3c5739 | 8861 | |
5e3c5739 | 8862 | if (TARGET_64BIT) |
8863 | { | |
8864 | /* Advance the base registers to their current locations. | |
8865 | ||
8866 | Remember, gprs grow towards smaller register numbers while | |
2a075f91 | 8867 | fprs grow to higher register numbers. Also remember that |
8868 | although FP regs are 32-bit addressable, we pretend that | |
8869 | the registers are 64-bits wide. */ | |
5e3c5739 | 8870 | gpr_reg_base = 26 - cum->words; |
8871 | fpr_reg_base = 32 + cum->words; | |
9840d99d | 8872 | |
ac965869 | 8873 | /* Arguments wider than one word and small aggregates need special |
8874 | treatment. */ | |
8875 | if (arg_size > 1 | |
8876 | || mode == BLKmode | |
8877 | || (type && AGGREGATE_TYPE_P (type))) | |
5e3c5739 | 8878 | { |
2a075f91 | 8879 | /* Double-extended precision (80-bit), quad-precision (128-bit) |
8880 | and aggregates including complex numbers are aligned on | |
8881 | 128-bit boundaries. The first eight 64-bit argument slots | |
8882 | are associated one-to-one, with general registers r26 | |
8883 | through r19, and also with floating-point registers fr4 | |
8884 | through fr11. Arguments larger than one word are always | |
ac965869 | 8885 | passed in general registers. |
8886 | ||
8887 | Using a PARALLEL with a word mode register results in left | |
8888 | justified data on a big-endian target. */ | |
2a075f91 | 8889 | |
8890 | rtx loc[8]; | |
8891 | int i, offset = 0, ub = arg_size; | |
8892 | ||
8893 | /* Align the base register. */ | |
8894 | gpr_reg_base -= alignment; | |
8895 | ||
8896 | ub = MIN (ub, max_arg_words - cum->words - alignment); | |
8897 | for (i = 0; i < ub; i++) | |
5e3c5739 | 8898 | { |
2a075f91 | 8899 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, |
8900 | gen_rtx_REG (DImode, gpr_reg_base), | |
8901 | GEN_INT (offset)); | |
8902 | gpr_reg_base -= 1; | |
8903 | offset += 8; | |
5e3c5739 | 8904 | } |
2a075f91 | 8905 | |
8906 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc)); | |
5e3c5739 | 8907 | } |
ac965869 | 8908 | } |
5e3c5739 | 8909 | else |
8910 | { | |
8911 | /* If the argument is larger than a word, then we know precisely | |
8912 | which registers we must use. */ | |
2a075f91 | 8913 | if (arg_size > 1) |
5e3c5739 | 8914 | { |
8915 | if (cum->words) | |
8916 | { | |
8917 | gpr_reg_base = 23; | |
8918 | fpr_reg_base = 38; | |
8919 | } | |
8920 | else | |
8921 | { | |
8922 | gpr_reg_base = 25; | |
8923 | fpr_reg_base = 34; | |
8924 | } | |
ac965869 | 8925 | |
8926 | /* Structures 5 to 8 bytes in size are passed in the general | |
8927 | registers in the same manner as other non floating-point | |
8928 | objects. The data is right-justified and zero-extended | |
8929 | to 64 bits. | |
8930 | ||
8931 | This is magic. Normally, using a PARALLEL results in left | |
8932 | justified data on a big-endian target. However, using a | |
8933 | single double-word register provides the required right | |
2cecd772 | 8934 | justification for 5 to 8 byte structures. This has nothing |
ac965869 | 8935 | to do with the direction of padding specified for the argument. |
8936 | It has to do with how the data is widened and shifted into | |
8937 | and from the register. | |
8938 | ||
8939 | Aside from adding load_multiple and store_multiple patterns, | |
8940 | this is the only way that I have found to obtain right | |
8941 | justification of BLKmode data when it has a size greater | |
8942 | than one word. Splitting the operation into two SImode loads | |
8943 | or returning a DImode REG results in left justified data. */ | |
8944 | if (mode == BLKmode) | |
8945 | { | |
58a72cce | 8946 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, |
8947 | gen_rtx_REG (DImode, gpr_reg_base), | |
8948 | const0_rtx); | |
8949 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc)); | |
ac965869 | 8950 | } |
5e3c5739 | 8951 | } |
8952 | else | |
8953 | { | |
8954 | /* We have a single word (32 bits). A simple computation | |
8955 | will get us the register #s we need. */ | |
8956 | gpr_reg_base = 26 - cum->words; | |
8957 | fpr_reg_base = 32 + 2 * cum->words; | |
8958 | } | |
8959 | } | |
8960 | ||
9503b0f7 | 8961 | /* Determine if the argument needs to be passed in both general and |
5e3c5739 | 8962 | floating point registers. */ |
9503b0f7 | 8963 | if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32) |
8964 | /* If we are doing soft-float with portable runtime, then there | |
8965 | is no need to worry about FP regs. */ | |
f336e0bc | 8966 | && !TARGET_SOFT_FLOAT |
9503b0f7 | 8967 | /* The parameter must be some kind of float, else we can just |
8968 | pass it in integer registers. */ | |
8969 | && FLOAT_MODE_P (mode) | |
8970 | /* The target function must not have a prototype. */ | |
8971 | && cum->nargs_prototype <= 0 | |
8972 | /* libcalls do not need to pass items in both FP and general | |
8973 | registers. */ | |
8974 | && type != NULL_TREE | |
f336e0bc | 8975 | /* All this hair applies to "outgoing" args only. This includes |
8976 | sibcall arguments setup with FUNCTION_INCOMING_ARG. */ | |
8977 | && !cum->incoming) | |
9503b0f7 | 8978 | /* Also pass outgoing floating arguments in both registers in indirect |
8979 | calls with the 32 bit ABI and the HP assembler since there is no | |
8980 | way to the specify argument locations in static functions. */ | |
f336e0bc | 8981 | || (!TARGET_64BIT |
8982 | && !TARGET_GAS | |
8983 | && !cum->incoming | |
9503b0f7 | 8984 | && cum->indirect |
8985 | && FLOAT_MODE_P (mode))) | |
5e3c5739 | 8986 | { |
8987 | retval | |
8988 | = gen_rtx_PARALLEL | |
8989 | (mode, | |
8990 | gen_rtvec (2, | |
8991 | gen_rtx_EXPR_LIST (VOIDmode, | |
8992 | gen_rtx_REG (mode, fpr_reg_base), | |
8993 | const0_rtx), | |
8994 | gen_rtx_EXPR_LIST (VOIDmode, | |
8995 | gen_rtx_REG (mode, gpr_reg_base), | |
8996 | const0_rtx))); | |
8997 | } | |
8998 | else | |
8999 | { | |
9000 | /* See if we should pass this parameter in a general register. */ | |
9001 | if (TARGET_SOFT_FLOAT | |
9002 | /* Indirect calls in the normal 32bit ABI require all arguments | |
9003 | to be passed in general registers. */ | |
9004 | || (!TARGET_PORTABLE_RUNTIME | |
9005 | && !TARGET_64BIT | |
a052da6f | 9006 | && !TARGET_ELF32 |
5e3c5739 | 9007 | && cum->indirect) |
9008 | /* If the parameter is not a floating point parameter, then | |
9009 | it belongs in GPRs. */ | |
9010 | || !FLOAT_MODE_P (mode)) | |
9011 | retval = gen_rtx_REG (mode, gpr_reg_base); | |
9012 | else | |
9013 | retval = gen_rtx_REG (mode, fpr_reg_base); | |
9014 | } | |
9015 | return retval; | |
9016 | } | |
9017 | ||
9018 | ||
9019 | /* If this arg would be passed totally in registers or totally on the stack, | |
9020 | then this routine should return zero. It is currently called only for | |
6dc3b0d9 | 9021 | the 64-bit target. */ |
5e3c5739 | 9022 | int |
5c1d8983 | 9023 | function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
9024 | tree type, int named ATTRIBUTE_UNUSED) | |
5e3c5739 | 9025 | { |
b7d86581 | 9026 | unsigned int max_arg_words = 8; |
9027 | unsigned int offset = 0; | |
5e3c5739 | 9028 | |
b7d86581 | 9029 | if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1)) |
5e3c5739 | 9030 | offset = 1; |
9031 | ||
b7d86581 | 9032 | if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words) |
6dc3b0d9 | 9033 | /* Arg fits fully into registers. */ |
5e3c5739 | 9034 | return 0; |
9840d99d | 9035 | else if (cum->words + offset >= max_arg_words) |
6dc3b0d9 | 9036 | /* Arg fully on the stack. */ |
5e3c5739 | 9037 | return 0; |
9038 | else | |
6dc3b0d9 | 9039 | /* Arg is split. */ |
5e3c5739 | 9040 | return max_arg_words - cum->words - offset; |
5e3c5739 | 9041 | } |
9042 | ||
9043 | ||
9044 | /* Return 1 if this is a comparison operator. This allows the use of | |
9045 | MATCH_OPERATOR to recognize all the branch insns. */ | |
9046 | ||
9047 | int | |
5c1d8983 | 9048 | cmpib_comparison_operator (rtx op, enum machine_mode mode) |
5e3c5739 | 9049 | { |
9050 | return ((mode == VOIDmode || GET_MODE (op) == mode) | |
9051 | && (GET_CODE (op) == EQ | |
9052 | || GET_CODE (op) == NE | |
9053 | || GET_CODE (op) == GT | |
5e3c5739 | 9054 | || GET_CODE (op) == GTU |
32509e56 | 9055 | || GET_CODE (op) == GE |
5e3c5739 | 9056 | || GET_CODE (op) == LT |
9057 | || GET_CODE (op) == LE | |
9058 | || GET_CODE (op) == LEU)); | |
9059 | } | |
9060 | ||
52470889 | 9061 | /* On hpux10, the linker will give an error if we have a reference |
9062 | in the read-only data section to a symbol defined in a shared | |
9063 | library. Therefore, expressions that might require a reloc can | |
9064 | not be placed in the read-only data section. */ | |
9065 | ||
9066 | static void | |
b572d1a5 | 9067 | pa_select_section (tree exp, int reloc, |
9068 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
52470889 | 9069 | { |
9070 | if (TREE_CODE (exp) == VAR_DECL | |
9071 | && TREE_READONLY (exp) | |
9072 | && !TREE_THIS_VOLATILE (exp) | |
9073 | && DECL_INITIAL (exp) | |
9074 | && (DECL_INITIAL (exp) == error_mark_node | |
9075 | || TREE_CONSTANT (DECL_INITIAL (exp))) | |
9076 | && !reloc) | |
9077 | readonly_data_section (); | |
9078 | else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c' | |
52470889 | 9079 | && !reloc) |
9080 | readonly_data_section (); | |
9081 | else | |
9082 | data_section (); | |
9083 | } | |
1f3233d1 | 9084 | |
67c1e638 | 9085 | static void |
5c1d8983 | 9086 | pa_globalize_label (FILE *stream, const char *name) |
67c1e638 | 9087 | { |
9088 | /* We only handle DATA objects here, functions are globalized in | |
9089 | ASM_DECLARE_FUNCTION_NAME. */ | |
9090 | if (! FUNCTION_NAME_P (name)) | |
9091 | { | |
9092 | fputs ("\t.EXPORT ", stream); | |
9093 | assemble_name (stream, name); | |
9094 | fputs (",DATA\n", stream); | |
9095 | } | |
9096 | } | |
b8debbe8 | 9097 | |
6644435d | 9098 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
9099 | ||
b8debbe8 | 9100 | static rtx |
9101 | pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
9102 | int incoming ATTRIBUTE_UNUSED) | |
9103 | { | |
9104 | return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM); | |
9105 | } | |
9106 | ||
6644435d | 9107 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
9108 | ||
b8debbe8 | 9109 | bool |
9110 | pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
9111 | { | |
9112 | /* SOM ABI says that objects larger than 64 bits are returned in memory. | |
9113 | PA64 ABI says that objects larger than 128 bits are returned in memory. | |
9114 | Note, int_size_in_bytes can return -1 if the size of the object is | |
9115 | variable or larger than the maximum value that can be expressed as | |
9116 | a HOST_WIDE_INT. It can also return zero for an empty type. The | |
9117 | simplest way to handle variable and empty types is to pass them in | |
9118 | memory. This avoids problems in defining the boundaries of argument | |
9119 | slots, allocating registers, etc. */ | |
9120 | return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8) | |
9121 | || int_size_in_bytes (type) <= 0); | |
9122 | } | |
9123 | ||
1f3233d1 | 9124 | #include "gt-pa.h" |