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87ad11b0 | 1 | /* Subroutines for insn-output.c for HPPA. |
a9ac13e4 | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
fbf5169c | 3 | 2002, 2003, 2004 Free Software Foundation, Inc. |
87ad11b0 | 4 | Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c |
5 | ||
5c1d8983 | 6 | This file is part of GCC. |
87ad11b0 | 7 | |
5c1d8983 | 8 | GCC is free software; you can redistribute it and/or modify |
87ad11b0 | 9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
5c1d8983 | 13 | GCC is distributed in the hope that it will be useful, |
87ad11b0 | 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
5c1d8983 | 19 | along with GCC; see the file COPYING. If not, write to |
01e379d0 | 20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
87ad11b0 | 22 | |
87ad11b0 | 23 | #include "config.h" |
b1ca791d | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
87ad11b0 | 27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
87ad11b0 | 33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "tree.h" | |
9d2d8bd6 | 36 | #include "output.h" |
a584fe8a | 37 | #include "except.h" |
32509e56 | 38 | #include "expr.h" |
d8fc4d0b | 39 | #include "optabs.h" |
d8fc4d0b | 40 | #include "reload.h" |
d7e2f694 | 41 | #include "integrate.h" |
0a893c29 | 42 | #include "function.h" |
b1ca791d | 43 | #include "toplev.h" |
5cb4669a | 44 | #include "ggc.h" |
611a88e1 | 45 | #include "recog.h" |
a584fe8a | 46 | #include "predict.h" |
611a88e1 | 47 | #include "tm_p.h" |
a767736d | 48 | #include "target.h" |
49 | #include "target-def.h" | |
87ad11b0 | 50 | |
bea4bad2 | 51 | #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE |
5e611c5f | 52 | #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1 |
bea4bad2 | 53 | |
cde3e16c | 54 | /* Return nonzero if there is a bypass for the output of |
55 | OUT_INSN and the fp store IN_INSN. */ | |
56 | int | |
5c1d8983 | 57 | hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn) |
cde3e16c | 58 | { |
59 | enum machine_mode store_mode; | |
60 | enum machine_mode other_mode; | |
61 | rtx set; | |
62 | ||
63 | if (recog_memoized (in_insn) < 0 | |
64 | || get_attr_type (in_insn) != TYPE_FPSTORE | |
65 | || recog_memoized (out_insn) < 0) | |
66 | return 0; | |
67 | ||
68 | store_mode = GET_MODE (SET_SRC (PATTERN (in_insn))); | |
69 | ||
70 | set = single_set (out_insn); | |
71 | if (!set) | |
72 | return 0; | |
73 | ||
74 | other_mode = GET_MODE (SET_SRC (set)); | |
75 | ||
76 | return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode)); | |
77 | } | |
78 | ||
79 | ||
cc858176 | 80 | #ifndef DO_FRAME_NOTES |
81 | #ifdef INCOMING_RETURN_ADDR_RTX | |
82 | #define DO_FRAME_NOTES 1 | |
83 | #else | |
84 | #define DO_FRAME_NOTES 0 | |
85 | #endif | |
86 | #endif | |
87 | ||
dbd3d89d | 88 | static void copy_reg_pointer (rtx, rtx); |
5c1d8983 | 89 | static int hppa_address_cost (rtx); |
90 | static bool hppa_rtx_costs (rtx, int, int, int *); | |
91 | static inline rtx force_mode (enum machine_mode, rtx); | |
92 | static void pa_reorg (void); | |
93 | static void pa_combine_instructions (void); | |
94 | static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx); | |
95 | static int forward_branch_p (rtx); | |
96 | static int shadd_constant_p (int); | |
97 | static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *); | |
008c057d | 98 | static int compute_movmem_length (rtx); |
99 | static int compute_clrmem_length (rtx); | |
5c1d8983 | 100 | static bool pa_assemble_integer (rtx, unsigned int, int); |
101 | static void remove_useless_addtr_insns (int); | |
6bcdc1fb | 102 | static void store_reg (int, HOST_WIDE_INT, int); |
103 | static void store_reg_modify (int, int, HOST_WIDE_INT); | |
104 | static void load_reg (int, HOST_WIDE_INT, int); | |
105 | static void set_reg_plus_d (int, int, HOST_WIDE_INT, int); | |
5c1d8983 | 106 | static void pa_output_function_prologue (FILE *, HOST_WIDE_INT); |
107 | static void update_total_code_bytes (int); | |
108 | static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
109 | static int pa_adjust_cost (rtx, rtx, rtx, int); | |
110 | static int pa_adjust_priority (rtx, int); | |
111 | static int pa_issue_rate (void); | |
112 | static void pa_select_section (tree, int, unsigned HOST_WIDE_INT) | |
52470889 | 113 | ATTRIBUTE_UNUSED; |
5c1d8983 | 114 | static void pa_encode_section_info (tree, rtx, int); |
115 | static const char *pa_strip_name_encoding (const char *); | |
116 | static bool pa_function_ok_for_sibcall (tree, tree); | |
117 | static void pa_globalize_label (FILE *, const char *) | |
63b8cd48 | 118 | ATTRIBUTE_UNUSED; |
5c1d8983 | 119 | static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
120 | HOST_WIDE_INT, tree); | |
de419443 | 121 | #if !defined(USE_COLLECT2) |
5c1d8983 | 122 | static void pa_asm_out_constructor (rtx, int); |
123 | static void pa_asm_out_destructor (rtx, int); | |
de419443 | 124 | #endif |
5c1d8983 | 125 | static void pa_init_builtins (void); |
b8debbe8 | 126 | static rtx hppa_builtin_saveregs (void); |
4c33eb68 | 127 | static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *); |
5c1d8983 | 128 | static void copy_fp_args (rtx) ATTRIBUTE_UNUSED; |
129 | static int length_fp_args (rtx) ATTRIBUTE_UNUSED; | |
130 | static struct deferred_plabel *get_plabel (const char *) | |
ece88821 | 131 | ATTRIBUTE_UNUSED; |
5c1d8983 | 132 | static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED; |
133 | static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED; | |
134 | static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED; | |
135 | static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED; | |
136 | static void pa_elf_file_start (void) ATTRIBUTE_UNUSED; | |
137 | static void pa_som_file_start (void) ATTRIBUTE_UNUSED; | |
138 | static void pa_linux_file_start (void) ATTRIBUTE_UNUSED; | |
139 | static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED; | |
140 | static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED; | |
141 | static void output_deferred_plabels (void); | |
f2f543a3 | 142 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
143 | static void pa_hpux_init_libfuncs (void); | |
144 | #endif | |
b8debbe8 | 145 | static rtx pa_struct_value_rtx (tree, int); |
9d3ddb8f | 146 | |
87ad11b0 | 147 | /* Save the operands last given to a compare for use when we |
148 | generate a scc or bcc insn. */ | |
87ad11b0 | 149 | rtx hppa_compare_op0, hppa_compare_op1; |
150 | enum cmp_type hppa_branch_type; | |
151 | ||
134b4858 | 152 | /* Which cpu we are scheduling for. */ |
153 | enum processor_type pa_cpu; | |
154 | ||
155 | /* String to hold which cpu we are scheduling for. */ | |
611a88e1 | 156 | const char *pa_cpu_string; |
134b4858 | 157 | |
4dc42288 | 158 | /* Which architecture we are generating code for. */ |
159 | enum architecture_type pa_arch; | |
160 | ||
161 | /* String to hold which architecture we are generating code for. */ | |
611a88e1 | 162 | const char *pa_arch_string; |
4dc42288 | 163 | |
a9960cdc | 164 | /* Counts for the number of callee-saved general and floating point |
165 | registers which were saved by the current function's prologue. */ | |
166 | static int gr_saved, fr_saved; | |
167 | ||
5c1d8983 | 168 | static rtx find_addr_reg (rtx); |
87ad11b0 | 169 | |
2247cc5f | 170 | /* Keep track of the number of bytes we have output in the CODE subspace |
06ddb6f8 | 171 | during this compilation so we'll know when to emit inline long-calls. */ |
ece88821 | 172 | unsigned long total_code_bytes; |
06ddb6f8 | 173 | |
2247cc5f | 174 | /* The last address of the previous function plus the number of bytes in |
175 | associated thunks that have been output. This is used to determine if | |
176 | a thunk can use an IA-relative branch to reach its target function. */ | |
177 | static int last_address; | |
178 | ||
e3f53689 | 179 | /* Variables to handle plabels that we discover are necessary at assembly |
01cc3b75 | 180 | output time. They are output after the current function. */ |
1f3233d1 | 181 | struct deferred_plabel GTY(()) |
e3f53689 | 182 | { |
183 | rtx internal_label; | |
8d0cec1a | 184 | const char *name; |
1f3233d1 | 185 | }; |
186 | static GTY((length ("n_deferred_plabels"))) struct deferred_plabel * | |
187 | deferred_plabels; | |
e11bd7e5 | 188 | static size_t n_deferred_plabels = 0; |
f6940372 | 189 | |
a767736d | 190 | \f |
191 | /* Initialize the GCC target structure. */ | |
58356836 | 192 | |
193 | #undef TARGET_ASM_ALIGNED_HI_OP | |
194 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
195 | #undef TARGET_ASM_ALIGNED_SI_OP | |
196 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
197 | #undef TARGET_ASM_ALIGNED_DI_OP | |
198 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
199 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
200 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
201 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
202 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
203 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
204 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
205 | #undef TARGET_ASM_INTEGER | |
206 | #define TARGET_ASM_INTEGER pa_assemble_integer | |
207 | ||
17d9b0c3 | 208 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
209 | #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue | |
210 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
211 | #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue | |
e3f53689 | 212 | |
747af5e7 | 213 | #undef TARGET_SCHED_ADJUST_COST |
214 | #define TARGET_SCHED_ADJUST_COST pa_adjust_cost | |
215 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
216 | #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority | |
217 | #undef TARGET_SCHED_ISSUE_RATE | |
218 | #define TARGET_SCHED_ISSUE_RATE pa_issue_rate | |
219 | ||
7811991d | 220 | #undef TARGET_ENCODE_SECTION_INFO |
221 | #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info | |
7b4a38a6 | 222 | #undef TARGET_STRIP_NAME_ENCODING |
223 | #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding | |
7811991d | 224 | |
805e22b2 | 225 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
226 | #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall | |
227 | ||
6988553d | 228 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
229 | #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk | |
eb344f43 | 230 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
231 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
6988553d | 232 | |
f6940372 | 233 | #undef TARGET_ASM_FILE_END |
234 | #define TARGET_ASM_FILE_END output_deferred_plabels | |
235 | ||
de419443 | 236 | #if !defined(USE_COLLECT2) |
237 | #undef TARGET_ASM_CONSTRUCTOR | |
238 | #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor | |
239 | #undef TARGET_ASM_DESTRUCTOR | |
240 | #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor | |
241 | #endif | |
242 | ||
ffa8918b | 243 | #undef TARGET_INIT_BUILTINS |
244 | #define TARGET_INIT_BUILTINS pa_init_builtins | |
245 | ||
fab7adbf | 246 | #undef TARGET_RTX_COSTS |
247 | #define TARGET_RTX_COSTS hppa_rtx_costs | |
ec0457a8 | 248 | #undef TARGET_ADDRESS_COST |
249 | #define TARGET_ADDRESS_COST hppa_address_cost | |
fab7adbf | 250 | |
2efea8c0 | 251 | #undef TARGET_MACHINE_DEPENDENT_REORG |
252 | #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg | |
253 | ||
f2f543a3 | 254 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
255 | #undef TARGET_INIT_LIBFUNCS | |
256 | #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs | |
257 | #endif | |
258 | ||
b8debbe8 | 259 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
260 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
261 | #undef TARGET_PROMOTE_PROTOTYPES | |
262 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
263 | ||
264 | #undef TARGET_STRUCT_VALUE_RTX | |
265 | #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx | |
266 | #undef TARGET_RETURN_IN_MEMORY | |
267 | #define TARGET_RETURN_IN_MEMORY pa_return_in_memory | |
0336f0f0 | 268 | #undef TARGET_MUST_PASS_IN_STACK |
269 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
b8debbe8 | 270 | |
271 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
272 | #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs | |
4c33eb68 | 273 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
274 | #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr | |
b8debbe8 | 275 | |
57e4bbfb | 276 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 277 | \f |
134b4858 | 278 | void |
5c1d8983 | 279 | override_options (void) |
134b4858 | 280 | { |
b3b62da8 | 281 | if (pa_cpu_string == NULL) |
282 | pa_cpu_string = TARGET_SCHED_DEFAULT; | |
283 | ||
284 | if (! strcmp (pa_cpu_string, "8000")) | |
285 | { | |
286 | pa_cpu_string = "8000"; | |
287 | pa_cpu = PROCESSOR_8000; | |
288 | } | |
289 | else if (! strcmp (pa_cpu_string, "7100")) | |
134b4858 | 290 | { |
291 | pa_cpu_string = "7100"; | |
292 | pa_cpu = PROCESSOR_7100; | |
293 | } | |
b3b62da8 | 294 | else if (! strcmp (pa_cpu_string, "700")) |
a87e1e15 | 295 | { |
296 | pa_cpu_string = "700"; | |
297 | pa_cpu = PROCESSOR_700; | |
298 | } | |
b3b62da8 | 299 | else if (! strcmp (pa_cpu_string, "7100LC")) |
134b4858 | 300 | { |
301 | pa_cpu_string = "7100LC"; | |
302 | pa_cpu = PROCESSOR_7100LC; | |
303 | } | |
b3b62da8 | 304 | else if (! strcmp (pa_cpu_string, "7200")) |
b4e0d953 | 305 | { |
306 | pa_cpu_string = "7200"; | |
307 | pa_cpu = PROCESSOR_7200; | |
308 | } | |
b3b62da8 | 309 | else if (! strcmp (pa_cpu_string, "7300")) |
bea4bad2 | 310 | { |
311 | pa_cpu_string = "7300"; | |
312 | pa_cpu = PROCESSOR_7300; | |
313 | } | |
134b4858 | 314 | else |
315 | { | |
bea4bad2 | 316 | warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string); |
134b4858 | 317 | } |
c7a4e712 | 318 | |
4dc42288 | 319 | /* Set the instruction set architecture. */ |
320 | if (pa_arch_string && ! strcmp (pa_arch_string, "1.0")) | |
321 | { | |
322 | pa_arch_string = "1.0"; | |
323 | pa_arch = ARCHITECTURE_10; | |
324 | target_flags &= ~(MASK_PA_11 | MASK_PA_20); | |
325 | } | |
326 | else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1")) | |
327 | { | |
328 | pa_arch_string = "1.1"; | |
329 | pa_arch = ARCHITECTURE_11; | |
330 | target_flags &= ~MASK_PA_20; | |
331 | target_flags |= MASK_PA_11; | |
332 | } | |
333 | else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0")) | |
334 | { | |
335 | pa_arch_string = "2.0"; | |
336 | pa_arch = ARCHITECTURE_20; | |
337 | target_flags |= MASK_PA_11 | MASK_PA_20; | |
338 | } | |
339 | else if (pa_arch_string) | |
340 | { | |
68435912 | 341 | warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string); |
4dc42288 | 342 | } |
343 | ||
7c5101fc | 344 | /* Unconditional branches in the delay slot are not compatible with dwarf2 |
345 | call frame information. There is no benefit in using this optimization | |
346 | on PA8000 and later processors. */ | |
347 | if (pa_cpu >= PROCESSOR_8000 | |
348 | || (! USING_SJLJ_EXCEPTIONS && flag_exceptions) | |
349 | || flag_unwind_tables) | |
350 | target_flags &= ~MASK_JUMP_IN_DELAY; | |
351 | ||
c7a4e712 | 352 | if (flag_pic && TARGET_PORTABLE_RUNTIME) |
353 | { | |
354 | warning ("PIC code generation is not supported in the portable runtime model\n"); | |
355 | } | |
356 | ||
b29897dd | 357 | if (flag_pic && TARGET_FAST_INDIRECT_CALLS) |
c7a4e712 | 358 | { |
ad87de1e | 359 | warning ("PIC code generation is not compatible with fast indirect calls\n"); |
c7a4e712 | 360 | } |
751e64a1 | 361 | |
5bd7b548 | 362 | if (! TARGET_GAS && write_symbols != NO_DEBUG) |
363 | { | |
364 | warning ("-g is only supported when using GAS on this processor,"); | |
68435912 | 365 | warning ("-g option disabled"); |
5bd7b548 | 366 | write_symbols = NO_DEBUG; |
367 | } | |
5cb4669a | 368 | |
fc44315f | 369 | /* We only support the "big PIC" model now. And we always generate PIC |
370 | code when in 64bit mode. */ | |
371 | if (flag_pic == 1 || TARGET_64BIT) | |
5e3c5739 | 372 | flag_pic = 2; |
373 | ||
58356836 | 374 | /* We can't guarantee that .dword is available for 32-bit targets. */ |
375 | if (UNITS_PER_WORD == 4) | |
376 | targetm.asm_out.aligned_op.di = NULL; | |
377 | ||
378 | /* The unaligned ops are only available when using GAS. */ | |
379 | if (!TARGET_GAS) | |
380 | { | |
381 | targetm.asm_out.unaligned_op.hi = NULL; | |
382 | targetm.asm_out.unaligned_op.si = NULL; | |
383 | targetm.asm_out.unaligned_op.di = NULL; | |
384 | } | |
134b4858 | 385 | } |
386 | ||
066397a3 | 387 | static void |
5c1d8983 | 388 | pa_init_builtins (void) |
ffa8918b | 389 | { |
390 | #ifdef DONT_HAVE_FPUTC_UNLOCKED | |
391 | built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE; | |
5ddc8fb8 | 392 | implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE; |
ffa8918b | 393 | #endif |
394 | } | |
395 | ||
dbd3d89d | 396 | /* If FROM is a probable pointer register, mark TO as a probable |
397 | pointer register with the same pointer alignment as FROM. */ | |
398 | ||
399 | static void | |
400 | copy_reg_pointer (rtx to, rtx from) | |
401 | { | |
402 | if (REG_POINTER (from)) | |
403 | mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from))); | |
404 | } | |
405 | ||
e911aedf | 406 | /* Return nonzero only if OP is a register of mode MODE, |
891b55b4 | 407 | or CONST0_RTX. */ |
87ad11b0 | 408 | int |
5c1d8983 | 409 | reg_or_0_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 410 | { |
891b55b4 | 411 | return (op == CONST0_RTX (mode) || register_operand (op, mode)); |
87ad11b0 | 412 | } |
413 | ||
e911aedf | 414 | /* Return nonzero if OP is suitable for use in a call to a named |
575e0eb4 | 415 | function. |
416 | ||
9dc4cbf1 | 417 | For 2.5 try to eliminate either call_operand_address or |
575e0eb4 | 418 | function_label_operand, they perform very similar functions. */ |
87ad11b0 | 419 | int |
5c1d8983 | 420 | call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 421 | { |
2db59d96 | 422 | return (GET_MODE (op) == word_mode |
423 | && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME); | |
87ad11b0 | 424 | } |
425 | ||
6d36483b | 426 | /* Return 1 if X contains a symbolic expression. We know these |
427 | expressions will have one of a few well defined forms, so | |
347b5848 | 428 | we need only check those forms. */ |
429 | int | |
5c1d8983 | 430 | symbolic_expression_p (rtx x) |
347b5848 | 431 | { |
432 | ||
6dc3b0d9 | 433 | /* Strip off any HIGH. */ |
347b5848 | 434 | if (GET_CODE (x) == HIGH) |
435 | x = XEXP (x, 0); | |
436 | ||
437 | return (symbolic_operand (x, VOIDmode)); | |
438 | } | |
439 | ||
87ad11b0 | 440 | int |
5c1d8983 | 441 | symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 442 | { |
443 | switch (GET_CODE (op)) | |
444 | { | |
445 | case SYMBOL_REF: | |
446 | case LABEL_REF: | |
447 | return 1; | |
448 | case CONST: | |
449 | op = XEXP (op, 0); | |
450 | return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
451 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
452 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
453 | default: | |
454 | return 0; | |
455 | } | |
456 | } | |
457 | ||
458 | /* Return truth value of statement that OP is a symbolic memory | |
459 | operand of mode MODE. */ | |
460 | ||
461 | int | |
5c1d8983 | 462 | symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 463 | { |
464 | if (GET_CODE (op) == SUBREG) | |
465 | op = SUBREG_REG (op); | |
466 | if (GET_CODE (op) != MEM) | |
467 | return 0; | |
468 | op = XEXP (op, 0); | |
469 | return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST | |
470 | || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF); | |
471 | } | |
472 | ||
6d36483b | 473 | /* Return 1 if the operand is either a register, zero, or a memory operand |
891b55b4 | 474 | that is not symbolic. */ |
475 | ||
476 | int | |
5c1d8983 | 477 | reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode) |
891b55b4 | 478 | { |
479 | if (register_operand (op, mode)) | |
480 | return 1; | |
481 | ||
482 | if (op == CONST0_RTX (mode)) | |
483 | return 1; | |
484 | ||
dbd3d89d | 485 | if (GET_CODE (op) == SUBREG) |
486 | op = SUBREG_REG (op); | |
891b55b4 | 487 | |
dbd3d89d | 488 | if (GET_CODE (op) != MEM) |
489 | return 0; | |
490 | ||
491 | /* Until problems with management of the REG_POINTER flag are resolved, | |
492 | we need to delay creating move insns with unscaled indexed addresses | |
493 | until CSE is not expected. */ | |
494 | if (!TARGET_NO_SPACE_REGS | |
495 | && !cse_not_expected | |
496 | && GET_CODE (XEXP (op, 0)) == PLUS | |
497 | && REG_P (XEXP (XEXP (op, 0), 0)) | |
498 | && REG_P (XEXP (XEXP (op, 0), 1))) | |
499 | return 0; | |
500 | ||
501 | return (!symbolic_memory_operand (op, mode) | |
502 | && memory_address_p (mode, XEXP (op, 0))); | |
891b55b4 | 503 | } |
504 | ||
d3138877 | 505 | /* Return 1 if the operand is a register operand or a non-symbolic memory |
506 | operand after reload. This predicate is used for branch patterns that | |
507 | internally handle register reloading. We need to accept non-symbolic | |
508 | memory operands after reload to ensure that the pattern is still valid | |
509 | if reload didn't find a hard register for the operand. */ | |
510 | ||
511 | int | |
5c1d8983 | 512 | reg_before_reload_operand (rtx op, enum machine_mode mode) |
d3138877 | 513 | { |
6df54749 | 514 | /* Don't accept a SUBREG since it will need a reload. */ |
515 | if (GET_CODE (op) == SUBREG) | |
516 | return 0; | |
517 | ||
d3138877 | 518 | if (register_operand (op, mode)) |
519 | return 1; | |
520 | ||
521 | if (reload_completed | |
522 | && memory_operand (op, mode) | |
dbd3d89d | 523 | && !symbolic_memory_operand (op, mode)) |
d3138877 | 524 | return 1; |
525 | ||
526 | return 0; | |
527 | } | |
528 | ||
7c4d3047 | 529 | /* Accept any constant that can be moved in one instruction into a |
d9d7c968 | 530 | general register. */ |
6d36483b | 531 | int |
5c1d8983 | 532 | cint_ok_for_move (HOST_WIDE_INT intval) |
d9d7c968 | 533 | { |
534 | /* OK if ldo, ldil, or zdepi, can be used. */ | |
d8d5c4ff | 535 | return (CONST_OK_FOR_LETTER_P (intval, 'J') |
536 | || CONST_OK_FOR_LETTER_P (intval, 'N') | |
537 | || CONST_OK_FOR_LETTER_P (intval, 'K')); | |
d9d7c968 | 538 | } |
539 | ||
dbd3d89d | 540 | /* Return 1 iff OP is an indexed memory operand. */ |
541 | int | |
542 | indexed_memory_operand (rtx op, enum machine_mode mode) | |
543 | { | |
544 | if (GET_MODE (op) != mode) | |
545 | return 0; | |
546 | ||
547 | /* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */ | |
548 | if (reload_completed && GET_CODE (op) == SUBREG) | |
549 | op = SUBREG_REG (op); | |
550 | ||
551 | if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode)) | |
552 | return 0; | |
553 | ||
554 | op = XEXP (op, 0); | |
555 | ||
556 | return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op)); | |
557 | } | |
558 | ||
559 | /* Accept anything that can be used as a destination operand for a | |
560 | move instruction. We don't accept indexed memory operands since | |
561 | they are supported only for floating point stores. */ | |
562 | int | |
563 | move_dest_operand (rtx op, enum machine_mode mode) | |
564 | { | |
565 | if (register_operand (op, mode)) | |
566 | return 1; | |
567 | ||
568 | if (GET_MODE (op) != mode) | |
569 | return 0; | |
570 | ||
571 | if (GET_CODE (op) == SUBREG) | |
572 | op = SUBREG_REG (op); | |
573 | ||
574 | if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode)) | |
575 | return 0; | |
576 | ||
577 | op = XEXP (op, 0); | |
578 | ||
579 | return (memory_address_p (mode, op) | |
580 | && !IS_INDEX_ADDR_P (op) | |
581 | && !IS_LO_SUM_DLT_ADDR_P (op)); | |
582 | } | |
583 | ||
584 | /* Accept anything that can be used as a source operand for a move | |
585 | instruction. */ | |
87ad11b0 | 586 | int |
dbd3d89d | 587 | move_src_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 588 | { |
589 | if (register_operand (op, mode)) | |
590 | return 1; | |
591 | ||
42faba01 | 592 | if (GET_CODE (op) == CONST_INT) |
d9d7c968 | 593 | return cint_ok_for_move (INTVAL (op)); |
87ad11b0 | 594 | |
dbd3d89d | 595 | if (GET_MODE (op) != mode) |
596 | return 0; | |
597 | ||
87ad11b0 | 598 | if (GET_CODE (op) == SUBREG) |
599 | op = SUBREG_REG (op); | |
dbd3d89d | 600 | |
87ad11b0 | 601 | if (GET_CODE (op) != MEM) |
602 | return 0; | |
603 | ||
dbd3d89d | 604 | /* Until problems with management of the REG_POINTER flag are resolved, |
605 | we need to delay creating move insns with unscaled indexed addresses | |
606 | until CSE is not expected. */ | |
607 | if (!TARGET_NO_SPACE_REGS | |
608 | && !cse_not_expected | |
609 | && GET_CODE (XEXP (op, 0)) == PLUS | |
610 | && REG_P (XEXP (XEXP (op, 0), 0)) | |
611 | && REG_P (XEXP (XEXP (op, 0), 1))) | |
612 | return 0; | |
27ef382d | 613 | |
dbd3d89d | 614 | return memory_address_p (mode, XEXP (op, 0)); |
87ad11b0 | 615 | } |
616 | ||
d1812381 | 617 | /* Accept anything that can be used as the source operand for a prefetch |
618 | instruction. */ | |
619 | int | |
620 | prefetch_operand (rtx op, enum machine_mode mode) | |
621 | { | |
622 | if (GET_CODE (op) != MEM) | |
623 | return 0; | |
624 | ||
625 | /* Until problems with management of the REG_POINTER flag are resolved, | |
626 | we need to delay creating prefetch insns with unscaled indexed addresses | |
627 | until CSE is not expected. */ | |
628 | if (!TARGET_NO_SPACE_REGS | |
629 | && !cse_not_expected | |
630 | && GET_CODE (XEXP (op, 0)) == PLUS | |
631 | && REG_P (XEXP (XEXP (op, 0), 0)) | |
632 | && REG_P (XEXP (XEXP (op, 0), 1))) | |
633 | return 0; | |
634 | ||
635 | return memory_address_p (mode, XEXP (op, 0)); | |
636 | } | |
637 | ||
6ecdbaa1 | 638 | /* Accept REG and any CONST_INT that can be moved in one instruction into a |
639 | general register. */ | |
640 | int | |
5c1d8983 | 641 | reg_or_cint_move_operand (rtx op, enum machine_mode mode) |
6ecdbaa1 | 642 | { |
643 | if (register_operand (op, mode)) | |
644 | return 1; | |
645 | ||
dbd3d89d | 646 | return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op))); |
6ecdbaa1 | 647 | } |
648 | ||
87ad11b0 | 649 | int |
5c1d8983 | 650 | pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 651 | { |
b4a7bf10 | 652 | if (!flag_pic) |
653 | return 0; | |
654 | ||
655 | switch (GET_CODE (op)) | |
656 | { | |
657 | case LABEL_REF: | |
658 | return 1; | |
b4a7bf10 | 659 | case CONST: |
660 | op = XEXP (op, 0); | |
3c69dc97 | 661 | return (GET_CODE (XEXP (op, 0)) == LABEL_REF |
b4a7bf10 | 662 | && GET_CODE (XEXP (op, 1)) == CONST_INT); |
663 | default: | |
664 | return 0; | |
665 | } | |
87ad11b0 | 666 | } |
667 | ||
87ad11b0 | 668 | int |
5c1d8983 | 669 | fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 670 | { |
671 | return reg_renumber && FP_REG_P (op); | |
672 | } | |
d6f01525 | 673 | |
87ad11b0 | 674 | \f |
87ad11b0 | 675 | |
87ad11b0 | 676 | /* Return truth value of whether OP can be used as an operand in a |
677 | three operand arithmetic insn that accepts registers of mode MODE | |
678 | or 14-bit signed integers. */ | |
679 | int | |
5c1d8983 | 680 | arith_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 681 | { |
682 | return (register_operand (op, mode) | |
683 | || (GET_CODE (op) == CONST_INT && INT_14_BITS (op))); | |
684 | } | |
685 | ||
686 | /* Return truth value of whether OP can be used as an operand in a | |
687 | three operand arithmetic insn that accepts registers of mode MODE | |
688 | or 11-bit signed integers. */ | |
689 | int | |
5c1d8983 | 690 | arith11_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 691 | { |
692 | return (register_operand (op, mode) | |
693 | || (GET_CODE (op) == CONST_INT && INT_11_BITS (op))); | |
694 | } | |
695 | ||
2a91e628 | 696 | /* Return truth value of whether OP can be used as an operand in a |
697 | adddi3 insn. */ | |
698 | int | |
5c1d8983 | 699 | adddi3_operand (rtx op, enum machine_mode mode) |
2a91e628 | 700 | { |
701 | return (register_operand (op, mode) | |
702 | || (GET_CODE (op) == CONST_INT | |
703 | && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op)))); | |
704 | } | |
705 | ||
6d36483b | 706 | /* A constant integer suitable for use in a PRE_MODIFY memory |
757d4970 | 707 | reference. */ |
42faba01 | 708 | int |
5c1d8983 | 709 | pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
42faba01 | 710 | { |
711 | return (GET_CODE (op) == CONST_INT | |
712 | && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10); | |
713 | } | |
714 | ||
6d36483b | 715 | /* A constant integer suitable for use in a POST_MODIFY memory |
757d4970 | 716 | reference. */ |
717 | int | |
5c1d8983 | 718 | post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
757d4970 | 719 | { |
720 | return (GET_CODE (op) == CONST_INT | |
721 | && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10); | |
722 | } | |
723 | ||
87ad11b0 | 724 | int |
5c1d8983 | 725 | arith_double_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 726 | { |
727 | return (register_operand (op, mode) | |
728 | || (GET_CODE (op) == CONST_DOUBLE | |
729 | && GET_MODE (op) == mode | |
730 | && VAL_14_BITS_P (CONST_DOUBLE_LOW (op)) | |
1fe9d310 | 731 | && ((CONST_DOUBLE_HIGH (op) >= 0) |
87ad11b0 | 732 | == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0)))); |
733 | } | |
734 | ||
45981c0a | 735 | /* Return truth value of whether OP is an integer which fits the |
546a40bd | 736 | range constraining immediate operands in three-address insns, or |
737 | is an integer register. */ | |
738 | ||
739 | int | |
5c1d8983 | 740 | ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
546a40bd | 741 | { |
742 | return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op)) | |
743 | || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32)); | |
744 | } | |
745 | ||
c7ae93c8 | 746 | /* Return nonzero if OP is an integer register, else return zero. */ |
747 | int | |
5c1d8983 | 748 | ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
c7ae93c8 | 749 | { |
750 | return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32); | |
751 | } | |
752 | ||
45981c0a | 753 | /* Return truth value of whether OP is an integer which fits the |
87ad11b0 | 754 | range constraining immediate operands in three-address insns. */ |
755 | ||
756 | int | |
5c1d8983 | 757 | int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 758 | { |
759 | return (GET_CODE (op) == CONST_INT && INT_5_BITS (op)); | |
760 | } | |
761 | ||
762 | int | |
5c1d8983 | 763 | uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 764 | { |
765 | return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op)); | |
766 | } | |
767 | ||
87ad11b0 | 768 | int |
5c1d8983 | 769 | int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 770 | { |
6d36483b | 771 | return (GET_CODE (op) == CONST_INT && INT_11_BITS (op)); |
772 | } | |
773 | ||
774 | int | |
5c1d8983 | 775 | uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
6d36483b | 776 | { |
777 | #if HOST_BITS_PER_WIDE_INT > 32 | |
778 | /* All allowed constants will fit a CONST_INT. */ | |
779 | return (GET_CODE (op) == CONST_INT | |
b7d86581 | 780 | && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32)); |
6d36483b | 781 | #else |
782 | return (GET_CODE (op) == CONST_INT | |
783 | || (GET_CODE (op) == CONST_DOUBLE | |
784 | && CONST_DOUBLE_HIGH (op) == 0)); | |
785 | #endif | |
87ad11b0 | 786 | } |
787 | ||
788 | int | |
5c1d8983 | 789 | arith5_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 790 | { |
791 | return register_operand (op, mode) || int5_operand (op, mode); | |
792 | } | |
793 | ||
ea52c577 | 794 | /* True iff zdepi can be used to generate this CONST_INT. |
795 | zdepi first sign extends a 5 bit signed number to a given field | |
796 | length, then places this field anywhere in a zero. */ | |
e057641f | 797 | int |
5c1d8983 | 798 | zdepi_cint_p (unsigned HOST_WIDE_INT x) |
fad0b60f | 799 | { |
3745c59b | 800 | unsigned HOST_WIDE_INT lsb_mask, t; |
fad0b60f | 801 | |
802 | /* This might not be obvious, but it's at least fast. | |
01cc3b75 | 803 | This function is critical; we don't have the time loops would take. */ |
42faba01 | 804 | lsb_mask = x & -x; |
805 | t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1); | |
806 | /* Return true iff t is a power of two. */ | |
fad0b60f | 807 | return ((t & (t - 1)) == 0); |
808 | } | |
809 | ||
6d36483b | 810 | /* True iff depi or extru can be used to compute (reg & mask). |
811 | Accept bit pattern like these: | |
812 | 0....01....1 | |
813 | 1....10....0 | |
814 | 1..10..01..1 */ | |
e057641f | 815 | int |
5c1d8983 | 816 | and_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 817 | { |
818 | mask = ~mask; | |
819 | mask += mask & -mask; | |
820 | return (mask & (mask - 1)) == 0; | |
821 | } | |
822 | ||
823 | /* True iff depi or extru can be used to compute (reg & OP). */ | |
824 | int | |
5c1d8983 | 825 | and_operand (rtx op, enum machine_mode mode) |
e057641f | 826 | { |
827 | return (register_operand (op, mode) | |
42faba01 | 828 | || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op)))); |
e057641f | 829 | } |
830 | ||
831 | /* True iff depi can be used to compute (reg | MASK). */ | |
832 | int | |
5c1d8983 | 833 | ior_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 834 | { |
835 | mask += mask & -mask; | |
836 | return (mask & (mask - 1)) == 0; | |
837 | } | |
838 | ||
839 | /* True iff depi can be used to compute (reg | OP). */ | |
840 | int | |
5c1d8983 | 841 | ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e057641f | 842 | { |
b744c8cb | 843 | return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op))); |
e057641f | 844 | } |
845 | ||
e5965947 | 846 | int |
5c1d8983 | 847 | lhs_lshift_operand (rtx op, enum machine_mode mode) |
e5965947 | 848 | { |
849 | return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode); | |
850 | } | |
851 | ||
852 | /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx. | |
853 | Such values can be the left hand side x in (x << r), using the zvdepi | |
854 | instruction. */ | |
855 | int | |
5c1d8983 | 856 | lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
e5965947 | 857 | { |
3745c59b | 858 | unsigned HOST_WIDE_INT x; |
e5965947 | 859 | if (GET_CODE (op) != CONST_INT) |
860 | return 0; | |
861 | x = INTVAL (op) >> 4; | |
862 | return (x & (x + 1)) == 0; | |
863 | } | |
864 | ||
9c6d4825 | 865 | int |
5c1d8983 | 866 | arith32_operand (rtx op, enum machine_mode mode) |
9c6d4825 | 867 | { |
868 | return register_operand (op, mode) || GET_CODE (op) == CONST_INT; | |
869 | } | |
ead9285f | 870 | |
871 | int | |
5c1d8983 | 872 | pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
ead9285f | 873 | { |
874 | return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF); | |
875 | } | |
87ad11b0 | 876 | \f |
877 | /* Legitimize PIC addresses. If the address is already | |
878 | position-independent, we return ORIG. Newly generated | |
879 | position-independent addresses go to REG. If we need more | |
880 | than one register, we lose. */ | |
881 | ||
882 | rtx | |
5c1d8983 | 883 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
87ad11b0 | 884 | { |
885 | rtx pic_ref = orig; | |
886 | ||
b090827b | 887 | /* Labels need special handling. */ |
611a88e1 | 888 | if (pic_label_operand (orig, mode)) |
b4a7bf10 | 889 | { |
2536cc16 | 890 | /* We do not want to go through the movXX expanders here since that |
891 | would create recursion. | |
892 | ||
893 | Nor do we really want to call a generator for a named pattern | |
894 | since that requires multiple patterns if we want to support | |
895 | multiple word sizes. | |
896 | ||
897 | So instead we just emit the raw set, which avoids the movXX | |
898 | expanders completely. */ | |
dbd3d89d | 899 | mark_reg_pointer (reg, BITS_PER_UNIT); |
2536cc16 | 900 | emit_insn (gen_rtx_SET (VOIDmode, reg, orig)); |
b4a7bf10 | 901 | current_function_uses_pic_offset_table = 1; |
902 | return reg; | |
903 | } | |
87ad11b0 | 904 | if (GET_CODE (orig) == SYMBOL_REF) |
905 | { | |
f9c1ba9d | 906 | rtx insn, tmp_reg; |
907 | ||
87ad11b0 | 908 | if (reg == 0) |
909 | abort (); | |
910 | ||
f9c1ba9d | 911 | /* Before reload, allocate a temporary register for the intermediate |
912 | result. This allows the sequence to be deleted when the final | |
913 | result is unused and the insns are trivially dead. */ | |
914 | tmp_reg = ((reload_in_progress || reload_completed) | |
915 | ? reg : gen_reg_rtx (Pmode)); | |
916 | ||
917 | emit_move_insn (tmp_reg, | |
fc44315f | 918 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, |
919 | gen_rtx_HIGH (word_mode, orig))); | |
920 | pic_ref | |
921 | = gen_rtx_MEM (Pmode, | |
f9c1ba9d | 922 | gen_rtx_LO_SUM (Pmode, tmp_reg, |
fc44315f | 923 | gen_rtx_UNSPEC (Pmode, |
924 | gen_rtvec (1, orig), | |
ebd5cf7c | 925 | UNSPEC_DLTIND14R))); |
7014838c | 926 | |
87ad11b0 | 927 | current_function_uses_pic_offset_table = 1; |
f9c1ba9d | 928 | MEM_NOTRAP_P (pic_ref) = 1; |
87ad11b0 | 929 | RTX_UNCHANGING_P (pic_ref) = 1; |
dbd3d89d | 930 | mark_reg_pointer (reg, BITS_PER_UNIT); |
f9c1ba9d | 931 | insn = emit_move_insn (reg, pic_ref); |
932 | ||
933 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
934 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn)); | |
935 | ||
87ad11b0 | 936 | return reg; |
937 | } | |
938 | else if (GET_CODE (orig) == CONST) | |
939 | { | |
57ed30e5 | 940 | rtx base; |
87ad11b0 | 941 | |
942 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
943 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
944 | return orig; | |
945 | ||
946 | if (reg == 0) | |
947 | abort (); | |
948 | ||
949 | if (GET_CODE (XEXP (orig, 0)) == PLUS) | |
950 | { | |
951 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
952 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
953 | base == reg ? 0 : reg); | |
954 | } | |
dbd3d89d | 955 | else |
956 | abort (); | |
957 | ||
87ad11b0 | 958 | if (GET_CODE (orig) == CONST_INT) |
959 | { | |
42faba01 | 960 | if (INT_14_BITS (orig)) |
b244d4c7 | 961 | return plus_constant (base, INTVAL (orig)); |
87ad11b0 | 962 | orig = force_reg (Pmode, orig); |
963 | } | |
ad851752 | 964 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
87ad11b0 | 965 | /* Likewise, should we set special REG_NOTEs here? */ |
966 | } | |
dbd3d89d | 967 | |
87ad11b0 | 968 | return pic_ref; |
969 | } | |
970 | ||
347b5848 | 971 | /* Try machine-dependent ways of modifying an illegitimate address |
972 | to be legitimate. If we find one, return the new, valid address. | |
973 | This macro is used in only one place: `memory_address' in explow.c. | |
974 | ||
975 | OLDX is the address as it was before break_out_memory_refs was called. | |
976 | In some cases it is useful to look at this to decide what needs to be done. | |
977 | ||
978 | MODE and WIN are passed so that this macro can use | |
979 | GO_IF_LEGITIMATE_ADDRESS. | |
980 | ||
981 | It is always safe for this macro to do nothing. It exists to recognize | |
6d36483b | 982 | opportunities to optimize the output. |
347b5848 | 983 | |
984 | For the PA, transform: | |
985 | ||
986 | memory(X + <large int>) | |
987 | ||
988 | into: | |
989 | ||
990 | if (<large int> & mask) >= 16 | |
991 | Y = (<large int> & ~mask) + mask + 1 Round up. | |
992 | else | |
993 | Y = (<large int> & ~mask) Round down. | |
994 | Z = X + Y | |
995 | memory (Z + (<large int> - Y)); | |
996 | ||
6d36483b | 997 | This is for CSE to find several similar references, and only use one Z. |
347b5848 | 998 | |
999 | X can either be a SYMBOL_REF or REG, but because combine can not | |
1000 | perform a 4->2 combination we do nothing for SYMBOL_REF + D where | |
1001 | D will not fit in 14 bits. | |
1002 | ||
1003 | MODE_FLOAT references allow displacements which fit in 5 bits, so use | |
6d36483b | 1004 | 0x1f as the mask. |
347b5848 | 1005 | |
1006 | MODE_INT references allow displacements which fit in 14 bits, so use | |
6d36483b | 1007 | 0x3fff as the mask. |
347b5848 | 1008 | |
1009 | This relies on the fact that most mode MODE_FLOAT references will use FP | |
1010 | registers and most mode MODE_INT references will use integer registers. | |
1011 | (In the rare case of an FP register used in an integer MODE, we depend | |
1012 | on secondary reloads to clean things up.) | |
1013 | ||
1014 | ||
1015 | It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special | |
1016 | manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed | |
01cc3b75 | 1017 | addressing modes to be used). |
347b5848 | 1018 | |
1019 | Put X and Z into registers. Then put the entire expression into | |
1020 | a register. */ | |
1021 | ||
1022 | rtx | |
5c1d8983 | 1023 | hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1024 | enum machine_mode mode) | |
347b5848 | 1025 | { |
347b5848 | 1026 | rtx orig = x; |
1027 | ||
dbd3d89d | 1028 | /* We need to canonicalize the order of operands in unscaled indexed |
1029 | addresses since the code that checks if an address is valid doesn't | |
1030 | always try both orders. */ | |
1031 | if (!TARGET_NO_SPACE_REGS | |
1032 | && GET_CODE (x) == PLUS | |
1033 | && GET_MODE (x) == Pmode | |
1034 | && REG_P (XEXP (x, 0)) | |
1035 | && REG_P (XEXP (x, 1)) | |
1036 | && REG_POINTER (XEXP (x, 0)) | |
1037 | && !REG_POINTER (XEXP (x, 1))) | |
1038 | return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0)); | |
1039 | ||
b4a7bf10 | 1040 | if (flag_pic) |
1041 | return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); | |
1042 | ||
6dc3b0d9 | 1043 | /* Strip off CONST. */ |
347b5848 | 1044 | if (GET_CODE (x) == CONST) |
1045 | x = XEXP (x, 0); | |
1046 | ||
42819d4e | 1047 | /* Special case. Get the SYMBOL_REF into a register and use indexing. |
1048 | That should always be safe. */ | |
1049 | if (GET_CODE (x) == PLUS | |
1050 | && GET_CODE (XEXP (x, 0)) == REG | |
1051 | && GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
1052 | { | |
440c23df | 1053 | rtx reg = force_reg (Pmode, XEXP (x, 1)); |
1054 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0))); | |
42819d4e | 1055 | } |
1056 | ||
166bf021 | 1057 | /* Note we must reject symbols which represent function addresses |
1058 | since the assembler/linker can't handle arithmetic on plabels. */ | |
347b5848 | 1059 | if (GET_CODE (x) == PLUS |
1060 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
166bf021 | 1061 | && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF |
1062 | && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0))) | |
347b5848 | 1063 | || GET_CODE (XEXP (x, 0)) == REG)) |
1064 | { | |
1065 | rtx int_part, ptr_reg; | |
1066 | int newoffset; | |
1067 | int offset = INTVAL (XEXP (x, 1)); | |
1b6f11e2 | 1068 | int mask; |
1069 | ||
1070 | mask = (GET_MODE_CLASS (mode) == MODE_FLOAT | |
1071 | ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff); | |
347b5848 | 1072 | |
6d36483b | 1073 | /* Choose which way to round the offset. Round up if we |
347b5848 | 1074 | are >= halfway to the next boundary. */ |
1075 | if ((offset & mask) >= ((mask + 1) / 2)) | |
1076 | newoffset = (offset & ~ mask) + mask + 1; | |
1077 | else | |
1078 | newoffset = (offset & ~ mask); | |
1079 | ||
1080 | /* If the newoffset will not fit in 14 bits (ldo), then | |
1081 | handling this would take 4 or 5 instructions (2 to load | |
1082 | the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to | |
1083 | add the new offset and the SYMBOL_REF.) Combine can | |
1084 | not handle 4->2 or 5->2 combinations, so do not create | |
1085 | them. */ | |
1086 | if (! VAL_14_BITS_P (newoffset) | |
1087 | && GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
1088 | { | |
7014838c | 1089 | rtx const_part = plus_constant (XEXP (x, 0), newoffset); |
347b5848 | 1090 | rtx tmp_reg |
339613b4 | 1091 | = force_reg (Pmode, |
ad851752 | 1092 | gen_rtx_HIGH (Pmode, const_part)); |
347b5848 | 1093 | ptr_reg |
339613b4 | 1094 | = force_reg (Pmode, |
7014838c | 1095 | gen_rtx_LO_SUM (Pmode, |
1096 | tmp_reg, const_part)); | |
347b5848 | 1097 | } |
1098 | else | |
1099 | { | |
1100 | if (! VAL_14_BITS_P (newoffset)) | |
339613b4 | 1101 | int_part = force_reg (Pmode, GEN_INT (newoffset)); |
347b5848 | 1102 | else |
1103 | int_part = GEN_INT (newoffset); | |
1104 | ||
339613b4 | 1105 | ptr_reg = force_reg (Pmode, |
ad851752 | 1106 | gen_rtx_PLUS (Pmode, |
1107 | force_reg (Pmode, XEXP (x, 0)), | |
1108 | int_part)); | |
347b5848 | 1109 | } |
1110 | return plus_constant (ptr_reg, offset - newoffset); | |
1111 | } | |
45f1285a | 1112 | |
5115683e | 1113 | /* Handle (plus (mult (a) (shadd_constant)) (b)). */ |
45f1285a | 1114 | |
347b5848 | 1115 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT |
1116 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
45f1285a | 1117 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))) |
6720e96c | 1118 | && (OBJECT_P (XEXP (x, 1)) |
45f1285a | 1119 | || GET_CODE (XEXP (x, 1)) == SUBREG) |
1120 | && GET_CODE (XEXP (x, 1)) != CONST) | |
347b5848 | 1121 | { |
1122 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1123 | rtx reg1, reg2; | |
5115683e | 1124 | |
1125 | reg1 = XEXP (x, 1); | |
1126 | if (GET_CODE (reg1) != REG) | |
1127 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1128 | ||
1129 | reg2 = XEXP (XEXP (x, 0), 0); | |
1130 | if (GET_CODE (reg2) != REG) | |
1131 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1132 | ||
ad851752 | 1133 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1134 | gen_rtx_MULT (Pmode, |
1135 | reg2, | |
1136 | GEN_INT (val)), | |
ad851752 | 1137 | reg1)); |
347b5848 | 1138 | } |
45f1285a | 1139 | |
00a87639 | 1140 | /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)). |
1141 | ||
1142 | Only do so for floating point modes since this is more speculative | |
1143 | and we lose if it's an integer store. */ | |
5115683e | 1144 | if (GET_CODE (x) == PLUS |
00a87639 | 1145 | && GET_CODE (XEXP (x, 0)) == PLUS |
1146 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
1147 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
5115683e | 1148 | && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) |
1149 | && (mode == SFmode || mode == DFmode)) | |
00a87639 | 1150 | { |
5115683e | 1151 | |
1152 | /* First, try and figure out what to use as a base register. */ | |
1153 | rtx reg1, reg2, base, idx, orig_base; | |
1154 | ||
1155 | reg1 = XEXP (XEXP (x, 0), 1); | |
1156 | reg2 = XEXP (x, 1); | |
1157 | base = NULL_RTX; | |
1158 | idx = NULL_RTX; | |
1159 | ||
1160 | /* Make sure they're both regs. If one was a SYMBOL_REF [+ const], | |
e61a0a7f | 1161 | then emit_move_sequence will turn on REG_POINTER so we'll know |
1162 | it's a base register below. */ | |
5115683e | 1163 | if (GET_CODE (reg1) != REG) |
1164 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1165 | ||
1166 | if (GET_CODE (reg2) != REG) | |
1167 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1168 | ||
1169 | /* Figure out what the base and index are. */ | |
9840d99d | 1170 | |
5115683e | 1171 | if (GET_CODE (reg1) == REG |
e61a0a7f | 1172 | && REG_POINTER (reg1)) |
5115683e | 1173 | { |
1174 | base = reg1; | |
1175 | orig_base = XEXP (XEXP (x, 0), 1); | |
ad851752 | 1176 | idx = gen_rtx_PLUS (Pmode, |
1177 | gen_rtx_MULT (Pmode, | |
1178 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
1179 | XEXP (XEXP (XEXP (x, 0), 0), 1)), | |
1180 | XEXP (x, 1)); | |
5115683e | 1181 | } |
1182 | else if (GET_CODE (reg2) == REG | |
e61a0a7f | 1183 | && REG_POINTER (reg2)) |
5115683e | 1184 | { |
1185 | base = reg2; | |
1186 | orig_base = XEXP (x, 1); | |
1187 | idx = XEXP (x, 0); | |
1188 | } | |
1189 | ||
1190 | if (base == 0) | |
21f3ee9c | 1191 | return orig; |
5115683e | 1192 | |
1193 | /* If the index adds a large constant, try to scale the | |
1194 | constant so that it can be loaded with only one insn. */ | |
1195 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1196 | && VAL_14_BITS_P (INTVAL (XEXP (idx, 1)) | |
1197 | / INTVAL (XEXP (XEXP (idx, 0), 1))) | |
1198 | && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0) | |
1199 | { | |
1200 | /* Divide the CONST_INT by the scale factor, then add it to A. */ | |
1201 | int val = INTVAL (XEXP (idx, 1)); | |
1202 | ||
1203 | val /= INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1204 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1205 | if (GET_CODE (reg1) != REG) | |
1206 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1207 | ||
ad851752 | 1208 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val))); |
5115683e | 1209 | |
1210 | /* We can now generate a simple scaled indexed address. */ | |
7014838c | 1211 | return |
1212 | force_reg | |
1213 | (Pmode, gen_rtx_PLUS (Pmode, | |
1214 | gen_rtx_MULT (Pmode, reg1, | |
1215 | XEXP (XEXP (idx, 0), 1)), | |
1216 | base)); | |
5115683e | 1217 | } |
1218 | ||
1219 | /* If B + C is still a valid base register, then add them. */ | |
1220 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1221 | && INTVAL (XEXP (idx, 1)) <= 4096 | |
1222 | && INTVAL (XEXP (idx, 1)) >= -4096) | |
1223 | { | |
1224 | int val = INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1225 | rtx reg1, reg2; | |
1226 | ||
ad851752 | 1227 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1))); |
5115683e | 1228 | |
1229 | reg2 = XEXP (XEXP (idx, 0), 0); | |
1230 | if (GET_CODE (reg2) != CONST_INT) | |
1231 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1232 | ||
ad851752 | 1233 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1234 | gen_rtx_MULT (Pmode, |
1235 | reg2, | |
ad851752 | 1236 | GEN_INT (val)), |
1237 | reg1)); | |
5115683e | 1238 | } |
1239 | ||
1240 | /* Get the index into a register, then add the base + index and | |
1241 | return a register holding the result. */ | |
1242 | ||
1243 | /* First get A into a register. */ | |
1244 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1245 | if (GET_CODE (reg1) != REG) | |
1246 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1247 | ||
1248 | /* And get B into a register. */ | |
1249 | reg2 = XEXP (idx, 1); | |
1250 | if (GET_CODE (reg2) != REG) | |
1251 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1252 | ||
ad851752 | 1253 | reg1 = force_reg (Pmode, |
1254 | gen_rtx_PLUS (Pmode, | |
1255 | gen_rtx_MULT (Pmode, reg1, | |
1256 | XEXP (XEXP (idx, 0), 1)), | |
1257 | reg2)); | |
5115683e | 1258 | |
1259 | /* Add the result to our base register and return. */ | |
ad851752 | 1260 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1)); |
9840d99d | 1261 | |
00a87639 | 1262 | } |
1263 | ||
6d36483b | 1264 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
fb5390c1 | 1265 | special handling to avoid creating an indexed memory address |
1266 | with x-100000 as the base. | |
9840d99d | 1267 | |
fb5390c1 | 1268 | If the constant part is small enough, then it's still safe because |
1269 | there is a guard page at the beginning and end of the data segment. | |
1270 | ||
1271 | Scaled references are common enough that we want to try and rearrange the | |
1272 | terms so that we can use indexing for these addresses too. Only | |
00a87639 | 1273 | do the optimization for floatint point modes. */ |
45f1285a | 1274 | |
fb5390c1 | 1275 | if (GET_CODE (x) == PLUS |
1276 | && symbolic_expression_p (XEXP (x, 1))) | |
45f1285a | 1277 | { |
1278 | /* Ugly. We modify things here so that the address offset specified | |
1279 | by the index expression is computed first, then added to x to form | |
fb5390c1 | 1280 | the entire address. */ |
45f1285a | 1281 | |
00a87639 | 1282 | rtx regx1, regx2, regy1, regy2, y; |
45f1285a | 1283 | |
1284 | /* Strip off any CONST. */ | |
1285 | y = XEXP (x, 1); | |
1286 | if (GET_CODE (y) == CONST) | |
1287 | y = XEXP (y, 0); | |
1288 | ||
7ee96d6e | 1289 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1290 | { | |
00a87639 | 1291 | /* See if this looks like |
1292 | (plus (mult (reg) (shadd_const)) | |
1293 | (const (plus (symbol_ref) (const_int)))) | |
1294 | ||
5115683e | 1295 | Where const_int is small. In that case the const |
9840d99d | 1296 | expression is a valid pointer for indexing. |
5115683e | 1297 | |
1298 | If const_int is big, but can be divided evenly by shadd_const | |
1299 | and added to (reg). This allows more scaled indexed addresses. */ | |
1300 | if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1301 | && GET_CODE (XEXP (x, 0)) == MULT | |
00a87639 | 1302 | && GET_CODE (XEXP (y, 1)) == CONST_INT |
5115683e | 1303 | && INTVAL (XEXP (y, 1)) >= -4096 |
1304 | && INTVAL (XEXP (y, 1)) <= 4095 | |
1305 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1306 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
1307 | { | |
1308 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1309 | rtx reg1, reg2; | |
1310 | ||
1311 | reg1 = XEXP (x, 1); | |
1312 | if (GET_CODE (reg1) != REG) | |
1313 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1314 | ||
1315 | reg2 = XEXP (XEXP (x, 0), 0); | |
1316 | if (GET_CODE (reg2) != REG) | |
1317 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1318 | ||
ad851752 | 1319 | return force_reg (Pmode, |
1320 | gen_rtx_PLUS (Pmode, | |
7014838c | 1321 | gen_rtx_MULT (Pmode, |
1322 | reg2, | |
ad851752 | 1323 | GEN_INT (val)), |
7014838c | 1324 | reg1)); |
5115683e | 1325 | } |
1326 | else if ((mode == DFmode || mode == SFmode) | |
1327 | && GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1328 | && GET_CODE (XEXP (x, 0)) == MULT | |
1329 | && GET_CODE (XEXP (y, 1)) == CONST_INT | |
1330 | && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0 | |
1331 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1332 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
00a87639 | 1333 | { |
1334 | regx1 | |
1335 | = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1)) | |
1336 | / INTVAL (XEXP (XEXP (x, 0), 1)))); | |
1337 | regx2 = XEXP (XEXP (x, 0), 0); | |
1338 | if (GET_CODE (regx2) != REG) | |
1339 | regx2 = force_reg (Pmode, force_operand (regx2, 0)); | |
ad851752 | 1340 | regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1341 | regx2, regx1)); | |
7014838c | 1342 | return |
1343 | force_reg (Pmode, | |
1344 | gen_rtx_PLUS (Pmode, | |
1345 | gen_rtx_MULT (Pmode, regx2, | |
1346 | XEXP (XEXP (x, 0), 1)), | |
1347 | force_reg (Pmode, XEXP (y, 0)))); | |
00a87639 | 1348 | } |
fb5390c1 | 1349 | else if (GET_CODE (XEXP (y, 1)) == CONST_INT |
1350 | && INTVAL (XEXP (y, 1)) >= -4096 | |
1351 | && INTVAL (XEXP (y, 1)) <= 4095) | |
1352 | { | |
1353 | /* This is safe because of the guard page at the | |
1354 | beginning and end of the data space. Just | |
1355 | return the original address. */ | |
1356 | return orig; | |
1357 | } | |
00a87639 | 1358 | else |
1359 | { | |
1360 | /* Doesn't look like one we can optimize. */ | |
1361 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1362 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1363 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1364 | regx1 = force_reg (Pmode, | |
ad851752 | 1365 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1366 | regx1, regy2)); | |
1367 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); | |
00a87639 | 1368 | } |
7ee96d6e | 1369 | } |
45f1285a | 1370 | } |
1371 | ||
347b5848 | 1372 | return orig; |
1373 | } | |
1374 | ||
87ad11b0 | 1375 | /* For the HPPA, REG and REG+CONST is cost 0 |
1376 | and addresses involving symbolic constants are cost 2. | |
1377 | ||
1378 | PIC addresses are very expensive. | |
1379 | ||
1380 | It is no coincidence that this has the same structure | |
1381 | as GO_IF_LEGITIMATE_ADDRESS. */ | |
ec0457a8 | 1382 | |
1383 | static int | |
5c1d8983 | 1384 | hppa_address_cost (rtx X) |
87ad11b0 | 1385 | { |
ec0457a8 | 1386 | switch (GET_CODE (X)) |
1387 | { | |
1388 | case REG: | |
1389 | case PLUS: | |
1390 | case LO_SUM: | |
87ad11b0 | 1391 | return 1; |
ec0457a8 | 1392 | case HIGH: |
1393 | return 2; | |
1394 | default: | |
1395 | return 4; | |
1396 | } | |
87ad11b0 | 1397 | } |
1398 | ||
fab7adbf | 1399 | /* Compute a (partial) cost for rtx X. Return true if the complete |
1400 | cost has been computed, and false if subexpressions should be | |
1401 | scanned. In either case, *TOTAL contains the cost result. */ | |
1402 | ||
1403 | static bool | |
5c1d8983 | 1404 | hppa_rtx_costs (rtx x, int code, int outer_code, int *total) |
fab7adbf | 1405 | { |
1406 | switch (code) | |
1407 | { | |
1408 | case CONST_INT: | |
1409 | if (INTVAL (x) == 0) | |
1410 | *total = 0; | |
1411 | else if (INT_14_BITS (x)) | |
1412 | *total = 1; | |
1413 | else | |
1414 | *total = 2; | |
1415 | return true; | |
1416 | ||
1417 | case HIGH: | |
1418 | *total = 2; | |
1419 | return true; | |
1420 | ||
1421 | case CONST: | |
1422 | case LABEL_REF: | |
1423 | case SYMBOL_REF: | |
1424 | *total = 4; | |
1425 | return true; | |
1426 | ||
1427 | case CONST_DOUBLE: | |
1428 | if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode)) | |
1429 | && outer_code != SET) | |
1430 | *total = 0; | |
1431 | else | |
1432 | *total = 8; | |
1433 | return true; | |
1434 | ||
1435 | case MULT: | |
1436 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1437 | *total = COSTS_N_INSNS (3); | |
1438 | else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT) | |
1439 | *total = COSTS_N_INSNS (8); | |
1440 | else | |
1441 | *total = COSTS_N_INSNS (20); | |
1442 | return true; | |
1443 | ||
1444 | case DIV: | |
1445 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1446 | { | |
1447 | *total = COSTS_N_INSNS (14); | |
1448 | return true; | |
1449 | } | |
8e262b5e | 1450 | /* FALLTHRU */ |
fab7adbf | 1451 | |
1452 | case UDIV: | |
1453 | case MOD: | |
1454 | case UMOD: | |
1455 | *total = COSTS_N_INSNS (60); | |
1456 | return true; | |
1457 | ||
1458 | case PLUS: /* this includes shNadd insns */ | |
1459 | case MINUS: | |
1460 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1461 | *total = COSTS_N_INSNS (3); | |
1462 | else | |
1463 | *total = COSTS_N_INSNS (1); | |
1464 | return true; | |
1465 | ||
1466 | case ASHIFT: | |
1467 | case ASHIFTRT: | |
1468 | case LSHIFTRT: | |
1469 | *total = COSTS_N_INSNS (1); | |
1470 | return true; | |
1471 | ||
1472 | default: | |
1473 | return false; | |
1474 | } | |
1475 | } | |
1476 | ||
9840d99d | 1477 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a |
1478 | new rtx with the correct mode. */ | |
1479 | static inline rtx | |
5c1d8983 | 1480 | force_mode (enum machine_mode mode, rtx orig) |
9840d99d | 1481 | { |
1482 | if (mode == GET_MODE (orig)) | |
1483 | return orig; | |
1484 | ||
1485 | if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) | |
1486 | abort (); | |
1487 | ||
1488 | return gen_rtx_REG (mode, REGNO (orig)); | |
1489 | } | |
1490 | ||
87ad11b0 | 1491 | /* Emit insns to move operands[1] into operands[0]. |
1492 | ||
1493 | Return 1 if we have written out everything that needs to be done to | |
1494 | do the move. Otherwise, return 0 and the caller will emit the move | |
9840d99d | 1495 | normally. |
f756078b | 1496 | |
1497 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
2cecd772 | 1498 | will be used. This routine is responsible for creating a new copy |
f756078b | 1499 | of SCRATCH_REG in the proper mode. */ |
87ad11b0 | 1500 | |
1501 | int | |
5c1d8983 | 1502 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) |
87ad11b0 | 1503 | { |
1504 | register rtx operand0 = operands[0]; | |
1505 | register rtx operand1 = operands[1]; | |
4a155b0f | 1506 | register rtx tem; |
87ad11b0 | 1507 | |
dbd3d89d | 1508 | /* We can only handle indexed addresses in the destination operand |
1509 | of floating point stores. Thus, we need to break out indexed | |
1510 | addresses from the destination operand. */ | |
1511 | if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0))) | |
1512 | { | |
1513 | /* This is only safe up to the beginning of life analysis. */ | |
1514 | if (no_new_pseudos) | |
1515 | abort (); | |
1516 | ||
1517 | tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0)); | |
1518 | operand0 = replace_equiv_address (operand0, tem); | |
1519 | } | |
1520 | ||
1521 | /* On targets with non-equivalent space registers, break out unscaled | |
1522 | indexed addresses from the source operand before the final CSE. | |
1523 | We have to do this because the REG_POINTER flag is not correctly | |
1524 | carried through various optimization passes and CSE may substitute | |
1525 | a pseudo without the pointer set for one with the pointer set. As | |
5aedf60c | 1526 | a result, we loose various opportunities to create insns with |
dbd3d89d | 1527 | unscaled indexed addresses. */ |
1528 | if (!TARGET_NO_SPACE_REGS | |
1529 | && !cse_not_expected | |
1530 | && GET_CODE (operand1) == MEM | |
1531 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1532 | && REG_P (XEXP (XEXP (operand1, 0), 0)) | |
1533 | && REG_P (XEXP (XEXP (operand1, 0), 1))) | |
1534 | operand1 | |
1535 | = replace_equiv_address (operand1, | |
1536 | copy_to_mode_reg (Pmode, XEXP (operand1, 0))); | |
1537 | ||
2d4dc8d2 | 1538 | if (scratch_reg |
1539 | && reload_in_progress && GET_CODE (operand0) == REG | |
d1e2bb73 | 1540 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) |
1541 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2d4dc8d2 | 1542 | else if (scratch_reg |
1543 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
d1e2bb73 | 1544 | && GET_CODE (SUBREG_REG (operand0)) == REG |
1545 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1546 | { |
701e46d0 | 1547 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1548 | the code which tracks sets/uses for delete_output_reload. */ |
1549 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
1550 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
701e46d0 | 1551 | SUBREG_BYTE (operand0)); |
e00b80b2 | 1552 | operand0 = alter_subreg (&temp); |
a3afad75 | 1553 | } |
d1e2bb73 | 1554 | |
2d4dc8d2 | 1555 | if (scratch_reg |
1556 | && reload_in_progress && GET_CODE (operand1) == REG | |
d1e2bb73 | 1557 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) |
1558 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2d4dc8d2 | 1559 | else if (scratch_reg |
1560 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
d1e2bb73 | 1561 | && GET_CODE (SUBREG_REG (operand1)) == REG |
1562 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1563 | { |
701e46d0 | 1564 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1565 | the code which tracks sets/uses for delete_output_reload. */ |
1566 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
1567 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
701e46d0 | 1568 | SUBREG_BYTE (operand1)); |
e00b80b2 | 1569 | operand1 = alter_subreg (&temp); |
a3afad75 | 1570 | } |
d1e2bb73 | 1571 | |
2d4dc8d2 | 1572 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM |
4a155b0f | 1573 | && ((tem = find_replacement (&XEXP (operand0, 0))) |
1574 | != XEXP (operand0, 0))) | |
ad851752 | 1575 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); |
dbd3d89d | 1576 | |
2d4dc8d2 | 1577 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM |
4a155b0f | 1578 | && ((tem = find_replacement (&XEXP (operand1, 0))) |
1579 | != XEXP (operand1, 0))) | |
ad851752 | 1580 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); |
4a155b0f | 1581 | |
e8fdbafa | 1582 | /* Handle secondary reloads for loads/stores of FP registers from |
047e3121 | 1583 | REG+D addresses where D does not fit in 5 or 14 bits, including |
42819d4e | 1584 | (subreg (mem (addr))) cases. */ |
6bcdc1fb | 1585 | if (scratch_reg |
1586 | && fp_reg_operand (operand0, mode) | |
6b1c36c2 | 1587 | && ((GET_CODE (operand1) == MEM |
047e3121 | 1588 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode), |
1589 | XEXP (operand1, 0))) | |
6b1c36c2 | 1590 | || ((GET_CODE (operand1) == SUBREG |
1591 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
047e3121 | 1592 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1593 | ? SFmode : DFmode), | |
1594 | XEXP (XEXP (operand1, 0), 0)))))) | |
d6f01525 | 1595 | { |
6b1c36c2 | 1596 | if (GET_CODE (operand1) == SUBREG) |
1597 | operand1 = XEXP (operand1, 0); | |
1598 | ||
f756078b | 1599 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1600 | it in WORD_MODE regardless of what mode it was originally given | |
1601 | to us. */ | |
9840d99d | 1602 | scratch_reg = force_mode (word_mode, scratch_reg); |
7ee39d73 | 1603 | |
1604 | /* D might not fit in 14 bits either; for such cases load D into | |
1605 | scratch reg. */ | |
440c23df | 1606 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) |
7ee39d73 | 1607 | { |
1608 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
dbd3d89d | 1609 | emit_move_insn (scratch_reg, |
1610 | gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
1611 | Pmode, | |
1612 | XEXP (XEXP (operand1, 0), 0), | |
1613 | scratch_reg)); | |
7ee39d73 | 1614 | } |
1615 | else | |
1616 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
7014838c | 1617 | emit_insn (gen_rtx_SET (VOIDmode, operand0, |
1618 | gen_rtx_MEM (mode, scratch_reg))); | |
d6f01525 | 1619 | return 1; |
1620 | } | |
6bcdc1fb | 1621 | else if (scratch_reg |
1622 | && fp_reg_operand (operand1, mode) | |
6b1c36c2 | 1623 | && ((GET_CODE (operand0) == MEM |
047e3121 | 1624 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1625 | ? SFmode : DFmode), | |
1626 | XEXP (operand0, 0))) | |
6b1c36c2 | 1627 | || ((GET_CODE (operand0) == SUBREG) |
1628 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
047e3121 | 1629 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1630 | ? SFmode : DFmode), | |
6bcdc1fb | 1631 | XEXP (XEXP (operand0, 0), 0))))) |
d6f01525 | 1632 | { |
6b1c36c2 | 1633 | if (GET_CODE (operand0) == SUBREG) |
1634 | operand0 = XEXP (operand0, 0); | |
1635 | ||
f756078b | 1636 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1637 | it in WORD_MODE regardless of what mode it was originally given | |
1638 | to us. */ | |
9840d99d | 1639 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1640 | |
7ee39d73 | 1641 | /* D might not fit in 14 bits either; for such cases load D into |
1642 | scratch reg. */ | |
440c23df | 1643 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) |
7ee39d73 | 1644 | { |
1645 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
ad851752 | 1646 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, |
1647 | 0)), | |
440c23df | 1648 | Pmode, |
ad851752 | 1649 | XEXP (XEXP (operand0, 0), |
1650 | 0), | |
1651 | scratch_reg)); | |
7ee39d73 | 1652 | } |
1653 | else | |
1654 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
ad851752 | 1655 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), |
1656 | operand1)); | |
d6f01525 | 1657 | return 1; |
1658 | } | |
753bd06a | 1659 | /* Handle secondary reloads for loads of FP registers from constant |
1660 | expressions by forcing the constant into memory. | |
1661 | ||
6bcdc1fb | 1662 | Use scratch_reg to hold the address of the memory location. |
753bd06a | 1663 | |
9dc4cbf1 | 1664 | The proper fix is to change PREFERRED_RELOAD_CLASS to return |
87fcb603 | 1665 | NO_REGS when presented with a const_int and a register class |
753bd06a | 1666 | containing only FP registers. Doing so unfortunately creates |
1667 | more problems than it solves. Fix this for 2.5. */ | |
6bcdc1fb | 1668 | else if (scratch_reg |
753bd06a | 1669 | && CONSTANT_P (operand1) |
6bcdc1fb | 1670 | && fp_reg_operand (operand0, mode)) |
753bd06a | 1671 | { |
1672 | rtx xoperands[2]; | |
1673 | ||
f756078b | 1674 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1675 | it in WORD_MODE regardless of what mode it was originally given | |
1676 | to us. */ | |
9840d99d | 1677 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1678 | |
753bd06a | 1679 | /* Force the constant into memory and put the address of the |
1680 | memory location into scratch_reg. */ | |
1681 | xoperands[0] = scratch_reg; | |
1682 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
8f258b49 | 1683 | emit_move_sequence (xoperands, Pmode, 0); |
753bd06a | 1684 | |
1685 | /* Now load the destination register. */ | |
7014838c | 1686 | emit_insn (gen_rtx_SET (mode, operand0, |
1687 | gen_rtx_MEM (mode, scratch_reg))); | |
753bd06a | 1688 | return 1; |
1689 | } | |
e8fdbafa | 1690 | /* Handle secondary reloads for SAR. These occur when trying to load |
2a170404 | 1691 | the SAR from memory, FP register, or with a constant. */ |
6bcdc1fb | 1692 | else if (scratch_reg |
1693 | && GET_CODE (operand0) == REG | |
2a170404 | 1694 | && REGNO (operand0) < FIRST_PSEUDO_REGISTER |
e8fdbafa | 1695 | && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS |
1696 | && (GET_CODE (operand1) == MEM | |
7d43e0f7 | 1697 | || GET_CODE (operand1) == CONST_INT |
e8fdbafa | 1698 | || (GET_CODE (operand1) == REG |
6bcdc1fb | 1699 | && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))) |
e8fdbafa | 1700 | { |
7eac600c | 1701 | /* D might not fit in 14 bits either; for such cases load D into |
1702 | scratch reg. */ | |
1703 | if (GET_CODE (operand1) == MEM | |
440c23df | 1704 | && !memory_address_p (Pmode, XEXP (operand1, 0))) |
7eac600c | 1705 | { |
fc4d127d | 1706 | /* We are reloading the address into the scratch register, so we |
1707 | want to make sure the scratch register is a full register. */ | |
9840d99d | 1708 | scratch_reg = force_mode (word_mode, scratch_reg); |
fc4d127d | 1709 | |
9840d99d | 1710 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); |
ad851752 | 1711 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, |
1712 | 0)), | |
440c23df | 1713 | Pmode, |
ad851752 | 1714 | XEXP (XEXP (operand1, 0), |
1715 | 0), | |
1716 | scratch_reg)); | |
fc4d127d | 1717 | |
1718 | /* Now we are going to load the scratch register from memory, | |
1719 | we want to load it in the same width as the original MEM, | |
1720 | which must be the same as the width of the ultimate destination, | |
1721 | OPERAND0. */ | |
9840d99d | 1722 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1723 | ||
fc4d127d | 1724 | emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0), |
ad851752 | 1725 | scratch_reg)); |
7eac600c | 1726 | } |
1727 | else | |
fc4d127d | 1728 | { |
1729 | /* We want to load the scratch register using the same mode as | |
1730 | the ultimate destination. */ | |
9840d99d | 1731 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1732 | ||
fc4d127d | 1733 | emit_move_insn (scratch_reg, operand1); |
1734 | } | |
1735 | ||
1736 | /* And emit the insn to set the ultimate destination. We know that | |
1737 | the scratch register has the same mode as the destination at this | |
1738 | point. */ | |
e8fdbafa | 1739 | emit_move_insn (operand0, scratch_reg); |
1740 | return 1; | |
1741 | } | |
dbd3d89d | 1742 | /* Handle the most common case: storing into a register. */ |
d6f01525 | 1743 | else if (register_operand (operand0, mode)) |
87ad11b0 | 1744 | { |
1745 | if (register_operand (operand1, mode) | |
93f6e1c7 | 1746 | || (GET_CODE (operand1) == CONST_INT |
1747 | && cint_ok_for_move (INTVAL (operand1))) | |
891b55b4 | 1748 | || (operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1749 | || (GET_CODE (operand1) == HIGH |
df0651dc | 1750 | && !symbolic_operand (XEXP (operand1, 0), VOIDmode)) |
87ad11b0 | 1751 | /* Only `general_operands' can come here, so MEM is ok. */ |
1752 | || GET_CODE (operand1) == MEM) | |
1753 | { | |
dbd3d89d | 1754 | /* Various sets are created during RTL generation which don't |
1755 | have the REG_POINTER flag correctly set. After the CSE pass, | |
1756 | instruction recognition can fail if we don't consistently | |
1757 | set this flag when performing register copies. This should | |
1758 | also improve the opportunities for creating insns that use | |
1759 | unscaled indexing. */ | |
1760 | if (REG_P (operand0) && REG_P (operand1)) | |
1761 | { | |
1762 | if (REG_POINTER (operand1) | |
1763 | && !REG_POINTER (operand0) | |
1764 | && !HARD_REGISTER_P (operand0)) | |
1765 | copy_reg_pointer (operand0, operand1); | |
1766 | else if (REG_POINTER (operand0) | |
1767 | && !REG_POINTER (operand1) | |
1768 | && !HARD_REGISTER_P (operand1)) | |
1769 | copy_reg_pointer (operand1, operand0); | |
1770 | } | |
1771 | ||
1772 | /* When MEMs are broken out, the REG_POINTER flag doesn't | |
1773 | get set. In some cases, we can set the REG_POINTER flag | |
1774 | from the declaration for the MEM. */ | |
1775 | if (REG_P (operand0) | |
1776 | && GET_CODE (operand1) == MEM | |
1777 | && !REG_POINTER (operand0)) | |
1778 | { | |
1779 | tree decl = MEM_EXPR (operand1); | |
1780 | ||
1781 | /* Set the register pointer flag and register alignment | |
1782 | if the declaration for this memory reference is a | |
1783 | pointer type. Fortran indirect argument references | |
1784 | are ignored. */ | |
1785 | if (decl | |
1786 | && !(flag_argument_noalias > 1 | |
1787 | && TREE_CODE (decl) == INDIRECT_REF | |
1788 | && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL)) | |
1789 | { | |
1790 | tree type; | |
1791 | ||
1792 | /* If this is a COMPONENT_REF, use the FIELD_DECL from | |
1793 | tree operand 1. */ | |
1794 | if (TREE_CODE (decl) == COMPONENT_REF) | |
1795 | decl = TREE_OPERAND (decl, 1); | |
1796 | ||
1797 | type = TREE_TYPE (decl); | |
1798 | if (TREE_CODE (type) == ARRAY_TYPE) | |
1799 | type = get_inner_array_type (type); | |
1800 | ||
1801 | if (POINTER_TYPE_P (type)) | |
1802 | { | |
1803 | int align; | |
1804 | ||
1805 | type = TREE_TYPE (type); | |
1806 | /* Using TYPE_ALIGN_OK is rather conservative as | |
1807 | only the ada frontend actually sets it. */ | |
1808 | align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type) | |
1809 | : BITS_PER_UNIT); | |
1810 | mark_reg_pointer (operand0, align); | |
1811 | } | |
1812 | } | |
1813 | } | |
1814 | ||
ad851752 | 1815 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1816 | return 1; |
1817 | } | |
1818 | } | |
1819 | else if (GET_CODE (operand0) == MEM) | |
1820 | { | |
85eb4c6e | 1821 | if (mode == DFmode && operand1 == CONST0_RTX (mode) |
1822 | && !(reload_in_progress || reload_completed)) | |
1823 | { | |
1824 | rtx temp = gen_reg_rtx (DFmode); | |
1825 | ||
ad851752 | 1826 | emit_insn (gen_rtx_SET (VOIDmode, temp, operand1)); |
1827 | emit_insn (gen_rtx_SET (VOIDmode, operand0, temp)); | |
85eb4c6e | 1828 | return 1; |
1829 | } | |
891b55b4 | 1830 | if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1831 | { |
1832 | /* Run this case quickly. */ | |
ad851752 | 1833 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1834 | return 1; |
1835 | } | |
2ff4bf8d | 1836 | if (! (reload_in_progress || reload_completed)) |
87ad11b0 | 1837 | { |
1838 | operands[0] = validize_mem (operand0); | |
1839 | operands[1] = operand1 = force_reg (mode, operand1); | |
1840 | } | |
1841 | } | |
1842 | ||
37a75d53 | 1843 | /* Simplify the source if we need to. |
1844 | Note we do have to handle function labels here, even though we do | |
1845 | not consider them legitimate constants. Loop optimizations can | |
bea60f66 | 1846 | call the emit_move_xxx with one as a source. */ |
57ed30e5 | 1847 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) |
37a75d53 | 1848 | || function_label_operand (operand1, mode) |
2ee034bc | 1849 | || (GET_CODE (operand1) == HIGH |
63882853 | 1850 | && symbolic_operand (XEXP (operand1, 0), mode))) |
87ad11b0 | 1851 | { |
2ee034bc | 1852 | int ishighonly = 0; |
1853 | ||
1854 | if (GET_CODE (operand1) == HIGH) | |
1855 | { | |
1856 | ishighonly = 1; | |
1857 | operand1 = XEXP (operand1, 0); | |
1858 | } | |
87ad11b0 | 1859 | if (symbolic_operand (operand1, mode)) |
1860 | { | |
005a7dd0 | 1861 | /* Argh. The assembler and linker can't handle arithmetic |
81653f9b | 1862 | involving plabels. |
005a7dd0 | 1863 | |
81653f9b | 1864 | So we force the plabel into memory, load operand0 from |
1865 | the memory location, then add in the constant part. */ | |
37a75d53 | 1866 | if ((GET_CODE (operand1) == CONST |
1867 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1868 | && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode)) | |
1869 | || function_label_operand (operand1, mode)) | |
005a7dd0 | 1870 | { |
b3d569a0 | 1871 | rtx temp, const_part; |
81653f9b | 1872 | |
1873 | /* Figure out what (if any) scratch register to use. */ | |
1874 | if (reload_in_progress || reload_completed) | |
f756078b | 1875 | { |
1876 | scratch_reg = scratch_reg ? scratch_reg : operand0; | |
1877 | /* SCRATCH_REG will hold an address and maybe the actual | |
1878 | data. We want it in WORD_MODE regardless of what mode it | |
1879 | was originally given to us. */ | |
9840d99d | 1880 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1881 | } |
81653f9b | 1882 | else if (flag_pic) |
1883 | scratch_reg = gen_reg_rtx (Pmode); | |
1884 | ||
37a75d53 | 1885 | if (GET_CODE (operand1) == CONST) |
1886 | { | |
1887 | /* Save away the constant part of the expression. */ | |
1888 | const_part = XEXP (XEXP (operand1, 0), 1); | |
1889 | if (GET_CODE (const_part) != CONST_INT) | |
1890 | abort (); | |
1891 | ||
1892 | /* Force the function label into memory. */ | |
1893 | temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0)); | |
1894 | } | |
1895 | else | |
1896 | { | |
1897 | /* No constant part. */ | |
1898 | const_part = NULL_RTX; | |
005a7dd0 | 1899 | |
37a75d53 | 1900 | /* Force the function label into memory. */ |
1901 | temp = force_const_mem (mode, operand1); | |
1902 | } | |
9840d99d | 1903 | |
81653f9b | 1904 | |
1905 | /* Get the address of the memory location. PIC-ify it if | |
1906 | necessary. */ | |
1907 | temp = XEXP (temp, 0); | |
1908 | if (flag_pic) | |
1909 | temp = legitimize_pic_address (temp, mode, scratch_reg); | |
1910 | ||
1911 | /* Put the address of the memory location into our destination | |
1912 | register. */ | |
1913 | operands[1] = temp; | |
1914 | emit_move_sequence (operands, mode, scratch_reg); | |
1915 | ||
1916 | /* Now load from the memory location into our destination | |
1917 | register. */ | |
ad851752 | 1918 | operands[1] = gen_rtx_MEM (Pmode, operands[0]); |
81653f9b | 1919 | emit_move_sequence (operands, mode, scratch_reg); |
1920 | ||
1921 | /* And add back in the constant part. */ | |
37a75d53 | 1922 | if (const_part != NULL_RTX) |
1923 | expand_inc (operand0, const_part); | |
81653f9b | 1924 | |
1925 | return 1; | |
005a7dd0 | 1926 | } |
1927 | ||
87ad11b0 | 1928 | if (flag_pic) |
1929 | { | |
2ff4bf8d | 1930 | rtx temp; |
1931 | ||
1932 | if (reload_in_progress || reload_completed) | |
f756078b | 1933 | { |
1934 | temp = scratch_reg ? scratch_reg : operand0; | |
1935 | /* TEMP will hold an address and maybe the actual | |
1936 | data. We want it in WORD_MODE regardless of what mode it | |
1937 | was originally given to us. */ | |
9840d99d | 1938 | temp = force_mode (word_mode, temp); |
f756078b | 1939 | } |
2ff4bf8d | 1940 | else |
1941 | temp = gen_reg_rtx (Pmode); | |
6d36483b | 1942 | |
81653f9b | 1943 | /* (const (plus (symbol) (const_int))) must be forced to |
1944 | memory during/after reload if the const_int will not fit | |
1945 | in 14 bits. */ | |
1946 | if (GET_CODE (operand1) == CONST | |
96b86ab6 | 1947 | && GET_CODE (XEXP (operand1, 0)) == PLUS |
1948 | && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT | |
1949 | && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)) | |
1950 | && (reload_completed || reload_in_progress) | |
1951 | && flag_pic) | |
1952 | { | |
1953 | operands[1] = force_const_mem (mode, operand1); | |
1954 | operands[1] = legitimize_pic_address (XEXP (operands[1], 0), | |
1955 | mode, temp); | |
f3c9071d | 1956 | operands[1] = gen_rtx_MEM (mode, operands[1]); |
96b86ab6 | 1957 | emit_move_sequence (operands, mode, temp); |
1958 | } | |
005a7dd0 | 1959 | else |
1960 | { | |
1961 | operands[1] = legitimize_pic_address (operand1, mode, temp); | |
dbd3d89d | 1962 | if (REG_P (operand0) && REG_P (operands[1])) |
1963 | copy_reg_pointer (operand0, operands[1]); | |
ad851752 | 1964 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1])); |
005a7dd0 | 1965 | } |
87ad11b0 | 1966 | } |
b4a7bf10 | 1967 | /* On the HPPA, references to data space are supposed to use dp, |
1968 | register 27, but showing it in the RTL inhibits various cse | |
1969 | and loop optimizations. */ | |
6d36483b | 1970 | else |
87ad11b0 | 1971 | { |
005a7dd0 | 1972 | rtx temp, set; |
2ee034bc | 1973 | |
6d36483b | 1974 | if (reload_in_progress || reload_completed) |
f756078b | 1975 | { |
1976 | temp = scratch_reg ? scratch_reg : operand0; | |
1977 | /* TEMP will hold an address and maybe the actual | |
1978 | data. We want it in WORD_MODE regardless of what mode it | |
1979 | was originally given to us. */ | |
9840d99d | 1980 | temp = force_mode (word_mode, temp); |
f756078b | 1981 | } |
2ee034bc | 1982 | else |
1983 | temp = gen_reg_rtx (mode); | |
1984 | ||
42819d4e | 1985 | /* Loading a SYMBOL_REF into a register makes that register |
9840d99d | 1986 | safe to be used as the base in an indexed address. |
42819d4e | 1987 | |
1988 | Don't mark hard registers though. That loses. */ | |
47a61b79 | 1989 | if (GET_CODE (operand0) == REG |
1990 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
dbd3d89d | 1991 | mark_reg_pointer (operand0, BITS_PER_UNIT); |
42819d4e | 1992 | if (REGNO (temp) >= FIRST_PSEUDO_REGISTER) |
dbd3d89d | 1993 | mark_reg_pointer (temp, BITS_PER_UNIT); |
1994 | ||
2ee034bc | 1995 | if (ishighonly) |
ad851752 | 1996 | set = gen_rtx_SET (mode, operand0, temp); |
2ee034bc | 1997 | else |
7014838c | 1998 | set = gen_rtx_SET (VOIDmode, |
1999 | operand0, | |
ad851752 | 2000 | gen_rtx_LO_SUM (mode, temp, operand1)); |
6d36483b | 2001 | |
ad851752 | 2002 | emit_insn (gen_rtx_SET (VOIDmode, |
2003 | temp, | |
2004 | gen_rtx_HIGH (mode, operand1))); | |
d2498717 | 2005 | emit_insn (set); |
166bf021 | 2006 | |
87ad11b0 | 2007 | } |
2ee034bc | 2008 | return 1; |
87ad11b0 | 2009 | } |
42faba01 | 2010 | else if (GET_CODE (operand1) != CONST_INT |
6bcdc1fb | 2011 | || !cint_ok_for_move (INTVAL (operand1))) |
87ad11b0 | 2012 | { |
6bcdc1fb | 2013 | rtx insn, temp; |
2014 | rtx op1 = operand1; | |
6edde44b | 2015 | HOST_WIDE_INT value = 0; |
6bcdc1fb | 2016 | HOST_WIDE_INT insv = 0; |
2017 | int insert = 0; | |
2018 | ||
6edde44b | 2019 | if (GET_CODE (operand1) == CONST_INT) |
2020 | value = INTVAL (operand1); | |
2021 | ||
6bcdc1fb | 2022 | if (TARGET_64BIT |
2023 | && GET_CODE (operand1) == CONST_INT | |
b7d86581 | 2024 | && HOST_BITS_PER_WIDE_INT > 32 |
5e3c5739 | 2025 | && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32) |
2026 | { | |
b7d86581 | 2027 | HOST_WIDE_INT nval; |
5e3c5739 | 2028 | |
93f6e1c7 | 2029 | /* Extract the low order 32 bits of the value and sign extend. |
2030 | If the new value is the same as the original value, we can | |
2031 | can use the original value as-is. If the new value is | |
2032 | different, we use it and insert the most-significant 32-bits | |
2033 | of the original value into the final result. */ | |
6bcdc1fb | 2034 | nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1)) |
b7d86581 | 2035 | ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31); |
6bcdc1fb | 2036 | if (value != nval) |
5e3c5739 | 2037 | { |
93f6e1c7 | 2038 | #if HOST_BITS_PER_WIDE_INT > 32 |
6bcdc1fb | 2039 | insv = value >= 0 ? value >> 32 : ~(~value >> 32); |
93f6e1c7 | 2040 | #endif |
6bcdc1fb | 2041 | insert = 1; |
2042 | value = nval; | |
5e3c5739 | 2043 | operand1 = GEN_INT (nval); |
2044 | } | |
2045 | } | |
2ff4bf8d | 2046 | |
2047 | if (reload_in_progress || reload_completed) | |
6bcdc1fb | 2048 | temp = scratch_reg ? scratch_reg : operand0; |
2ff4bf8d | 2049 | else |
2050 | temp = gen_reg_rtx (mode); | |
2051 | ||
7c4d3047 | 2052 | /* We don't directly split DImode constants on 32-bit targets |
2053 | because PLUS uses an 11-bit immediate and the insn sequence | |
2054 | generated is not as efficient as the one using HIGH/LO_SUM. */ | |
2055 | if (GET_CODE (operand1) == CONST_INT | |
6bcdc1fb | 2056 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
2057 | && !insert) | |
93f6e1c7 | 2058 | { |
7c4d3047 | 2059 | /* Directly break constant into high and low parts. This |
93f6e1c7 | 2060 | provides better optimization opportunities because various |
2061 | passes recognize constants split with PLUS but not LO_SUM. | |
2062 | We use a 14-bit signed low part except when the addition | |
2063 | of 0x4000 to the high part might change the sign of the | |
2064 | high part. */ | |
93f6e1c7 | 2065 | HOST_WIDE_INT low = value & 0x3fff; |
2066 | HOST_WIDE_INT high = value & ~ 0x3fff; | |
2067 | ||
2068 | if (low >= 0x2000) | |
2069 | { | |
2070 | if (high == 0x7fffc000 || (mode == HImode && high == 0x4000)) | |
2071 | high += 0x2000; | |
2072 | else | |
2073 | high += 0x4000; | |
2074 | } | |
2075 | ||
2076 | low = value - high; | |
5e3c5739 | 2077 | |
93f6e1c7 | 2078 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high))); |
2079 | operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low)); | |
2080 | } | |
2081 | else | |
5e3c5739 | 2082 | { |
93f6e1c7 | 2083 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
2084 | gen_rtx_HIGH (mode, operand1))); | |
2085 | operands[1] = gen_rtx_LO_SUM (mode, temp, operand1); | |
5e3c5739 | 2086 | } |
9840d99d | 2087 | |
6bcdc1fb | 2088 | insn = emit_move_insn (operands[0], operands[1]); |
2089 | ||
2090 | /* Now insert the most significant 32 bits of the value | |
2091 | into the register. When we don't have a second register | |
2092 | available, it could take up to nine instructions to load | |
2093 | a 64-bit integer constant. Prior to reload, we force | |
2094 | constants that would take more than three instructions | |
2095 | to load to the constant pool. During and after reload, | |
2096 | we have to handle all possible values. */ | |
2097 | if (insert) | |
2098 | { | |
2099 | /* Use a HIGH/LO_SUM/INSV sequence if we have a second | |
2100 | register and the value to be inserted is outside the | |
2101 | range that can be loaded with three depdi instructions. */ | |
2102 | if (temp != operand0 && (insv >= 16384 || insv < -16384)) | |
2103 | { | |
2104 | operand1 = GEN_INT (insv); | |
2105 | ||
2106 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
2107 | gen_rtx_HIGH (mode, operand1))); | |
2108 | emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1)); | |
2109 | emit_insn (gen_insv (operand0, GEN_INT (32), | |
2110 | const0_rtx, temp)); | |
2111 | } | |
2112 | else | |
2113 | { | |
2114 | int len = 5, pos = 27; | |
2115 | ||
2116 | /* Insert the bits using the depdi instruction. */ | |
2117 | while (pos >= 0) | |
2118 | { | |
2119 | HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16; | |
2120 | HOST_WIDE_INT sign = v5 < 0; | |
2121 | ||
2122 | /* Left extend the insertion. */ | |
2123 | insv = (insv >= 0 ? insv >> len : ~(~insv >> len)); | |
2124 | while (pos > 0 && (insv & 1) == sign) | |
2125 | { | |
2126 | insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1)); | |
2127 | len += 1; | |
2128 | pos -= 1; | |
2129 | } | |
2130 | ||
2131 | emit_insn (gen_insv (operand0, GEN_INT (len), | |
2132 | GEN_INT (pos), GEN_INT (v5))); | |
2133 | ||
2134 | len = pos > 0 && pos < 5 ? pos : 5; | |
2135 | pos -= len; | |
2136 | } | |
2137 | } | |
2138 | } | |
93f6e1c7 | 2139 | |
6bcdc1fb | 2140 | REG_NOTES (insn) |
2141 | = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn)); | |
93f6e1c7 | 2142 | |
5e3c5739 | 2143 | return 1; |
87ad11b0 | 2144 | } |
2145 | } | |
2146 | /* Now have insn-emit do whatever it normally does. */ | |
2147 | return 0; | |
2148 | } | |
2149 | ||
1946138e | 2150 | /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning |
bd49d362 | 2151 | it will need a link/runtime reloc). */ |
1946138e | 2152 | |
2153 | int | |
5c1d8983 | 2154 | reloc_needed (tree exp) |
1946138e | 2155 | { |
2156 | int reloc = 0; | |
2157 | ||
2158 | switch (TREE_CODE (exp)) | |
2159 | { | |
2160 | case ADDR_EXPR: | |
2161 | return 1; | |
2162 | ||
2163 | case PLUS_EXPR: | |
2164 | case MINUS_EXPR: | |
2165 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
2166 | reloc |= reloc_needed (TREE_OPERAND (exp, 1)); | |
2167 | break; | |
2168 | ||
2169 | case NOP_EXPR: | |
2170 | case CONVERT_EXPR: | |
2171 | case NON_LVALUE_EXPR: | |
2172 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
2173 | break; | |
2174 | ||
2175 | case CONSTRUCTOR: | |
2176 | { | |
2177 | register tree link; | |
2178 | for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link)) | |
2179 | if (TREE_VALUE (link) != 0) | |
2180 | reloc |= reloc_needed (TREE_VALUE (link)); | |
2181 | } | |
2182 | break; | |
2183 | ||
2184 | case ERROR_MARK: | |
2185 | break; | |
7d27e4c9 | 2186 | |
2187 | default: | |
2188 | break; | |
1946138e | 2189 | } |
2190 | return reloc; | |
2191 | } | |
2192 | ||
7811991d | 2193 | /* Does operand (which is a symbolic_operand) live in text space? |
2194 | If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info, | |
2195 | will be true. */ | |
87ad11b0 | 2196 | |
2197 | int | |
5c1d8983 | 2198 | read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 2199 | { |
2200 | if (GET_CODE (operand) == CONST) | |
2201 | operand = XEXP (XEXP (operand, 0), 0); | |
b4a7bf10 | 2202 | if (flag_pic) |
2203 | { | |
2204 | if (GET_CODE (operand) == SYMBOL_REF) | |
2205 | return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand); | |
2206 | } | |
2207 | else | |
2208 | { | |
2209 | if (GET_CODE (operand) == SYMBOL_REF) | |
2210 | return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand); | |
2211 | } | |
87ad11b0 | 2212 | return 1; |
2213 | } | |
6d36483b | 2214 | |
87ad11b0 | 2215 | \f |
2216 | /* Return the best assembler insn template | |
5aedf60c | 2217 | for moving operands[1] into operands[0] as a fullword. */ |
611a88e1 | 2218 | const char * |
5c1d8983 | 2219 | singlemove_string (rtx *operands) |
87ad11b0 | 2220 | { |
3745c59b | 2221 | HOST_WIDE_INT intval; |
2222 | ||
87ad11b0 | 2223 | if (GET_CODE (operands[0]) == MEM) |
2224 | return "stw %r1,%0"; | |
3745c59b | 2225 | if (GET_CODE (operands[1]) == MEM) |
87ad11b0 | 2226 | return "ldw %1,%0"; |
3745c59b | 2227 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
9d5108ea | 2228 | { |
3745c59b | 2229 | long i; |
2230 | REAL_VALUE_TYPE d; | |
9d5108ea | 2231 | |
3745c59b | 2232 | if (GET_MODE (operands[1]) != SFmode) |
2233 | abort (); | |
9d5108ea | 2234 | |
3745c59b | 2235 | /* Translate the CONST_DOUBLE to a CONST_INT with the same target |
2236 | bit pattern. */ | |
2237 | REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]); | |
2238 | REAL_VALUE_TO_TARGET_SINGLE (d, i); | |
9d5108ea | 2239 | |
3745c59b | 2240 | operands[1] = GEN_INT (i); |
2241 | /* Fall through to CONST_INT case. */ | |
2242 | } | |
2243 | if (GET_CODE (operands[1]) == CONST_INT) | |
9d5108ea | 2244 | { |
3745c59b | 2245 | intval = INTVAL (operands[1]); |
2246 | ||
2247 | if (VAL_14_BITS_P (intval)) | |
2248 | return "ldi %1,%0"; | |
2249 | else if ((intval & 0x7ff) == 0) | |
2250 | return "ldil L'%1,%0"; | |
2251 | else if (zdepi_cint_p (intval)) | |
e4065f95 | 2252 | return "{zdepi %Z1,%0|depwi,z %Z1,%0}"; |
9d5108ea | 2253 | else |
2254 | return "ldil L'%1,%0\n\tldo R'%1(%0),%0"; | |
2255 | } | |
87ad11b0 | 2256 | return "copy %1,%0"; |
2257 | } | |
2258 | \f | |
2259 | ||
201f01e9 | 2260 | /* Compute position (in OP[1]) and width (in OP[2]) |
2261 | useful for copying IMM to a register using the zdepi | |
2262 | instructions. Store the immediate value to insert in OP[0]. */ | |
611a88e1 | 2263 | static void |
5c1d8983 | 2264 | compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
7e10ba53 | 2265 | { |
e057641f | 2266 | int lsb, len; |
7e10ba53 | 2267 | |
e057641f | 2268 | /* Find the least significant set bit in IMM. */ |
2269 | for (lsb = 0; lsb < 32; lsb++) | |
7e10ba53 | 2270 | { |
e057641f | 2271 | if ((imm & 1) != 0) |
7e10ba53 | 2272 | break; |
e057641f | 2273 | imm >>= 1; |
7e10ba53 | 2274 | } |
2275 | ||
e057641f | 2276 | /* Choose variants based on *sign* of the 5-bit field. */ |
2277 | if ((imm & 0x10) == 0) | |
2278 | len = (lsb <= 28) ? 4 : 32 - lsb; | |
7e10ba53 | 2279 | else |
2280 | { | |
e057641f | 2281 | /* Find the width of the bitstring in IMM. */ |
2282 | for (len = 5; len < 32; len++) | |
7e10ba53 | 2283 | { |
e057641f | 2284 | if ((imm & (1 << len)) == 0) |
7e10ba53 | 2285 | break; |
7e10ba53 | 2286 | } |
2287 | ||
e057641f | 2288 | /* Sign extend IMM as a 5-bit value. */ |
2289 | imm = (imm & 0xf) - 0x10; | |
7e10ba53 | 2290 | } |
2291 | ||
42faba01 | 2292 | op[0] = imm; |
2293 | op[1] = 31 - lsb; | |
2294 | op[2] = len; | |
7e10ba53 | 2295 | } |
2296 | ||
5e3c5739 | 2297 | /* Compute position (in OP[1]) and width (in OP[2]) |
2298 | useful for copying IMM to a register using the depdi,z | |
2299 | instructions. Store the immediate value to insert in OP[0]. */ | |
2300 | void | |
5c1d8983 | 2301 | compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
5e3c5739 | 2302 | { |
2303 | HOST_WIDE_INT lsb, len; | |
2304 | ||
2305 | /* Find the least significant set bit in IMM. */ | |
2306 | for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++) | |
2307 | { | |
2308 | if ((imm & 1) != 0) | |
2309 | break; | |
2310 | imm >>= 1; | |
2311 | } | |
2312 | ||
2313 | /* Choose variants based on *sign* of the 5-bit field. */ | |
2314 | if ((imm & 0x10) == 0) | |
2315 | len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4) | |
2316 | ? 4 : HOST_BITS_PER_WIDE_INT - lsb); | |
2317 | else | |
2318 | { | |
2319 | /* Find the width of the bitstring in IMM. */ | |
2320 | for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++) | |
2321 | { | |
ea52c577 | 2322 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
5e3c5739 | 2323 | break; |
2324 | } | |
2325 | ||
2326 | /* Sign extend IMM as a 5-bit value. */ | |
2327 | imm = (imm & 0xf) - 0x10; | |
2328 | } | |
2329 | ||
2330 | op[0] = imm; | |
2331 | op[1] = 63 - lsb; | |
2332 | op[2] = len; | |
2333 | } | |
2334 | ||
87ad11b0 | 2335 | /* Output assembler code to perform a doubleword move insn |
2336 | with operands OPERANDS. */ | |
2337 | ||
611a88e1 | 2338 | const char * |
5c1d8983 | 2339 | output_move_double (rtx *operands) |
87ad11b0 | 2340 | { |
2341 | enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1; | |
2342 | rtx latehalf[2]; | |
2343 | rtx addreg0 = 0, addreg1 = 0; | |
2344 | ||
2345 | /* First classify both operands. */ | |
2346 | ||
2347 | if (REG_P (operands[0])) | |
2348 | optype0 = REGOP; | |
2349 | else if (offsettable_memref_p (operands[0])) | |
2350 | optype0 = OFFSOP; | |
2351 | else if (GET_CODE (operands[0]) == MEM) | |
2352 | optype0 = MEMOP; | |
2353 | else | |
2354 | optype0 = RNDOP; | |
2355 | ||
2356 | if (REG_P (operands[1])) | |
2357 | optype1 = REGOP; | |
2358 | else if (CONSTANT_P (operands[1])) | |
2359 | optype1 = CNSTOP; | |
2360 | else if (offsettable_memref_p (operands[1])) | |
2361 | optype1 = OFFSOP; | |
2362 | else if (GET_CODE (operands[1]) == MEM) | |
2363 | optype1 = MEMOP; | |
2364 | else | |
2365 | optype1 = RNDOP; | |
2366 | ||
2367 | /* Check for the cases that the operand constraints are not | |
2368 | supposed to allow to happen. Abort if we get one, | |
2369 | because generating code for these cases is painful. */ | |
2370 | ||
2371 | if (optype0 != REGOP && optype1 != REGOP) | |
2372 | abort (); | |
2373 | ||
2374 | /* Handle auto decrementing and incrementing loads and stores | |
2375 | specifically, since the structure of the function doesn't work | |
2376 | for them without major modification. Do it better when we learn | |
2377 | this port about the general inc/dec addressing of PA. | |
2378 | (This was written by tege. Chide him if it doesn't work.) */ | |
2379 | ||
2380 | if (optype0 == MEMOP) | |
2381 | { | |
1df0058a | 2382 | /* We have to output the address syntax ourselves, since print_operand |
2383 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2384 | ||
87ad11b0 | 2385 | rtx addr = XEXP (operands[0], 0); |
1df0058a | 2386 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) |
87ad11b0 | 2387 | { |
ad851752 | 2388 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2389 | |
2390 | operands[0] = XEXP (addr, 0); | |
2391 | if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG) | |
2392 | abort (); | |
2393 | ||
2394 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2395 | { | |
2396 | /* No overlap between high target register and address | |
2397 | register. (We do this in a non-obvious way to | |
2398 | save a register file writeback) */ | |
2399 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2400 | return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)"; |
2401 | return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)"; | |
1df0058a | 2402 | } |
2403 | else | |
ea52c577 | 2404 | abort (); |
a3217f65 | 2405 | } |
1df0058a | 2406 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) |
a3217f65 | 2407 | { |
ad851752 | 2408 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2409 | |
2410 | operands[0] = XEXP (addr, 0); | |
2411 | if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG) | |
2412 | abort (); | |
2413 | ||
2414 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2415 | { | |
2416 | /* No overlap between high target register and address | |
2417 | register. (We do this in a non-obvious way to | |
2418 | save a register file writeback) */ | |
2419 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2420 | return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)"; |
2421 | return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)"; | |
1df0058a | 2422 | } |
2423 | else | |
ea52c577 | 2424 | abort (); |
87ad11b0 | 2425 | } |
2426 | } | |
2427 | if (optype1 == MEMOP) | |
2428 | { | |
2429 | /* We have to output the address syntax ourselves, since print_operand | |
2430 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2431 | ||
2432 | rtx addr = XEXP (operands[1], 0); | |
2433 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) | |
2434 | { | |
ad851752 | 2435 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2436 | |
2437 | operands[1] = XEXP (addr, 0); | |
2438 | if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG) | |
2439 | abort (); | |
2440 | ||
2441 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2442 | { | |
2443 | /* No overlap between high target register and address | |
3857fa62 | 2444 | register. (We do this in a non-obvious way to |
87ad11b0 | 2445 | save a register file writeback) */ |
2446 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2447 | return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0"; |
01fd4b49 | 2448 | return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0"; |
87ad11b0 | 2449 | } |
2450 | else | |
2451 | { | |
2452 | /* This is an undefined situation. We should load into the | |
2453 | address register *and* update that register. Probably | |
2454 | we don't need to handle this at all. */ | |
2455 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2456 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0"; |
2457 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0"; | |
87ad11b0 | 2458 | } |
2459 | } | |
2460 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) | |
2461 | { | |
ad851752 | 2462 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2463 | |
2464 | operands[1] = XEXP (addr, 0); | |
2465 | if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG) | |
2466 | abort (); | |
2467 | ||
2468 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2469 | { | |
2470 | /* No overlap between high target register and address | |
3857fa62 | 2471 | register. (We do this in a non-obvious way to |
87ad11b0 | 2472 | save a register file writeback) */ |
2473 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2474 | return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0"; |
2475 | return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0"; | |
87ad11b0 | 2476 | } |
2477 | else | |
2478 | { | |
2479 | /* This is an undefined situation. We should load into the | |
2480 | address register *and* update that register. Probably | |
2481 | we don't need to handle this at all. */ | |
2482 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2483 | return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0"; |
2484 | return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0"; | |
87ad11b0 | 2485 | } |
2486 | } | |
12b02046 | 2487 | else if (GET_CODE (addr) == PLUS |
2488 | && GET_CODE (XEXP (addr, 0)) == MULT) | |
2489 | { | |
ad851752 | 2490 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
12b02046 | 2491 | |
2492 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2493 | { | |
2494 | rtx xoperands[3]; | |
2495 | ||
2496 | xoperands[0] = high_reg; | |
2497 | xoperands[1] = XEXP (addr, 1); | |
2498 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2499 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2500 | output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}", |
2501 | xoperands); | |
34940871 | 2502 | return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; |
12b02046 | 2503 | } |
2504 | else | |
2505 | { | |
2506 | rtx xoperands[3]; | |
2507 | ||
2508 | xoperands[0] = high_reg; | |
2509 | xoperands[1] = XEXP (addr, 1); | |
2510 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2511 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2512 | output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}", |
2513 | xoperands); | |
34940871 | 2514 | return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0"; |
12b02046 | 2515 | } |
12b02046 | 2516 | } |
87ad11b0 | 2517 | } |
2518 | ||
2519 | /* If an operand is an unoffsettable memory ref, find a register | |
2520 | we can increment temporarily to make it refer to the second word. */ | |
2521 | ||
2522 | if (optype0 == MEMOP) | |
2523 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2524 | ||
2525 | if (optype1 == MEMOP) | |
2526 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2527 | ||
2528 | /* Ok, we can do one word at a time. | |
2529 | Normally we do the low-numbered word first. | |
2530 | ||
2531 | In either case, set up in LATEHALF the operands to use | |
2532 | for the high-numbered word and in some cases alter the | |
2533 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2534 | ||
2535 | if (optype0 == REGOP) | |
ad851752 | 2536 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
87ad11b0 | 2537 | else if (optype0 == OFFSOP) |
eafc6604 | 2538 | latehalf[0] = adjust_address (operands[0], SImode, 4); |
87ad11b0 | 2539 | else |
2540 | latehalf[0] = operands[0]; | |
2541 | ||
2542 | if (optype1 == REGOP) | |
ad851752 | 2543 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
87ad11b0 | 2544 | else if (optype1 == OFFSOP) |
eafc6604 | 2545 | latehalf[1] = adjust_address (operands[1], SImode, 4); |
87ad11b0 | 2546 | else if (optype1 == CNSTOP) |
2547 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2548 | else | |
2549 | latehalf[1] = operands[1]; | |
2550 | ||
2551 | /* If the first move would clobber the source of the second one, | |
2552 | do them in the other order. | |
2553 | ||
cf489d53 | 2554 | This can happen in two cases: |
87ad11b0 | 2555 | |
cf489d53 | 2556 | mem -> register where the first half of the destination register |
2557 | is the same register used in the memory's address. Reload | |
2558 | can create such insns. | |
87ad11b0 | 2559 | |
cf489d53 | 2560 | mem in this case will be either register indirect or register |
9840d99d | 2561 | indirect plus a valid offset. |
cf489d53 | 2562 | |
2563 | register -> register move where REGNO(dst) == REGNO(src + 1) | |
9840d99d | 2564 | someone (Tim/Tege?) claimed this can happen for parameter loads. |
cf489d53 | 2565 | |
2566 | Handle mem -> register case first. */ | |
2567 | if (optype0 == REGOP | |
2568 | && (optype1 == MEMOP || optype1 == OFFSOP) | |
2569 | && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2570 | operands[1], 0)) | |
87ad11b0 | 2571 | { |
87ad11b0 | 2572 | /* Do the late half first. */ |
2573 | if (addreg1) | |
6a5d085a | 2574 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2575 | output_asm_insn (singlemove_string (latehalf), latehalf); |
cf489d53 | 2576 | |
2577 | /* Then clobber. */ | |
87ad11b0 | 2578 | if (addreg1) |
6a5d085a | 2579 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2580 | return singlemove_string (operands); |
2581 | } | |
2582 | ||
cf489d53 | 2583 | /* Now handle register -> register case. */ |
c4fa5937 | 2584 | if (optype0 == REGOP && optype1 == REGOP |
2585 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
2586 | { | |
2587 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2588 | return singlemove_string (operands); | |
2589 | } | |
2590 | ||
87ad11b0 | 2591 | /* Normal case: do the two words, low-numbered first. */ |
2592 | ||
2593 | output_asm_insn (singlemove_string (operands), operands); | |
2594 | ||
2595 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2596 | if (addreg0) | |
6a5d085a | 2597 | output_asm_insn ("ldo 4(%0),%0", &addreg0); |
87ad11b0 | 2598 | if (addreg1) |
6a5d085a | 2599 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2600 | |
2601 | /* Do that word. */ | |
2602 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2603 | ||
2604 | /* Undo the adds we just did. */ | |
2605 | if (addreg0) | |
6a5d085a | 2606 | output_asm_insn ("ldo -4(%0),%0", &addreg0); |
87ad11b0 | 2607 | if (addreg1) |
6a5d085a | 2608 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2609 | |
2610 | return ""; | |
2611 | } | |
2612 | \f | |
611a88e1 | 2613 | const char * |
5c1d8983 | 2614 | output_fp_move_double (rtx *operands) |
87ad11b0 | 2615 | { |
2616 | if (FP_REG_P (operands[0])) | |
2617 | { | |
6d36483b | 2618 | if (FP_REG_P (operands[1]) |
891b55b4 | 2619 | || operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
c6ae275c | 2620 | output_asm_insn ("fcpy,dbl %f1,%0", operands); |
6d36483b | 2621 | else |
27ef382d | 2622 | output_asm_insn ("fldd%F1 %1,%0", operands); |
87ad11b0 | 2623 | } |
2624 | else if (FP_REG_P (operands[1])) | |
2625 | { | |
27ef382d | 2626 | output_asm_insn ("fstd%F0 %1,%0", operands); |
87ad11b0 | 2627 | } |
891b55b4 | 2628 | else if (operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
2629 | { | |
2630 | if (GET_CODE (operands[0]) == REG) | |
2631 | { | |
2632 | rtx xoperands[2]; | |
ad851752 | 2633 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
891b55b4 | 2634 | xoperands[0] = operands[0]; |
2635 | output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands); | |
2636 | } | |
6d36483b | 2637 | /* This is a pain. You have to be prepared to deal with an |
01cc3b75 | 2638 | arbitrary address here including pre/post increment/decrement. |
891b55b4 | 2639 | |
2640 | so avoid this in the MD. */ | |
2641 | else | |
2642 | abort (); | |
2643 | } | |
87ad11b0 | 2644 | else abort (); |
2645 | return ""; | |
2646 | } | |
2647 | \f | |
2648 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2649 | ADDR can be effectively incremented by incrementing REG. */ | |
2650 | ||
2651 | static rtx | |
5c1d8983 | 2652 | find_addr_reg (rtx addr) |
87ad11b0 | 2653 | { |
2654 | while (GET_CODE (addr) == PLUS) | |
2655 | { | |
2656 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2657 | addr = XEXP (addr, 0); | |
2658 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2659 | addr = XEXP (addr, 1); | |
2660 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2661 | addr = XEXP (addr, 1); | |
2662 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2663 | addr = XEXP (addr, 0); | |
2664 | else | |
2665 | abort (); | |
2666 | } | |
2667 | if (GET_CODE (addr) == REG) | |
2668 | return addr; | |
2669 | abort (); | |
2670 | } | |
2671 | ||
87ad11b0 | 2672 | /* Emit code to perform a block move. |
2673 | ||
87ad11b0 | 2674 | OPERANDS[0] is the destination pointer as a REG, clobbered. |
2675 | OPERANDS[1] is the source pointer as a REG, clobbered. | |
42819d4e | 2676 | OPERANDS[2] is a register for temporary storage. |
87ad11b0 | 2677 | OPERANDS[3] is a register for temporary storage. |
a7e1bb24 | 2678 | OPERANDS[4] is the size as a CONST_INT |
9840d99d | 2679 | OPERANDS[5] is the alignment safe to use, as a CONST_INT. |
5aedf60c | 2680 | OPERANDS[6] is another temporary register. */ |
87ad11b0 | 2681 | |
611a88e1 | 2682 | const char * |
5c1d8983 | 2683 | output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) |
87ad11b0 | 2684 | { |
2685 | int align = INTVAL (operands[5]); | |
42819d4e | 2686 | unsigned long n_bytes = INTVAL (operands[4]); |
87ad11b0 | 2687 | |
a7e1bb24 | 2688 | /* We can't move more than a word at a time because the PA |
87ad11b0 | 2689 | has no longer integer move insns. (Could use fp mem ops?) */ |
a7e1bb24 | 2690 | if (align > (TARGET_64BIT ? 8 : 4)) |
2691 | align = (TARGET_64BIT ? 8 : 4); | |
87ad11b0 | 2692 | |
42819d4e | 2693 | /* Note that we know each loop below will execute at least twice |
2694 | (else we would have open-coded the copy). */ | |
2695 | switch (align) | |
87ad11b0 | 2696 | { |
a7e1bb24 | 2697 | case 8: |
2698 | /* Pre-adjust the loop counter. */ | |
2699 | operands[4] = GEN_INT (n_bytes - 16); | |
2700 | output_asm_insn ("ldi %4,%2", operands); | |
2701 | ||
2702 | /* Copying loop. */ | |
2703 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2704 | output_asm_insn ("ldd,ma 8(%1),%6", operands); | |
2705 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2706 | output_asm_insn ("addib,>= -16,%2,.-12", operands); | |
2707 | output_asm_insn ("std,ma %6,8(%0)", operands); | |
2708 | ||
2709 | /* Handle the residual. There could be up to 7 bytes of | |
2710 | residual to copy! */ | |
2711 | if (n_bytes % 16 != 0) | |
2712 | { | |
2713 | operands[4] = GEN_INT (n_bytes % 8); | |
2714 | if (n_bytes % 16 >= 8) | |
2715 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2716 | if (n_bytes % 8 != 0) | |
2717 | output_asm_insn ("ldd 0(%1),%6", operands); | |
2718 | if (n_bytes % 16 >= 8) | |
2719 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2720 | if (n_bytes % 8 != 0) | |
2721 | output_asm_insn ("stdby,e %6,%4(%0)", operands); | |
2722 | } | |
2723 | return ""; | |
2724 | ||
42819d4e | 2725 | case 4: |
2726 | /* Pre-adjust the loop counter. */ | |
2727 | operands[4] = GEN_INT (n_bytes - 8); | |
2728 | output_asm_insn ("ldi %4,%2", operands); | |
2729 | ||
2730 | /* Copying loop. */ | |
e4065f95 | 2731 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
2732 | output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands); | |
2733 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); | |
42819d4e | 2734 | output_asm_insn ("addib,>= -8,%2,.-12", operands); |
e4065f95 | 2735 | output_asm_insn ("{stws|stw},ma %6,4(%0)", operands); |
42819d4e | 2736 | |
2737 | /* Handle the residual. There could be up to 7 bytes of | |
2738 | residual to copy! */ | |
2739 | if (n_bytes % 8 != 0) | |
2740 | { | |
2741 | operands[4] = GEN_INT (n_bytes % 4); | |
2742 | if (n_bytes % 8 >= 4) | |
e4065f95 | 2743 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
42819d4e | 2744 | if (n_bytes % 4 != 0) |
34940871 | 2745 | output_asm_insn ("ldw 0(%1),%6", operands); |
42819d4e | 2746 | if (n_bytes % 8 >= 4) |
e4065f95 | 2747 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); |
42819d4e | 2748 | if (n_bytes % 4 != 0) |
e4065f95 | 2749 | output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands); |
42819d4e | 2750 | } |
2751 | return ""; | |
87ad11b0 | 2752 | |
42819d4e | 2753 | case 2: |
2754 | /* Pre-adjust the loop counter. */ | |
2755 | operands[4] = GEN_INT (n_bytes - 4); | |
2756 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2757 | |
42819d4e | 2758 | /* Copying loop. */ |
e4065f95 | 2759 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
2760 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands); | |
2761 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); | |
42819d4e | 2762 | output_asm_insn ("addib,>= -4,%2,.-12", operands); |
e4065f95 | 2763 | output_asm_insn ("{sths|sth},ma %6,2(%0)", operands); |
87ad11b0 | 2764 | |
42819d4e | 2765 | /* Handle the residual. */ |
2766 | if (n_bytes % 4 != 0) | |
2767 | { | |
2768 | if (n_bytes % 4 >= 2) | |
e4065f95 | 2769 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
42819d4e | 2770 | if (n_bytes % 2 != 0) |
34940871 | 2771 | output_asm_insn ("ldb 0(%1),%6", operands); |
42819d4e | 2772 | if (n_bytes % 4 >= 2) |
e4065f95 | 2773 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); |
42819d4e | 2774 | if (n_bytes % 2 != 0) |
34940871 | 2775 | output_asm_insn ("stb %6,0(%0)", operands); |
42819d4e | 2776 | } |
2777 | return ""; | |
87ad11b0 | 2778 | |
42819d4e | 2779 | case 1: |
2780 | /* Pre-adjust the loop counter. */ | |
2781 | operands[4] = GEN_INT (n_bytes - 2); | |
2782 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2783 | |
42819d4e | 2784 | /* Copying loop. */ |
e4065f95 | 2785 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands); |
2786 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands); | |
2787 | output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands); | |
42819d4e | 2788 | output_asm_insn ("addib,>= -2,%2,.-12", operands); |
e4065f95 | 2789 | output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands); |
87ad11b0 | 2790 | |
42819d4e | 2791 | /* Handle the residual. */ |
2792 | if (n_bytes % 2 != 0) | |
2793 | { | |
34940871 | 2794 | output_asm_insn ("ldb 0(%1),%3", operands); |
2795 | output_asm_insn ("stb %3,0(%0)", operands); | |
42819d4e | 2796 | } |
2797 | return ""; | |
87ad11b0 | 2798 | |
42819d4e | 2799 | default: |
2800 | abort (); | |
87ad11b0 | 2801 | } |
87ad11b0 | 2802 | } |
58e17b0b | 2803 | |
2804 | /* Count the number of insns necessary to handle this block move. | |
2805 | ||
2806 | Basic structure is the same as emit_block_move, except that we | |
2807 | count insns rather than emit them. */ | |
2808 | ||
611a88e1 | 2809 | static int |
008c057d | 2810 | compute_movmem_length (rtx insn) |
58e17b0b | 2811 | { |
2812 | rtx pat = PATTERN (insn); | |
fc1fb057 | 2813 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0)); |
2814 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0)); | |
42819d4e | 2815 | unsigned int n_insns = 0; |
58e17b0b | 2816 | |
2817 | /* We can't move more than four bytes at a time because the PA | |
2818 | has no longer integer move insns. (Could use fp mem ops?) */ | |
a7e1bb24 | 2819 | if (align > (TARGET_64BIT ? 8 : 4)) |
2820 | align = (TARGET_64BIT ? 8 : 4); | |
58e17b0b | 2821 | |
79bfe6ae | 2822 | /* The basic copying loop. */ |
42819d4e | 2823 | n_insns = 6; |
58e17b0b | 2824 | |
42819d4e | 2825 | /* Residuals. */ |
2826 | if (n_bytes % (2 * align) != 0) | |
58e17b0b | 2827 | { |
79bfe6ae | 2828 | if ((n_bytes % (2 * align)) >= align) |
2829 | n_insns += 2; | |
2830 | ||
2831 | if ((n_bytes % align) != 0) | |
2832 | n_insns += 2; | |
58e17b0b | 2833 | } |
42819d4e | 2834 | |
2835 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2836 | return n_insns * 4; | |
58e17b0b | 2837 | } |
a7e1bb24 | 2838 | |
2839 | /* Emit code to perform a block clear. | |
2840 | ||
2841 | OPERANDS[0] is the destination pointer as a REG, clobbered. | |
2842 | OPERANDS[1] is a register for temporary storage. | |
2843 | OPERANDS[2] is the size as a CONST_INT | |
2844 | OPERANDS[3] is the alignment safe to use, as a CONST_INT. */ | |
2845 | ||
2846 | const char * | |
2847 | output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) | |
2848 | { | |
2849 | int align = INTVAL (operands[3]); | |
2850 | unsigned long n_bytes = INTVAL (operands[2]); | |
2851 | ||
2852 | /* We can't clear more than a word at a time because the PA | |
2853 | has no longer integer move insns. */ | |
2854 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2855 | align = (TARGET_64BIT ? 8 : 4); | |
2856 | ||
2857 | /* Note that we know each loop below will execute at least twice | |
2858 | (else we would have open-coded the copy). */ | |
2859 | switch (align) | |
2860 | { | |
2861 | case 8: | |
2862 | /* Pre-adjust the loop counter. */ | |
2863 | operands[2] = GEN_INT (n_bytes - 16); | |
2864 | output_asm_insn ("ldi %2,%1", operands); | |
2865 | ||
2866 | /* Loop. */ | |
2867 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2868 | output_asm_insn ("addib,>= -16,%1,.-4", operands); | |
2869 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2870 | ||
2871 | /* Handle the residual. There could be up to 7 bytes of | |
2872 | residual to copy! */ | |
2873 | if (n_bytes % 16 != 0) | |
2874 | { | |
2875 | operands[2] = GEN_INT (n_bytes % 8); | |
2876 | if (n_bytes % 16 >= 8) | |
2877 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2878 | if (n_bytes % 8 != 0) | |
2879 | output_asm_insn ("stdby,e %%r0,%2(%0)", operands); | |
2880 | } | |
2881 | return ""; | |
2882 | ||
2883 | case 4: | |
2884 | /* Pre-adjust the loop counter. */ | |
2885 | operands[2] = GEN_INT (n_bytes - 8); | |
2886 | output_asm_insn ("ldi %2,%1", operands); | |
2887 | ||
2888 | /* Loop. */ | |
2889 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2890 | output_asm_insn ("addib,>= -8,%1,.-4", operands); | |
2891 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2892 | ||
2893 | /* Handle the residual. There could be up to 7 bytes of | |
2894 | residual to copy! */ | |
2895 | if (n_bytes % 8 != 0) | |
2896 | { | |
2897 | operands[2] = GEN_INT (n_bytes % 4); | |
2898 | if (n_bytes % 8 >= 4) | |
2899 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2900 | if (n_bytes % 4 != 0) | |
2901 | output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands); | |
2902 | } | |
2903 | return ""; | |
2904 | ||
2905 | case 2: | |
2906 | /* Pre-adjust the loop counter. */ | |
2907 | operands[2] = GEN_INT (n_bytes - 4); | |
2908 | output_asm_insn ("ldi %2,%1", operands); | |
2909 | ||
2910 | /* Loop. */ | |
2911 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2912 | output_asm_insn ("addib,>= -4,%1,.-4", operands); | |
2913 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2914 | ||
2915 | /* Handle the residual. */ | |
2916 | if (n_bytes % 4 != 0) | |
2917 | { | |
2918 | if (n_bytes % 4 >= 2) | |
2919 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2920 | if (n_bytes % 2 != 0) | |
2921 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2922 | } | |
2923 | return ""; | |
2924 | ||
2925 | case 1: | |
2926 | /* Pre-adjust the loop counter. */ | |
2927 | operands[2] = GEN_INT (n_bytes - 2); | |
2928 | output_asm_insn ("ldi %2,%1", operands); | |
2929 | ||
2930 | /* Loop. */ | |
2931 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2932 | output_asm_insn ("addib,>= -2,%1,.-4", operands); | |
2933 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2934 | ||
2935 | /* Handle the residual. */ | |
2936 | if (n_bytes % 2 != 0) | |
2937 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2938 | ||
2939 | return ""; | |
2940 | ||
2941 | default: | |
2942 | abort (); | |
2943 | } | |
2944 | } | |
2945 | ||
2946 | /* Count the number of insns necessary to handle this block move. | |
2947 | ||
2948 | Basic structure is the same as emit_block_move, except that we | |
2949 | count insns rather than emit them. */ | |
2950 | ||
2951 | static int | |
008c057d | 2952 | compute_clrmem_length (rtx insn) |
a7e1bb24 | 2953 | { |
2954 | rtx pat = PATTERN (insn); | |
2955 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0)); | |
2956 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0)); | |
2957 | unsigned int n_insns = 0; | |
2958 | ||
2959 | /* We can't clear more than a word at a time because the PA | |
2960 | has no longer integer move insns. */ | |
2961 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2962 | align = (TARGET_64BIT ? 8 : 4); | |
2963 | ||
2964 | /* The basic loop. */ | |
2965 | n_insns = 4; | |
2966 | ||
2967 | /* Residuals. */ | |
2968 | if (n_bytes % (2 * align) != 0) | |
2969 | { | |
2970 | if ((n_bytes % (2 * align)) >= align) | |
2971 | n_insns++; | |
2972 | ||
2973 | if ((n_bytes % align) != 0) | |
2974 | n_insns++; | |
2975 | } | |
2976 | ||
2977 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2978 | return n_insns * 4; | |
2979 | } | |
87ad11b0 | 2980 | \f |
2981 | ||
611a88e1 | 2982 | const char * |
5c1d8983 | 2983 | output_and (rtx *operands) |
e057641f | 2984 | { |
d6f01525 | 2985 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) |
e057641f | 2986 | { |
3745c59b | 2987 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
e057641f | 2988 | int ls0, ls1, ms0, p, len; |
2989 | ||
2990 | for (ls0 = 0; ls0 < 32; ls0++) | |
2991 | if ((mask & (1 << ls0)) == 0) | |
2992 | break; | |
2993 | ||
2994 | for (ls1 = ls0; ls1 < 32; ls1++) | |
2995 | if ((mask & (1 << ls1)) != 0) | |
2996 | break; | |
2997 | ||
2998 | for (ms0 = ls1; ms0 < 32; ms0++) | |
2999 | if ((mask & (1 << ms0)) == 0) | |
3000 | break; | |
3001 | ||
3002 | if (ms0 != 32) | |
ea52c577 | 3003 | abort (); |
e057641f | 3004 | |
3005 | if (ls1 == 32) | |
3006 | { | |
3007 | len = ls0; | |
3008 | ||
3009 | if (len == 0) | |
3010 | abort (); | |
3011 | ||
ef618fe4 | 3012 | operands[2] = GEN_INT (len); |
e4065f95 | 3013 | return "{extru|extrw,u} %1,31,%2,%0"; |
e057641f | 3014 | } |
3015 | else | |
3016 | { | |
3017 | /* We could use this `depi' for the case above as well, but `depi' | |
3018 | requires one more register file access than an `extru'. */ | |
3019 | ||
3020 | p = 31 - ls0; | |
3021 | len = ls1 - ls0; | |
3022 | ||
ef618fe4 | 3023 | operands[2] = GEN_INT (p); |
3024 | operands[3] = GEN_INT (len); | |
e4065f95 | 3025 | return "{depi|depwi} 0,%2,%3,%0"; |
e057641f | 3026 | } |
3027 | } | |
3028 | else | |
3029 | return "and %1,%2,%0"; | |
3030 | } | |
3031 | ||
5e3c5739 | 3032 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] |
3033 | storing the result in operands[0]. */ | |
9aadea62 | 3034 | const char * |
5c1d8983 | 3035 | output_64bit_and (rtx *operands) |
5e3c5739 | 3036 | { |
3037 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) | |
3038 | { | |
3039 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 3040 | int ls0, ls1, ms0, p, len; |
5e3c5739 | 3041 | |
3042 | for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++) | |
b7d86581 | 3043 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0) |
5e3c5739 | 3044 | break; |
3045 | ||
3046 | for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++) | |
b7d86581 | 3047 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0) |
5e3c5739 | 3048 | break; |
3049 | ||
3050 | for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++) | |
b7d86581 | 3051 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0) |
5e3c5739 | 3052 | break; |
3053 | ||
3054 | if (ms0 != HOST_BITS_PER_WIDE_INT) | |
b7d86581 | 3055 | abort (); |
5e3c5739 | 3056 | |
3057 | if (ls1 == HOST_BITS_PER_WIDE_INT) | |
3058 | { | |
3059 | len = ls0; | |
3060 | ||
3061 | if (len == 0) | |
3062 | abort (); | |
3063 | ||
3064 | operands[2] = GEN_INT (len); | |
3065 | return "extrd,u %1,63,%2,%0"; | |
3066 | } | |
3067 | else | |
3068 | { | |
3069 | /* We could use this `depi' for the case above as well, but `depi' | |
3070 | requires one more register file access than an `extru'. */ | |
3071 | ||
3072 | p = 63 - ls0; | |
3073 | len = ls1 - ls0; | |
3074 | ||
3075 | operands[2] = GEN_INT (p); | |
3076 | operands[3] = GEN_INT (len); | |
3077 | return "depdi 0,%2,%3,%0"; | |
3078 | } | |
3079 | } | |
3080 | else | |
3081 | return "and %1,%2,%0"; | |
3082 | } | |
3083 | ||
611a88e1 | 3084 | const char * |
5c1d8983 | 3085 | output_ior (rtx *operands) |
e057641f | 3086 | { |
3745c59b | 3087 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
57ed30e5 | 3088 | int bs0, bs1, p, len; |
6d36483b | 3089 | |
c9da5f4d | 3090 | if (INTVAL (operands[2]) == 0) |
3091 | return "copy %1,%0"; | |
e057641f | 3092 | |
c9da5f4d | 3093 | for (bs0 = 0; bs0 < 32; bs0++) |
3094 | if ((mask & (1 << bs0)) != 0) | |
3095 | break; | |
e057641f | 3096 | |
c9da5f4d | 3097 | for (bs1 = bs0; bs1 < 32; bs1++) |
3098 | if ((mask & (1 << bs1)) == 0) | |
3099 | break; | |
e057641f | 3100 | |
3745c59b | 3101 | if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask) |
ea52c577 | 3102 | abort (); |
e057641f | 3103 | |
c9da5f4d | 3104 | p = 31 - bs0; |
3105 | len = bs1 - bs0; | |
e057641f | 3106 | |
ef618fe4 | 3107 | operands[2] = GEN_INT (p); |
3108 | operands[3] = GEN_INT (len); | |
e4065f95 | 3109 | return "{depi|depwi} -1,%2,%3,%0"; |
e057641f | 3110 | } |
5e3c5739 | 3111 | |
3112 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] | |
3113 | storing the result in operands[0]. */ | |
9aadea62 | 3114 | const char * |
5c1d8983 | 3115 | output_64bit_ior (rtx *operands) |
5e3c5739 | 3116 | { |
3117 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 3118 | int bs0, bs1, p, len; |
5e3c5739 | 3119 | |
3120 | if (INTVAL (operands[2]) == 0) | |
3121 | return "copy %1,%0"; | |
3122 | ||
3123 | for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++) | |
b7d86581 | 3124 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0) |
5e3c5739 | 3125 | break; |
3126 | ||
3127 | for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++) | |
b7d86581 | 3128 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0) |
5e3c5739 | 3129 | break; |
3130 | ||
3131 | if (bs1 != HOST_BITS_PER_WIDE_INT | |
3132 | && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask) | |
b7d86581 | 3133 | abort (); |
5e3c5739 | 3134 | |
3135 | p = 63 - bs0; | |
3136 | len = bs1 - bs0; | |
3137 | ||
3138 | operands[2] = GEN_INT (p); | |
3139 | operands[3] = GEN_INT (len); | |
3140 | return "depdi -1,%2,%3,%0"; | |
3141 | } | |
e057641f | 3142 | \f |
58356836 | 3143 | /* Target hook for assembling integer objects. This code handles |
3144 | aligned SI and DI integers specially, since function references must | |
3145 | be preceded by P%. */ | |
3146 | ||
3147 | static bool | |
5c1d8983 | 3148 | pa_assemble_integer (rtx x, unsigned int size, int aligned_p) |
58356836 | 3149 | { |
3150 | if (size == UNITS_PER_WORD && aligned_p | |
3151 | && function_label_operand (x, VOIDmode)) | |
3152 | { | |
3153 | fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file); | |
3154 | output_addr_const (asm_out_file, x); | |
3155 | fputc ('\n', asm_out_file); | |
3156 | return true; | |
3157 | } | |
3158 | return default_assemble_integer (x, size, aligned_p); | |
3159 | } | |
3160 | \f | |
87ad11b0 | 3161 | /* Output an ascii string. */ |
57ed30e5 | 3162 | void |
5c1d8983 | 3163 | output_ascii (FILE *file, const char *p, int size) |
87ad11b0 | 3164 | { |
3165 | int i; | |
3166 | int chars_output; | |
5aedf60c | 3167 | unsigned char partial_output[16]; /* Max space 4 chars can occupy. */ |
87ad11b0 | 3168 | |
3169 | /* The HP assembler can only take strings of 256 characters at one | |
3170 | time. This is a limitation on input line length, *not* the | |
3171 | length of the string. Sigh. Even worse, it seems that the | |
3172 | restriction is in number of input characters (see \xnn & | |
3173 | \whatever). So we have to do this very carefully. */ | |
3174 | ||
9c0ac0fd | 3175 | fputs ("\t.STRING \"", file); |
87ad11b0 | 3176 | |
3177 | chars_output = 0; | |
3178 | for (i = 0; i < size; i += 4) | |
3179 | { | |
3180 | int co = 0; | |
3181 | int io = 0; | |
3182 | for (io = 0, co = 0; io < MIN (4, size - i); io++) | |
3183 | { | |
bf8aac3e | 3184 | register unsigned int c = (unsigned char) p[i + io]; |
87ad11b0 | 3185 | |
3186 | if (c == '\"' || c == '\\') | |
3187 | partial_output[co++] = '\\'; | |
3188 | if (c >= ' ' && c < 0177) | |
3189 | partial_output[co++] = c; | |
3190 | else | |
3191 | { | |
3192 | unsigned int hexd; | |
3193 | partial_output[co++] = '\\'; | |
3194 | partial_output[co++] = 'x'; | |
3195 | hexd = c / 16 - 0 + '0'; | |
3196 | if (hexd > '9') | |
3197 | hexd -= '9' - 'a' + 1; | |
3198 | partial_output[co++] = hexd; | |
3199 | hexd = c % 16 - 0 + '0'; | |
3200 | if (hexd > '9') | |
3201 | hexd -= '9' - 'a' + 1; | |
3202 | partial_output[co++] = hexd; | |
3203 | } | |
3204 | } | |
3205 | if (chars_output + co > 243) | |
3206 | { | |
9c0ac0fd | 3207 | fputs ("\"\n\t.STRING \"", file); |
87ad11b0 | 3208 | chars_output = 0; |
3209 | } | |
a584fe8a | 3210 | fwrite (partial_output, 1, (size_t) co, file); |
87ad11b0 | 3211 | chars_output += co; |
3212 | co = 0; | |
3213 | } | |
9c0ac0fd | 3214 | fputs ("\"\n", file); |
87ad11b0 | 3215 | } |
c533da59 | 3216 | |
3217 | /* Try to rewrite floating point comparisons & branches to avoid | |
3218 | useless add,tr insns. | |
3219 | ||
3220 | CHECK_NOTES is nonzero if we should examine REG_DEAD notes | |
3221 | to see if FPCC is dead. CHECK_NOTES is nonzero for the | |
3222 | first attempt to remove useless add,tr insns. It is zero | |
3223 | for the second pass as reorg sometimes leaves bogus REG_DEAD | |
3224 | notes lying around. | |
3225 | ||
3226 | When CHECK_NOTES is zero we can only eliminate add,tr insns | |
3227 | when there's a 1:1 correspondence between fcmp and ftest/fbranch | |
3228 | instructions. */ | |
611a88e1 | 3229 | static void |
5c1d8983 | 3230 | remove_useless_addtr_insns (int check_notes) |
c533da59 | 3231 | { |
3232 | rtx insn; | |
c533da59 | 3233 | static int pass = 0; |
3234 | ||
3235 | /* This is fairly cheap, so always run it when optimizing. */ | |
3236 | if (optimize > 0) | |
3237 | { | |
3238 | int fcmp_count = 0; | |
3239 | int fbranch_count = 0; | |
3240 | ||
3241 | /* Walk all the insns in this function looking for fcmp & fbranch | |
3242 | instructions. Keep track of how many of each we find. */ | |
2efea8c0 | 3243 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3244 | { |
3245 | rtx tmp; | |
3246 | ||
3247 | /* Ignore anything that isn't an INSN or a JUMP_INSN. */ | |
3248 | if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
3249 | continue; | |
3250 | ||
3251 | tmp = PATTERN (insn); | |
3252 | ||
3253 | /* It must be a set. */ | |
3254 | if (GET_CODE (tmp) != SET) | |
3255 | continue; | |
3256 | ||
3257 | /* If the destination is CCFP, then we've found an fcmp insn. */ | |
3258 | tmp = SET_DEST (tmp); | |
3259 | if (GET_CODE (tmp) == REG && REGNO (tmp) == 0) | |
3260 | { | |
3261 | fcmp_count++; | |
3262 | continue; | |
3263 | } | |
9840d99d | 3264 | |
c533da59 | 3265 | tmp = PATTERN (insn); |
3266 | /* If this is an fbranch instruction, bump the fbranch counter. */ | |
3267 | if (GET_CODE (tmp) == SET | |
3268 | && SET_DEST (tmp) == pc_rtx | |
3269 | && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE | |
3270 | && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE | |
3271 | && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG | |
3272 | && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0) | |
3273 | { | |
3274 | fbranch_count++; | |
3275 | continue; | |
3276 | } | |
3277 | } | |
3278 | ||
3279 | ||
3280 | /* Find all floating point compare + branch insns. If possible, | |
3281 | reverse the comparison & the branch to avoid add,tr insns. */ | |
2efea8c0 | 3282 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3283 | { |
3284 | rtx tmp, next; | |
3285 | ||
3286 | /* Ignore anything that isn't an INSN. */ | |
3287 | if (GET_CODE (insn) != INSN) | |
3288 | continue; | |
3289 | ||
3290 | tmp = PATTERN (insn); | |
3291 | ||
3292 | /* It must be a set. */ | |
3293 | if (GET_CODE (tmp) != SET) | |
3294 | continue; | |
3295 | ||
3296 | /* The destination must be CCFP, which is register zero. */ | |
3297 | tmp = SET_DEST (tmp); | |
3298 | if (GET_CODE (tmp) != REG || REGNO (tmp) != 0) | |
3299 | continue; | |
3300 | ||
3301 | /* INSN should be a set of CCFP. | |
3302 | ||
3303 | See if the result of this insn is used in a reversed FP | |
3304 | conditional branch. If so, reverse our condition and | |
3305 | the branch. Doing so avoids useless add,tr insns. */ | |
3306 | next = next_insn (insn); | |
3307 | while (next) | |
3308 | { | |
3309 | /* Jumps, calls and labels stop our search. */ | |
3310 | if (GET_CODE (next) == JUMP_INSN | |
3311 | || GET_CODE (next) == CALL_INSN | |
3312 | || GET_CODE (next) == CODE_LABEL) | |
3313 | break; | |
3314 | ||
3315 | /* As does another fcmp insn. */ | |
3316 | if (GET_CODE (next) == INSN | |
3317 | && GET_CODE (PATTERN (next)) == SET | |
3318 | && GET_CODE (SET_DEST (PATTERN (next))) == REG | |
3319 | && REGNO (SET_DEST (PATTERN (next))) == 0) | |
3320 | break; | |
3321 | ||
3322 | next = next_insn (next); | |
3323 | } | |
3324 | ||
3325 | /* Is NEXT_INSN a branch? */ | |
3326 | if (next | |
3327 | && GET_CODE (next) == JUMP_INSN) | |
3328 | { | |
3329 | rtx pattern = PATTERN (next); | |
3330 | ||
3331 | /* If it a reversed fp conditional branch (eg uses add,tr) | |
3332 | and CCFP dies, then reverse our conditional and the branch | |
3333 | to avoid the add,tr. */ | |
3334 | if (GET_CODE (pattern) == SET | |
3335 | && SET_DEST (pattern) == pc_rtx | |
3336 | && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE | |
3337 | && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE | |
3338 | && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG | |
3339 | && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0 | |
3340 | && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC | |
3341 | && (fcmp_count == fbranch_count | |
3342 | || (check_notes | |
3343 | && find_regno_note (next, REG_DEAD, 0)))) | |
3344 | { | |
3345 | /* Reverse the branch. */ | |
3346 | tmp = XEXP (SET_SRC (pattern), 1); | |
3347 | XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2); | |
3348 | XEXP (SET_SRC (pattern), 2) = tmp; | |
3349 | INSN_CODE (next) = -1; | |
3350 | ||
3351 | /* Reverse our condition. */ | |
3352 | tmp = PATTERN (insn); | |
3353 | PUT_CODE (XEXP (tmp, 1), | |
ea52c577 | 3354 | (reverse_condition_maybe_unordered |
3355 | (GET_CODE (XEXP (tmp, 1))))); | |
c533da59 | 3356 | } |
3357 | } | |
3358 | } | |
3359 | } | |
3360 | ||
3361 | pass = !pass; | |
3362 | ||
3363 | } | |
87ad11b0 | 3364 | \f |
ea52c577 | 3365 | /* You may have trouble believing this, but this is the 32 bit HP-PA |
3366 | stack layout. Wow. | |
87ad11b0 | 3367 | |
3368 | Offset Contents | |
3369 | ||
3370 | Variable arguments (optional; any number may be allocated) | |
3371 | ||
3372 | SP-(4*(N+9)) arg word N | |
3373 | : : | |
3374 | SP-56 arg word 5 | |
3375 | SP-52 arg word 4 | |
3376 | ||
3377 | Fixed arguments (must be allocated; may remain unused) | |
3378 | ||
3379 | SP-48 arg word 3 | |
3380 | SP-44 arg word 2 | |
3381 | SP-40 arg word 1 | |
3382 | SP-36 arg word 0 | |
3383 | ||
3384 | Frame Marker | |
3385 | ||
3386 | SP-32 External Data Pointer (DP) | |
3387 | SP-28 External sr4 | |
3388 | SP-24 External/stub RP (RP') | |
3389 | SP-20 Current RP | |
3390 | SP-16 Static Link | |
3391 | SP-12 Clean up | |
3392 | SP-8 Calling Stub RP (RP'') | |
3393 | SP-4 Previous SP | |
3394 | ||
3395 | Top of Frame | |
3396 | ||
3397 | SP-0 Stack Pointer (points to next available address) | |
3398 | ||
3399 | */ | |
3400 | ||
3401 | /* This function saves registers as follows. Registers marked with ' are | |
3402 | this function's registers (as opposed to the previous function's). | |
3403 | If a frame_pointer isn't needed, r4 is saved as a general register; | |
3404 | the space for the frame pointer is still allocated, though, to keep | |
3405 | things simple. | |
3406 | ||
3407 | ||
3408 | Top of Frame | |
3409 | ||
3410 | SP (FP') Previous FP | |
3411 | SP + 4 Alignment filler (sigh) | |
3412 | SP + 8 Space for locals reserved here. | |
3413 | . | |
3414 | . | |
3415 | . | |
3416 | SP + n All call saved register used. | |
3417 | . | |
3418 | . | |
3419 | . | |
3420 | SP + o All call saved fp registers used. | |
3421 | . | |
3422 | . | |
3423 | . | |
3424 | SP + p (SP') points to next available address. | |
6d36483b | 3425 | |
87ad11b0 | 3426 | */ |
3427 | ||
17d9b0c3 | 3428 | /* Global variables set by output_function_prologue(). */ |
cc858176 | 3429 | /* Size of frame. Need to know this to emit return insns from |
3430 | leaf procedures. */ | |
6bcdc1fb | 3431 | static HOST_WIDE_INT actual_fsize, local_fsize; |
3432 | static int save_fregs; | |
cc858176 | 3433 | |
daee63dd | 3434 | /* Emit RTL to store REG at the memory location specified by BASE+DISP. |
359a0be8 | 3435 | Handle case where DISP > 8k by using the add_high_const patterns. |
daee63dd | 3436 | |
3437 | Note in DISP > 8k case, we will leave the high part of the address | |
3438 | in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/ | |
7014838c | 3439 | |
6a2c16d6 | 3440 | static void |
6bcdc1fb | 3441 | store_reg (int reg, HOST_WIDE_INT disp, int base) |
87ad11b0 | 3442 | { |
6a2c16d6 | 3443 | rtx insn, dest, src, basereg; |
cc858176 | 3444 | |
3445 | src = gen_rtx_REG (word_mode, reg); | |
3446 | basereg = gen_rtx_REG (Pmode, base); | |
87ad11b0 | 3447 | if (VAL_14_BITS_P (disp)) |
daee63dd | 3448 | { |
cc858176 | 3449 | dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
6a2c16d6 | 3450 | insn = emit_move_insn (dest, src); |
daee63dd | 3451 | } |
6bcdc1fb | 3452 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3453 | { | |
3454 | rtx delta = GEN_INT (disp); | |
3455 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3456 | ||
3457 | emit_move_insn (tmpreg, delta); | |
3458 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
3459 | dest = gen_rtx_MEM (word_mode, tmpreg); | |
3460 | insn = emit_move_insn (dest, src); | |
3461 | if (DO_FRAME_NOTES) | |
3462 | { | |
3463 | REG_NOTES (insn) | |
3464 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3465 | gen_rtx_SET (VOIDmode, | |
3466 | gen_rtx_MEM (word_mode, | |
3467 | gen_rtx_PLUS (word_mode, basereg, | |
3468 | delta)), | |
3469 | src), | |
3470 | REG_NOTES (insn)); | |
3471 | } | |
3472 | } | |
daee63dd | 3473 | else |
3474 | { | |
cc858176 | 3475 | rtx delta = GEN_INT (disp); |
3476 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3477 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 3478 | |
cc858176 | 3479 | emit_move_insn (tmpreg, high); |
3480 | dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
6a2c16d6 | 3481 | insn = emit_move_insn (dest, src); |
3482 | if (DO_FRAME_NOTES) | |
3483 | { | |
3484 | REG_NOTES (insn) | |
3485 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3486 | gen_rtx_SET (VOIDmode, | |
3487 | gen_rtx_MEM (word_mode, | |
3488 | gen_rtx_PLUS (word_mode, basereg, | |
3489 | delta)), | |
3490 | src), | |
3491 | REG_NOTES (insn)); | |
3492 | } | |
daee63dd | 3493 | } |
6a2c16d6 | 3494 | |
3495 | if (DO_FRAME_NOTES) | |
3496 | RTX_FRAME_RELATED_P (insn) = 1; | |
daee63dd | 3497 | } |
3498 | ||
a584fe8a | 3499 | /* Emit RTL to store REG at the memory location specified by BASE and then |
3500 | add MOD to BASE. MOD must be <= 8k. */ | |
daee63dd | 3501 | |
a584fe8a | 3502 | static void |
6bcdc1fb | 3503 | store_reg_modify (int base, int reg, HOST_WIDE_INT mod) |
a584fe8a | 3504 | { |
3505 | rtx insn, basereg, srcreg, delta; | |
3506 | ||
6bcdc1fb | 3507 | if (!VAL_14_BITS_P (mod)) |
a584fe8a | 3508 | abort (); |
3509 | ||
3510 | basereg = gen_rtx_REG (Pmode, base); | |
3511 | srcreg = gen_rtx_REG (word_mode, reg); | |
3512 | delta = GEN_INT (mod); | |
3513 | ||
3514 | insn = emit_insn (gen_post_store (basereg, srcreg, delta)); | |
3515 | if (DO_FRAME_NOTES) | |
3516 | { | |
3517 | RTX_FRAME_RELATED_P (insn) = 1; | |
3518 | ||
3519 | /* RTX_FRAME_RELATED_P must be set on each frame related set | |
3520 | in a parallel with more than one element. Don't set | |
3521 | RTX_FRAME_RELATED_P in the first set if reg is temporary | |
3522 | register 1. The effect of this operation is recorded in | |
3523 | the initial copy. */ | |
3524 | if (reg != 1) | |
3525 | { | |
3526 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1; | |
3527 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; | |
3528 | } | |
3529 | else | |
3530 | { | |
3531 | /* The first element of a PARALLEL is always processed if it is | |
3532 | a SET. Thus, we need an expression list for this case. */ | |
3533 | REG_NOTES (insn) | |
3534 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3535 | gen_rtx_SET (VOIDmode, basereg, | |
3536 | gen_rtx_PLUS (word_mode, basereg, delta)), | |
3537 | REG_NOTES (insn)); | |
3538 | } | |
3539 | } | |
3540 | } | |
3541 | ||
3542 | /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case | |
3543 | where DISP > 8k by using the add_high_const patterns. NOTE indicates | |
3544 | whether to add a frame note or not. | |
3545 | ||
3546 | In the DISP > 8k case, we leave the high part of the address in %r1. | |
3547 | There is code in expand_hppa_{prologue,epilogue} that knows about this. */ | |
7014838c | 3548 | |
6a2c16d6 | 3549 | static void |
6bcdc1fb | 3550 | set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note) |
87ad11b0 | 3551 | { |
6a2c16d6 | 3552 | rtx insn; |
cc858176 | 3553 | |
87ad11b0 | 3554 | if (VAL_14_BITS_P (disp)) |
cc858176 | 3555 | { |
6a2c16d6 | 3556 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
3557 | plus_constant (gen_rtx_REG (Pmode, base), disp)); | |
cc858176 | 3558 | } |
6bcdc1fb | 3559 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3560 | { | |
3561 | rtx basereg = gen_rtx_REG (Pmode, base); | |
3562 | rtx delta = GEN_INT (disp); | |
3563 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3564 | ||
3565 | emit_move_insn (tmpreg, delta); | |
3566 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), | |
3567 | gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
3568 | } | |
87ad11b0 | 3569 | else |
daee63dd | 3570 | { |
6a2c16d6 | 3571 | rtx basereg = gen_rtx_REG (Pmode, base); |
cc858176 | 3572 | rtx delta = GEN_INT (disp); |
6bcdc1fb | 3573 | rtx tmpreg = gen_rtx_REG (Pmode, 1); |
6a2c16d6 | 3574 | |
6bcdc1fb | 3575 | emit_move_insn (tmpreg, |
6a2c16d6 | 3576 | gen_rtx_PLUS (Pmode, basereg, |
cc858176 | 3577 | gen_rtx_HIGH (Pmode, delta))); |
6a2c16d6 | 3578 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
6bcdc1fb | 3579 | gen_rtx_LO_SUM (Pmode, tmpreg, delta)); |
daee63dd | 3580 | } |
6a2c16d6 | 3581 | |
a584fe8a | 3582 | if (DO_FRAME_NOTES && note) |
6a2c16d6 | 3583 | RTX_FRAME_RELATED_P (insn) = 1; |
87ad11b0 | 3584 | } |
3585 | ||
6bcdc1fb | 3586 | HOST_WIDE_INT |
3587 | compute_frame_size (HOST_WIDE_INT size, int *fregs_live) | |
87ad11b0 | 3588 | { |
256f9b65 | 3589 | int freg_saved = 0; |
3590 | int i, j; | |
3591 | ||
3592 | /* The code in hppa_expand_prologue and hppa_expand_epilogue must | |
3593 | be consistent with the rounding and size calculation done here. | |
3594 | Change them at the same time. */ | |
3595 | ||
3596 | /* We do our own stack alignment. First, round the size of the | |
3597 | stack locals up to a word boundary. */ | |
3598 | size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3599 | ||
3600 | /* Space for previous frame pointer + filler. If any frame is | |
3601 | allocated, we need to add in the STARTING_FRAME_OFFSET. We | |
3602 | waste some space here for the sake of HP compatibility. The | |
3603 | first slot is only used when the frame pointer is needed. */ | |
3604 | if (size || frame_pointer_needed) | |
3605 | size += STARTING_FRAME_OFFSET; | |
3606 | ||
a584fe8a | 3607 | /* If the current function calls __builtin_eh_return, then we need |
3608 | to allocate stack space for registers that will hold data for | |
3609 | the exception handler. */ | |
3610 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3611 | { | |
3612 | unsigned int i; | |
3613 | ||
3614 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
3615 | continue; | |
256f9b65 | 3616 | size += i * UNITS_PER_WORD; |
a584fe8a | 3617 | } |
3618 | ||
3a51bad9 | 3619 | /* Account for space used by the callee general register saves. */ |
256f9b65 | 3620 | for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--) |
7f7c4869 | 3621 | if (regs_ever_live[i]) |
256f9b65 | 3622 | size += UNITS_PER_WORD; |
df0651dc | 3623 | |
3a51bad9 | 3624 | /* Account for space used by the callee floating point register saves. */ |
bac38c40 | 3625 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
5e3c5739 | 3626 | if (regs_ever_live[i] |
256f9b65 | 3627 | || (!TARGET_64BIT && regs_ever_live[i + 1])) |
df0651dc | 3628 | { |
256f9b65 | 3629 | freg_saved = 1; |
002fc5f7 | 3630 | |
3a51bad9 | 3631 | /* We always save both halves of the FP register, so always |
3632 | increment the frame size by 8 bytes. */ | |
256f9b65 | 3633 | size += 8; |
df0651dc | 3634 | } |
3635 | ||
256f9b65 | 3636 | /* If any of the floating registers are saved, account for the |
3637 | alignment needed for the floating point register save block. */ | |
3638 | if (freg_saved) | |
3639 | { | |
3640 | size = (size + 7) & ~7; | |
3641 | if (fregs_live) | |
3642 | *fregs_live = 1; | |
3643 | } | |
3644 | ||
3a51bad9 | 3645 | /* The various ABIs include space for the outgoing parameters in the |
256f9b65 | 3646 | size of the current function's stack frame. We don't need to align |
3647 | for the outgoing arguments as their alignment is set by the final | |
3648 | rounding for the frame as a whole. */ | |
3649 | size += current_function_outgoing_args_size; | |
3a51bad9 | 3650 | |
3651 | /* Allocate space for the fixed frame marker. This space must be | |
e9ec370e | 3652 | allocated for any function that makes calls or allocates |
3a51bad9 | 3653 | stack space. */ |
256f9b65 | 3654 | if (!current_function_is_leaf || size) |
e9ec370e | 3655 | size += TARGET_64BIT ? 48 : 32; |
5e3c5739 | 3656 | |
256f9b65 | 3657 | /* Finally, round to the preferred stack boundary. */ |
2247cc5f | 3658 | return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1) |
3659 | & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
87ad11b0 | 3660 | } |
6d36483b | 3661 | |
17d9b0c3 | 3662 | /* Generate the assembly code for function entry. FILE is a stdio |
3663 | stream to output the code to. SIZE is an int: how many units of | |
3664 | temporary storage to allocate. | |
3665 | ||
3666 | Refer to the array `regs_ever_live' to determine which registers to | |
3667 | save; `regs_ever_live[I]' is nonzero if register number I is ever | |
3668 | used in the function. This function is responsible for knowing | |
3669 | which registers should not be saved even if used. */ | |
3670 | ||
3671 | /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block | |
3672 | of memory. If any fpu reg is used in the function, we allocate | |
3673 | such a block here, at the bottom of the frame, just in case it's needed. | |
3674 | ||
3675 | If this function is a leaf procedure, then we may choose not | |
3676 | to do a "save" insn. The decision about whether or not | |
3677 | to do this is made in regclass.c. */ | |
3678 | ||
6988553d | 3679 | static void |
5c1d8983 | 3680 | pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 3681 | { |
d151162a | 3682 | /* The function's label and associated .PROC must never be |
3683 | separated and must be output *after* any profiling declarations | |
3684 | to avoid changing spaces/subspaces within a procedure. */ | |
3685 | ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3686 | fputs ("\t.PROC\n", file); | |
3687 | ||
daee63dd | 3688 | /* hppa_expand_prologue does the dirty work now. We just need |
3689 | to output the assembler directives which denote the start | |
3690 | of a function. */ | |
6bcdc1fb | 3691 | fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize); |
df6edefa | 3692 | if (regs_ever_live[2]) |
9c0ac0fd | 3693 | fputs (",CALLS,SAVE_RP", file); |
daee63dd | 3694 | else |
9c0ac0fd | 3695 | fputs (",NO_CALLS", file); |
f3ba7709 | 3696 | |
e9ec370e | 3697 | /* The SAVE_SP flag is used to indicate that register %r3 is stored |
3698 | at the beginning of the frame and that it is used as the frame | |
3699 | pointer for the frame. We do this because our current frame | |
3700 | layout doesn't conform to that specified in the the HP runtime | |
3701 | documentation and we need a way to indicate to programs such as | |
3702 | GDB where %r3 is saved. The SAVE_SP flag was chosen because it | |
3703 | isn't used by HP compilers but is supported by the assembler. | |
3704 | However, SAVE_SP is supposed to indicate that the previous stack | |
3705 | pointer has been saved in the frame marker. */ | |
f3ba7709 | 3706 | if (frame_pointer_needed) |
9c0ac0fd | 3707 | fputs (",SAVE_SP", file); |
f3ba7709 | 3708 | |
a9960cdc | 3709 | /* Pass on information about the number of callee register saves |
9b0c95be | 3710 | performed in the prologue. |
3711 | ||
3712 | The compiler is supposed to pass the highest register number | |
6d36483b | 3713 | saved, the assembler then has to adjust that number before |
9b0c95be | 3714 | entering it into the unwind descriptor (to account for any |
6d36483b | 3715 | caller saved registers with lower register numbers than the |
9b0c95be | 3716 | first callee saved register). */ |
3717 | if (gr_saved) | |
3718 | fprintf (file, ",ENTRY_GR=%d", gr_saved + 2); | |
3719 | ||
3720 | if (fr_saved) | |
3721 | fprintf (file, ",ENTRY_FR=%d", fr_saved + 11); | |
a9960cdc | 3722 | |
9c0ac0fd | 3723 | fputs ("\n\t.ENTRY\n", file); |
daee63dd | 3724 | |
2efea8c0 | 3725 | remove_useless_addtr_insns (0); |
daee63dd | 3726 | } |
3727 | ||
57ed30e5 | 3728 | void |
5c1d8983 | 3729 | hppa_expand_prologue (void) |
daee63dd | 3730 | { |
afd7b680 | 3731 | int merge_sp_adjust_with_store = 0; |
6bcdc1fb | 3732 | HOST_WIDE_INT size = get_frame_size (); |
3733 | HOST_WIDE_INT offset; | |
3734 | int i; | |
a584fe8a | 3735 | rtx insn, tmpreg; |
daee63dd | 3736 | |
a9960cdc | 3737 | gr_saved = 0; |
3738 | fr_saved = 0; | |
3ddcbb9d | 3739 | save_fregs = 0; |
3a51bad9 | 3740 | |
256f9b65 | 3741 | /* Compute total size for frame pointer, filler, locals and rounding to |
3742 | the next word boundary. Similar code appears in compute_frame_size | |
3743 | and must be changed in tandem with this code. */ | |
3744 | local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3745 | if (local_fsize || frame_pointer_needed) | |
3746 | local_fsize += STARTING_FRAME_OFFSET; | |
3a51bad9 | 3747 | |
a1ab4fa3 | 3748 | actual_fsize = compute_frame_size (size, &save_fregs); |
87ad11b0 | 3749 | |
daee63dd | 3750 | /* Compute a few things we will use often. */ |
440c23df | 3751 | tmpreg = gen_rtx_REG (word_mode, 1); |
87ad11b0 | 3752 | |
6d36483b | 3753 | /* Save RP first. The calling conventions manual states RP will |
cc858176 | 3754 | always be stored into the caller's frame at sp - 20 or sp - 16 |
5e3c5739 | 3755 | depending on which ABI is in use. */ |
a584fe8a | 3756 | if (regs_ever_live[2] || current_function_calls_eh_return) |
6a2c16d6 | 3757 | store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM); |
6d36483b | 3758 | |
daee63dd | 3759 | /* Allocate the local frame and set up the frame pointer if needed. */ |
58361f39 | 3760 | if (actual_fsize != 0) |
3761 | { | |
3762 | if (frame_pointer_needed) | |
3763 | { | |
3764 | /* Copy the old frame pointer temporarily into %r1. Set up the | |
3765 | new stack pointer, then store away the saved old frame pointer | |
a584fe8a | 3766 | into the stack at sp and at the same time update the stack |
3767 | pointer by actual_fsize bytes. Two versions, first | |
58361f39 | 3768 | handles small (<8k) frames. The second handles large (>=8k) |
3769 | frames. */ | |
a584fe8a | 3770 | insn = emit_move_insn (tmpreg, frame_pointer_rtx); |
3771 | if (DO_FRAME_NOTES) | |
cc858176 | 3772 | { |
a584fe8a | 3773 | /* We need to record the frame pointer save here since the |
3774 | new frame pointer is set in the following insn. */ | |
3775 | RTX_FRAME_RELATED_P (insn) = 1; | |
3776 | REG_NOTES (insn) | |
3777 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3778 | gen_rtx_SET (VOIDmode, | |
3779 | gen_rtx_MEM (word_mode, stack_pointer_rtx), | |
3780 | frame_pointer_rtx), | |
3781 | REG_NOTES (insn)); | |
cc858176 | 3782 | } |
a584fe8a | 3783 | |
3784 | insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); | |
3785 | if (DO_FRAME_NOTES) | |
3786 | RTX_FRAME_RELATED_P (insn) = 1; | |
3787 | ||
3788 | if (VAL_14_BITS_P (actual_fsize)) | |
3789 | store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize); | |
58361f39 | 3790 | else |
3791 | { | |
3792 | /* It is incorrect to store the saved frame pointer at *sp, | |
3793 | then increment sp (writes beyond the current stack boundary). | |
3794 | ||
3795 | So instead use stwm to store at *sp and post-increment the | |
3796 | stack pointer as an atomic operation. Then increment sp to | |
3797 | finish allocating the new frame. */ | |
6bcdc1fb | 3798 | HOST_WIDE_INT adjust1 = 8192 - 64; |
3799 | HOST_WIDE_INT adjust2 = actual_fsize - adjust1; | |
cc858176 | 3800 | |
a584fe8a | 3801 | store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1); |
6a2c16d6 | 3802 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3803 | adjust2, 1); |
58361f39 | 3804 | } |
a584fe8a | 3805 | |
e9ec370e | 3806 | /* We set SAVE_SP in frames that need a frame pointer. Thus, |
3807 | we need to store the previous stack pointer (frame pointer) | |
3808 | into the frame marker on targets that use the HP unwind | |
3809 | library. This allows the HP unwind library to be used to | |
3810 | unwind GCC frames. However, we are not fully compatible | |
3811 | with the HP library because our frame layout differs from | |
3812 | that specified in the HP runtime specification. | |
3813 | ||
3814 | We don't want a frame note on this instruction as the frame | |
3815 | marker moves during dynamic stack allocation. | |
3816 | ||
3817 | This instruction also serves as a blockage to prevent | |
3818 | register spills from being scheduled before the stack | |
3819 | pointer is raised. This is necessary as we store | |
3820 | registers using the frame pointer as a base register, | |
3821 | and the frame pointer is set before sp is raised. */ | |
3822 | if (TARGET_HPUX_UNWIND_LIBRARY) | |
3823 | { | |
3824 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, | |
3825 | GEN_INT (TARGET_64BIT ? -8 : -4)); | |
3826 | ||
3827 | emit_move_insn (gen_rtx_MEM (word_mode, addr), | |
3828 | frame_pointer_rtx); | |
3829 | } | |
3830 | else | |
3831 | emit_insn (gen_blockage ()); | |
58361f39 | 3832 | } |
3833 | /* no frame pointer needed. */ | |
3834 | else | |
3835 | { | |
3836 | /* In some cases we can perform the first callee register save | |
3837 | and allocating the stack frame at the same time. If so, just | |
3838 | make a note of it and defer allocating the frame until saving | |
3839 | the callee registers. */ | |
df6edefa | 3840 | if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0) |
58361f39 | 3841 | merge_sp_adjust_with_store = 1; |
3842 | /* Can not optimize. Adjust the stack frame by actual_fsize | |
3843 | bytes. */ | |
3844 | else | |
6a2c16d6 | 3845 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3846 | actual_fsize, 1); |
58361f39 | 3847 | } |
372ef038 | 3848 | } |
3849 | ||
6d36483b | 3850 | /* Normal register save. |
daee63dd | 3851 | |
3852 | Do not save the frame pointer in the frame_pointer_needed case. It | |
3853 | was done earlier. */ | |
87ad11b0 | 3854 | if (frame_pointer_needed) |
3855 | { | |
a584fe8a | 3856 | offset = local_fsize; |
3857 | ||
3858 | /* Saving the EH return data registers in the frame is the simplest | |
3859 | way to get the frame unwind information emitted. We put them | |
3860 | just before the general registers. */ | |
3861 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3862 | { | |
3863 | unsigned int i, regno; | |
3864 | ||
3865 | for (i = 0; ; ++i) | |
3866 | { | |
3867 | regno = EH_RETURN_DATA_REGNO (i); | |
3868 | if (regno == INVALID_REGNUM) | |
3869 | break; | |
3870 | ||
3871 | store_reg (regno, offset, FRAME_POINTER_REGNUM); | |
3872 | offset += UNITS_PER_WORD; | |
3873 | } | |
3874 | } | |
3875 | ||
3876 | for (i = 18; i >= 4; i--) | |
98328a39 | 3877 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3878 | { |
6a2c16d6 | 3879 | store_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 3880 | offset += UNITS_PER_WORD; |
a9960cdc | 3881 | gr_saved++; |
87ad11b0 | 3882 | } |
7f7c4869 | 3883 | /* Account for %r3 which is saved in a special place. */ |
9b0c95be | 3884 | gr_saved++; |
87ad11b0 | 3885 | } |
daee63dd | 3886 | /* No frame pointer needed. */ |
87ad11b0 | 3887 | else |
3888 | { | |
a584fe8a | 3889 | offset = local_fsize - actual_fsize; |
3890 | ||
3891 | /* Saving the EH return data registers in the frame is the simplest | |
3892 | way to get the frame unwind information emitted. */ | |
3893 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3894 | { | |
3895 | unsigned int i, regno; | |
3896 | ||
3897 | for (i = 0; ; ++i) | |
3898 | { | |
3899 | regno = EH_RETURN_DATA_REGNO (i); | |
3900 | if (regno == INVALID_REGNUM) | |
3901 | break; | |
3902 | ||
3903 | /* If merge_sp_adjust_with_store is nonzero, then we can | |
3904 | optimize the first save. */ | |
3905 | if (merge_sp_adjust_with_store) | |
3906 | { | |
3907 | store_reg_modify (STACK_POINTER_REGNUM, regno, -offset); | |
3908 | merge_sp_adjust_with_store = 0; | |
3909 | } | |
3910 | else | |
3911 | store_reg (regno, offset, STACK_POINTER_REGNUM); | |
3912 | offset += UNITS_PER_WORD; | |
3913 | } | |
3914 | } | |
3915 | ||
3916 | for (i = 18; i >= 3; i--) | |
98328a39 | 3917 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3918 | { |
6d36483b | 3919 | /* If merge_sp_adjust_with_store is nonzero, then we can |
afd7b680 | 3920 | optimize the first GR save. */ |
201f01e9 | 3921 | if (merge_sp_adjust_with_store) |
afd7b680 | 3922 | { |
a584fe8a | 3923 | store_reg_modify (STACK_POINTER_REGNUM, i, -offset); |
afd7b680 | 3924 | merge_sp_adjust_with_store = 0; |
afd7b680 | 3925 | } |
3926 | else | |
6a2c16d6 | 3927 | store_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 3928 | offset += UNITS_PER_WORD; |
a9960cdc | 3929 | gr_saved++; |
87ad11b0 | 3930 | } |
daee63dd | 3931 | |
afd7b680 | 3932 | /* If we wanted to merge the SP adjustment with a GR save, but we never |
daee63dd | 3933 | did any GR saves, then just emit the adjustment here. */ |
201f01e9 | 3934 | if (merge_sp_adjust_with_store) |
6a2c16d6 | 3935 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3936 | actual_fsize, 1); |
87ad11b0 | 3937 | } |
6d36483b | 3938 | |
df6edefa | 3939 | /* The hppa calling conventions say that %r19, the pic offset |
3940 | register, is saved at sp - 32 (in this function's frame) | |
3941 | when generating PIC code. FIXME: What is the correct thing | |
3942 | to do for functions which make no calls and allocate no | |
3943 | frame? Do we need to allocate a frame, or can we just omit | |
8f177faf | 3944 | the save? For now we'll just omit the save. |
3945 | ||
3946 | We don't want a note on this insn as the frame marker can | |
3947 | move if there is a dynamic stack allocation. */ | |
df6edefa | 3948 | if (flag_pic && actual_fsize != 0 && !TARGET_64BIT) |
8f177faf | 3949 | { |
3950 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32)); | |
3951 | ||
3952 | emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx); | |
3953 | ||
3954 | } | |
df6edefa | 3955 | |
87ad11b0 | 3956 | /* Align pointer properly (doubleword boundary). */ |
3957 | offset = (offset + 7) & ~7; | |
3958 | ||
3959 | /* Floating point register store. */ | |
3960 | if (save_fregs) | |
87ad11b0 | 3961 | { |
a584fe8a | 3962 | rtx base; |
3963 | ||
daee63dd | 3964 | /* First get the frame or stack pointer to the start of the FP register |
3965 | save area. */ | |
a1ab4fa3 | 3966 | if (frame_pointer_needed) |
a584fe8a | 3967 | { |
3968 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); | |
3969 | base = frame_pointer_rtx; | |
3970 | } | |
a1ab4fa3 | 3971 | else |
a584fe8a | 3972 | { |
3973 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); | |
3974 | base = stack_pointer_rtx; | |
3975 | } | |
daee63dd | 3976 | |
3977 | /* Now actually save the FP registers. */ | |
bac38c40 | 3978 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
7f7c4869 | 3979 | { |
5e3c5739 | 3980 | if (regs_ever_live[i] |
3981 | || (! TARGET_64BIT && regs_ever_live[i + 1])) | |
7f7c4869 | 3982 | { |
6a2c16d6 | 3983 | rtx addr, insn, reg; |
cc858176 | 3984 | addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); |
3985 | reg = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 3986 | insn = emit_move_insn (addr, reg); |
3987 | if (DO_FRAME_NOTES) | |
3988 | { | |
3989 | RTX_FRAME_RELATED_P (insn) = 1; | |
a584fe8a | 3990 | if (TARGET_64BIT) |
3991 | { | |
3992 | rtx mem = gen_rtx_MEM (DFmode, | |
3993 | plus_constant (base, offset)); | |
3994 | REG_NOTES (insn) | |
3995 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3996 | gen_rtx_SET (VOIDmode, mem, reg), | |
3997 | REG_NOTES (insn)); | |
3998 | } | |
3999 | else | |
4000 | { | |
4001 | rtx meml = gen_rtx_MEM (SFmode, | |
4002 | plus_constant (base, offset)); | |
4003 | rtx memr = gen_rtx_MEM (SFmode, | |
4004 | plus_constant (base, offset + 4)); | |
4005 | rtx regl = gen_rtx_REG (SFmode, i); | |
4006 | rtx regr = gen_rtx_REG (SFmode, i + 1); | |
4007 | rtx setl = gen_rtx_SET (VOIDmode, meml, regl); | |
4008 | rtx setr = gen_rtx_SET (VOIDmode, memr, regr); | |
4009 | rtvec vec; | |
4010 | ||
4011 | RTX_FRAME_RELATED_P (setl) = 1; | |
4012 | RTX_FRAME_RELATED_P (setr) = 1; | |
4013 | vec = gen_rtvec (2, setl, setr); | |
4014 | REG_NOTES (insn) | |
4015 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
4016 | gen_rtx_SEQUENCE (VOIDmode, vec), | |
4017 | REG_NOTES (insn)); | |
4018 | } | |
6a2c16d6 | 4019 | } |
4020 | offset += GET_MODE_SIZE (DFmode); | |
7f7c4869 | 4021 | fr_saved++; |
4022 | } | |
4023 | } | |
87ad11b0 | 4024 | } |
4025 | } | |
4026 | ||
cc858176 | 4027 | /* Emit RTL to load REG from the memory location specified by BASE+DISP. |
4028 | Handle case where DISP > 8k by using the add_high_const patterns. */ | |
4029 | ||
6a2c16d6 | 4030 | static void |
6bcdc1fb | 4031 | load_reg (int reg, HOST_WIDE_INT disp, int base) |
cc858176 | 4032 | { |
6bcdc1fb | 4033 | rtx dest = gen_rtx_REG (word_mode, reg); |
4034 | rtx basereg = gen_rtx_REG (Pmode, base); | |
4035 | rtx src; | |
cc858176 | 4036 | |
cc858176 | 4037 | if (VAL_14_BITS_P (disp)) |
6bcdc1fb | 4038 | src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
4039 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) | |
cc858176 | 4040 | { |
6bcdc1fb | 4041 | rtx delta = GEN_INT (disp); |
4042 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
4043 | ||
4044 | emit_move_insn (tmpreg, delta); | |
4045 | if (TARGET_DISABLE_INDEXING) | |
4046 | { | |
4047 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
4048 | src = gen_rtx_MEM (word_mode, tmpreg); | |
4049 | } | |
4050 | else | |
4051 | src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
cc858176 | 4052 | } |
4053 | else | |
4054 | { | |
4055 | rtx delta = GEN_INT (disp); | |
4056 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
4057 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 4058 | |
cc858176 | 4059 | emit_move_insn (tmpreg, high); |
4060 | src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
cc858176 | 4061 | } |
6bcdc1fb | 4062 | |
4063 | emit_move_insn (dest, src); | |
cc858176 | 4064 | } |
daee63dd | 4065 | |
2247cc5f | 4066 | /* Update the total code bytes output to the text section. */ |
4067 | ||
4068 | static void | |
5c1d8983 | 4069 | update_total_code_bytes (int nbytes) |
2247cc5f | 4070 | { |
4071 | if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM) | |
8a05c3c2 | 4072 | && !IN_NAMED_SECTION_P (cfun->decl)) |
2247cc5f | 4073 | { |
4074 | if (INSN_ADDRESSES_SET_P ()) | |
4075 | { | |
4076 | unsigned long old_total = total_code_bytes; | |
4077 | ||
4078 | total_code_bytes += nbytes; | |
4079 | ||
4080 | /* Be prepared to handle overflows. */ | |
4081 | if (old_total > total_code_bytes) | |
4082 | total_code_bytes = -1; | |
4083 | } | |
4084 | else | |
4085 | total_code_bytes = -1; | |
4086 | } | |
4087 | } | |
4088 | ||
17d9b0c3 | 4089 | /* This function generates the assembly code for function exit. |
4090 | Args are as for output_function_prologue (). | |
4091 | ||
4092 | The function epilogue should not depend on the current stack | |
4093 | pointer! It should use the frame pointer only. This is mandatory | |
4094 | because of alloca; we also take advantage of it to omit stack | |
6dc3b0d9 | 4095 | adjustments before returning. */ |
17d9b0c3 | 4096 | |
4097 | static void | |
5c1d8983 | 4098 | pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 4099 | { |
3695c664 | 4100 | rtx insn = get_last_insn (); |
4101 | ||
2247cc5f | 4102 | last_address = 0; |
4103 | ||
daee63dd | 4104 | /* hppa_expand_epilogue does the dirty work now. We just need |
4105 | to output the assembler directives which denote the end | |
3695c664 | 4106 | of a function. |
4107 | ||
4108 | To make debuggers happy, emit a nop if the epilogue was completely | |
4109 | eliminated due to a volatile call as the last insn in the | |
6d36483b | 4110 | current function. That way the return address (in %r2) will |
3695c664 | 4111 | always point to a valid instruction in the current function. */ |
4112 | ||
4113 | /* Get the last real insn. */ | |
4114 | if (GET_CODE (insn) == NOTE) | |
4115 | insn = prev_real_insn (insn); | |
4116 | ||
4117 | /* If it is a sequence, then look inside. */ | |
4118 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
4119 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
4120 | ||
6d36483b | 4121 | /* If insn is a CALL_INSN, then it must be a call to a volatile |
3695c664 | 4122 | function (otherwise there would be epilogue insns). */ |
4123 | if (insn && GET_CODE (insn) == CALL_INSN) | |
90c41894 | 4124 | { |
4125 | fputs ("\tnop\n", file); | |
4126 | last_address += 4; | |
4127 | } | |
6d36483b | 4128 | |
9c0ac0fd | 4129 | fputs ("\t.EXIT\n\t.PROCEND\n", file); |
90c41894 | 4130 | |
2247cc5f | 4131 | if (INSN_ADDRESSES_SET_P ()) |
90c41894 | 4132 | { |
2247cc5f | 4133 | insn = get_last_nonnote_insn (); |
4134 | last_address += INSN_ADDRESSES (INSN_UID (insn)); | |
4135 | if (INSN_P (insn)) | |
4136 | last_address += insn_default_length (insn); | |
4137 | last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) | |
4138 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
90c41894 | 4139 | } |
2247cc5f | 4140 | |
4141 | /* Finally, update the total number of code bytes output so far. */ | |
4142 | update_total_code_bytes (last_address); | |
daee63dd | 4143 | } |
afd7b680 | 4144 | |
daee63dd | 4145 | void |
5c1d8983 | 4146 | hppa_expand_epilogue (void) |
daee63dd | 4147 | { |
6d36483b | 4148 | rtx tmpreg; |
6bcdc1fb | 4149 | HOST_WIDE_INT offset; |
4150 | HOST_WIDE_INT ret_off = 0; | |
4151 | int i; | |
58361f39 | 4152 | int merge_sp_adjust_with_load = 0; |
daee63dd | 4153 | |
4154 | /* We will use this often. */ | |
440c23df | 4155 | tmpreg = gen_rtx_REG (word_mode, 1); |
daee63dd | 4156 | |
4157 | /* Try to restore RP early to avoid load/use interlocks when | |
4158 | RP gets used in the return (bv) instruction. This appears to still | |
6dc3b0d9 | 4159 | be necessary even when we schedule the prologue and epilogue. */ |
a584fe8a | 4160 | if (regs_ever_live [2] || current_function_calls_eh_return) |
58361f39 | 4161 | { |
4162 | ret_off = TARGET_64BIT ? -16 : -20; | |
4163 | if (frame_pointer_needed) | |
4164 | { | |
6a2c16d6 | 4165 | load_reg (2, ret_off, FRAME_POINTER_REGNUM); |
58361f39 | 4166 | ret_off = 0; |
4167 | } | |
4168 | else | |
4169 | { | |
4170 | /* No frame pointer, and stack is smaller than 8k. */ | |
4171 | if (VAL_14_BITS_P (ret_off - actual_fsize)) | |
4172 | { | |
6a2c16d6 | 4173 | load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM); |
58361f39 | 4174 | ret_off = 0; |
4175 | } | |
4176 | } | |
4177 | } | |
daee63dd | 4178 | |
4179 | /* General register restores. */ | |
87ad11b0 | 4180 | if (frame_pointer_needed) |
4181 | { | |
a584fe8a | 4182 | offset = local_fsize; |
4183 | ||
4184 | /* If the current function calls __builtin_eh_return, then we need | |
4185 | to restore the saved EH data registers. */ | |
4186 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
4187 | { | |
4188 | unsigned int i, regno; | |
4189 | ||
4190 | for (i = 0; ; ++i) | |
4191 | { | |
4192 | regno = EH_RETURN_DATA_REGNO (i); | |
4193 | if (regno == INVALID_REGNUM) | |
4194 | break; | |
4195 | ||
4196 | load_reg (regno, offset, FRAME_POINTER_REGNUM); | |
4197 | offset += UNITS_PER_WORD; | |
4198 | } | |
4199 | } | |
4200 | ||
4201 | for (i = 18; i >= 4; i--) | |
98328a39 | 4202 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 4203 | { |
6a2c16d6 | 4204 | load_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 4205 | offset += UNITS_PER_WORD; |
87ad11b0 | 4206 | } |
87ad11b0 | 4207 | } |
4208 | else | |
4209 | { | |
a584fe8a | 4210 | offset = local_fsize - actual_fsize; |
4211 | ||
4212 | /* If the current function calls __builtin_eh_return, then we need | |
4213 | to restore the saved EH data registers. */ | |
4214 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
4215 | { | |
4216 | unsigned int i, regno; | |
4217 | ||
4218 | for (i = 0; ; ++i) | |
4219 | { | |
4220 | regno = EH_RETURN_DATA_REGNO (i); | |
4221 | if (regno == INVALID_REGNUM) | |
4222 | break; | |
4223 | ||
4224 | /* Only for the first load. | |
4225 | merge_sp_adjust_with_load holds the register load | |
4226 | with which we will merge the sp adjustment. */ | |
4227 | if (merge_sp_adjust_with_load == 0 | |
4228 | && local_fsize == 0 | |
4229 | && VAL_14_BITS_P (-actual_fsize)) | |
4230 | merge_sp_adjust_with_load = regno; | |
4231 | else | |
4232 | load_reg (regno, offset, STACK_POINTER_REGNUM); | |
4233 | offset += UNITS_PER_WORD; | |
4234 | } | |
4235 | } | |
4236 | ||
4237 | for (i = 18; i >= 3; i--) | |
7f7c4869 | 4238 | { |
98328a39 | 4239 | if (regs_ever_live[i] && ! call_used_regs[i]) |
7f7c4869 | 4240 | { |
7f7c4869 | 4241 | /* Only for the first load. |
4242 | merge_sp_adjust_with_load holds the register load | |
4243 | with which we will merge the sp adjustment. */ | |
58361f39 | 4244 | if (merge_sp_adjust_with_load == 0 |
7f7c4869 | 4245 | && local_fsize == 0 |
58361f39 | 4246 | && VAL_14_BITS_P (-actual_fsize)) |
7f7c4869 | 4247 | merge_sp_adjust_with_load = i; |
4248 | else | |
6a2c16d6 | 4249 | load_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 4250 | offset += UNITS_PER_WORD; |
7f7c4869 | 4251 | } |
4252 | } | |
87ad11b0 | 4253 | } |
daee63dd | 4254 | |
87ad11b0 | 4255 | /* Align pointer properly (doubleword boundary). */ |
4256 | offset = (offset + 7) & ~7; | |
4257 | ||
daee63dd | 4258 | /* FP register restores. */ |
87ad11b0 | 4259 | if (save_fregs) |
87ad11b0 | 4260 | { |
daee63dd | 4261 | /* Adjust the register to index off of. */ |
a1ab4fa3 | 4262 | if (frame_pointer_needed) |
a584fe8a | 4263 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); |
a1ab4fa3 | 4264 | else |
a584fe8a | 4265 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); |
daee63dd | 4266 | |
4267 | /* Actually do the restores now. */ | |
bac38c40 | 4268 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
cc858176 | 4269 | if (regs_ever_live[i] |
4270 | || (! TARGET_64BIT && regs_ever_live[i + 1])) | |
4271 | { | |
4272 | rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); | |
4273 | rtx dest = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 4274 | emit_move_insn (dest, src); |
cc858176 | 4275 | } |
87ad11b0 | 4276 | } |
daee63dd | 4277 | |
14660146 | 4278 | /* Emit a blockage insn here to keep these insns from being moved to |
4279 | an earlier spot in the epilogue, or into the main instruction stream. | |
4280 | ||
4281 | This is necessary as we must not cut the stack back before all the | |
4282 | restores are finished. */ | |
4283 | emit_insn (gen_blockage ()); | |
daee63dd | 4284 | |
9840d99d | 4285 | /* Reset stack pointer (and possibly frame pointer). The stack |
42819d4e | 4286 | pointer is initially set to fp + 64 to avoid a race condition. */ |
58361f39 | 4287 | if (frame_pointer_needed) |
87ad11b0 | 4288 | { |
cc858176 | 4289 | rtx delta = GEN_INT (-64); |
a584fe8a | 4290 | |
4291 | set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0); | |
4292 | emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta)); | |
87ad11b0 | 4293 | } |
daee63dd | 4294 | /* If we were deferring a callee register restore, do it now. */ |
58361f39 | 4295 | else if (merge_sp_adjust_with_load) |
4296 | { | |
4297 | rtx delta = GEN_INT (-actual_fsize); | |
cc858176 | 4298 | rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load); |
a584fe8a | 4299 | |
4300 | emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)); | |
58361f39 | 4301 | } |
daee63dd | 4302 | else if (actual_fsize != 0) |
a584fe8a | 4303 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
4304 | - actual_fsize, 0); | |
58361f39 | 4305 | |
4306 | /* If we haven't restored %r2 yet (no frame pointer, and a stack | |
4307 | frame greater than 8k), do so now. */ | |
4308 | if (ret_off != 0) | |
6a2c16d6 | 4309 | load_reg (2, ret_off, STACK_POINTER_REGNUM); |
a584fe8a | 4310 | |
4311 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
4312 | { | |
4313 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
4314 | ||
4315 | emit_insn (gen_blockage ()); | |
4316 | emit_insn (TARGET_64BIT | |
4317 | ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa) | |
4318 | : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa)); | |
4319 | } | |
87ad11b0 | 4320 | } |
4321 | ||
d7e2f694 | 4322 | rtx |
5c1d8983 | 4323 | hppa_pic_save_rtx (void) |
cf3de5bb | 4324 | { |
d7e2f694 | 4325 | return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM); |
df6edefa | 4326 | } |
4327 | ||
4328 | void | |
5c1d8983 | 4329 | hppa_profile_hook (int label_no) |
df6edefa | 4330 | { |
4da37e2f | 4331 | /* We use SImode for the address of the function in both 32 and |
4332 | 64-bit code to avoid having to provide DImode versions of the | |
4333 | lcla2 and load_offset_label_address insn patterns. */ | |
4334 | rtx reg = gen_reg_rtx (SImode); | |
4335 | rtx label_rtx = gen_label_rtx (); | |
a9ac13e4 | 4336 | rtx begin_label_rtx, call_insn; |
4337 | char begin_label_name[16]; | |
df6edefa | 4338 | |
a9ac13e4 | 4339 | ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL, |
b8a21949 | 4340 | label_no); |
4da37e2f | 4341 | begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name)); |
df6edefa | 4342 | |
4343 | if (TARGET_64BIT) | |
4344 | emit_move_insn (arg_pointer_rtx, | |
4345 | gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, | |
4346 | GEN_INT (64))); | |
4347 | ||
df6edefa | 4348 | emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2)); |
4349 | ||
4da37e2f | 4350 | /* The address of the function is loaded into %r25 with a instruction- |
4351 | relative sequence that avoids the use of relocations. The sequence | |
4352 | is split so that the load_offset_label_address instruction can | |
4353 | occupy the delay slot of the call to _mcount. */ | |
4354 | if (TARGET_PA_20) | |
4355 | emit_insn (gen_lcla2 (reg, label_rtx)); | |
4356 | else | |
4357 | emit_insn (gen_lcla1 (reg, label_rtx)); | |
4358 | ||
4359 | emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25), | |
4360 | reg, begin_label_rtx, label_rtx)); | |
4361 | ||
df6edefa | 4362 | #ifndef NO_PROFILE_COUNTERS |
4363 | { | |
4364 | rtx count_label_rtx, addr, r24; | |
a9ac13e4 | 4365 | char count_label_name[16]; |
df6edefa | 4366 | |
a9ac13e4 | 4367 | ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no); |
4368 | count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name)); | |
df6edefa | 4369 | |
831a12d9 | 4370 | addr = force_reg (Pmode, count_label_rtx); |
df6edefa | 4371 | r24 = gen_rtx_REG (Pmode, 24); |
4372 | emit_move_insn (r24, addr); | |
4373 | ||
df6edefa | 4374 | call_insn = |
4da37e2f | 4375 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4376 | gen_rtx_SYMBOL_REF (Pmode, | |
4377 | "_mcount")), | |
4378 | GEN_INT (TARGET_64BIT ? 24 : 12))); | |
df6edefa | 4379 | |
4380 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24); | |
4381 | } | |
4382 | #else | |
4da37e2f | 4383 | |
df6edefa | 4384 | call_insn = |
4da37e2f | 4385 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4386 | gen_rtx_SYMBOL_REF (Pmode, | |
4387 | "_mcount")), | |
4388 | GEN_INT (TARGET_64BIT ? 16 : 8))); | |
4389 | ||
df6edefa | 4390 | #endif |
4391 | ||
4da37e2f | 4392 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25)); |
4393 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26)); | |
4394 | ||
df6edefa | 4395 | /* Indicate the _mcount call cannot throw, nor will it execute a |
4396 | non-local goto. */ | |
4397 | REG_NOTES (call_insn) | |
4398 | = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn)); | |
cf3de5bb | 4399 | } |
4400 | ||
e07ff380 | 4401 | /* Fetch the return address for the frame COUNT steps up from |
4402 | the current frame, after the prologue. FRAMEADDR is the | |
4403 | frame pointer of the COUNT frame. | |
4404 | ||
f49b2e77 | 4405 | We want to ignore any export stub remnants here. To handle this, |
4406 | we examine the code at the return address, and if it is an export | |
4407 | stub, we return a memory rtx for the stub return address stored | |
4408 | at frame-24. | |
a6c6fd6c | 4409 | |
4410 | The value returned is used in two different ways: | |
4411 | ||
4412 | 1. To find a function's caller. | |
4413 | ||
4414 | 2. To change the return address for a function. | |
4415 | ||
4416 | This function handles most instances of case 1; however, it will | |
4417 | fail if there are two levels of stubs to execute on the return | |
4418 | path. The only way I believe that can happen is if the return value | |
4419 | needs a parameter relocation, which never happens for C code. | |
4420 | ||
4421 | This function handles most instances of case 2; however, it will | |
4422 | fail if we did not originally have stub code on the return path | |
f49b2e77 | 4423 | but will need stub code on the new return path. This can happen if |
a6c6fd6c | 4424 | the caller & callee are both in the main program, but the new |
f49b2e77 | 4425 | return location is in a shared library. */ |
e07ff380 | 4426 | |
4427 | rtx | |
5c1d8983 | 4428 | return_addr_rtx (int count, rtx frameaddr) |
e07ff380 | 4429 | { |
4430 | rtx label; | |
f49b2e77 | 4431 | rtx rp; |
e07ff380 | 4432 | rtx saved_rp; |
4433 | rtx ins; | |
4434 | ||
f49b2e77 | 4435 | if (count != 0) |
4436 | return NULL_RTX; | |
b29897dd | 4437 | |
f49b2e77 | 4438 | rp = get_hard_reg_initial_val (Pmode, 2); |
e07ff380 | 4439 | |
f49b2e77 | 4440 | if (TARGET_64BIT || TARGET_NO_SPACE_REGS) |
4441 | return rp; | |
e07ff380 | 4442 | |
b29897dd | 4443 | saved_rp = gen_reg_rtx (Pmode); |
f49b2e77 | 4444 | emit_move_insn (saved_rp, rp); |
e07ff380 | 4445 | |
4446 | /* Get pointer to the instruction stream. We have to mask out the | |
4447 | privilege level from the two low order bits of the return address | |
4448 | pointer here so that ins will point to the start of the first | |
4449 | instruction that would have been executed if we returned. */ | |
f49b2e77 | 4450 | ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR)); |
e07ff380 | 4451 | label = gen_label_rtx (); |
4452 | ||
4453 | /* Check the instruction stream at the normal return address for the | |
4454 | export stub: | |
4455 | ||
4456 | 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp | |
4457 | 0x004010a1 | stub+12: ldsid (sr0,rp),r1 | |
4458 | 0x00011820 | stub+16: mtsp r1,sr0 | |
4459 | 0xe0400002 | stub+20: be,n 0(sr0,rp) | |
4460 | ||
4461 | If it is an export stub, than our return address is really in | |
4462 | -24[frameaddr]. */ | |
4463 | ||
e00b80b2 | 4464 | emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE, |
4465 | NULL_RTX, SImode, 1); | |
e07ff380 | 4466 | emit_jump_insn (gen_bne (label)); |
4467 | ||
ad851752 | 4468 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)), |
e00b80b2 | 4469 | GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4470 | emit_jump_insn (gen_bne (label)); |
4471 | ||
ad851752 | 4472 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)), |
e00b80b2 | 4473 | GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4474 | emit_jump_insn (gen_bne (label)); |
4475 | ||
ad851752 | 4476 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)), |
e00b80b2 | 4477 | GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4478 | |
f49b2e77 | 4479 | /* If there is no export stub then just use the value saved from |
4480 | the return pointer register. */ | |
e07ff380 | 4481 | |
4482 | emit_jump_insn (gen_bne (label)); | |
4483 | ||
f49b2e77 | 4484 | /* Here we know that our return address points to an export |
e07ff380 | 4485 | stub. We don't want to return the address of the export stub, |
f49b2e77 | 4486 | but rather the return address of the export stub. That return |
4487 | address is stored at -24[frameaddr]. */ | |
e07ff380 | 4488 | |
f49b2e77 | 4489 | emit_move_insn (saved_rp, |
4490 | gen_rtx_MEM (Pmode, | |
4491 | memory_address (Pmode, | |
4492 | plus_constant (frameaddr, | |
4493 | -24)))); | |
e07ff380 | 4494 | |
4495 | emit_label (label); | |
f49b2e77 | 4496 | return saved_rp; |
e07ff380 | 4497 | } |
4498 | ||
757d4970 | 4499 | /* This is only valid once reload has completed because it depends on |
4500 | knowing exactly how much (if any) frame there is and... | |
4501 | ||
4502 | It's only valid if there is no frame marker to de-allocate and... | |
4503 | ||
4504 | It's only valid if %r2 hasn't been saved into the caller's frame | |
4505 | (we're not profiling and %r2 isn't live anywhere). */ | |
4506 | int | |
5c1d8983 | 4507 | hppa_can_use_return_insn_p (void) |
757d4970 | 4508 | { |
4509 | return (reload_completed | |
4510 | && (compute_frame_size (get_frame_size (), 0) ? 0 : 1) | |
757d4970 | 4511 | && ! regs_ever_live[2] |
4512 | && ! frame_pointer_needed); | |
4513 | } | |
4514 | ||
87ad11b0 | 4515 | void |
5c1d8983 | 4516 | emit_bcond_fp (enum rtx_code code, rtx operand0) |
87ad11b0 | 4517 | { |
ad851752 | 4518 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, |
4519 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
4520 | gen_rtx_fmt_ee (code, | |
4521 | VOIDmode, | |
4522 | gen_rtx_REG (CCFPmode, 0), | |
4523 | const0_rtx), | |
4524 | gen_rtx_LABEL_REF (VOIDmode, operand0), | |
4525 | pc_rtx))); | |
87ad11b0 | 4526 | |
4527 | } | |
4528 | ||
4529 | rtx | |
5c1d8983 | 4530 | gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1) |
87ad11b0 | 4531 | { |
ad851752 | 4532 | return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0), |
4533 | gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1)); | |
87ad11b0 | 4534 | } |
4535 | ||
8b49b3c7 | 4536 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
4537 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4538 | ||
747af5e7 | 4539 | static int |
5c1d8983 | 4540 | pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
8b49b3c7 | 4541 | { |
43048d2c | 4542 | enum attr_type attr_type; |
4543 | ||
cde3e16c | 4544 | /* Don't adjust costs for a pa8000 chip, also do not adjust any |
4545 | true dependencies as they are described with bypasses now. */ | |
4546 | if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0) | |
342aabd9 | 4547 | return cost; |
4548 | ||
d402da4b | 4549 | if (! recog_memoized (insn)) |
4550 | return 0; | |
8b49b3c7 | 4551 | |
43048d2c | 4552 | attr_type = get_attr_type (insn); |
4553 | ||
cde3e16c | 4554 | if (REG_NOTE_KIND (link) == REG_DEP_ANTI) |
8b49b3c7 | 4555 | { |
4556 | /* Anti dependency; DEP_INSN reads a register that INSN writes some | |
4557 | cycles later. */ | |
4558 | ||
43048d2c | 4559 | if (attr_type == TYPE_FPLOAD) |
8b49b3c7 | 4560 | { |
d402da4b | 4561 | rtx pat = PATTERN (insn); |
4562 | rtx dep_pat = PATTERN (dep_insn); | |
4563 | if (GET_CODE (pat) == PARALLEL) | |
4564 | { | |
4565 | /* This happens for the fldXs,mb patterns. */ | |
4566 | pat = XVECEXP (pat, 0, 0); | |
4567 | } | |
4568 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
8b49b3c7 | 4569 | /* If this happens, we have to extend this to schedule |
d402da4b | 4570 | optimally. Return 0 for now. */ |
4571 | return 0; | |
8b49b3c7 | 4572 | |
d402da4b | 4573 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) |
8b49b3c7 | 4574 | { |
d402da4b | 4575 | if (! recog_memoized (dep_insn)) |
4576 | return 0; | |
8b49b3c7 | 4577 | switch (get_attr_type (dep_insn)) |
4578 | { | |
4579 | case TYPE_FPALU: | |
134b4858 | 4580 | case TYPE_FPMULSGL: |
4581 | case TYPE_FPMULDBL: | |
8b49b3c7 | 4582 | case TYPE_FPDIVSGL: |
4583 | case TYPE_FPDIVDBL: | |
4584 | case TYPE_FPSQRTSGL: | |
4585 | case TYPE_FPSQRTDBL: | |
d402da4b | 4586 | /* A fpload can't be issued until one cycle before a |
01cc3b75 | 4587 | preceding arithmetic operation has finished if |
d402da4b | 4588 | the target of the fpload is any of the sources |
4589 | (or destination) of the arithmetic operation. */ | |
cde3e16c | 4590 | return insn_default_latency (dep_insn) - 1; |
134b4858 | 4591 | |
4592 | default: | |
4593 | return 0; | |
4594 | } | |
4595 | } | |
4596 | } | |
43048d2c | 4597 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4598 | { |
4599 | rtx pat = PATTERN (insn); | |
4600 | rtx dep_pat = PATTERN (dep_insn); | |
4601 | if (GET_CODE (pat) == PARALLEL) | |
4602 | { | |
4603 | /* This happens for the fldXs,mb patterns. */ | |
4604 | pat = XVECEXP (pat, 0, 0); | |
4605 | } | |
4606 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4607 | /* If this happens, we have to extend this to schedule | |
4608 | optimally. Return 0 for now. */ | |
4609 | return 0; | |
4610 | ||
4611 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) | |
4612 | { | |
4613 | if (! recog_memoized (dep_insn)) | |
4614 | return 0; | |
4615 | switch (get_attr_type (dep_insn)) | |
4616 | { | |
4617 | case TYPE_FPDIVSGL: | |
4618 | case TYPE_FPDIVDBL: | |
4619 | case TYPE_FPSQRTSGL: | |
4620 | case TYPE_FPSQRTDBL: | |
4621 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4622 | preceding divide or sqrt operation has finished if |
134b4858 | 4623 | the target of the ALU flop is any of the sources |
4624 | (or destination) of the divide or sqrt operation. */ | |
cde3e16c | 4625 | return insn_default_latency (dep_insn) - 2; |
8b49b3c7 | 4626 | |
4627 | default: | |
4628 | return 0; | |
4629 | } | |
4630 | } | |
4631 | } | |
4632 | ||
4633 | /* For other anti dependencies, the cost is 0. */ | |
4634 | return 0; | |
4635 | } | |
134b4858 | 4636 | else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT) |
4637 | { | |
4638 | /* Output dependency; DEP_INSN writes a register that INSN writes some | |
4639 | cycles later. */ | |
43048d2c | 4640 | if (attr_type == TYPE_FPLOAD) |
134b4858 | 4641 | { |
4642 | rtx pat = PATTERN (insn); | |
4643 | rtx dep_pat = PATTERN (dep_insn); | |
4644 | if (GET_CODE (pat) == PARALLEL) | |
4645 | { | |
4646 | /* This happens for the fldXs,mb patterns. */ | |
4647 | pat = XVECEXP (pat, 0, 0); | |
4648 | } | |
4649 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4650 | /* If this happens, we have to extend this to schedule | |
4651 | optimally. Return 0 for now. */ | |
4652 | return 0; | |
4653 | ||
4654 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4655 | { | |
4656 | if (! recog_memoized (dep_insn)) | |
4657 | return 0; | |
4658 | switch (get_attr_type (dep_insn)) | |
4659 | { | |
4660 | case TYPE_FPALU: | |
4661 | case TYPE_FPMULSGL: | |
4662 | case TYPE_FPMULDBL: | |
4663 | case TYPE_FPDIVSGL: | |
4664 | case TYPE_FPDIVDBL: | |
4665 | case TYPE_FPSQRTSGL: | |
4666 | case TYPE_FPSQRTDBL: | |
4667 | /* A fpload can't be issued until one cycle before a | |
01cc3b75 | 4668 | preceding arithmetic operation has finished if |
134b4858 | 4669 | the target of the fpload is the destination of the |
bea4bad2 | 4670 | arithmetic operation. |
4671 | ||
4672 | Exception: For PA7100LC, PA7200 and PA7300, the cost | |
4673 | is 3 cycles, unless they bundle together. We also | |
4674 | pay the penalty if the second insn is a fpload. */ | |
cde3e16c | 4675 | return insn_default_latency (dep_insn) - 1; |
8b49b3c7 | 4676 | |
134b4858 | 4677 | default: |
4678 | return 0; | |
4679 | } | |
4680 | } | |
4681 | } | |
43048d2c | 4682 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4683 | { |
4684 | rtx pat = PATTERN (insn); | |
4685 | rtx dep_pat = PATTERN (dep_insn); | |
4686 | if (GET_CODE (pat) == PARALLEL) | |
4687 | { | |
4688 | /* This happens for the fldXs,mb patterns. */ | |
4689 | pat = XVECEXP (pat, 0, 0); | |
4690 | } | |
4691 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4692 | /* If this happens, we have to extend this to schedule | |
4693 | optimally. Return 0 for now. */ | |
4694 | return 0; | |
4695 | ||
4696 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4697 | { | |
4698 | if (! recog_memoized (dep_insn)) | |
4699 | return 0; | |
4700 | switch (get_attr_type (dep_insn)) | |
4701 | { | |
4702 | case TYPE_FPDIVSGL: | |
4703 | case TYPE_FPDIVDBL: | |
4704 | case TYPE_FPSQRTSGL: | |
4705 | case TYPE_FPSQRTDBL: | |
4706 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4707 | preceding divide or sqrt operation has finished if |
134b4858 | 4708 | the target of the ALU flop is also the target of |
3398e91d | 4709 | the divide or sqrt operation. */ |
cde3e16c | 4710 | return insn_default_latency (dep_insn) - 2; |
134b4858 | 4711 | |
4712 | default: | |
4713 | return 0; | |
4714 | } | |
4715 | } | |
4716 | } | |
4717 | ||
4718 | /* For other output dependencies, the cost is 0. */ | |
4719 | return 0; | |
4720 | } | |
4721 | else | |
4722 | abort (); | |
8b49b3c7 | 4723 | } |
87ad11b0 | 4724 | |
747af5e7 | 4725 | /* Adjust scheduling priorities. We use this to try and keep addil |
4726 | and the next use of %r1 close together. */ | |
4727 | static int | |
5c1d8983 | 4728 | pa_adjust_priority (rtx insn, int priority) |
747af5e7 | 4729 | { |
4730 | rtx set = single_set (insn); | |
4731 | rtx src, dest; | |
4732 | if (set) | |
4733 | { | |
4734 | src = SET_SRC (set); | |
4735 | dest = SET_DEST (set); | |
4736 | if (GET_CODE (src) == LO_SUM | |
4737 | && symbolic_operand (XEXP (src, 1), VOIDmode) | |
4738 | && ! read_only_operand (XEXP (src, 1), VOIDmode)) | |
4739 | priority >>= 3; | |
4740 | ||
4741 | else if (GET_CODE (src) == MEM | |
4742 | && GET_CODE (XEXP (src, 0)) == LO_SUM | |
4743 | && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode) | |
4744 | && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode)) | |
4745 | priority >>= 1; | |
4746 | ||
4747 | else if (GET_CODE (dest) == MEM | |
4748 | && GET_CODE (XEXP (dest, 0)) == LO_SUM | |
4749 | && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode) | |
4750 | && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)) | |
4751 | priority >>= 3; | |
4752 | } | |
4753 | return priority; | |
4754 | } | |
4755 | ||
4756 | /* The 700 can only issue a single insn at a time. | |
4757 | The 7XXX processors can issue two insns at a time. | |
4758 | The 8000 can issue 4 insns at a time. */ | |
4759 | static int | |
5c1d8983 | 4760 | pa_issue_rate (void) |
747af5e7 | 4761 | { |
4762 | switch (pa_cpu) | |
4763 | { | |
4764 | case PROCESSOR_700: return 1; | |
4765 | case PROCESSOR_7100: return 2; | |
4766 | case PROCESSOR_7100LC: return 2; | |
4767 | case PROCESSOR_7200: return 2; | |
bea4bad2 | 4768 | case PROCESSOR_7300: return 2; |
747af5e7 | 4769 | case PROCESSOR_8000: return 4; |
4770 | ||
4771 | default: | |
4772 | abort (); | |
4773 | } | |
4774 | } | |
4775 | ||
4776 | ||
4777 | ||
58e17b0b | 4778 | /* Return any length adjustment needed by INSN which already has its length |
6d36483b | 4779 | computed as LENGTH. Return zero if no adjustment is necessary. |
58e17b0b | 4780 | |
5fbd5940 | 4781 | For the PA: function calls, millicode calls, and backwards short |
6d36483b | 4782 | conditional branches with unfilled delay slots need an adjustment by +1 |
5fbd5940 | 4783 | (to account for the NOP which will be inserted into the instruction stream). |
58e17b0b | 4784 | |
4785 | Also compute the length of an inline block move here as it is too | |
5fbd5940 | 4786 | complicated to express as a length attribute in pa.md. */ |
58e17b0b | 4787 | int |
5c1d8983 | 4788 | pa_adjust_insn_length (rtx insn, int length) |
58e17b0b | 4789 | { |
4790 | rtx pat = PATTERN (insn); | |
4791 | ||
faf3f8c1 | 4792 | /* Jumps inside switch tables which have unfilled delay slots need |
4793 | adjustment. */ | |
4794 | if (GET_CODE (insn) == JUMP_INSN | |
b932f66c | 4795 | && GET_CODE (pat) == PARALLEL |
4796 | && get_attr_type (insn) == TYPE_BTABLE_BRANCH) | |
3b1e673e | 4797 | return 4; |
58e17b0b | 4798 | /* Millicode insn with an unfilled delay slot. */ |
4799 | else if (GET_CODE (insn) == INSN | |
4800 | && GET_CODE (pat) != SEQUENCE | |
4801 | && GET_CODE (pat) != USE | |
4802 | && GET_CODE (pat) != CLOBBER | |
4803 | && get_attr_type (insn) == TYPE_MILLI) | |
5a1231ef | 4804 | return 4; |
58e17b0b | 4805 | /* Block move pattern. */ |
4806 | else if (GET_CODE (insn) == INSN | |
4807 | && GET_CODE (pat) == PARALLEL | |
f2ebcf32 | 4808 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET |
58e17b0b | 4809 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM |
4810 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM | |
4811 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode | |
4812 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode) | |
008c057d | 4813 | return compute_movmem_length (insn) - 4; |
a7e1bb24 | 4814 | /* Block clear pattern. */ |
4815 | else if (GET_CODE (insn) == INSN | |
4816 | && GET_CODE (pat) == PARALLEL | |
4817 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET | |
4818 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM | |
4819 | && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx | |
4820 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode) | |
008c057d | 4821 | return compute_clrmem_length (insn) - 4; |
58e17b0b | 4822 | /* Conditional branch with an unfilled delay slot. */ |
5fbd5940 | 4823 | else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn)) |
4824 | { | |
4825 | /* Adjust a short backwards conditional with an unfilled delay slot. */ | |
4826 | if (GET_CODE (pat) == SET | |
5a1231ef | 4827 | && length == 4 |
5fbd5940 | 4828 | && ! forward_branch_p (insn)) |
5a1231ef | 4829 | return 4; |
546a40bd | 4830 | else if (GET_CODE (pat) == PARALLEL |
4831 | && get_attr_type (insn) == TYPE_PARALLEL_BRANCH | |
4832 | && length == 4) | |
4833 | return 4; | |
5fbd5940 | 4834 | /* Adjust dbra insn with short backwards conditional branch with |
6d36483b | 4835 | unfilled delay slot -- only for case where counter is in a |
6dc3b0d9 | 4836 | general register register. */ |
5fbd5940 | 4837 | else if (GET_CODE (pat) == PARALLEL |
4838 | && GET_CODE (XVECEXP (pat, 0, 1)) == SET | |
4839 | && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG | |
6d36483b | 4840 | && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0)) |
5a1231ef | 4841 | && length == 4 |
5fbd5940 | 4842 | && ! forward_branch_p (insn)) |
5a1231ef | 4843 | return 4; |
5fbd5940 | 4844 | else |
4845 | return 0; | |
4846 | } | |
546a40bd | 4847 | return 0; |
58e17b0b | 4848 | } |
4849 | ||
87ad11b0 | 4850 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
4851 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
4852 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
4853 | ||
4854 | void | |
5c1d8983 | 4855 | print_operand (FILE *file, rtx x, int code) |
87ad11b0 | 4856 | { |
4857 | switch (code) | |
4858 | { | |
4859 | case '#': | |
4860 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
4861 | if (dbr_sequence_length () == 0) | |
4862 | fputs ("\n\tnop", file); | |
4863 | return; | |
4864 | case '*': | |
87fcb603 | 4865 | /* Output a nullification completer if there's nothing for the */ |
6d36483b | 4866 | /* delay slot or nullification is requested. */ |
87ad11b0 | 4867 | if (dbr_sequence_length () == 0 || |
4868 | (final_sequence && | |
4869 | INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))) | |
4870 | fputs (",n", file); | |
4871 | return; | |
4872 | case 'R': | |
4873 | /* Print out the second register name of a register pair. | |
4874 | I.e., R (6) => 7. */ | |
ea52c577 | 4875 | fputs (reg_names[REGNO (x) + 1], file); |
87ad11b0 | 4876 | return; |
4877 | case 'r': | |
6dc3b0d9 | 4878 | /* A register or zero. */ |
891b55b4 | 4879 | if (x == const0_rtx |
4880 | || (x == CONST0_RTX (DFmode)) | |
4881 | || (x == CONST0_RTX (SFmode))) | |
87ad11b0 | 4882 | { |
c6ae275c | 4883 | fputs ("%r0", file); |
4884 | return; | |
4885 | } | |
4886 | else | |
4887 | break; | |
4888 | case 'f': | |
6dc3b0d9 | 4889 | /* A register or zero (floating point). */ |
c6ae275c | 4890 | if (x == const0_rtx |
4891 | || (x == CONST0_RTX (DFmode)) | |
4892 | || (x == CONST0_RTX (SFmode))) | |
4893 | { | |
4894 | fputs ("%fr0", file); | |
87ad11b0 | 4895 | return; |
4896 | } | |
4897 | else | |
4898 | break; | |
2d14b1f0 | 4899 | case 'A': |
4900 | { | |
4901 | rtx xoperands[2]; | |
4902 | ||
4903 | xoperands[0] = XEXP (XEXP (x, 0), 0); | |
4904 | xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0); | |
4905 | output_global_address (file, xoperands[1], 0); | |
4906 | fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]); | |
4907 | return; | |
4908 | } | |
4909 | ||
c8975385 | 4910 | case 'C': /* Plain (C)ondition */ |
87ad11b0 | 4911 | case 'X': |
4912 | switch (GET_CODE (x)) | |
6d36483b | 4913 | { |
87ad11b0 | 4914 | case EQ: |
9c0ac0fd | 4915 | fputs ("=", file); break; |
87ad11b0 | 4916 | case NE: |
9c0ac0fd | 4917 | fputs ("<>", file); break; |
87ad11b0 | 4918 | case GT: |
9c0ac0fd | 4919 | fputs (">", file); break; |
87ad11b0 | 4920 | case GE: |
9c0ac0fd | 4921 | fputs (">=", file); break; |
87ad11b0 | 4922 | case GEU: |
9c0ac0fd | 4923 | fputs (">>=", file); break; |
87ad11b0 | 4924 | case GTU: |
9c0ac0fd | 4925 | fputs (">>", file); break; |
87ad11b0 | 4926 | case LT: |
9c0ac0fd | 4927 | fputs ("<", file); break; |
87ad11b0 | 4928 | case LE: |
9c0ac0fd | 4929 | fputs ("<=", file); break; |
87ad11b0 | 4930 | case LEU: |
9c0ac0fd | 4931 | fputs ("<<=", file); break; |
87ad11b0 | 4932 | case LTU: |
9c0ac0fd | 4933 | fputs ("<<", file); break; |
87ad11b0 | 4934 | default: |
87ad11b0 | 4935 | abort (); |
4936 | } | |
4937 | return; | |
c8975385 | 4938 | case 'N': /* Condition, (N)egated */ |
87ad11b0 | 4939 | switch (GET_CODE (x)) |
4940 | { | |
4941 | case EQ: | |
9c0ac0fd | 4942 | fputs ("<>", file); break; |
87ad11b0 | 4943 | case NE: |
9c0ac0fd | 4944 | fputs ("=", file); break; |
87ad11b0 | 4945 | case GT: |
9c0ac0fd | 4946 | fputs ("<=", file); break; |
87ad11b0 | 4947 | case GE: |
9c0ac0fd | 4948 | fputs ("<", file); break; |
87ad11b0 | 4949 | case GEU: |
9c0ac0fd | 4950 | fputs ("<<", file); break; |
87ad11b0 | 4951 | case GTU: |
9c0ac0fd | 4952 | fputs ("<<=", file); break; |
87ad11b0 | 4953 | case LT: |
9c0ac0fd | 4954 | fputs (">=", file); break; |
87ad11b0 | 4955 | case LE: |
9c0ac0fd | 4956 | fputs (">", file); break; |
87ad11b0 | 4957 | case LEU: |
9c0ac0fd | 4958 | fputs (">>", file); break; |
87ad11b0 | 4959 | case LTU: |
9c0ac0fd | 4960 | fputs (">>=", file); break; |
87ad11b0 | 4961 | default: |
87ad11b0 | 4962 | abort (); |
4963 | } | |
4964 | return; | |
ea52c577 | 4965 | /* For floating point comparisons. Note that the output |
4966 | predicates are the complement of the desired mode. */ | |
61230bc9 | 4967 | case 'Y': |
4968 | switch (GET_CODE (x)) | |
4969 | { | |
4970 | case EQ: | |
9c0ac0fd | 4971 | fputs ("!=", file); break; |
61230bc9 | 4972 | case NE: |
9c0ac0fd | 4973 | fputs ("=", file); break; |
61230bc9 | 4974 | case GT: |
32509e56 | 4975 | fputs ("!>", file); break; |
61230bc9 | 4976 | case GE: |
32509e56 | 4977 | fputs ("!>=", file); break; |
61230bc9 | 4978 | case LT: |
32509e56 | 4979 | fputs ("!<", file); break; |
61230bc9 | 4980 | case LE: |
32509e56 | 4981 | fputs ("!<=", file); break; |
4982 | case LTGT: | |
4983 | fputs ("!<>", file); break; | |
4984 | case UNLE: | |
85837adc | 4985 | fputs (">", file); break; |
32509e56 | 4986 | case UNLT: |
4987 | fputs (">=", file); break; | |
4988 | case UNGE: | |
4989 | fputs ("<", file); break; | |
4990 | case UNGT: | |
4991 | fputs ("<=", file); break; | |
4992 | case UNEQ: | |
4993 | fputs ("<>", file); break; | |
4994 | case UNORDERED: | |
4995 | fputs ("<=>", file); break; | |
4996 | case ORDERED: | |
4997 | fputs ("!<=>", file); break; | |
61230bc9 | 4998 | default: |
61230bc9 | 4999 | abort (); |
5000 | } | |
5001 | return; | |
c8975385 | 5002 | case 'S': /* Condition, operands are (S)wapped. */ |
5003 | switch (GET_CODE (x)) | |
5004 | { | |
5005 | case EQ: | |
9c0ac0fd | 5006 | fputs ("=", file); break; |
c8975385 | 5007 | case NE: |
9c0ac0fd | 5008 | fputs ("<>", file); break; |
c8975385 | 5009 | case GT: |
9c0ac0fd | 5010 | fputs ("<", file); break; |
c8975385 | 5011 | case GE: |
9c0ac0fd | 5012 | fputs ("<=", file); break; |
c8975385 | 5013 | case GEU: |
9c0ac0fd | 5014 | fputs ("<<=", file); break; |
c8975385 | 5015 | case GTU: |
9c0ac0fd | 5016 | fputs ("<<", file); break; |
c8975385 | 5017 | case LT: |
9c0ac0fd | 5018 | fputs (">", file); break; |
c8975385 | 5019 | case LE: |
9c0ac0fd | 5020 | fputs (">=", file); break; |
c8975385 | 5021 | case LEU: |
9c0ac0fd | 5022 | fputs (">>=", file); break; |
c8975385 | 5023 | case LTU: |
9c0ac0fd | 5024 | fputs (">>", file); break; |
c8975385 | 5025 | default: |
c8975385 | 5026 | abort (); |
6d36483b | 5027 | } |
c8975385 | 5028 | return; |
5029 | case 'B': /* Condition, (B)oth swapped and negate. */ | |
5030 | switch (GET_CODE (x)) | |
5031 | { | |
5032 | case EQ: | |
9c0ac0fd | 5033 | fputs ("<>", file); break; |
c8975385 | 5034 | case NE: |
9c0ac0fd | 5035 | fputs ("=", file); break; |
c8975385 | 5036 | case GT: |
9c0ac0fd | 5037 | fputs (">=", file); break; |
c8975385 | 5038 | case GE: |
9c0ac0fd | 5039 | fputs (">", file); break; |
c8975385 | 5040 | case GEU: |
9c0ac0fd | 5041 | fputs (">>", file); break; |
c8975385 | 5042 | case GTU: |
9c0ac0fd | 5043 | fputs (">>=", file); break; |
c8975385 | 5044 | case LT: |
9c0ac0fd | 5045 | fputs ("<=", file); break; |
c8975385 | 5046 | case LE: |
9c0ac0fd | 5047 | fputs ("<", file); break; |
c8975385 | 5048 | case LEU: |
9c0ac0fd | 5049 | fputs ("<<", file); break; |
c8975385 | 5050 | case LTU: |
9c0ac0fd | 5051 | fputs ("<<=", file); break; |
c8975385 | 5052 | default: |
c8975385 | 5053 | abort (); |
6d36483b | 5054 | } |
c8975385 | 5055 | return; |
5056 | case 'k': | |
5057 | if (GET_CODE (x) == CONST_INT) | |
5058 | { | |
96b529f2 | 5059 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x)); |
c8975385 | 5060 | return; |
5061 | } | |
ea52c577 | 5062 | abort (); |
5e3c5739 | 5063 | case 'Q': |
5064 | if (GET_CODE (x) == CONST_INT) | |
5065 | { | |
96b529f2 | 5066 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63)); |
5e3c5739 | 5067 | return; |
5068 | } | |
ea52c577 | 5069 | abort (); |
e5965947 | 5070 | case 'L': |
5071 | if (GET_CODE (x) == CONST_INT) | |
5072 | { | |
96b529f2 | 5073 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31)); |
e5965947 | 5074 | return; |
5075 | } | |
ea52c577 | 5076 | abort (); |
3a16146d | 5077 | case 'O': |
5078 | if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0) | |
5079 | { | |
5080 | fprintf (file, "%d", exact_log2 (INTVAL (x))); | |
5081 | return; | |
5082 | } | |
ea52c577 | 5083 | abort (); |
5e3c5739 | 5084 | case 'p': |
5085 | if (GET_CODE (x) == CONST_INT) | |
5086 | { | |
96b529f2 | 5087 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63)); |
5e3c5739 | 5088 | return; |
5089 | } | |
ea52c577 | 5090 | abort (); |
e5965947 | 5091 | case 'P': |
5092 | if (GET_CODE (x) == CONST_INT) | |
5093 | { | |
96b529f2 | 5094 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31)); |
e5965947 | 5095 | return; |
5096 | } | |
ea52c577 | 5097 | abort (); |
c8975385 | 5098 | case 'I': |
5099 | if (GET_CODE (x) == CONST_INT) | |
5100 | fputs ("i", file); | |
5101 | return; | |
87ad11b0 | 5102 | case 'M': |
27ef382d | 5103 | case 'F': |
87ad11b0 | 5104 | switch (GET_CODE (XEXP (x, 0))) |
5105 | { | |
5106 | case PRE_DEC: | |
5107 | case PRE_INC: | |
e4065f95 | 5108 | if (ASSEMBLER_DIALECT == 0) |
5109 | fputs ("s,mb", file); | |
5110 | else | |
5111 | fputs (",mb", file); | |
87ad11b0 | 5112 | break; |
5113 | case POST_DEC: | |
5114 | case POST_INC: | |
e4065f95 | 5115 | if (ASSEMBLER_DIALECT == 0) |
5116 | fputs ("s,ma", file); | |
5117 | else | |
5118 | fputs (",ma", file); | |
87ad11b0 | 5119 | break; |
27ef382d | 5120 | case PLUS: |
dbd3d89d | 5121 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5122 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5123 | { | |
5124 | if (ASSEMBLER_DIALECT == 0) | |
5125 | fputs ("x", file); | |
5126 | } | |
5127 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
5128 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) | |
e4065f95 | 5129 | { |
5130 | if (ASSEMBLER_DIALECT == 0) | |
5131 | fputs ("x,s", file); | |
5132 | else | |
5133 | fputs (",s", file); | |
5134 | } | |
5135 | else if (code == 'F' && ASSEMBLER_DIALECT == 0) | |
27ef382d | 5136 | fputs ("s", file); |
87ad11b0 | 5137 | break; |
5138 | default: | |
e4065f95 | 5139 | if (code == 'F' && ASSEMBLER_DIALECT == 0) |
27ef382d | 5140 | fputs ("s", file); |
87ad11b0 | 5141 | break; |
5142 | } | |
5143 | return; | |
5144 | case 'G': | |
f9333726 | 5145 | output_global_address (file, x, 0); |
5146 | return; | |
5147 | case 'H': | |
5148 | output_global_address (file, x, 1); | |
87ad11b0 | 5149 | return; |
5150 | case 0: /* Don't do anything special */ | |
5151 | break; | |
42faba01 | 5152 | case 'Z': |
5153 | { | |
5154 | unsigned op[3]; | |
fb22aedc | 5155 | compute_zdepwi_operands (INTVAL (x), op); |
42faba01 | 5156 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); |
5157 | return; | |
5158 | } | |
5e3c5739 | 5159 | case 'z': |
5160 | { | |
5161 | unsigned op[3]; | |
5162 | compute_zdepdi_operands (INTVAL (x), op); | |
5163 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); | |
5164 | return; | |
5165 | } | |
c9cc98e1 | 5166 | case 'c': |
5167 | /* We can get here from a .vtable_inherit due to our | |
5168 | CONSTANT_ADDRESS_P rejecting perfectly good constant | |
5169 | addresses. */ | |
5170 | break; | |
87ad11b0 | 5171 | default: |
5172 | abort (); | |
5173 | } | |
5174 | if (GET_CODE (x) == REG) | |
df0651dc | 5175 | { |
35661368 | 5176 | fputs (reg_names [REGNO (x)], file); |
5e3c5739 | 5177 | if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4) |
5178 | { | |
5179 | fputs ("R", file); | |
5180 | return; | |
5181 | } | |
5182 | if (FP_REG_P (x) | |
5183 | && GET_MODE_SIZE (GET_MODE (x)) <= 4 | |
5184 | && (REGNO (x) & 1) == 0) | |
35661368 | 5185 | fputs ("L", file); |
df0651dc | 5186 | } |
87ad11b0 | 5187 | else if (GET_CODE (x) == MEM) |
5188 | { | |
5189 | int size = GET_MODE_SIZE (GET_MODE (x)); | |
f7dff90d | 5190 | rtx base = NULL_RTX; |
87ad11b0 | 5191 | switch (GET_CODE (XEXP (x, 0))) |
5192 | { | |
5193 | case PRE_DEC: | |
5194 | case POST_DEC: | |
5e3c5739 | 5195 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 5196 | fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5197 | break; |
5198 | case PRE_INC: | |
5199 | case POST_INC: | |
5e3c5739 | 5200 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 5201 | fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5202 | break; |
dbd3d89d | 5203 | case PLUS: |
5204 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT) | |
34940871 | 5205 | fprintf (file, "%s(%s)", |
27ef382d | 5206 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))], |
5207 | reg_names [REGNO (XEXP (XEXP (x, 0), 1))]); | |
dbd3d89d | 5208 | else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) |
34940871 | 5209 | fprintf (file, "%s(%s)", |
27ef382d | 5210 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))], |
5211 | reg_names [REGNO (XEXP (XEXP (x, 0), 0))]); | |
dbd3d89d | 5212 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5213 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5214 | { | |
5215 | /* Because the REG_POINTER flag can get lost during reload, | |
5216 | GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the | |
5217 | index and base registers in the combined move patterns. */ | |
5218 | rtx base = XEXP (XEXP (x, 0), 1); | |
5219 | rtx index = XEXP (XEXP (x, 0), 0); | |
5220 | ||
5221 | fprintf (file, "%s(%s)", | |
5222 | reg_names [REGNO (index)], reg_names [REGNO (base)]); | |
5223 | } | |
27ef382d | 5224 | else |
5225 | output_address (XEXP (x, 0)); | |
87ad11b0 | 5226 | break; |
dbd3d89d | 5227 | default: |
5228 | output_address (XEXP (x, 0)); | |
5229 | break; | |
87ad11b0 | 5230 | } |
5231 | } | |
87ad11b0 | 5232 | else |
5233 | output_addr_const (file, x); | |
5234 | } | |
5235 | ||
6dc3b0d9 | 5236 | /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */ |
87ad11b0 | 5237 | |
5238 | void | |
5c1d8983 | 5239 | output_global_address (FILE *file, rtx x, int round_constant) |
87ad11b0 | 5240 | { |
2ee034bc | 5241 | |
5242 | /* Imagine (high (const (plus ...))). */ | |
5243 | if (GET_CODE (x) == HIGH) | |
5244 | x = XEXP (x, 0); | |
5245 | ||
611a88e1 | 5246 | if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode)) |
87ad11b0 | 5247 | assemble_name (file, XSTR (x, 0)); |
b4a7bf10 | 5248 | else if (GET_CODE (x) == SYMBOL_REF && !flag_pic) |
87ad11b0 | 5249 | { |
5250 | assemble_name (file, XSTR (x, 0)); | |
9c0ac0fd | 5251 | fputs ("-$global$", file); |
87ad11b0 | 5252 | } |
5253 | else if (GET_CODE (x) == CONST) | |
5254 | { | |
611a88e1 | 5255 | const char *sep = ""; |
87ad11b0 | 5256 | int offset = 0; /* assembler wants -$global$ at end */ |
33ae0dba | 5257 | rtx base = NULL_RTX; |
6d36483b | 5258 | |
87ad11b0 | 5259 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF) |
5260 | { | |
5261 | base = XEXP (XEXP (x, 0), 0); | |
5262 | output_addr_const (file, base); | |
5263 | } | |
5264 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT) | |
5265 | offset = INTVAL (XEXP (XEXP (x, 0), 0)); | |
5266 | else abort (); | |
5267 | ||
5268 | if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF) | |
5269 | { | |
5270 | base = XEXP (XEXP (x, 0), 1); | |
5271 | output_addr_const (file, base); | |
5272 | } | |
5273 | else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
ea52c577 | 5274 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); |
87ad11b0 | 5275 | else abort (); |
5276 | ||
f9333726 | 5277 | /* How bogus. The compiler is apparently responsible for |
5278 | rounding the constant if it uses an LR field selector. | |
5279 | ||
5280 | The linker and/or assembler seem a better place since | |
5281 | they have to do this kind of thing already. | |
5282 | ||
5283 | If we fail to do this, HP's optimizing linker may eliminate | |
5284 | an addil, but not update the ldw/stw/ldo instruction that | |
5285 | uses the result of the addil. */ | |
5286 | if (round_constant) | |
5287 | offset = ((offset + 0x1000) & ~0x1fff); | |
5288 | ||
87ad11b0 | 5289 | if (GET_CODE (XEXP (x, 0)) == PLUS) |
5290 | { | |
5291 | if (offset < 0) | |
5292 | { | |
5293 | offset = -offset; | |
5294 | sep = "-"; | |
5295 | } | |
5296 | else | |
5297 | sep = "+"; | |
5298 | } | |
5299 | else if (GET_CODE (XEXP (x, 0)) == MINUS | |
5300 | && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) | |
5301 | sep = "-"; | |
5302 | else abort (); | |
5303 | ||
611a88e1 | 5304 | if (!read_only_operand (base, VOIDmode) && !flag_pic) |
9c0ac0fd | 5305 | fputs ("-$global$", file); |
f9333726 | 5306 | if (offset) |
ea52c577 | 5307 | fprintf (file, "%s%d", sep, offset); |
87ad11b0 | 5308 | } |
5309 | else | |
5310 | output_addr_const (file, x); | |
5311 | } | |
5312 | ||
92c473b8 | 5313 | /* Output boilerplate text to appear at the beginning of the file. |
5314 | There are several possible versions. */ | |
5315 | #define aputs(x) fputs(x, asm_out_file) | |
5316 | static inline void | |
5c1d8983 | 5317 | pa_file_start_level (void) |
92c473b8 | 5318 | { |
5319 | if (TARGET_64BIT) | |
5320 | aputs ("\t.LEVEL 2.0w\n"); | |
5321 | else if (TARGET_PA_20) | |
5322 | aputs ("\t.LEVEL 2.0\n"); | |
5323 | else if (TARGET_PA_11) | |
5324 | aputs ("\t.LEVEL 1.1\n"); | |
5325 | else | |
5326 | aputs ("\t.LEVEL 1.0\n"); | |
5327 | } | |
5328 | ||
5329 | static inline void | |
5c1d8983 | 5330 | pa_file_start_space (int sortspace) |
92c473b8 | 5331 | { |
5332 | aputs ("\t.SPACE $PRIVATE$"); | |
5333 | if (sortspace) | |
5334 | aputs (",SORT=16"); | |
5335 | aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31" | |
5336 | "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82" | |
5337 | "\n\t.SPACE $TEXT$"); | |
5338 | if (sortspace) | |
5339 | aputs (",SORT=8"); | |
5340 | aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44" | |
5341 | "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n"); | |
5342 | } | |
5343 | ||
5344 | static inline void | |
5c1d8983 | 5345 | pa_file_start_file (int want_version) |
92c473b8 | 5346 | { |
5347 | if (write_symbols != NO_DEBUG) | |
5348 | { | |
5349 | output_file_directive (asm_out_file, main_input_filename); | |
5350 | if (want_version) | |
5351 | aputs ("\t.version\t\"01.01\"\n"); | |
5352 | } | |
5353 | } | |
5354 | ||
5355 | static inline void | |
5c1d8983 | 5356 | pa_file_start_mcount (const char *aswhat) |
92c473b8 | 5357 | { |
5358 | if (profile_flag) | |
5359 | fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat); | |
5360 | } | |
5361 | ||
5362 | static void | |
5c1d8983 | 5363 | pa_elf_file_start (void) |
92c473b8 | 5364 | { |
5365 | pa_file_start_level (); | |
5366 | pa_file_start_mcount ("ENTRY"); | |
5367 | pa_file_start_file (0); | |
5368 | } | |
5369 | ||
5370 | static void | |
5c1d8983 | 5371 | pa_som_file_start (void) |
92c473b8 | 5372 | { |
5373 | pa_file_start_level (); | |
5374 | pa_file_start_space (0); | |
5375 | aputs ("\t.IMPORT $global$,DATA\n" | |
5376 | "\t.IMPORT $$dyncall,MILLICODE\n"); | |
5377 | pa_file_start_mcount ("CODE"); | |
5378 | pa_file_start_file (0); | |
5379 | } | |
5380 | ||
5381 | static void | |
5c1d8983 | 5382 | pa_linux_file_start (void) |
92c473b8 | 5383 | { |
5384 | pa_file_start_file (1); | |
5385 | pa_file_start_level (); | |
5386 | pa_file_start_mcount ("CODE"); | |
5387 | } | |
5388 | ||
5389 | static void | |
5c1d8983 | 5390 | pa_hpux64_gas_file_start (void) |
92c473b8 | 5391 | { |
5392 | pa_file_start_level (); | |
5393 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
5394 | if (profile_flag) | |
5395 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function"); | |
5396 | #endif | |
5397 | pa_file_start_file (1); | |
5398 | } | |
5399 | ||
5400 | static void | |
5c1d8983 | 5401 | pa_hpux64_hpas_file_start (void) |
92c473b8 | 5402 | { |
5403 | pa_file_start_level (); | |
5404 | pa_file_start_space (1); | |
5405 | pa_file_start_mcount ("CODE"); | |
5406 | pa_file_start_file (0); | |
5407 | } | |
5408 | #undef aputs | |
5409 | ||
ece88821 | 5410 | static struct deferred_plabel * |
5c1d8983 | 5411 | get_plabel (const char *fname) |
ece88821 | 5412 | { |
5413 | size_t i; | |
5414 | ||
5415 | /* See if we have already put this function on the list of deferred | |
5416 | plabels. This list is generally small, so a liner search is not | |
5417 | too ugly. If it proves too slow replace it with something faster. */ | |
5418 | for (i = 0; i < n_deferred_plabels; i++) | |
5419 | if (strcmp (fname, deferred_plabels[i].name) == 0) | |
5420 | break; | |
5421 | ||
5422 | /* If the deferred plabel list is empty, or this entry was not found | |
5423 | on the list, create a new entry on the list. */ | |
5424 | if (deferred_plabels == NULL || i == n_deferred_plabels) | |
5425 | { | |
5426 | const char *real_name; | |
5427 | ||
5428 | if (deferred_plabels == 0) | |
5429 | deferred_plabels = (struct deferred_plabel *) | |
5430 | ggc_alloc (sizeof (struct deferred_plabel)); | |
5431 | else | |
5432 | deferred_plabels = (struct deferred_plabel *) | |
5433 | ggc_realloc (deferred_plabels, | |
5434 | ((n_deferred_plabels + 1) | |
5435 | * sizeof (struct deferred_plabel))); | |
5436 | ||
5437 | i = n_deferred_plabels++; | |
5438 | deferred_plabels[i].internal_label = gen_label_rtx (); | |
5439 | deferred_plabels[i].name = ggc_strdup (fname); | |
5440 | ||
5441 | /* Gross. We have just implicitly taken the address of this function, | |
5442 | mark it as such. */ | |
5443 | real_name = (*targetm.strip_name_encoding) (fname); | |
5444 | TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1; | |
5445 | } | |
5446 | ||
5447 | return &deferred_plabels[i]; | |
5448 | } | |
5449 | ||
f6940372 | 5450 | static void |
5c1d8983 | 5451 | output_deferred_plabels (void) |
5cc6b2bc | 5452 | { |
e11bd7e5 | 5453 | size_t i; |
5cc6b2bc | 5454 | /* If we have deferred plabels, then we need to switch into the data |
5455 | section and align it to a 4 byte boundary before we output the | |
5456 | deferred plabels. */ | |
5457 | if (n_deferred_plabels) | |
5458 | { | |
5459 | data_section (); | |
f6940372 | 5460 | ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2); |
5cc6b2bc | 5461 | } |
5462 | ||
5463 | /* Now output the deferred plabels. */ | |
5464 | for (i = 0; i < n_deferred_plabels; i++) | |
5465 | { | |
f6940372 | 5466 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
5467 | CODE_LABEL_NUMBER (deferred_plabels[i].internal_label)); | |
09d688ff | 5468 | assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name), |
b70ea764 | 5469 | TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1); |
5cc6b2bc | 5470 | } |
5471 | } | |
5472 | ||
f2f543a3 | 5473 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
5474 | /* Initialize optabs to point to HPUX long double emulation routines. */ | |
5475 | static void | |
5476 | pa_hpux_init_libfuncs (void) | |
5477 | { | |
5478 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
5479 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
5480 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
5481 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
5482 | set_optab_libfunc (smin_optab, TFmode, "_U_Qmin"); | |
5483 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
5484 | set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt"); | |
5485 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
5486 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
5487 | ||
c88a6ebd | 5488 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); |
5489 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
5490 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
5491 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
5492 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
5493 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
6b27baea | 5494 | set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord"); |
f2f543a3 | 5495 | |
a7cc195f | 5496 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); |
5497 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
5498 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
5499 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
5500 | ||
5501 | set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT | |
5502 | ? "__U_Qfcnvfxt_quad_to_sgl" | |
5503 | : "_U_Qfcnvfxt_quad_to_sgl"); | |
5504 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl"); | |
5505 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl"); | |
5506 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl"); | |
5507 | ||
5508 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad"); | |
5509 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad"); | |
f2f543a3 | 5510 | } |
5511 | #endif | |
5512 | ||
87ad11b0 | 5513 | /* HP's millicode routines mean something special to the assembler. |
5514 | Keep track of which ones we have used. */ | |
5515 | ||
c2271c34 | 5516 | enum millicodes { remI, remU, divI, divU, mulI, end1000 }; |
5c1d8983 | 5517 | static void import_milli (enum millicodes); |
ea52c577 | 5518 | static char imported[(int) end1000]; |
c2271c34 | 5519 | static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"}; |
e99c3a1d | 5520 | static const char import_string[] = ".IMPORT $$....,MILLICODE"; |
87ad11b0 | 5521 | #define MILLI_START 10 |
5522 | ||
57ed30e5 | 5523 | static void |
5c1d8983 | 5524 | import_milli (enum millicodes code) |
87ad11b0 | 5525 | { |
5526 | char str[sizeof (import_string)]; | |
6d36483b | 5527 | |
ea52c577 | 5528 | if (!imported[(int) code]) |
87ad11b0 | 5529 | { |
ea52c577 | 5530 | imported[(int) code] = 1; |
87ad11b0 | 5531 | strcpy (str, import_string); |
ea52c577 | 5532 | strncpy (str + MILLI_START, milli_names[(int) code], 4); |
87ad11b0 | 5533 | output_asm_insn (str, 0); |
5534 | } | |
5535 | } | |
5536 | ||
6d36483b | 5537 | /* The register constraints have put the operands and return value in |
6dc3b0d9 | 5538 | the proper registers. */ |
87ad11b0 | 5539 | |
611a88e1 | 5540 | const char * |
5c1d8983 | 5541 | output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn) |
87ad11b0 | 5542 | { |
d178f670 | 5543 | import_milli (mulI); |
440c23df | 5544 | return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI")); |
87ad11b0 | 5545 | } |
5546 | ||
6dc3b0d9 | 5547 | /* Emit the rtl for doing a division by a constant. */ |
87ad11b0 | 5548 | |
d178f670 | 5549 | /* Do magic division millicodes exist for this value? */ |
e99c3a1d | 5550 | static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, |
5551 | 1, 1}; | |
87ad11b0 | 5552 | |
6d36483b | 5553 | /* We'll use an array to keep track of the magic millicodes and |
87ad11b0 | 5554 | whether or not we've used them already. [n][0] is signed, [n][1] is |
6dc3b0d9 | 5555 | unsigned. */ |
87ad11b0 | 5556 | |
87ad11b0 | 5557 | static int div_milli[16][2]; |
5558 | ||
5559 | int | |
5c1d8983 | 5560 | div_operand (rtx op, enum machine_mode mode) |
87ad11b0 | 5561 | { |
5562 | return (mode == SImode | |
5563 | && ((GET_CODE (op) == REG && REGNO (op) == 25) | |
5564 | || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0 | |
5565 | && INTVAL (op) < 16 && magic_milli[INTVAL (op)]))); | |
5566 | } | |
5567 | ||
5568 | int | |
5c1d8983 | 5569 | emit_hpdiv_const (rtx *operands, int unsignedp) |
87ad11b0 | 5570 | { |
5571 | if (GET_CODE (operands[2]) == CONST_INT | |
5572 | && INTVAL (operands[2]) > 0 | |
5573 | && INTVAL (operands[2]) < 16 | |
5574 | && magic_milli[INTVAL (operands[2])]) | |
5575 | { | |
2013ddf6 | 5576 | rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31); |
5577 | ||
ad851752 | 5578 | emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]); |
87ad11b0 | 5579 | emit |
75b1a41a | 5580 | (gen_rtx_PARALLEL |
5581 | (VOIDmode, | |
c2078db8 | 5582 | gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29), |
ad851752 | 5583 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, |
5584 | SImode, | |
5585 | gen_rtx_REG (SImode, 26), | |
5586 | operands[2])), | |
c2078db8 | 5587 | gen_rtx_CLOBBER (VOIDmode, operands[4]), |
ad851752 | 5588 | gen_rtx_CLOBBER (VOIDmode, operands[3]), |
5589 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)), | |
5590 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)), | |
2013ddf6 | 5591 | gen_rtx_CLOBBER (VOIDmode, ret)))); |
ad851752 | 5592 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 29)); |
87ad11b0 | 5593 | return 1; |
5594 | } | |
5595 | return 0; | |
5596 | } | |
5597 | ||
611a88e1 | 5598 | const char * |
5c1d8983 | 5599 | output_div_insn (rtx *operands, int unsignedp, rtx insn) |
87ad11b0 | 5600 | { |
5601 | int divisor; | |
6d36483b | 5602 | |
5603 | /* If the divisor is a constant, try to use one of the special | |
87ad11b0 | 5604 | opcodes .*/ |
5605 | if (GET_CODE (operands[0]) == CONST_INT) | |
5606 | { | |
d6686e21 | 5607 | static char buf[100]; |
87ad11b0 | 5608 | divisor = INTVAL (operands[0]); |
5609 | if (!div_milli[divisor][unsignedp]) | |
5610 | { | |
d6686e21 | 5611 | div_milli[divisor][unsignedp] = 1; |
87ad11b0 | 5612 | if (unsignedp) |
5613 | output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands); | |
5614 | else | |
5615 | output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands); | |
87ad11b0 | 5616 | } |
5617 | if (unsignedp) | |
d6686e21 | 5618 | { |
4840a03a | 5619 | sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC, |
5620 | INTVAL (operands[0])); | |
c7a4e712 | 5621 | return output_millicode_call (insn, |
ad851752 | 5622 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5623 | } |
5624 | else | |
5625 | { | |
4840a03a | 5626 | sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC, |
5627 | INTVAL (operands[0])); | |
c7a4e712 | 5628 | return output_millicode_call (insn, |
ad851752 | 5629 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5630 | } |
87ad11b0 | 5631 | } |
6dc3b0d9 | 5632 | /* Divisor isn't a special constant. */ |
87ad11b0 | 5633 | else |
5634 | { | |
5635 | if (unsignedp) | |
5636 | { | |
5637 | import_milli (divU); | |
c7a4e712 | 5638 | return output_millicode_call (insn, |
ad851752 | 5639 | gen_rtx_SYMBOL_REF (SImode, "$$divU")); |
87ad11b0 | 5640 | } |
5641 | else | |
5642 | { | |
5643 | import_milli (divI); | |
c7a4e712 | 5644 | return output_millicode_call (insn, |
ad851752 | 5645 | gen_rtx_SYMBOL_REF (SImode, "$$divI")); |
87ad11b0 | 5646 | } |
5647 | } | |
5648 | } | |
5649 | ||
6dc3b0d9 | 5650 | /* Output a $$rem millicode to do mod. */ |
87ad11b0 | 5651 | |
611a88e1 | 5652 | const char * |
5c1d8983 | 5653 | output_mod_insn (int unsignedp, rtx insn) |
87ad11b0 | 5654 | { |
5655 | if (unsignedp) | |
5656 | { | |
5657 | import_milli (remU); | |
c7a4e712 | 5658 | return output_millicode_call (insn, |
ad851752 | 5659 | gen_rtx_SYMBOL_REF (SImode, "$$remU")); |
87ad11b0 | 5660 | } |
5661 | else | |
5662 | { | |
5663 | import_milli (remI); | |
c7a4e712 | 5664 | return output_millicode_call (insn, |
ad851752 | 5665 | gen_rtx_SYMBOL_REF (SImode, "$$remI")); |
87ad11b0 | 5666 | } |
5667 | } | |
5668 | ||
5669 | void | |
5c1d8983 | 5670 | output_arg_descriptor (rtx call_insn) |
87ad11b0 | 5671 | { |
611a88e1 | 5672 | const char *arg_regs[4]; |
87ad11b0 | 5673 | enum machine_mode arg_mode; |
df0651dc | 5674 | rtx link; |
87ad11b0 | 5675 | int i, output_flag = 0; |
5676 | int regno; | |
6d36483b | 5677 | |
5e3c5739 | 5678 | /* We neither need nor want argument location descriptors for the |
5d0619cc | 5679 | 64bit runtime environment or the ELF32 environment. */ |
5680 | if (TARGET_64BIT || TARGET_ELF32) | |
5e3c5739 | 5681 | return; |
5682 | ||
87ad11b0 | 5683 | for (i = 0; i < 4; i++) |
5684 | arg_regs[i] = 0; | |
5685 | ||
738176ab | 5686 | /* Specify explicitly that no argument relocations should take place |
5687 | if using the portable runtime calling conventions. */ | |
5688 | if (TARGET_PORTABLE_RUNTIME) | |
5689 | { | |
9c0ac0fd | 5690 | fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n", |
5691 | asm_out_file); | |
738176ab | 5692 | return; |
5693 | } | |
5694 | ||
df0651dc | 5695 | if (GET_CODE (call_insn) != CALL_INSN) |
5696 | abort (); | |
5697 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1)) | |
87ad11b0 | 5698 | { |
df0651dc | 5699 | rtx use = XEXP (link, 0); |
c12afafd | 5700 | |
df0651dc | 5701 | if (! (GET_CODE (use) == USE |
5702 | && GET_CODE (XEXP (use, 0)) == REG | |
5703 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
c12afafd | 5704 | continue; |
5705 | ||
df0651dc | 5706 | arg_mode = GET_MODE (XEXP (use, 0)); |
5707 | regno = REGNO (XEXP (use, 0)); | |
87ad11b0 | 5708 | if (regno >= 23 && regno <= 26) |
372ef038 | 5709 | { |
5710 | arg_regs[26 - regno] = "GR"; | |
5711 | if (arg_mode == DImode) | |
5712 | arg_regs[25 - regno] = "GR"; | |
5713 | } | |
df0651dc | 5714 | else if (regno >= 32 && regno <= 39) |
87ad11b0 | 5715 | { |
5716 | if (arg_mode == SFmode) | |
df0651dc | 5717 | arg_regs[(regno - 32) / 2] = "FR"; |
e6ba640e | 5718 | else |
87ad11b0 | 5719 | { |
eeec72c0 | 5720 | #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED |
df0651dc | 5721 | arg_regs[(regno - 34) / 2] = "FR"; |
5722 | arg_regs[(regno - 34) / 2 + 1] = "FU"; | |
87ad11b0 | 5723 | #else |
df0651dc | 5724 | arg_regs[(regno - 34) / 2] = "FU"; |
5725 | arg_regs[(regno - 34) / 2 + 1] = "FR"; | |
87ad11b0 | 5726 | #endif |
5727 | } | |
87ad11b0 | 5728 | } |
5729 | } | |
5730 | fputs ("\t.CALL ", asm_out_file); | |
5731 | for (i = 0; i < 4; i++) | |
5732 | { | |
5733 | if (arg_regs[i]) | |
5734 | { | |
5735 | if (output_flag++) | |
5736 | fputc (',', asm_out_file); | |
5737 | fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]); | |
5738 | } | |
5739 | } | |
5740 | fputc ('\n', asm_out_file); | |
5741 | } | |
5742 | \f | |
9c0ac0fd | 5743 | /* Return the class of any secondary reload register that is needed to |
5744 | move IN into a register in class CLASS using mode MODE. | |
5745 | ||
5746 | Profiling has showed this routine and its descendants account for | |
5747 | a significant amount of compile time (~7%). So it has been | |
5748 | optimized to reduce redundant computations and eliminate useless | |
5749 | function calls. | |
5750 | ||
5751 | It might be worthwhile to try and make this a leaf function too. */ | |
87ad11b0 | 5752 | |
5753 | enum reg_class | |
5c1d8983 | 5754 | secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in) |
87ad11b0 | 5755 | { |
9c0ac0fd | 5756 | int regno, is_symbolic; |
87ad11b0 | 5757 | |
b4a7bf10 | 5758 | /* Trying to load a constant into a FP register during PIC code |
5759 | generation will require %r1 as a scratch register. */ | |
fc44315f | 5760 | if (flag_pic |
b4a7bf10 | 5761 | && GET_MODE_CLASS (mode) == MODE_INT |
5762 | && FP_REG_CLASS_P (class) | |
5763 | && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE)) | |
5764 | return R1_REGS; | |
5765 | ||
9c0ac0fd | 5766 | /* Profiling showed the PA port spends about 1.3% of its compilation |
5767 | time in true_regnum from calls inside secondary_reload_class. */ | |
5768 | ||
5769 | if (GET_CODE (in) == REG) | |
5770 | { | |
5771 | regno = REGNO (in); | |
5772 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5773 | regno = true_regnum (in); | |
5774 | } | |
5775 | else if (GET_CODE (in) == SUBREG) | |
5776 | regno = true_regnum (in); | |
9c0ac0fd | 5777 | else |
5778 | regno = -1; | |
5779 | ||
76a0ced5 | 5780 | /* If we have something like (mem (mem (...)), we can safely assume the |
5781 | inner MEM will end up in a general register after reloading, so there's | |
5782 | no need for a secondary reload. */ | |
5783 | if (GET_CODE (in) == MEM | |
5784 | && GET_CODE (XEXP (in, 0)) == MEM) | |
5785 | return NO_REGS; | |
5786 | ||
5787 | /* Handle out of range displacement for integer mode loads/stores of | |
5788 | FP registers. */ | |
d2498717 | 5789 | if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1) |
6d36483b | 5790 | && GET_MODE_CLASS (mode) == MODE_INT |
5791 | && FP_REG_CLASS_P (class)) | |
d6f01525 | 5792 | || (class == SHIFT_REGS && (regno <= 0 || regno >= 32))) |
9c6d4825 | 5793 | return GENERAL_REGS; |
d2c1d63d | 5794 | |
7c4b32f3 | 5795 | /* A SAR<->FP register copy requires a secondary register (GPR) as |
5796 | well as secondary memory. */ | |
5797 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5798 | && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class)) | |
5799 | || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno))))) | |
5800 | return GENERAL_REGS; | |
5801 | ||
2ee034bc | 5802 | if (GET_CODE (in) == HIGH) |
5803 | in = XEXP (in, 0); | |
5804 | ||
9c0ac0fd | 5805 | /* Profiling has showed GCC spends about 2.6% of its compilation |
5806 | time in symbolic_operand from calls inside secondary_reload_class. | |
5807 | ||
5808 | We use an inline copy and only compute its return value once to avoid | |
5809 | useless work. */ | |
5810 | switch (GET_CODE (in)) | |
5811 | { | |
5812 | rtx tmp; | |
5813 | ||
5814 | case SYMBOL_REF: | |
5815 | case LABEL_REF: | |
5816 | is_symbolic = 1; | |
5817 | break; | |
5818 | case CONST: | |
5819 | tmp = XEXP (in, 0); | |
5820 | is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF | |
5821 | || GET_CODE (XEXP (tmp, 0)) == LABEL_REF) | |
5822 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT); | |
5823 | break; | |
76a0ced5 | 5824 | |
9c0ac0fd | 5825 | default: |
5826 | is_symbolic = 0; | |
5827 | break; | |
5828 | } | |
9840d99d | 5829 | |
b4a7bf10 | 5830 | if (!flag_pic |
9c0ac0fd | 5831 | && is_symbolic |
611a88e1 | 5832 | && read_only_operand (in, VOIDmode)) |
b4a7bf10 | 5833 | return NO_REGS; |
5834 | ||
9c0ac0fd | 5835 | if (class != R1_REGS && is_symbolic) |
2ee034bc | 5836 | return R1_REGS; |
5837 | ||
d2c1d63d | 5838 | return NO_REGS; |
87ad11b0 | 5839 | } |
5840 | ||
5841 | enum direction | |
5c1d8983 | 5842 | function_arg_padding (enum machine_mode mode, tree type) |
87ad11b0 | 5843 | { |
ac965869 | 5844 | if (mode == BLKmode |
5845 | || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type))) | |
5846 | { | |
5847 | /* Return none if justification is not required. */ | |
5848 | if (type | |
5849 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
5850 | && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0) | |
5851 | return none; | |
5852 | ||
5853 | /* The directions set here are ignored when a BLKmode argument larger | |
5854 | than a word is placed in a register. Different code is used for | |
5855 | the stack and registers. This makes it difficult to have a | |
5856 | consistent data representation for both the stack and registers. | |
5857 | For both runtimes, the justification and padding for arguments on | |
5858 | the stack and in registers should be identical. */ | |
5859 | if (TARGET_64BIT) | |
5860 | /* The 64-bit runtime specifies left justification for aggregates. */ | |
5861 | return upward; | |
87ad11b0 | 5862 | else |
ac965869 | 5863 | /* The 32-bit runtime architecture specifies right justification. |
5864 | When the argument is passed on the stack, the argument is padded | |
5865 | with garbage on the left. The HP compiler pads with zeros. */ | |
5866 | return downward; | |
87ad11b0 | 5867 | } |
ac965869 | 5868 | |
5869 | if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
87ad11b0 | 5870 | return downward; |
87ad11b0 | 5871 | else |
5872 | return none; | |
5873 | } | |
5874 | ||
87ad11b0 | 5875 | \f |
55f54832 | 5876 | /* Do what is necessary for `va_start'. We look at the current function |
5877 | to determine if stdargs or varargs is used and fill in an initial | |
5878 | va_list. A pointer to this constructor is returned. */ | |
87ad11b0 | 5879 | |
b8debbe8 | 5880 | static rtx |
5c1d8983 | 5881 | hppa_builtin_saveregs (void) |
87ad11b0 | 5882 | { |
01251cbc | 5883 | rtx offset, dest; |
87ad11b0 | 5884 | tree fntype = TREE_TYPE (current_function_decl); |
5885 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
5886 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
5887 | != void_type_node))) | |
5888 | ? UNITS_PER_WORD : 0); | |
5889 | ||
5890 | if (argadj) | |
5891 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
5892 | else | |
5893 | offset = current_function_arg_offset_rtx; | |
9c6d4825 | 5894 | |
5e3c5739 | 5895 | if (TARGET_64BIT) |
5896 | { | |
5897 | int i, off; | |
9840d99d | 5898 | |
5e3c5739 | 5899 | /* Adjust for varargs/stdarg differences. */ |
5900 | if (argadj) | |
5901 | offset = plus_constant (current_function_arg_offset_rtx, -argadj); | |
5902 | else | |
5903 | offset = current_function_arg_offset_rtx; | |
5904 | ||
5905 | /* We need to save %r26 .. %r19 inclusive starting at offset -64 | |
5906 | from the incoming arg pointer and growing to larger addresses. */ | |
5907 | for (i = 26, off = -64; i >= 19; i--, off += 8) | |
5908 | emit_move_insn (gen_rtx_MEM (word_mode, | |
5909 | plus_constant (arg_pointer_rtx, off)), | |
5910 | gen_rtx_REG (word_mode, i)); | |
5911 | ||
5912 | /* The incoming args pointer points just beyond the flushback area; | |
8ef587dc | 5913 | normally this is not a serious concern. However, when we are doing |
5e3c5739 | 5914 | varargs/stdargs we want to make the arg pointer point to the start |
5915 | of the incoming argument area. */ | |
5916 | emit_move_insn (virtual_incoming_args_rtx, | |
5917 | plus_constant (arg_pointer_rtx, -64)); | |
5918 | ||
5919 | /* Now return a pointer to the first anonymous argument. */ | |
5920 | return copy_to_reg (expand_binop (Pmode, add_optab, | |
5921 | virtual_incoming_args_rtx, | |
5922 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
5923 | } | |
5924 | ||
6dc3b0d9 | 5925 | /* Store general registers on the stack. */ |
ad851752 | 5926 | dest = gen_rtx_MEM (BLKmode, |
5927 | plus_constant (current_function_internal_arg_pointer, | |
5928 | -16)); | |
ab6ab77e | 5929 | set_mem_alias_set (dest, get_varargs_alias_set ()); |
2a631e19 | 5930 | set_mem_align (dest, BITS_PER_WORD); |
530178a9 | 5931 | move_block_from_reg (23, dest, 4); |
01251cbc | 5932 | |
76a0ced5 | 5933 | /* move_block_from_reg will emit code to store the argument registers |
5934 | individually as scalar stores. | |
5935 | ||
5936 | However, other insns may later load from the same addresses for | |
ad87de1e | 5937 | a structure load (passing a struct to a varargs routine). |
76a0ced5 | 5938 | |
5939 | The alias code assumes that such aliasing can never happen, so we | |
5940 | have to keep memory referencing insns from moving up beyond the | |
5941 | last argument register store. So we emit a blockage insn here. */ | |
5942 | emit_insn (gen_blockage ()); | |
5943 | ||
9c6d4825 | 5944 | return copy_to_reg (expand_binop (Pmode, add_optab, |
5945 | current_function_internal_arg_pointer, | |
5946 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
87ad11b0 | 5947 | } |
d6f01525 | 5948 | |
72899a61 | 5949 | void |
5c1d8983 | 5950 | hppa_va_start (tree valist, rtx nextarg) |
72899a61 | 5951 | { |
5952 | nextarg = expand_builtin_saveregs (); | |
7df226a2 | 5953 | std_expand_builtin_va_start (valist, nextarg); |
72899a61 | 5954 | } |
5955 | ||
4c33eb68 | 5956 | static tree |
5957 | hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p) | |
72899a61 | 5958 | { |
5e3c5739 | 5959 | if (TARGET_64BIT) |
5960 | { | |
4c33eb68 | 5961 | /* Args grow upward. We can use the generic routines. */ |
bef380a4 | 5962 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
72899a61 | 5963 | } |
ac965869 | 5964 | else /* !TARGET_64BIT */ |
72899a61 | 5965 | { |
4c33eb68 | 5966 | tree ptr = build_pointer_type (type); |
5967 | tree valist_type; | |
5968 | tree t, u; | |
5969 | unsigned int size, ofs; | |
bef380a4 | 5970 | bool indirect; |
72899a61 | 5971 | |
bef380a4 | 5972 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0); |
4c33eb68 | 5973 | if (indirect) |
ac965869 | 5974 | { |
4c33eb68 | 5975 | type = ptr; |
5976 | ptr = build_pointer_type (type); | |
72899a61 | 5977 | } |
4c33eb68 | 5978 | size = int_size_in_bytes (type); |
5979 | valist_type = TREE_TYPE (valist); | |
ac965869 | 5980 | |
4c33eb68 | 5981 | /* Args grow down. Not handled by generic routines. */ |
ac965869 | 5982 | |
4c33eb68 | 5983 | u = fold_convert (valist_type, size_in_bytes (type)); |
5984 | t = build (MINUS_EXPR, valist_type, valist, u); | |
ac965869 | 5985 | |
4c33eb68 | 5986 | /* Copied from va-pa.h, but we probably don't need to align to |
5987 | word size, since we generate and preserve that invariant. */ | |
5988 | u = build_int_2 ((size > 4 ? -8 : -4), -1); | |
5989 | u = fold_convert (valist_type, u); | |
5990 | t = build (BIT_AND_EXPR, valist_type, t, u); | |
5991 | ||
5992 | t = build (MODIFY_EXPR, valist_type, valist, t); | |
72899a61 | 5993 | |
4c33eb68 | 5994 | ofs = (8 - size) % 4; |
5995 | if (ofs != 0) | |
5996 | { | |
5997 | u = fold_convert (valist_type, size_int (ofs)); | |
5998 | t = build (PLUS_EXPR, valist_type, t, u); | |
ac965869 | 5999 | } |
72899a61 | 6000 | |
4c33eb68 | 6001 | t = fold_convert (ptr, t); |
6002 | t = build_fold_indirect_ref (t); | |
72899a61 | 6003 | |
4c33eb68 | 6004 | if (indirect) |
6005 | t = build_fold_indirect_ref (t); | |
72899a61 | 6006 | |
4c33eb68 | 6007 | return t; |
6008 | } | |
6009 | } | |
72899a61 | 6010 | |
6d36483b | 6011 | /* This routine handles all the normal conditional branch sequences we |
6012 | might need to generate. It handles compare immediate vs compare | |
6013 | register, nullification of delay slots, varying length branches, | |
0d986529 | 6014 | negated branches, and all combinations of the above. It returns the |
6d36483b | 6015 | output appropriate to emit the branch corresponding to all given |
0d986529 | 6016 | parameters. */ |
6017 | ||
611a88e1 | 6018 | const char * |
5c1d8983 | 6019 | output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn) |
29a4502c | 6020 | { |
0d986529 | 6021 | static char buf[100]; |
6022 | int useskip = 0; | |
e9ec370e | 6023 | rtx xoperands[5]; |
0d986529 | 6024 | |
ece0fa59 | 6025 | /* A conditional branch to the following instruction (eg the delay slot) |
6026 | is asking for a disaster. This can happen when not optimizing and | |
6027 | when jump optimization fails. | |
29a4502c | 6028 | |
38efba6c | 6029 | While it is usually safe to emit nothing, this can fail if the |
6030 | preceding instruction is a nullified branch with an empty delay | |
6031 | slot and the same branch target as this branch. We could check | |
6032 | for this but jump optimization should eliminate nop jumps. It | |
6033 | is always safe to emit a nop. */ | |
ece0fa59 | 6034 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6035 | return "nop"; | |
6d36483b | 6036 | |
22699a7e | 6037 | /* The doubleword form of the cmpib instruction doesn't have the LEU |
6038 | and GTU conditions while the cmpb instruction does. Since we accept | |
6039 | zero for cmpb, we must ensure that we use cmpb for the comparison. */ | |
6040 | if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx) | |
6041 | operands[2] = gen_rtx_REG (DImode, 0); | |
6042 | ||
5fbd5940 | 6043 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6044 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6045 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6046 | nullify = 1; |
6047 | ||
6048 | /* If this is a short forward conditional branch which did not get | |
6049 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6050 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6051 | nullify = forward_branch_p (insn); |
6052 | ||
6d36483b | 6053 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6054 | comclr instruction. This avoids a single cycle penalty due to |
6055 | mis-predicted branch if we fall through (branch not taken). */ | |
5a1231ef | 6056 | if (length == 4 |
5fbd5940 | 6057 | && next_real_insn (insn) != 0 |
5a1231ef | 6058 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 6059 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 6060 | && nullify) |
6061 | useskip = 1; | |
6062 | ||
6063 | switch (length) | |
6064 | { | |
5fbd5940 | 6065 | /* All short conditional branches except backwards with an unfilled |
6066 | delay slot. */ | |
5a1231ef | 6067 | case 4: |
0d986529 | 6068 | if (useskip) |
e4065f95 | 6069 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
0d986529 | 6070 | else |
e4065f95 | 6071 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6072 | if (GET_MODE (operands[1]) == DImode) |
6073 | strcat (buf, "*"); | |
0d986529 | 6074 | if (negated) |
6075 | strcat (buf, "%B3"); | |
6076 | else | |
6077 | strcat (buf, "%S3"); | |
6078 | if (useskip) | |
5a811d43 | 6079 | strcat (buf, " %2,%r1,%%r0"); |
0d986529 | 6080 | else if (nullify) |
9e49be0e | 6081 | strcat (buf, ",n %2,%r1,%0"); |
6d36483b | 6082 | else |
9e49be0e | 6083 | strcat (buf, " %2,%r1,%0"); |
0d986529 | 6084 | break; |
6085 | ||
87fcb603 | 6086 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6087 | unfilled delay slot is treated just like a long backward branch |
6088 | with an unfilled delay slot. */ | |
5a1231ef | 6089 | case 8: |
5fbd5940 | 6090 | /* Handle weird backwards branch with a filled delay slot |
6091 | with is nullified. */ | |
6092 | if (dbr_sequence_length () != 0 | |
6093 | && ! forward_branch_p (insn) | |
6094 | && nullify) | |
6095 | { | |
e4065f95 | 6096 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6097 | if (GET_MODE (operands[1]) == DImode) |
6098 | strcat (buf, "*"); | |
5fbd5940 | 6099 | if (negated) |
6100 | strcat (buf, "%S3"); | |
6101 | else | |
6102 | strcat (buf, "%B3"); | |
5a811d43 | 6103 | strcat (buf, ",n %2,%r1,.+12\n\tb %0"); |
5fbd5940 | 6104 | } |
43f0c1f2 | 6105 | /* Handle short backwards branch with an unfilled delay slot. |
6106 | Using a comb;nop rather than comiclr;bl saves 1 cycle for both | |
6107 | taken and untaken branches. */ | |
6108 | else if (dbr_sequence_length () == 0 | |
6109 | && ! forward_branch_p (insn) | |
47fc0706 | 6110 | && INSN_ADDRESSES_SET_P () |
6111 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6112 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6113 | { |
e4065f95 | 6114 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6115 | if (GET_MODE (operands[1]) == DImode) |
6116 | strcat (buf, "*"); | |
43f0c1f2 | 6117 | if (negated) |
9e49be0e | 6118 | strcat (buf, "%B3 %2,%r1,%0%#"); |
43f0c1f2 | 6119 | else |
9e49be0e | 6120 | strcat (buf, "%S3 %2,%r1,%0%#"); |
43f0c1f2 | 6121 | } |
0d986529 | 6122 | else |
5fbd5940 | 6123 | { |
e4065f95 | 6124 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
5e3c5739 | 6125 | if (GET_MODE (operands[1]) == DImode) |
6126 | strcat (buf, "*"); | |
5fbd5940 | 6127 | if (negated) |
6128 | strcat (buf, "%S3"); | |
6129 | else | |
6130 | strcat (buf, "%B3"); | |
6131 | if (nullify) | |
5a811d43 | 6132 | strcat (buf, " %2,%r1,%%r0\n\tb,n %0"); |
5fbd5940 | 6133 | else |
5a811d43 | 6134 | strcat (buf, " %2,%r1,%%r0\n\tb %0"); |
5fbd5940 | 6135 | } |
0d986529 | 6136 | break; |
6137 | ||
c8a0e52b | 6138 | case 20: |
e9ec370e | 6139 | case 28: |
6140 | xoperands[0] = operands[0]; | |
6141 | xoperands[1] = operands[1]; | |
6142 | xoperands[2] = operands[2]; | |
6143 | xoperands[3] = operands[3]; | |
6144 | ||
6145 | /* The reversed conditional branch must branch over one additional | |
6146 | instruction if the delay slot is filled. If the delay slot | |
6147 | is empty, the instruction after the reversed condition branch | |
6148 | must be nullified. */ | |
6149 | nullify = dbr_sequence_length () == 0; | |
6150 | xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4); | |
c8a0e52b | 6151 | |
6152 | /* Create a reversed conditional branch which branches around | |
6153 | the following insns. */ | |
e9ec370e | 6154 | if (GET_MODE (operands[1]) != DImode) |
6155 | { | |
6156 | if (nullify) | |
6157 | { | |
6158 | if (negated) | |
6159 | strcpy (buf, | |
6160 | "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}"); | |
6161 | else | |
6162 | strcpy (buf, | |
6163 | "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}"); | |
6164 | } | |
6165 | else | |
6166 | { | |
6167 | if (negated) | |
6168 | strcpy (buf, | |
6169 | "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}"); | |
6170 | else | |
6171 | strcpy (buf, | |
6172 | "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}"); | |
6173 | } | |
6174 | } | |
c8a0e52b | 6175 | else |
5e3c5739 | 6176 | { |
e9ec370e | 6177 | if (nullify) |
6178 | { | |
6179 | if (negated) | |
6180 | strcpy (buf, | |
6181 | "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}"); | |
6182 | else | |
6183 | strcpy (buf, | |
6184 | "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}"); | |
6185 | } | |
5e3c5739 | 6186 | else |
e9ec370e | 6187 | { |
6188 | if (negated) | |
6189 | strcpy (buf, | |
6190 | "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}"); | |
6191 | else | |
6192 | strcpy (buf, | |
6193 | "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}"); | |
6194 | } | |
5e3c5739 | 6195 | } |
c8a0e52b | 6196 | |
e9ec370e | 6197 | output_asm_insn (buf, xoperands); |
6198 | return output_lbranch (operands[0], insn); | |
c8a0e52b | 6199 | |
e9ec370e | 6200 | default: |
6201 | abort (); | |
6202 | } | |
6203 | return buf; | |
6204 | } | |
c8a0e52b | 6205 | |
e9ec370e | 6206 | /* This routine handles long unconditional branches that exceed the |
6207 | maximum range of a simple branch instruction. */ | |
c8a0e52b | 6208 | |
e9ec370e | 6209 | const char * |
5c1d8983 | 6210 | output_lbranch (rtx dest, rtx insn) |
e9ec370e | 6211 | { |
6212 | rtx xoperands[2]; | |
6213 | ||
6214 | xoperands[0] = dest; | |
c8a0e52b | 6215 | |
e9ec370e | 6216 | /* First, free up the delay slot. */ |
6217 | if (dbr_sequence_length () != 0) | |
6218 | { | |
6219 | /* We can't handle a jump in the delay slot. */ | |
6220 | if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN) | |
6221 | abort (); | |
c8a0e52b | 6222 | |
e9ec370e | 6223 | final_scan_insn (NEXT_INSN (insn), asm_out_file, |
fbf5169c | 6224 | optimize, 0, 0, NULL); |
c8a0e52b | 6225 | |
e9ec370e | 6226 | /* Now delete the delay insn. */ |
6227 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
6228 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
6229 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
6230 | } | |
c8a0e52b | 6231 | |
e9ec370e | 6232 | /* Output an insn to save %r1. The runtime documentation doesn't |
6233 | specify whether the "Clean Up" slot in the callers frame can | |
6234 | be clobbered by the callee. It isn't copied by HP's builtin | |
6235 | alloca, so this suggests that it can be clobbered if necessary. | |
6236 | The "Static Link" location is copied by HP builtin alloca, so | |
6237 | we avoid using it. Using the cleanup slot might be a problem | |
6238 | if we have to interoperate with languages that pass cleanup | |
6239 | information. However, it should be possible to handle these | |
6240 | situations with GCC's asm feature. | |
6241 | ||
6242 | The "Current RP" slot is reserved for the called procedure, so | |
6243 | we try to use it when we don't have a frame of our own. It's | |
6244 | rather unlikely that we won't have a frame when we need to emit | |
6245 | a very long branch. | |
6246 | ||
6247 | Really the way to go long term is a register scavenger; goto | |
6248 | the target of the jump and find a register which we can use | |
6249 | as a scratch to hold the value in %r1. Then, we wouldn't have | |
6250 | to free up the delay slot or clobber a slot that may be needed | |
6251 | for other purposes. */ | |
6252 | if (TARGET_64BIT) | |
6253 | { | |
6254 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6255 | /* Use the return pointer slot in the frame marker. */ | |
6256 | output_asm_insn ("std %%r1,-16(%%r30)", xoperands); | |
6257 | else | |
6258 | /* Use the slot at -40 in the frame marker since HP builtin | |
6259 | alloca doesn't copy it. */ | |
6260 | output_asm_insn ("std %%r1,-40(%%r30)", xoperands); | |
6261 | } | |
6262 | else | |
6263 | { | |
6264 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6265 | /* Use the return pointer slot in the frame marker. */ | |
6266 | output_asm_insn ("stw %%r1,-20(%%r30)", xoperands); | |
6267 | else | |
6268 | /* Use the "Clean Up" slot in the frame marker. In GCC, | |
6269 | the only other use of this location is for copying a | |
6270 | floating point double argument from a floating-point | |
6271 | register to two general registers. The copy is done | |
19ee40ed | 6272 | as an "atomic" operation when outputting a call, so it |
e9ec370e | 6273 | won't interfere with our using the location here. */ |
6274 | output_asm_insn ("stw %%r1,-12(%%r30)", xoperands); | |
6275 | } | |
b70ea764 | 6276 | |
2247cc5f | 6277 | if (TARGET_PORTABLE_RUNTIME) |
6278 | { | |
6279 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6280 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
6281 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6282 | } | |
6283 | else if (flag_pic) | |
e9ec370e | 6284 | { |
6285 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
6286 | if (TARGET_SOM || !TARGET_GAS) | |
6287 | { | |
6288 | xoperands[1] = gen_label_rtx (); | |
6289 | output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands); | |
6290 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
6291 | CODE_LABEL_NUMBER (xoperands[1])); | |
6292 | output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands); | |
c8a0e52b | 6293 | } |
e9ec370e | 6294 | else |
6295 | { | |
6296 | output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6297 | output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6298 | } | |
6299 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6300 | } | |
6301 | else | |
6302 | /* Now output a very long branch to the original target. */ | |
6303 | output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands); | |
c8a0e52b | 6304 | |
e9ec370e | 6305 | /* Now restore the value of %r1 in the delay slot. */ |
6306 | if (TARGET_64BIT) | |
6307 | { | |
6308 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6309 | return "ldd -16(%%r30),%%r1"; | |
6310 | else | |
6311 | return "ldd -40(%%r30),%%r1"; | |
6312 | } | |
6313 | else | |
6314 | { | |
6315 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6316 | return "ldw -20(%%r30),%%r1"; | |
6317 | else | |
6318 | return "ldw -12(%%r30),%%r1"; | |
5fbd5940 | 6319 | } |
0d986529 | 6320 | } |
6321 | ||
6d36483b | 6322 | /* This routine handles all the branch-on-bit conditional branch sequences we |
0d986529 | 6323 | might need to generate. It handles nullification of delay slots, |
6324 | varying length branches, negated branches and all combinations of the | |
6325 | above. it returns the appropriate output template to emit the branch. */ | |
6326 | ||
611a88e1 | 6327 | const char * |
5c1d8983 | 6328 | output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length, |
6329 | int negated, rtx insn, int which) | |
29a4502c | 6330 | { |
0d986529 | 6331 | static char buf[100]; |
6332 | int useskip = 0; | |
6333 | ||
29a4502c | 6334 | /* A conditional branch to the following instruction (eg the delay slot) is |
6335 | asking for a disaster. I do not think this can happen as this pattern | |
6d36483b | 6336 | is only used when optimizing; jump optimization should eliminate the |
29a4502c | 6337 | jump. But be prepared just in case. */ |
6d36483b | 6338 | |
ece0fa59 | 6339 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6340 | return "nop"; | |
6d36483b | 6341 | |
5fbd5940 | 6342 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6343 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6344 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6345 | nullify = 1; |
6346 | ||
6347 | /* If this is a short forward conditional branch which did not get | |
6348 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6349 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6350 | nullify = forward_branch_p (insn); |
6351 | ||
6d36483b | 6352 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6353 | extrs instruction. This avoids a single cycle penalty due to |
6354 | mis-predicted branch if we fall through (branch not taken). */ | |
6355 | ||
5a1231ef | 6356 | if (length == 4 |
5fbd5940 | 6357 | && next_real_insn (insn) != 0 |
5a1231ef | 6358 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 6359 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 6360 | && nullify) |
6361 | useskip = 1; | |
6362 | ||
6363 | switch (length) | |
6364 | { | |
6365 | ||
5fbd5940 | 6366 | /* All short conditional branches except backwards with an unfilled |
6367 | delay slot. */ | |
5a1231ef | 6368 | case 4: |
0d986529 | 6369 | if (useskip) |
e4065f95 | 6370 | strcpy (buf, "{extrs,|extrw,s,}"); |
6d36483b | 6371 | else |
0d986529 | 6372 | strcpy (buf, "bb,"); |
5e3c5739 | 6373 | if (useskip && GET_MODE (operands[0]) == DImode) |
6374 | strcpy (buf, "extrd,s,*"); | |
6375 | else if (GET_MODE (operands[0]) == DImode) | |
6376 | strcpy (buf, "bb,*"); | |
0d986529 | 6377 | if ((which == 0 && negated) |
6378 | || (which == 1 && ! negated)) | |
6379 | strcat (buf, ">="); | |
6380 | else | |
6381 | strcat (buf, "<"); | |
6382 | if (useskip) | |
5a811d43 | 6383 | strcat (buf, " %0,%1,1,%%r0"); |
0d986529 | 6384 | else if (nullify && negated) |
6385 | strcat (buf, ",n %0,%1,%3"); | |
6386 | else if (nullify && ! negated) | |
6387 | strcat (buf, ",n %0,%1,%2"); | |
6388 | else if (! nullify && negated) | |
5fbd5940 | 6389 | strcat (buf, "%0,%1,%3"); |
0d986529 | 6390 | else if (! nullify && ! negated) |
5fbd5940 | 6391 | strcat (buf, " %0,%1,%2"); |
0d986529 | 6392 | break; |
6393 | ||
87fcb603 | 6394 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6395 | unfilled delay slot is treated just like a long backward branch |
6396 | with an unfilled delay slot. */ | |
5a1231ef | 6397 | case 8: |
5fbd5940 | 6398 | /* Handle weird backwards branch with a filled delay slot |
6399 | with is nullified. */ | |
6400 | if (dbr_sequence_length () != 0 | |
6401 | && ! forward_branch_p (insn) | |
6402 | && nullify) | |
6403 | { | |
6404 | strcpy (buf, "bb,"); | |
5e3c5739 | 6405 | if (GET_MODE (operands[0]) == DImode) |
6406 | strcat (buf, "*"); | |
5fbd5940 | 6407 | if ((which == 0 && negated) |
6408 | || (which == 1 && ! negated)) | |
6409 | strcat (buf, "<"); | |
6410 | else | |
6411 | strcat (buf, ">="); | |
6412 | if (negated) | |
5a811d43 | 6413 | strcat (buf, ",n %0,%1,.+12\n\tb %3"); |
5fbd5940 | 6414 | else |
5a811d43 | 6415 | strcat (buf, ",n %0,%1,.+12\n\tb %2"); |
5fbd5940 | 6416 | } |
43f0c1f2 | 6417 | /* Handle short backwards branch with an unfilled delay slot. |
6418 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6419 | taken and untaken branches. */ | |
6420 | else if (dbr_sequence_length () == 0 | |
6421 | && ! forward_branch_p (insn) | |
47fc0706 | 6422 | && INSN_ADDRESSES_SET_P () |
6423 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6424 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6425 | { |
6426 | strcpy (buf, "bb,"); | |
5e3c5739 | 6427 | if (GET_MODE (operands[0]) == DImode) |
6428 | strcat (buf, "*"); | |
43f0c1f2 | 6429 | if ((which == 0 && negated) |
6430 | || (which == 1 && ! negated)) | |
6431 | strcat (buf, ">="); | |
6432 | else | |
6433 | strcat (buf, "<"); | |
6434 | if (negated) | |
6435 | strcat (buf, " %0,%1,%3%#"); | |
6436 | else | |
6437 | strcat (buf, " %0,%1,%2%#"); | |
6438 | } | |
0d986529 | 6439 | else |
5fbd5940 | 6440 | { |
e4065f95 | 6441 | strcpy (buf, "{extrs,|extrw,s,}"); |
5e3c5739 | 6442 | if (GET_MODE (operands[0]) == DImode) |
6443 | strcpy (buf, "extrd,s,*"); | |
5fbd5940 | 6444 | if ((which == 0 && negated) |
6445 | || (which == 1 && ! negated)) | |
6446 | strcat (buf, "<"); | |
6447 | else | |
6448 | strcat (buf, ">="); | |
6449 | if (nullify && negated) | |
c6ae275c | 6450 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %3"); |
5fbd5940 | 6451 | else if (nullify && ! negated) |
c6ae275c | 6452 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %2"); |
5fbd5940 | 6453 | else if (negated) |
5a811d43 | 6454 | strcat (buf, " %0,%1,1,%%r0\n\tb %3"); |
6d36483b | 6455 | else |
5a811d43 | 6456 | strcat (buf, " %0,%1,1,%%r0\n\tb %2"); |
5fbd5940 | 6457 | } |
0d986529 | 6458 | break; |
6459 | ||
6460 | default: | |
ea52c577 | 6461 | abort (); |
5fbd5940 | 6462 | } |
0d986529 | 6463 | return buf; |
6464 | } | |
6465 | ||
c7a4e712 | 6466 | /* This routine handles all the branch-on-variable-bit conditional branch |
6467 | sequences we might need to generate. It handles nullification of delay | |
6468 | slots, varying length branches, negated branches and all combinations | |
6469 | of the above. it returns the appropriate output template to emit the | |
6470 | branch. */ | |
6471 | ||
611a88e1 | 6472 | const char * |
5c1d8983 | 6473 | output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length, |
6474 | int negated, rtx insn, int which) | |
c7a4e712 | 6475 | { |
6476 | static char buf[100]; | |
6477 | int useskip = 0; | |
6478 | ||
6479 | /* A conditional branch to the following instruction (eg the delay slot) is | |
6480 | asking for a disaster. I do not think this can happen as this pattern | |
6481 | is only used when optimizing; jump optimization should eliminate the | |
6482 | jump. But be prepared just in case. */ | |
6483 | ||
ece0fa59 | 6484 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6485 | return "nop"; | |
c7a4e712 | 6486 | |
6487 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6488 | as it can nullify the delay slot and save a nop. */ | |
6489 | if (length == 8 && dbr_sequence_length () == 0) | |
6490 | nullify = 1; | |
6491 | ||
6492 | /* If this is a short forward conditional branch which did not get | |
6493 | its delay slot filled, the delay slot can still be nullified. */ | |
6494 | if (! nullify && length == 4 && dbr_sequence_length () == 0) | |
6495 | nullify = forward_branch_p (insn); | |
6496 | ||
6497 | /* A forward branch over a single nullified insn can be done with a | |
6498 | extrs instruction. This avoids a single cycle penalty due to | |
6499 | mis-predicted branch if we fall through (branch not taken). */ | |
6500 | ||
6501 | if (length == 4 | |
6502 | && next_real_insn (insn) != 0 | |
6503 | && get_attr_length (next_real_insn (insn)) == 4 | |
6504 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) | |
6505 | && nullify) | |
6506 | useskip = 1; | |
6507 | ||
6508 | switch (length) | |
6509 | { | |
6510 | ||
6511 | /* All short conditional branches except backwards with an unfilled | |
6512 | delay slot. */ | |
6513 | case 4: | |
6514 | if (useskip) | |
e4065f95 | 6515 | strcpy (buf, "{vextrs,|extrw,s,}"); |
c7a4e712 | 6516 | else |
e4065f95 | 6517 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6518 | if (useskip && GET_MODE (operands[0]) == DImode) |
e75269fd | 6519 | strcpy (buf, "extrd,s,*"); |
5e3c5739 | 6520 | else if (GET_MODE (operands[0]) == DImode) |
6521 | strcpy (buf, "bb,*"); | |
c7a4e712 | 6522 | if ((which == 0 && negated) |
6523 | || (which == 1 && ! negated)) | |
6524 | strcat (buf, ">="); | |
6525 | else | |
6526 | strcat (buf, "<"); | |
6527 | if (useskip) | |
e4065f95 | 6528 | strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}"); |
c7a4e712 | 6529 | else if (nullify && negated) |
e4065f95 | 6530 | strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}"); |
c7a4e712 | 6531 | else if (nullify && ! negated) |
e4065f95 | 6532 | strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}"); |
c7a4e712 | 6533 | else if (! nullify && negated) |
e4065f95 | 6534 | strcat (buf, "{%0,%3|%0,%%sar,%3}"); |
c7a4e712 | 6535 | else if (! nullify && ! negated) |
e4065f95 | 6536 | strcat (buf, "{ %0,%2| %0,%%sar,%2}"); |
c7a4e712 | 6537 | break; |
6538 | ||
87fcb603 | 6539 | /* All long conditionals. Note a short backward branch with an |
c7a4e712 | 6540 | unfilled delay slot is treated just like a long backward branch |
6541 | with an unfilled delay slot. */ | |
6542 | case 8: | |
6543 | /* Handle weird backwards branch with a filled delay slot | |
6544 | with is nullified. */ | |
6545 | if (dbr_sequence_length () != 0 | |
6546 | && ! forward_branch_p (insn) | |
6547 | && nullify) | |
6548 | { | |
e4065f95 | 6549 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6550 | if (GET_MODE (operands[0]) == DImode) |
6551 | strcat (buf, "*"); | |
c7a4e712 | 6552 | if ((which == 0 && negated) |
6553 | || (which == 1 && ! negated)) | |
6554 | strcat (buf, "<"); | |
6555 | else | |
6556 | strcat (buf, ">="); | |
6557 | if (negated) | |
e4065f95 | 6558 | strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}"); |
c7a4e712 | 6559 | else |
e4065f95 | 6560 | strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}"); |
c7a4e712 | 6561 | } |
6562 | /* Handle short backwards branch with an unfilled delay slot. | |
6563 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6564 | taken and untaken branches. */ | |
6565 | else if (dbr_sequence_length () == 0 | |
6566 | && ! forward_branch_p (insn) | |
47fc0706 | 6567 | && INSN_ADDRESSES_SET_P () |
6568 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6569 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
c7a4e712 | 6570 | { |
e4065f95 | 6571 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6572 | if (GET_MODE (operands[0]) == DImode) |
6573 | strcat (buf, "*"); | |
c7a4e712 | 6574 | if ((which == 0 && negated) |
6575 | || (which == 1 && ! negated)) | |
6576 | strcat (buf, ">="); | |
6577 | else | |
6578 | strcat (buf, "<"); | |
6579 | if (negated) | |
e4065f95 | 6580 | strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}"); |
c7a4e712 | 6581 | else |
e4065f95 | 6582 | strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}"); |
c7a4e712 | 6583 | } |
6584 | else | |
6585 | { | |
e4065f95 | 6586 | strcpy (buf, "{vextrs,|extrw,s,}"); |
5e3c5739 | 6587 | if (GET_MODE (operands[0]) == DImode) |
6588 | strcpy (buf, "extrd,s,*"); | |
c7a4e712 | 6589 | if ((which == 0 && negated) |
6590 | || (which == 1 && ! negated)) | |
6591 | strcat (buf, "<"); | |
6592 | else | |
6593 | strcat (buf, ">="); | |
6594 | if (nullify && negated) | |
e4065f95 | 6595 | strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}"); |
c7a4e712 | 6596 | else if (nullify && ! negated) |
e4065f95 | 6597 | strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}"); |
c7a4e712 | 6598 | else if (negated) |
e4065f95 | 6599 | strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}"); |
c7a4e712 | 6600 | else |
e4065f95 | 6601 | strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}"); |
c7a4e712 | 6602 | } |
6603 | break; | |
6604 | ||
6605 | default: | |
ea52c577 | 6606 | abort (); |
c7a4e712 | 6607 | } |
6608 | return buf; | |
6609 | } | |
6610 | ||
29a4502c | 6611 | /* Return the output template for emitting a dbra type insn. |
6612 | ||
6613 | Note it may perform some output operations on its own before | |
6614 | returning the final output string. */ | |
611a88e1 | 6615 | const char * |
5c1d8983 | 6616 | output_dbra (rtx *operands, rtx insn, int which_alternative) |
29a4502c | 6617 | { |
6618 | ||
6619 | /* A conditional branch to the following instruction (eg the delay slot) is | |
6620 | asking for a disaster. Be prepared! */ | |
6621 | ||
ece0fa59 | 6622 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
29a4502c | 6623 | { |
6624 | if (which_alternative == 0) | |
6625 | return "ldo %1(%0),%0"; | |
6626 | else if (which_alternative == 1) | |
6627 | { | |
ea52c577 | 6628 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands); |
6629 | output_asm_insn ("ldw -16(%%r30),%4", operands); | |
34940871 | 6630 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
e4065f95 | 6631 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6632 | } |
6633 | else | |
6634 | { | |
6635 | output_asm_insn ("ldw %0,%4", operands); | |
6636 | return "ldo %1(%4),%4\n\tstw %4,%0"; | |
6637 | } | |
6638 | } | |
6639 | ||
6640 | if (which_alternative == 0) | |
6641 | { | |
6642 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
6643 | int length = get_attr_length (insn); | |
6644 | ||
6645 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6646 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6647 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 6648 | nullify = 1; |
6649 | ||
6650 | /* If this is a short forward conditional branch which did not get | |
6651 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6652 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 6653 | nullify = forward_branch_p (insn); |
6654 | ||
6655 | /* Handle short versions first. */ | |
5a1231ef | 6656 | if (length == 4 && nullify) |
29a4502c | 6657 | return "addib,%C2,n %1,%0,%3"; |
5a1231ef | 6658 | else if (length == 4 && ! nullify) |
29a4502c | 6659 | return "addib,%C2 %1,%0,%3"; |
5a1231ef | 6660 | else if (length == 8) |
29a4502c | 6661 | { |
6d36483b | 6662 | /* Handle weird backwards branch with a fulled delay slot |
29a4502c | 6663 | which is nullified. */ |
6664 | if (dbr_sequence_length () != 0 | |
6665 | && ! forward_branch_p (insn) | |
6666 | && nullify) | |
5a811d43 | 6667 | return "addib,%N2,n %1,%0,.+12\n\tb %3"; |
43f0c1f2 | 6668 | /* Handle short backwards branch with an unfilled delay slot. |
6669 | Using a addb;nop rather than addi;bl saves 1 cycle for both | |
6670 | taken and untaken branches. */ | |
6671 | else if (dbr_sequence_length () == 0 | |
6672 | && ! forward_branch_p (insn) | |
47fc0706 | 6673 | && INSN_ADDRESSES_SET_P () |
6674 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6675 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6676 | return "addib,%C2 %1,%0,%3%#"; |
6d36483b | 6677 | |
6678 | /* Handle normal cases. */ | |
29a4502c | 6679 | if (nullify) |
5a811d43 | 6680 | return "addi,%N2 %1,%0,%0\n\tb,n %3"; |
29a4502c | 6681 | else |
5a811d43 | 6682 | return "addi,%N2 %1,%0,%0\n\tb %3"; |
29a4502c | 6683 | } |
6684 | else | |
ea52c577 | 6685 | abort (); |
29a4502c | 6686 | } |
6687 | /* Deal with gross reload from FP register case. */ | |
6688 | else if (which_alternative == 1) | |
6689 | { | |
6690 | /* Move loop counter from FP register to MEM then into a GR, | |
6691 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 6692 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 6693 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4", |
6694 | operands); | |
34940871 | 6695 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
5a1231ef | 6696 | if (get_attr_length (insn) == 24) |
e4065f95 | 6697 | return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6698 | else |
e4065f95 | 6699 | return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6700 | } |
6701 | /* Deal with gross reload from memory case. */ | |
6702 | else | |
6703 | { | |
6704 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 6705 | happens in the branch's delay slot. */ |
29a4502c | 6706 | output_asm_insn ("ldw %0,%4", operands); |
5a1231ef | 6707 | if (get_attr_length (insn) == 12) |
29a4502c | 6708 | return "addib,%C2 %1,%4,%3\n\tstw %4,%0"; |
6709 | else | |
5a811d43 | 6710 | return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0"; |
29a4502c | 6711 | } |
6712 | } | |
6713 | ||
6714 | /* Return the output template for emitting a dbra type insn. | |
6715 | ||
6716 | Note it may perform some output operations on its own before | |
6717 | returning the final output string. */ | |
611a88e1 | 6718 | const char * |
5c1d8983 | 6719 | output_movb (rtx *operands, rtx insn, int which_alternative, |
6720 | int reverse_comparison) | |
29a4502c | 6721 | { |
6722 | ||
6723 | /* A conditional branch to the following instruction (eg the delay slot) is | |
6724 | asking for a disaster. Be prepared! */ | |
6725 | ||
ece0fa59 | 6726 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
29a4502c | 6727 | { |
6728 | if (which_alternative == 0) | |
6729 | return "copy %1,%0"; | |
6730 | else if (which_alternative == 1) | |
6731 | { | |
ea52c577 | 6732 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
e4065f95 | 6733 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6734 | } |
546a40bd | 6735 | else if (which_alternative == 2) |
29a4502c | 6736 | return "stw %1,%0"; |
546a40bd | 6737 | else |
6738 | return "mtsar %r1"; | |
29a4502c | 6739 | } |
6740 | ||
6741 | /* Support the second variant. */ | |
6742 | if (reverse_comparison) | |
6743 | PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2]))); | |
6744 | ||
6745 | if (which_alternative == 0) | |
6746 | { | |
6747 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
6748 | int length = get_attr_length (insn); | |
6749 | ||
6750 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6751 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6752 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 6753 | nullify = 1; |
6754 | ||
6755 | /* If this is a short forward conditional branch which did not get | |
6756 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6757 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 6758 | nullify = forward_branch_p (insn); |
6759 | ||
6760 | /* Handle short versions first. */ | |
5a1231ef | 6761 | if (length == 4 && nullify) |
29a4502c | 6762 | return "movb,%C2,n %1,%0,%3"; |
5a1231ef | 6763 | else if (length == 4 && ! nullify) |
29a4502c | 6764 | return "movb,%C2 %1,%0,%3"; |
5a1231ef | 6765 | else if (length == 8) |
29a4502c | 6766 | { |
6d36483b | 6767 | /* Handle weird backwards branch with a filled delay slot |
29a4502c | 6768 | which is nullified. */ |
6769 | if (dbr_sequence_length () != 0 | |
6770 | && ! forward_branch_p (insn) | |
6771 | && nullify) | |
5a811d43 | 6772 | return "movb,%N2,n %1,%0,.+12\n\tb %3"; |
6d36483b | 6773 | |
43f0c1f2 | 6774 | /* Handle short backwards branch with an unfilled delay slot. |
6775 | Using a movb;nop rather than or;bl saves 1 cycle for both | |
6776 | taken and untaken branches. */ | |
6777 | else if (dbr_sequence_length () == 0 | |
6778 | && ! forward_branch_p (insn) | |
47fc0706 | 6779 | && INSN_ADDRESSES_SET_P () |
6780 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6781 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6782 | return "movb,%C2 %1,%0,%3%#"; |
6d36483b | 6783 | /* Handle normal cases. */ |
29a4502c | 6784 | if (nullify) |
5a811d43 | 6785 | return "or,%N2 %1,%%r0,%0\n\tb,n %3"; |
29a4502c | 6786 | else |
5a811d43 | 6787 | return "or,%N2 %1,%%r0,%0\n\tb %3"; |
29a4502c | 6788 | } |
6789 | else | |
ea52c577 | 6790 | abort (); |
29a4502c | 6791 | } |
6792 | /* Deal with gross reload from FP register case. */ | |
6793 | else if (which_alternative == 1) | |
6794 | { | |
6795 | /* Move loop counter from FP register to MEM then into a GR, | |
6796 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 6797 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 6798 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
5a1231ef | 6799 | if (get_attr_length (insn) == 12) |
e4065f95 | 6800 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6801 | else |
e4065f95 | 6802 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6803 | } |
6804 | /* Deal with gross reload from memory case. */ | |
546a40bd | 6805 | else if (which_alternative == 2) |
29a4502c | 6806 | { |
6807 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 6808 | happens in the branch's delay slot. */ |
5a1231ef | 6809 | if (get_attr_length (insn) == 8) |
e4065f95 | 6810 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0"; |
29a4502c | 6811 | else |
e4065f95 | 6812 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0"; |
29a4502c | 6813 | } |
546a40bd | 6814 | /* Handle SAR as a destination. */ |
6815 | else | |
6816 | { | |
6817 | if (get_attr_length (insn) == 8) | |
e4065f95 | 6818 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1"; |
546a40bd | 6819 | else |
e4065f95 | 6820 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1"; |
546a40bd | 6821 | } |
29a4502c | 6822 | } |
6823 | ||
ece88821 | 6824 | /* Copy any FP arguments in INSN into integer registers. */ |
6825 | static void | |
5c1d8983 | 6826 | copy_fp_args (rtx insn) |
ece88821 | 6827 | { |
6828 | rtx link; | |
6829 | rtx xoperands[2]; | |
29a4502c | 6830 | |
ece88821 | 6831 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
6832 | { | |
6833 | int arg_mode, regno; | |
6834 | rtx use = XEXP (link, 0); | |
3683f840 | 6835 | |
ece88821 | 6836 | if (! (GET_CODE (use) == USE |
6837 | && GET_CODE (XEXP (use, 0)) == REG | |
6838 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
6839 | continue; | |
d6686e21 | 6840 | |
ece88821 | 6841 | arg_mode = GET_MODE (XEXP (use, 0)); |
6842 | regno = REGNO (XEXP (use, 0)); | |
5e3c5739 | 6843 | |
ece88821 | 6844 | /* Is it a floating point register? */ |
6845 | if (regno >= 32 && regno <= 39) | |
6846 | { | |
6847 | /* Copy the FP register into an integer register via memory. */ | |
6848 | if (arg_mode == SFmode) | |
6849 | { | |
6850 | xoperands[0] = XEXP (use, 0); | |
6851 | xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2); | |
6852 | output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands); | |
6853 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
6854 | } | |
6855 | else | |
6856 | { | |
6857 | xoperands[0] = XEXP (use, 0); | |
6858 | xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2); | |
6859 | output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands); | |
6860 | output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands); | |
6861 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
6862 | } | |
6863 | } | |
06ddb6f8 | 6864 | } |
ece88821 | 6865 | } |
6866 | ||
6867 | /* Compute length of the FP argument copy sequence for INSN. */ | |
6868 | static int | |
5c1d8983 | 6869 | length_fp_args (rtx insn) |
ece88821 | 6870 | { |
6871 | int length = 0; | |
6872 | rtx link; | |
06ddb6f8 | 6873 | |
ece88821 | 6874 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
c7a4e712 | 6875 | { |
ece88821 | 6876 | int arg_mode, regno; |
6877 | rtx use = XEXP (link, 0); | |
6878 | ||
6879 | if (! (GET_CODE (use) == USE | |
6880 | && GET_CODE (XEXP (use, 0)) == REG | |
6881 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
6882 | continue; | |
c7a4e712 | 6883 | |
ece88821 | 6884 | arg_mode = GET_MODE (XEXP (use, 0)); |
6885 | regno = REGNO (XEXP (use, 0)); | |
6886 | ||
6887 | /* Is it a floating point register? */ | |
6888 | if (regno >= 32 && regno <= 39) | |
c7a4e712 | 6889 | { |
ece88821 | 6890 | if (arg_mode == SFmode) |
6891 | length += 8; | |
6892 | else | |
6893 | length += 12; | |
c7a4e712 | 6894 | } |
ece88821 | 6895 | } |
c7a4e712 | 6896 | |
ece88821 | 6897 | return length; |
6898 | } | |
b70ea764 | 6899 | |
cd0dfcc5 | 6900 | /* Return the attribute length for the millicode call instruction INSN. |
6901 | The length must match the code generated by output_millicode_call. | |
6902 | We include the delay slot in the returned length as it is better to | |
ece88821 | 6903 | over estimate the length than to under estimate it. */ |
b29897dd | 6904 | |
ece88821 | 6905 | int |
5c1d8983 | 6906 | attr_length_millicode_call (rtx insn) |
ece88821 | 6907 | { |
cd0dfcc5 | 6908 | unsigned long distance = -1; |
8a05c3c2 | 6909 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
ece88821 | 6910 | |
cd0dfcc5 | 6911 | if (INSN_ADDRESSES_SET_P ()) |
6912 | { | |
2247cc5f | 6913 | distance = (total + insn_current_reference_address (insn)); |
6914 | if (distance < total) | |
cd0dfcc5 | 6915 | distance = -1; |
6916 | } | |
ece88821 | 6917 | |
6918 | if (TARGET_64BIT) | |
6919 | { | |
6920 | if (!TARGET_LONG_CALLS && distance < 7600000) | |
cd0dfcc5 | 6921 | return 8; |
ece88821 | 6922 | |
cd0dfcc5 | 6923 | return 20; |
ece88821 | 6924 | } |
6925 | else if (TARGET_PORTABLE_RUNTIME) | |
cd0dfcc5 | 6926 | return 24; |
ece88821 | 6927 | else |
6928 | { | |
6929 | if (!TARGET_LONG_CALLS && distance < 240000) | |
cd0dfcc5 | 6930 | return 8; |
ece88821 | 6931 | |
6932 | if (TARGET_LONG_ABS_CALL && !flag_pic) | |
cd0dfcc5 | 6933 | return 12; |
ece88821 | 6934 | |
cd0dfcc5 | 6935 | return 24; |
ece88821 | 6936 | } |
6937 | } | |
6938 | ||
6939 | /* INSN is a function call. It may have an unconditional jump | |
6940 | in its delay slot. | |
b29897dd | 6941 | |
ece88821 | 6942 | CALL_DEST is the routine we are calling. */ |
b29897dd | 6943 | |
ece88821 | 6944 | const char * |
5c1d8983 | 6945 | output_millicode_call (rtx insn, rtx call_dest) |
ece88821 | 6946 | { |
6947 | int attr_length = get_attr_length (insn); | |
6948 | int seq_length = dbr_sequence_length (); | |
6949 | int distance; | |
6950 | rtx seq_insn; | |
6951 | rtx xoperands[3]; | |
b29897dd | 6952 | |
ece88821 | 6953 | xoperands[0] = call_dest; |
6954 | xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31); | |
6955 | ||
6956 | /* Handle the common case where we are sure that the branch will | |
6957 | reach the beginning of the $CODE$ subspace. The within reach | |
6958 | form of the $$sh_func_adrs call has a length of 28. Because | |
a8b24921 | 6959 | it has an attribute type of multi, it never has a nonzero |
ece88821 | 6960 | sequence length. The length of the $$sh_func_adrs is the same |
6961 | as certain out of reach PIC calls to other routines. */ | |
6962 | if (!TARGET_LONG_CALLS | |
6963 | && ((seq_length == 0 | |
6964 | && (attr_length == 12 | |
6965 | || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI))) | |
6966 | || (seq_length != 0 && attr_length == 8))) | |
6967 | { | |
6968 | output_asm_insn ("{bl|b,l} %0,%2", xoperands); | |
6969 | } | |
6970 | else | |
6971 | { | |
6972 | if (TARGET_64BIT) | |
6973 | { | |
6974 | /* It might seem that one insn could be saved by accessing | |
6975 | the millicode function using the linkage table. However, | |
6976 | this doesn't work in shared libraries and other dynamically | |
6977 | loaded objects. Using a pc-relative sequence also avoids | |
6978 | problems related to the implicit use of the gp register. */ | |
6979 | output_asm_insn ("b,l .+8,%%r1", xoperands); | |
9bd9af5d | 6980 | |
6981 | if (TARGET_GAS) | |
6982 | { | |
6983 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6984 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6985 | } | |
6986 | else | |
6987 | { | |
6988 | xoperands[1] = gen_label_rtx (); | |
6989 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
805e22b2 | 6990 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
9bd9af5d | 6991 | CODE_LABEL_NUMBER (xoperands[1])); |
6992 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
6993 | } | |
6994 | ||
ece88821 | 6995 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); |
c7a4e712 | 6996 | } |
c7a4e712 | 6997 | else if (TARGET_PORTABLE_RUNTIME) |
6998 | { | |
ece88821 | 6999 | /* Pure portable runtime doesn't allow be/ble; we also don't |
7000 | have PIC support in the assembler/linker, so this sequence | |
7001 | is needed. */ | |
c7a4e712 | 7002 | |
ece88821 | 7003 | /* Get the address of our target into %r1. */ |
7004 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
7005 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
c7a4e712 | 7006 | |
ece88821 | 7007 | /* Get our return address into %r31. */ |
7008 | output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands); | |
7009 | output_asm_insn ("addi 8,%%r31,%%r31", xoperands); | |
c7a4e712 | 7010 | |
ece88821 | 7011 | /* Jump to our target address in %r1. */ |
7012 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 7013 | } |
ece88821 | 7014 | else if (!flag_pic) |
c7a4e712 | 7015 | { |
ece88821 | 7016 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
356267e0 | 7017 | if (TARGET_PA_20) |
ece88821 | 7018 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands); |
356267e0 | 7019 | else |
ece88821 | 7020 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); |
c7a4e712 | 7021 | } |
ece88821 | 7022 | else |
c7a4e712 | 7023 | { |
9bd9af5d | 7024 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
7025 | output_asm_insn ("addi 16,%%r1,%%r31", xoperands); | |
7026 | ||
ece88821 | 7027 | if (TARGET_SOM || !TARGET_GAS) |
7028 | { | |
7029 | /* The HP assembler can generate relocations for the | |
7030 | difference of two symbols. GAS can do this for a | |
7031 | millicode symbol but not an arbitrary external | |
7032 | symbol when generating SOM output. */ | |
7033 | xoperands[1] = gen_label_rtx (); | |
805e22b2 | 7034 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
ece88821 | 7035 | CODE_LABEL_NUMBER (xoperands[1])); |
7036 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
7037 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
7038 | } | |
7039 | else | |
7040 | { | |
ece88821 | 7041 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands); |
7042 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1", | |
7043 | xoperands); | |
7044 | } | |
c7a4e712 | 7045 | |
ece88821 | 7046 | /* Jump to our target address in %r1. */ |
7047 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 7048 | } |
c7a4e712 | 7049 | } |
7050 | ||
ece88821 | 7051 | if (seq_length == 0) |
7052 | output_asm_insn ("nop", xoperands); | |
c7a4e712 | 7053 | |
ece88821 | 7054 | /* We are done if there isn't a jump in the delay slot. */ |
7055 | if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7056 | return ""; | |
c7a4e712 | 7057 | |
ece88821 | 7058 | /* This call has an unconditional jump in its delay slot. */ |
7059 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
c7a4e712 | 7060 | |
ece88821 | 7061 | /* See if the return address can be adjusted. Use the containing |
7062 | sequence insn's address. */ | |
cd0dfcc5 | 7063 | if (INSN_ADDRESSES_SET_P ()) |
c7a4e712 | 7064 | { |
cd0dfcc5 | 7065 | seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); |
7066 | distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7067 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7068 | ||
7069 | if (VAL_14_BITS_P (distance)) | |
7070 | { | |
7071 | xoperands[1] = gen_label_rtx (); | |
7072 | output_asm_insn ("ldo %0-%1(%2),%2", xoperands); | |
7073 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
7074 | CODE_LABEL_NUMBER (xoperands[1])); | |
7075 | } | |
7076 | else | |
7077 | /* ??? This branch may not reach its target. */ | |
7078 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 7079 | } |
ece88821 | 7080 | else |
7081 | /* ??? This branch may not reach its target. */ | |
7082 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 7083 | |
7084 | /* Delete the jump. */ | |
7085 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7086 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7087 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
ece88821 | 7088 | |
c7a4e712 | 7089 | return ""; |
7090 | } | |
7091 | ||
cd0dfcc5 | 7092 | /* Return the attribute length of the call instruction INSN. The SIBCALL |
7093 | flag indicates whether INSN is a regular call or a sibling call. The | |
faf3f8c1 | 7094 | length returned must be longer than the code actually generated by |
7095 | output_call. Since branch shortening is done before delay branch | |
7096 | sequencing, there is no way to determine whether or not the delay | |
7097 | slot will be filled during branch shortening. Even when the delay | |
7098 | slot is filled, we may have to add a nop if the delay slot contains | |
7099 | a branch that can't reach its target. Thus, we always have to include | |
7100 | the delay slot in the length estimate. This used to be done in | |
7101 | pa_adjust_insn_length but we do it here now as some sequences always | |
7102 | fill the delay slot and we can save four bytes in the estimate for | |
7103 | these sequences. */ | |
ece88821 | 7104 | |
7105 | int | |
5c1d8983 | 7106 | attr_length_call (rtx insn, int sibcall) |
ece88821 | 7107 | { |
faf3f8c1 | 7108 | int local_call; |
7109 | rtx call_dest; | |
7110 | tree call_decl; | |
7111 | int length = 0; | |
7112 | rtx pat = PATTERN (insn); | |
cd0dfcc5 | 7113 | unsigned long distance = -1; |
ece88821 | 7114 | |
cd0dfcc5 | 7115 | if (INSN_ADDRESSES_SET_P ()) |
7116 | { | |
faf3f8c1 | 7117 | unsigned long total; |
7118 | ||
7119 | total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; | |
2247cc5f | 7120 | distance = (total + insn_current_reference_address (insn)); |
7121 | if (distance < total) | |
cd0dfcc5 | 7122 | distance = -1; |
7123 | } | |
ece88821 | 7124 | |
faf3f8c1 | 7125 | /* Determine if this is a local call. */ |
7126 | if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL) | |
7127 | call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0); | |
ece88821 | 7128 | else |
faf3f8c1 | 7129 | call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0); |
ece88821 | 7130 | |
faf3f8c1 | 7131 | call_decl = SYMBOL_REF_DECL (call_dest); |
7132 | local_call = call_decl && (*targetm.binds_local_p) (call_decl); | |
ece88821 | 7133 | |
faf3f8c1 | 7134 | /* pc-relative branch. */ |
7135 | if (!TARGET_LONG_CALLS | |
7136 | && ((TARGET_PA_20 && !sibcall && distance < 7600000) | |
7137 | || distance < 240000)) | |
7138 | length += 8; | |
ece88821 | 7139 | |
faf3f8c1 | 7140 | /* 64-bit plabel sequence. */ |
7141 | else if (TARGET_64BIT && !local_call) | |
7142 | length += sibcall ? 28 : 24; | |
ece88821 | 7143 | |
faf3f8c1 | 7144 | /* non-pic long absolute branch sequence. */ |
7145 | else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) | |
7146 | length += 12; | |
ece88821 | 7147 | |
faf3f8c1 | 7148 | /* long pc-relative branch sequence. */ |
7149 | else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) | |
7150 | || (TARGET_64BIT && !TARGET_GAS) | |
7151 | || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))) | |
7152 | { | |
7153 | length += 20; | |
ece88821 | 7154 | |
faf3f8c1 | 7155 | if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS) |
7156 | length += 8; | |
7157 | } | |
8a05c3c2 | 7158 | |
faf3f8c1 | 7159 | /* 32-bit plabel sequence. */ |
7160 | else | |
7161 | { | |
7162 | length += 32; | |
ece88821 | 7163 | |
faf3f8c1 | 7164 | if (TARGET_SOM) |
7165 | length += length_fp_args (insn); | |
7166 | ||
7167 | if (flag_pic) | |
7168 | length += 4; | |
ee376abe | 7169 | |
faf3f8c1 | 7170 | if (!TARGET_PA_20) |
7171 | { | |
ece88821 | 7172 | if (!sibcall) |
7173 | length += 8; | |
7174 | ||
faf3f8c1 | 7175 | if (!TARGET_NO_SPACE_REGS) |
7176 | length += 8; | |
ece88821 | 7177 | } |
7178 | } | |
faf3f8c1 | 7179 | |
7180 | return length; | |
ece88821 | 7181 | } |
7182 | ||
7183 | /* INSN is a function call. It may have an unconditional jump | |
c7a4e712 | 7184 | in its delay slot. |
7185 | ||
7186 | CALL_DEST is the routine we are calling. */ | |
7187 | ||
611a88e1 | 7188 | const char * |
5c1d8983 | 7189 | output_call (rtx insn, rtx call_dest, int sibcall) |
c7a4e712 | 7190 | { |
ece88821 | 7191 | int delay_insn_deleted = 0; |
7192 | int delay_slot_filled = 0; | |
b70ea764 | 7193 | int seq_length = dbr_sequence_length (); |
2247cc5f | 7194 | tree call_decl = SYMBOL_REF_DECL (call_dest); |
faf3f8c1 | 7195 | int local_call = call_decl && (*targetm.binds_local_p) (call_decl); |
ece88821 | 7196 | rtx xoperands[2]; |
7197 | ||
7198 | xoperands[0] = call_dest; | |
c7a4e712 | 7199 | |
ece88821 | 7200 | /* Handle the common case where we're sure that the branch will reach |
2247cc5f | 7201 | the beginning of the "$CODE$" subspace. This is the beginning of |
7202 | the current function if we are in a named section. */ | |
cd0dfcc5 | 7203 | if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8) |
d6686e21 | 7204 | { |
5e3c5739 | 7205 | xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2); |
ece88821 | 7206 | output_asm_insn ("{bl|b,l} %0,%1", xoperands); |
06ddb6f8 | 7207 | } |
ece88821 | 7208 | else |
06ddb6f8 | 7209 | { |
2247cc5f | 7210 | if (TARGET_64BIT && !local_call) |
3683f840 | 7211 | { |
ece88821 | 7212 | /* ??? As far as I can tell, the HP linker doesn't support the |
7213 | long pc-relative sequence described in the 64-bit runtime | |
7214 | architecture. So, we use a slightly longer indirect call. */ | |
7215 | struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0)); | |
7216 | ||
7217 | xoperands[0] = p->internal_label; | |
7218 | xoperands[1] = gen_label_rtx (); | |
7219 | ||
7220 | /* If this isn't a sibcall, we put the load of %r27 into the | |
7221 | delay slot. We can't do this in a sibcall as we don't | |
7222 | have a second call-clobbered scratch register available. */ | |
7223 | if (seq_length != 0 | |
7224 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7225 | && !sibcall) | |
7226 | { | |
7227 | final_scan_insn (NEXT_INSN (insn), asm_out_file, | |
fbf5169c | 7228 | optimize, 0, 0, NULL); |
ece88821 | 7229 | |
7230 | /* Now delete the delay insn. */ | |
7231 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7232 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7233 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
7234 | delay_insn_deleted = 1; | |
7235 | } | |
06ddb6f8 | 7236 | |
ece88821 | 7237 | output_asm_insn ("addil LT'%0,%%r27", xoperands); |
7238 | output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands); | |
7239 | output_asm_insn ("ldd 0(%%r1),%%r1", xoperands); | |
06ddb6f8 | 7240 | |
ece88821 | 7241 | if (sibcall) |
06ddb6f8 | 7242 | { |
ece88821 | 7243 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); |
7244 | output_asm_insn ("ldd 16(%%r1),%%r1", xoperands); | |
7245 | output_asm_insn ("bve (%%r1)", xoperands); | |
7246 | } | |
7247 | else | |
7248 | { | |
7249 | output_asm_insn ("ldd 16(%%r1),%%r2", xoperands); | |
7250 | output_asm_insn ("bve,l (%%r2),%%r2", xoperands); | |
7251 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); | |
7252 | delay_slot_filled = 1; | |
06ddb6f8 | 7253 | } |
7254 | } | |
ece88821 | 7255 | else |
e3f53689 | 7256 | { |
ece88821 | 7257 | int indirect_call = 0; |
7258 | ||
7259 | /* Emit a long call. There are several different sequences | |
7260 | of increasing length and complexity. In most cases, | |
7261 | they don't allow an instruction in the delay slot. */ | |
2247cc5f | 7262 | if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
ece88821 | 7263 | && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) |
2247cc5f | 7264 | && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)) |
7265 | && !TARGET_64BIT) | |
ece88821 | 7266 | indirect_call = 1; |
7267 | ||
7268 | if (seq_length != 0 | |
7269 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7270 | && !sibcall | |
7271 | && (!TARGET_PA_20 || indirect_call)) | |
5cc6b2bc | 7272 | { |
ece88821 | 7273 | /* A non-jump insn in the delay slot. By definition we can |
7274 | emit this insn before the call (and in fact before argument | |
7275 | relocating. */ | |
fbf5169c | 7276 | final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0, |
7277 | NULL); | |
ece88821 | 7278 | |
7279 | /* Now delete the delay insn. */ | |
7280 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7281 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7282 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
7283 | delay_insn_deleted = 1; | |
5cc6b2bc | 7284 | } |
e3f53689 | 7285 | |
2247cc5f | 7286 | if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
5cc6b2bc | 7287 | { |
ece88821 | 7288 | /* This is the best sequence for making long calls in |
7289 | non-pic code. Unfortunately, GNU ld doesn't provide | |
7290 | the stub needed for external calls, and GAS's support | |
2247cc5f | 7291 | for this with the SOM linker is buggy. It is safe |
7292 | to use this for local calls. */ | |
ece88821 | 7293 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
7294 | if (sibcall) | |
7295 | output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands); | |
7296 | else | |
7297 | { | |
7298 | if (TARGET_PA_20) | |
7299 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", | |
7300 | xoperands); | |
7301 | else | |
7302 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); | |
c7a4e712 | 7303 | |
ece88821 | 7304 | output_asm_insn ("copy %%r31,%%r2", xoperands); |
7305 | delay_slot_filled = 1; | |
7306 | } | |
7307 | } | |
7308 | else | |
7309 | { | |
2247cc5f | 7310 | if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) |
7311 | || (TARGET_64BIT && !TARGET_GAS)) | |
b70ea764 | 7312 | { |
ece88821 | 7313 | /* The HP assembler and linker can handle relocations |
7314 | for the difference of two symbols. GAS and the HP | |
7315 | linker can't do this when one of the symbols is | |
7316 | external. */ | |
7317 | xoperands[1] = gen_label_rtx (); | |
7318 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7319 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
805e22b2 | 7320 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
b70ea764 | 7321 | CODE_LABEL_NUMBER (xoperands[1])); |
ece88821 | 7322 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); |
7323 | } | |
2247cc5f | 7324 | else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)) |
b70ea764 | 7325 | { |
ece88821 | 7326 | /* GAS currently can't generate the relocations that |
7327 | are needed for the SOM linker under HP-UX using this | |
7328 | sequence. The GNU linker doesn't generate the stubs | |
7329 | that are needed for external calls on TARGET_ELF32 | |
7330 | with this sequence. For now, we have to use a | |
7331 | longer plabel sequence when using GAS. */ | |
7332 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7333 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", | |
b70ea764 | 7334 | xoperands); |
ece88821 | 7335 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", |
b70ea764 | 7336 | xoperands); |
7337 | } | |
5e3c5739 | 7338 | else |
7339 | { | |
ece88821 | 7340 | /* Emit a long plabel-based call sequence. This is |
7341 | essentially an inline implementation of $$dyncall. | |
7342 | We don't actually try to call $$dyncall as this is | |
7343 | as difficult as calling the function itself. */ | |
7344 | struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0)); | |
7345 | ||
7346 | xoperands[0] = p->internal_label; | |
7347 | xoperands[1] = gen_label_rtx (); | |
7348 | ||
7349 | /* Since the call is indirect, FP arguments in registers | |
7350 | need to be copied to the general registers. Then, the | |
7351 | argument relocation stub will copy them back. */ | |
7352 | if (TARGET_SOM) | |
7353 | copy_fp_args (insn); | |
7354 | ||
7355 | if (flag_pic) | |
7356 | { | |
7357 | output_asm_insn ("addil LT'%0,%%r19", xoperands); | |
7358 | output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands); | |
7359 | output_asm_insn ("ldw 0(%%r1),%%r1", xoperands); | |
7360 | } | |
7361 | else | |
7362 | { | |
7363 | output_asm_insn ("addil LR'%0-$global$,%%r27", | |
7364 | xoperands); | |
7365 | output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1", | |
7366 | xoperands); | |
7367 | } | |
06ddb6f8 | 7368 | |
ece88821 | 7369 | output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands); |
7370 | output_asm_insn ("depi 0,31,2,%%r1", xoperands); | |
7371 | output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands); | |
7372 | output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands); | |
c7a4e712 | 7373 | |
ece88821 | 7374 | if (!sibcall && !TARGET_PA_20) |
7375 | { | |
7376 | output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands); | |
ee376abe | 7377 | if (TARGET_NO_SPACE_REGS) |
7378 | output_asm_insn ("addi 8,%%r2,%%r2", xoperands); | |
7379 | else | |
7380 | output_asm_insn ("addi 16,%%r2,%%r2", xoperands); | |
ece88821 | 7381 | } |
7382 | } | |
c7a4e712 | 7383 | |
ece88821 | 7384 | if (TARGET_PA_20) |
5e3c5739 | 7385 | { |
ece88821 | 7386 | if (sibcall) |
7387 | output_asm_insn ("bve (%%r1)", xoperands); | |
7388 | else | |
7389 | { | |
7390 | if (indirect_call) | |
7391 | { | |
7392 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7393 | output_asm_insn ("stw %%r2,-24(%%sp)", xoperands); | |
7394 | delay_slot_filled = 1; | |
7395 | } | |
7396 | else | |
7397 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7398 | } | |
5e3c5739 | 7399 | } |
7400 | else | |
7401 | { | |
ee376abe | 7402 | if (!TARGET_NO_SPACE_REGS) |
7403 | output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0", | |
7404 | xoperands); | |
06ddb6f8 | 7405 | |
ece88821 | 7406 | if (sibcall) |
ee376abe | 7407 | { |
7408 | if (TARGET_NO_SPACE_REGS) | |
7409 | output_asm_insn ("be 0(%%sr4,%%r1)", xoperands); | |
7410 | else | |
7411 | output_asm_insn ("be 0(%%sr0,%%r1)", xoperands); | |
7412 | } | |
ece88821 | 7413 | else |
7414 | { | |
ee376abe | 7415 | if (TARGET_NO_SPACE_REGS) |
7416 | output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands); | |
7417 | else | |
7418 | output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands); | |
06ddb6f8 | 7419 | |
ece88821 | 7420 | if (indirect_call) |
7421 | output_asm_insn ("stw %%r31,-24(%%sp)", xoperands); | |
7422 | else | |
7423 | output_asm_insn ("copy %%r31,%%r2", xoperands); | |
7424 | delay_slot_filled = 1; | |
7425 | } | |
7426 | } | |
7427 | } | |
06ddb6f8 | 7428 | } |
d6686e21 | 7429 | } |
6d36483b | 7430 | |
8a05c3c2 | 7431 | if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted)) |
ece88821 | 7432 | output_asm_insn ("nop", xoperands); |
d6686e21 | 7433 | |
ece88821 | 7434 | /* We are done if there isn't a jump in the delay slot. */ |
7435 | if (seq_length == 0 | |
7436 | || delay_insn_deleted | |
7437 | || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7438 | return ""; | |
d6686e21 | 7439 | |
ece88821 | 7440 | /* A sibcall should never have a branch in the delay slot. */ |
7441 | if (sibcall) | |
7442 | abort (); | |
d6686e21 | 7443 | |
ece88821 | 7444 | /* This call has an unconditional jump in its delay slot. */ |
7445 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
d6686e21 | 7446 | |
cd0dfcc5 | 7447 | if (!delay_slot_filled && INSN_ADDRESSES_SET_P ()) |
d6686e21 | 7448 | { |
ece88821 | 7449 | /* See if the return address can be adjusted. Use the containing |
7450 | sequence insn's address. */ | |
7451 | rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); | |
7452 | int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7453 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7454 | ||
7455 | if (VAL_14_BITS_P (distance)) | |
7456 | { | |
7457 | xoperands[1] = gen_label_rtx (); | |
7458 | output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands); | |
805e22b2 | 7459 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
7460 | CODE_LABEL_NUMBER (xoperands[1])); | |
ece88821 | 7461 | } |
7462 | else | |
ece88821 | 7463 | output_asm_insn ("nop\n\tb,n %0", xoperands); |
d6686e21 | 7464 | } |
ece88821 | 7465 | else |
ece88821 | 7466 | output_asm_insn ("b,n %0", xoperands); |
d6686e21 | 7467 | |
7468 | /* Delete the jump. */ | |
7469 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7470 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7471 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
ece88821 | 7472 | |
d6686e21 | 7473 | return ""; |
7474 | } | |
7475 | ||
cd0dfcc5 | 7476 | /* Return the attribute length of the indirect call instruction INSN. |
7477 | The length must match the code generated by output_indirect call. | |
7478 | The returned length includes the delay slot. Currently, the delay | |
7479 | slot of an indirect call sequence is not exposed and it is used by | |
7480 | the sequence itself. */ | |
7481 | ||
7482 | int | |
5c1d8983 | 7483 | attr_length_indirect_call (rtx insn) |
cd0dfcc5 | 7484 | { |
7485 | unsigned long distance = -1; | |
8a05c3c2 | 7486 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
cd0dfcc5 | 7487 | |
7488 | if (INSN_ADDRESSES_SET_P ()) | |
7489 | { | |
2247cc5f | 7490 | distance = (total + insn_current_reference_address (insn)); |
7491 | if (distance < total) | |
cd0dfcc5 | 7492 | distance = -1; |
7493 | } | |
7494 | ||
7495 | if (TARGET_64BIT) | |
7496 | return 12; | |
7497 | ||
7498 | if (TARGET_FAST_INDIRECT_CALLS | |
7499 | || (!TARGET_PORTABLE_RUNTIME | |
7500 | && ((TARGET_PA_20 && distance < 7600000) || distance < 240000))) | |
7501 | return 8; | |
7502 | ||
7503 | if (flag_pic) | |
7504 | return 24; | |
7505 | ||
7506 | if (TARGET_PORTABLE_RUNTIME) | |
7507 | return 20; | |
7508 | ||
7509 | /* Out of reach, can use ble. */ | |
7510 | return 12; | |
7511 | } | |
7512 | ||
7513 | const char * | |
5c1d8983 | 7514 | output_indirect_call (rtx insn, rtx call_dest) |
cd0dfcc5 | 7515 | { |
7516 | rtx xoperands[1]; | |
7517 | ||
7518 | if (TARGET_64BIT) | |
7519 | { | |
7520 | xoperands[0] = call_dest; | |
7521 | output_asm_insn ("ldd 16(%0),%%r2", xoperands); | |
7522 | output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands); | |
7523 | return ""; | |
7524 | } | |
7525 | ||
7526 | /* First the special case for kernels, level 0 systems, etc. */ | |
7527 | if (TARGET_FAST_INDIRECT_CALLS) | |
7528 | return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2"; | |
7529 | ||
7530 | /* Now the normal case -- we can reach $$dyncall directly or | |
7531 | we're sure that we can get there via a long-branch stub. | |
7532 | ||
7533 | No need to check target flags as the length uniquely identifies | |
7534 | the remaining cases. */ | |
7535 | if (attr_length_indirect_call (insn) == 8) | |
f707acb9 | 7536 | { |
7537 | /* The HP linker substitutes a BLE for millicode calls using | |
7538 | the short PIC PCREL form. Thus, we must use %r31 as the | |
7539 | link register when generating PA 1.x code. */ | |
7540 | if (TARGET_PA_20) | |
7541 | return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31"; | |
7542 | else | |
7543 | return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2"; | |
7544 | } | |
cd0dfcc5 | 7545 | |
7546 | /* Long millicode call, but we are not generating PIC or portable runtime | |
7547 | code. */ | |
7548 | if (attr_length_indirect_call (insn) == 12) | |
7549 | return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2"; | |
7550 | ||
7551 | /* Long millicode call for portable runtime. */ | |
7552 | if (attr_length_indirect_call (insn) == 20) | |
7553 | return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop"; | |
7554 | ||
7555 | /* We need a long PIC call to $$dyncall. */ | |
7556 | xoperands[0] = NULL_RTX; | |
7557 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7558 | if (TARGET_SOM || !TARGET_GAS) | |
7559 | { | |
7560 | xoperands[0] = gen_label_rtx (); | |
7561 | output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands); | |
7562 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
7563 | CODE_LABEL_NUMBER (xoperands[0])); | |
7564 | output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands); | |
7565 | } | |
7566 | else | |
7567 | { | |
7568 | output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands); | |
7569 | output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1", | |
7570 | xoperands); | |
7571 | } | |
7572 | output_asm_insn ("blr %%r0,%%r2", xoperands); | |
7573 | output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands); | |
7574 | return ""; | |
7575 | } | |
7576 | ||
7577 | /* Return the total length of the save and restore instructions needed for | |
7578 | the data linkage table pointer (i.e., the PIC register) across the call | |
7579 | instruction INSN. No-return calls do not require a save and restore. | |
7580 | In addition, we may be able to avoid the save and restore for calls | |
7581 | within the same translation unit. */ | |
7582 | ||
7583 | int | |
5c1d8983 | 7584 | attr_length_save_restore_dltp (rtx insn) |
cd0dfcc5 | 7585 | { |
7586 | if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
7587 | return 0; | |
7588 | ||
7589 | return 8; | |
7590 | } | |
7591 | ||
d6f01525 | 7592 | /* In HPUX 8.0's shared library scheme, special relocations are needed |
6d36483b | 7593 | for function labels if they might be passed to a function |
d6f01525 | 7594 | in a shared library (because shared libraries don't live in code |
44acf429 | 7595 | space), and special magic is needed to construct their address. */ |
d6f01525 | 7596 | |
7597 | void | |
5c1d8983 | 7598 | hppa_encode_label (rtx sym) |
d6f01525 | 7599 | { |
611a88e1 | 7600 | const char *str = XSTR (sym, 0); |
cccfb31e | 7601 | int len = strlen (str) + 1; |
7602 | char *newstr, *p; | |
d6f01525 | 7603 | |
cccfb31e | 7604 | p = newstr = alloca (len + 1); |
cccfb31e | 7605 | *p++ = '@'; |
7606 | strcpy (p, str); | |
74d80a9a | 7607 | |
ea52c577 | 7608 | XSTR (sym, 0) = ggc_alloc_string (newstr, len); |
d6f01525 | 7609 | } |
6d36483b | 7610 | |
7811991d | 7611 | static void |
5c1d8983 | 7612 | pa_encode_section_info (tree decl, rtx rtl, int first) |
7811991d | 7613 | { |
7614 | if (first && TEXT_SPACE_P (decl)) | |
7615 | { | |
7811991d | 7616 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
7617 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2c129d70 | 7618 | hppa_encode_label (XEXP (rtl, 0)); |
7811991d | 7619 | } |
7620 | } | |
7621 | ||
7b4a38a6 | 7622 | /* This is sort of inverse to pa_encode_section_info. */ |
7623 | ||
7624 | static const char * | |
5c1d8983 | 7625 | pa_strip_name_encoding (const char *str) |
7b4a38a6 | 7626 | { |
c0264367 | 7627 | str += (*str == '@'); |
7628 | str += (*str == '*'); | |
7629 | return str; | |
7b4a38a6 | 7630 | } |
7631 | ||
d6f01525 | 7632 | int |
5c1d8983 | 7633 | function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d6f01525 | 7634 | { |
c1b3411e | 7635 | return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0)); |
d6f01525 | 7636 | } |
f33e3942 | 7637 | |
166bf021 | 7638 | /* Returns 1 if OP is a function label involved in a simple addition |
7639 | with a constant. Used to keep certain patterns from matching | |
7640 | during instruction combination. */ | |
7641 | int | |
5c1d8983 | 7642 | is_function_label_plus_const (rtx op) |
166bf021 | 7643 | { |
7644 | /* Strip off any CONST. */ | |
7645 | if (GET_CODE (op) == CONST) | |
7646 | op = XEXP (op, 0); | |
7647 | ||
7648 | return (GET_CODE (op) == PLUS | |
7649 | && function_label_operand (XEXP (op, 0), Pmode) | |
7650 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
7651 | } | |
7652 | ||
f1752b7e | 7653 | /* Output assembly code for a thunk to FUNCTION. */ |
7654 | ||
6988553d | 7655 | static void |
5c1d8983 | 7656 | pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, |
7657 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
7658 | tree function) | |
f1752b7e | 7659 | { |
2247cc5f | 7660 | const char *fname = XSTR (XEXP (DECL_RTL (function), 0), 0); |
7661 | const char *tname = XSTR (XEXP (DECL_RTL (thunk_fndecl), 0), 0); | |
7662 | int val_14 = VAL_14_BITS_P (delta); | |
7663 | int nbytes = 0; | |
f1752b7e | 7664 | static unsigned int current_thunk_number; |
7665 | char label[16]; | |
2247cc5f | 7666 | |
7667 | ASM_OUTPUT_LABEL (file, tname); | |
7668 | fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); | |
7669 | ||
7670 | fname = (*targetm.strip_name_encoding) (fname); | |
7671 | tname = (*targetm.strip_name_encoding) (tname); | |
7672 | ||
7673 | /* Output the thunk. We know that the function is in the same | |
7674 | translation unit (i.e., the same space) as the thunk, and that | |
7675 | thunks are output after their method. Thus, we don't need an | |
7676 | external branch to reach the function. With SOM and GAS, | |
7677 | functions and thunks are effectively in different sections. | |
7678 | Thus, we can always use a IA-relative branch and the linker | |
7679 | will add a long branch stub if necessary. | |
7680 | ||
7681 | However, we have to be careful when generating PIC code on the | |
7682 | SOM port to ensure that the sequence does not transfer to an | |
7683 | import stub for the target function as this could clobber the | |
7684 | return value saved at SP-24. This would also apply to the | |
7685 | 32-bit linux port if the multi-space model is implemented. */ | |
7686 | if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
7687 | && !(flag_pic && TREE_PUBLIC (function)) | |
7688 | && (TARGET_GAS || last_address < 262132)) | |
7689 | || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
7690 | && ((targetm.have_named_sections | |
7691 | && DECL_SECTION_NAME (thunk_fndecl) != NULL | |
7692 | /* The GNU 64-bit linker has rather poor stub management. | |
7693 | So, we use a long branch from thunks that aren't in | |
7694 | the same section as the target function. */ | |
7695 | && ((!TARGET_64BIT | |
7696 | && (DECL_SECTION_NAME (thunk_fndecl) | |
7697 | != DECL_SECTION_NAME (function))) | |
7698 | || ((DECL_SECTION_NAME (thunk_fndecl) | |
7699 | == DECL_SECTION_NAME (function)) | |
7700 | && last_address < 262132))) | |
7701 | || (!targetm.have_named_sections && last_address < 262132)))) | |
7702 | { | |
7703 | if (val_14) | |
7704 | { | |
7705 | fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC | |
7706 | "(%%r26),%%r26\n", fname, delta); | |
7707 | nbytes += 8; | |
7708 | } | |
7709 | else | |
7710 | { | |
7711 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC | |
7712 | ",%%r26\n", delta); | |
7713 | fprintf (file, "\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC | |
7714 | "(%%r1),%%r26\n", fname, delta); | |
7715 | nbytes += 12; | |
7716 | } | |
7717 | } | |
7718 | else if (TARGET_64BIT) | |
7719 | { | |
7720 | /* We only have one call-clobbered scratch register, so we can't | |
7721 | make use of the delay slot if delta doesn't fit in 14 bits. */ | |
7722 | if (!val_14) | |
7723 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC | |
7724 | ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC | |
7725 | "(%%r1),%%r26\n", delta, delta); | |
7726 | ||
7727 | fprintf (file, "\tb,l .+8,%%r1\n"); | |
7728 | ||
7729 | if (TARGET_GAS) | |
7730 | { | |
7731 | fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname); | |
7732 | fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r1\n", fname); | |
7733 | } | |
7734 | else | |
7735 | { | |
7736 | int off = val_14 ? 8 : 16; | |
7737 | fprintf (file, "\taddil L'%s-%s-%d,%%r1\n", fname, tname, off); | |
7738 | fprintf (file, "\tldo R'%s-%s-%d(%%r1),%%r1\n", fname, tname, off); | |
7739 | } | |
7740 | ||
7741 | if (val_14) | |
7742 | { | |
7743 | fprintf (file, "\tbv %%r0(%%r1)\n\tldo "); | |
7744 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta); | |
7745 | nbytes += 20; | |
7746 | } | |
7747 | else | |
7748 | { | |
7749 | fprintf (file, "\tbv,n %%r0(%%r1)\n"); | |
7750 | nbytes += 24; | |
7751 | } | |
7752 | } | |
7753 | else if (TARGET_PORTABLE_RUNTIME) | |
7754 | { | |
7755 | fprintf (file, "\tldil L'%s,%%r1\n", fname); | |
7756 | fprintf (file, "\tldo R'%s(%%r1),%%r22\n", fname); | |
7757 | ||
7758 | if (val_14) | |
7759 | { | |
7760 | fprintf (file, "\tbv %%r0(%%r22)\n\tldo "); | |
7761 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta); | |
7762 | nbytes += 16; | |
7763 | } | |
7764 | else | |
7765 | { | |
7766 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC | |
7767 | ",%%r26\n", delta); | |
7768 | fprintf (file, "\tbv %%r0(%%r22)\n\tldo "); | |
7769 | fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta); | |
7770 | nbytes += 20; | |
7771 | } | |
7772 | } | |
7773 | else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
7774 | { | |
7775 | /* The function is accessible from outside this module. The only | |
7776 | way to avoid an import stub between the thunk and function is to | |
7777 | call the function directly with an indirect sequence similar to | |
7778 | that used by $$dyncall. This is possible because $$dyncall acts | |
7779 | as the import stub in an indirect call. */ | |
7780 | const char *lab; | |
7781 | ||
7782 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number); | |
7783 | lab = (*targetm.strip_name_encoding) (label); | |
7784 | ||
7785 | fprintf (file, "\taddil LT'%s,%%r19\n", lab); | |
7786 | fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab); | |
7787 | fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n"); | |
7788 | fprintf (file, "\tbb,>=,n %%r22,30,.+16\n"); | |
7789 | fprintf (file, "\tdepi 0,31,2,%%r22\n"); | |
7790 | fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n"); | |
7791 | fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n"); | |
7792 | if (!val_14) | |
7793 | { | |
7794 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC | |
7795 | ",%%r26\n", delta); | |
7796 | nbytes += 4; | |
7797 | } | |
7798 | if (TARGET_PA_20) | |
7799 | { | |
7800 | fprintf (file, "\tbve (%%r22)\n\tldo "); | |
7801 | nbytes += 36; | |
7802 | } | |
7803 | else | |
f1752b7e | 7804 | { |
ee376abe | 7805 | if (TARGET_NO_SPACE_REGS) |
2247cc5f | 7806 | { |
7807 | fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo "); | |
7808 | nbytes += 36; | |
7809 | } | |
ee376abe | 7810 | else |
7811 | { | |
6454616d | 7812 | fprintf (file, "\tldsid (%%sr0,%%r22),%%r21\n"); |
2247cc5f | 7813 | fprintf (file, "\tmtsp %%r21,%%sr0\n"); |
ee376abe | 7814 | fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo "); |
2247cc5f | 7815 | nbytes += 44; |
ee376abe | 7816 | } |
2247cc5f | 7817 | } |
7818 | ||
7819 | if (val_14) | |
7820 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta); | |
7821 | else | |
7822 | fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta); | |
7823 | } | |
7824 | else if (flag_pic) | |
7825 | { | |
7826 | if (TARGET_PA_20) | |
7827 | fprintf (file, "\tb,l .+8,%%r1\n"); | |
7828 | else | |
7829 | fprintf (file, "\tbl .+8,%%r1\n"); | |
7830 | ||
7831 | if (TARGET_SOM || !TARGET_GAS) | |
7832 | { | |
7833 | fprintf (file, "\taddil L'%s-%s-8,%%r1\n", fname, tname); | |
7834 | fprintf (file, "\tldo R'%s-%s-8(%%r1),%%r22\n", fname, tname); | |
7835 | } | |
7836 | else | |
7837 | { | |
7838 | fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname); | |
7839 | fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r22\n", fname); | |
7840 | } | |
7841 | ||
7842 | if (val_14) | |
7843 | { | |
7844 | fprintf (file, "\tbv %%r0(%%r22)\n\tldo "); | |
4840a03a | 7845 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta); |
2247cc5f | 7846 | nbytes += 20; |
f1752b7e | 7847 | } |
7848 | else | |
2247cc5f | 7849 | { |
7850 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC | |
7851 | ",%%r26\n", delta); | |
7852 | fprintf (file, "\tbv %%r0(%%r22)\n\tldo "); | |
7853 | fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta); | |
7854 | nbytes += 24; | |
7855 | } | |
f1752b7e | 7856 | } |
7857 | else | |
7858 | { | |
2247cc5f | 7859 | if (!val_14) |
7860 | fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC ",%%r26\n", delta); | |
7861 | ||
7862 | fprintf (file, "\tldil L'%s,%%r22\n", fname); | |
7863 | fprintf (file, "\tbe R'%s(%%sr4,%%r22)\n\tldo ", fname); | |
7864 | ||
7865 | if (val_14) | |
f1752b7e | 7866 | { |
2247cc5f | 7867 | fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta); |
7868 | nbytes += 12; | |
f1752b7e | 7869 | } |
7870 | else | |
2247cc5f | 7871 | { |
7872 | fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta); | |
7873 | nbytes += 16; | |
7874 | } | |
f1752b7e | 7875 | } |
2247cc5f | 7876 | |
f1752b7e | 7877 | fprintf (file, "\t.EXIT\n\t.PROCEND\n"); |
2247cc5f | 7878 | |
7879 | if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
f1752b7e | 7880 | { |
7881 | data_section (); | |
7882 | fprintf (file, "\t.align 4\n"); | |
2247cc5f | 7883 | ASM_OUTPUT_LABEL (file, label); |
7884 | fprintf (file, "\t.word P'%s\n", fname); | |
f1752b7e | 7885 | function_section (thunk_fndecl); |
7886 | } | |
2247cc5f | 7887 | |
f1752b7e | 7888 | current_thunk_number++; |
2247cc5f | 7889 | nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) |
7890 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
7891 | last_address += nbytes; | |
7892 | update_total_code_bytes (nbytes); | |
f1752b7e | 7893 | } |
7894 | ||
805e22b2 | 7895 | /* Only direct calls to static functions are allowed to be sibling (tail) |
7896 | call optimized. | |
7897 | ||
7898 | This restriction is necessary because some linker generated stubs will | |
7899 | store return pointers into rp' in some cases which might clobber a | |
7900 | live value already in rp'. | |
7901 | ||
7902 | In a sibcall the current function and the target function share stack | |
7903 | space. Thus if the path to the current function and the path to the | |
7904 | target function save a value in rp', they save the value into the | |
7905 | same stack slot, which has undesirable consequences. | |
7906 | ||
7907 | Because of the deferred binding nature of shared libraries any function | |
7908 | with external scope could be in a different load module and thus require | |
7909 | rp' to be saved when calling that function. So sibcall optimizations | |
7910 | can only be safe for static function. | |
7911 | ||
7912 | Note that GCC never needs return value relocations, so we don't have to | |
7913 | worry about static calls with return value relocations (which require | |
7914 | saving rp'). | |
7915 | ||
7916 | It is safe to perform a sibcall optimization when the target function | |
7917 | will never return. */ | |
7918 | static bool | |
5c1d8983 | 7919 | pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
805e22b2 | 7920 | { |
f62b73b6 | 7921 | /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in |
7922 | single subspace mode and the call is not indirect. As far as I know, | |
7923 | there is no operating system support for the multiple subspace mode. | |
7924 | It might be possible to support indirect calls if we didn't use | |
7925 | $$dyncall (see the indirect sequence generated in output_call). */ | |
7926 | if (TARGET_ELF32) | |
7927 | return (decl != NULL_TREE); | |
7928 | ||
7929 | /* Sibcalls are not ok because the arg pointer register is not a fixed | |
2cecd772 | 7930 | register. This prevents the sibcall optimization from occurring. In |
f62b73b6 | 7931 | addition, there are problems with stub placement using GNU ld. This |
7932 | is because a normal sibcall branch uses a 17-bit relocation while | |
7933 | a regular call branch uses a 22-bit relocation. As a result, more | |
7934 | care needs to be taken in the placement of long-branch stubs. */ | |
7935 | if (TARGET_64BIT) | |
7936 | return false; | |
7937 | ||
805e22b2 | 7938 | return (decl |
f62b73b6 | 7939 | && !TARGET_PORTABLE_RUNTIME |
7940 | && !TREE_PUBLIC (decl)); | |
805e22b2 | 7941 | } |
7942 | ||
37580c80 | 7943 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
7944 | use in fmpyadd instructions. */ | |
4ed6ee50 | 7945 | int |
5c1d8983 | 7946 | fmpyaddoperands (rtx *operands) |
4ed6ee50 | 7947 | { |
201f01e9 | 7948 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 7949 | |
ab449421 | 7950 | /* Must be a floating point mode. */ |
7951 | if (mode != SFmode && mode != DFmode) | |
7952 | return 0; | |
7953 | ||
4ed6ee50 | 7954 | /* All modes must be the same. */ |
201f01e9 | 7955 | if (! (mode == GET_MODE (operands[1]) |
7956 | && mode == GET_MODE (operands[2]) | |
7957 | && mode == GET_MODE (operands[3]) | |
7958 | && mode == GET_MODE (operands[4]) | |
7959 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 7960 | return 0; |
7961 | ||
ab449421 | 7962 | /* All operands must be registers. */ |
7963 | if (! (GET_CODE (operands[1]) == REG | |
7964 | && GET_CODE (operands[2]) == REG | |
7965 | && GET_CODE (operands[3]) == REG | |
7966 | && GET_CODE (operands[4]) == REG | |
7967 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 7968 | return 0; |
7969 | ||
37580c80 | 7970 | /* Only 2 real operands to the addition. One of the input operands must |
7971 | be the same as the output operand. */ | |
4ed6ee50 | 7972 | if (! rtx_equal_p (operands[3], operands[4]) |
7973 | && ! rtx_equal_p (operands[3], operands[5])) | |
7974 | return 0; | |
7975 | ||
7976 | /* Inout operand of add can not conflict with any operands from multiply. */ | |
7977 | if (rtx_equal_p (operands[3], operands[0]) | |
7978 | || rtx_equal_p (operands[3], operands[1]) | |
7979 | || rtx_equal_p (operands[3], operands[2])) | |
7980 | return 0; | |
7981 | ||
7982 | /* multiply can not feed into addition operands. */ | |
7983 | if (rtx_equal_p (operands[4], operands[0]) | |
7984 | || rtx_equal_p (operands[5], operands[0])) | |
7985 | return 0; | |
7986 | ||
ab449421 | 7987 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
7988 | if (mode == SFmode | |
bac38c40 | 7989 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
7990 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
7991 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
7992 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
7993 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
7994 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 7995 | return 0; |
7996 | ||
4ed6ee50 | 7997 | /* Passed. Operands are suitable for fmpyadd. */ |
7998 | return 1; | |
7999 | } | |
8000 | ||
de419443 | 8001 | #if !defined(USE_COLLECT2) |
8002 | static void | |
5c1d8983 | 8003 | pa_asm_out_constructor (rtx symbol, int priority) |
de419443 | 8004 | { |
8005 | if (!function_label_operand (symbol, VOIDmode)) | |
8006 | hppa_encode_label (symbol); | |
8007 | ||
8008 | #ifdef CTORS_SECTION_ASM_OP | |
8009 | default_ctor_section_asm_out_constructor (symbol, priority); | |
8010 | #else | |
8011 | # ifdef TARGET_ASM_NAMED_SECTION | |
8012 | default_named_section_asm_out_constructor (symbol, priority); | |
8013 | # else | |
8014 | default_stabs_asm_out_constructor (symbol, priority); | |
8015 | # endif | |
8016 | #endif | |
8017 | } | |
8018 | ||
8019 | static void | |
5c1d8983 | 8020 | pa_asm_out_destructor (rtx symbol, int priority) |
de419443 | 8021 | { |
8022 | if (!function_label_operand (symbol, VOIDmode)) | |
8023 | hppa_encode_label (symbol); | |
8024 | ||
8025 | #ifdef DTORS_SECTION_ASM_OP | |
8026 | default_dtor_section_asm_out_destructor (symbol, priority); | |
8027 | #else | |
8028 | # ifdef TARGET_ASM_NAMED_SECTION | |
8029 | default_named_section_asm_out_destructor (symbol, priority); | |
8030 | # else | |
8031 | default_stabs_asm_out_destructor (symbol, priority); | |
8032 | # endif | |
8033 | #endif | |
8034 | } | |
8035 | #endif | |
8036 | ||
37580c80 | 8037 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
8038 | use in fmpysub instructions. */ | |
4ed6ee50 | 8039 | int |
5c1d8983 | 8040 | fmpysuboperands (rtx *operands) |
4ed6ee50 | 8041 | { |
201f01e9 | 8042 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 8043 | |
ab449421 | 8044 | /* Must be a floating point mode. */ |
8045 | if (mode != SFmode && mode != DFmode) | |
8046 | return 0; | |
8047 | ||
4ed6ee50 | 8048 | /* All modes must be the same. */ |
201f01e9 | 8049 | if (! (mode == GET_MODE (operands[1]) |
8050 | && mode == GET_MODE (operands[2]) | |
8051 | && mode == GET_MODE (operands[3]) | |
8052 | && mode == GET_MODE (operands[4]) | |
8053 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 8054 | return 0; |
8055 | ||
ab449421 | 8056 | /* All operands must be registers. */ |
8057 | if (! (GET_CODE (operands[1]) == REG | |
8058 | && GET_CODE (operands[2]) == REG | |
8059 | && GET_CODE (operands[3]) == REG | |
8060 | && GET_CODE (operands[4]) == REG | |
8061 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 8062 | return 0; |
8063 | ||
37580c80 | 8064 | /* Only 2 real operands to the subtraction. Subtraction is not a commutative |
8065 | operation, so operands[4] must be the same as operand[3]. */ | |
4ed6ee50 | 8066 | if (! rtx_equal_p (operands[3], operands[4])) |
8067 | return 0; | |
8068 | ||
8069 | /* multiply can not feed into subtraction. */ | |
37580c80 | 8070 | if (rtx_equal_p (operands[5], operands[0])) |
4ed6ee50 | 8071 | return 0; |
8072 | ||
37580c80 | 8073 | /* Inout operand of sub can not conflict with any operands from multiply. */ |
4ed6ee50 | 8074 | if (rtx_equal_p (operands[3], operands[0]) |
8075 | || rtx_equal_p (operands[3], operands[1]) | |
8076 | || rtx_equal_p (operands[3], operands[2])) | |
8077 | return 0; | |
8078 | ||
ab449421 | 8079 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8080 | if (mode == SFmode | |
bac38c40 | 8081 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8082 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8083 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8084 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8085 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8086 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 8087 | return 0; |
8088 | ||
4ed6ee50 | 8089 | /* Passed. Operands are suitable for fmpysub. */ |
8090 | return 1; | |
8091 | } | |
8092 | ||
89f29d73 | 8093 | int |
5c1d8983 | 8094 | plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
89f29d73 | 8095 | { |
8096 | return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR | |
8097 | || GET_CODE (op) == IOR); | |
8098 | } | |
6720f95e | 8099 | |
8100 | /* Return 1 if the given constant is 2, 4, or 8. These are the valid | |
8101 | constants for shadd instructions. */ | |
7d27e4c9 | 8102 | static int |
5c1d8983 | 8103 | shadd_constant_p (int val) |
6720f95e | 8104 | { |
8105 | if (val == 2 || val == 4 || val == 8) | |
8106 | return 1; | |
8107 | else | |
8108 | return 0; | |
8109 | } | |
3a16146d | 8110 | |
8111 | /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are | |
8112 | the valid constant for shadd instructions. */ | |
8113 | int | |
5c1d8983 | 8114 | shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
3a16146d | 8115 | { |
8116 | return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op))); | |
8117 | } | |
5fbd5940 | 8118 | |
dbd3d89d | 8119 | /* Return 1 if OP is valid as a base or index register in a |
8120 | REG+REG address. */ | |
42819d4e | 8121 | |
8122 | int | |
dbd3d89d | 8123 | borx_reg_operand (rtx op, enum machine_mode mode) |
42819d4e | 8124 | { |
dbd3d89d | 8125 | if (GET_CODE (op) != REG) |
21f3ee9c | 8126 | return 0; |
8127 | ||
dbd3d89d | 8128 | /* We must reject virtual registers as the only expressions that |
8129 | can be instantiated are REG and REG+CONST. */ | |
8130 | if (op == virtual_incoming_args_rtx | |
8131 | || op == virtual_stack_vars_rtx | |
8132 | || op == virtual_stack_dynamic_rtx | |
8133 | || op == virtual_outgoing_args_rtx | |
8134 | || op == virtual_cfa_rtx) | |
8135 | return 0; | |
42819d4e | 8136 | |
21f3ee9c | 8137 | /* While it's always safe to index off the frame pointer, it's not |
dbd3d89d | 8138 | profitable to do so when the frame pointer is being eliminated. */ |
8139 | if (!reload_completed | |
8140 | && flag_omit_frame_pointer | |
8141 | && !current_function_calls_alloca | |
8142 | && op == frame_pointer_rtx) | |
8143 | return 0; | |
42819d4e | 8144 | |
dbd3d89d | 8145 | return register_operand (op, mode); |
42819d4e | 8146 | } |
8147 | ||
51987f90 | 8148 | /* Return 1 if this operand is anything other than a hard register. */ |
8149 | ||
8150 | int | |
5c1d8983 | 8151 | non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
51987f90 | 8152 | { |
8153 | return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER); | |
8154 | } | |
8155 | ||
5fbd5940 | 8156 | /* Return 1 if INSN branches forward. Should be using insn_addresses |
6dc3b0d9 | 8157 | to avoid walking through all the insns... */ |
7d27e4c9 | 8158 | static int |
5c1d8983 | 8159 | forward_branch_p (rtx insn) |
5fbd5940 | 8160 | { |
8161 | rtx label = JUMP_LABEL (insn); | |
8162 | ||
8163 | while (insn) | |
8164 | { | |
8165 | if (insn == label) | |
8166 | break; | |
8167 | else | |
8168 | insn = NEXT_INSN (insn); | |
8169 | } | |
8170 | ||
8171 | return (insn == label); | |
8172 | } | |
8173 | ||
29a4502c | 8174 | /* Return 1 if OP is an equality comparison, else return 0. */ |
8175 | int | |
5c1d8983 | 8176 | eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
29a4502c | 8177 | { |
8178 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
8179 | } | |
8180 | ||
8181 | /* Return 1 if OP is an operator suitable for use in a movb instruction. */ | |
8182 | int | |
5c1d8983 | 8183 | movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
29a4502c | 8184 | { |
8185 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE | |
8186 | || GET_CODE (op) == LT || GET_CODE (op) == GE); | |
8187 | } | |
8188 | ||
d6686e21 | 8189 | /* Return 1 if INSN is in the delay slot of a call instruction. */ |
8190 | int | |
5c1d8983 | 8191 | jump_in_call_delay (rtx insn) |
d6686e21 | 8192 | { |
8193 | ||
8194 | if (GET_CODE (insn) != JUMP_INSN) | |
8195 | return 0; | |
8196 | ||
8197 | if (PREV_INSN (insn) | |
8198 | && PREV_INSN (PREV_INSN (insn)) | |
ece0fa59 | 8199 | && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN) |
d6686e21 | 8200 | { |
ece0fa59 | 8201 | rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn))); |
d6686e21 | 8202 | |
8203 | return (GET_CODE (PATTERN (test_insn)) == SEQUENCE | |
8204 | && XVECEXP (PATTERN (test_insn), 0, 1) == insn); | |
8205 | ||
8206 | } | |
8207 | else | |
8208 | return 0; | |
8209 | } | |
3b1e673e | 8210 | |
546a40bd | 8211 | /* Output an unconditional move and branch insn. */ |
8212 | ||
611a88e1 | 8213 | const char * |
5c1d8983 | 8214 | output_parallel_movb (rtx *operands, int length) |
546a40bd | 8215 | { |
8216 | /* These are the cases in which we win. */ | |
8217 | if (length == 4) | |
8218 | return "mov%I1b,tr %1,%0,%2"; | |
8219 | ||
8220 | /* None of these cases wins, but they don't lose either. */ | |
8221 | if (dbr_sequence_length () == 0) | |
8222 | { | |
8223 | /* Nothing in the delay slot, fake it by putting the combined | |
8224 | insn (the copy or add) in the delay slot of a bl. */ | |
8225 | if (GET_CODE (operands[1]) == CONST_INT) | |
5a811d43 | 8226 | return "b %2\n\tldi %1,%0"; |
546a40bd | 8227 | else |
5a811d43 | 8228 | return "b %2\n\tcopy %1,%0"; |
546a40bd | 8229 | } |
8230 | else | |
8231 | { | |
8232 | /* Something in the delay slot, but we've got a long branch. */ | |
8233 | if (GET_CODE (operands[1]) == CONST_INT) | |
5a811d43 | 8234 | return "ldi %1,%0\n\tb %2"; |
546a40bd | 8235 | else |
5a811d43 | 8236 | return "copy %1,%0\n\tb %2"; |
546a40bd | 8237 | } |
8238 | } | |
8239 | ||
8240 | /* Output an unconditional add and branch insn. */ | |
8241 | ||
611a88e1 | 8242 | const char * |
5c1d8983 | 8243 | output_parallel_addb (rtx *operands, int length) |
546a40bd | 8244 | { |
8245 | /* To make life easy we want operand0 to be the shared input/output | |
8246 | operand and operand1 to be the readonly operand. */ | |
8247 | if (operands[0] == operands[1]) | |
8248 | operands[1] = operands[2]; | |
8249 | ||
8250 | /* These are the cases in which we win. */ | |
8251 | if (length == 4) | |
8252 | return "add%I1b,tr %1,%0,%3"; | |
8253 | ||
8254 | /* None of these cases win, but they don't lose either. */ | |
8255 | if (dbr_sequence_length () == 0) | |
8256 | { | |
8257 | /* Nothing in the delay slot, fake it by putting the combined | |
8258 | insn (the copy or add) in the delay slot of a bl. */ | |
5a811d43 | 8259 | return "b %3\n\tadd%I1 %1,%0,%0"; |
546a40bd | 8260 | } |
8261 | else | |
8262 | { | |
8263 | /* Something in the delay slot, but we've got a long branch. */ | |
5a811d43 | 8264 | return "add%I1 %1,%0,%0\n\tb %3"; |
546a40bd | 8265 | } |
8266 | } | |
8267 | ||
7c5101fc | 8268 | /* Return nonzero if INSN (a jump insn) immediately follows a call |
8269 | to a named function. This is used to avoid filling the delay slot | |
8270 | of the jump since it can usually be eliminated by modifying RP in | |
8271 | the delay slot of the call. */ | |
9840d99d | 8272 | |
7d27e4c9 | 8273 | int |
5c1d8983 | 8274 | following_call (rtx insn) |
546a40bd | 8275 | { |
ed1b0769 | 8276 | if (! TARGET_JUMP_IN_DELAY) |
1b6f11e2 | 8277 | return 0; |
8278 | ||
546a40bd | 8279 | /* Find the previous real insn, skipping NOTEs. */ |
8280 | insn = PREV_INSN (insn); | |
8281 | while (insn && GET_CODE (insn) == NOTE) | |
8282 | insn = PREV_INSN (insn); | |
8283 | ||
8284 | /* Check for CALL_INSNs and millicode calls. */ | |
8285 | if (insn | |
1d2e016c | 8286 | && ((GET_CODE (insn) == CALL_INSN |
8287 | && get_attr_type (insn) != TYPE_DYNCALL) | |
546a40bd | 8288 | || (GET_CODE (insn) == INSN |
8289 | && GET_CODE (PATTERN (insn)) != SEQUENCE | |
8290 | && GET_CODE (PATTERN (insn)) != USE | |
8291 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8292 | && get_attr_type (insn) == TYPE_MILLI))) | |
8293 | return 1; | |
8294 | ||
8295 | return 0; | |
8296 | } | |
8297 | ||
3b1e673e | 8298 | /* We use this hook to perform a PA specific optimization which is difficult |
8299 | to do in earlier passes. | |
8300 | ||
8301 | We want the delay slots of branches within jump tables to be filled. | |
8302 | None of the compiler passes at the moment even has the notion that a | |
8303 | PA jump table doesn't contain addresses, but instead contains actual | |
8304 | instructions! | |
8305 | ||
8306 | Because we actually jump into the table, the addresses of each entry | |
01cc3b75 | 8307 | must stay constant in relation to the beginning of the table (which |
3b1e673e | 8308 | itself must stay constant relative to the instruction to jump into |
8309 | it). I don't believe we can guarantee earlier passes of the compiler | |
8310 | will adhere to those rules. | |
8311 | ||
8312 | So, late in the compilation process we find all the jump tables, and | |
8313 | expand them into real code -- eg each entry in the jump table vector | |
8314 | will get an appropriate label followed by a jump to the final target. | |
8315 | ||
8316 | Reorg and the final jump pass can then optimize these branches and | |
8317 | fill their delay slots. We end up with smaller, more efficient code. | |
8318 | ||
9840d99d | 8319 | The jump instructions within the table are special; we must be able |
3b1e673e | 8320 | to identify them during assembly output (if the jumps don't get filled |
8321 | we need to emit a nop rather than nullifying the delay slot)). We | |
b932f66c | 8322 | identify jumps in switch tables by using insns with the attribute |
8323 | type TYPE_BTABLE_BRANCH. | |
9239127b | 8324 | |
8325 | We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB | |
8326 | insns. This serves two purposes, first it prevents jump.c from | |
8327 | noticing that the last N entries in the table jump to the instruction | |
8328 | immediately after the table and deleting the jumps. Second, those | |
8329 | insns mark where we should emit .begin_brtab and .end_brtab directives | |
8330 | when using GAS (allows for better link time optimizations). */ | |
3b1e673e | 8331 | |
2efea8c0 | 8332 | static void |
5c1d8983 | 8333 | pa_reorg (void) |
3b1e673e | 8334 | { |
8335 | rtx insn; | |
8336 | ||
2efea8c0 | 8337 | remove_useless_addtr_insns (1); |
3d457930 | 8338 | |
342aabd9 | 8339 | if (pa_cpu < PROCESSOR_8000) |
2efea8c0 | 8340 | pa_combine_instructions (); |
342aabd9 | 8341 | |
bd49d362 | 8342 | |
3d457930 | 8343 | /* This is fairly cheap, so always run it if optimizing. */ |
a66555b2 | 8344 | if (optimize > 0 && !TARGET_BIG_SWITCH) |
3b1e673e | 8345 | { |
b41266d4 | 8346 | /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */ |
2efea8c0 | 8347 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
3b1e673e | 8348 | { |
b932f66c | 8349 | rtx pattern, tmp, location, label; |
3b1e673e | 8350 | unsigned int length, i; |
8351 | ||
b41266d4 | 8352 | /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */ |
3b1e673e | 8353 | if (GET_CODE (insn) != JUMP_INSN |
b41266d4 | 8354 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8355 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
3b1e673e | 8356 | continue; |
8357 | ||
9239127b | 8358 | /* Emit marker for the beginning of the branch table. */ |
8359 | emit_insn_before (gen_begin_brtab (), insn); | |
f9333726 | 8360 | |
3b1e673e | 8361 | pattern = PATTERN (insn); |
8362 | location = PREV_INSN (insn); | |
b41266d4 | 8363 | length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC); |
f9333726 | 8364 | |
3b1e673e | 8365 | for (i = 0; i < length; i++) |
8366 | { | |
a66555b2 | 8367 | /* Emit a label before each jump to keep jump.c from |
8368 | removing this code. */ | |
8369 | tmp = gen_label_rtx (); | |
8370 | LABEL_NUSES (tmp) = 1; | |
8371 | emit_label_after (tmp, location); | |
8372 | location = NEXT_INSN (location); | |
8373 | ||
b41266d4 | 8374 | if (GET_CODE (pattern) == ADDR_VEC) |
b932f66c | 8375 | label = XEXP (XVECEXP (pattern, 0, i), 0); |
b41266d4 | 8376 | else |
b932f66c | 8377 | label = XEXP (XVECEXP (pattern, 1, i), 0); |
8378 | ||
8379 | tmp = gen_short_jump (label); | |
8380 | ||
8381 | /* Emit the jump itself. */ | |
8382 | tmp = emit_jump_insn_after (tmp, location); | |
8383 | JUMP_LABEL (tmp) = label; | |
8384 | LABEL_NUSES (label)++; | |
8385 | location = NEXT_INSN (location); | |
3b1e673e | 8386 | |
8387 | /* Emit a BARRIER after the jump. */ | |
3b1e673e | 8388 | emit_barrier_after (location); |
3b1e673e | 8389 | location = NEXT_INSN (location); |
8390 | } | |
f9333726 | 8391 | |
9239127b | 8392 | /* Emit marker for the end of the branch table. */ |
8393 | emit_insn_before (gen_end_brtab (), location); | |
8394 | location = NEXT_INSN (location); | |
8395 | emit_barrier_after (location); | |
a66555b2 | 8396 | |
b41266d4 | 8397 | /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */ |
3b1e673e | 8398 | delete_insn (insn); |
8399 | } | |
8400 | } | |
9239127b | 8401 | else |
f9333726 | 8402 | { |
b932f66c | 8403 | /* Still need brtab marker insns. FIXME: the presence of these |
8404 | markers disables output of the branch table to readonly memory, | |
8405 | and any alignment directives that might be needed. Possibly, | |
8406 | the begin_brtab insn should be output before the label for the | |
7bd28bba | 8407 | table. This doesn't matter at the moment since the tables are |
b932f66c | 8408 | always output in the text section. */ |
2efea8c0 | 8409 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
f9333726 | 8410 | { |
8411 | /* Find an ADDR_VEC insn. */ | |
8412 | if (GET_CODE (insn) != JUMP_INSN | |
b41266d4 | 8413 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8414 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
f9333726 | 8415 | continue; |
8416 | ||
8417 | /* Now generate markers for the beginning and end of the | |
ad87de1e | 8418 | branch table. */ |
f9333726 | 8419 | emit_insn_before (gen_begin_brtab (), insn); |
8420 | emit_insn_after (gen_end_brtab (), insn); | |
8421 | } | |
8422 | } | |
d3287673 | 8423 | } |
bd49d362 | 8424 | |
8425 | /* The PA has a number of odd instructions which can perform multiple | |
8426 | tasks at once. On first generation PA machines (PA1.0 and PA1.1) | |
8427 | it may be profitable to combine two instructions into one instruction | |
8428 | with two outputs. It's not profitable PA2.0 machines because the | |
8429 | two outputs would take two slots in the reorder buffers. | |
8430 | ||
8431 | This routine finds instructions which can be combined and combines | |
8432 | them. We only support some of the potential combinations, and we | |
8433 | only try common ways to find suitable instructions. | |
8434 | ||
8435 | * addb can add two registers or a register and a small integer | |
8436 | and jump to a nearby (+-8k) location. Normally the jump to the | |
8437 | nearby location is conditional on the result of the add, but by | |
8438 | using the "true" condition we can make the jump unconditional. | |
8439 | Thus addb can perform two independent operations in one insn. | |
8440 | ||
8441 | * movb is similar to addb in that it can perform a reg->reg | |
8442 | or small immediate->reg copy and jump to a nearby (+-8k location). | |
8443 | ||
8444 | * fmpyadd and fmpysub can perform a FP multiply and either an | |
8445 | FP add or FP sub if the operands of the multiply and add/sub are | |
8446 | independent (there are other minor restrictions). Note both | |
8447 | the fmpy and fadd/fsub can in theory move to better spots according | |
8448 | to data dependencies, but for now we require the fmpy stay at a | |
8449 | fixed location. | |
8450 | ||
8451 | * Many of the memory operations can perform pre & post updates | |
8452 | of index registers. GCC's pre/post increment/decrement addressing | |
8453 | is far too simple to take advantage of all the possibilities. This | |
8454 | pass may not be suitable since those insns may not be independent. | |
8455 | ||
8456 | * comclr can compare two ints or an int and a register, nullify | |
8457 | the following instruction and zero some other register. This | |
8458 | is more difficult to use as it's harder to find an insn which | |
8459 | will generate a comclr than finding something like an unconditional | |
8460 | branch. (conditional moves & long branches create comclr insns). | |
8461 | ||
8462 | * Most arithmetic operations can conditionally skip the next | |
8463 | instruction. They can be viewed as "perform this operation | |
8464 | and conditionally jump to this nearby location" (where nearby | |
8465 | is an insns away). These are difficult to use due to the | |
8466 | branch length restrictions. */ | |
8467 | ||
7d27e4c9 | 8468 | static void |
5c1d8983 | 8469 | pa_combine_instructions (void) |
bd49d362 | 8470 | { |
8471 | rtx anchor, new; | |
8472 | ||
8473 | /* This can get expensive since the basic algorithm is on the | |
8474 | order of O(n^2) (or worse). Only do it for -O2 or higher | |
ad87de1e | 8475 | levels of optimization. */ |
bd49d362 | 8476 | if (optimize < 2) |
8477 | return; | |
8478 | ||
8479 | /* Walk down the list of insns looking for "anchor" insns which | |
8480 | may be combined with "floating" insns. As the name implies, | |
8481 | "anchor" instructions don't move, while "floating" insns may | |
8482 | move around. */ | |
ad851752 | 8483 | new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX)); |
bd49d362 | 8484 | new = make_insn_raw (new); |
8485 | ||
8486 | for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor)) | |
8487 | { | |
8488 | enum attr_pa_combine_type anchor_attr; | |
8489 | enum attr_pa_combine_type floater_attr; | |
8490 | ||
8491 | /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs. | |
8492 | Also ignore any special USE insns. */ | |
7d27e4c9 | 8493 | if ((GET_CODE (anchor) != INSN |
bd49d362 | 8494 | && GET_CODE (anchor) != JUMP_INSN |
7d27e4c9 | 8495 | && GET_CODE (anchor) != CALL_INSN) |
bd49d362 | 8496 | || GET_CODE (PATTERN (anchor)) == USE |
8497 | || GET_CODE (PATTERN (anchor)) == CLOBBER | |
8498 | || GET_CODE (PATTERN (anchor)) == ADDR_VEC | |
8499 | || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC) | |
8500 | continue; | |
8501 | ||
8502 | anchor_attr = get_attr_pa_combine_type (anchor); | |
8503 | /* See if anchor is an insn suitable for combination. */ | |
8504 | if (anchor_attr == PA_COMBINE_TYPE_FMPY | |
8505 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8506 | || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
8507 | && ! forward_branch_p (anchor))) | |
8508 | { | |
8509 | rtx floater; | |
8510 | ||
8511 | for (floater = PREV_INSN (anchor); | |
8512 | floater; | |
8513 | floater = PREV_INSN (floater)) | |
8514 | { | |
8515 | if (GET_CODE (floater) == NOTE | |
8516 | || (GET_CODE (floater) == INSN | |
8517 | && (GET_CODE (PATTERN (floater)) == USE | |
8518 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
8519 | continue; | |
8520 | ||
8521 | /* Anything except a regular INSN will stop our search. */ | |
8522 | if (GET_CODE (floater) != INSN | |
8523 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
8524 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
8525 | { | |
8526 | floater = NULL_RTX; | |
8527 | break; | |
8528 | } | |
8529 | ||
8530 | /* See if FLOATER is suitable for combination with the | |
8531 | anchor. */ | |
8532 | floater_attr = get_attr_pa_combine_type (floater); | |
8533 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
8534 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
8535 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8536 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
8537 | { | |
8538 | /* If ANCHOR and FLOATER can be combined, then we're | |
8539 | done with this pass. */ | |
8540 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8541 | SET_DEST (PATTERN (floater)), | |
8542 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
8543 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
8544 | break; | |
8545 | } | |
8546 | ||
8547 | else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
8548 | && floater_attr == PA_COMBINE_TYPE_ADDMOVE) | |
8549 | { | |
8550 | if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS) | |
8551 | { | |
8552 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8553 | SET_DEST (PATTERN (floater)), | |
8554 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
8555 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
8556 | break; | |
8557 | } | |
8558 | else | |
8559 | { | |
8560 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8561 | SET_DEST (PATTERN (floater)), | |
8562 | SET_SRC (PATTERN (floater)), | |
8563 | SET_SRC (PATTERN (floater)))) | |
8564 | break; | |
8565 | } | |
8566 | } | |
8567 | } | |
8568 | ||
8569 | /* If we didn't find anything on the backwards scan try forwards. */ | |
8570 | if (!floater | |
8571 | && (anchor_attr == PA_COMBINE_TYPE_FMPY | |
8572 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB)) | |
8573 | { | |
8574 | for (floater = anchor; floater; floater = NEXT_INSN (floater)) | |
8575 | { | |
8576 | if (GET_CODE (floater) == NOTE | |
8577 | || (GET_CODE (floater) == INSN | |
8578 | && (GET_CODE (PATTERN (floater)) == USE | |
8579 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
9840d99d | 8580 | |
bd49d362 | 8581 | continue; |
8582 | ||
8583 | /* Anything except a regular INSN will stop our search. */ | |
8584 | if (GET_CODE (floater) != INSN | |
8585 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
8586 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
8587 | { | |
8588 | floater = NULL_RTX; | |
8589 | break; | |
8590 | } | |
8591 | ||
8592 | /* See if FLOATER is suitable for combination with the | |
8593 | anchor. */ | |
8594 | floater_attr = get_attr_pa_combine_type (floater); | |
8595 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
8596 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
8597 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8598 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
8599 | { | |
8600 | /* If ANCHOR and FLOATER can be combined, then we're | |
8601 | done with this pass. */ | |
8602 | if (pa_can_combine_p (new, anchor, floater, 1, | |
8603 | SET_DEST (PATTERN (floater)), | |
ea52c577 | 8604 | XEXP (SET_SRC (PATTERN (floater)), |
8605 | 0), | |
8606 | XEXP (SET_SRC (PATTERN (floater)), | |
8607 | 1))) | |
bd49d362 | 8608 | break; |
8609 | } | |
8610 | } | |
8611 | } | |
8612 | ||
8613 | /* FLOATER will be nonzero if we found a suitable floating | |
8614 | insn for combination with ANCHOR. */ | |
8615 | if (floater | |
8616 | && (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8617 | || anchor_attr == PA_COMBINE_TYPE_FMPY)) | |
8618 | { | |
8619 | /* Emit the new instruction and delete the old anchor. */ | |
7014838c | 8620 | emit_insn_before (gen_rtx_PARALLEL |
8621 | (VOIDmode, | |
8622 | gen_rtvec (2, PATTERN (anchor), | |
8623 | PATTERN (floater))), | |
8624 | anchor); | |
8625 | ||
bd49d362 | 8626 | PUT_CODE (anchor, NOTE); |
8627 | NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED; | |
8628 | NOTE_SOURCE_FILE (anchor) = 0; | |
8629 | ||
8630 | /* Emit a special USE insn for FLOATER, then delete | |
8631 | the floating insn. */ | |
ad851752 | 8632 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 8633 | delete_insn (floater); |
8634 | ||
8635 | continue; | |
8636 | } | |
8637 | else if (floater | |
8638 | && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH) | |
8639 | { | |
8640 | rtx temp; | |
8641 | /* Emit the new_jump instruction and delete the old anchor. */ | |
7014838c | 8642 | temp |
8643 | = emit_jump_insn_before (gen_rtx_PARALLEL | |
8644 | (VOIDmode, | |
8645 | gen_rtvec (2, PATTERN (anchor), | |
8646 | PATTERN (floater))), | |
8647 | anchor); | |
8648 | ||
bd49d362 | 8649 | JUMP_LABEL (temp) = JUMP_LABEL (anchor); |
8650 | PUT_CODE (anchor, NOTE); | |
8651 | NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED; | |
8652 | NOTE_SOURCE_FILE (anchor) = 0; | |
8653 | ||
8654 | /* Emit a special USE insn for FLOATER, then delete | |
8655 | the floating insn. */ | |
ad851752 | 8656 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 8657 | delete_insn (floater); |
8658 | continue; | |
8659 | } | |
8660 | } | |
8661 | } | |
8662 | } | |
8663 | ||
9aadea62 | 8664 | static int |
5c1d8983 | 8665 | pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest, |
8666 | rtx src1, rtx src2) | |
bd49d362 | 8667 | { |
8668 | int insn_code_number; | |
8669 | rtx start, end; | |
8670 | ||
8671 | /* Create a PARALLEL with the patterns of ANCHOR and | |
8672 | FLOATER, try to recognize it, then test constraints | |
8673 | for the resulting pattern. | |
8674 | ||
8675 | If the pattern doesn't match or the constraints | |
8676 | aren't met keep searching for a suitable floater | |
8677 | insn. */ | |
8678 | XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor); | |
8679 | XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater); | |
8680 | INSN_CODE (new) = -1; | |
8681 | insn_code_number = recog_memoized (new); | |
8682 | if (insn_code_number < 0 | |
bf9fd117 | 8683 | || (extract_insn (new), ! constrain_operands (1))) |
bd49d362 | 8684 | return 0; |
8685 | ||
8686 | if (reversed) | |
8687 | { | |
8688 | start = anchor; | |
8689 | end = floater; | |
8690 | } | |
8691 | else | |
8692 | { | |
8693 | start = floater; | |
8694 | end = anchor; | |
8695 | } | |
8696 | ||
8697 | /* There's up to three operands to consider. One | |
8698 | output and two inputs. | |
8699 | ||
8700 | The output must not be used between FLOATER & ANCHOR | |
8701 | exclusive. The inputs must not be set between | |
8702 | FLOATER and ANCHOR exclusive. */ | |
8703 | ||
8704 | if (reg_used_between_p (dest, start, end)) | |
8705 | return 0; | |
8706 | ||
8707 | if (reg_set_between_p (src1, start, end)) | |
8708 | return 0; | |
8709 | ||
8710 | if (reg_set_between_p (src2, start, end)) | |
8711 | return 0; | |
8712 | ||
8713 | /* If we get here, then everything is good. */ | |
8714 | return 1; | |
8715 | } | |
14d18de3 | 8716 | |
a6582a53 | 8717 | /* Return nonzero if references for INSN are delayed. |
14d18de3 | 8718 | |
8719 | Millicode insns are actually function calls with some special | |
8720 | constraints on arguments and register usage. | |
8721 | ||
8722 | Millicode calls always expect their arguments in the integer argument | |
8723 | registers, and always return their result in %r29 (ret1). They | |
2013ddf6 | 8724 | are expected to clobber their arguments, %r1, %r29, and the return |
8725 | pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else. | |
8726 | ||
8727 | This function tells reorg that the references to arguments and | |
8728 | millicode calls do not appear to happen until after the millicode call. | |
8729 | This allows reorg to put insns which set the argument registers into the | |
8730 | delay slot of the millicode call -- thus they act more like traditional | |
8731 | CALL_INSNs. | |
8732 | ||
8733 | Note we can not consider side effects of the insn to be delayed because | |
8734 | the branch and link insn will clobber the return pointer. If we happened | |
8735 | to use the return pointer in the delay slot of the call, then we lose. | |
14d18de3 | 8736 | |
8737 | get_attr_type will try to recognize the given insn, so make sure to | |
8738 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
8739 | in particular. */ | |
8740 | int | |
5c1d8983 | 8741 | insn_refs_are_delayed (rtx insn) |
14d18de3 | 8742 | { |
9840d99d | 8743 | return ((GET_CODE (insn) == INSN |
14d18de3 | 8744 | && GET_CODE (PATTERN (insn)) != SEQUENCE |
8745 | && GET_CODE (PATTERN (insn)) != USE | |
8746 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8747 | && get_attr_type (insn) == TYPE_MILLI)); | |
8748 | } | |
5cb4669a | 8749 | |
58a72cce | 8750 | /* On the HP-PA the value is found in register(s) 28(-29), unless |
8751 | the mode is SF or DF. Then the value is returned in fr4 (32). | |
8752 | ||
8753 | This must perform the same promotions as PROMOTE_MODE, else | |
b8debbe8 | 8754 | TARGET_PROMOTE_FUNCTION_RETURN will not work correctly. |
58a72cce | 8755 | |
8756 | Small structures must be returned in a PARALLEL on PA64 in order | |
8757 | to match the HP Compiler ABI. */ | |
8758 | ||
8759 | rtx | |
5c1d8983 | 8760 | function_value (tree valtype, tree func ATTRIBUTE_UNUSED) |
58a72cce | 8761 | { |
8762 | enum machine_mode valmode; | |
8763 | ||
8764 | /* Aggregates with a size less than or equal to 128 bits are returned | |
8765 | in GR 28(-29). They are left justified. The pad bits are undefined. | |
8766 | Larger aggregates are returned in memory. */ | |
8767 | if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype)) | |
8768 | { | |
8769 | rtx loc[2]; | |
8770 | int i, offset = 0; | |
8771 | int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2; | |
8772 | ||
8773 | for (i = 0; i < ub; i++) | |
8774 | { | |
8775 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
8776 | gen_rtx_REG (DImode, 28 + i), | |
8777 | GEN_INT (offset)); | |
8778 | offset += 8; | |
8779 | } | |
8780 | ||
8781 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc)); | |
8782 | } | |
8783 | ||
8784 | if ((INTEGRAL_TYPE_P (valtype) | |
8785 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
8786 | || POINTER_TYPE_P (valtype)) | |
8787 | valmode = word_mode; | |
8788 | else | |
8789 | valmode = TYPE_MODE (valtype); | |
8790 | ||
8791 | if (TREE_CODE (valtype) == REAL_TYPE | |
8792 | && TYPE_MODE (valtype) != TFmode | |
8793 | && !TARGET_SOFT_FLOAT) | |
8794 | return gen_rtx_REG (valmode, 32); | |
8795 | ||
8796 | return gen_rtx_REG (valmode, 28); | |
8797 | } | |
8798 | ||
5e3c5739 | 8799 | /* Return the location of a parameter that is passed in a register or NULL |
8800 | if the parameter has any component that is passed in memory. | |
8801 | ||
8802 | This is new code and will be pushed to into the net sources after | |
9840d99d | 8803 | further testing. |
5e3c5739 | 8804 | |
8805 | ??? We might want to restructure this so that it looks more like other | |
8806 | ports. */ | |
8807 | rtx | |
5c1d8983 | 8808 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, |
8809 | int named ATTRIBUTE_UNUSED) | |
5e3c5739 | 8810 | { |
8811 | int max_arg_words = (TARGET_64BIT ? 8 : 4); | |
2a075f91 | 8812 | int alignment = 0; |
ac965869 | 8813 | int arg_size; |
5e3c5739 | 8814 | int fpr_reg_base; |
8815 | int gpr_reg_base; | |
8816 | rtx retval; | |
8817 | ||
ac965869 | 8818 | if (mode == VOIDmode) |
8819 | return NULL_RTX; | |
8820 | ||
8821 | arg_size = FUNCTION_ARG_SIZE (mode, type); | |
8822 | ||
8823 | /* If this arg would be passed partially or totally on the stack, then | |
8824 | this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will | |
8825 | handle arguments which are split between regs and stack slots if | |
8826 | the ABI mandates split arguments. */ | |
5e3c5739 | 8827 | if (! TARGET_64BIT) |
8828 | { | |
ac965869 | 8829 | /* The 32-bit ABI does not split arguments. */ |
8830 | if (cum->words + arg_size > max_arg_words) | |
5e3c5739 | 8831 | return NULL_RTX; |
8832 | } | |
8833 | else | |
8834 | { | |
2a075f91 | 8835 | if (arg_size > 1) |
8836 | alignment = cum->words & 1; | |
ac965869 | 8837 | if (cum->words + alignment >= max_arg_words) |
5e3c5739 | 8838 | return NULL_RTX; |
8839 | } | |
8840 | ||
8841 | /* The 32bit ABIs and the 64bit ABIs are rather different, | |
8842 | particularly in their handling of FP registers. We might | |
8843 | be able to cleverly share code between them, but I'm not | |
9aadea62 | 8844 | going to bother in the hope that splitting them up results |
2a075f91 | 8845 | in code that is more easily understood. */ |
5e3c5739 | 8846 | |
5e3c5739 | 8847 | if (TARGET_64BIT) |
8848 | { | |
8849 | /* Advance the base registers to their current locations. | |
8850 | ||
8851 | Remember, gprs grow towards smaller register numbers while | |
2a075f91 | 8852 | fprs grow to higher register numbers. Also remember that |
8853 | although FP regs are 32-bit addressable, we pretend that | |
8854 | the registers are 64-bits wide. */ | |
5e3c5739 | 8855 | gpr_reg_base = 26 - cum->words; |
8856 | fpr_reg_base = 32 + cum->words; | |
9840d99d | 8857 | |
ac965869 | 8858 | /* Arguments wider than one word and small aggregates need special |
8859 | treatment. */ | |
8860 | if (arg_size > 1 | |
8861 | || mode == BLKmode | |
8862 | || (type && AGGREGATE_TYPE_P (type))) | |
5e3c5739 | 8863 | { |
2a075f91 | 8864 | /* Double-extended precision (80-bit), quad-precision (128-bit) |
8865 | and aggregates including complex numbers are aligned on | |
8866 | 128-bit boundaries. The first eight 64-bit argument slots | |
8867 | are associated one-to-one, with general registers r26 | |
8868 | through r19, and also with floating-point registers fr4 | |
8869 | through fr11. Arguments larger than one word are always | |
ac965869 | 8870 | passed in general registers. |
8871 | ||
8872 | Using a PARALLEL with a word mode register results in left | |
8873 | justified data on a big-endian target. */ | |
2a075f91 | 8874 | |
8875 | rtx loc[8]; | |
8876 | int i, offset = 0, ub = arg_size; | |
8877 | ||
8878 | /* Align the base register. */ | |
8879 | gpr_reg_base -= alignment; | |
8880 | ||
8881 | ub = MIN (ub, max_arg_words - cum->words - alignment); | |
8882 | for (i = 0; i < ub; i++) | |
5e3c5739 | 8883 | { |
2a075f91 | 8884 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, |
8885 | gen_rtx_REG (DImode, gpr_reg_base), | |
8886 | GEN_INT (offset)); | |
8887 | gpr_reg_base -= 1; | |
8888 | offset += 8; | |
5e3c5739 | 8889 | } |
2a075f91 | 8890 | |
8891 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc)); | |
5e3c5739 | 8892 | } |
ac965869 | 8893 | } |
5e3c5739 | 8894 | else |
8895 | { | |
8896 | /* If the argument is larger than a word, then we know precisely | |
8897 | which registers we must use. */ | |
2a075f91 | 8898 | if (arg_size > 1) |
5e3c5739 | 8899 | { |
8900 | if (cum->words) | |
8901 | { | |
8902 | gpr_reg_base = 23; | |
8903 | fpr_reg_base = 38; | |
8904 | } | |
8905 | else | |
8906 | { | |
8907 | gpr_reg_base = 25; | |
8908 | fpr_reg_base = 34; | |
8909 | } | |
ac965869 | 8910 | |
8911 | /* Structures 5 to 8 bytes in size are passed in the general | |
8912 | registers in the same manner as other non floating-point | |
8913 | objects. The data is right-justified and zero-extended | |
9f0b40a7 | 8914 | to 64 bits. This is opposite to the normal justification |
8915 | used on big endian targets and requires special treatment. | |
8916 | We now define BLOCK_REG_PADDING to pad these objects. */ | |
ac965869 | 8917 | if (mode == BLKmode) |
8918 | { | |
58a72cce | 8919 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, |
8920 | gen_rtx_REG (DImode, gpr_reg_base), | |
8921 | const0_rtx); | |
8922 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc)); | |
ac965869 | 8923 | } |
5e3c5739 | 8924 | } |
8925 | else | |
8926 | { | |
8927 | /* We have a single word (32 bits). A simple computation | |
8928 | will get us the register #s we need. */ | |
8929 | gpr_reg_base = 26 - cum->words; | |
8930 | fpr_reg_base = 32 + 2 * cum->words; | |
8931 | } | |
8932 | } | |
8933 | ||
9503b0f7 | 8934 | /* Determine if the argument needs to be passed in both general and |
5e3c5739 | 8935 | floating point registers. */ |
9503b0f7 | 8936 | if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32) |
8937 | /* If we are doing soft-float with portable runtime, then there | |
8938 | is no need to worry about FP regs. */ | |
f336e0bc | 8939 | && !TARGET_SOFT_FLOAT |
9503b0f7 | 8940 | /* The parameter must be some kind of float, else we can just |
8941 | pass it in integer registers. */ | |
8942 | && FLOAT_MODE_P (mode) | |
8943 | /* The target function must not have a prototype. */ | |
8944 | && cum->nargs_prototype <= 0 | |
8945 | /* libcalls do not need to pass items in both FP and general | |
8946 | registers. */ | |
8947 | && type != NULL_TREE | |
f336e0bc | 8948 | /* All this hair applies to "outgoing" args only. This includes |
8949 | sibcall arguments setup with FUNCTION_INCOMING_ARG. */ | |
8950 | && !cum->incoming) | |
9503b0f7 | 8951 | /* Also pass outgoing floating arguments in both registers in indirect |
8952 | calls with the 32 bit ABI and the HP assembler since there is no | |
8953 | way to the specify argument locations in static functions. */ | |
f336e0bc | 8954 | || (!TARGET_64BIT |
8955 | && !TARGET_GAS | |
8956 | && !cum->incoming | |
9503b0f7 | 8957 | && cum->indirect |
8958 | && FLOAT_MODE_P (mode))) | |
5e3c5739 | 8959 | { |
8960 | retval | |
8961 | = gen_rtx_PARALLEL | |
8962 | (mode, | |
8963 | gen_rtvec (2, | |
8964 | gen_rtx_EXPR_LIST (VOIDmode, | |
8965 | gen_rtx_REG (mode, fpr_reg_base), | |
8966 | const0_rtx), | |
8967 | gen_rtx_EXPR_LIST (VOIDmode, | |
8968 | gen_rtx_REG (mode, gpr_reg_base), | |
8969 | const0_rtx))); | |
8970 | } | |
8971 | else | |
8972 | { | |
8973 | /* See if we should pass this parameter in a general register. */ | |
8974 | if (TARGET_SOFT_FLOAT | |
8975 | /* Indirect calls in the normal 32bit ABI require all arguments | |
8976 | to be passed in general registers. */ | |
8977 | || (!TARGET_PORTABLE_RUNTIME | |
8978 | && !TARGET_64BIT | |
a052da6f | 8979 | && !TARGET_ELF32 |
5e3c5739 | 8980 | && cum->indirect) |
8981 | /* If the parameter is not a floating point parameter, then | |
8982 | it belongs in GPRs. */ | |
8983 | || !FLOAT_MODE_P (mode)) | |
8984 | retval = gen_rtx_REG (mode, gpr_reg_base); | |
8985 | else | |
8986 | retval = gen_rtx_REG (mode, fpr_reg_base); | |
8987 | } | |
8988 | return retval; | |
8989 | } | |
8990 | ||
8991 | ||
8992 | /* If this arg would be passed totally in registers or totally on the stack, | |
8993 | then this routine should return zero. It is currently called only for | |
6dc3b0d9 | 8994 | the 64-bit target. */ |
5e3c5739 | 8995 | int |
5c1d8983 | 8996 | function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
8997 | tree type, int named ATTRIBUTE_UNUSED) | |
5e3c5739 | 8998 | { |
b7d86581 | 8999 | unsigned int max_arg_words = 8; |
9000 | unsigned int offset = 0; | |
5e3c5739 | 9001 | |
b7d86581 | 9002 | if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1)) |
5e3c5739 | 9003 | offset = 1; |
9004 | ||
b7d86581 | 9005 | if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words) |
6dc3b0d9 | 9006 | /* Arg fits fully into registers. */ |
5e3c5739 | 9007 | return 0; |
9840d99d | 9008 | else if (cum->words + offset >= max_arg_words) |
6dc3b0d9 | 9009 | /* Arg fully on the stack. */ |
5e3c5739 | 9010 | return 0; |
9011 | else | |
6dc3b0d9 | 9012 | /* Arg is split. */ |
5e3c5739 | 9013 | return max_arg_words - cum->words - offset; |
5e3c5739 | 9014 | } |
9015 | ||
9016 | ||
9017 | /* Return 1 if this is a comparison operator. This allows the use of | |
9018 | MATCH_OPERATOR to recognize all the branch insns. */ | |
9019 | ||
9020 | int | |
5c1d8983 | 9021 | cmpib_comparison_operator (rtx op, enum machine_mode mode) |
5e3c5739 | 9022 | { |
9023 | return ((mode == VOIDmode || GET_MODE (op) == mode) | |
9024 | && (GET_CODE (op) == EQ | |
9025 | || GET_CODE (op) == NE | |
9026 | || GET_CODE (op) == GT | |
5e3c5739 | 9027 | || GET_CODE (op) == GTU |
32509e56 | 9028 | || GET_CODE (op) == GE |
5e3c5739 | 9029 | || GET_CODE (op) == LT |
9030 | || GET_CODE (op) == LE | |
9031 | || GET_CODE (op) == LEU)); | |
9032 | } | |
9033 | ||
52470889 | 9034 | /* On hpux10, the linker will give an error if we have a reference |
9035 | in the read-only data section to a symbol defined in a shared | |
9036 | library. Therefore, expressions that might require a reloc can | |
9037 | not be placed in the read-only data section. */ | |
9038 | ||
9039 | static void | |
b572d1a5 | 9040 | pa_select_section (tree exp, int reloc, |
9041 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
52470889 | 9042 | { |
9043 | if (TREE_CODE (exp) == VAR_DECL | |
9044 | && TREE_READONLY (exp) | |
9045 | && !TREE_THIS_VOLATILE (exp) | |
9046 | && DECL_INITIAL (exp) | |
9047 | && (DECL_INITIAL (exp) == error_mark_node | |
9048 | || TREE_CONSTANT (DECL_INITIAL (exp))) | |
9049 | && !reloc) | |
9050 | readonly_data_section (); | |
9051 | else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c' | |
52470889 | 9052 | && !reloc) |
9053 | readonly_data_section (); | |
9054 | else | |
9055 | data_section (); | |
9056 | } | |
1f3233d1 | 9057 | |
67c1e638 | 9058 | static void |
5c1d8983 | 9059 | pa_globalize_label (FILE *stream, const char *name) |
67c1e638 | 9060 | { |
9061 | /* We only handle DATA objects here, functions are globalized in | |
9062 | ASM_DECLARE_FUNCTION_NAME. */ | |
9063 | if (! FUNCTION_NAME_P (name)) | |
9064 | { | |
9065 | fputs ("\t.EXPORT ", stream); | |
9066 | assemble_name (stream, name); | |
9067 | fputs (",DATA\n", stream); | |
9068 | } | |
9069 | } | |
b8debbe8 | 9070 | |
6644435d | 9071 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
9072 | ||
b8debbe8 | 9073 | static rtx |
9074 | pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
9075 | int incoming ATTRIBUTE_UNUSED) | |
9076 | { | |
9077 | return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM); | |
9078 | } | |
9079 | ||
6644435d | 9080 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
9081 | ||
b8debbe8 | 9082 | bool |
9083 | pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
9084 | { | |
9085 | /* SOM ABI says that objects larger than 64 bits are returned in memory. | |
9086 | PA64 ABI says that objects larger than 128 bits are returned in memory. | |
9087 | Note, int_size_in_bytes can return -1 if the size of the object is | |
9088 | variable or larger than the maximum value that can be expressed as | |
9089 | a HOST_WIDE_INT. It can also return zero for an empty type. The | |
9090 | simplest way to handle variable and empty types is to pass them in | |
9091 | memory. This avoids problems in defining the boundaries of argument | |
9092 | slots, allocating registers, etc. */ | |
9093 | return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8) | |
9094 | || int_size_in_bytes (type) <= 0); | |
9095 | } | |
9096 | ||
1f3233d1 | 9097 | #include "gt-pa.h" |