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87ad11b0 | 1 | /* Subroutines for insn-output.c for HPPA. |
a9ac13e4 | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
7cf0dbf3 | 3 | 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
cfaf579d | 4 | Free Software Foundation, Inc. |
87ad11b0 | 5 | Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c |
6 | ||
5c1d8983 | 7 | This file is part of GCC. |
87ad11b0 | 8 | |
5c1d8983 | 9 | GCC is free software; you can redistribute it and/or modify |
87ad11b0 | 10 | it under the terms of the GNU General Public License as published by |
038d1e19 | 11 | the Free Software Foundation; either version 3, or (at your option) |
87ad11b0 | 12 | any later version. |
13 | ||
5c1d8983 | 14 | GCC is distributed in the hope that it will be useful, |
87ad11b0 | 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
038d1e19 | 20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
87ad11b0 | 22 | |
87ad11b0 | 23 | #include "config.h" |
b1ca791d | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
87ad11b0 | 27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
87ad11b0 | 30 | #include "insn-config.h" |
31 | #include "conditions.h" | |
87ad11b0 | 32 | #include "insn-attr.h" |
33 | #include "flags.h" | |
34 | #include "tree.h" | |
9d2d8bd6 | 35 | #include "output.h" |
a584fe8a | 36 | #include "except.h" |
32509e56 | 37 | #include "expr.h" |
d8fc4d0b | 38 | #include "optabs.h" |
d8fc4d0b | 39 | #include "reload.h" |
d7e2f694 | 40 | #include "integrate.h" |
0a893c29 | 41 | #include "function.h" |
0b205f4c | 42 | #include "diagnostic-core.h" |
b1ca791d | 43 | #include "toplev.h" |
5cb4669a | 44 | #include "ggc.h" |
611a88e1 | 45 | #include "recog.h" |
a584fe8a | 46 | #include "predict.h" |
611a88e1 | 47 | #include "tm_p.h" |
a767736d | 48 | #include "target.h" |
49 | #include "target-def.h" | |
a179d6b2 | 50 | #include "df.h" |
87ad11b0 | 51 | |
cde3e16c | 52 | /* Return nonzero if there is a bypass for the output of |
53 | OUT_INSN and the fp store IN_INSN. */ | |
54 | int | |
5c1d8983 | 55 | hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn) |
cde3e16c | 56 | { |
57 | enum machine_mode store_mode; | |
58 | enum machine_mode other_mode; | |
59 | rtx set; | |
60 | ||
61 | if (recog_memoized (in_insn) < 0 | |
7d9f62cc | 62 | || (get_attr_type (in_insn) != TYPE_FPSTORE |
63 | && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD) | |
cde3e16c | 64 | || recog_memoized (out_insn) < 0) |
65 | return 0; | |
66 | ||
67 | store_mode = GET_MODE (SET_SRC (PATTERN (in_insn))); | |
68 | ||
69 | set = single_set (out_insn); | |
70 | if (!set) | |
71 | return 0; | |
72 | ||
73 | other_mode = GET_MODE (SET_SRC (set)); | |
74 | ||
75 | return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode)); | |
76 | } | |
77 | ||
78 | ||
cc858176 | 79 | #ifndef DO_FRAME_NOTES |
80 | #ifdef INCOMING_RETURN_ADDR_RTX | |
81 | #define DO_FRAME_NOTES 1 | |
82 | #else | |
83 | #define DO_FRAME_NOTES 0 | |
84 | #endif | |
85 | #endif | |
86 | ||
93d3ee56 | 87 | static void pa_option_override (void); |
dbd3d89d | 88 | static void copy_reg_pointer (rtx, rtx); |
320e1276 | 89 | static void fix_range (const char *); |
bd57250e | 90 | static bool pa_handle_option (size_t, const char *, int); |
93d3ee56 | 91 | static int hppa_register_move_cost (enum machine_mode mode, reg_class_t, |
92 | reg_class_t); | |
f529eb25 | 93 | static int hppa_address_cost (rtx, bool); |
94 | static bool hppa_rtx_costs (rtx, int, int, int *, bool); | |
5c1d8983 | 95 | static inline rtx force_mode (enum machine_mode, rtx); |
96 | static void pa_reorg (void); | |
97 | static void pa_combine_instructions (void); | |
98 | static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx); | |
372b3fe2 | 99 | static bool forward_branch_p (rtx); |
5c1d8983 | 100 | static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *); |
008c057d | 101 | static int compute_movmem_length (rtx); |
102 | static int compute_clrmem_length (rtx); | |
5c1d8983 | 103 | static bool pa_assemble_integer (rtx, unsigned int, int); |
104 | static void remove_useless_addtr_insns (int); | |
6bcdc1fb | 105 | static void store_reg (int, HOST_WIDE_INT, int); |
106 | static void store_reg_modify (int, int, HOST_WIDE_INT); | |
107 | static void load_reg (int, HOST_WIDE_INT, int); | |
108 | static void set_reg_plus_d (int, int, HOST_WIDE_INT, int); | |
cb0b8817 | 109 | static rtx pa_function_value (const_tree, const_tree, bool); |
93d3ee56 | 110 | static rtx pa_libcall_value (enum machine_mode, const_rtx); |
111 | static bool pa_function_value_regno_p (const unsigned int); | |
5c1d8983 | 112 | static void pa_output_function_prologue (FILE *, HOST_WIDE_INT); |
21a47bc9 | 113 | static void update_total_code_bytes (unsigned int); |
5c1d8983 | 114 | static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT); |
115 | static int pa_adjust_cost (rtx, rtx, rtx, int); | |
116 | static int pa_adjust_priority (rtx, int); | |
117 | static int pa_issue_rate (void); | |
2f14b1f9 | 118 | static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED; |
119 | static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT) | |
52470889 | 120 | ATTRIBUTE_UNUSED; |
5c1d8983 | 121 | static void pa_encode_section_info (tree, rtx, int); |
122 | static const char *pa_strip_name_encoding (const char *); | |
123 | static bool pa_function_ok_for_sibcall (tree, tree); | |
124 | static void pa_globalize_label (FILE *, const char *) | |
63b8cd48 | 125 | ATTRIBUTE_UNUSED; |
5c1d8983 | 126 | static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
127 | HOST_WIDE_INT, tree); | |
de419443 | 128 | #if !defined(USE_COLLECT2) |
5c1d8983 | 129 | static void pa_asm_out_constructor (rtx, int); |
130 | static void pa_asm_out_destructor (rtx, int); | |
de419443 | 131 | #endif |
5c1d8983 | 132 | static void pa_init_builtins (void); |
b8debbe8 | 133 | static rtx hppa_builtin_saveregs (void); |
8a58ed0a | 134 | static void hppa_va_start (tree, rtx); |
75a70cf9 | 135 | static tree hppa_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); |
2b1e7cc3 | 136 | static bool pa_scalar_mode_supported_p (enum machine_mode); |
a9f1838b | 137 | static bool pa_commutative_p (const_rtx x, int outer_code); |
5c1d8983 | 138 | static void copy_fp_args (rtx) ATTRIBUTE_UNUSED; |
139 | static int length_fp_args (rtx) ATTRIBUTE_UNUSED; | |
41e3a0c7 | 140 | static rtx hppa_legitimize_address (rtx, rtx, enum machine_mode); |
5c1d8983 | 141 | static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED; |
142 | static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED; | |
143 | static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED; | |
144 | static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED; | |
145 | static void pa_elf_file_start (void) ATTRIBUTE_UNUSED; | |
146 | static void pa_som_file_start (void) ATTRIBUTE_UNUSED; | |
147 | static void pa_linux_file_start (void) ATTRIBUTE_UNUSED; | |
148 | static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED; | |
149 | static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED; | |
150 | static void output_deferred_plabels (void); | |
bb1bc2ca | 151 | static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED; |
5f43b4f6 | 152 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
153 | static void pa_hpux_file_end (void); | |
154 | #endif | |
f2f543a3 | 155 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
156 | static void pa_hpux_init_libfuncs (void); | |
157 | #endif | |
b8debbe8 | 158 | static rtx pa_struct_value_rtx (tree, int); |
f054eb3c | 159 | static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
fb80456a | 160 | const_tree, bool); |
f054eb3c | 161 | static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
162 | tree, bool); | |
916c9cef | 163 | static struct machine_function * pa_init_machine_status (void); |
964229b7 | 164 | static reg_class_t pa_secondary_reload (bool, rtx, reg_class_t, |
165 | enum machine_mode, | |
166 | secondary_reload_info *); | |
df6b92e4 | 167 | static void pa_extra_live_on_entry (bitmap); |
15a27966 | 168 | static enum machine_mode pa_promote_function_mode (const_tree, |
169 | enum machine_mode, int *, | |
170 | const_tree, int); | |
9d3ddb8f | 171 | |
623a97bc | 172 | static void pa_asm_trampoline_template (FILE *); |
173 | static void pa_trampoline_init (rtx, tree, rtx); | |
174 | static rtx pa_trampoline_adjust_address (rtx); | |
c731c4f5 | 175 | static rtx pa_delegitimize_address (rtx); |
93d3ee56 | 176 | static bool pa_print_operand_punct_valid_p (unsigned char); |
623a97bc | 177 | |
2f14b1f9 | 178 | /* The following extra sections are only used for SOM. */ |
179 | static GTY(()) section *som_readonly_data_section; | |
180 | static GTY(()) section *som_one_only_readonly_data_section; | |
181 | static GTY(()) section *som_one_only_data_section; | |
182 | ||
320e1276 | 183 | /* Which cpu we are scheduling for. */ |
bd57250e | 184 | enum processor_type pa_cpu = TARGET_SCHED_DEFAULT; |
8ab32933 | 185 | |
186 | /* The UNIX standard to use for predefines and linking. */ | |
bd57250e | 187 | int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993; |
8ab32933 | 188 | |
a9960cdc | 189 | /* Counts for the number of callee-saved general and floating point |
190 | registers which were saved by the current function's prologue. */ | |
191 | static int gr_saved, fr_saved; | |
192 | ||
df6b92e4 | 193 | /* Boolean indicating whether the return pointer was saved by the |
194 | current function's prologue. */ | |
195 | static bool rp_saved; | |
196 | ||
5c1d8983 | 197 | static rtx find_addr_reg (rtx); |
87ad11b0 | 198 | |
2247cc5f | 199 | /* Keep track of the number of bytes we have output in the CODE subspace |
06ddb6f8 | 200 | during this compilation so we'll know when to emit inline long-calls. */ |
ece88821 | 201 | unsigned long total_code_bytes; |
06ddb6f8 | 202 | |
2247cc5f | 203 | /* The last address of the previous function plus the number of bytes in |
204 | associated thunks that have been output. This is used to determine if | |
205 | a thunk can use an IA-relative branch to reach its target function. */ | |
21a47bc9 | 206 | static unsigned int last_address; |
2247cc5f | 207 | |
e3f53689 | 208 | /* Variables to handle plabels that we discover are necessary at assembly |
01cc3b75 | 209 | output time. They are output after the current function. */ |
fb1e4f4a | 210 | struct GTY(()) deferred_plabel |
e3f53689 | 211 | { |
212 | rtx internal_label; | |
5f43b4f6 | 213 | rtx symbol; |
1f3233d1 | 214 | }; |
215 | static GTY((length ("n_deferred_plabels"))) struct deferred_plabel * | |
216 | deferred_plabels; | |
e11bd7e5 | 217 | static size_t n_deferred_plabels = 0; |
f6940372 | 218 | |
a767736d | 219 | \f |
220 | /* Initialize the GCC target structure. */ | |
58356836 | 221 | |
93d3ee56 | 222 | #undef TARGET_OPTION_OVERRIDE |
223 | #define TARGET_OPTION_OVERRIDE pa_option_override | |
224 | ||
58356836 | 225 | #undef TARGET_ASM_ALIGNED_HI_OP |
226 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
227 | #undef TARGET_ASM_ALIGNED_SI_OP | |
228 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
229 | #undef TARGET_ASM_ALIGNED_DI_OP | |
230 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
231 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
232 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
233 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
234 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
235 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
236 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
237 | #undef TARGET_ASM_INTEGER | |
238 | #define TARGET_ASM_INTEGER pa_assemble_integer | |
239 | ||
17d9b0c3 | 240 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
241 | #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue | |
242 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
243 | #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue | |
e3f53689 | 244 | |
cb0b8817 | 245 | #undef TARGET_FUNCTION_VALUE |
246 | #define TARGET_FUNCTION_VALUE pa_function_value | |
93d3ee56 | 247 | #undef TARGET_LIBCALL_VALUE |
248 | #define TARGET_LIBCALL_VALUE pa_libcall_value | |
249 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
250 | #define TARGET_FUNCTION_VALUE_REGNO_P pa_function_value_regno_p | |
cb0b8817 | 251 | |
41e3a0c7 | 252 | #undef TARGET_LEGITIMIZE_ADDRESS |
253 | #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address | |
254 | ||
747af5e7 | 255 | #undef TARGET_SCHED_ADJUST_COST |
256 | #define TARGET_SCHED_ADJUST_COST pa_adjust_cost | |
257 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
258 | #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority | |
259 | #undef TARGET_SCHED_ISSUE_RATE | |
260 | #define TARGET_SCHED_ISSUE_RATE pa_issue_rate | |
261 | ||
7811991d | 262 | #undef TARGET_ENCODE_SECTION_INFO |
263 | #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info | |
7b4a38a6 | 264 | #undef TARGET_STRIP_NAME_ENCODING |
265 | #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding | |
7811991d | 266 | |
805e22b2 | 267 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
268 | #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall | |
269 | ||
280566a7 | 270 | #undef TARGET_COMMUTATIVE_P |
271 | #define TARGET_COMMUTATIVE_P pa_commutative_p | |
272 | ||
6988553d | 273 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
274 | #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk | |
eb344f43 | 275 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
276 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
6988553d | 277 | |
f6940372 | 278 | #undef TARGET_ASM_FILE_END |
5f43b4f6 | 279 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
280 | #define TARGET_ASM_FILE_END pa_hpux_file_end | |
281 | #else | |
f6940372 | 282 | #define TARGET_ASM_FILE_END output_deferred_plabels |
5f43b4f6 | 283 | #endif |
f6940372 | 284 | |
93d3ee56 | 285 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P |
286 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pa_print_operand_punct_valid_p | |
287 | ||
de419443 | 288 | #if !defined(USE_COLLECT2) |
289 | #undef TARGET_ASM_CONSTRUCTOR | |
290 | #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor | |
291 | #undef TARGET_ASM_DESTRUCTOR | |
292 | #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor | |
293 | #endif | |
294 | ||
bd57250e | 295 | #undef TARGET_DEFAULT_TARGET_FLAGS |
296 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT) | |
297 | #undef TARGET_HANDLE_OPTION | |
298 | #define TARGET_HANDLE_OPTION pa_handle_option | |
299 | ||
ffa8918b | 300 | #undef TARGET_INIT_BUILTINS |
301 | #define TARGET_INIT_BUILTINS pa_init_builtins | |
302 | ||
93d3ee56 | 303 | #undef TARGET_REGISTER_MOVE_COST |
304 | #define TARGET_REGISTER_MOVE_COST hppa_register_move_cost | |
fab7adbf | 305 | #undef TARGET_RTX_COSTS |
306 | #define TARGET_RTX_COSTS hppa_rtx_costs | |
ec0457a8 | 307 | #undef TARGET_ADDRESS_COST |
308 | #define TARGET_ADDRESS_COST hppa_address_cost | |
fab7adbf | 309 | |
2efea8c0 | 310 | #undef TARGET_MACHINE_DEPENDENT_REORG |
311 | #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg | |
312 | ||
f2f543a3 | 313 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
314 | #undef TARGET_INIT_LIBFUNCS | |
315 | #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs | |
316 | #endif | |
317 | ||
3b2411a8 | 318 | #undef TARGET_PROMOTE_FUNCTION_MODE |
319 | #define TARGET_PROMOTE_FUNCTION_MODE pa_promote_function_mode | |
b8debbe8 | 320 | #undef TARGET_PROMOTE_PROTOTYPES |
fb80456a | 321 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
b8debbe8 | 322 | |
323 | #undef TARGET_STRUCT_VALUE_RTX | |
324 | #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx | |
325 | #undef TARGET_RETURN_IN_MEMORY | |
326 | #define TARGET_RETURN_IN_MEMORY pa_return_in_memory | |
0336f0f0 | 327 | #undef TARGET_MUST_PASS_IN_STACK |
328 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
b981d932 | 329 | #undef TARGET_PASS_BY_REFERENCE |
330 | #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference | |
13f08ee7 | 331 | #undef TARGET_CALLEE_COPIES |
332 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
f054eb3c | 333 | #undef TARGET_ARG_PARTIAL_BYTES |
334 | #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes | |
b8debbe8 | 335 | |
336 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
337 | #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs | |
8a58ed0a | 338 | #undef TARGET_EXPAND_BUILTIN_VA_START |
339 | #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start | |
4c33eb68 | 340 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
341 | #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr | |
b8debbe8 | 342 | |
2b1e7cc3 | 343 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
344 | #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p | |
345 | ||
716b2c5a | 346 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
347 | #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p | |
348 | ||
5655a0e5 | 349 | #undef TARGET_SECONDARY_RELOAD |
350 | #define TARGET_SECONDARY_RELOAD pa_secondary_reload | |
351 | ||
df6b92e4 | 352 | #undef TARGET_EXTRA_LIVE_ON_ENTRY |
353 | #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry | |
354 | ||
623a97bc | 355 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
356 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE pa_asm_trampoline_template | |
357 | #undef TARGET_TRAMPOLINE_INIT | |
358 | #define TARGET_TRAMPOLINE_INIT pa_trampoline_init | |
359 | #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS | |
360 | #define TARGET_TRAMPOLINE_ADJUST_ADDRESS pa_trampoline_adjust_address | |
c731c4f5 | 361 | #undef TARGET_DELEGITIMIZE_ADDRESS |
362 | #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address | |
623a97bc | 363 | |
57e4bbfb | 364 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 365 | \f |
320e1276 | 366 | /* Parse the -mfixed-range= option string. */ |
367 | ||
368 | static void | |
369 | fix_range (const char *const_str) | |
370 | { | |
371 | int i, first, last; | |
372 | char *str, *dash, *comma; | |
373 | ||
374 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and | |
375 | REG2 are either register names or register numbers. The effect | |
376 | of this option is to mark the registers in the range from REG1 to | |
377 | REG2 as ``fixed'' so they won't be used by the compiler. This is | |
765cebfc | 378 | used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */ |
320e1276 | 379 | |
380 | i = strlen (const_str); | |
381 | str = (char *) alloca (i + 1); | |
382 | memcpy (str, const_str, i + 1); | |
383 | ||
384 | while (1) | |
385 | { | |
386 | dash = strchr (str, '-'); | |
387 | if (!dash) | |
388 | { | |
c3ceba8e | 389 | warning (0, "value of -mfixed-range must have form REG1-REG2"); |
320e1276 | 390 | return; |
391 | } | |
392 | *dash = '\0'; | |
393 | ||
394 | comma = strchr (dash + 1, ','); | |
395 | if (comma) | |
396 | *comma = '\0'; | |
397 | ||
398 | first = decode_reg_name (str); | |
399 | if (first < 0) | |
400 | { | |
c3ceba8e | 401 | warning (0, "unknown register name: %s", str); |
320e1276 | 402 | return; |
403 | } | |
404 | ||
405 | last = decode_reg_name (dash + 1); | |
406 | if (last < 0) | |
407 | { | |
c3ceba8e | 408 | warning (0, "unknown register name: %s", dash + 1); |
320e1276 | 409 | return; |
410 | } | |
411 | ||
412 | *dash = '-'; | |
413 | ||
414 | if (first > last) | |
415 | { | |
c3ceba8e | 416 | warning (0, "%s-%s is an empty range", str, dash + 1); |
320e1276 | 417 | return; |
418 | } | |
419 | ||
420 | for (i = first; i <= last; ++i) | |
421 | fixed_regs[i] = call_used_regs[i] = 1; | |
422 | ||
423 | if (!comma) | |
424 | break; | |
425 | ||
426 | *comma = ','; | |
427 | str = comma + 1; | |
428 | } | |
429 | ||
430 | /* Check if all floating point registers have been fixed. */ | |
431 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
432 | if (!fixed_regs[i]) | |
433 | break; | |
434 | ||
435 | if (i > FP_REG_LAST) | |
436 | target_flags |= MASK_DISABLE_FPREGS; | |
437 | } | |
438 | ||
bd57250e | 439 | /* Implement TARGET_HANDLE_OPTION. */ |
c7a4e712 | 440 | |
bd57250e | 441 | static bool |
442 | pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
443 | { | |
444 | switch (code) | |
4dc42288 | 445 | { |
bd57250e | 446 | case OPT_mnosnake: |
447 | case OPT_mpa_risc_1_0: | |
448 | case OPT_march_1_0: | |
4dc42288 | 449 | target_flags &= ~(MASK_PA_11 | MASK_PA_20); |
bd57250e | 450 | return true; |
451 | ||
452 | case OPT_msnake: | |
453 | case OPT_mpa_risc_1_1: | |
454 | case OPT_march_1_1: | |
4dc42288 | 455 | target_flags &= ~MASK_PA_20; |
456 | target_flags |= MASK_PA_11; | |
bd57250e | 457 | return true; |
4dc42288 | 458 | |
bd57250e | 459 | case OPT_mpa_risc_2_0: |
460 | case OPT_march_2_0: | |
461 | target_flags |= MASK_PA_11 | MASK_PA_20; | |
462 | return true; | |
463 | ||
464 | case OPT_mschedule_: | |
465 | if (strcmp (arg, "8000") == 0) | |
466 | pa_cpu = PROCESSOR_8000; | |
467 | else if (strcmp (arg, "7100") == 0) | |
468 | pa_cpu = PROCESSOR_7100; | |
469 | else if (strcmp (arg, "700") == 0) | |
470 | pa_cpu = PROCESSOR_700; | |
471 | else if (strcmp (arg, "7100LC") == 0) | |
472 | pa_cpu = PROCESSOR_7100LC; | |
473 | else if (strcmp (arg, "7200") == 0) | |
474 | pa_cpu = PROCESSOR_7200; | |
475 | else if (strcmp (arg, "7300") == 0) | |
476 | pa_cpu = PROCESSOR_7300; | |
8ab32933 | 477 | else |
bd57250e | 478 | return false; |
479 | return true; | |
8ab32933 | 480 | |
bd57250e | 481 | case OPT_mfixed_range_: |
482 | fix_range (arg); | |
483 | return true; | |
320e1276 | 484 | |
bd57250e | 485 | #if TARGET_HPUX |
486 | case OPT_munix_93: | |
487 | flag_pa_unix = 1993; | |
488 | return true; | |
489 | #endif | |
490 | ||
491 | #if TARGET_HPUX_10_10 | |
492 | case OPT_munix_95: | |
493 | flag_pa_unix = 1995; | |
494 | return true; | |
495 | #endif | |
496 | ||
497 | #if TARGET_HPUX_11_11 | |
498 | case OPT_munix_98: | |
499 | flag_pa_unix = 1998; | |
500 | return true; | |
501 | #endif | |
502 | ||
503 | default: | |
504 | return true; | |
505 | } | |
506 | } | |
507 | ||
93d3ee56 | 508 | /* Implement the TARGET_OPTION_OVERRIDE hook. */ |
509 | ||
510 | static void | |
511 | pa_option_override (void) | |
bd57250e | 512 | { |
7c5101fc | 513 | /* Unconditional branches in the delay slot are not compatible with dwarf2 |
514 | call frame information. There is no benefit in using this optimization | |
515 | on PA8000 and later processors. */ | |
516 | if (pa_cpu >= PROCESSOR_8000 | |
517 | || (! USING_SJLJ_EXCEPTIONS && flag_exceptions) | |
518 | || flag_unwind_tables) | |
519 | target_flags &= ~MASK_JUMP_IN_DELAY; | |
520 | ||
c7a4e712 | 521 | if (flag_pic && TARGET_PORTABLE_RUNTIME) |
522 | { | |
0a81f5a0 | 523 | warning (0, "PIC code generation is not supported in the portable runtime model"); |
c7a4e712 | 524 | } |
525 | ||
b29897dd | 526 | if (flag_pic && TARGET_FAST_INDIRECT_CALLS) |
c7a4e712 | 527 | { |
0a81f5a0 | 528 | warning (0, "PIC code generation is not compatible with fast indirect calls"); |
c7a4e712 | 529 | } |
751e64a1 | 530 | |
5bd7b548 | 531 | if (! TARGET_GAS && write_symbols != NO_DEBUG) |
532 | { | |
c3ceba8e | 533 | warning (0, "-g is only supported when using GAS on this processor,"); |
534 | warning (0, "-g option disabled"); | |
5bd7b548 | 535 | write_symbols = NO_DEBUG; |
536 | } | |
5cb4669a | 537 | |
fc44315f | 538 | /* We only support the "big PIC" model now. And we always generate PIC |
539 | code when in 64bit mode. */ | |
540 | if (flag_pic == 1 || TARGET_64BIT) | |
5e3c5739 | 541 | flag_pic = 2; |
542 | ||
1724df0b | 543 | /* Disable -freorder-blocks-and-partition as we don't support hot and |
544 | cold partitioning. */ | |
545 | if (flag_reorder_blocks_and_partition) | |
546 | { | |
547 | inform (input_location, | |
548 | "-freorder-blocks-and-partition does not work " | |
549 | "on this architecture"); | |
550 | flag_reorder_blocks_and_partition = 0; | |
551 | flag_reorder_blocks = 1; | |
552 | } | |
553 | ||
58356836 | 554 | /* We can't guarantee that .dword is available for 32-bit targets. */ |
555 | if (UNITS_PER_WORD == 4) | |
556 | targetm.asm_out.aligned_op.di = NULL; | |
557 | ||
558 | /* The unaligned ops are only available when using GAS. */ | |
559 | if (!TARGET_GAS) | |
560 | { | |
561 | targetm.asm_out.unaligned_op.hi = NULL; | |
562 | targetm.asm_out.unaligned_op.si = NULL; | |
563 | targetm.asm_out.unaligned_op.di = NULL; | |
564 | } | |
916c9cef | 565 | |
566 | init_machine_status = pa_init_machine_status; | |
134b4858 | 567 | } |
568 | ||
066397a3 | 569 | static void |
5c1d8983 | 570 | pa_init_builtins (void) |
ffa8918b | 571 | { |
572 | #ifdef DONT_HAVE_FPUTC_UNLOCKED | |
4a08b134 | 573 | built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = |
574 | built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED]; | |
575 | implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] | |
576 | = implicit_built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED]; | |
ffa8918b | 577 | #endif |
01cbacb9 | 578 | #if TARGET_HPUX_11 |
aafb162c | 579 | if (built_in_decls [BUILT_IN_FINITE]) |
580 | set_user_assembler_name (built_in_decls [BUILT_IN_FINITE], "_Isfinite"); | |
581 | if (built_in_decls [BUILT_IN_FINITEF]) | |
582 | set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF], "_Isfinitef"); | |
583 | #endif | |
ffa8918b | 584 | } |
585 | ||
916c9cef | 586 | /* Function to init struct machine_function. |
587 | This will be called, via a pointer variable, | |
588 | from push_function_context. */ | |
589 | ||
590 | static struct machine_function * | |
591 | pa_init_machine_status (void) | |
592 | { | |
ba72912a | 593 | return ggc_alloc_cleared_machine_function (); |
916c9cef | 594 | } |
595 | ||
dbd3d89d | 596 | /* If FROM is a probable pointer register, mark TO as a probable |
597 | pointer register with the same pointer alignment as FROM. */ | |
598 | ||
599 | static void | |
600 | copy_reg_pointer (rtx to, rtx from) | |
601 | { | |
602 | if (REG_POINTER (from)) | |
603 | mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from))); | |
604 | } | |
605 | ||
6d36483b | 606 | /* Return 1 if X contains a symbolic expression. We know these |
607 | expressions will have one of a few well defined forms, so | |
347b5848 | 608 | we need only check those forms. */ |
609 | int | |
5c1d8983 | 610 | symbolic_expression_p (rtx x) |
347b5848 | 611 | { |
612 | ||
6dc3b0d9 | 613 | /* Strip off any HIGH. */ |
347b5848 | 614 | if (GET_CODE (x) == HIGH) |
615 | x = XEXP (x, 0); | |
616 | ||
617 | return (symbolic_operand (x, VOIDmode)); | |
618 | } | |
619 | ||
7c4d3047 | 620 | /* Accept any constant that can be moved in one instruction into a |
d9d7c968 | 621 | general register. */ |
6d36483b | 622 | int |
59ad2f1e | 623 | cint_ok_for_move (HOST_WIDE_INT ival) |
d9d7c968 | 624 | { |
625 | /* OK if ldo, ldil, or zdepi, can be used. */ | |
59ad2f1e | 626 | return (VAL_14_BITS_P (ival) |
627 | || ldil_cint_p (ival) | |
628 | || zdepi_cint_p (ival)); | |
d9d7c968 | 629 | } |
87ad11b0 | 630 | \f |
2a91e628 | 631 | /* Return truth value of whether OP can be used as an operand in a |
632 | adddi3 insn. */ | |
633 | int | |
5c1d8983 | 634 | adddi3_operand (rtx op, enum machine_mode mode) |
2a91e628 | 635 | { |
636 | return (register_operand (op, mode) | |
637 | || (GET_CODE (op) == CONST_INT | |
638 | && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op)))); | |
639 | } | |
640 | ||
59ad2f1e | 641 | /* True iff the operand OP can be used as the destination operand of |
642 | an integer store. This also implies the operand could be used as | |
643 | the source operand of an integer load. Symbolic, lo_sum and indexed | |
644 | memory operands are not allowed. We accept reloading pseudos and | |
645 | other memory operands. */ | |
646 | int | |
647 | integer_store_memory_operand (rtx op, enum machine_mode mode) | |
648 | { | |
649 | return ((reload_in_progress | |
650 | && REG_P (op) | |
651 | && REGNO (op) >= FIRST_PSEUDO_REGISTER | |
652 | && reg_renumber [REGNO (op)] < 0) | |
653 | || (GET_CODE (op) == MEM | |
654 | && (reload_in_progress || memory_address_p (mode, XEXP (op, 0))) | |
655 | && !symbolic_memory_operand (op, VOIDmode) | |
656 | && !IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0)) | |
657 | && !IS_INDEX_ADDR_P (XEXP (op, 0)))); | |
658 | } | |
659 | ||
660 | /* True iff ldil can be used to load this CONST_INT. The least | |
661 | significant 11 bits of the value must be zero and the value must | |
662 | not change sign when extended from 32 to 64 bits. */ | |
663 | int | |
664 | ldil_cint_p (HOST_WIDE_INT ival) | |
665 | { | |
666 | HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff); | |
667 | ||
668 | return x == 0 || x == ((HOST_WIDE_INT) -1 << 31); | |
669 | } | |
670 | ||
ea52c577 | 671 | /* True iff zdepi can be used to generate this CONST_INT. |
5b865faf | 672 | zdepi first sign extends a 5-bit signed number to a given field |
ea52c577 | 673 | length, then places this field anywhere in a zero. */ |
e057641f | 674 | int |
5c1d8983 | 675 | zdepi_cint_p (unsigned HOST_WIDE_INT x) |
fad0b60f | 676 | { |
3745c59b | 677 | unsigned HOST_WIDE_INT lsb_mask, t; |
fad0b60f | 678 | |
679 | /* This might not be obvious, but it's at least fast. | |
01cc3b75 | 680 | This function is critical; we don't have the time loops would take. */ |
42faba01 | 681 | lsb_mask = x & -x; |
682 | t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1); | |
683 | /* Return true iff t is a power of two. */ | |
fad0b60f | 684 | return ((t & (t - 1)) == 0); |
685 | } | |
686 | ||
6d36483b | 687 | /* True iff depi or extru can be used to compute (reg & mask). |
688 | Accept bit pattern like these: | |
689 | 0....01....1 | |
690 | 1....10....0 | |
691 | 1..10..01..1 */ | |
e057641f | 692 | int |
5c1d8983 | 693 | and_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 694 | { |
695 | mask = ~mask; | |
696 | mask += mask & -mask; | |
697 | return (mask & (mask - 1)) == 0; | |
698 | } | |
699 | ||
e057641f | 700 | /* True iff depi can be used to compute (reg | MASK). */ |
701 | int | |
5c1d8983 | 702 | ior_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 703 | { |
704 | mask += mask & -mask; | |
705 | return (mask & (mask - 1)) == 0; | |
706 | } | |
87ad11b0 | 707 | \f |
708 | /* Legitimize PIC addresses. If the address is already | |
709 | position-independent, we return ORIG. Newly generated | |
710 | position-independent addresses go to REG. If we need more | |
711 | than one register, we lose. */ | |
712 | ||
713 | rtx | |
5c1d8983 | 714 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
87ad11b0 | 715 | { |
716 | rtx pic_ref = orig; | |
717 | ||
f7229f19 | 718 | gcc_assert (!PA_SYMBOL_REF_TLS_P (orig)); |
716b2c5a | 719 | |
b090827b | 720 | /* Labels need special handling. */ |
611a88e1 | 721 | if (pic_label_operand (orig, mode)) |
b4a7bf10 | 722 | { |
3e478718 | 723 | rtx insn; |
724 | ||
2536cc16 | 725 | /* We do not want to go through the movXX expanders here since that |
726 | would create recursion. | |
727 | ||
728 | Nor do we really want to call a generator for a named pattern | |
729 | since that requires multiple patterns if we want to support | |
730 | multiple word sizes. | |
731 | ||
732 | So instead we just emit the raw set, which avoids the movXX | |
733 | expanders completely. */ | |
dbd3d89d | 734 | mark_reg_pointer (reg, BITS_PER_UNIT); |
3e478718 | 735 | insn = emit_insn (gen_rtx_SET (VOIDmode, reg, orig)); |
736 | ||
737 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
b9c74b4d | 738 | add_reg_note (insn, REG_EQUAL, orig); |
3e478718 | 739 | |
740 | /* During and after reload, we need to generate a REG_LABEL_OPERAND note | |
741 | and update LABEL_NUSES because this is not done automatically. */ | |
742 | if (reload_in_progress || reload_completed) | |
743 | { | |
744 | /* Extract LABEL_REF. */ | |
745 | if (GET_CODE (orig) == CONST) | |
746 | orig = XEXP (XEXP (orig, 0), 0); | |
747 | /* Extract CODE_LABEL. */ | |
748 | orig = XEXP (orig, 0); | |
a1ddb869 | 749 | add_reg_note (insn, REG_LABEL_OPERAND, orig); |
3e478718 | 750 | LABEL_NUSES (orig)++; |
751 | } | |
18d50ae6 | 752 | crtl->uses_pic_offset_table = 1; |
b4a7bf10 | 753 | return reg; |
754 | } | |
87ad11b0 | 755 | if (GET_CODE (orig) == SYMBOL_REF) |
756 | { | |
f9c1ba9d | 757 | rtx insn, tmp_reg; |
758 | ||
ecf2283d | 759 | gcc_assert (reg); |
87ad11b0 | 760 | |
f9c1ba9d | 761 | /* Before reload, allocate a temporary register for the intermediate |
762 | result. This allows the sequence to be deleted when the final | |
763 | result is unused and the insns are trivially dead. */ | |
764 | tmp_reg = ((reload_in_progress || reload_completed) | |
765 | ? reg : gen_reg_rtx (Pmode)); | |
766 | ||
dc58a0ec | 767 | if (function_label_operand (orig, mode)) |
3635d963 | 768 | { |
cefef42c | 769 | /* Force function label into memory in word mode. */ |
770 | orig = XEXP (force_const_mem (word_mode, orig), 0); | |
3635d963 | 771 | /* Load plabel address from DLT. */ |
772 | emit_move_insn (tmp_reg, | |
773 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, | |
774 | gen_rtx_HIGH (word_mode, orig))); | |
775 | pic_ref | |
776 | = gen_const_mem (Pmode, | |
777 | gen_rtx_LO_SUM (Pmode, tmp_reg, | |
778 | gen_rtx_UNSPEC (Pmode, | |
e265a6da | 779 | gen_rtvec (1, orig), |
780 | UNSPEC_DLTIND14R))); | |
3635d963 | 781 | emit_move_insn (reg, pic_ref); |
782 | /* Now load address of function descriptor. */ | |
783 | pic_ref = gen_rtx_MEM (Pmode, reg); | |
784 | } | |
785 | else | |
786 | { | |
787 | /* Load symbol reference from DLT. */ | |
788 | emit_move_insn (tmp_reg, | |
789 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, | |
790 | gen_rtx_HIGH (word_mode, orig))); | |
791 | pic_ref | |
792 | = gen_const_mem (Pmode, | |
793 | gen_rtx_LO_SUM (Pmode, tmp_reg, | |
794 | gen_rtx_UNSPEC (Pmode, | |
795 | gen_rtvec (1, orig), | |
796 | UNSPEC_DLTIND14R))); | |
797 | } | |
7014838c | 798 | |
18d50ae6 | 799 | crtl->uses_pic_offset_table = 1; |
dbd3d89d | 800 | mark_reg_pointer (reg, BITS_PER_UNIT); |
f9c1ba9d | 801 | insn = emit_move_insn (reg, pic_ref); |
802 | ||
803 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
24153880 | 804 | set_unique_reg_note (insn, REG_EQUAL, orig); |
f9c1ba9d | 805 | |
87ad11b0 | 806 | return reg; |
807 | } | |
808 | else if (GET_CODE (orig) == CONST) | |
809 | { | |
57ed30e5 | 810 | rtx base; |
87ad11b0 | 811 | |
812 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
813 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
814 | return orig; | |
815 | ||
ecf2283d | 816 | gcc_assert (reg); |
817 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); | |
818 | ||
819 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
820 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
821 | base == reg ? 0 : reg); | |
dbd3d89d | 822 | |
87ad11b0 | 823 | if (GET_CODE (orig) == CONST_INT) |
824 | { | |
42faba01 | 825 | if (INT_14_BITS (orig)) |
b244d4c7 | 826 | return plus_constant (base, INTVAL (orig)); |
87ad11b0 | 827 | orig = force_reg (Pmode, orig); |
828 | } | |
ad851752 | 829 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
87ad11b0 | 830 | /* Likewise, should we set special REG_NOTEs here? */ |
831 | } | |
dbd3d89d | 832 | |
87ad11b0 | 833 | return pic_ref; |
834 | } | |
835 | ||
716b2c5a | 836 | static GTY(()) rtx gen_tls_tga; |
837 | ||
838 | static rtx | |
839 | gen_tls_get_addr (void) | |
840 | { | |
841 | if (!gen_tls_tga) | |
842 | gen_tls_tga = init_one_libfunc ("__tls_get_addr"); | |
843 | return gen_tls_tga; | |
844 | } | |
845 | ||
846 | static rtx | |
847 | hppa_tls_call (rtx arg) | |
848 | { | |
849 | rtx ret; | |
850 | ||
851 | ret = gen_reg_rtx (Pmode); | |
852 | emit_library_call_value (gen_tls_get_addr (), ret, | |
853 | LCT_CONST, Pmode, 1, arg, Pmode); | |
854 | ||
855 | return ret; | |
856 | } | |
857 | ||
858 | static rtx | |
859 | legitimize_tls_address (rtx addr) | |
860 | { | |
861 | rtx ret, insn, tmp, t1, t2, tp; | |
862 | enum tls_model model = SYMBOL_REF_TLS_MODEL (addr); | |
863 | ||
864 | switch (model) | |
865 | { | |
866 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
867 | tmp = gen_reg_rtx (Pmode); | |
3f8d8851 | 868 | if (flag_pic) |
869 | emit_insn (gen_tgd_load_pic (tmp, addr)); | |
870 | else | |
871 | emit_insn (gen_tgd_load (tmp, addr)); | |
716b2c5a | 872 | ret = hppa_tls_call (tmp); |
873 | break; | |
874 | ||
875 | case TLS_MODEL_LOCAL_DYNAMIC: | |
876 | ret = gen_reg_rtx (Pmode); | |
877 | tmp = gen_reg_rtx (Pmode); | |
878 | start_sequence (); | |
3f8d8851 | 879 | if (flag_pic) |
880 | emit_insn (gen_tld_load_pic (tmp, addr)); | |
881 | else | |
882 | emit_insn (gen_tld_load (tmp, addr)); | |
716b2c5a | 883 | t1 = hppa_tls_call (tmp); |
884 | insn = get_insns (); | |
885 | end_sequence (); | |
886 | t2 = gen_reg_rtx (Pmode); | |
887 | emit_libcall_block (insn, t2, t1, | |
888 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
889 | UNSPEC_TLSLDBASE)); | |
890 | emit_insn (gen_tld_offset_load (ret, addr, t2)); | |
891 | break; | |
892 | ||
893 | case TLS_MODEL_INITIAL_EXEC: | |
894 | tp = gen_reg_rtx (Pmode); | |
895 | tmp = gen_reg_rtx (Pmode); | |
896 | ret = gen_reg_rtx (Pmode); | |
897 | emit_insn (gen_tp_load (tp)); | |
3f8d8851 | 898 | if (flag_pic) |
899 | emit_insn (gen_tie_load_pic (tmp, addr)); | |
900 | else | |
901 | emit_insn (gen_tie_load (tmp, addr)); | |
716b2c5a | 902 | emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp)); |
903 | break; | |
904 | ||
905 | case TLS_MODEL_LOCAL_EXEC: | |
906 | tp = gen_reg_rtx (Pmode); | |
907 | ret = gen_reg_rtx (Pmode); | |
908 | emit_insn (gen_tp_load (tp)); | |
909 | emit_insn (gen_tle_load (ret, addr, tp)); | |
910 | break; | |
911 | ||
912 | default: | |
f7229f19 | 913 | gcc_unreachable (); |
716b2c5a | 914 | } |
915 | ||
916 | return ret; | |
917 | } | |
918 | ||
347b5848 | 919 | /* Try machine-dependent ways of modifying an illegitimate address |
920 | to be legitimate. If we find one, return the new, valid address. | |
921 | This macro is used in only one place: `memory_address' in explow.c. | |
922 | ||
923 | OLDX is the address as it was before break_out_memory_refs was called. | |
924 | In some cases it is useful to look at this to decide what needs to be done. | |
925 | ||
347b5848 | 926 | It is always safe for this macro to do nothing. It exists to recognize |
6d36483b | 927 | opportunities to optimize the output. |
347b5848 | 928 | |
929 | For the PA, transform: | |
930 | ||
931 | memory(X + <large int>) | |
932 | ||
933 | into: | |
934 | ||
935 | if (<large int> & mask) >= 16 | |
936 | Y = (<large int> & ~mask) + mask + 1 Round up. | |
937 | else | |
938 | Y = (<large int> & ~mask) Round down. | |
939 | Z = X + Y | |
940 | memory (Z + (<large int> - Y)); | |
941 | ||
6d36483b | 942 | This is for CSE to find several similar references, and only use one Z. |
347b5848 | 943 | |
33f88b1c | 944 | X can either be a SYMBOL_REF or REG, but because combine cannot |
347b5848 | 945 | perform a 4->2 combination we do nothing for SYMBOL_REF + D where |
946 | D will not fit in 14 bits. | |
947 | ||
948 | MODE_FLOAT references allow displacements which fit in 5 bits, so use | |
6d36483b | 949 | 0x1f as the mask. |
347b5848 | 950 | |
951 | MODE_INT references allow displacements which fit in 14 bits, so use | |
6d36483b | 952 | 0x3fff as the mask. |
347b5848 | 953 | |
954 | This relies on the fact that most mode MODE_FLOAT references will use FP | |
955 | registers and most mode MODE_INT references will use integer registers. | |
956 | (In the rare case of an FP register used in an integer MODE, we depend | |
957 | on secondary reloads to clean things up.) | |
958 | ||
959 | ||
960 | It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special | |
961 | manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed | |
01cc3b75 | 962 | addressing modes to be used). |
347b5848 | 963 | |
964 | Put X and Z into registers. Then put the entire expression into | |
965 | a register. */ | |
966 | ||
967 | rtx | |
5c1d8983 | 968 | hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
969 | enum machine_mode mode) | |
347b5848 | 970 | { |
347b5848 | 971 | rtx orig = x; |
972 | ||
dbd3d89d | 973 | /* We need to canonicalize the order of operands in unscaled indexed |
974 | addresses since the code that checks if an address is valid doesn't | |
975 | always try both orders. */ | |
976 | if (!TARGET_NO_SPACE_REGS | |
977 | && GET_CODE (x) == PLUS | |
978 | && GET_MODE (x) == Pmode | |
979 | && REG_P (XEXP (x, 0)) | |
980 | && REG_P (XEXP (x, 1)) | |
981 | && REG_POINTER (XEXP (x, 0)) | |
982 | && !REG_POINTER (XEXP (x, 1))) | |
983 | return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0)); | |
984 | ||
716b2c5a | 985 | if (PA_SYMBOL_REF_TLS_P (x)) |
986 | return legitimize_tls_address (x); | |
987 | else if (flag_pic) | |
b4a7bf10 | 988 | return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); |
989 | ||
6dc3b0d9 | 990 | /* Strip off CONST. */ |
347b5848 | 991 | if (GET_CODE (x) == CONST) |
992 | x = XEXP (x, 0); | |
993 | ||
42819d4e | 994 | /* Special case. Get the SYMBOL_REF into a register and use indexing. |
995 | That should always be safe. */ | |
996 | if (GET_CODE (x) == PLUS | |
997 | && GET_CODE (XEXP (x, 0)) == REG | |
998 | && GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
999 | { | |
440c23df | 1000 | rtx reg = force_reg (Pmode, XEXP (x, 1)); |
1001 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0))); | |
42819d4e | 1002 | } |
1003 | ||
166bf021 | 1004 | /* Note we must reject symbols which represent function addresses |
1005 | since the assembler/linker can't handle arithmetic on plabels. */ | |
347b5848 | 1006 | if (GET_CODE (x) == PLUS |
1007 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
166bf021 | 1008 | && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF |
1009 | && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0))) | |
347b5848 | 1010 | || GET_CODE (XEXP (x, 0)) == REG)) |
1011 | { | |
1012 | rtx int_part, ptr_reg; | |
1013 | int newoffset; | |
1014 | int offset = INTVAL (XEXP (x, 1)); | |
1b6f11e2 | 1015 | int mask; |
1016 | ||
1017 | mask = (GET_MODE_CLASS (mode) == MODE_FLOAT | |
c78e6152 | 1018 | ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff); |
347b5848 | 1019 | |
6d36483b | 1020 | /* Choose which way to round the offset. Round up if we |
347b5848 | 1021 | are >= halfway to the next boundary. */ |
1022 | if ((offset & mask) >= ((mask + 1) / 2)) | |
1023 | newoffset = (offset & ~ mask) + mask + 1; | |
1024 | else | |
1025 | newoffset = (offset & ~ mask); | |
1026 | ||
1027 | /* If the newoffset will not fit in 14 bits (ldo), then | |
1028 | handling this would take 4 or 5 instructions (2 to load | |
1029 | the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to | |
1030 | add the new offset and the SYMBOL_REF.) Combine can | |
1031 | not handle 4->2 or 5->2 combinations, so do not create | |
1032 | them. */ | |
1033 | if (! VAL_14_BITS_P (newoffset) | |
1034 | && GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
1035 | { | |
7014838c | 1036 | rtx const_part = plus_constant (XEXP (x, 0), newoffset); |
347b5848 | 1037 | rtx tmp_reg |
339613b4 | 1038 | = force_reg (Pmode, |
ad851752 | 1039 | gen_rtx_HIGH (Pmode, const_part)); |
347b5848 | 1040 | ptr_reg |
339613b4 | 1041 | = force_reg (Pmode, |
7014838c | 1042 | gen_rtx_LO_SUM (Pmode, |
1043 | tmp_reg, const_part)); | |
347b5848 | 1044 | } |
1045 | else | |
1046 | { | |
1047 | if (! VAL_14_BITS_P (newoffset)) | |
339613b4 | 1048 | int_part = force_reg (Pmode, GEN_INT (newoffset)); |
347b5848 | 1049 | else |
1050 | int_part = GEN_INT (newoffset); | |
1051 | ||
339613b4 | 1052 | ptr_reg = force_reg (Pmode, |
ad851752 | 1053 | gen_rtx_PLUS (Pmode, |
1054 | force_reg (Pmode, XEXP (x, 0)), | |
1055 | int_part)); | |
347b5848 | 1056 | } |
1057 | return plus_constant (ptr_reg, offset - newoffset); | |
1058 | } | |
45f1285a | 1059 | |
5115683e | 1060 | /* Handle (plus (mult (a) (shadd_constant)) (b)). */ |
45f1285a | 1061 | |
347b5848 | 1062 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT |
1063 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
45f1285a | 1064 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))) |
6720e96c | 1065 | && (OBJECT_P (XEXP (x, 1)) |
45f1285a | 1066 | || GET_CODE (XEXP (x, 1)) == SUBREG) |
1067 | && GET_CODE (XEXP (x, 1)) != CONST) | |
347b5848 | 1068 | { |
1069 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1070 | rtx reg1, reg2; | |
5115683e | 1071 | |
1072 | reg1 = XEXP (x, 1); | |
1073 | if (GET_CODE (reg1) != REG) | |
1074 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1075 | ||
1076 | reg2 = XEXP (XEXP (x, 0), 0); | |
1077 | if (GET_CODE (reg2) != REG) | |
1078 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1079 | ||
ad851752 | 1080 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1081 | gen_rtx_MULT (Pmode, |
1082 | reg2, | |
1083 | GEN_INT (val)), | |
ad851752 | 1084 | reg1)); |
347b5848 | 1085 | } |
45f1285a | 1086 | |
00a87639 | 1087 | /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)). |
1088 | ||
1089 | Only do so for floating point modes since this is more speculative | |
1090 | and we lose if it's an integer store. */ | |
5115683e | 1091 | if (GET_CODE (x) == PLUS |
00a87639 | 1092 | && GET_CODE (XEXP (x, 0)) == PLUS |
1093 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
1094 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
5115683e | 1095 | && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) |
1096 | && (mode == SFmode || mode == DFmode)) | |
00a87639 | 1097 | { |
5115683e | 1098 | |
1099 | /* First, try and figure out what to use as a base register. */ | |
1ce99229 | 1100 | rtx reg1, reg2, base, idx; |
5115683e | 1101 | |
1102 | reg1 = XEXP (XEXP (x, 0), 1); | |
1103 | reg2 = XEXP (x, 1); | |
1104 | base = NULL_RTX; | |
1105 | idx = NULL_RTX; | |
1106 | ||
1107 | /* Make sure they're both regs. If one was a SYMBOL_REF [+ const], | |
e61a0a7f | 1108 | then emit_move_sequence will turn on REG_POINTER so we'll know |
1109 | it's a base register below. */ | |
5115683e | 1110 | if (GET_CODE (reg1) != REG) |
1111 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1112 | ||
1113 | if (GET_CODE (reg2) != REG) | |
1114 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1115 | ||
1116 | /* Figure out what the base and index are. */ | |
9840d99d | 1117 | |
5115683e | 1118 | if (GET_CODE (reg1) == REG |
e61a0a7f | 1119 | && REG_POINTER (reg1)) |
5115683e | 1120 | { |
1121 | base = reg1; | |
ad851752 | 1122 | idx = gen_rtx_PLUS (Pmode, |
1123 | gen_rtx_MULT (Pmode, | |
1124 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
1125 | XEXP (XEXP (XEXP (x, 0), 0), 1)), | |
1126 | XEXP (x, 1)); | |
5115683e | 1127 | } |
1128 | else if (GET_CODE (reg2) == REG | |
e61a0a7f | 1129 | && REG_POINTER (reg2)) |
5115683e | 1130 | { |
1131 | base = reg2; | |
5115683e | 1132 | idx = XEXP (x, 0); |
1133 | } | |
1134 | ||
1135 | if (base == 0) | |
21f3ee9c | 1136 | return orig; |
5115683e | 1137 | |
1138 | /* If the index adds a large constant, try to scale the | |
1139 | constant so that it can be loaded with only one insn. */ | |
1140 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1141 | && VAL_14_BITS_P (INTVAL (XEXP (idx, 1)) | |
1142 | / INTVAL (XEXP (XEXP (idx, 0), 1))) | |
1143 | && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0) | |
1144 | { | |
1145 | /* Divide the CONST_INT by the scale factor, then add it to A. */ | |
1146 | int val = INTVAL (XEXP (idx, 1)); | |
1147 | ||
1148 | val /= INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1149 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1150 | if (GET_CODE (reg1) != REG) | |
1151 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1152 | ||
ad851752 | 1153 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val))); |
5115683e | 1154 | |
1155 | /* We can now generate a simple scaled indexed address. */ | |
7014838c | 1156 | return |
1157 | force_reg | |
1158 | (Pmode, gen_rtx_PLUS (Pmode, | |
1159 | gen_rtx_MULT (Pmode, reg1, | |
1160 | XEXP (XEXP (idx, 0), 1)), | |
1161 | base)); | |
5115683e | 1162 | } |
1163 | ||
1164 | /* If B + C is still a valid base register, then add them. */ | |
1165 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1166 | && INTVAL (XEXP (idx, 1)) <= 4096 | |
1167 | && INTVAL (XEXP (idx, 1)) >= -4096) | |
1168 | { | |
1169 | int val = INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1170 | rtx reg1, reg2; | |
1171 | ||
ad851752 | 1172 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1))); |
5115683e | 1173 | |
1174 | reg2 = XEXP (XEXP (idx, 0), 0); | |
1175 | if (GET_CODE (reg2) != CONST_INT) | |
1176 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1177 | ||
ad851752 | 1178 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1179 | gen_rtx_MULT (Pmode, |
1180 | reg2, | |
ad851752 | 1181 | GEN_INT (val)), |
1182 | reg1)); | |
5115683e | 1183 | } |
1184 | ||
1185 | /* Get the index into a register, then add the base + index and | |
1186 | return a register holding the result. */ | |
1187 | ||
1188 | /* First get A into a register. */ | |
1189 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1190 | if (GET_CODE (reg1) != REG) | |
1191 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1192 | ||
1193 | /* And get B into a register. */ | |
1194 | reg2 = XEXP (idx, 1); | |
1195 | if (GET_CODE (reg2) != REG) | |
1196 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1197 | ||
ad851752 | 1198 | reg1 = force_reg (Pmode, |
1199 | gen_rtx_PLUS (Pmode, | |
1200 | gen_rtx_MULT (Pmode, reg1, | |
1201 | XEXP (XEXP (idx, 0), 1)), | |
1202 | reg2)); | |
5115683e | 1203 | |
1204 | /* Add the result to our base register and return. */ | |
ad851752 | 1205 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1)); |
9840d99d | 1206 | |
00a87639 | 1207 | } |
1208 | ||
6d36483b | 1209 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
fb5390c1 | 1210 | special handling to avoid creating an indexed memory address |
1211 | with x-100000 as the base. | |
9840d99d | 1212 | |
fb5390c1 | 1213 | If the constant part is small enough, then it's still safe because |
1214 | there is a guard page at the beginning and end of the data segment. | |
1215 | ||
1216 | Scaled references are common enough that we want to try and rearrange the | |
1217 | terms so that we can use indexing for these addresses too. Only | |
00a87639 | 1218 | do the optimization for floatint point modes. */ |
45f1285a | 1219 | |
fb5390c1 | 1220 | if (GET_CODE (x) == PLUS |
1221 | && symbolic_expression_p (XEXP (x, 1))) | |
45f1285a | 1222 | { |
1223 | /* Ugly. We modify things here so that the address offset specified | |
1224 | by the index expression is computed first, then added to x to form | |
fb5390c1 | 1225 | the entire address. */ |
45f1285a | 1226 | |
00a87639 | 1227 | rtx regx1, regx2, regy1, regy2, y; |
45f1285a | 1228 | |
1229 | /* Strip off any CONST. */ | |
1230 | y = XEXP (x, 1); | |
1231 | if (GET_CODE (y) == CONST) | |
1232 | y = XEXP (y, 0); | |
1233 | ||
7ee96d6e | 1234 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1235 | { | |
00a87639 | 1236 | /* See if this looks like |
1237 | (plus (mult (reg) (shadd_const)) | |
1238 | (const (plus (symbol_ref) (const_int)))) | |
1239 | ||
5115683e | 1240 | Where const_int is small. In that case the const |
9840d99d | 1241 | expression is a valid pointer for indexing. |
5115683e | 1242 | |
1243 | If const_int is big, but can be divided evenly by shadd_const | |
1244 | and added to (reg). This allows more scaled indexed addresses. */ | |
1245 | if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1246 | && GET_CODE (XEXP (x, 0)) == MULT | |
00a87639 | 1247 | && GET_CODE (XEXP (y, 1)) == CONST_INT |
5115683e | 1248 | && INTVAL (XEXP (y, 1)) >= -4096 |
1249 | && INTVAL (XEXP (y, 1)) <= 4095 | |
1250 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1251 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
1252 | { | |
1253 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1254 | rtx reg1, reg2; | |
1255 | ||
1256 | reg1 = XEXP (x, 1); | |
1257 | if (GET_CODE (reg1) != REG) | |
1258 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1259 | ||
1260 | reg2 = XEXP (XEXP (x, 0), 0); | |
1261 | if (GET_CODE (reg2) != REG) | |
1262 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1263 | ||
ad851752 | 1264 | return force_reg (Pmode, |
1265 | gen_rtx_PLUS (Pmode, | |
7014838c | 1266 | gen_rtx_MULT (Pmode, |
1267 | reg2, | |
ad851752 | 1268 | GEN_INT (val)), |
7014838c | 1269 | reg1)); |
5115683e | 1270 | } |
1271 | else if ((mode == DFmode || mode == SFmode) | |
1272 | && GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1273 | && GET_CODE (XEXP (x, 0)) == MULT | |
1274 | && GET_CODE (XEXP (y, 1)) == CONST_INT | |
1275 | && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0 | |
1276 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1277 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
00a87639 | 1278 | { |
1279 | regx1 | |
1280 | = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1)) | |
1281 | / INTVAL (XEXP (XEXP (x, 0), 1)))); | |
1282 | regx2 = XEXP (XEXP (x, 0), 0); | |
1283 | if (GET_CODE (regx2) != REG) | |
1284 | regx2 = force_reg (Pmode, force_operand (regx2, 0)); | |
ad851752 | 1285 | regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1286 | regx2, regx1)); | |
7014838c | 1287 | return |
1288 | force_reg (Pmode, | |
1289 | gen_rtx_PLUS (Pmode, | |
1290 | gen_rtx_MULT (Pmode, regx2, | |
1291 | XEXP (XEXP (x, 0), 1)), | |
1292 | force_reg (Pmode, XEXP (y, 0)))); | |
00a87639 | 1293 | } |
fb5390c1 | 1294 | else if (GET_CODE (XEXP (y, 1)) == CONST_INT |
1295 | && INTVAL (XEXP (y, 1)) >= -4096 | |
1296 | && INTVAL (XEXP (y, 1)) <= 4095) | |
1297 | { | |
1298 | /* This is safe because of the guard page at the | |
1299 | beginning and end of the data space. Just | |
1300 | return the original address. */ | |
1301 | return orig; | |
1302 | } | |
00a87639 | 1303 | else |
1304 | { | |
1305 | /* Doesn't look like one we can optimize. */ | |
1306 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1307 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1308 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1309 | regx1 = force_reg (Pmode, | |
ad851752 | 1310 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1311 | regx1, regy2)); | |
1312 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); | |
00a87639 | 1313 | } |
7ee96d6e | 1314 | } |
45f1285a | 1315 | } |
1316 | ||
347b5848 | 1317 | return orig; |
1318 | } | |
1319 | ||
93d3ee56 | 1320 | /* Implement the TARGET_REGISTER_MOVE_COST hook. |
1321 | ||
1322 | Compute extra cost of moving data between one register class | |
1323 | and another. | |
1324 | ||
1325 | Make moves from SAR so expensive they should never happen. We used to | |
1326 | have 0xffff here, but that generates overflow in rare cases. | |
1327 | ||
1328 | Copies involving a FP register and a non-FP register are relatively | |
1329 | expensive because they must go through memory. | |
1330 | ||
1331 | Other copies are reasonably cheap. */ | |
1332 | ||
1333 | static int | |
1334 | hppa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
1335 | reg_class_t from, reg_class_t to) | |
1336 | { | |
1337 | if (from == SHIFT_REGS) | |
1338 | return 0x100; | |
1339 | else if ((FP_REG_CLASS_P (from) && ! FP_REG_CLASS_P (to)) | |
1340 | || (FP_REG_CLASS_P (to) && ! FP_REG_CLASS_P (from))) | |
1341 | return 16; | |
1342 | else | |
1343 | return 2; | |
1344 | } | |
1345 | ||
87ad11b0 | 1346 | /* For the HPPA, REG and REG+CONST is cost 0 |
1347 | and addresses involving symbolic constants are cost 2. | |
1348 | ||
1349 | PIC addresses are very expensive. | |
1350 | ||
1351 | It is no coincidence that this has the same structure | |
1352 | as GO_IF_LEGITIMATE_ADDRESS. */ | |
ec0457a8 | 1353 | |
1354 | static int | |
f529eb25 | 1355 | hppa_address_cost (rtx X, |
1356 | bool speed ATTRIBUTE_UNUSED) | |
87ad11b0 | 1357 | { |
ec0457a8 | 1358 | switch (GET_CODE (X)) |
1359 | { | |
1360 | case REG: | |
1361 | case PLUS: | |
1362 | case LO_SUM: | |
87ad11b0 | 1363 | return 1; |
ec0457a8 | 1364 | case HIGH: |
1365 | return 2; | |
1366 | default: | |
1367 | return 4; | |
1368 | } | |
87ad11b0 | 1369 | } |
1370 | ||
fab7adbf | 1371 | /* Compute a (partial) cost for rtx X. Return true if the complete |
1372 | cost has been computed, and false if subexpressions should be | |
1373 | scanned. In either case, *TOTAL contains the cost result. */ | |
1374 | ||
1375 | static bool | |
f529eb25 | 1376 | hppa_rtx_costs (rtx x, int code, int outer_code, int *total, |
1377 | bool speed ATTRIBUTE_UNUSED) | |
fab7adbf | 1378 | { |
1379 | switch (code) | |
1380 | { | |
1381 | case CONST_INT: | |
1382 | if (INTVAL (x) == 0) | |
1383 | *total = 0; | |
1384 | else if (INT_14_BITS (x)) | |
1385 | *total = 1; | |
1386 | else | |
1387 | *total = 2; | |
1388 | return true; | |
1389 | ||
1390 | case HIGH: | |
1391 | *total = 2; | |
1392 | return true; | |
1393 | ||
1394 | case CONST: | |
1395 | case LABEL_REF: | |
1396 | case SYMBOL_REF: | |
1397 | *total = 4; | |
1398 | return true; | |
1399 | ||
1400 | case CONST_DOUBLE: | |
1401 | if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode)) | |
1402 | && outer_code != SET) | |
1403 | *total = 0; | |
1404 | else | |
1405 | *total = 8; | |
1406 | return true; | |
1407 | ||
1408 | case MULT: | |
1409 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1410 | *total = COSTS_N_INSNS (3); | |
1411 | else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT) | |
1412 | *total = COSTS_N_INSNS (8); | |
1413 | else | |
1414 | *total = COSTS_N_INSNS (20); | |
1415 | return true; | |
1416 | ||
1417 | case DIV: | |
1418 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1419 | { | |
1420 | *total = COSTS_N_INSNS (14); | |
1421 | return true; | |
1422 | } | |
8e262b5e | 1423 | /* FALLTHRU */ |
fab7adbf | 1424 | |
1425 | case UDIV: | |
1426 | case MOD: | |
1427 | case UMOD: | |
1428 | *total = COSTS_N_INSNS (60); | |
1429 | return true; | |
1430 | ||
1431 | case PLUS: /* this includes shNadd insns */ | |
1432 | case MINUS: | |
1433 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1434 | *total = COSTS_N_INSNS (3); | |
1435 | else | |
1436 | *total = COSTS_N_INSNS (1); | |
1437 | return true; | |
1438 | ||
1439 | case ASHIFT: | |
1440 | case ASHIFTRT: | |
1441 | case LSHIFTRT: | |
1442 | *total = COSTS_N_INSNS (1); | |
1443 | return true; | |
1444 | ||
1445 | default: | |
1446 | return false; | |
1447 | } | |
1448 | } | |
1449 | ||
9840d99d | 1450 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a |
1451 | new rtx with the correct mode. */ | |
1452 | static inline rtx | |
5c1d8983 | 1453 | force_mode (enum machine_mode mode, rtx orig) |
9840d99d | 1454 | { |
1455 | if (mode == GET_MODE (orig)) | |
1456 | return orig; | |
1457 | ||
ecf2283d | 1458 | gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER); |
9840d99d | 1459 | |
1460 | return gen_rtx_REG (mode, REGNO (orig)); | |
1461 | } | |
1462 | ||
716b2c5a | 1463 | /* Return 1 if *X is a thread-local symbol. */ |
1464 | ||
1465 | static int | |
1466 | pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
1467 | { | |
1468 | return PA_SYMBOL_REF_TLS_P (*x); | |
1469 | } | |
1470 | ||
1471 | /* Return 1 if X contains a thread-local symbol. */ | |
1472 | ||
1473 | bool | |
1474 | pa_tls_referenced_p (rtx x) | |
1475 | { | |
1476 | if (!TARGET_HAVE_TLS) | |
1477 | return false; | |
1478 | ||
1479 | return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0); | |
1480 | } | |
1481 | ||
87ad11b0 | 1482 | /* Emit insns to move operands[1] into operands[0]. |
1483 | ||
1484 | Return 1 if we have written out everything that needs to be done to | |
1485 | do the move. Otherwise, return 0 and the caller will emit the move | |
9840d99d | 1486 | normally. |
f756078b | 1487 | |
1488 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
2cecd772 | 1489 | will be used. This routine is responsible for creating a new copy |
f756078b | 1490 | of SCRATCH_REG in the proper mode. */ |
87ad11b0 | 1491 | |
1492 | int | |
5c1d8983 | 1493 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) |
87ad11b0 | 1494 | { |
1495 | register rtx operand0 = operands[0]; | |
1496 | register rtx operand1 = operands[1]; | |
4a155b0f | 1497 | register rtx tem; |
87ad11b0 | 1498 | |
dbd3d89d | 1499 | /* We can only handle indexed addresses in the destination operand |
1500 | of floating point stores. Thus, we need to break out indexed | |
1501 | addresses from the destination operand. */ | |
1502 | if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0))) | |
1503 | { | |
e1ba4a27 | 1504 | gcc_assert (can_create_pseudo_p ()); |
dbd3d89d | 1505 | |
1506 | tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0)); | |
1507 | operand0 = replace_equiv_address (operand0, tem); | |
1508 | } | |
1509 | ||
1510 | /* On targets with non-equivalent space registers, break out unscaled | |
1511 | indexed addresses from the source operand before the final CSE. | |
1512 | We have to do this because the REG_POINTER flag is not correctly | |
1513 | carried through various optimization passes and CSE may substitute | |
1514 | a pseudo without the pointer set for one with the pointer set. As | |
5aedf60c | 1515 | a result, we loose various opportunities to create insns with |
dbd3d89d | 1516 | unscaled indexed addresses. */ |
1517 | if (!TARGET_NO_SPACE_REGS | |
1518 | && !cse_not_expected | |
1519 | && GET_CODE (operand1) == MEM | |
1520 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1521 | && REG_P (XEXP (XEXP (operand1, 0), 0)) | |
1522 | && REG_P (XEXP (XEXP (operand1, 0), 1))) | |
1523 | operand1 | |
1524 | = replace_equiv_address (operand1, | |
1525 | copy_to_mode_reg (Pmode, XEXP (operand1, 0))); | |
1526 | ||
2d4dc8d2 | 1527 | if (scratch_reg |
1528 | && reload_in_progress && GET_CODE (operand0) == REG | |
d1e2bb73 | 1529 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) |
1530 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2d4dc8d2 | 1531 | else if (scratch_reg |
1532 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
d1e2bb73 | 1533 | && GET_CODE (SUBREG_REG (operand0)) == REG |
1534 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1535 | { |
701e46d0 | 1536 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1537 | the code which tracks sets/uses for delete_output_reload. */ |
1538 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
1539 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
701e46d0 | 1540 | SUBREG_BYTE (operand0)); |
e00b80b2 | 1541 | operand0 = alter_subreg (&temp); |
a3afad75 | 1542 | } |
d1e2bb73 | 1543 | |
2d4dc8d2 | 1544 | if (scratch_reg |
1545 | && reload_in_progress && GET_CODE (operand1) == REG | |
d1e2bb73 | 1546 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) |
1547 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2d4dc8d2 | 1548 | else if (scratch_reg |
1549 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
d1e2bb73 | 1550 | && GET_CODE (SUBREG_REG (operand1)) == REG |
1551 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1552 | { |
701e46d0 | 1553 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1554 | the code which tracks sets/uses for delete_output_reload. */ |
1555 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
1556 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
701e46d0 | 1557 | SUBREG_BYTE (operand1)); |
e00b80b2 | 1558 | operand1 = alter_subreg (&temp); |
a3afad75 | 1559 | } |
d1e2bb73 | 1560 | |
2d4dc8d2 | 1561 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM |
4a155b0f | 1562 | && ((tem = find_replacement (&XEXP (operand0, 0))) |
1563 | != XEXP (operand0, 0))) | |
ed498904 | 1564 | operand0 = replace_equiv_address (operand0, tem); |
dbd3d89d | 1565 | |
2d4dc8d2 | 1566 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM |
4a155b0f | 1567 | && ((tem = find_replacement (&XEXP (operand1, 0))) |
1568 | != XEXP (operand1, 0))) | |
ed498904 | 1569 | operand1 = replace_equiv_address (operand1, tem); |
4a155b0f | 1570 | |
e8fdbafa | 1571 | /* Handle secondary reloads for loads/stores of FP registers from |
047e3121 | 1572 | REG+D addresses where D does not fit in 5 or 14 bits, including |
42819d4e | 1573 | (subreg (mem (addr))) cases. */ |
6bcdc1fb | 1574 | if (scratch_reg |
1575 | && fp_reg_operand (operand0, mode) | |
6b1c36c2 | 1576 | && ((GET_CODE (operand1) == MEM |
047e3121 | 1577 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode), |
1578 | XEXP (operand1, 0))) | |
6b1c36c2 | 1579 | || ((GET_CODE (operand1) == SUBREG |
1580 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
047e3121 | 1581 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1582 | ? SFmode : DFmode), | |
1583 | XEXP (XEXP (operand1, 0), 0)))))) | |
d6f01525 | 1584 | { |
6b1c36c2 | 1585 | if (GET_CODE (operand1) == SUBREG) |
1586 | operand1 = XEXP (operand1, 0); | |
1587 | ||
f756078b | 1588 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1589 | it in WORD_MODE regardless of what mode it was originally given | |
1590 | to us. */ | |
9840d99d | 1591 | scratch_reg = force_mode (word_mode, scratch_reg); |
7ee39d73 | 1592 | |
1593 | /* D might not fit in 14 bits either; for such cases load D into | |
1594 | scratch reg. */ | |
440c23df | 1595 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) |
7ee39d73 | 1596 | { |
1597 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
dbd3d89d | 1598 | emit_move_insn (scratch_reg, |
1599 | gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
1600 | Pmode, | |
1601 | XEXP (XEXP (operand1, 0), 0), | |
1602 | scratch_reg)); | |
7ee39d73 | 1603 | } |
1604 | else | |
1605 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
7014838c | 1606 | emit_insn (gen_rtx_SET (VOIDmode, operand0, |
ed498904 | 1607 | replace_equiv_address (operand1, scratch_reg))); |
d6f01525 | 1608 | return 1; |
1609 | } | |
6bcdc1fb | 1610 | else if (scratch_reg |
1611 | && fp_reg_operand (operand1, mode) | |
6b1c36c2 | 1612 | && ((GET_CODE (operand0) == MEM |
047e3121 | 1613 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1614 | ? SFmode : DFmode), | |
1615 | XEXP (operand0, 0))) | |
6b1c36c2 | 1616 | || ((GET_CODE (operand0) == SUBREG) |
1617 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
047e3121 | 1618 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1619 | ? SFmode : DFmode), | |
6bcdc1fb | 1620 | XEXP (XEXP (operand0, 0), 0))))) |
d6f01525 | 1621 | { |
6b1c36c2 | 1622 | if (GET_CODE (operand0) == SUBREG) |
1623 | operand0 = XEXP (operand0, 0); | |
1624 | ||
f756078b | 1625 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1626 | it in WORD_MODE regardless of what mode it was originally given | |
1627 | to us. */ | |
9840d99d | 1628 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1629 | |
7ee39d73 | 1630 | /* D might not fit in 14 bits either; for such cases load D into |
1631 | scratch reg. */ | |
440c23df | 1632 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) |
7ee39d73 | 1633 | { |
1634 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
ad851752 | 1635 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, |
1636 | 0)), | |
440c23df | 1637 | Pmode, |
ad851752 | 1638 | XEXP (XEXP (operand0, 0), |
1639 | 0), | |
1640 | scratch_reg)); | |
7ee39d73 | 1641 | } |
1642 | else | |
1643 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
ed498904 | 1644 | emit_insn (gen_rtx_SET (VOIDmode, |
1645 | replace_equiv_address (operand0, scratch_reg), | |
ad851752 | 1646 | operand1)); |
d6f01525 | 1647 | return 1; |
1648 | } | |
753bd06a | 1649 | /* Handle secondary reloads for loads of FP registers from constant |
1650 | expressions by forcing the constant into memory. | |
1651 | ||
6bcdc1fb | 1652 | Use scratch_reg to hold the address of the memory location. |
753bd06a | 1653 | |
9dc4cbf1 | 1654 | The proper fix is to change PREFERRED_RELOAD_CLASS to return |
87fcb603 | 1655 | NO_REGS when presented with a const_int and a register class |
753bd06a | 1656 | containing only FP registers. Doing so unfortunately creates |
1657 | more problems than it solves. Fix this for 2.5. */ | |
6bcdc1fb | 1658 | else if (scratch_reg |
753bd06a | 1659 | && CONSTANT_P (operand1) |
6bcdc1fb | 1660 | && fp_reg_operand (operand0, mode)) |
753bd06a | 1661 | { |
ed498904 | 1662 | rtx const_mem, xoperands[2]; |
753bd06a | 1663 | |
f756078b | 1664 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1665 | it in WORD_MODE regardless of what mode it was originally given | |
1666 | to us. */ | |
9840d99d | 1667 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1668 | |
753bd06a | 1669 | /* Force the constant into memory and put the address of the |
1670 | memory location into scratch_reg. */ | |
ed498904 | 1671 | const_mem = force_const_mem (mode, operand1); |
753bd06a | 1672 | xoperands[0] = scratch_reg; |
ed498904 | 1673 | xoperands[1] = XEXP (const_mem, 0); |
8f258b49 | 1674 | emit_move_sequence (xoperands, Pmode, 0); |
753bd06a | 1675 | |
1676 | /* Now load the destination register. */ | |
7014838c | 1677 | emit_insn (gen_rtx_SET (mode, operand0, |
ed498904 | 1678 | replace_equiv_address (const_mem, scratch_reg))); |
753bd06a | 1679 | return 1; |
1680 | } | |
e8fdbafa | 1681 | /* Handle secondary reloads for SAR. These occur when trying to load |
2a170404 | 1682 | the SAR from memory, FP register, or with a constant. */ |
6bcdc1fb | 1683 | else if (scratch_reg |
1684 | && GET_CODE (operand0) == REG | |
2a170404 | 1685 | && REGNO (operand0) < FIRST_PSEUDO_REGISTER |
e8fdbafa | 1686 | && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS |
1687 | && (GET_CODE (operand1) == MEM | |
7d43e0f7 | 1688 | || GET_CODE (operand1) == CONST_INT |
e8fdbafa | 1689 | || (GET_CODE (operand1) == REG |
6bcdc1fb | 1690 | && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))) |
e8fdbafa | 1691 | { |
7eac600c | 1692 | /* D might not fit in 14 bits either; for such cases load D into |
1693 | scratch reg. */ | |
1694 | if (GET_CODE (operand1) == MEM | |
853940d9 | 1695 | && !memory_address_p (GET_MODE (operand0), XEXP (operand1, 0))) |
7eac600c | 1696 | { |
fc4d127d | 1697 | /* We are reloading the address into the scratch register, so we |
1698 | want to make sure the scratch register is a full register. */ | |
9840d99d | 1699 | scratch_reg = force_mode (word_mode, scratch_reg); |
fc4d127d | 1700 | |
9840d99d | 1701 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); |
ad851752 | 1702 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, |
1703 | 0)), | |
440c23df | 1704 | Pmode, |
ad851752 | 1705 | XEXP (XEXP (operand1, 0), |
1706 | 0), | |
1707 | scratch_reg)); | |
fc4d127d | 1708 | |
1709 | /* Now we are going to load the scratch register from memory, | |
1710 | we want to load it in the same width as the original MEM, | |
1711 | which must be the same as the width of the ultimate destination, | |
1712 | OPERAND0. */ | |
9840d99d | 1713 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1714 | ||
ed498904 | 1715 | emit_move_insn (scratch_reg, |
1716 | replace_equiv_address (operand1, scratch_reg)); | |
7eac600c | 1717 | } |
1718 | else | |
fc4d127d | 1719 | { |
1720 | /* We want to load the scratch register using the same mode as | |
1721 | the ultimate destination. */ | |
9840d99d | 1722 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1723 | ||
fc4d127d | 1724 | emit_move_insn (scratch_reg, operand1); |
1725 | } | |
1726 | ||
1727 | /* And emit the insn to set the ultimate destination. We know that | |
1728 | the scratch register has the same mode as the destination at this | |
1729 | point. */ | |
e8fdbafa | 1730 | emit_move_insn (operand0, scratch_reg); |
1731 | return 1; | |
1732 | } | |
dbd3d89d | 1733 | /* Handle the most common case: storing into a register. */ |
d6f01525 | 1734 | else if (register_operand (operand0, mode)) |
87ad11b0 | 1735 | { |
1736 | if (register_operand (operand1, mode) | |
93f6e1c7 | 1737 | || (GET_CODE (operand1) == CONST_INT |
1738 | && cint_ok_for_move (INTVAL (operand1))) | |
891b55b4 | 1739 | || (operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1740 | || (GET_CODE (operand1) == HIGH |
df0651dc | 1741 | && !symbolic_operand (XEXP (operand1, 0), VOIDmode)) |
87ad11b0 | 1742 | /* Only `general_operands' can come here, so MEM is ok. */ |
1743 | || GET_CODE (operand1) == MEM) | |
1744 | { | |
dbd3d89d | 1745 | /* Various sets are created during RTL generation which don't |
1746 | have the REG_POINTER flag correctly set. After the CSE pass, | |
1747 | instruction recognition can fail if we don't consistently | |
1748 | set this flag when performing register copies. This should | |
1749 | also improve the opportunities for creating insns that use | |
1750 | unscaled indexing. */ | |
1751 | if (REG_P (operand0) && REG_P (operand1)) | |
1752 | { | |
1753 | if (REG_POINTER (operand1) | |
1754 | && !REG_POINTER (operand0) | |
1755 | && !HARD_REGISTER_P (operand0)) | |
1756 | copy_reg_pointer (operand0, operand1); | |
dbd3d89d | 1757 | } |
1758 | ||
1759 | /* When MEMs are broken out, the REG_POINTER flag doesn't | |
1760 | get set. In some cases, we can set the REG_POINTER flag | |
1761 | from the declaration for the MEM. */ | |
1762 | if (REG_P (operand0) | |
1763 | && GET_CODE (operand1) == MEM | |
1764 | && !REG_POINTER (operand0)) | |
1765 | { | |
1766 | tree decl = MEM_EXPR (operand1); | |
1767 | ||
1768 | /* Set the register pointer flag and register alignment | |
1769 | if the declaration for this memory reference is a | |
4d41e927 | 1770 | pointer type. */ |
1771 | if (decl) | |
dbd3d89d | 1772 | { |
1773 | tree type; | |
1774 | ||
1775 | /* If this is a COMPONENT_REF, use the FIELD_DECL from | |
1776 | tree operand 1. */ | |
1777 | if (TREE_CODE (decl) == COMPONENT_REF) | |
1778 | decl = TREE_OPERAND (decl, 1); | |
1779 | ||
1780 | type = TREE_TYPE (decl); | |
eec9c06d | 1781 | type = strip_array_types (type); |
dbd3d89d | 1782 | |
1783 | if (POINTER_TYPE_P (type)) | |
1784 | { | |
1785 | int align; | |
1786 | ||
1787 | type = TREE_TYPE (type); | |
1788 | /* Using TYPE_ALIGN_OK is rather conservative as | |
1789 | only the ada frontend actually sets it. */ | |
1790 | align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type) | |
1791 | : BITS_PER_UNIT); | |
1792 | mark_reg_pointer (operand0, align); | |
1793 | } | |
1794 | } | |
1795 | } | |
1796 | ||
ad851752 | 1797 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1798 | return 1; |
1799 | } | |
1800 | } | |
1801 | else if (GET_CODE (operand0) == MEM) | |
1802 | { | |
85eb4c6e | 1803 | if (mode == DFmode && operand1 == CONST0_RTX (mode) |
1804 | && !(reload_in_progress || reload_completed)) | |
1805 | { | |
1806 | rtx temp = gen_reg_rtx (DFmode); | |
1807 | ||
ad851752 | 1808 | emit_insn (gen_rtx_SET (VOIDmode, temp, operand1)); |
1809 | emit_insn (gen_rtx_SET (VOIDmode, operand0, temp)); | |
85eb4c6e | 1810 | return 1; |
1811 | } | |
891b55b4 | 1812 | if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1813 | { |
1814 | /* Run this case quickly. */ | |
ad851752 | 1815 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1816 | return 1; |
1817 | } | |
2ff4bf8d | 1818 | if (! (reload_in_progress || reload_completed)) |
87ad11b0 | 1819 | { |
1820 | operands[0] = validize_mem (operand0); | |
1821 | operands[1] = operand1 = force_reg (mode, operand1); | |
1822 | } | |
1823 | } | |
1824 | ||
37a75d53 | 1825 | /* Simplify the source if we need to. |
1826 | Note we do have to handle function labels here, even though we do | |
1827 | not consider them legitimate constants. Loop optimizations can | |
bea60f66 | 1828 | call the emit_move_xxx with one as a source. */ |
57ed30e5 | 1829 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) |
37a75d53 | 1830 | || function_label_operand (operand1, mode) |
2ee034bc | 1831 | || (GET_CODE (operand1) == HIGH |
63882853 | 1832 | && symbolic_operand (XEXP (operand1, 0), mode))) |
87ad11b0 | 1833 | { |
2ee034bc | 1834 | int ishighonly = 0; |
1835 | ||
1836 | if (GET_CODE (operand1) == HIGH) | |
1837 | { | |
1838 | ishighonly = 1; | |
1839 | operand1 = XEXP (operand1, 0); | |
1840 | } | |
87ad11b0 | 1841 | if (symbolic_operand (operand1, mode)) |
1842 | { | |
005a7dd0 | 1843 | /* Argh. The assembler and linker can't handle arithmetic |
81653f9b | 1844 | involving plabels. |
005a7dd0 | 1845 | |
81653f9b | 1846 | So we force the plabel into memory, load operand0 from |
1847 | the memory location, then add in the constant part. */ | |
37a75d53 | 1848 | if ((GET_CODE (operand1) == CONST |
1849 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1850 | && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode)) | |
1851 | || function_label_operand (operand1, mode)) | |
005a7dd0 | 1852 | { |
b3d569a0 | 1853 | rtx temp, const_part; |
81653f9b | 1854 | |
1855 | /* Figure out what (if any) scratch register to use. */ | |
1856 | if (reload_in_progress || reload_completed) | |
f756078b | 1857 | { |
1858 | scratch_reg = scratch_reg ? scratch_reg : operand0; | |
1859 | /* SCRATCH_REG will hold an address and maybe the actual | |
1860 | data. We want it in WORD_MODE regardless of what mode it | |
1861 | was originally given to us. */ | |
9840d99d | 1862 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1863 | } |
81653f9b | 1864 | else if (flag_pic) |
1865 | scratch_reg = gen_reg_rtx (Pmode); | |
1866 | ||
37a75d53 | 1867 | if (GET_CODE (operand1) == CONST) |
1868 | { | |
1869 | /* Save away the constant part of the expression. */ | |
1870 | const_part = XEXP (XEXP (operand1, 0), 1); | |
ecf2283d | 1871 | gcc_assert (GET_CODE (const_part) == CONST_INT); |
37a75d53 | 1872 | |
1873 | /* Force the function label into memory. */ | |
1874 | temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0)); | |
1875 | } | |
1876 | else | |
1877 | { | |
1878 | /* No constant part. */ | |
1879 | const_part = NULL_RTX; | |
005a7dd0 | 1880 | |
37a75d53 | 1881 | /* Force the function label into memory. */ |
1882 | temp = force_const_mem (mode, operand1); | |
1883 | } | |
9840d99d | 1884 | |
81653f9b | 1885 | |
1886 | /* Get the address of the memory location. PIC-ify it if | |
1887 | necessary. */ | |
1888 | temp = XEXP (temp, 0); | |
1889 | if (flag_pic) | |
1890 | temp = legitimize_pic_address (temp, mode, scratch_reg); | |
1891 | ||
1892 | /* Put the address of the memory location into our destination | |
1893 | register. */ | |
1894 | operands[1] = temp; | |
1895 | emit_move_sequence (operands, mode, scratch_reg); | |
1896 | ||
1897 | /* Now load from the memory location into our destination | |
1898 | register. */ | |
ad851752 | 1899 | operands[1] = gen_rtx_MEM (Pmode, operands[0]); |
81653f9b | 1900 | emit_move_sequence (operands, mode, scratch_reg); |
1901 | ||
1902 | /* And add back in the constant part. */ | |
37a75d53 | 1903 | if (const_part != NULL_RTX) |
1904 | expand_inc (operand0, const_part); | |
81653f9b | 1905 | |
1906 | return 1; | |
005a7dd0 | 1907 | } |
1908 | ||
87ad11b0 | 1909 | if (flag_pic) |
1910 | { | |
2ff4bf8d | 1911 | rtx temp; |
1912 | ||
1913 | if (reload_in_progress || reload_completed) | |
f756078b | 1914 | { |
1915 | temp = scratch_reg ? scratch_reg : operand0; | |
1916 | /* TEMP will hold an address and maybe the actual | |
1917 | data. We want it in WORD_MODE regardless of what mode it | |
1918 | was originally given to us. */ | |
9840d99d | 1919 | temp = force_mode (word_mode, temp); |
f756078b | 1920 | } |
2ff4bf8d | 1921 | else |
1922 | temp = gen_reg_rtx (Pmode); | |
6d36483b | 1923 | |
81653f9b | 1924 | /* (const (plus (symbol) (const_int))) must be forced to |
1925 | memory during/after reload if the const_int will not fit | |
1926 | in 14 bits. */ | |
1927 | if (GET_CODE (operand1) == CONST | |
96b86ab6 | 1928 | && GET_CODE (XEXP (operand1, 0)) == PLUS |
1929 | && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT | |
1930 | && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)) | |
1931 | && (reload_completed || reload_in_progress) | |
1932 | && flag_pic) | |
1933 | { | |
ed498904 | 1934 | rtx const_mem = force_const_mem (mode, operand1); |
4109fd6d | 1935 | operands[1] = legitimize_pic_address (XEXP (const_mem, 0), |
96b86ab6 | 1936 | mode, temp); |
ed498904 | 1937 | operands[1] = replace_equiv_address (const_mem, operands[1]); |
96b86ab6 | 1938 | emit_move_sequence (operands, mode, temp); |
1939 | } | |
005a7dd0 | 1940 | else |
1941 | { | |
1942 | operands[1] = legitimize_pic_address (operand1, mode, temp); | |
dbd3d89d | 1943 | if (REG_P (operand0) && REG_P (operands[1])) |
1944 | copy_reg_pointer (operand0, operands[1]); | |
ad851752 | 1945 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1])); |
005a7dd0 | 1946 | } |
87ad11b0 | 1947 | } |
b4a7bf10 | 1948 | /* On the HPPA, references to data space are supposed to use dp, |
1949 | register 27, but showing it in the RTL inhibits various cse | |
1950 | and loop optimizations. */ | |
6d36483b | 1951 | else |
87ad11b0 | 1952 | { |
005a7dd0 | 1953 | rtx temp, set; |
2ee034bc | 1954 | |
6d36483b | 1955 | if (reload_in_progress || reload_completed) |
f756078b | 1956 | { |
1957 | temp = scratch_reg ? scratch_reg : operand0; | |
1958 | /* TEMP will hold an address and maybe the actual | |
1959 | data. We want it in WORD_MODE regardless of what mode it | |
1960 | was originally given to us. */ | |
9840d99d | 1961 | temp = force_mode (word_mode, temp); |
f756078b | 1962 | } |
2ee034bc | 1963 | else |
1964 | temp = gen_reg_rtx (mode); | |
1965 | ||
42819d4e | 1966 | /* Loading a SYMBOL_REF into a register makes that register |
9840d99d | 1967 | safe to be used as the base in an indexed address. |
42819d4e | 1968 | |
1969 | Don't mark hard registers though. That loses. */ | |
47a61b79 | 1970 | if (GET_CODE (operand0) == REG |
1971 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
dbd3d89d | 1972 | mark_reg_pointer (operand0, BITS_PER_UNIT); |
42819d4e | 1973 | if (REGNO (temp) >= FIRST_PSEUDO_REGISTER) |
dbd3d89d | 1974 | mark_reg_pointer (temp, BITS_PER_UNIT); |
1975 | ||
2ee034bc | 1976 | if (ishighonly) |
ad851752 | 1977 | set = gen_rtx_SET (mode, operand0, temp); |
2ee034bc | 1978 | else |
7014838c | 1979 | set = gen_rtx_SET (VOIDmode, |
1980 | operand0, | |
ad851752 | 1981 | gen_rtx_LO_SUM (mode, temp, operand1)); |
6d36483b | 1982 | |
ad851752 | 1983 | emit_insn (gen_rtx_SET (VOIDmode, |
1984 | temp, | |
1985 | gen_rtx_HIGH (mode, operand1))); | |
d2498717 | 1986 | emit_insn (set); |
166bf021 | 1987 | |
87ad11b0 | 1988 | } |
2ee034bc | 1989 | return 1; |
87ad11b0 | 1990 | } |
716b2c5a | 1991 | else if (pa_tls_referenced_p (operand1)) |
1992 | { | |
1993 | rtx tmp = operand1; | |
1994 | rtx addend = NULL; | |
1995 | ||
1996 | if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS) | |
1997 | { | |
1998 | addend = XEXP (XEXP (tmp, 0), 1); | |
1999 | tmp = XEXP (XEXP (tmp, 0), 0); | |
2000 | } | |
2001 | ||
2002 | gcc_assert (GET_CODE (tmp) == SYMBOL_REF); | |
2003 | tmp = legitimize_tls_address (tmp); | |
2004 | if (addend) | |
2005 | { | |
2006 | tmp = gen_rtx_PLUS (mode, tmp, addend); | |
2007 | tmp = force_operand (tmp, operands[0]); | |
2008 | } | |
2009 | operands[1] = tmp; | |
2010 | } | |
42faba01 | 2011 | else if (GET_CODE (operand1) != CONST_INT |
6bcdc1fb | 2012 | || !cint_ok_for_move (INTVAL (operand1))) |
87ad11b0 | 2013 | { |
6bcdc1fb | 2014 | rtx insn, temp; |
2015 | rtx op1 = operand1; | |
6edde44b | 2016 | HOST_WIDE_INT value = 0; |
6bcdc1fb | 2017 | HOST_WIDE_INT insv = 0; |
2018 | int insert = 0; | |
2019 | ||
6edde44b | 2020 | if (GET_CODE (operand1) == CONST_INT) |
2021 | value = INTVAL (operand1); | |
2022 | ||
6bcdc1fb | 2023 | if (TARGET_64BIT |
2024 | && GET_CODE (operand1) == CONST_INT | |
b7d86581 | 2025 | && HOST_BITS_PER_WIDE_INT > 32 |
5e3c5739 | 2026 | && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32) |
2027 | { | |
b7d86581 | 2028 | HOST_WIDE_INT nval; |
5e3c5739 | 2029 | |
93f6e1c7 | 2030 | /* Extract the low order 32 bits of the value and sign extend. |
2031 | If the new value is the same as the original value, we can | |
2032 | can use the original value as-is. If the new value is | |
2033 | different, we use it and insert the most-significant 32-bits | |
2034 | of the original value into the final result. */ | |
6bcdc1fb | 2035 | nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1)) |
b7d86581 | 2036 | ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31); |
6bcdc1fb | 2037 | if (value != nval) |
5e3c5739 | 2038 | { |
93f6e1c7 | 2039 | #if HOST_BITS_PER_WIDE_INT > 32 |
6bcdc1fb | 2040 | insv = value >= 0 ? value >> 32 : ~(~value >> 32); |
93f6e1c7 | 2041 | #endif |
6bcdc1fb | 2042 | insert = 1; |
2043 | value = nval; | |
5e3c5739 | 2044 | operand1 = GEN_INT (nval); |
2045 | } | |
2046 | } | |
2ff4bf8d | 2047 | |
2048 | if (reload_in_progress || reload_completed) | |
6bcdc1fb | 2049 | temp = scratch_reg ? scratch_reg : operand0; |
2ff4bf8d | 2050 | else |
2051 | temp = gen_reg_rtx (mode); | |
2052 | ||
7c4d3047 | 2053 | /* We don't directly split DImode constants on 32-bit targets |
2054 | because PLUS uses an 11-bit immediate and the insn sequence | |
2055 | generated is not as efficient as the one using HIGH/LO_SUM. */ | |
2056 | if (GET_CODE (operand1) == CONST_INT | |
58cac6ba | 2057 | && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD |
6bcdc1fb | 2058 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
2059 | && !insert) | |
93f6e1c7 | 2060 | { |
7c4d3047 | 2061 | /* Directly break constant into high and low parts. This |
93f6e1c7 | 2062 | provides better optimization opportunities because various |
2063 | passes recognize constants split with PLUS but not LO_SUM. | |
2064 | We use a 14-bit signed low part except when the addition | |
2065 | of 0x4000 to the high part might change the sign of the | |
2066 | high part. */ | |
93f6e1c7 | 2067 | HOST_WIDE_INT low = value & 0x3fff; |
2068 | HOST_WIDE_INT high = value & ~ 0x3fff; | |
2069 | ||
2070 | if (low >= 0x2000) | |
2071 | { | |
2072 | if (high == 0x7fffc000 || (mode == HImode && high == 0x4000)) | |
2073 | high += 0x2000; | |
2074 | else | |
2075 | high += 0x4000; | |
2076 | } | |
2077 | ||
2078 | low = value - high; | |
5e3c5739 | 2079 | |
93f6e1c7 | 2080 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high))); |
2081 | operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low)); | |
2082 | } | |
2083 | else | |
5e3c5739 | 2084 | { |
93f6e1c7 | 2085 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
2086 | gen_rtx_HIGH (mode, operand1))); | |
2087 | operands[1] = gen_rtx_LO_SUM (mode, temp, operand1); | |
5e3c5739 | 2088 | } |
9840d99d | 2089 | |
6bcdc1fb | 2090 | insn = emit_move_insn (operands[0], operands[1]); |
2091 | ||
2092 | /* Now insert the most significant 32 bits of the value | |
2093 | into the register. When we don't have a second register | |
2094 | available, it could take up to nine instructions to load | |
2095 | a 64-bit integer constant. Prior to reload, we force | |
2096 | constants that would take more than three instructions | |
2097 | to load to the constant pool. During and after reload, | |
2098 | we have to handle all possible values. */ | |
2099 | if (insert) | |
2100 | { | |
2101 | /* Use a HIGH/LO_SUM/INSV sequence if we have a second | |
2102 | register and the value to be inserted is outside the | |
2103 | range that can be loaded with three depdi instructions. */ | |
2104 | if (temp != operand0 && (insv >= 16384 || insv < -16384)) | |
2105 | { | |
2106 | operand1 = GEN_INT (insv); | |
2107 | ||
2108 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
2109 | gen_rtx_HIGH (mode, operand1))); | |
2110 | emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1)); | |
2111 | emit_insn (gen_insv (operand0, GEN_INT (32), | |
2112 | const0_rtx, temp)); | |
2113 | } | |
2114 | else | |
2115 | { | |
2116 | int len = 5, pos = 27; | |
2117 | ||
2118 | /* Insert the bits using the depdi instruction. */ | |
2119 | while (pos >= 0) | |
2120 | { | |
2121 | HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16; | |
2122 | HOST_WIDE_INT sign = v5 < 0; | |
2123 | ||
2124 | /* Left extend the insertion. */ | |
2125 | insv = (insv >= 0 ? insv >> len : ~(~insv >> len)); | |
2126 | while (pos > 0 && (insv & 1) == sign) | |
2127 | { | |
2128 | insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1)); | |
2129 | len += 1; | |
2130 | pos -= 1; | |
2131 | } | |
2132 | ||
2133 | emit_insn (gen_insv (operand0, GEN_INT (len), | |
2134 | GEN_INT (pos), GEN_INT (v5))); | |
2135 | ||
2136 | len = pos > 0 && pos < 5 ? pos : 5; | |
2137 | pos -= len; | |
2138 | } | |
2139 | } | |
2140 | } | |
93f6e1c7 | 2141 | |
24153880 | 2142 | set_unique_reg_note (insn, REG_EQUAL, op1); |
93f6e1c7 | 2143 | |
5e3c5739 | 2144 | return 1; |
87ad11b0 | 2145 | } |
2146 | } | |
2147 | /* Now have insn-emit do whatever it normally does. */ | |
2148 | return 0; | |
2149 | } | |
2150 | ||
1946138e | 2151 | /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning |
bd49d362 | 2152 | it will need a link/runtime reloc). */ |
1946138e | 2153 | |
2154 | int | |
5c1d8983 | 2155 | reloc_needed (tree exp) |
1946138e | 2156 | { |
2157 | int reloc = 0; | |
2158 | ||
2159 | switch (TREE_CODE (exp)) | |
2160 | { | |
2161 | case ADDR_EXPR: | |
2162 | return 1; | |
2163 | ||
0de36bdb | 2164 | case POINTER_PLUS_EXPR: |
1946138e | 2165 | case PLUS_EXPR: |
2166 | case MINUS_EXPR: | |
2167 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
2168 | reloc |= reloc_needed (TREE_OPERAND (exp, 1)); | |
2169 | break; | |
2170 | ||
72dd6141 | 2171 | CASE_CONVERT: |
1946138e | 2172 | case NON_LVALUE_EXPR: |
2173 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
2174 | break; | |
2175 | ||
2176 | case CONSTRUCTOR: | |
2177 | { | |
729d4a82 | 2178 | tree value; |
2179 | unsigned HOST_WIDE_INT ix; | |
2180 | ||
2181 | FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value) | |
2182 | if (value) | |
2183 | reloc |= reloc_needed (value); | |
1946138e | 2184 | } |
2185 | break; | |
2186 | ||
2187 | case ERROR_MARK: | |
2188 | break; | |
7d27e4c9 | 2189 | |
2190 | default: | |
2191 | break; | |
1946138e | 2192 | } |
2193 | return reloc; | |
2194 | } | |
2195 | ||
7811991d | 2196 | /* Does operand (which is a symbolic_operand) live in text space? |
2197 | If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info, | |
2198 | will be true. */ | |
87ad11b0 | 2199 | |
2200 | int | |
5c1d8983 | 2201 | read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 2202 | { |
2203 | if (GET_CODE (operand) == CONST) | |
2204 | operand = XEXP (XEXP (operand, 0), 0); | |
b4a7bf10 | 2205 | if (flag_pic) |
2206 | { | |
2207 | if (GET_CODE (operand) == SYMBOL_REF) | |
2208 | return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand); | |
2209 | } | |
2210 | else | |
2211 | { | |
2212 | if (GET_CODE (operand) == SYMBOL_REF) | |
2213 | return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand); | |
2214 | } | |
87ad11b0 | 2215 | return 1; |
2216 | } | |
6d36483b | 2217 | |
87ad11b0 | 2218 | \f |
2219 | /* Return the best assembler insn template | |
5aedf60c | 2220 | for moving operands[1] into operands[0] as a fullword. */ |
611a88e1 | 2221 | const char * |
5c1d8983 | 2222 | singlemove_string (rtx *operands) |
87ad11b0 | 2223 | { |
3745c59b | 2224 | HOST_WIDE_INT intval; |
2225 | ||
87ad11b0 | 2226 | if (GET_CODE (operands[0]) == MEM) |
2227 | return "stw %r1,%0"; | |
3745c59b | 2228 | if (GET_CODE (operands[1]) == MEM) |
87ad11b0 | 2229 | return "ldw %1,%0"; |
3745c59b | 2230 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
9d5108ea | 2231 | { |
3745c59b | 2232 | long i; |
2233 | REAL_VALUE_TYPE d; | |
9d5108ea | 2234 | |
ecf2283d | 2235 | gcc_assert (GET_MODE (operands[1]) == SFmode); |
9d5108ea | 2236 | |
3745c59b | 2237 | /* Translate the CONST_DOUBLE to a CONST_INT with the same target |
2238 | bit pattern. */ | |
2239 | REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]); | |
2240 | REAL_VALUE_TO_TARGET_SINGLE (d, i); | |
9d5108ea | 2241 | |
3745c59b | 2242 | operands[1] = GEN_INT (i); |
2243 | /* Fall through to CONST_INT case. */ | |
2244 | } | |
2245 | if (GET_CODE (operands[1]) == CONST_INT) | |
9d5108ea | 2246 | { |
3745c59b | 2247 | intval = INTVAL (operands[1]); |
2248 | ||
2249 | if (VAL_14_BITS_P (intval)) | |
2250 | return "ldi %1,%0"; | |
2251 | else if ((intval & 0x7ff) == 0) | |
2252 | return "ldil L'%1,%0"; | |
2253 | else if (zdepi_cint_p (intval)) | |
e4065f95 | 2254 | return "{zdepi %Z1,%0|depwi,z %Z1,%0}"; |
9d5108ea | 2255 | else |
2256 | return "ldil L'%1,%0\n\tldo R'%1(%0),%0"; | |
2257 | } | |
87ad11b0 | 2258 | return "copy %1,%0"; |
2259 | } | |
2260 | \f | |
2261 | ||
201f01e9 | 2262 | /* Compute position (in OP[1]) and width (in OP[2]) |
2263 | useful for copying IMM to a register using the zdepi | |
2264 | instructions. Store the immediate value to insert in OP[0]. */ | |
611a88e1 | 2265 | static void |
5c1d8983 | 2266 | compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
7e10ba53 | 2267 | { |
e057641f | 2268 | int lsb, len; |
7e10ba53 | 2269 | |
e057641f | 2270 | /* Find the least significant set bit in IMM. */ |
2271 | for (lsb = 0; lsb < 32; lsb++) | |
7e10ba53 | 2272 | { |
e057641f | 2273 | if ((imm & 1) != 0) |
7e10ba53 | 2274 | break; |
e057641f | 2275 | imm >>= 1; |
7e10ba53 | 2276 | } |
2277 | ||
e057641f | 2278 | /* Choose variants based on *sign* of the 5-bit field. */ |
2279 | if ((imm & 0x10) == 0) | |
2280 | len = (lsb <= 28) ? 4 : 32 - lsb; | |
7e10ba53 | 2281 | else |
2282 | { | |
e057641f | 2283 | /* Find the width of the bitstring in IMM. */ |
eab96f1c | 2284 | for (len = 5; len < 32 - lsb; len++) |
7e10ba53 | 2285 | { |
eab96f1c | 2286 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
7e10ba53 | 2287 | break; |
7e10ba53 | 2288 | } |
2289 | ||
e057641f | 2290 | /* Sign extend IMM as a 5-bit value. */ |
2291 | imm = (imm & 0xf) - 0x10; | |
7e10ba53 | 2292 | } |
2293 | ||
42faba01 | 2294 | op[0] = imm; |
2295 | op[1] = 31 - lsb; | |
2296 | op[2] = len; | |
7e10ba53 | 2297 | } |
2298 | ||
5e3c5739 | 2299 | /* Compute position (in OP[1]) and width (in OP[2]) |
2300 | useful for copying IMM to a register using the depdi,z | |
2301 | instructions. Store the immediate value to insert in OP[0]. */ | |
2302 | void | |
5c1d8983 | 2303 | compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
5e3c5739 | 2304 | { |
eab96f1c | 2305 | int lsb, len, maxlen; |
2306 | ||
2307 | maxlen = MIN (HOST_BITS_PER_WIDE_INT, 64); | |
5e3c5739 | 2308 | |
2309 | /* Find the least significant set bit in IMM. */ | |
eab96f1c | 2310 | for (lsb = 0; lsb < maxlen; lsb++) |
5e3c5739 | 2311 | { |
2312 | if ((imm & 1) != 0) | |
2313 | break; | |
2314 | imm >>= 1; | |
2315 | } | |
2316 | ||
2317 | /* Choose variants based on *sign* of the 5-bit field. */ | |
2318 | if ((imm & 0x10) == 0) | |
eab96f1c | 2319 | len = (lsb <= maxlen - 4) ? 4 : maxlen - lsb; |
5e3c5739 | 2320 | else |
2321 | { | |
2322 | /* Find the width of the bitstring in IMM. */ | |
eab96f1c | 2323 | for (len = 5; len < maxlen - lsb; len++) |
5e3c5739 | 2324 | { |
ea52c577 | 2325 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
5e3c5739 | 2326 | break; |
2327 | } | |
2328 | ||
eab96f1c | 2329 | /* Extend length if host is narrow and IMM is negative. */ |
2330 | if (HOST_BITS_PER_WIDE_INT == 32 && len == maxlen - lsb) | |
2331 | len += 32; | |
2332 | ||
5e3c5739 | 2333 | /* Sign extend IMM as a 5-bit value. */ |
2334 | imm = (imm & 0xf) - 0x10; | |
2335 | } | |
2336 | ||
2337 | op[0] = imm; | |
2338 | op[1] = 63 - lsb; | |
2339 | op[2] = len; | |
2340 | } | |
2341 | ||
87ad11b0 | 2342 | /* Output assembler code to perform a doubleword move insn |
2343 | with operands OPERANDS. */ | |
2344 | ||
611a88e1 | 2345 | const char * |
5c1d8983 | 2346 | output_move_double (rtx *operands) |
87ad11b0 | 2347 | { |
2348 | enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1; | |
2349 | rtx latehalf[2]; | |
2350 | rtx addreg0 = 0, addreg1 = 0; | |
2351 | ||
2352 | /* First classify both operands. */ | |
2353 | ||
2354 | if (REG_P (operands[0])) | |
2355 | optype0 = REGOP; | |
2356 | else if (offsettable_memref_p (operands[0])) | |
2357 | optype0 = OFFSOP; | |
2358 | else if (GET_CODE (operands[0]) == MEM) | |
2359 | optype0 = MEMOP; | |
2360 | else | |
2361 | optype0 = RNDOP; | |
2362 | ||
2363 | if (REG_P (operands[1])) | |
2364 | optype1 = REGOP; | |
2365 | else if (CONSTANT_P (operands[1])) | |
2366 | optype1 = CNSTOP; | |
2367 | else if (offsettable_memref_p (operands[1])) | |
2368 | optype1 = OFFSOP; | |
2369 | else if (GET_CODE (operands[1]) == MEM) | |
2370 | optype1 = MEMOP; | |
2371 | else | |
2372 | optype1 = RNDOP; | |
2373 | ||
2374 | /* Check for the cases that the operand constraints are not | |
ecf2283d | 2375 | supposed to allow to happen. */ |
2376 | gcc_assert (optype0 == REGOP || optype1 == REGOP); | |
87ad11b0 | 2377 | |
e106b699 | 2378 | /* Handle copies between general and floating registers. */ |
2379 | ||
2380 | if (optype0 == REGOP && optype1 == REGOP | |
2381 | && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])) | |
2382 | { | |
2383 | if (FP_REG_P (operands[0])) | |
2384 | { | |
2385 | output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands); | |
2386 | output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands); | |
2387 | return "{fldds|fldd} -16(%%sp),%0"; | |
2388 | } | |
2389 | else | |
2390 | { | |
2391 | output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands); | |
2392 | output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands); | |
2393 | return "{ldws|ldw} -12(%%sp),%R0"; | |
2394 | } | |
2395 | } | |
2396 | ||
87ad11b0 | 2397 | /* Handle auto decrementing and incrementing loads and stores |
2398 | specifically, since the structure of the function doesn't work | |
2399 | for them without major modification. Do it better when we learn | |
2400 | this port about the general inc/dec addressing of PA. | |
2401 | (This was written by tege. Chide him if it doesn't work.) */ | |
2402 | ||
2403 | if (optype0 == MEMOP) | |
2404 | { | |
1df0058a | 2405 | /* We have to output the address syntax ourselves, since print_operand |
2406 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2407 | ||
87ad11b0 | 2408 | rtx addr = XEXP (operands[0], 0); |
1df0058a | 2409 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) |
87ad11b0 | 2410 | { |
ad851752 | 2411 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2412 | |
2413 | operands[0] = XEXP (addr, 0); | |
ecf2283d | 2414 | gcc_assert (GET_CODE (operands[1]) == REG |
2415 | && GET_CODE (operands[0]) == REG); | |
1df0058a | 2416 | |
ecf2283d | 2417 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); |
2418 | ||
2419 | /* No overlap between high target register and address | |
2420 | register. (We do this in a non-obvious way to | |
2421 | save a register file writeback) */ | |
2422 | if (GET_CODE (addr) == POST_INC) | |
2423 | return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)"; | |
2424 | return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)"; | |
a3217f65 | 2425 | } |
1df0058a | 2426 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) |
a3217f65 | 2427 | { |
ad851752 | 2428 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2429 | |
2430 | operands[0] = XEXP (addr, 0); | |
ecf2283d | 2431 | gcc_assert (GET_CODE (operands[1]) == REG |
2432 | && GET_CODE (operands[0]) == REG); | |
2433 | ||
2434 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); | |
2435 | /* No overlap between high target register and address | |
2436 | register. (We do this in a non-obvious way to save a | |
2437 | register file writeback) */ | |
2438 | if (GET_CODE (addr) == PRE_INC) | |
2439 | return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)"; | |
2440 | return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)"; | |
87ad11b0 | 2441 | } |
2442 | } | |
2443 | if (optype1 == MEMOP) | |
2444 | { | |
2445 | /* We have to output the address syntax ourselves, since print_operand | |
2446 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2447 | ||
2448 | rtx addr = XEXP (operands[1], 0); | |
2449 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) | |
2450 | { | |
ad851752 | 2451 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2452 | |
2453 | operands[1] = XEXP (addr, 0); | |
ecf2283d | 2454 | gcc_assert (GET_CODE (operands[0]) == REG |
2455 | && GET_CODE (operands[1]) == REG); | |
87ad11b0 | 2456 | |
2457 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2458 | { | |
2459 | /* No overlap between high target register and address | |
3857fa62 | 2460 | register. (We do this in a non-obvious way to |
87ad11b0 | 2461 | save a register file writeback) */ |
2462 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2463 | return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0"; |
01fd4b49 | 2464 | return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0"; |
87ad11b0 | 2465 | } |
2466 | else | |
2467 | { | |
2468 | /* This is an undefined situation. We should load into the | |
2469 | address register *and* update that register. Probably | |
2470 | we don't need to handle this at all. */ | |
2471 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2472 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0"; |
2473 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0"; | |
87ad11b0 | 2474 | } |
2475 | } | |
2476 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) | |
2477 | { | |
ad851752 | 2478 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2479 | |
2480 | operands[1] = XEXP (addr, 0); | |
ecf2283d | 2481 | gcc_assert (GET_CODE (operands[0]) == REG |
2482 | && GET_CODE (operands[1]) == REG); | |
87ad11b0 | 2483 | |
2484 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2485 | { | |
2486 | /* No overlap between high target register and address | |
3857fa62 | 2487 | register. (We do this in a non-obvious way to |
87ad11b0 | 2488 | save a register file writeback) */ |
2489 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2490 | return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0"; |
2491 | return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0"; | |
87ad11b0 | 2492 | } |
2493 | else | |
2494 | { | |
2495 | /* This is an undefined situation. We should load into the | |
2496 | address register *and* update that register. Probably | |
2497 | we don't need to handle this at all. */ | |
2498 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2499 | return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0"; |
2500 | return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0"; | |
87ad11b0 | 2501 | } |
2502 | } | |
12b02046 | 2503 | else if (GET_CODE (addr) == PLUS |
2504 | && GET_CODE (XEXP (addr, 0)) == MULT) | |
2505 | { | |
b2f8bd14 | 2506 | rtx xoperands[4]; |
ad851752 | 2507 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
12b02046 | 2508 | |
2509 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2510 | { | |
12b02046 | 2511 | xoperands[0] = high_reg; |
2512 | xoperands[1] = XEXP (addr, 1); | |
2513 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2514 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2515 | output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}", |
2516 | xoperands); | |
34940871 | 2517 | return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; |
12b02046 | 2518 | } |
2519 | else | |
2520 | { | |
12b02046 | 2521 | xoperands[0] = high_reg; |
2522 | xoperands[1] = XEXP (addr, 1); | |
2523 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2524 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2525 | output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}", |
2526 | xoperands); | |
34940871 | 2527 | return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0"; |
12b02046 | 2528 | } |
12b02046 | 2529 | } |
87ad11b0 | 2530 | } |
2531 | ||
2532 | /* If an operand is an unoffsettable memory ref, find a register | |
2533 | we can increment temporarily to make it refer to the second word. */ | |
2534 | ||
2535 | if (optype0 == MEMOP) | |
2536 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2537 | ||
2538 | if (optype1 == MEMOP) | |
2539 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2540 | ||
2541 | /* Ok, we can do one word at a time. | |
2542 | Normally we do the low-numbered word first. | |
2543 | ||
2544 | In either case, set up in LATEHALF the operands to use | |
2545 | for the high-numbered word and in some cases alter the | |
2546 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2547 | ||
2548 | if (optype0 == REGOP) | |
ad851752 | 2549 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
87ad11b0 | 2550 | else if (optype0 == OFFSOP) |
eafc6604 | 2551 | latehalf[0] = adjust_address (operands[0], SImode, 4); |
87ad11b0 | 2552 | else |
2553 | latehalf[0] = operands[0]; | |
2554 | ||
2555 | if (optype1 == REGOP) | |
ad851752 | 2556 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
87ad11b0 | 2557 | else if (optype1 == OFFSOP) |
eafc6604 | 2558 | latehalf[1] = adjust_address (operands[1], SImode, 4); |
87ad11b0 | 2559 | else if (optype1 == CNSTOP) |
2560 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2561 | else | |
2562 | latehalf[1] = operands[1]; | |
2563 | ||
2564 | /* If the first move would clobber the source of the second one, | |
2565 | do them in the other order. | |
2566 | ||
cf489d53 | 2567 | This can happen in two cases: |
87ad11b0 | 2568 | |
cf489d53 | 2569 | mem -> register where the first half of the destination register |
2570 | is the same register used in the memory's address. Reload | |
2571 | can create such insns. | |
87ad11b0 | 2572 | |
cf489d53 | 2573 | mem in this case will be either register indirect or register |
9840d99d | 2574 | indirect plus a valid offset. |
cf489d53 | 2575 | |
2576 | register -> register move where REGNO(dst) == REGNO(src + 1) | |
9840d99d | 2577 | someone (Tim/Tege?) claimed this can happen for parameter loads. |
cf489d53 | 2578 | |
2579 | Handle mem -> register case first. */ | |
2580 | if (optype0 == REGOP | |
2581 | && (optype1 == MEMOP || optype1 == OFFSOP) | |
2582 | && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2583 | operands[1], 0)) | |
87ad11b0 | 2584 | { |
87ad11b0 | 2585 | /* Do the late half first. */ |
2586 | if (addreg1) | |
6a5d085a | 2587 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2588 | output_asm_insn (singlemove_string (latehalf), latehalf); |
cf489d53 | 2589 | |
2590 | /* Then clobber. */ | |
87ad11b0 | 2591 | if (addreg1) |
6a5d085a | 2592 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2593 | return singlemove_string (operands); |
2594 | } | |
2595 | ||
cf489d53 | 2596 | /* Now handle register -> register case. */ |
c4fa5937 | 2597 | if (optype0 == REGOP && optype1 == REGOP |
2598 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
2599 | { | |
2600 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2601 | return singlemove_string (operands); | |
2602 | } | |
2603 | ||
87ad11b0 | 2604 | /* Normal case: do the two words, low-numbered first. */ |
2605 | ||
2606 | output_asm_insn (singlemove_string (operands), operands); | |
2607 | ||
2608 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2609 | if (addreg0) | |
6a5d085a | 2610 | output_asm_insn ("ldo 4(%0),%0", &addreg0); |
87ad11b0 | 2611 | if (addreg1) |
6a5d085a | 2612 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2613 | |
2614 | /* Do that word. */ | |
2615 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2616 | ||
2617 | /* Undo the adds we just did. */ | |
2618 | if (addreg0) | |
6a5d085a | 2619 | output_asm_insn ("ldo -4(%0),%0", &addreg0); |
87ad11b0 | 2620 | if (addreg1) |
6a5d085a | 2621 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2622 | |
2623 | return ""; | |
2624 | } | |
2625 | \f | |
611a88e1 | 2626 | const char * |
5c1d8983 | 2627 | output_fp_move_double (rtx *operands) |
87ad11b0 | 2628 | { |
2629 | if (FP_REG_P (operands[0])) | |
2630 | { | |
6d36483b | 2631 | if (FP_REG_P (operands[1]) |
891b55b4 | 2632 | || operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
c6ae275c | 2633 | output_asm_insn ("fcpy,dbl %f1,%0", operands); |
6d36483b | 2634 | else |
27ef382d | 2635 | output_asm_insn ("fldd%F1 %1,%0", operands); |
87ad11b0 | 2636 | } |
2637 | else if (FP_REG_P (operands[1])) | |
2638 | { | |
27ef382d | 2639 | output_asm_insn ("fstd%F0 %1,%0", operands); |
87ad11b0 | 2640 | } |
ecf2283d | 2641 | else |
891b55b4 | 2642 | { |
ecf2283d | 2643 | rtx xoperands[2]; |
2644 | ||
2645 | gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0]))); | |
2646 | ||
6d36483b | 2647 | /* This is a pain. You have to be prepared to deal with an |
01cc3b75 | 2648 | arbitrary address here including pre/post increment/decrement. |
891b55b4 | 2649 | |
2650 | so avoid this in the MD. */ | |
ecf2283d | 2651 | gcc_assert (GET_CODE (operands[0]) == REG); |
2652 | ||
2653 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2654 | xoperands[0] = operands[0]; | |
2655 | output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands); | |
891b55b4 | 2656 | } |
87ad11b0 | 2657 | return ""; |
2658 | } | |
2659 | \f | |
2660 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2661 | ADDR can be effectively incremented by incrementing REG. */ | |
2662 | ||
2663 | static rtx | |
5c1d8983 | 2664 | find_addr_reg (rtx addr) |
87ad11b0 | 2665 | { |
2666 | while (GET_CODE (addr) == PLUS) | |
2667 | { | |
2668 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2669 | addr = XEXP (addr, 0); | |
2670 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2671 | addr = XEXP (addr, 1); | |
2672 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2673 | addr = XEXP (addr, 1); | |
2674 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2675 | addr = XEXP (addr, 0); | |
2676 | else | |
ecf2283d | 2677 | gcc_unreachable (); |
87ad11b0 | 2678 | } |
ecf2283d | 2679 | gcc_assert (GET_CODE (addr) == REG); |
2680 | return addr; | |
87ad11b0 | 2681 | } |
2682 | ||
87ad11b0 | 2683 | /* Emit code to perform a block move. |
2684 | ||
87ad11b0 | 2685 | OPERANDS[0] is the destination pointer as a REG, clobbered. |
2686 | OPERANDS[1] is the source pointer as a REG, clobbered. | |
42819d4e | 2687 | OPERANDS[2] is a register for temporary storage. |
87ad11b0 | 2688 | OPERANDS[3] is a register for temporary storage. |
a7e1bb24 | 2689 | OPERANDS[4] is the size as a CONST_INT |
9840d99d | 2690 | OPERANDS[5] is the alignment safe to use, as a CONST_INT. |
5aedf60c | 2691 | OPERANDS[6] is another temporary register. */ |
87ad11b0 | 2692 | |
611a88e1 | 2693 | const char * |
5c1d8983 | 2694 | output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) |
87ad11b0 | 2695 | { |
2696 | int align = INTVAL (operands[5]); | |
42819d4e | 2697 | unsigned long n_bytes = INTVAL (operands[4]); |
87ad11b0 | 2698 | |
a7e1bb24 | 2699 | /* We can't move more than a word at a time because the PA |
87ad11b0 | 2700 | has no longer integer move insns. (Could use fp mem ops?) */ |
a7e1bb24 | 2701 | if (align > (TARGET_64BIT ? 8 : 4)) |
2702 | align = (TARGET_64BIT ? 8 : 4); | |
87ad11b0 | 2703 | |
42819d4e | 2704 | /* Note that we know each loop below will execute at least twice |
2705 | (else we would have open-coded the copy). */ | |
2706 | switch (align) | |
87ad11b0 | 2707 | { |
a7e1bb24 | 2708 | case 8: |
2709 | /* Pre-adjust the loop counter. */ | |
2710 | operands[4] = GEN_INT (n_bytes - 16); | |
2711 | output_asm_insn ("ldi %4,%2", operands); | |
2712 | ||
2713 | /* Copying loop. */ | |
2714 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2715 | output_asm_insn ("ldd,ma 8(%1),%6", operands); | |
2716 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2717 | output_asm_insn ("addib,>= -16,%2,.-12", operands); | |
2718 | output_asm_insn ("std,ma %6,8(%0)", operands); | |
2719 | ||
2720 | /* Handle the residual. There could be up to 7 bytes of | |
2721 | residual to copy! */ | |
2722 | if (n_bytes % 16 != 0) | |
2723 | { | |
2724 | operands[4] = GEN_INT (n_bytes % 8); | |
2725 | if (n_bytes % 16 >= 8) | |
2726 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2727 | if (n_bytes % 8 != 0) | |
2728 | output_asm_insn ("ldd 0(%1),%6", operands); | |
2729 | if (n_bytes % 16 >= 8) | |
2730 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2731 | if (n_bytes % 8 != 0) | |
2732 | output_asm_insn ("stdby,e %6,%4(%0)", operands); | |
2733 | } | |
2734 | return ""; | |
2735 | ||
42819d4e | 2736 | case 4: |
2737 | /* Pre-adjust the loop counter. */ | |
2738 | operands[4] = GEN_INT (n_bytes - 8); | |
2739 | output_asm_insn ("ldi %4,%2", operands); | |
2740 | ||
2741 | /* Copying loop. */ | |
e4065f95 | 2742 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
2743 | output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands); | |
2744 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); | |
42819d4e | 2745 | output_asm_insn ("addib,>= -8,%2,.-12", operands); |
e4065f95 | 2746 | output_asm_insn ("{stws|stw},ma %6,4(%0)", operands); |
42819d4e | 2747 | |
2748 | /* Handle the residual. There could be up to 7 bytes of | |
2749 | residual to copy! */ | |
2750 | if (n_bytes % 8 != 0) | |
2751 | { | |
2752 | operands[4] = GEN_INT (n_bytes % 4); | |
2753 | if (n_bytes % 8 >= 4) | |
e4065f95 | 2754 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
42819d4e | 2755 | if (n_bytes % 4 != 0) |
34940871 | 2756 | output_asm_insn ("ldw 0(%1),%6", operands); |
42819d4e | 2757 | if (n_bytes % 8 >= 4) |
e4065f95 | 2758 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); |
42819d4e | 2759 | if (n_bytes % 4 != 0) |
e4065f95 | 2760 | output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands); |
42819d4e | 2761 | } |
2762 | return ""; | |
87ad11b0 | 2763 | |
42819d4e | 2764 | case 2: |
2765 | /* Pre-adjust the loop counter. */ | |
2766 | operands[4] = GEN_INT (n_bytes - 4); | |
2767 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2768 | |
42819d4e | 2769 | /* Copying loop. */ |
e4065f95 | 2770 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
2771 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands); | |
2772 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); | |
42819d4e | 2773 | output_asm_insn ("addib,>= -4,%2,.-12", operands); |
e4065f95 | 2774 | output_asm_insn ("{sths|sth},ma %6,2(%0)", operands); |
87ad11b0 | 2775 | |
42819d4e | 2776 | /* Handle the residual. */ |
2777 | if (n_bytes % 4 != 0) | |
2778 | { | |
2779 | if (n_bytes % 4 >= 2) | |
e4065f95 | 2780 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
42819d4e | 2781 | if (n_bytes % 2 != 0) |
34940871 | 2782 | output_asm_insn ("ldb 0(%1),%6", operands); |
42819d4e | 2783 | if (n_bytes % 4 >= 2) |
e4065f95 | 2784 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); |
42819d4e | 2785 | if (n_bytes % 2 != 0) |
34940871 | 2786 | output_asm_insn ("stb %6,0(%0)", operands); |
42819d4e | 2787 | } |
2788 | return ""; | |
87ad11b0 | 2789 | |
42819d4e | 2790 | case 1: |
2791 | /* Pre-adjust the loop counter. */ | |
2792 | operands[4] = GEN_INT (n_bytes - 2); | |
2793 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2794 | |
42819d4e | 2795 | /* Copying loop. */ |
e4065f95 | 2796 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands); |
2797 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands); | |
2798 | output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands); | |
42819d4e | 2799 | output_asm_insn ("addib,>= -2,%2,.-12", operands); |
e4065f95 | 2800 | output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands); |
87ad11b0 | 2801 | |
42819d4e | 2802 | /* Handle the residual. */ |
2803 | if (n_bytes % 2 != 0) | |
2804 | { | |
34940871 | 2805 | output_asm_insn ("ldb 0(%1),%3", operands); |
2806 | output_asm_insn ("stb %3,0(%0)", operands); | |
42819d4e | 2807 | } |
2808 | return ""; | |
87ad11b0 | 2809 | |
42819d4e | 2810 | default: |
ecf2283d | 2811 | gcc_unreachable (); |
87ad11b0 | 2812 | } |
87ad11b0 | 2813 | } |
58e17b0b | 2814 | |
2815 | /* Count the number of insns necessary to handle this block move. | |
2816 | ||
2817 | Basic structure is the same as emit_block_move, except that we | |
2818 | count insns rather than emit them. */ | |
2819 | ||
611a88e1 | 2820 | static int |
008c057d | 2821 | compute_movmem_length (rtx insn) |
58e17b0b | 2822 | { |
2823 | rtx pat = PATTERN (insn); | |
fc1fb057 | 2824 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0)); |
2825 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0)); | |
42819d4e | 2826 | unsigned int n_insns = 0; |
58e17b0b | 2827 | |
2828 | /* We can't move more than four bytes at a time because the PA | |
2829 | has no longer integer move insns. (Could use fp mem ops?) */ | |
a7e1bb24 | 2830 | if (align > (TARGET_64BIT ? 8 : 4)) |
2831 | align = (TARGET_64BIT ? 8 : 4); | |
58e17b0b | 2832 | |
79bfe6ae | 2833 | /* The basic copying loop. */ |
42819d4e | 2834 | n_insns = 6; |
58e17b0b | 2835 | |
42819d4e | 2836 | /* Residuals. */ |
2837 | if (n_bytes % (2 * align) != 0) | |
58e17b0b | 2838 | { |
79bfe6ae | 2839 | if ((n_bytes % (2 * align)) >= align) |
2840 | n_insns += 2; | |
2841 | ||
2842 | if ((n_bytes % align) != 0) | |
2843 | n_insns += 2; | |
58e17b0b | 2844 | } |
42819d4e | 2845 | |
2846 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2847 | return n_insns * 4; | |
58e17b0b | 2848 | } |
a7e1bb24 | 2849 | |
2850 | /* Emit code to perform a block clear. | |
2851 | ||
2852 | OPERANDS[0] is the destination pointer as a REG, clobbered. | |
2853 | OPERANDS[1] is a register for temporary storage. | |
2854 | OPERANDS[2] is the size as a CONST_INT | |
2855 | OPERANDS[3] is the alignment safe to use, as a CONST_INT. */ | |
2856 | ||
2857 | const char * | |
2858 | output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) | |
2859 | { | |
2860 | int align = INTVAL (operands[3]); | |
2861 | unsigned long n_bytes = INTVAL (operands[2]); | |
2862 | ||
2863 | /* We can't clear more than a word at a time because the PA | |
2864 | has no longer integer move insns. */ | |
2865 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2866 | align = (TARGET_64BIT ? 8 : 4); | |
2867 | ||
2868 | /* Note that we know each loop below will execute at least twice | |
2869 | (else we would have open-coded the copy). */ | |
2870 | switch (align) | |
2871 | { | |
2872 | case 8: | |
2873 | /* Pre-adjust the loop counter. */ | |
2874 | operands[2] = GEN_INT (n_bytes - 16); | |
2875 | output_asm_insn ("ldi %2,%1", operands); | |
2876 | ||
2877 | /* Loop. */ | |
2878 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2879 | output_asm_insn ("addib,>= -16,%1,.-4", operands); | |
2880 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2881 | ||
2882 | /* Handle the residual. There could be up to 7 bytes of | |
2883 | residual to copy! */ | |
2884 | if (n_bytes % 16 != 0) | |
2885 | { | |
2886 | operands[2] = GEN_INT (n_bytes % 8); | |
2887 | if (n_bytes % 16 >= 8) | |
2888 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2889 | if (n_bytes % 8 != 0) | |
2890 | output_asm_insn ("stdby,e %%r0,%2(%0)", operands); | |
2891 | } | |
2892 | return ""; | |
2893 | ||
2894 | case 4: | |
2895 | /* Pre-adjust the loop counter. */ | |
2896 | operands[2] = GEN_INT (n_bytes - 8); | |
2897 | output_asm_insn ("ldi %2,%1", operands); | |
2898 | ||
2899 | /* Loop. */ | |
2900 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2901 | output_asm_insn ("addib,>= -8,%1,.-4", operands); | |
2902 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2903 | ||
2904 | /* Handle the residual. There could be up to 7 bytes of | |
2905 | residual to copy! */ | |
2906 | if (n_bytes % 8 != 0) | |
2907 | { | |
2908 | operands[2] = GEN_INT (n_bytes % 4); | |
2909 | if (n_bytes % 8 >= 4) | |
2910 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2911 | if (n_bytes % 4 != 0) | |
2912 | output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands); | |
2913 | } | |
2914 | return ""; | |
2915 | ||
2916 | case 2: | |
2917 | /* Pre-adjust the loop counter. */ | |
2918 | operands[2] = GEN_INT (n_bytes - 4); | |
2919 | output_asm_insn ("ldi %2,%1", operands); | |
2920 | ||
2921 | /* Loop. */ | |
2922 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2923 | output_asm_insn ("addib,>= -4,%1,.-4", operands); | |
2924 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2925 | ||
2926 | /* Handle the residual. */ | |
2927 | if (n_bytes % 4 != 0) | |
2928 | { | |
2929 | if (n_bytes % 4 >= 2) | |
2930 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2931 | if (n_bytes % 2 != 0) | |
2932 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2933 | } | |
2934 | return ""; | |
2935 | ||
2936 | case 1: | |
2937 | /* Pre-adjust the loop counter. */ | |
2938 | operands[2] = GEN_INT (n_bytes - 2); | |
2939 | output_asm_insn ("ldi %2,%1", operands); | |
2940 | ||
2941 | /* Loop. */ | |
2942 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2943 | output_asm_insn ("addib,>= -2,%1,.-4", operands); | |
2944 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2945 | ||
2946 | /* Handle the residual. */ | |
2947 | if (n_bytes % 2 != 0) | |
2948 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2949 | ||
2950 | return ""; | |
2951 | ||
2952 | default: | |
ecf2283d | 2953 | gcc_unreachable (); |
a7e1bb24 | 2954 | } |
2955 | } | |
2956 | ||
2957 | /* Count the number of insns necessary to handle this block move. | |
2958 | ||
2959 | Basic structure is the same as emit_block_move, except that we | |
2960 | count insns rather than emit them. */ | |
2961 | ||
2962 | static int | |
008c057d | 2963 | compute_clrmem_length (rtx insn) |
a7e1bb24 | 2964 | { |
2965 | rtx pat = PATTERN (insn); | |
2966 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0)); | |
2967 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0)); | |
2968 | unsigned int n_insns = 0; | |
2969 | ||
2970 | /* We can't clear more than a word at a time because the PA | |
2971 | has no longer integer move insns. */ | |
2972 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2973 | align = (TARGET_64BIT ? 8 : 4); | |
2974 | ||
2975 | /* The basic loop. */ | |
2976 | n_insns = 4; | |
2977 | ||
2978 | /* Residuals. */ | |
2979 | if (n_bytes % (2 * align) != 0) | |
2980 | { | |
2981 | if ((n_bytes % (2 * align)) >= align) | |
2982 | n_insns++; | |
2983 | ||
2984 | if ((n_bytes % align) != 0) | |
2985 | n_insns++; | |
2986 | } | |
2987 | ||
2988 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2989 | return n_insns * 4; | |
2990 | } | |
87ad11b0 | 2991 | \f |
2992 | ||
611a88e1 | 2993 | const char * |
5c1d8983 | 2994 | output_and (rtx *operands) |
e057641f | 2995 | { |
d6f01525 | 2996 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) |
e057641f | 2997 | { |
3745c59b | 2998 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
e057641f | 2999 | int ls0, ls1, ms0, p, len; |
3000 | ||
3001 | for (ls0 = 0; ls0 < 32; ls0++) | |
3002 | if ((mask & (1 << ls0)) == 0) | |
3003 | break; | |
3004 | ||
3005 | for (ls1 = ls0; ls1 < 32; ls1++) | |
3006 | if ((mask & (1 << ls1)) != 0) | |
3007 | break; | |
3008 | ||
3009 | for (ms0 = ls1; ms0 < 32; ms0++) | |
3010 | if ((mask & (1 << ms0)) == 0) | |
3011 | break; | |
3012 | ||
ecf2283d | 3013 | gcc_assert (ms0 == 32); |
e057641f | 3014 | |
3015 | if (ls1 == 32) | |
3016 | { | |
3017 | len = ls0; | |
3018 | ||
ecf2283d | 3019 | gcc_assert (len); |
e057641f | 3020 | |
ef618fe4 | 3021 | operands[2] = GEN_INT (len); |
e4065f95 | 3022 | return "{extru|extrw,u} %1,31,%2,%0"; |
e057641f | 3023 | } |
3024 | else | |
3025 | { | |
3026 | /* We could use this `depi' for the case above as well, but `depi' | |
3027 | requires one more register file access than an `extru'. */ | |
3028 | ||
3029 | p = 31 - ls0; | |
3030 | len = ls1 - ls0; | |
3031 | ||
ef618fe4 | 3032 | operands[2] = GEN_INT (p); |
3033 | operands[3] = GEN_INT (len); | |
e4065f95 | 3034 | return "{depi|depwi} 0,%2,%3,%0"; |
e057641f | 3035 | } |
3036 | } | |
3037 | else | |
3038 | return "and %1,%2,%0"; | |
3039 | } | |
3040 | ||
5e3c5739 | 3041 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] |
3042 | storing the result in operands[0]. */ | |
9aadea62 | 3043 | const char * |
5c1d8983 | 3044 | output_64bit_and (rtx *operands) |
5e3c5739 | 3045 | { |
3046 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) | |
3047 | { | |
3048 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 3049 | int ls0, ls1, ms0, p, len; |
5e3c5739 | 3050 | |
3051 | for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++) | |
b7d86581 | 3052 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0) |
5e3c5739 | 3053 | break; |
3054 | ||
3055 | for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++) | |
b7d86581 | 3056 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0) |
5e3c5739 | 3057 | break; |
3058 | ||
3059 | for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++) | |
b7d86581 | 3060 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0) |
5e3c5739 | 3061 | break; |
3062 | ||
ecf2283d | 3063 | gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT); |
5e3c5739 | 3064 | |
3065 | if (ls1 == HOST_BITS_PER_WIDE_INT) | |
3066 | { | |
3067 | len = ls0; | |
3068 | ||
ecf2283d | 3069 | gcc_assert (len); |
5e3c5739 | 3070 | |
3071 | operands[2] = GEN_INT (len); | |
3072 | return "extrd,u %1,63,%2,%0"; | |
3073 | } | |
3074 | else | |
3075 | { | |
3076 | /* We could use this `depi' for the case above as well, but `depi' | |
3077 | requires one more register file access than an `extru'. */ | |
3078 | ||
3079 | p = 63 - ls0; | |
3080 | len = ls1 - ls0; | |
3081 | ||
3082 | operands[2] = GEN_INT (p); | |
3083 | operands[3] = GEN_INT (len); | |
3084 | return "depdi 0,%2,%3,%0"; | |
3085 | } | |
3086 | } | |
3087 | else | |
3088 | return "and %1,%2,%0"; | |
3089 | } | |
3090 | ||
611a88e1 | 3091 | const char * |
5c1d8983 | 3092 | output_ior (rtx *operands) |
e057641f | 3093 | { |
3745c59b | 3094 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
57ed30e5 | 3095 | int bs0, bs1, p, len; |
6d36483b | 3096 | |
c9da5f4d | 3097 | if (INTVAL (operands[2]) == 0) |
3098 | return "copy %1,%0"; | |
e057641f | 3099 | |
c9da5f4d | 3100 | for (bs0 = 0; bs0 < 32; bs0++) |
3101 | if ((mask & (1 << bs0)) != 0) | |
3102 | break; | |
e057641f | 3103 | |
c9da5f4d | 3104 | for (bs1 = bs0; bs1 < 32; bs1++) |
3105 | if ((mask & (1 << bs1)) == 0) | |
3106 | break; | |
e057641f | 3107 | |
ecf2283d | 3108 | gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); |
e057641f | 3109 | |
c9da5f4d | 3110 | p = 31 - bs0; |
3111 | len = bs1 - bs0; | |
e057641f | 3112 | |
ef618fe4 | 3113 | operands[2] = GEN_INT (p); |
3114 | operands[3] = GEN_INT (len); | |
e4065f95 | 3115 | return "{depi|depwi} -1,%2,%3,%0"; |
e057641f | 3116 | } |
5e3c5739 | 3117 | |
3118 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] | |
3119 | storing the result in operands[0]. */ | |
9aadea62 | 3120 | const char * |
5c1d8983 | 3121 | output_64bit_ior (rtx *operands) |
5e3c5739 | 3122 | { |
3123 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 3124 | int bs0, bs1, p, len; |
5e3c5739 | 3125 | |
3126 | if (INTVAL (operands[2]) == 0) | |
3127 | return "copy %1,%0"; | |
3128 | ||
3129 | for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++) | |
b7d86581 | 3130 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0) |
5e3c5739 | 3131 | break; |
3132 | ||
3133 | for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++) | |
b7d86581 | 3134 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0) |
5e3c5739 | 3135 | break; |
3136 | ||
ecf2283d | 3137 | gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT |
3138 | || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); | |
5e3c5739 | 3139 | |
3140 | p = 63 - bs0; | |
3141 | len = bs1 - bs0; | |
3142 | ||
3143 | operands[2] = GEN_INT (p); | |
3144 | operands[3] = GEN_INT (len); | |
3145 | return "depdi -1,%2,%3,%0"; | |
3146 | } | |
e057641f | 3147 | \f |
58356836 | 3148 | /* Target hook for assembling integer objects. This code handles |
e678758c | 3149 | aligned SI and DI integers specially since function references |
3150 | must be preceded by P%. */ | |
58356836 | 3151 | |
3152 | static bool | |
5c1d8983 | 3153 | pa_assemble_integer (rtx x, unsigned int size, int aligned_p) |
58356836 | 3154 | { |
e678758c | 3155 | if (size == UNITS_PER_WORD |
3156 | && aligned_p | |
58356836 | 3157 | && function_label_operand (x, VOIDmode)) |
3158 | { | |
3159 | fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file); | |
3160 | output_addr_const (asm_out_file, x); | |
3161 | fputc ('\n', asm_out_file); | |
3162 | return true; | |
3163 | } | |
3164 | return default_assemble_integer (x, size, aligned_p); | |
3165 | } | |
3166 | \f | |
87ad11b0 | 3167 | /* Output an ascii string. */ |
57ed30e5 | 3168 | void |
5c1d8983 | 3169 | output_ascii (FILE *file, const char *p, int size) |
87ad11b0 | 3170 | { |
3171 | int i; | |
3172 | int chars_output; | |
5aedf60c | 3173 | unsigned char partial_output[16]; /* Max space 4 chars can occupy. */ |
87ad11b0 | 3174 | |
3175 | /* The HP assembler can only take strings of 256 characters at one | |
3176 | time. This is a limitation on input line length, *not* the | |
3177 | length of the string. Sigh. Even worse, it seems that the | |
3178 | restriction is in number of input characters (see \xnn & | |
3179 | \whatever). So we have to do this very carefully. */ | |
3180 | ||
9c0ac0fd | 3181 | fputs ("\t.STRING \"", file); |
87ad11b0 | 3182 | |
3183 | chars_output = 0; | |
3184 | for (i = 0; i < size; i += 4) | |
3185 | { | |
3186 | int co = 0; | |
3187 | int io = 0; | |
3188 | for (io = 0, co = 0; io < MIN (4, size - i); io++) | |
3189 | { | |
bf8aac3e | 3190 | register unsigned int c = (unsigned char) p[i + io]; |
87ad11b0 | 3191 | |
3192 | if (c == '\"' || c == '\\') | |
3193 | partial_output[co++] = '\\'; | |
3194 | if (c >= ' ' && c < 0177) | |
3195 | partial_output[co++] = c; | |
3196 | else | |
3197 | { | |
3198 | unsigned int hexd; | |
3199 | partial_output[co++] = '\\'; | |
3200 | partial_output[co++] = 'x'; | |
3201 | hexd = c / 16 - 0 + '0'; | |
3202 | if (hexd > '9') | |
3203 | hexd -= '9' - 'a' + 1; | |
3204 | partial_output[co++] = hexd; | |
3205 | hexd = c % 16 - 0 + '0'; | |
3206 | if (hexd > '9') | |
3207 | hexd -= '9' - 'a' + 1; | |
3208 | partial_output[co++] = hexd; | |
3209 | } | |
3210 | } | |
3211 | if (chars_output + co > 243) | |
3212 | { | |
9c0ac0fd | 3213 | fputs ("\"\n\t.STRING \"", file); |
87ad11b0 | 3214 | chars_output = 0; |
3215 | } | |
a584fe8a | 3216 | fwrite (partial_output, 1, (size_t) co, file); |
87ad11b0 | 3217 | chars_output += co; |
3218 | co = 0; | |
3219 | } | |
9c0ac0fd | 3220 | fputs ("\"\n", file); |
87ad11b0 | 3221 | } |
c533da59 | 3222 | |
3223 | /* Try to rewrite floating point comparisons & branches to avoid | |
3224 | useless add,tr insns. | |
3225 | ||
3226 | CHECK_NOTES is nonzero if we should examine REG_DEAD notes | |
3227 | to see if FPCC is dead. CHECK_NOTES is nonzero for the | |
3228 | first attempt to remove useless add,tr insns. It is zero | |
3229 | for the second pass as reorg sometimes leaves bogus REG_DEAD | |
3230 | notes lying around. | |
3231 | ||
3232 | When CHECK_NOTES is zero we can only eliminate add,tr insns | |
3233 | when there's a 1:1 correspondence between fcmp and ftest/fbranch | |
3234 | instructions. */ | |
611a88e1 | 3235 | static void |
5c1d8983 | 3236 | remove_useless_addtr_insns (int check_notes) |
c533da59 | 3237 | { |
3238 | rtx insn; | |
c533da59 | 3239 | static int pass = 0; |
3240 | ||
3241 | /* This is fairly cheap, so always run it when optimizing. */ | |
3242 | if (optimize > 0) | |
3243 | { | |
3244 | int fcmp_count = 0; | |
3245 | int fbranch_count = 0; | |
3246 | ||
3247 | /* Walk all the insns in this function looking for fcmp & fbranch | |
3248 | instructions. Keep track of how many of each we find. */ | |
2efea8c0 | 3249 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3250 | { |
3251 | rtx tmp; | |
3252 | ||
3253 | /* Ignore anything that isn't an INSN or a JUMP_INSN. */ | |
3254 | if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
3255 | continue; | |
3256 | ||
3257 | tmp = PATTERN (insn); | |
3258 | ||
3259 | /* It must be a set. */ | |
3260 | if (GET_CODE (tmp) != SET) | |
3261 | continue; | |
3262 | ||
3263 | /* If the destination is CCFP, then we've found an fcmp insn. */ | |
3264 | tmp = SET_DEST (tmp); | |
3265 | if (GET_CODE (tmp) == REG && REGNO (tmp) == 0) | |
3266 | { | |
3267 | fcmp_count++; | |
3268 | continue; | |
3269 | } | |
9840d99d | 3270 | |
c533da59 | 3271 | tmp = PATTERN (insn); |
3272 | /* If this is an fbranch instruction, bump the fbranch counter. */ | |
3273 | if (GET_CODE (tmp) == SET | |
3274 | && SET_DEST (tmp) == pc_rtx | |
3275 | && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE | |
3276 | && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE | |
3277 | && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG | |
3278 | && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0) | |
3279 | { | |
3280 | fbranch_count++; | |
3281 | continue; | |
3282 | } | |
3283 | } | |
3284 | ||
3285 | ||
3286 | /* Find all floating point compare + branch insns. If possible, | |
3287 | reverse the comparison & the branch to avoid add,tr insns. */ | |
2efea8c0 | 3288 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3289 | { |
3290 | rtx tmp, next; | |
3291 | ||
3292 | /* Ignore anything that isn't an INSN. */ | |
3293 | if (GET_CODE (insn) != INSN) | |
3294 | continue; | |
3295 | ||
3296 | tmp = PATTERN (insn); | |
3297 | ||
3298 | /* It must be a set. */ | |
3299 | if (GET_CODE (tmp) != SET) | |
3300 | continue; | |
3301 | ||
3302 | /* The destination must be CCFP, which is register zero. */ | |
3303 | tmp = SET_DEST (tmp); | |
3304 | if (GET_CODE (tmp) != REG || REGNO (tmp) != 0) | |
3305 | continue; | |
3306 | ||
3307 | /* INSN should be a set of CCFP. | |
3308 | ||
3309 | See if the result of this insn is used in a reversed FP | |
3310 | conditional branch. If so, reverse our condition and | |
3311 | the branch. Doing so avoids useless add,tr insns. */ | |
3312 | next = next_insn (insn); | |
3313 | while (next) | |
3314 | { | |
3315 | /* Jumps, calls and labels stop our search. */ | |
3316 | if (GET_CODE (next) == JUMP_INSN | |
3317 | || GET_CODE (next) == CALL_INSN | |
3318 | || GET_CODE (next) == CODE_LABEL) | |
3319 | break; | |
3320 | ||
3321 | /* As does another fcmp insn. */ | |
3322 | if (GET_CODE (next) == INSN | |
3323 | && GET_CODE (PATTERN (next)) == SET | |
3324 | && GET_CODE (SET_DEST (PATTERN (next))) == REG | |
3325 | && REGNO (SET_DEST (PATTERN (next))) == 0) | |
3326 | break; | |
3327 | ||
3328 | next = next_insn (next); | |
3329 | } | |
3330 | ||
3331 | /* Is NEXT_INSN a branch? */ | |
3332 | if (next | |
3333 | && GET_CODE (next) == JUMP_INSN) | |
3334 | { | |
3335 | rtx pattern = PATTERN (next); | |
3336 | ||
a361b456 | 3337 | /* If it a reversed fp conditional branch (e.g. uses add,tr) |
c533da59 | 3338 | and CCFP dies, then reverse our conditional and the branch |
3339 | to avoid the add,tr. */ | |
3340 | if (GET_CODE (pattern) == SET | |
3341 | && SET_DEST (pattern) == pc_rtx | |
3342 | && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE | |
3343 | && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE | |
3344 | && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG | |
3345 | && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0 | |
3346 | && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC | |
3347 | && (fcmp_count == fbranch_count | |
3348 | || (check_notes | |
3349 | && find_regno_note (next, REG_DEAD, 0)))) | |
3350 | { | |
3351 | /* Reverse the branch. */ | |
3352 | tmp = XEXP (SET_SRC (pattern), 1); | |
3353 | XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2); | |
3354 | XEXP (SET_SRC (pattern), 2) = tmp; | |
3355 | INSN_CODE (next) = -1; | |
3356 | ||
3357 | /* Reverse our condition. */ | |
3358 | tmp = PATTERN (insn); | |
3359 | PUT_CODE (XEXP (tmp, 1), | |
ea52c577 | 3360 | (reverse_condition_maybe_unordered |
3361 | (GET_CODE (XEXP (tmp, 1))))); | |
c533da59 | 3362 | } |
3363 | } | |
3364 | } | |
3365 | } | |
3366 | ||
3367 | pass = !pass; | |
3368 | ||
3369 | } | |
87ad11b0 | 3370 | \f |
ea52c577 | 3371 | /* You may have trouble believing this, but this is the 32 bit HP-PA |
3372 | stack layout. Wow. | |
87ad11b0 | 3373 | |
3374 | Offset Contents | |
3375 | ||
3376 | Variable arguments (optional; any number may be allocated) | |
3377 | ||
3378 | SP-(4*(N+9)) arg word N | |
3379 | : : | |
3380 | SP-56 arg word 5 | |
3381 | SP-52 arg word 4 | |
3382 | ||
3383 | Fixed arguments (must be allocated; may remain unused) | |
3384 | ||
3385 | SP-48 arg word 3 | |
3386 | SP-44 arg word 2 | |
3387 | SP-40 arg word 1 | |
3388 | SP-36 arg word 0 | |
3389 | ||
3390 | Frame Marker | |
3391 | ||
3392 | SP-32 External Data Pointer (DP) | |
3393 | SP-28 External sr4 | |
3394 | SP-24 External/stub RP (RP') | |
3395 | SP-20 Current RP | |
3396 | SP-16 Static Link | |
3397 | SP-12 Clean up | |
3398 | SP-8 Calling Stub RP (RP'') | |
3399 | SP-4 Previous SP | |
3400 | ||
3401 | Top of Frame | |
3402 | ||
3403 | SP-0 Stack Pointer (points to next available address) | |
3404 | ||
3405 | */ | |
3406 | ||
3407 | /* This function saves registers as follows. Registers marked with ' are | |
3408 | this function's registers (as opposed to the previous function's). | |
3409 | If a frame_pointer isn't needed, r4 is saved as a general register; | |
3410 | the space for the frame pointer is still allocated, though, to keep | |
3411 | things simple. | |
3412 | ||
3413 | ||
3414 | Top of Frame | |
3415 | ||
3416 | SP (FP') Previous FP | |
3417 | SP + 4 Alignment filler (sigh) | |
3418 | SP + 8 Space for locals reserved here. | |
3419 | . | |
3420 | . | |
3421 | . | |
3422 | SP + n All call saved register used. | |
3423 | . | |
3424 | . | |
3425 | . | |
3426 | SP + o All call saved fp registers used. | |
3427 | . | |
3428 | . | |
3429 | . | |
3430 | SP + p (SP') points to next available address. | |
6d36483b | 3431 | |
87ad11b0 | 3432 | */ |
3433 | ||
17d9b0c3 | 3434 | /* Global variables set by output_function_prologue(). */ |
cc858176 | 3435 | /* Size of frame. Need to know this to emit return insns from |
3436 | leaf procedures. */ | |
6bcdc1fb | 3437 | static HOST_WIDE_INT actual_fsize, local_fsize; |
3438 | static int save_fregs; | |
cc858176 | 3439 | |
daee63dd | 3440 | /* Emit RTL to store REG at the memory location specified by BASE+DISP. |
359a0be8 | 3441 | Handle case where DISP > 8k by using the add_high_const patterns. |
daee63dd | 3442 | |
3443 | Note in DISP > 8k case, we will leave the high part of the address | |
3444 | in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/ | |
7014838c | 3445 | |
6a2c16d6 | 3446 | static void |
6bcdc1fb | 3447 | store_reg (int reg, HOST_WIDE_INT disp, int base) |
87ad11b0 | 3448 | { |
6a2c16d6 | 3449 | rtx insn, dest, src, basereg; |
cc858176 | 3450 | |
3451 | src = gen_rtx_REG (word_mode, reg); | |
3452 | basereg = gen_rtx_REG (Pmode, base); | |
87ad11b0 | 3453 | if (VAL_14_BITS_P (disp)) |
daee63dd | 3454 | { |
cc858176 | 3455 | dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
6a2c16d6 | 3456 | insn = emit_move_insn (dest, src); |
daee63dd | 3457 | } |
6bcdc1fb | 3458 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3459 | { | |
3460 | rtx delta = GEN_INT (disp); | |
3461 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3462 | ||
3463 | emit_move_insn (tmpreg, delta); | |
5ecfd087 | 3464 | insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); |
6bcdc1fb | 3465 | if (DO_FRAME_NOTES) |
3466 | { | |
b9c74b4d | 3467 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3468 | gen_rtx_SET (VOIDmode, tmpreg, | |
3469 | gen_rtx_PLUS (Pmode, basereg, delta))); | |
5ecfd087 | 3470 | RTX_FRAME_RELATED_P (insn) = 1; |
6bcdc1fb | 3471 | } |
5ecfd087 | 3472 | dest = gen_rtx_MEM (word_mode, tmpreg); |
3473 | insn = emit_move_insn (dest, src); | |
6bcdc1fb | 3474 | } |
daee63dd | 3475 | else |
3476 | { | |
cc858176 | 3477 | rtx delta = GEN_INT (disp); |
3478 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3479 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 3480 | |
cc858176 | 3481 | emit_move_insn (tmpreg, high); |
3482 | dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
6a2c16d6 | 3483 | insn = emit_move_insn (dest, src); |
3484 | if (DO_FRAME_NOTES) | |
b9c74b4d | 3485 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3486 | gen_rtx_SET (VOIDmode, | |
3487 | gen_rtx_MEM (word_mode, | |
3488 | gen_rtx_PLUS (word_mode, | |
3489 | basereg, | |
3490 | delta)), | |
3491 | src)); | |
daee63dd | 3492 | } |
6a2c16d6 | 3493 | |
3494 | if (DO_FRAME_NOTES) | |
3495 | RTX_FRAME_RELATED_P (insn) = 1; | |
daee63dd | 3496 | } |
3497 | ||
a584fe8a | 3498 | /* Emit RTL to store REG at the memory location specified by BASE and then |
3499 | add MOD to BASE. MOD must be <= 8k. */ | |
daee63dd | 3500 | |
a584fe8a | 3501 | static void |
6bcdc1fb | 3502 | store_reg_modify (int base, int reg, HOST_WIDE_INT mod) |
a584fe8a | 3503 | { |
3504 | rtx insn, basereg, srcreg, delta; | |
3505 | ||
ecf2283d | 3506 | gcc_assert (VAL_14_BITS_P (mod)); |
a584fe8a | 3507 | |
3508 | basereg = gen_rtx_REG (Pmode, base); | |
3509 | srcreg = gen_rtx_REG (word_mode, reg); | |
3510 | delta = GEN_INT (mod); | |
3511 | ||
3512 | insn = emit_insn (gen_post_store (basereg, srcreg, delta)); | |
3513 | if (DO_FRAME_NOTES) | |
3514 | { | |
3515 | RTX_FRAME_RELATED_P (insn) = 1; | |
3516 | ||
3517 | /* RTX_FRAME_RELATED_P must be set on each frame related set | |
dc873350 | 3518 | in a parallel with more than one element. */ |
3519 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1; | |
3520 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; | |
a584fe8a | 3521 | } |
3522 | } | |
3523 | ||
3524 | /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case | |
3525 | where DISP > 8k by using the add_high_const patterns. NOTE indicates | |
3526 | whether to add a frame note or not. | |
3527 | ||
3528 | In the DISP > 8k case, we leave the high part of the address in %r1. | |
3529 | There is code in expand_hppa_{prologue,epilogue} that knows about this. */ | |
7014838c | 3530 | |
6a2c16d6 | 3531 | static void |
6bcdc1fb | 3532 | set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note) |
87ad11b0 | 3533 | { |
6a2c16d6 | 3534 | rtx insn; |
cc858176 | 3535 | |
87ad11b0 | 3536 | if (VAL_14_BITS_P (disp)) |
cc858176 | 3537 | { |
6a2c16d6 | 3538 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
3539 | plus_constant (gen_rtx_REG (Pmode, base), disp)); | |
cc858176 | 3540 | } |
6bcdc1fb | 3541 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3542 | { | |
3543 | rtx basereg = gen_rtx_REG (Pmode, base); | |
3544 | rtx delta = GEN_INT (disp); | |
3545 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3546 | ||
3547 | emit_move_insn (tmpreg, delta); | |
3548 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), | |
3549 | gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
5ecfd087 | 3550 | if (DO_FRAME_NOTES) |
b9c74b4d | 3551 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3552 | gen_rtx_SET (VOIDmode, tmpreg, | |
3553 | gen_rtx_PLUS (Pmode, basereg, delta))); | |
6bcdc1fb | 3554 | } |
87ad11b0 | 3555 | else |
daee63dd | 3556 | { |
6a2c16d6 | 3557 | rtx basereg = gen_rtx_REG (Pmode, base); |
cc858176 | 3558 | rtx delta = GEN_INT (disp); |
6bcdc1fb | 3559 | rtx tmpreg = gen_rtx_REG (Pmode, 1); |
6a2c16d6 | 3560 | |
6bcdc1fb | 3561 | emit_move_insn (tmpreg, |
6a2c16d6 | 3562 | gen_rtx_PLUS (Pmode, basereg, |
cc858176 | 3563 | gen_rtx_HIGH (Pmode, delta))); |
6a2c16d6 | 3564 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
6bcdc1fb | 3565 | gen_rtx_LO_SUM (Pmode, tmpreg, delta)); |
daee63dd | 3566 | } |
6a2c16d6 | 3567 | |
a584fe8a | 3568 | if (DO_FRAME_NOTES && note) |
6a2c16d6 | 3569 | RTX_FRAME_RELATED_P (insn) = 1; |
87ad11b0 | 3570 | } |
3571 | ||
6bcdc1fb | 3572 | HOST_WIDE_INT |
3573 | compute_frame_size (HOST_WIDE_INT size, int *fregs_live) | |
87ad11b0 | 3574 | { |
256f9b65 | 3575 | int freg_saved = 0; |
3576 | int i, j; | |
3577 | ||
3578 | /* The code in hppa_expand_prologue and hppa_expand_epilogue must | |
3579 | be consistent with the rounding and size calculation done here. | |
3580 | Change them at the same time. */ | |
3581 | ||
3582 | /* We do our own stack alignment. First, round the size of the | |
3583 | stack locals up to a word boundary. */ | |
3584 | size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3585 | ||
3586 | /* Space for previous frame pointer + filler. If any frame is | |
3587 | allocated, we need to add in the STARTING_FRAME_OFFSET. We | |
3588 | waste some space here for the sake of HP compatibility. The | |
3589 | first slot is only used when the frame pointer is needed. */ | |
3590 | if (size || frame_pointer_needed) | |
3591 | size += STARTING_FRAME_OFFSET; | |
3592 | ||
a584fe8a | 3593 | /* If the current function calls __builtin_eh_return, then we need |
3594 | to allocate stack space for registers that will hold data for | |
3595 | the exception handler. */ | |
18d50ae6 | 3596 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 3597 | { |
3598 | unsigned int i; | |
3599 | ||
3600 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
3601 | continue; | |
256f9b65 | 3602 | size += i * UNITS_PER_WORD; |
a584fe8a | 3603 | } |
3604 | ||
3a51bad9 | 3605 | /* Account for space used by the callee general register saves. */ |
256f9b65 | 3606 | for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--) |
3072d30e | 3607 | if (df_regs_ever_live_p (i)) |
256f9b65 | 3608 | size += UNITS_PER_WORD; |
df0651dc | 3609 | |
3a51bad9 | 3610 | /* Account for space used by the callee floating point register saves. */ |
bac38c40 | 3611 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
3072d30e | 3612 | if (df_regs_ever_live_p (i) |
3613 | || (!TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
df0651dc | 3614 | { |
256f9b65 | 3615 | freg_saved = 1; |
002fc5f7 | 3616 | |
3a51bad9 | 3617 | /* We always save both halves of the FP register, so always |
3618 | increment the frame size by 8 bytes. */ | |
256f9b65 | 3619 | size += 8; |
df0651dc | 3620 | } |
3621 | ||
256f9b65 | 3622 | /* If any of the floating registers are saved, account for the |
3623 | alignment needed for the floating point register save block. */ | |
3624 | if (freg_saved) | |
3625 | { | |
3626 | size = (size + 7) & ~7; | |
3627 | if (fregs_live) | |
3628 | *fregs_live = 1; | |
3629 | } | |
3630 | ||
3a51bad9 | 3631 | /* The various ABIs include space for the outgoing parameters in the |
256f9b65 | 3632 | size of the current function's stack frame. We don't need to align |
3633 | for the outgoing arguments as their alignment is set by the final | |
3634 | rounding for the frame as a whole. */ | |
abe32cce | 3635 | size += crtl->outgoing_args_size; |
3a51bad9 | 3636 | |
3637 | /* Allocate space for the fixed frame marker. This space must be | |
e9ec370e | 3638 | allocated for any function that makes calls or allocates |
3a51bad9 | 3639 | stack space. */ |
256f9b65 | 3640 | if (!current_function_is_leaf || size) |
e9ec370e | 3641 | size += TARGET_64BIT ? 48 : 32; |
5e3c5739 | 3642 | |
256f9b65 | 3643 | /* Finally, round to the preferred stack boundary. */ |
2247cc5f | 3644 | return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1) |
3645 | & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
87ad11b0 | 3646 | } |
6d36483b | 3647 | |
17d9b0c3 | 3648 | /* Generate the assembly code for function entry. FILE is a stdio |
3649 | stream to output the code to. SIZE is an int: how many units of | |
3650 | temporary storage to allocate. | |
3651 | ||
3652 | Refer to the array `regs_ever_live' to determine which registers to | |
3653 | save; `regs_ever_live[I]' is nonzero if register number I is ever | |
3654 | used in the function. This function is responsible for knowing | |
3655 | which registers should not be saved even if used. */ | |
3656 | ||
3657 | /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block | |
3658 | of memory. If any fpu reg is used in the function, we allocate | |
3659 | such a block here, at the bottom of the frame, just in case it's needed. | |
3660 | ||
3661 | If this function is a leaf procedure, then we may choose not | |
3662 | to do a "save" insn. The decision about whether or not | |
3663 | to do this is made in regclass.c. */ | |
3664 | ||
6988553d | 3665 | static void |
5c1d8983 | 3666 | pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 3667 | { |
d151162a | 3668 | /* The function's label and associated .PROC must never be |
3669 | separated and must be output *after* any profiling declarations | |
3670 | to avoid changing spaces/subspaces within a procedure. */ | |
3671 | ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3672 | fputs ("\t.PROC\n", file); | |
3673 | ||
daee63dd | 3674 | /* hppa_expand_prologue does the dirty work now. We just need |
3675 | to output the assembler directives which denote the start | |
3676 | of a function. */ | |
6bcdc1fb | 3677 | fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize); |
df6b92e4 | 3678 | if (current_function_is_leaf) |
9c0ac0fd | 3679 | fputs (",NO_CALLS", file); |
df6b92e4 | 3680 | else |
3681 | fputs (",CALLS", file); | |
3682 | if (rp_saved) | |
3683 | fputs (",SAVE_RP", file); | |
f3ba7709 | 3684 | |
e9ec370e | 3685 | /* The SAVE_SP flag is used to indicate that register %r3 is stored |
3686 | at the beginning of the frame and that it is used as the frame | |
3687 | pointer for the frame. We do this because our current frame | |
3ce7ff97 | 3688 | layout doesn't conform to that specified in the HP runtime |
e9ec370e | 3689 | documentation and we need a way to indicate to programs such as |
3690 | GDB where %r3 is saved. The SAVE_SP flag was chosen because it | |
3691 | isn't used by HP compilers but is supported by the assembler. | |
3692 | However, SAVE_SP is supposed to indicate that the previous stack | |
3693 | pointer has been saved in the frame marker. */ | |
f3ba7709 | 3694 | if (frame_pointer_needed) |
9c0ac0fd | 3695 | fputs (",SAVE_SP", file); |
f3ba7709 | 3696 | |
a9960cdc | 3697 | /* Pass on information about the number of callee register saves |
9b0c95be | 3698 | performed in the prologue. |
3699 | ||
3700 | The compiler is supposed to pass the highest register number | |
6d36483b | 3701 | saved, the assembler then has to adjust that number before |
9b0c95be | 3702 | entering it into the unwind descriptor (to account for any |
6d36483b | 3703 | caller saved registers with lower register numbers than the |
9b0c95be | 3704 | first callee saved register). */ |
3705 | if (gr_saved) | |
3706 | fprintf (file, ",ENTRY_GR=%d", gr_saved + 2); | |
3707 | ||
3708 | if (fr_saved) | |
3709 | fprintf (file, ",ENTRY_FR=%d", fr_saved + 11); | |
a9960cdc | 3710 | |
9c0ac0fd | 3711 | fputs ("\n\t.ENTRY\n", file); |
daee63dd | 3712 | |
2efea8c0 | 3713 | remove_useless_addtr_insns (0); |
daee63dd | 3714 | } |
3715 | ||
57ed30e5 | 3716 | void |
5c1d8983 | 3717 | hppa_expand_prologue (void) |
daee63dd | 3718 | { |
afd7b680 | 3719 | int merge_sp_adjust_with_store = 0; |
6bcdc1fb | 3720 | HOST_WIDE_INT size = get_frame_size (); |
3721 | HOST_WIDE_INT offset; | |
3722 | int i; | |
a584fe8a | 3723 | rtx insn, tmpreg; |
daee63dd | 3724 | |
a9960cdc | 3725 | gr_saved = 0; |
3726 | fr_saved = 0; | |
3ddcbb9d | 3727 | save_fregs = 0; |
3a51bad9 | 3728 | |
256f9b65 | 3729 | /* Compute total size for frame pointer, filler, locals and rounding to |
3730 | the next word boundary. Similar code appears in compute_frame_size | |
3731 | and must be changed in tandem with this code. */ | |
3732 | local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3733 | if (local_fsize || frame_pointer_needed) | |
3734 | local_fsize += STARTING_FRAME_OFFSET; | |
3a51bad9 | 3735 | |
a1ab4fa3 | 3736 | actual_fsize = compute_frame_size (size, &save_fregs); |
990495a7 | 3737 | if (flag_stack_usage) |
3738 | current_function_static_stack_size = actual_fsize; | |
87ad11b0 | 3739 | |
daee63dd | 3740 | /* Compute a few things we will use often. */ |
440c23df | 3741 | tmpreg = gen_rtx_REG (word_mode, 1); |
87ad11b0 | 3742 | |
6d36483b | 3743 | /* Save RP first. The calling conventions manual states RP will |
cc858176 | 3744 | always be stored into the caller's frame at sp - 20 or sp - 16 |
5e3c5739 | 3745 | depending on which ABI is in use. */ |
18d50ae6 | 3746 | if (df_regs_ever_live_p (2) || crtl->calls_eh_return) |
df6b92e4 | 3747 | { |
3748 | store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM); | |
3749 | rp_saved = true; | |
3750 | } | |
3751 | else | |
3752 | rp_saved = false; | |
6d36483b | 3753 | |
daee63dd | 3754 | /* Allocate the local frame and set up the frame pointer if needed. */ |
58361f39 | 3755 | if (actual_fsize != 0) |
3756 | { | |
3757 | if (frame_pointer_needed) | |
3758 | { | |
3759 | /* Copy the old frame pointer temporarily into %r1. Set up the | |
3760 | new stack pointer, then store away the saved old frame pointer | |
a584fe8a | 3761 | into the stack at sp and at the same time update the stack |
3762 | pointer by actual_fsize bytes. Two versions, first | |
58361f39 | 3763 | handles small (<8k) frames. The second handles large (>=8k) |
3764 | frames. */ | |
a584fe8a | 3765 | insn = emit_move_insn (tmpreg, frame_pointer_rtx); |
3766 | if (DO_FRAME_NOTES) | |
dc873350 | 3767 | RTX_FRAME_RELATED_P (insn) = 1; |
a584fe8a | 3768 | |
3769 | insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); | |
3770 | if (DO_FRAME_NOTES) | |
3771 | RTX_FRAME_RELATED_P (insn) = 1; | |
3772 | ||
3773 | if (VAL_14_BITS_P (actual_fsize)) | |
3774 | store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize); | |
58361f39 | 3775 | else |
3776 | { | |
3777 | /* It is incorrect to store the saved frame pointer at *sp, | |
3778 | then increment sp (writes beyond the current stack boundary). | |
3779 | ||
3780 | So instead use stwm to store at *sp and post-increment the | |
3781 | stack pointer as an atomic operation. Then increment sp to | |
3782 | finish allocating the new frame. */ | |
6bcdc1fb | 3783 | HOST_WIDE_INT adjust1 = 8192 - 64; |
3784 | HOST_WIDE_INT adjust2 = actual_fsize - adjust1; | |
cc858176 | 3785 | |
a584fe8a | 3786 | store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1); |
6a2c16d6 | 3787 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3788 | adjust2, 1); |
58361f39 | 3789 | } |
a584fe8a | 3790 | |
e9ec370e | 3791 | /* We set SAVE_SP in frames that need a frame pointer. Thus, |
3792 | we need to store the previous stack pointer (frame pointer) | |
3793 | into the frame marker on targets that use the HP unwind | |
3794 | library. This allows the HP unwind library to be used to | |
3795 | unwind GCC frames. However, we are not fully compatible | |
3796 | with the HP library because our frame layout differs from | |
3797 | that specified in the HP runtime specification. | |
3798 | ||
3799 | We don't want a frame note on this instruction as the frame | |
3800 | marker moves during dynamic stack allocation. | |
3801 | ||
3802 | This instruction also serves as a blockage to prevent | |
3803 | register spills from being scheduled before the stack | |
3804 | pointer is raised. This is necessary as we store | |
3805 | registers using the frame pointer as a base register, | |
3806 | and the frame pointer is set before sp is raised. */ | |
3807 | if (TARGET_HPUX_UNWIND_LIBRARY) | |
3808 | { | |
3809 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, | |
3810 | GEN_INT (TARGET_64BIT ? -8 : -4)); | |
3811 | ||
3812 | emit_move_insn (gen_rtx_MEM (word_mode, addr), | |
3813 | frame_pointer_rtx); | |
3814 | } | |
3815 | else | |
3816 | emit_insn (gen_blockage ()); | |
58361f39 | 3817 | } |
3818 | /* no frame pointer needed. */ | |
3819 | else | |
3820 | { | |
3821 | /* In some cases we can perform the first callee register save | |
3822 | and allocating the stack frame at the same time. If so, just | |
3823 | make a note of it and defer allocating the frame until saving | |
3824 | the callee registers. */ | |
df6edefa | 3825 | if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0) |
58361f39 | 3826 | merge_sp_adjust_with_store = 1; |
3827 | /* Can not optimize. Adjust the stack frame by actual_fsize | |
3828 | bytes. */ | |
3829 | else | |
6a2c16d6 | 3830 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3831 | actual_fsize, 1); |
58361f39 | 3832 | } |
372ef038 | 3833 | } |
3834 | ||
6d36483b | 3835 | /* Normal register save. |
daee63dd | 3836 | |
3837 | Do not save the frame pointer in the frame_pointer_needed case. It | |
3838 | was done earlier. */ | |
87ad11b0 | 3839 | if (frame_pointer_needed) |
3840 | { | |
a584fe8a | 3841 | offset = local_fsize; |
3842 | ||
3843 | /* Saving the EH return data registers in the frame is the simplest | |
3844 | way to get the frame unwind information emitted. We put them | |
3845 | just before the general registers. */ | |
18d50ae6 | 3846 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 3847 | { |
3848 | unsigned int i, regno; | |
3849 | ||
3850 | for (i = 0; ; ++i) | |
3851 | { | |
3852 | regno = EH_RETURN_DATA_REGNO (i); | |
3853 | if (regno == INVALID_REGNUM) | |
3854 | break; | |
3855 | ||
3856 | store_reg (regno, offset, FRAME_POINTER_REGNUM); | |
3857 | offset += UNITS_PER_WORD; | |
3858 | } | |
3859 | } | |
3860 | ||
3861 | for (i = 18; i >= 4; i--) | |
3072d30e | 3862 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
87ad11b0 | 3863 | { |
6a2c16d6 | 3864 | store_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 3865 | offset += UNITS_PER_WORD; |
a9960cdc | 3866 | gr_saved++; |
87ad11b0 | 3867 | } |
7f7c4869 | 3868 | /* Account for %r3 which is saved in a special place. */ |
9b0c95be | 3869 | gr_saved++; |
87ad11b0 | 3870 | } |
daee63dd | 3871 | /* No frame pointer needed. */ |
87ad11b0 | 3872 | else |
3873 | { | |
a584fe8a | 3874 | offset = local_fsize - actual_fsize; |
3875 | ||
3876 | /* Saving the EH return data registers in the frame is the simplest | |
3877 | way to get the frame unwind information emitted. */ | |
18d50ae6 | 3878 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 3879 | { |
3880 | unsigned int i, regno; | |
3881 | ||
3882 | for (i = 0; ; ++i) | |
3883 | { | |
3884 | regno = EH_RETURN_DATA_REGNO (i); | |
3885 | if (regno == INVALID_REGNUM) | |
3886 | break; | |
3887 | ||
3888 | /* If merge_sp_adjust_with_store is nonzero, then we can | |
3889 | optimize the first save. */ | |
3890 | if (merge_sp_adjust_with_store) | |
3891 | { | |
3892 | store_reg_modify (STACK_POINTER_REGNUM, regno, -offset); | |
3893 | merge_sp_adjust_with_store = 0; | |
3894 | } | |
3895 | else | |
3896 | store_reg (regno, offset, STACK_POINTER_REGNUM); | |
3897 | offset += UNITS_PER_WORD; | |
3898 | } | |
3899 | } | |
3900 | ||
3901 | for (i = 18; i >= 3; i--) | |
3072d30e | 3902 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
87ad11b0 | 3903 | { |
6d36483b | 3904 | /* If merge_sp_adjust_with_store is nonzero, then we can |
afd7b680 | 3905 | optimize the first GR save. */ |
201f01e9 | 3906 | if (merge_sp_adjust_with_store) |
afd7b680 | 3907 | { |
a584fe8a | 3908 | store_reg_modify (STACK_POINTER_REGNUM, i, -offset); |
afd7b680 | 3909 | merge_sp_adjust_with_store = 0; |
afd7b680 | 3910 | } |
3911 | else | |
6a2c16d6 | 3912 | store_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 3913 | offset += UNITS_PER_WORD; |
a9960cdc | 3914 | gr_saved++; |
87ad11b0 | 3915 | } |
daee63dd | 3916 | |
afd7b680 | 3917 | /* If we wanted to merge the SP adjustment with a GR save, but we never |
daee63dd | 3918 | did any GR saves, then just emit the adjustment here. */ |
201f01e9 | 3919 | if (merge_sp_adjust_with_store) |
6a2c16d6 | 3920 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3921 | actual_fsize, 1); |
87ad11b0 | 3922 | } |
6d36483b | 3923 | |
df6edefa | 3924 | /* The hppa calling conventions say that %r19, the pic offset |
3925 | register, is saved at sp - 32 (in this function's frame) | |
3926 | when generating PIC code. FIXME: What is the correct thing | |
3927 | to do for functions which make no calls and allocate no | |
3928 | frame? Do we need to allocate a frame, or can we just omit | |
8f177faf | 3929 | the save? For now we'll just omit the save. |
3930 | ||
3931 | We don't want a note on this insn as the frame marker can | |
3932 | move if there is a dynamic stack allocation. */ | |
df6edefa | 3933 | if (flag_pic && actual_fsize != 0 && !TARGET_64BIT) |
8f177faf | 3934 | { |
3935 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32)); | |
3936 | ||
3937 | emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx); | |
3938 | ||
3939 | } | |
df6edefa | 3940 | |
87ad11b0 | 3941 | /* Align pointer properly (doubleword boundary). */ |
3942 | offset = (offset + 7) & ~7; | |
3943 | ||
3944 | /* Floating point register store. */ | |
3945 | if (save_fregs) | |
87ad11b0 | 3946 | { |
a584fe8a | 3947 | rtx base; |
3948 | ||
daee63dd | 3949 | /* First get the frame or stack pointer to the start of the FP register |
3950 | save area. */ | |
a1ab4fa3 | 3951 | if (frame_pointer_needed) |
a584fe8a | 3952 | { |
3953 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); | |
3954 | base = frame_pointer_rtx; | |
3955 | } | |
a1ab4fa3 | 3956 | else |
a584fe8a | 3957 | { |
3958 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); | |
3959 | base = stack_pointer_rtx; | |
3960 | } | |
daee63dd | 3961 | |
3962 | /* Now actually save the FP registers. */ | |
bac38c40 | 3963 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
7f7c4869 | 3964 | { |
3072d30e | 3965 | if (df_regs_ever_live_p (i) |
3966 | || (! TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
7f7c4869 | 3967 | { |
6a2c16d6 | 3968 | rtx addr, insn, reg; |
cc858176 | 3969 | addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); |
3970 | reg = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 3971 | insn = emit_move_insn (addr, reg); |
3972 | if (DO_FRAME_NOTES) | |
3973 | { | |
3974 | RTX_FRAME_RELATED_P (insn) = 1; | |
a584fe8a | 3975 | if (TARGET_64BIT) |
3976 | { | |
3977 | rtx mem = gen_rtx_MEM (DFmode, | |
3978 | plus_constant (base, offset)); | |
b9c74b4d | 3979 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3980 | gen_rtx_SET (VOIDmode, mem, reg)); | |
a584fe8a | 3981 | } |
3982 | else | |
3983 | { | |
3984 | rtx meml = gen_rtx_MEM (SFmode, | |
3985 | plus_constant (base, offset)); | |
3986 | rtx memr = gen_rtx_MEM (SFmode, | |
3987 | plus_constant (base, offset + 4)); | |
3988 | rtx regl = gen_rtx_REG (SFmode, i); | |
3989 | rtx regr = gen_rtx_REG (SFmode, i + 1); | |
3990 | rtx setl = gen_rtx_SET (VOIDmode, meml, regl); | |
3991 | rtx setr = gen_rtx_SET (VOIDmode, memr, regr); | |
3992 | rtvec vec; | |
3993 | ||
3994 | RTX_FRAME_RELATED_P (setl) = 1; | |
3995 | RTX_FRAME_RELATED_P (setr) = 1; | |
3996 | vec = gen_rtvec (2, setl, setr); | |
b9c74b4d | 3997 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3998 | gen_rtx_SEQUENCE (VOIDmode, vec)); | |
a584fe8a | 3999 | } |
6a2c16d6 | 4000 | } |
4001 | offset += GET_MODE_SIZE (DFmode); | |
7f7c4869 | 4002 | fr_saved++; |
4003 | } | |
4004 | } | |
87ad11b0 | 4005 | } |
4006 | } | |
4007 | ||
cc858176 | 4008 | /* Emit RTL to load REG from the memory location specified by BASE+DISP. |
4009 | Handle case where DISP > 8k by using the add_high_const patterns. */ | |
4010 | ||
6a2c16d6 | 4011 | static void |
6bcdc1fb | 4012 | load_reg (int reg, HOST_WIDE_INT disp, int base) |
cc858176 | 4013 | { |
6bcdc1fb | 4014 | rtx dest = gen_rtx_REG (word_mode, reg); |
4015 | rtx basereg = gen_rtx_REG (Pmode, base); | |
4016 | rtx src; | |
cc858176 | 4017 | |
cc858176 | 4018 | if (VAL_14_BITS_P (disp)) |
6bcdc1fb | 4019 | src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
4020 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) | |
cc858176 | 4021 | { |
6bcdc1fb | 4022 | rtx delta = GEN_INT (disp); |
4023 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
4024 | ||
4025 | emit_move_insn (tmpreg, delta); | |
4026 | if (TARGET_DISABLE_INDEXING) | |
4027 | { | |
4028 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
4029 | src = gen_rtx_MEM (word_mode, tmpreg); | |
4030 | } | |
4031 | else | |
4032 | src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
cc858176 | 4033 | } |
4034 | else | |
4035 | { | |
4036 | rtx delta = GEN_INT (disp); | |
4037 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
4038 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 4039 | |
cc858176 | 4040 | emit_move_insn (tmpreg, high); |
4041 | src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
cc858176 | 4042 | } |
6bcdc1fb | 4043 | |
4044 | emit_move_insn (dest, src); | |
cc858176 | 4045 | } |
daee63dd | 4046 | |
2247cc5f | 4047 | /* Update the total code bytes output to the text section. */ |
4048 | ||
4049 | static void | |
21a47bc9 | 4050 | update_total_code_bytes (unsigned int nbytes) |
2247cc5f | 4051 | { |
4052 | if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM) | |
8a05c3c2 | 4053 | && !IN_NAMED_SECTION_P (cfun->decl)) |
2247cc5f | 4054 | { |
21a47bc9 | 4055 | unsigned int old_total = total_code_bytes; |
2247cc5f | 4056 | |
21a47bc9 | 4057 | total_code_bytes += nbytes; |
2247cc5f | 4058 | |
21a47bc9 | 4059 | /* Be prepared to handle overflows. */ |
4060 | if (old_total > total_code_bytes) | |
4061 | total_code_bytes = UINT_MAX; | |
2247cc5f | 4062 | } |
4063 | } | |
4064 | ||
17d9b0c3 | 4065 | /* This function generates the assembly code for function exit. |
4066 | Args are as for output_function_prologue (). | |
4067 | ||
4068 | The function epilogue should not depend on the current stack | |
4069 | pointer! It should use the frame pointer only. This is mandatory | |
4070 | because of alloca; we also take advantage of it to omit stack | |
6dc3b0d9 | 4071 | adjustments before returning. */ |
17d9b0c3 | 4072 | |
4073 | static void | |
5c1d8983 | 4074 | pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 4075 | { |
3695c664 | 4076 | rtx insn = get_last_insn (); |
4077 | ||
2247cc5f | 4078 | last_address = 0; |
4079 | ||
daee63dd | 4080 | /* hppa_expand_epilogue does the dirty work now. We just need |
4081 | to output the assembler directives which denote the end | |
3695c664 | 4082 | of a function. |
4083 | ||
4084 | To make debuggers happy, emit a nop if the epilogue was completely | |
4085 | eliminated due to a volatile call as the last insn in the | |
6d36483b | 4086 | current function. That way the return address (in %r2) will |
3695c664 | 4087 | always point to a valid instruction in the current function. */ |
4088 | ||
4089 | /* Get the last real insn. */ | |
4090 | if (GET_CODE (insn) == NOTE) | |
4091 | insn = prev_real_insn (insn); | |
4092 | ||
4093 | /* If it is a sequence, then look inside. */ | |
4094 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
4095 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
4096 | ||
6d36483b | 4097 | /* If insn is a CALL_INSN, then it must be a call to a volatile |
3695c664 | 4098 | function (otherwise there would be epilogue insns). */ |
4099 | if (insn && GET_CODE (insn) == CALL_INSN) | |
90c41894 | 4100 | { |
4101 | fputs ("\tnop\n", file); | |
4102 | last_address += 4; | |
4103 | } | |
6d36483b | 4104 | |
9c0ac0fd | 4105 | fputs ("\t.EXIT\n\t.PROCEND\n", file); |
90c41894 | 4106 | |
916c9cef | 4107 | if (TARGET_SOM && TARGET_GAS) |
4108 | { | |
4109 | /* We done with this subspace except possibly for some additional | |
4110 | debug information. Forget that we are in this subspace to ensure | |
4111 | that the next function is output in its own subspace. */ | |
2f14b1f9 | 4112 | in_section = NULL; |
78962d38 | 4113 | cfun->machine->in_nsubspa = 2; |
916c9cef | 4114 | } |
4115 | ||
2247cc5f | 4116 | if (INSN_ADDRESSES_SET_P ()) |
90c41894 | 4117 | { |
2247cc5f | 4118 | insn = get_last_nonnote_insn (); |
4119 | last_address += INSN_ADDRESSES (INSN_UID (insn)); | |
4120 | if (INSN_P (insn)) | |
4121 | last_address += insn_default_length (insn); | |
4122 | last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) | |
4123 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
90c41894 | 4124 | } |
21a47bc9 | 4125 | else |
4126 | last_address = UINT_MAX; | |
2247cc5f | 4127 | |
4128 | /* Finally, update the total number of code bytes output so far. */ | |
4129 | update_total_code_bytes (last_address); | |
daee63dd | 4130 | } |
afd7b680 | 4131 | |
daee63dd | 4132 | void |
5c1d8983 | 4133 | hppa_expand_epilogue (void) |
daee63dd | 4134 | { |
6d36483b | 4135 | rtx tmpreg; |
6bcdc1fb | 4136 | HOST_WIDE_INT offset; |
4137 | HOST_WIDE_INT ret_off = 0; | |
4138 | int i; | |
58361f39 | 4139 | int merge_sp_adjust_with_load = 0; |
daee63dd | 4140 | |
4141 | /* We will use this often. */ | |
440c23df | 4142 | tmpreg = gen_rtx_REG (word_mode, 1); |
daee63dd | 4143 | |
4144 | /* Try to restore RP early to avoid load/use interlocks when | |
4145 | RP gets used in the return (bv) instruction. This appears to still | |
6dc3b0d9 | 4146 | be necessary even when we schedule the prologue and epilogue. */ |
df6b92e4 | 4147 | if (rp_saved) |
58361f39 | 4148 | { |
4149 | ret_off = TARGET_64BIT ? -16 : -20; | |
4150 | if (frame_pointer_needed) | |
4151 | { | |
6a2c16d6 | 4152 | load_reg (2, ret_off, FRAME_POINTER_REGNUM); |
58361f39 | 4153 | ret_off = 0; |
4154 | } | |
4155 | else | |
4156 | { | |
4157 | /* No frame pointer, and stack is smaller than 8k. */ | |
4158 | if (VAL_14_BITS_P (ret_off - actual_fsize)) | |
4159 | { | |
6a2c16d6 | 4160 | load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM); |
58361f39 | 4161 | ret_off = 0; |
4162 | } | |
4163 | } | |
4164 | } | |
daee63dd | 4165 | |
4166 | /* General register restores. */ | |
87ad11b0 | 4167 | if (frame_pointer_needed) |
4168 | { | |
a584fe8a | 4169 | offset = local_fsize; |
4170 | ||
4171 | /* If the current function calls __builtin_eh_return, then we need | |
4172 | to restore the saved EH data registers. */ | |
18d50ae6 | 4173 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 4174 | { |
4175 | unsigned int i, regno; | |
4176 | ||
4177 | for (i = 0; ; ++i) | |
4178 | { | |
4179 | regno = EH_RETURN_DATA_REGNO (i); | |
4180 | if (regno == INVALID_REGNUM) | |
4181 | break; | |
4182 | ||
4183 | load_reg (regno, offset, FRAME_POINTER_REGNUM); | |
4184 | offset += UNITS_PER_WORD; | |
4185 | } | |
4186 | } | |
4187 | ||
4188 | for (i = 18; i >= 4; i--) | |
3072d30e | 4189 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
87ad11b0 | 4190 | { |
6a2c16d6 | 4191 | load_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 4192 | offset += UNITS_PER_WORD; |
87ad11b0 | 4193 | } |
87ad11b0 | 4194 | } |
4195 | else | |
4196 | { | |
a584fe8a | 4197 | offset = local_fsize - actual_fsize; |
4198 | ||
4199 | /* If the current function calls __builtin_eh_return, then we need | |
4200 | to restore the saved EH data registers. */ | |
18d50ae6 | 4201 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 4202 | { |
4203 | unsigned int i, regno; | |
4204 | ||
4205 | for (i = 0; ; ++i) | |
4206 | { | |
4207 | regno = EH_RETURN_DATA_REGNO (i); | |
4208 | if (regno == INVALID_REGNUM) | |
4209 | break; | |
4210 | ||
4211 | /* Only for the first load. | |
4212 | merge_sp_adjust_with_load holds the register load | |
4213 | with which we will merge the sp adjustment. */ | |
4214 | if (merge_sp_adjust_with_load == 0 | |
4215 | && local_fsize == 0 | |
4216 | && VAL_14_BITS_P (-actual_fsize)) | |
4217 | merge_sp_adjust_with_load = regno; | |
4218 | else | |
4219 | load_reg (regno, offset, STACK_POINTER_REGNUM); | |
4220 | offset += UNITS_PER_WORD; | |
4221 | } | |
4222 | } | |
4223 | ||
4224 | for (i = 18; i >= 3; i--) | |
7f7c4869 | 4225 | { |
3072d30e | 4226 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
7f7c4869 | 4227 | { |
7f7c4869 | 4228 | /* Only for the first load. |
4229 | merge_sp_adjust_with_load holds the register load | |
4230 | with which we will merge the sp adjustment. */ | |
58361f39 | 4231 | if (merge_sp_adjust_with_load == 0 |
7f7c4869 | 4232 | && local_fsize == 0 |
58361f39 | 4233 | && VAL_14_BITS_P (-actual_fsize)) |
7f7c4869 | 4234 | merge_sp_adjust_with_load = i; |
4235 | else | |
6a2c16d6 | 4236 | load_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 4237 | offset += UNITS_PER_WORD; |
7f7c4869 | 4238 | } |
4239 | } | |
87ad11b0 | 4240 | } |
daee63dd | 4241 | |
87ad11b0 | 4242 | /* Align pointer properly (doubleword boundary). */ |
4243 | offset = (offset + 7) & ~7; | |
4244 | ||
daee63dd | 4245 | /* FP register restores. */ |
87ad11b0 | 4246 | if (save_fregs) |
87ad11b0 | 4247 | { |
daee63dd | 4248 | /* Adjust the register to index off of. */ |
a1ab4fa3 | 4249 | if (frame_pointer_needed) |
a584fe8a | 4250 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); |
a1ab4fa3 | 4251 | else |
a584fe8a | 4252 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); |
daee63dd | 4253 | |
4254 | /* Actually do the restores now. */ | |
bac38c40 | 4255 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
3072d30e | 4256 | if (df_regs_ever_live_p (i) |
4257 | || (! TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
cc858176 | 4258 | { |
4259 | rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); | |
4260 | rtx dest = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 4261 | emit_move_insn (dest, src); |
cc858176 | 4262 | } |
87ad11b0 | 4263 | } |
daee63dd | 4264 | |
14660146 | 4265 | /* Emit a blockage insn here to keep these insns from being moved to |
4266 | an earlier spot in the epilogue, or into the main instruction stream. | |
4267 | ||
4268 | This is necessary as we must not cut the stack back before all the | |
4269 | restores are finished. */ | |
4270 | emit_insn (gen_blockage ()); | |
daee63dd | 4271 | |
9840d99d | 4272 | /* Reset stack pointer (and possibly frame pointer). The stack |
42819d4e | 4273 | pointer is initially set to fp + 64 to avoid a race condition. */ |
58361f39 | 4274 | if (frame_pointer_needed) |
87ad11b0 | 4275 | { |
cc858176 | 4276 | rtx delta = GEN_INT (-64); |
a584fe8a | 4277 | |
4278 | set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0); | |
4279 | emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta)); | |
87ad11b0 | 4280 | } |
daee63dd | 4281 | /* If we were deferring a callee register restore, do it now. */ |
58361f39 | 4282 | else if (merge_sp_adjust_with_load) |
4283 | { | |
4284 | rtx delta = GEN_INT (-actual_fsize); | |
cc858176 | 4285 | rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load); |
a584fe8a | 4286 | |
4287 | emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)); | |
58361f39 | 4288 | } |
daee63dd | 4289 | else if (actual_fsize != 0) |
a584fe8a | 4290 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
4291 | - actual_fsize, 0); | |
58361f39 | 4292 | |
4293 | /* If we haven't restored %r2 yet (no frame pointer, and a stack | |
4294 | frame greater than 8k), do so now. */ | |
4295 | if (ret_off != 0) | |
6a2c16d6 | 4296 | load_reg (2, ret_off, STACK_POINTER_REGNUM); |
a584fe8a | 4297 | |
18d50ae6 | 4298 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 4299 | { |
4300 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
4301 | ||
4302 | emit_insn (gen_blockage ()); | |
4303 | emit_insn (TARGET_64BIT | |
4304 | ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa) | |
4305 | : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa)); | |
4306 | } | |
87ad11b0 | 4307 | } |
4308 | ||
d7e2f694 | 4309 | rtx |
5c1d8983 | 4310 | hppa_pic_save_rtx (void) |
cf3de5bb | 4311 | { |
d7e2f694 | 4312 | return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM); |
df6edefa | 4313 | } |
4314 | ||
bb1bc2ca | 4315 | #ifndef NO_DEFERRED_PROFILE_COUNTERS |
4316 | #define NO_DEFERRED_PROFILE_COUNTERS 0 | |
4317 | #endif | |
4318 | ||
bb1bc2ca | 4319 | |
4320 | /* Vector of funcdef numbers. */ | |
4321 | static VEC(int,heap) *funcdef_nos; | |
4322 | ||
4323 | /* Output deferred profile counters. */ | |
4324 | static void | |
4325 | output_deferred_profile_counters (void) | |
4326 | { | |
4327 | unsigned int i; | |
4328 | int align, n; | |
4329 | ||
4330 | if (VEC_empty (int, funcdef_nos)) | |
4331 | return; | |
4332 | ||
2f14b1f9 | 4333 | switch_to_section (data_section); |
bb1bc2ca | 4334 | align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE); |
4335 | ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT)); | |
4336 | ||
4337 | for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++) | |
4338 | { | |
4339 | targetm.asm_out.internal_label (asm_out_file, "LP", n); | |
4340 | assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1); | |
4341 | } | |
4342 | ||
4343 | VEC_free (int, heap, funcdef_nos); | |
4344 | } | |
4345 | ||
df6edefa | 4346 | void |
5c1d8983 | 4347 | hppa_profile_hook (int label_no) |
df6edefa | 4348 | { |
4da37e2f | 4349 | /* We use SImode for the address of the function in both 32 and |
4350 | 64-bit code to avoid having to provide DImode versions of the | |
4351 | lcla2 and load_offset_label_address insn patterns. */ | |
4352 | rtx reg = gen_reg_rtx (SImode); | |
4353 | rtx label_rtx = gen_label_rtx (); | |
a9ac13e4 | 4354 | rtx begin_label_rtx, call_insn; |
4355 | char begin_label_name[16]; | |
df6edefa | 4356 | |
a9ac13e4 | 4357 | ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL, |
b8a21949 | 4358 | label_no); |
4da37e2f | 4359 | begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name)); |
df6edefa | 4360 | |
4361 | if (TARGET_64BIT) | |
4362 | emit_move_insn (arg_pointer_rtx, | |
4363 | gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, | |
4364 | GEN_INT (64))); | |
4365 | ||
df6edefa | 4366 | emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2)); |
4367 | ||
80777cd8 | 4368 | /* The address of the function is loaded into %r25 with an instruction- |
4da37e2f | 4369 | relative sequence that avoids the use of relocations. The sequence |
4370 | is split so that the load_offset_label_address instruction can | |
4371 | occupy the delay slot of the call to _mcount. */ | |
4372 | if (TARGET_PA_20) | |
4373 | emit_insn (gen_lcla2 (reg, label_rtx)); | |
4374 | else | |
4375 | emit_insn (gen_lcla1 (reg, label_rtx)); | |
4376 | ||
4377 | emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25), | |
4378 | reg, begin_label_rtx, label_rtx)); | |
4379 | ||
bb1bc2ca | 4380 | #if !NO_DEFERRED_PROFILE_COUNTERS |
df6edefa | 4381 | { |
4382 | rtx count_label_rtx, addr, r24; | |
a9ac13e4 | 4383 | char count_label_name[16]; |
df6edefa | 4384 | |
bb1bc2ca | 4385 | VEC_safe_push (int, heap, funcdef_nos, label_no); |
a9ac13e4 | 4386 | ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no); |
4387 | count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name)); | |
df6edefa | 4388 | |
831a12d9 | 4389 | addr = force_reg (Pmode, count_label_rtx); |
df6edefa | 4390 | r24 = gen_rtx_REG (Pmode, 24); |
4391 | emit_move_insn (r24, addr); | |
4392 | ||
df6edefa | 4393 | call_insn = |
4da37e2f | 4394 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4395 | gen_rtx_SYMBOL_REF (Pmode, | |
4396 | "_mcount")), | |
4397 | GEN_INT (TARGET_64BIT ? 24 : 12))); | |
df6edefa | 4398 | |
4399 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24); | |
4400 | } | |
4401 | #else | |
4da37e2f | 4402 | |
df6edefa | 4403 | call_insn = |
4da37e2f | 4404 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4405 | gen_rtx_SYMBOL_REF (Pmode, | |
4406 | "_mcount")), | |
4407 | GEN_INT (TARGET_64BIT ? 16 : 8))); | |
4408 | ||
df6edefa | 4409 | #endif |
4410 | ||
4da37e2f | 4411 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25)); |
4412 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26)); | |
4413 | ||
df6edefa | 4414 | /* Indicate the _mcount call cannot throw, nor will it execute a |
4415 | non-local goto. */ | |
450040e5 | 4416 | make_reg_eh_region_note_nothrow_nononlocal (call_insn); |
cf3de5bb | 4417 | } |
4418 | ||
e07ff380 | 4419 | /* Fetch the return address for the frame COUNT steps up from |
4420 | the current frame, after the prologue. FRAMEADDR is the | |
4421 | frame pointer of the COUNT frame. | |
4422 | ||
f49b2e77 | 4423 | We want to ignore any export stub remnants here. To handle this, |
4424 | we examine the code at the return address, and if it is an export | |
4425 | stub, we return a memory rtx for the stub return address stored | |
4426 | at frame-24. | |
a6c6fd6c | 4427 | |
4428 | The value returned is used in two different ways: | |
4429 | ||
4430 | 1. To find a function's caller. | |
4431 | ||
4432 | 2. To change the return address for a function. | |
4433 | ||
4434 | This function handles most instances of case 1; however, it will | |
4435 | fail if there are two levels of stubs to execute on the return | |
4436 | path. The only way I believe that can happen is if the return value | |
4437 | needs a parameter relocation, which never happens for C code. | |
4438 | ||
4439 | This function handles most instances of case 2; however, it will | |
4440 | fail if we did not originally have stub code on the return path | |
f49b2e77 | 4441 | but will need stub code on the new return path. This can happen if |
a6c6fd6c | 4442 | the caller & callee are both in the main program, but the new |
f49b2e77 | 4443 | return location is in a shared library. */ |
e07ff380 | 4444 | |
4445 | rtx | |
5c1d8983 | 4446 | return_addr_rtx (int count, rtx frameaddr) |
e07ff380 | 4447 | { |
4448 | rtx label; | |
f49b2e77 | 4449 | rtx rp; |
e07ff380 | 4450 | rtx saved_rp; |
4451 | rtx ins; | |
4452 | ||
74f4459c | 4453 | /* Instruction stream at the normal return address for the export stub: |
4454 | ||
4455 | 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp | |
4456 | 0x004010a1 | stub+12: ldsid (sr0,rp),r1 | |
4457 | 0x00011820 | stub+16: mtsp r1,sr0 | |
4458 | 0xe0400002 | stub+20: be,n 0(sr0,rp) | |
4459 | ||
4460 | 0xe0400002 must be specified as -532676606 so that it won't be | |
4461 | rejected as an invalid immediate operand on 64-bit hosts. */ | |
4462 | ||
4463 | HOST_WIDE_INT insns[4] = {0x4bc23fd1, 0x004010a1, 0x00011820, -532676606}; | |
4464 | int i; | |
4465 | ||
f49b2e77 | 4466 | if (count != 0) |
4467 | return NULL_RTX; | |
b29897dd | 4468 | |
f49b2e77 | 4469 | rp = get_hard_reg_initial_val (Pmode, 2); |
e07ff380 | 4470 | |
f49b2e77 | 4471 | if (TARGET_64BIT || TARGET_NO_SPACE_REGS) |
4472 | return rp; | |
e07ff380 | 4473 | |
74f4459c | 4474 | /* If there is no export stub then just use the value saved from |
4475 | the return pointer register. */ | |
4476 | ||
b29897dd | 4477 | saved_rp = gen_reg_rtx (Pmode); |
f49b2e77 | 4478 | emit_move_insn (saved_rp, rp); |
e07ff380 | 4479 | |
4480 | /* Get pointer to the instruction stream. We have to mask out the | |
4481 | privilege level from the two low order bits of the return address | |
4482 | pointer here so that ins will point to the start of the first | |
4483 | instruction that would have been executed if we returned. */ | |
f49b2e77 | 4484 | ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR)); |
e07ff380 | 4485 | label = gen_label_rtx (); |
4486 | ||
4487 | /* Check the instruction stream at the normal return address for the | |
74f4459c | 4488 | export stub. If it is an export stub, than our return address is |
4489 | really in -24[frameaddr]. */ | |
e07ff380 | 4490 | |
74f4459c | 4491 | for (i = 0; i < 3; i++) |
4492 | { | |
4493 | rtx op0 = gen_rtx_MEM (SImode, plus_constant (ins, i * 4)); | |
4494 | rtx op1 = GEN_INT (insns[i]); | |
4495 | emit_cmp_and_jump_insns (op0, op1, NE, NULL, SImode, 0, label); | |
4496 | } | |
e07ff380 | 4497 | |
f49b2e77 | 4498 | /* Here we know that our return address points to an export |
e07ff380 | 4499 | stub. We don't want to return the address of the export stub, |
f49b2e77 | 4500 | but rather the return address of the export stub. That return |
4501 | address is stored at -24[frameaddr]. */ | |
e07ff380 | 4502 | |
f49b2e77 | 4503 | emit_move_insn (saved_rp, |
4504 | gen_rtx_MEM (Pmode, | |
4505 | memory_address (Pmode, | |
4506 | plus_constant (frameaddr, | |
4507 | -24)))); | |
e07ff380 | 4508 | |
4509 | emit_label (label); | |
74f4459c | 4510 | |
f49b2e77 | 4511 | return saved_rp; |
e07ff380 | 4512 | } |
4513 | ||
87ad11b0 | 4514 | void |
74f4459c | 4515 | emit_bcond_fp (rtx operands[]) |
87ad11b0 | 4516 | { |
74f4459c | 4517 | enum rtx_code code = GET_CODE (operands[0]); |
4518 | rtx operand0 = operands[1]; | |
4519 | rtx operand1 = operands[2]; | |
4520 | rtx label = operands[3]; | |
4521 | ||
4522 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0), | |
4523 | gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1))); | |
4524 | ||
ad851752 | 4525 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, |
4526 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
74f4459c | 4527 | gen_rtx_fmt_ee (NE, |
ad851752 | 4528 | VOIDmode, |
4529 | gen_rtx_REG (CCFPmode, 0), | |
4530 | const0_rtx), | |
74f4459c | 4531 | gen_rtx_LABEL_REF (VOIDmode, label), |
ad851752 | 4532 | pc_rtx))); |
87ad11b0 | 4533 | |
4534 | } | |
4535 | ||
8b49b3c7 | 4536 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
4537 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4538 | ||
747af5e7 | 4539 | static int |
5c1d8983 | 4540 | pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
8b49b3c7 | 4541 | { |
43048d2c | 4542 | enum attr_type attr_type; |
4543 | ||
cde3e16c | 4544 | /* Don't adjust costs for a pa8000 chip, also do not adjust any |
4545 | true dependencies as they are described with bypasses now. */ | |
4546 | if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0) | |
342aabd9 | 4547 | return cost; |
4548 | ||
d402da4b | 4549 | if (! recog_memoized (insn)) |
4550 | return 0; | |
8b49b3c7 | 4551 | |
43048d2c | 4552 | attr_type = get_attr_type (insn); |
4553 | ||
ecf2283d | 4554 | switch (REG_NOTE_KIND (link)) |
8b49b3c7 | 4555 | { |
ecf2283d | 4556 | case REG_DEP_ANTI: |
8b49b3c7 | 4557 | /* Anti dependency; DEP_INSN reads a register that INSN writes some |
4558 | cycles later. */ | |
4559 | ||
43048d2c | 4560 | if (attr_type == TYPE_FPLOAD) |
8b49b3c7 | 4561 | { |
d402da4b | 4562 | rtx pat = PATTERN (insn); |
4563 | rtx dep_pat = PATTERN (dep_insn); | |
4564 | if (GET_CODE (pat) == PARALLEL) | |
4565 | { | |
4566 | /* This happens for the fldXs,mb patterns. */ | |
4567 | pat = XVECEXP (pat, 0, 0); | |
4568 | } | |
4569 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
8b49b3c7 | 4570 | /* If this happens, we have to extend this to schedule |
d402da4b | 4571 | optimally. Return 0 for now. */ |
4572 | return 0; | |
8b49b3c7 | 4573 | |
d402da4b | 4574 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) |
8b49b3c7 | 4575 | { |
d402da4b | 4576 | if (! recog_memoized (dep_insn)) |
4577 | return 0; | |
8b49b3c7 | 4578 | switch (get_attr_type (dep_insn)) |
4579 | { | |
4580 | case TYPE_FPALU: | |
134b4858 | 4581 | case TYPE_FPMULSGL: |
4582 | case TYPE_FPMULDBL: | |
8b49b3c7 | 4583 | case TYPE_FPDIVSGL: |
4584 | case TYPE_FPDIVDBL: | |
4585 | case TYPE_FPSQRTSGL: | |
4586 | case TYPE_FPSQRTDBL: | |
d402da4b | 4587 | /* A fpload can't be issued until one cycle before a |
01cc3b75 | 4588 | preceding arithmetic operation has finished if |
d402da4b | 4589 | the target of the fpload is any of the sources |
4590 | (or destination) of the arithmetic operation. */ | |
cde3e16c | 4591 | return insn_default_latency (dep_insn) - 1; |
134b4858 | 4592 | |
4593 | default: | |
4594 | return 0; | |
4595 | } | |
4596 | } | |
4597 | } | |
43048d2c | 4598 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4599 | { |
4600 | rtx pat = PATTERN (insn); | |
4601 | rtx dep_pat = PATTERN (dep_insn); | |
4602 | if (GET_CODE (pat) == PARALLEL) | |
4603 | { | |
4604 | /* This happens for the fldXs,mb patterns. */ | |
4605 | pat = XVECEXP (pat, 0, 0); | |
4606 | } | |
4607 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4608 | /* If this happens, we have to extend this to schedule | |
4609 | optimally. Return 0 for now. */ | |
4610 | return 0; | |
4611 | ||
4612 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) | |
4613 | { | |
4614 | if (! recog_memoized (dep_insn)) | |
4615 | return 0; | |
4616 | switch (get_attr_type (dep_insn)) | |
4617 | { | |
4618 | case TYPE_FPDIVSGL: | |
4619 | case TYPE_FPDIVDBL: | |
4620 | case TYPE_FPSQRTSGL: | |
4621 | case TYPE_FPSQRTDBL: | |
4622 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4623 | preceding divide or sqrt operation has finished if |
134b4858 | 4624 | the target of the ALU flop is any of the sources |
4625 | (or destination) of the divide or sqrt operation. */ | |
cde3e16c | 4626 | return insn_default_latency (dep_insn) - 2; |
8b49b3c7 | 4627 | |
4628 | default: | |
4629 | return 0; | |
4630 | } | |
4631 | } | |
4632 | } | |
4633 | ||
4634 | /* For other anti dependencies, the cost is 0. */ | |
4635 | return 0; | |
ecf2283d | 4636 | |
4637 | case REG_DEP_OUTPUT: | |
134b4858 | 4638 | /* Output dependency; DEP_INSN writes a register that INSN writes some |
4639 | cycles later. */ | |
43048d2c | 4640 | if (attr_type == TYPE_FPLOAD) |
134b4858 | 4641 | { |
4642 | rtx pat = PATTERN (insn); | |
4643 | rtx dep_pat = PATTERN (dep_insn); | |
4644 | if (GET_CODE (pat) == PARALLEL) | |
4645 | { | |
4646 | /* This happens for the fldXs,mb patterns. */ | |
4647 | pat = XVECEXP (pat, 0, 0); | |
4648 | } | |
4649 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4650 | /* If this happens, we have to extend this to schedule | |
4651 | optimally. Return 0 for now. */ | |
4652 | return 0; | |
4653 | ||
4654 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4655 | { | |
4656 | if (! recog_memoized (dep_insn)) | |
4657 | return 0; | |
4658 | switch (get_attr_type (dep_insn)) | |
4659 | { | |
4660 | case TYPE_FPALU: | |
4661 | case TYPE_FPMULSGL: | |
4662 | case TYPE_FPMULDBL: | |
4663 | case TYPE_FPDIVSGL: | |
4664 | case TYPE_FPDIVDBL: | |
4665 | case TYPE_FPSQRTSGL: | |
4666 | case TYPE_FPSQRTDBL: | |
4667 | /* A fpload can't be issued until one cycle before a | |
01cc3b75 | 4668 | preceding arithmetic operation has finished if |
134b4858 | 4669 | the target of the fpload is the destination of the |
bea4bad2 | 4670 | arithmetic operation. |
4671 | ||
4672 | Exception: For PA7100LC, PA7200 and PA7300, the cost | |
4673 | is 3 cycles, unless they bundle together. We also | |
4674 | pay the penalty if the second insn is a fpload. */ | |
cde3e16c | 4675 | return insn_default_latency (dep_insn) - 1; |
8b49b3c7 | 4676 | |
134b4858 | 4677 | default: |
4678 | return 0; | |
4679 | } | |
4680 | } | |
4681 | } | |
43048d2c | 4682 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4683 | { |
4684 | rtx pat = PATTERN (insn); | |
4685 | rtx dep_pat = PATTERN (dep_insn); | |
4686 | if (GET_CODE (pat) == PARALLEL) | |
4687 | { | |
4688 | /* This happens for the fldXs,mb patterns. */ | |
4689 | pat = XVECEXP (pat, 0, 0); | |
4690 | } | |
4691 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4692 | /* If this happens, we have to extend this to schedule | |
4693 | optimally. Return 0 for now. */ | |
4694 | return 0; | |
4695 | ||
4696 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4697 | { | |
4698 | if (! recog_memoized (dep_insn)) | |
4699 | return 0; | |
4700 | switch (get_attr_type (dep_insn)) | |
4701 | { | |
4702 | case TYPE_FPDIVSGL: | |
4703 | case TYPE_FPDIVDBL: | |
4704 | case TYPE_FPSQRTSGL: | |
4705 | case TYPE_FPSQRTDBL: | |
4706 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4707 | preceding divide or sqrt operation has finished if |
134b4858 | 4708 | the target of the ALU flop is also the target of |
3398e91d | 4709 | the divide or sqrt operation. */ |
cde3e16c | 4710 | return insn_default_latency (dep_insn) - 2; |
134b4858 | 4711 | |
4712 | default: | |
4713 | return 0; | |
4714 | } | |
4715 | } | |
4716 | } | |
4717 | ||
4718 | /* For other output dependencies, the cost is 0. */ | |
4719 | return 0; | |
ecf2283d | 4720 | |
4721 | default: | |
4722 | gcc_unreachable (); | |
134b4858 | 4723 | } |
8b49b3c7 | 4724 | } |
87ad11b0 | 4725 | |
747af5e7 | 4726 | /* Adjust scheduling priorities. We use this to try and keep addil |
4727 | and the next use of %r1 close together. */ | |
4728 | static int | |
5c1d8983 | 4729 | pa_adjust_priority (rtx insn, int priority) |
747af5e7 | 4730 | { |
4731 | rtx set = single_set (insn); | |
4732 | rtx src, dest; | |
4733 | if (set) | |
4734 | { | |
4735 | src = SET_SRC (set); | |
4736 | dest = SET_DEST (set); | |
4737 | if (GET_CODE (src) == LO_SUM | |
4738 | && symbolic_operand (XEXP (src, 1), VOIDmode) | |
4739 | && ! read_only_operand (XEXP (src, 1), VOIDmode)) | |
4740 | priority >>= 3; | |
4741 | ||
4742 | else if (GET_CODE (src) == MEM | |
4743 | && GET_CODE (XEXP (src, 0)) == LO_SUM | |
4744 | && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode) | |
4745 | && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode)) | |
4746 | priority >>= 1; | |
4747 | ||
4748 | else if (GET_CODE (dest) == MEM | |
4749 | && GET_CODE (XEXP (dest, 0)) == LO_SUM | |
4750 | && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode) | |
4751 | && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)) | |
4752 | priority >>= 3; | |
4753 | } | |
4754 | return priority; | |
4755 | } | |
4756 | ||
4757 | /* The 700 can only issue a single insn at a time. | |
4758 | The 7XXX processors can issue two insns at a time. | |
4759 | The 8000 can issue 4 insns at a time. */ | |
4760 | static int | |
5c1d8983 | 4761 | pa_issue_rate (void) |
747af5e7 | 4762 | { |
4763 | switch (pa_cpu) | |
4764 | { | |
4765 | case PROCESSOR_700: return 1; | |
4766 | case PROCESSOR_7100: return 2; | |
4767 | case PROCESSOR_7100LC: return 2; | |
4768 | case PROCESSOR_7200: return 2; | |
bea4bad2 | 4769 | case PROCESSOR_7300: return 2; |
747af5e7 | 4770 | case PROCESSOR_8000: return 4; |
4771 | ||
4772 | default: | |
ecf2283d | 4773 | gcc_unreachable (); |
747af5e7 | 4774 | } |
4775 | } | |
4776 | ||
4777 | ||
4778 | ||
58e17b0b | 4779 | /* Return any length adjustment needed by INSN which already has its length |
6d36483b | 4780 | computed as LENGTH. Return zero if no adjustment is necessary. |
58e17b0b | 4781 | |
5fbd5940 | 4782 | For the PA: function calls, millicode calls, and backwards short |
6d36483b | 4783 | conditional branches with unfilled delay slots need an adjustment by +1 |
5fbd5940 | 4784 | (to account for the NOP which will be inserted into the instruction stream). |
58e17b0b | 4785 | |
4786 | Also compute the length of an inline block move here as it is too | |
5fbd5940 | 4787 | complicated to express as a length attribute in pa.md. */ |
58e17b0b | 4788 | int |
5c1d8983 | 4789 | pa_adjust_insn_length (rtx insn, int length) |
58e17b0b | 4790 | { |
4791 | rtx pat = PATTERN (insn); | |
4792 | ||
faf3f8c1 | 4793 | /* Jumps inside switch tables which have unfilled delay slots need |
4794 | adjustment. */ | |
4795 | if (GET_CODE (insn) == JUMP_INSN | |
b932f66c | 4796 | && GET_CODE (pat) == PARALLEL |
4797 | && get_attr_type (insn) == TYPE_BTABLE_BRANCH) | |
3b1e673e | 4798 | return 4; |
58e17b0b | 4799 | /* Millicode insn with an unfilled delay slot. */ |
4800 | else if (GET_CODE (insn) == INSN | |
4801 | && GET_CODE (pat) != SEQUENCE | |
4802 | && GET_CODE (pat) != USE | |
4803 | && GET_CODE (pat) != CLOBBER | |
4804 | && get_attr_type (insn) == TYPE_MILLI) | |
5a1231ef | 4805 | return 4; |
58e17b0b | 4806 | /* Block move pattern. */ |
4807 | else if (GET_CODE (insn) == INSN | |
4808 | && GET_CODE (pat) == PARALLEL | |
f2ebcf32 | 4809 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET |
58e17b0b | 4810 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM |
4811 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM | |
4812 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode | |
4813 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode) | |
008c057d | 4814 | return compute_movmem_length (insn) - 4; |
a7e1bb24 | 4815 | /* Block clear pattern. */ |
4816 | else if (GET_CODE (insn) == INSN | |
4817 | && GET_CODE (pat) == PARALLEL | |
4818 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET | |
4819 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM | |
4820 | && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx | |
4821 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode) | |
008c057d | 4822 | return compute_clrmem_length (insn) - 4; |
58e17b0b | 4823 | /* Conditional branch with an unfilled delay slot. */ |
5fbd5940 | 4824 | else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn)) |
4825 | { | |
4826 | /* Adjust a short backwards conditional with an unfilled delay slot. */ | |
4827 | if (GET_CODE (pat) == SET | |
5a1231ef | 4828 | && length == 4 |
372b3fe2 | 4829 | && JUMP_LABEL (insn) != NULL_RTX |
5fbd5940 | 4830 | && ! forward_branch_p (insn)) |
5a1231ef | 4831 | return 4; |
546a40bd | 4832 | else if (GET_CODE (pat) == PARALLEL |
4833 | && get_attr_type (insn) == TYPE_PARALLEL_BRANCH | |
4834 | && length == 4) | |
4835 | return 4; | |
5fbd5940 | 4836 | /* Adjust dbra insn with short backwards conditional branch with |
6d36483b | 4837 | unfilled delay slot -- only for case where counter is in a |
6dc3b0d9 | 4838 | general register register. */ |
5fbd5940 | 4839 | else if (GET_CODE (pat) == PARALLEL |
4840 | && GET_CODE (XVECEXP (pat, 0, 1)) == SET | |
4841 | && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG | |
6d36483b | 4842 | && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0)) |
5a1231ef | 4843 | && length == 4 |
5fbd5940 | 4844 | && ! forward_branch_p (insn)) |
5a1231ef | 4845 | return 4; |
5fbd5940 | 4846 | else |
4847 | return 0; | |
4848 | } | |
546a40bd | 4849 | return 0; |
58e17b0b | 4850 | } |
4851 | ||
93d3ee56 | 4852 | /* Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook. */ |
4853 | ||
4854 | static bool | |
4855 | pa_print_operand_punct_valid_p (unsigned char code) | |
4856 | { | |
4857 | if (code == '@' | |
4858 | || code == '#' | |
4859 | || code == '*' | |
4860 | || code == '^') | |
4861 | return true; | |
4862 | ||
4863 | return false; | |
4864 | } | |
4865 | ||
87ad11b0 | 4866 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
4867 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
4868 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
4869 | ||
4870 | void | |
5c1d8983 | 4871 | print_operand (FILE *file, rtx x, int code) |
87ad11b0 | 4872 | { |
4873 | switch (code) | |
4874 | { | |
4875 | case '#': | |
4876 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
4877 | if (dbr_sequence_length () == 0) | |
4878 | fputs ("\n\tnop", file); | |
4879 | return; | |
4880 | case '*': | |
87fcb603 | 4881 | /* Output a nullification completer if there's nothing for the */ |
6d36483b | 4882 | /* delay slot or nullification is requested. */ |
87ad11b0 | 4883 | if (dbr_sequence_length () == 0 || |
4884 | (final_sequence && | |
4885 | INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))) | |
4886 | fputs (",n", file); | |
4887 | return; | |
4888 | case 'R': | |
4889 | /* Print out the second register name of a register pair. | |
4890 | I.e., R (6) => 7. */ | |
ea52c577 | 4891 | fputs (reg_names[REGNO (x) + 1], file); |
87ad11b0 | 4892 | return; |
4893 | case 'r': | |
6dc3b0d9 | 4894 | /* A register or zero. */ |
891b55b4 | 4895 | if (x == const0_rtx |
4896 | || (x == CONST0_RTX (DFmode)) | |
4897 | || (x == CONST0_RTX (SFmode))) | |
87ad11b0 | 4898 | { |
c6ae275c | 4899 | fputs ("%r0", file); |
4900 | return; | |
4901 | } | |
4902 | else | |
4903 | break; | |
4904 | case 'f': | |
6dc3b0d9 | 4905 | /* A register or zero (floating point). */ |
c6ae275c | 4906 | if (x == const0_rtx |
4907 | || (x == CONST0_RTX (DFmode)) | |
4908 | || (x == CONST0_RTX (SFmode))) | |
4909 | { | |
4910 | fputs ("%fr0", file); | |
87ad11b0 | 4911 | return; |
4912 | } | |
4913 | else | |
4914 | break; | |
2d14b1f0 | 4915 | case 'A': |
4916 | { | |
4917 | rtx xoperands[2]; | |
4918 | ||
4919 | xoperands[0] = XEXP (XEXP (x, 0), 0); | |
4920 | xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0); | |
4921 | output_global_address (file, xoperands[1], 0); | |
4922 | fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]); | |
4923 | return; | |
4924 | } | |
4925 | ||
c8975385 | 4926 | case 'C': /* Plain (C)ondition */ |
87ad11b0 | 4927 | case 'X': |
4928 | switch (GET_CODE (x)) | |
6d36483b | 4929 | { |
87ad11b0 | 4930 | case EQ: |
9c0ac0fd | 4931 | fputs ("=", file); break; |
87ad11b0 | 4932 | case NE: |
9c0ac0fd | 4933 | fputs ("<>", file); break; |
87ad11b0 | 4934 | case GT: |
9c0ac0fd | 4935 | fputs (">", file); break; |
87ad11b0 | 4936 | case GE: |
9c0ac0fd | 4937 | fputs (">=", file); break; |
87ad11b0 | 4938 | case GEU: |
9c0ac0fd | 4939 | fputs (">>=", file); break; |
87ad11b0 | 4940 | case GTU: |
9c0ac0fd | 4941 | fputs (">>", file); break; |
87ad11b0 | 4942 | case LT: |
9c0ac0fd | 4943 | fputs ("<", file); break; |
87ad11b0 | 4944 | case LE: |
9c0ac0fd | 4945 | fputs ("<=", file); break; |
87ad11b0 | 4946 | case LEU: |
9c0ac0fd | 4947 | fputs ("<<=", file); break; |
87ad11b0 | 4948 | case LTU: |
9c0ac0fd | 4949 | fputs ("<<", file); break; |
87ad11b0 | 4950 | default: |
ecf2283d | 4951 | gcc_unreachable (); |
87ad11b0 | 4952 | } |
4953 | return; | |
c8975385 | 4954 | case 'N': /* Condition, (N)egated */ |
87ad11b0 | 4955 | switch (GET_CODE (x)) |
4956 | { | |
4957 | case EQ: | |
9c0ac0fd | 4958 | fputs ("<>", file); break; |
87ad11b0 | 4959 | case NE: |
9c0ac0fd | 4960 | fputs ("=", file); break; |
87ad11b0 | 4961 | case GT: |
9c0ac0fd | 4962 | fputs ("<=", file); break; |
87ad11b0 | 4963 | case GE: |
9c0ac0fd | 4964 | fputs ("<", file); break; |
87ad11b0 | 4965 | case GEU: |
9c0ac0fd | 4966 | fputs ("<<", file); break; |
87ad11b0 | 4967 | case GTU: |
9c0ac0fd | 4968 | fputs ("<<=", file); break; |
87ad11b0 | 4969 | case LT: |
9c0ac0fd | 4970 | fputs (">=", file); break; |
87ad11b0 | 4971 | case LE: |
9c0ac0fd | 4972 | fputs (">", file); break; |
87ad11b0 | 4973 | case LEU: |
9c0ac0fd | 4974 | fputs (">>", file); break; |
87ad11b0 | 4975 | case LTU: |
9c0ac0fd | 4976 | fputs (">>=", file); break; |
87ad11b0 | 4977 | default: |
ecf2283d | 4978 | gcc_unreachable (); |
87ad11b0 | 4979 | } |
4980 | return; | |
ea52c577 | 4981 | /* For floating point comparisons. Note that the output |
321c1598 | 4982 | predicates are the complement of the desired mode. The |
4983 | conditions for GT, GE, LT, LE and LTGT cause an invalid | |
4984 | operation exception if the result is unordered and this | |
4985 | exception is enabled in the floating-point status register. */ | |
61230bc9 | 4986 | case 'Y': |
4987 | switch (GET_CODE (x)) | |
4988 | { | |
4989 | case EQ: | |
9c0ac0fd | 4990 | fputs ("!=", file); break; |
61230bc9 | 4991 | case NE: |
9c0ac0fd | 4992 | fputs ("=", file); break; |
61230bc9 | 4993 | case GT: |
32509e56 | 4994 | fputs ("!>", file); break; |
61230bc9 | 4995 | case GE: |
32509e56 | 4996 | fputs ("!>=", file); break; |
61230bc9 | 4997 | case LT: |
32509e56 | 4998 | fputs ("!<", file); break; |
61230bc9 | 4999 | case LE: |
32509e56 | 5000 | fputs ("!<=", file); break; |
5001 | case LTGT: | |
5002 | fputs ("!<>", file); break; | |
5003 | case UNLE: | |
321c1598 | 5004 | fputs ("!?<=", file); break; |
32509e56 | 5005 | case UNLT: |
321c1598 | 5006 | fputs ("!?<", file); break; |
32509e56 | 5007 | case UNGE: |
321c1598 | 5008 | fputs ("!?>=", file); break; |
32509e56 | 5009 | case UNGT: |
321c1598 | 5010 | fputs ("!?>", file); break; |
32509e56 | 5011 | case UNEQ: |
321c1598 | 5012 | fputs ("!?=", file); break; |
32509e56 | 5013 | case UNORDERED: |
321c1598 | 5014 | fputs ("!?", file); break; |
32509e56 | 5015 | case ORDERED: |
321c1598 | 5016 | fputs ("?", file); break; |
61230bc9 | 5017 | default: |
ecf2283d | 5018 | gcc_unreachable (); |
61230bc9 | 5019 | } |
5020 | return; | |
c8975385 | 5021 | case 'S': /* Condition, operands are (S)wapped. */ |
5022 | switch (GET_CODE (x)) | |
5023 | { | |
5024 | case EQ: | |
9c0ac0fd | 5025 | fputs ("=", file); break; |
c8975385 | 5026 | case NE: |
9c0ac0fd | 5027 | fputs ("<>", file); break; |
c8975385 | 5028 | case GT: |
9c0ac0fd | 5029 | fputs ("<", file); break; |
c8975385 | 5030 | case GE: |
9c0ac0fd | 5031 | fputs ("<=", file); break; |
c8975385 | 5032 | case GEU: |
9c0ac0fd | 5033 | fputs ("<<=", file); break; |
c8975385 | 5034 | case GTU: |
9c0ac0fd | 5035 | fputs ("<<", file); break; |
c8975385 | 5036 | case LT: |
9c0ac0fd | 5037 | fputs (">", file); break; |
c8975385 | 5038 | case LE: |
9c0ac0fd | 5039 | fputs (">=", file); break; |
c8975385 | 5040 | case LEU: |
9c0ac0fd | 5041 | fputs (">>=", file); break; |
c8975385 | 5042 | case LTU: |
9c0ac0fd | 5043 | fputs (">>", file); break; |
c8975385 | 5044 | default: |
ecf2283d | 5045 | gcc_unreachable (); |
6d36483b | 5046 | } |
c8975385 | 5047 | return; |
5048 | case 'B': /* Condition, (B)oth swapped and negate. */ | |
5049 | switch (GET_CODE (x)) | |
5050 | { | |
5051 | case EQ: | |
9c0ac0fd | 5052 | fputs ("<>", file); break; |
c8975385 | 5053 | case NE: |
9c0ac0fd | 5054 | fputs ("=", file); break; |
c8975385 | 5055 | case GT: |
9c0ac0fd | 5056 | fputs (">=", file); break; |
c8975385 | 5057 | case GE: |
9c0ac0fd | 5058 | fputs (">", file); break; |
c8975385 | 5059 | case GEU: |
9c0ac0fd | 5060 | fputs (">>", file); break; |
c8975385 | 5061 | case GTU: |
9c0ac0fd | 5062 | fputs (">>=", file); break; |
c8975385 | 5063 | case LT: |
9c0ac0fd | 5064 | fputs ("<=", file); break; |
c8975385 | 5065 | case LE: |
9c0ac0fd | 5066 | fputs ("<", file); break; |
c8975385 | 5067 | case LEU: |
9c0ac0fd | 5068 | fputs ("<<", file); break; |
c8975385 | 5069 | case LTU: |
9c0ac0fd | 5070 | fputs ("<<=", file); break; |
c8975385 | 5071 | default: |
ecf2283d | 5072 | gcc_unreachable (); |
6d36483b | 5073 | } |
c8975385 | 5074 | return; |
5075 | case 'k': | |
ecf2283d | 5076 | gcc_assert (GET_CODE (x) == CONST_INT); |
5077 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x)); | |
5078 | return; | |
5e3c5739 | 5079 | case 'Q': |
ecf2283d | 5080 | gcc_assert (GET_CODE (x) == CONST_INT); |
5081 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63)); | |
5082 | return; | |
e5965947 | 5083 | case 'L': |
ecf2283d | 5084 | gcc_assert (GET_CODE (x) == CONST_INT); |
5085 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31)); | |
5086 | return; | |
3a16146d | 5087 | case 'O': |
ecf2283d | 5088 | gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0); |
5089 | fprintf (file, "%d", exact_log2 (INTVAL (x))); | |
5090 | return; | |
5e3c5739 | 5091 | case 'p': |
ecf2283d | 5092 | gcc_assert (GET_CODE (x) == CONST_INT); |
5093 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63)); | |
5094 | return; | |
e5965947 | 5095 | case 'P': |
ecf2283d | 5096 | gcc_assert (GET_CODE (x) == CONST_INT); |
5097 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31)); | |
5098 | return; | |
c8975385 | 5099 | case 'I': |
5100 | if (GET_CODE (x) == CONST_INT) | |
5101 | fputs ("i", file); | |
5102 | return; | |
87ad11b0 | 5103 | case 'M': |
27ef382d | 5104 | case 'F': |
87ad11b0 | 5105 | switch (GET_CODE (XEXP (x, 0))) |
5106 | { | |
5107 | case PRE_DEC: | |
5108 | case PRE_INC: | |
e4065f95 | 5109 | if (ASSEMBLER_DIALECT == 0) |
5110 | fputs ("s,mb", file); | |
5111 | else | |
5112 | fputs (",mb", file); | |
87ad11b0 | 5113 | break; |
5114 | case POST_DEC: | |
5115 | case POST_INC: | |
e4065f95 | 5116 | if (ASSEMBLER_DIALECT == 0) |
5117 | fputs ("s,ma", file); | |
5118 | else | |
5119 | fputs (",ma", file); | |
87ad11b0 | 5120 | break; |
27ef382d | 5121 | case PLUS: |
dbd3d89d | 5122 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5123 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5124 | { | |
5125 | if (ASSEMBLER_DIALECT == 0) | |
5126 | fputs ("x", file); | |
5127 | } | |
5128 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
5129 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) | |
e4065f95 | 5130 | { |
5131 | if (ASSEMBLER_DIALECT == 0) | |
5132 | fputs ("x,s", file); | |
5133 | else | |
5134 | fputs (",s", file); | |
5135 | } | |
5136 | else if (code == 'F' && ASSEMBLER_DIALECT == 0) | |
27ef382d | 5137 | fputs ("s", file); |
87ad11b0 | 5138 | break; |
5139 | default: | |
e4065f95 | 5140 | if (code == 'F' && ASSEMBLER_DIALECT == 0) |
27ef382d | 5141 | fputs ("s", file); |
87ad11b0 | 5142 | break; |
5143 | } | |
5144 | return; | |
5145 | case 'G': | |
f9333726 | 5146 | output_global_address (file, x, 0); |
5147 | return; | |
5148 | case 'H': | |
5149 | output_global_address (file, x, 1); | |
87ad11b0 | 5150 | return; |
5151 | case 0: /* Don't do anything special */ | |
5152 | break; | |
42faba01 | 5153 | case 'Z': |
5154 | { | |
5155 | unsigned op[3]; | |
fb22aedc | 5156 | compute_zdepwi_operands (INTVAL (x), op); |
42faba01 | 5157 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); |
5158 | return; | |
5159 | } | |
5e3c5739 | 5160 | case 'z': |
5161 | { | |
5162 | unsigned op[3]; | |
5163 | compute_zdepdi_operands (INTVAL (x), op); | |
5164 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); | |
5165 | return; | |
5166 | } | |
c9cc98e1 | 5167 | case 'c': |
5168 | /* We can get here from a .vtable_inherit due to our | |
5169 | CONSTANT_ADDRESS_P rejecting perfectly good constant | |
5170 | addresses. */ | |
5171 | break; | |
87ad11b0 | 5172 | default: |
ecf2283d | 5173 | gcc_unreachable (); |
87ad11b0 | 5174 | } |
5175 | if (GET_CODE (x) == REG) | |
df0651dc | 5176 | { |
35661368 | 5177 | fputs (reg_names [REGNO (x)], file); |
5e3c5739 | 5178 | if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4) |
5179 | { | |
5180 | fputs ("R", file); | |
5181 | return; | |
5182 | } | |
5183 | if (FP_REG_P (x) | |
5184 | && GET_MODE_SIZE (GET_MODE (x)) <= 4 | |
5185 | && (REGNO (x) & 1) == 0) | |
35661368 | 5186 | fputs ("L", file); |
df0651dc | 5187 | } |
87ad11b0 | 5188 | else if (GET_CODE (x) == MEM) |
5189 | { | |
5190 | int size = GET_MODE_SIZE (GET_MODE (x)); | |
f7dff90d | 5191 | rtx base = NULL_RTX; |
87ad11b0 | 5192 | switch (GET_CODE (XEXP (x, 0))) |
5193 | { | |
5194 | case PRE_DEC: | |
5195 | case POST_DEC: | |
5e3c5739 | 5196 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 5197 | fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5198 | break; |
5199 | case PRE_INC: | |
5200 | case POST_INC: | |
5e3c5739 | 5201 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 5202 | fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5203 | break; |
dbd3d89d | 5204 | case PLUS: |
5205 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT) | |
34940871 | 5206 | fprintf (file, "%s(%s)", |
27ef382d | 5207 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))], |
5208 | reg_names [REGNO (XEXP (XEXP (x, 0), 1))]); | |
dbd3d89d | 5209 | else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) |
34940871 | 5210 | fprintf (file, "%s(%s)", |
27ef382d | 5211 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))], |
5212 | reg_names [REGNO (XEXP (XEXP (x, 0), 0))]); | |
dbd3d89d | 5213 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5214 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5215 | { | |
5216 | /* Because the REG_POINTER flag can get lost during reload, | |
5217 | GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the | |
5218 | index and base registers in the combined move patterns. */ | |
5219 | rtx base = XEXP (XEXP (x, 0), 1); | |
5220 | rtx index = XEXP (XEXP (x, 0), 0); | |
5221 | ||
5222 | fprintf (file, "%s(%s)", | |
5223 | reg_names [REGNO (index)], reg_names [REGNO (base)]); | |
5224 | } | |
27ef382d | 5225 | else |
5226 | output_address (XEXP (x, 0)); | |
87ad11b0 | 5227 | break; |
dbd3d89d | 5228 | default: |
5229 | output_address (XEXP (x, 0)); | |
5230 | break; | |
87ad11b0 | 5231 | } |
5232 | } | |
87ad11b0 | 5233 | else |
5234 | output_addr_const (file, x); | |
5235 | } | |
5236 | ||
6dc3b0d9 | 5237 | /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */ |
87ad11b0 | 5238 | |
5239 | void | |
5c1d8983 | 5240 | output_global_address (FILE *file, rtx x, int round_constant) |
87ad11b0 | 5241 | { |
2ee034bc | 5242 | |
5243 | /* Imagine (high (const (plus ...))). */ | |
5244 | if (GET_CODE (x) == HIGH) | |
5245 | x = XEXP (x, 0); | |
5246 | ||
611a88e1 | 5247 | if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode)) |
5f43b4f6 | 5248 | output_addr_const (file, x); |
b4a7bf10 | 5249 | else if (GET_CODE (x) == SYMBOL_REF && !flag_pic) |
87ad11b0 | 5250 | { |
5f43b4f6 | 5251 | output_addr_const (file, x); |
9c0ac0fd | 5252 | fputs ("-$global$", file); |
87ad11b0 | 5253 | } |
5254 | else if (GET_CODE (x) == CONST) | |
5255 | { | |
611a88e1 | 5256 | const char *sep = ""; |
87ad11b0 | 5257 | int offset = 0; /* assembler wants -$global$ at end */ |
33ae0dba | 5258 | rtx base = NULL_RTX; |
6d36483b | 5259 | |
ecf2283d | 5260 | switch (GET_CODE (XEXP (XEXP (x, 0), 0))) |
87ad11b0 | 5261 | { |
ecf2283d | 5262 | case SYMBOL_REF: |
87ad11b0 | 5263 | base = XEXP (XEXP (x, 0), 0); |
5264 | output_addr_const (file, base); | |
ecf2283d | 5265 | break; |
5266 | case CONST_INT: | |
5267 | offset = INTVAL (XEXP (XEXP (x, 0), 0)); | |
5268 | break; | |
5269 | default: | |
5270 | gcc_unreachable (); | |
87ad11b0 | 5271 | } |
87ad11b0 | 5272 | |
ecf2283d | 5273 | switch (GET_CODE (XEXP (XEXP (x, 0), 1))) |
87ad11b0 | 5274 | { |
ecf2283d | 5275 | case SYMBOL_REF: |
87ad11b0 | 5276 | base = XEXP (XEXP (x, 0), 1); |
5277 | output_addr_const (file, base); | |
ecf2283d | 5278 | break; |
5279 | case CONST_INT: | |
5280 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
5281 | break; | |
5282 | default: | |
5283 | gcc_unreachable (); | |
87ad11b0 | 5284 | } |
87ad11b0 | 5285 | |
f9333726 | 5286 | /* How bogus. The compiler is apparently responsible for |
5287 | rounding the constant if it uses an LR field selector. | |
5288 | ||
5289 | The linker and/or assembler seem a better place since | |
5290 | they have to do this kind of thing already. | |
5291 | ||
5292 | If we fail to do this, HP's optimizing linker may eliminate | |
5293 | an addil, but not update the ldw/stw/ldo instruction that | |
5294 | uses the result of the addil. */ | |
5295 | if (round_constant) | |
5296 | offset = ((offset + 0x1000) & ~0x1fff); | |
5297 | ||
ecf2283d | 5298 | switch (GET_CODE (XEXP (x, 0))) |
87ad11b0 | 5299 | { |
ecf2283d | 5300 | case PLUS: |
87ad11b0 | 5301 | if (offset < 0) |
5302 | { | |
5303 | offset = -offset; | |
5304 | sep = "-"; | |
5305 | } | |
5306 | else | |
5307 | sep = "+"; | |
ecf2283d | 5308 | break; |
5309 | ||
5310 | case MINUS: | |
5311 | gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF); | |
5312 | sep = "-"; | |
5313 | break; | |
87ad11b0 | 5314 | |
ecf2283d | 5315 | default: |
5316 | gcc_unreachable (); | |
5317 | } | |
5318 | ||
611a88e1 | 5319 | if (!read_only_operand (base, VOIDmode) && !flag_pic) |
9c0ac0fd | 5320 | fputs ("-$global$", file); |
f9333726 | 5321 | if (offset) |
ea52c577 | 5322 | fprintf (file, "%s%d", sep, offset); |
87ad11b0 | 5323 | } |
5324 | else | |
5325 | output_addr_const (file, x); | |
5326 | } | |
5327 | ||
92c473b8 | 5328 | /* Output boilerplate text to appear at the beginning of the file. |
5329 | There are several possible versions. */ | |
5330 | #define aputs(x) fputs(x, asm_out_file) | |
5331 | static inline void | |
5c1d8983 | 5332 | pa_file_start_level (void) |
92c473b8 | 5333 | { |
5334 | if (TARGET_64BIT) | |
5335 | aputs ("\t.LEVEL 2.0w\n"); | |
5336 | else if (TARGET_PA_20) | |
5337 | aputs ("\t.LEVEL 2.0\n"); | |
5338 | else if (TARGET_PA_11) | |
5339 | aputs ("\t.LEVEL 1.1\n"); | |
5340 | else | |
5341 | aputs ("\t.LEVEL 1.0\n"); | |
5342 | } | |
5343 | ||
5344 | static inline void | |
5c1d8983 | 5345 | pa_file_start_space (int sortspace) |
92c473b8 | 5346 | { |
5347 | aputs ("\t.SPACE $PRIVATE$"); | |
5348 | if (sortspace) | |
5349 | aputs (",SORT=16"); | |
5350 | aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31" | |
5351 | "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82" | |
5352 | "\n\t.SPACE $TEXT$"); | |
5353 | if (sortspace) | |
5354 | aputs (",SORT=8"); | |
5355 | aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44" | |
5356 | "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n"); | |
5357 | } | |
5358 | ||
5359 | static inline void | |
5c1d8983 | 5360 | pa_file_start_file (int want_version) |
92c473b8 | 5361 | { |
5362 | if (write_symbols != NO_DEBUG) | |
5363 | { | |
5364 | output_file_directive (asm_out_file, main_input_filename); | |
5365 | if (want_version) | |
5366 | aputs ("\t.version\t\"01.01\"\n"); | |
5367 | } | |
5368 | } | |
5369 | ||
5370 | static inline void | |
5c1d8983 | 5371 | pa_file_start_mcount (const char *aswhat) |
92c473b8 | 5372 | { |
5373 | if (profile_flag) | |
5374 | fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat); | |
5375 | } | |
5376 | ||
5377 | static void | |
5c1d8983 | 5378 | pa_elf_file_start (void) |
92c473b8 | 5379 | { |
5380 | pa_file_start_level (); | |
5381 | pa_file_start_mcount ("ENTRY"); | |
5382 | pa_file_start_file (0); | |
5383 | } | |
5384 | ||
5385 | static void | |
5c1d8983 | 5386 | pa_som_file_start (void) |
92c473b8 | 5387 | { |
5388 | pa_file_start_level (); | |
5389 | pa_file_start_space (0); | |
5390 | aputs ("\t.IMPORT $global$,DATA\n" | |
5391 | "\t.IMPORT $$dyncall,MILLICODE\n"); | |
5392 | pa_file_start_mcount ("CODE"); | |
5393 | pa_file_start_file (0); | |
5394 | } | |
5395 | ||
5396 | static void | |
5c1d8983 | 5397 | pa_linux_file_start (void) |
92c473b8 | 5398 | { |
5399 | pa_file_start_file (1); | |
5400 | pa_file_start_level (); | |
5401 | pa_file_start_mcount ("CODE"); | |
5402 | } | |
5403 | ||
5404 | static void | |
5c1d8983 | 5405 | pa_hpux64_gas_file_start (void) |
92c473b8 | 5406 | { |
5407 | pa_file_start_level (); | |
5408 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
5409 | if (profile_flag) | |
5410 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function"); | |
5411 | #endif | |
5412 | pa_file_start_file (1); | |
5413 | } | |
5414 | ||
5415 | static void | |
5c1d8983 | 5416 | pa_hpux64_hpas_file_start (void) |
92c473b8 | 5417 | { |
5418 | pa_file_start_level (); | |
5419 | pa_file_start_space (1); | |
5420 | pa_file_start_mcount ("CODE"); | |
5421 | pa_file_start_file (0); | |
5422 | } | |
5423 | #undef aputs | |
5424 | ||
4e75439e | 5425 | /* Search the deferred plabel list for SYMBOL and return its internal |
5426 | label. If an entry for SYMBOL is not found, a new entry is created. */ | |
5427 | ||
5428 | rtx | |
5429 | get_deferred_plabel (rtx symbol) | |
ece88821 | 5430 | { |
5f43b4f6 | 5431 | const char *fname = XSTR (symbol, 0); |
ece88821 | 5432 | size_t i; |
5433 | ||
5434 | /* See if we have already put this function on the list of deferred | |
5435 | plabels. This list is generally small, so a liner search is not | |
5436 | too ugly. If it proves too slow replace it with something faster. */ | |
5437 | for (i = 0; i < n_deferred_plabels; i++) | |
5f43b4f6 | 5438 | if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0) |
ece88821 | 5439 | break; |
5440 | ||
5441 | /* If the deferred plabel list is empty, or this entry was not found | |
5442 | on the list, create a new entry on the list. */ | |
5443 | if (deferred_plabels == NULL || i == n_deferred_plabels) | |
5444 | { | |
5f43b4f6 | 5445 | tree id; |
5446 | ||
ece88821 | 5447 | if (deferred_plabels == 0) |
ba72912a | 5448 | deferred_plabels = ggc_alloc_deferred_plabel (); |
ece88821 | 5449 | else |
ba72912a | 5450 | deferred_plabels = GGC_RESIZEVEC (struct deferred_plabel, |
5451 | deferred_plabels, | |
5452 | n_deferred_plabels + 1); | |
ece88821 | 5453 | |
5454 | i = n_deferred_plabels++; | |
5455 | deferred_plabels[i].internal_label = gen_label_rtx (); | |
5f43b4f6 | 5456 | deferred_plabels[i].symbol = symbol; |
ece88821 | 5457 | |
5f43b4f6 | 5458 | /* Gross. We have just implicitly taken the address of this |
5459 | function. Mark it in the same manner as assemble_name. */ | |
5460 | id = maybe_get_identifier (targetm.strip_name_encoding (fname)); | |
5461 | if (id) | |
5462 | mark_referenced (id); | |
ece88821 | 5463 | } |
5464 | ||
4e75439e | 5465 | return deferred_plabels[i].internal_label; |
ece88821 | 5466 | } |
5467 | ||
f6940372 | 5468 | static void |
5c1d8983 | 5469 | output_deferred_plabels (void) |
5cc6b2bc | 5470 | { |
e11bd7e5 | 5471 | size_t i; |
78962d38 | 5472 | |
5473 | /* If we have some deferred plabels, then we need to switch into the | |
5474 | data or readonly data section, and align it to a 4 byte boundary | |
191ec5a2 | 5475 | before outputting the deferred plabels. */ |
5cc6b2bc | 5476 | if (n_deferred_plabels) |
5477 | { | |
78962d38 | 5478 | switch_to_section (flag_pic ? data_section : readonly_data_section); |
f6940372 | 5479 | ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2); |
5cc6b2bc | 5480 | } |
5481 | ||
5482 | /* Now output the deferred plabels. */ | |
5483 | for (i = 0; i < n_deferred_plabels; i++) | |
5484 | { | |
c5559ed4 | 5485 | targetm.asm_out.internal_label (asm_out_file, "L", |
f6940372 | 5486 | CODE_LABEL_NUMBER (deferred_plabels[i].internal_label)); |
5f43b4f6 | 5487 | assemble_integer (deferred_plabels[i].symbol, |
b70ea764 | 5488 | TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1); |
5cc6b2bc | 5489 | } |
5490 | } | |
5491 | ||
f2f543a3 | 5492 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
5493 | /* Initialize optabs to point to HPUX long double emulation routines. */ | |
5494 | static void | |
5495 | pa_hpux_init_libfuncs (void) | |
5496 | { | |
5497 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
5498 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
5499 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
5500 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
5501 | set_optab_libfunc (smin_optab, TFmode, "_U_Qmin"); | |
5502 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
5503 | set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt"); | |
5504 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
5505 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
5506 | ||
c88a6ebd | 5507 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); |
5508 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
5509 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
5510 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
5511 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
5512 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
6b27baea | 5513 | set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord"); |
f2f543a3 | 5514 | |
a7cc195f | 5515 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); |
5516 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
5517 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
5518 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
5519 | ||
5520 | set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT | |
5521 | ? "__U_Qfcnvfxt_quad_to_sgl" | |
5522 | : "_U_Qfcnvfxt_quad_to_sgl"); | |
5523 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl"); | |
5524 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl"); | |
5525 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl"); | |
5526 | ||
5527 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad"); | |
5528 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad"); | |
3e647485 | 5529 | set_conv_libfunc (ufloat_optab, TFmode, SImode, "_U_Qfcnvxf_usgl_to_quad"); |
5530 | set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxf_udbl_to_quad"); | |
f2f543a3 | 5531 | } |
5532 | #endif | |
5533 | ||
87ad11b0 | 5534 | /* HP's millicode routines mean something special to the assembler. |
5535 | Keep track of which ones we have used. */ | |
5536 | ||
c2271c34 | 5537 | enum millicodes { remI, remU, divI, divU, mulI, end1000 }; |
5c1d8983 | 5538 | static void import_milli (enum millicodes); |
ea52c577 | 5539 | static char imported[(int) end1000]; |
c2271c34 | 5540 | static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"}; |
e99c3a1d | 5541 | static const char import_string[] = ".IMPORT $$....,MILLICODE"; |
87ad11b0 | 5542 | #define MILLI_START 10 |
5543 | ||
57ed30e5 | 5544 | static void |
5c1d8983 | 5545 | import_milli (enum millicodes code) |
87ad11b0 | 5546 | { |
5547 | char str[sizeof (import_string)]; | |
6d36483b | 5548 | |
ea52c577 | 5549 | if (!imported[(int) code]) |
87ad11b0 | 5550 | { |
ea52c577 | 5551 | imported[(int) code] = 1; |
87ad11b0 | 5552 | strcpy (str, import_string); |
ea52c577 | 5553 | strncpy (str + MILLI_START, milli_names[(int) code], 4); |
87ad11b0 | 5554 | output_asm_insn (str, 0); |
5555 | } | |
5556 | } | |
5557 | ||
6d36483b | 5558 | /* The register constraints have put the operands and return value in |
6dc3b0d9 | 5559 | the proper registers. */ |
87ad11b0 | 5560 | |
611a88e1 | 5561 | const char * |
5c1d8983 | 5562 | output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn) |
87ad11b0 | 5563 | { |
d178f670 | 5564 | import_milli (mulI); |
440c23df | 5565 | return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI")); |
87ad11b0 | 5566 | } |
5567 | ||
6dc3b0d9 | 5568 | /* Emit the rtl for doing a division by a constant. */ |
87ad11b0 | 5569 | |
d178f670 | 5570 | /* Do magic division millicodes exist for this value? */ |
913de4b4 | 5571 | const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1}; |
87ad11b0 | 5572 | |
6d36483b | 5573 | /* We'll use an array to keep track of the magic millicodes and |
87ad11b0 | 5574 | whether or not we've used them already. [n][0] is signed, [n][1] is |
6dc3b0d9 | 5575 | unsigned. */ |
87ad11b0 | 5576 | |
87ad11b0 | 5577 | static int div_milli[16][2]; |
5578 | ||
87ad11b0 | 5579 | int |
5c1d8983 | 5580 | emit_hpdiv_const (rtx *operands, int unsignedp) |
87ad11b0 | 5581 | { |
5582 | if (GET_CODE (operands[2]) == CONST_INT | |
5583 | && INTVAL (operands[2]) > 0 | |
5584 | && INTVAL (operands[2]) < 16 | |
5585 | && magic_milli[INTVAL (operands[2])]) | |
5586 | { | |
2013ddf6 | 5587 | rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31); |
5588 | ||
ad851752 | 5589 | emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]); |
87ad11b0 | 5590 | emit |
75b1a41a | 5591 | (gen_rtx_PARALLEL |
5592 | (VOIDmode, | |
c2078db8 | 5593 | gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29), |
ad851752 | 5594 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, |
5595 | SImode, | |
5596 | gen_rtx_REG (SImode, 26), | |
5597 | operands[2])), | |
c2078db8 | 5598 | gen_rtx_CLOBBER (VOIDmode, operands[4]), |
ad851752 | 5599 | gen_rtx_CLOBBER (VOIDmode, operands[3]), |
5600 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)), | |
5601 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)), | |
2013ddf6 | 5602 | gen_rtx_CLOBBER (VOIDmode, ret)))); |
ad851752 | 5603 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 29)); |
87ad11b0 | 5604 | return 1; |
5605 | } | |
5606 | return 0; | |
5607 | } | |
5608 | ||
611a88e1 | 5609 | const char * |
5c1d8983 | 5610 | output_div_insn (rtx *operands, int unsignedp, rtx insn) |
87ad11b0 | 5611 | { |
5612 | int divisor; | |
6d36483b | 5613 | |
5614 | /* If the divisor is a constant, try to use one of the special | |
87ad11b0 | 5615 | opcodes .*/ |
5616 | if (GET_CODE (operands[0]) == CONST_INT) | |
5617 | { | |
d6686e21 | 5618 | static char buf[100]; |
87ad11b0 | 5619 | divisor = INTVAL (operands[0]); |
5620 | if (!div_milli[divisor][unsignedp]) | |
5621 | { | |
d6686e21 | 5622 | div_milli[divisor][unsignedp] = 1; |
87ad11b0 | 5623 | if (unsignedp) |
5624 | output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands); | |
5625 | else | |
5626 | output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands); | |
87ad11b0 | 5627 | } |
5628 | if (unsignedp) | |
d6686e21 | 5629 | { |
4840a03a | 5630 | sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC, |
5631 | INTVAL (operands[0])); | |
c7a4e712 | 5632 | return output_millicode_call (insn, |
ad851752 | 5633 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5634 | } |
5635 | else | |
5636 | { | |
4840a03a | 5637 | sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC, |
5638 | INTVAL (operands[0])); | |
c7a4e712 | 5639 | return output_millicode_call (insn, |
ad851752 | 5640 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5641 | } |
87ad11b0 | 5642 | } |
6dc3b0d9 | 5643 | /* Divisor isn't a special constant. */ |
87ad11b0 | 5644 | else |
5645 | { | |
5646 | if (unsignedp) | |
5647 | { | |
5648 | import_milli (divU); | |
c7a4e712 | 5649 | return output_millicode_call (insn, |
ad851752 | 5650 | gen_rtx_SYMBOL_REF (SImode, "$$divU")); |
87ad11b0 | 5651 | } |
5652 | else | |
5653 | { | |
5654 | import_milli (divI); | |
c7a4e712 | 5655 | return output_millicode_call (insn, |
ad851752 | 5656 | gen_rtx_SYMBOL_REF (SImode, "$$divI")); |
87ad11b0 | 5657 | } |
5658 | } | |
5659 | } | |
5660 | ||
6dc3b0d9 | 5661 | /* Output a $$rem millicode to do mod. */ |
87ad11b0 | 5662 | |
611a88e1 | 5663 | const char * |
5c1d8983 | 5664 | output_mod_insn (int unsignedp, rtx insn) |
87ad11b0 | 5665 | { |
5666 | if (unsignedp) | |
5667 | { | |
5668 | import_milli (remU); | |
c7a4e712 | 5669 | return output_millicode_call (insn, |
ad851752 | 5670 | gen_rtx_SYMBOL_REF (SImode, "$$remU")); |
87ad11b0 | 5671 | } |
5672 | else | |
5673 | { | |
5674 | import_milli (remI); | |
c7a4e712 | 5675 | return output_millicode_call (insn, |
ad851752 | 5676 | gen_rtx_SYMBOL_REF (SImode, "$$remI")); |
87ad11b0 | 5677 | } |
5678 | } | |
5679 | ||
5680 | void | |
5c1d8983 | 5681 | output_arg_descriptor (rtx call_insn) |
87ad11b0 | 5682 | { |
611a88e1 | 5683 | const char *arg_regs[4]; |
87ad11b0 | 5684 | enum machine_mode arg_mode; |
df0651dc | 5685 | rtx link; |
87ad11b0 | 5686 | int i, output_flag = 0; |
5687 | int regno; | |
6d36483b | 5688 | |
5e3c5739 | 5689 | /* We neither need nor want argument location descriptors for the |
5d0619cc | 5690 | 64bit runtime environment or the ELF32 environment. */ |
5691 | if (TARGET_64BIT || TARGET_ELF32) | |
5e3c5739 | 5692 | return; |
5693 | ||
87ad11b0 | 5694 | for (i = 0; i < 4; i++) |
5695 | arg_regs[i] = 0; | |
5696 | ||
738176ab | 5697 | /* Specify explicitly that no argument relocations should take place |
5698 | if using the portable runtime calling conventions. */ | |
5699 | if (TARGET_PORTABLE_RUNTIME) | |
5700 | { | |
9c0ac0fd | 5701 | fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n", |
5702 | asm_out_file); | |
738176ab | 5703 | return; |
5704 | } | |
5705 | ||
ecf2283d | 5706 | gcc_assert (GET_CODE (call_insn) == CALL_INSN); |
5707 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); | |
5708 | link; link = XEXP (link, 1)) | |
87ad11b0 | 5709 | { |
df0651dc | 5710 | rtx use = XEXP (link, 0); |
c12afafd | 5711 | |
df0651dc | 5712 | if (! (GET_CODE (use) == USE |
5713 | && GET_CODE (XEXP (use, 0)) == REG | |
5714 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
c12afafd | 5715 | continue; |
5716 | ||
df0651dc | 5717 | arg_mode = GET_MODE (XEXP (use, 0)); |
5718 | regno = REGNO (XEXP (use, 0)); | |
87ad11b0 | 5719 | if (regno >= 23 && regno <= 26) |
372ef038 | 5720 | { |
5721 | arg_regs[26 - regno] = "GR"; | |
5722 | if (arg_mode == DImode) | |
5723 | arg_regs[25 - regno] = "GR"; | |
5724 | } | |
df0651dc | 5725 | else if (regno >= 32 && regno <= 39) |
87ad11b0 | 5726 | { |
5727 | if (arg_mode == SFmode) | |
df0651dc | 5728 | arg_regs[(regno - 32) / 2] = "FR"; |
e6ba640e | 5729 | else |
87ad11b0 | 5730 | { |
eeec72c0 | 5731 | #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED |
df0651dc | 5732 | arg_regs[(regno - 34) / 2] = "FR"; |
5733 | arg_regs[(regno - 34) / 2 + 1] = "FU"; | |
87ad11b0 | 5734 | #else |
df0651dc | 5735 | arg_regs[(regno - 34) / 2] = "FU"; |
5736 | arg_regs[(regno - 34) / 2 + 1] = "FR"; | |
87ad11b0 | 5737 | #endif |
5738 | } | |
87ad11b0 | 5739 | } |
5740 | } | |
5741 | fputs ("\t.CALL ", asm_out_file); | |
5742 | for (i = 0; i < 4; i++) | |
5743 | { | |
5744 | if (arg_regs[i]) | |
5745 | { | |
5746 | if (output_flag++) | |
5747 | fputc (',', asm_out_file); | |
5748 | fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]); | |
5749 | } | |
5750 | } | |
5751 | fputc ('\n', asm_out_file); | |
5752 | } | |
5753 | \f | |
964229b7 | 5754 | static reg_class_t |
5755 | pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, | |
5655a0e5 | 5756 | enum machine_mode mode, secondary_reload_info *sri) |
5757 | { | |
cca0fae1 | 5758 | int is_symbolic, regno; |
964229b7 | 5759 | enum reg_class rclass = (enum reg_class) rclass_i; |
9c0ac0fd | 5760 | |
5655a0e5 | 5761 | /* Handle the easy stuff first. */ |
8deb3959 | 5762 | if (rclass == R1_REGS) |
5655a0e5 | 5763 | return NO_REGS; |
9c0ac0fd | 5764 | |
5655a0e5 | 5765 | if (REG_P (x)) |
5766 | { | |
5767 | regno = REGNO (x); | |
8deb3959 | 5768 | if (rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER) |
5655a0e5 | 5769 | return NO_REGS; |
5770 | } | |
cca0fae1 | 5771 | else |
5772 | regno = -1; | |
87ad11b0 | 5773 | |
5655a0e5 | 5774 | /* If we have something like (mem (mem (...)), we can safely assume the |
5775 | inner MEM will end up in a general register after reloading, so there's | |
5776 | no need for a secondary reload. */ | |
5777 | if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM) | |
5778 | return NO_REGS; | |
87ad11b0 | 5779 | |
b4a7bf10 | 5780 | /* Trying to load a constant into a FP register during PIC code |
5655a0e5 | 5781 | generation requires %r1 as a scratch register. */ |
fc44315f | 5782 | if (flag_pic |
9c0b6987 | 5783 | && (mode == SImode || mode == DImode) |
8deb3959 | 5784 | && FP_REG_CLASS_P (rclass) |
5655a0e5 | 5785 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
9c0ac0fd | 5786 | { |
5655a0e5 | 5787 | sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1 |
5788 | : CODE_FOR_reload_indi_r1); | |
5789 | return NO_REGS; | |
9c0ac0fd | 5790 | } |
9c0ac0fd | 5791 | |
5655a0e5 | 5792 | /* Profiling showed the PA port spends about 1.3% of its compilation |
5793 | time in true_regnum from calls inside pa_secondary_reload_class. */ | |
5794 | if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG) | |
5795 | regno = true_regnum (x); | |
76a0ced5 | 5796 | |
7050ff73 | 5797 | /* In order to allow 14-bit displacements in integer loads and stores, |
5798 | we need to prevent reload from generating out of range integer mode | |
5799 | loads and stores to the floating point registers. Previously, we | |
5800 | used to call for a secondary reload and have emit_move_sequence() | |
5801 | fix the instruction sequence. However, reload occasionally wouldn't | |
5802 | generate the reload and we would end up with an invalid REG+D memory | |
5803 | address. So, now we use an intermediate general register for most | |
5804 | memory loads and stores. */ | |
5805 | if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1) | |
5806 | && GET_MODE_CLASS (mode) == MODE_INT | |
8deb3959 | 5807 | && FP_REG_CLASS_P (rclass)) |
7050ff73 | 5808 | { |
5809 | /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check | |
5810 | the secondary reload needed for a pseudo. It never passes a | |
5811 | REG+D address. */ | |
5812 | if (GET_CODE (x) == MEM) | |
5813 | { | |
5814 | x = XEXP (x, 0); | |
5815 | ||
5816 | /* We don't need an intermediate for indexed and LO_SUM DLT | |
5817 | memory addresses. When INT14_OK_STRICT is true, it might | |
5818 | appear that we could directly allow register indirect | |
5819 | memory addresses. However, this doesn't work because we | |
5820 | don't support SUBREGs in floating-point register copies | |
5821 | and reload doesn't tell us when it's going to use a SUBREG. */ | |
5822 | if (IS_INDEX_ADDR_P (x) | |
5823 | || IS_LO_SUM_DLT_ADDR_P (x)) | |
5824 | return NO_REGS; | |
5825 | ||
5826 | /* Otherwise, we need an intermediate general register. */ | |
5827 | return GENERAL_REGS; | |
5828 | } | |
5829 | ||
5830 | /* Request a secondary reload with a general scratch register | |
5831 | for everthing else. ??? Could symbolic operands be handled | |
5832 | directly when generating non-pic PA 2.0 code? */ | |
6b531606 | 5833 | sri->icode = (in_p |
5834 | ? direct_optab_handler (reload_in_optab, mode) | |
5835 | : direct_optab_handler (reload_out_optab, mode)); | |
7050ff73 | 5836 | return NO_REGS; |
5837 | } | |
5838 | ||
5839 | /* We need a secondary register (GPR) for copies between the SAR | |
5840 | and anything other than a general register. */ | |
8deb3959 | 5841 | if (rclass == SHIFT_REGS && (regno <= 0 || regno >= 32)) |
5655a0e5 | 5842 | { |
6b531606 | 5843 | sri->icode = (in_p |
5844 | ? direct_optab_handler (reload_in_optab, mode) | |
5845 | : direct_optab_handler (reload_out_optab, mode)); | |
5655a0e5 | 5846 | return NO_REGS; |
5847 | } | |
d2c1d63d | 5848 | |
7c4b32f3 | 5849 | /* A SAR<->FP register copy requires a secondary register (GPR) as |
5850 | well as secondary memory. */ | |
5851 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
7050ff73 | 5852 | && (REGNO_REG_CLASS (regno) == SHIFT_REGS |
8deb3959 | 5853 | && FP_REG_CLASS_P (rclass))) |
5655a0e5 | 5854 | { |
6b531606 | 5855 | sri->icode = (in_p |
5856 | ? direct_optab_handler (reload_in_optab, mode) | |
5857 | : direct_optab_handler (reload_out_optab, mode)); | |
5655a0e5 | 5858 | return NO_REGS; |
5859 | } | |
7c4b32f3 | 5860 | |
5655a0e5 | 5861 | /* Secondary reloads of symbolic operands require %r1 as a scratch |
7050ff73 | 5862 | register when we're generating PIC code and when the operand isn't |
5655a0e5 | 5863 | readonly. */ |
5864 | if (GET_CODE (x) == HIGH) | |
5865 | x = XEXP (x, 0); | |
2ee034bc | 5866 | |
9c0ac0fd | 5867 | /* Profiling has showed GCC spends about 2.6% of its compilation |
51149d85 | 5868 | time in symbolic_operand from calls inside pa_secondary_reload_class. |
5655a0e5 | 5869 | So, we use an inline copy to avoid useless work. */ |
5870 | switch (GET_CODE (x)) | |
9c0ac0fd | 5871 | { |
5655a0e5 | 5872 | rtx op; |
9c0ac0fd | 5873 | |
5874 | case SYMBOL_REF: | |
5655a0e5 | 5875 | is_symbolic = !SYMBOL_REF_TLS_MODEL (x); |
5876 | break; | |
9c0ac0fd | 5877 | case LABEL_REF: |
5878 | is_symbolic = 1; | |
5879 | break; | |
5880 | case CONST: | |
5655a0e5 | 5881 | op = XEXP (x, 0); |
7fd14dc3 | 5882 | is_symbolic = (GET_CODE (op) == PLUS |
5883 | && ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
5884 | && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0))) | |
5885 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
5655a0e5 | 5886 | && GET_CODE (XEXP (op, 1)) == CONST_INT); |
9c0ac0fd | 5887 | break; |
5888 | default: | |
5889 | is_symbolic = 0; | |
5890 | break; | |
5891 | } | |
9840d99d | 5892 | |
5655a0e5 | 5893 | if (is_symbolic && (flag_pic || !read_only_operand (x, VOIDmode))) |
5894 | { | |
5895 | gcc_assert (mode == SImode || mode == DImode); | |
5896 | sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1 | |
5897 | : CODE_FOR_reload_indi_r1); | |
5898 | } | |
2ee034bc | 5899 | |
d2c1d63d | 5900 | return NO_REGS; |
87ad11b0 | 5901 | } |
5902 | ||
df6b92e4 | 5903 | /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer |
5904 | is only marked as live on entry by df-scan when it is a fixed | |
5905 | register. It isn't a fixed register in the 64-bit runtime, | |
5906 | so we need to mark it here. */ | |
5907 | ||
5908 | static void | |
5909 | pa_extra_live_on_entry (bitmap regs) | |
5910 | { | |
5911 | if (TARGET_64BIT) | |
5912 | bitmap_set_bit (regs, ARG_POINTER_REGNUM); | |
5913 | } | |
5914 | ||
5915 | /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile | |
5916 | to prevent it from being deleted. */ | |
5917 | ||
5918 | rtx | |
5919 | pa_eh_return_handler_rtx (void) | |
5920 | { | |
5921 | rtx tmp; | |
5922 | ||
5923 | tmp = gen_rtx_PLUS (word_mode, frame_pointer_rtx, | |
5924 | TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)); | |
5925 | tmp = gen_rtx_MEM (word_mode, tmp); | |
5926 | tmp->volatil = 1; | |
5927 | return tmp; | |
5928 | } | |
5929 | ||
b981d932 | 5930 | /* In the 32-bit runtime, arguments larger than eight bytes are passed |
5931 | by invisible reference. As a GCC extension, we also pass anything | |
5932 | with a zero or variable size by reference. | |
5933 | ||
5934 | The 64-bit runtime does not describe passing any types by invisible | |
5935 | reference. The internals of GCC can't currently handle passing | |
5936 | empty structures, and zero or variable length arrays when they are | |
5937 | not passed entirely on the stack or by reference. Thus, as a GCC | |
5938 | extension, we pass these types by reference. The HP compiler doesn't | |
5939 | support these types, so hopefully there shouldn't be any compatibility | |
5940 | issues. This may have to be revisited when HP releases a C99 compiler | |
5941 | or updates the ABI. */ | |
5942 | ||
5943 | static bool | |
5944 | pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, | |
fb80456a | 5945 | enum machine_mode mode, const_tree type, |
b981d932 | 5946 | bool named ATTRIBUTE_UNUSED) |
5947 | { | |
5948 | HOST_WIDE_INT size; | |
5949 | ||
5950 | if (type) | |
5951 | size = int_size_in_bytes (type); | |
5952 | else | |
5953 | size = GET_MODE_SIZE (mode); | |
5954 | ||
5955 | if (TARGET_64BIT) | |
5956 | return size <= 0; | |
5957 | else | |
5958 | return size <= 0 || size > 8; | |
5959 | } | |
5960 | ||
87ad11b0 | 5961 | enum direction |
fb80456a | 5962 | function_arg_padding (enum machine_mode mode, const_tree type) |
87ad11b0 | 5963 | { |
ac965869 | 5964 | if (mode == BLKmode |
ef669d1a | 5965 | || (TARGET_64BIT |
5966 | && type | |
5967 | && (AGGREGATE_TYPE_P (type) | |
5968 | || TREE_CODE (type) == COMPLEX_TYPE | |
5969 | || TREE_CODE (type) == VECTOR_TYPE))) | |
ac965869 | 5970 | { |
5971 | /* Return none if justification is not required. */ | |
5972 | if (type | |
5973 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
5974 | && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0) | |
5975 | return none; | |
5976 | ||
5977 | /* The directions set here are ignored when a BLKmode argument larger | |
5978 | than a word is placed in a register. Different code is used for | |
5979 | the stack and registers. This makes it difficult to have a | |
5980 | consistent data representation for both the stack and registers. | |
5981 | For both runtimes, the justification and padding for arguments on | |
5982 | the stack and in registers should be identical. */ | |
5983 | if (TARGET_64BIT) | |
5984 | /* The 64-bit runtime specifies left justification for aggregates. */ | |
5985 | return upward; | |
87ad11b0 | 5986 | else |
ac965869 | 5987 | /* The 32-bit runtime architecture specifies right justification. |
5988 | When the argument is passed on the stack, the argument is padded | |
5989 | with garbage on the left. The HP compiler pads with zeros. */ | |
5990 | return downward; | |
87ad11b0 | 5991 | } |
ac965869 | 5992 | |
5993 | if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
87ad11b0 | 5994 | return downward; |
87ad11b0 | 5995 | else |
5996 | return none; | |
5997 | } | |
5998 | ||
87ad11b0 | 5999 | \f |
55f54832 | 6000 | /* Do what is necessary for `va_start'. We look at the current function |
6001 | to determine if stdargs or varargs is used and fill in an initial | |
6002 | va_list. A pointer to this constructor is returned. */ | |
87ad11b0 | 6003 | |
b8debbe8 | 6004 | static rtx |
5c1d8983 | 6005 | hppa_builtin_saveregs (void) |
87ad11b0 | 6006 | { |
01251cbc | 6007 | rtx offset, dest; |
87ad11b0 | 6008 | tree fntype = TREE_TYPE (current_function_decl); |
257d99c3 | 6009 | int argadj = ((!stdarg_p (fntype)) |
87ad11b0 | 6010 | ? UNITS_PER_WORD : 0); |
6011 | ||
6012 | if (argadj) | |
abe32cce | 6013 | offset = plus_constant (crtl->args.arg_offset_rtx, argadj); |
87ad11b0 | 6014 | else |
abe32cce | 6015 | offset = crtl->args.arg_offset_rtx; |
9c6d4825 | 6016 | |
5e3c5739 | 6017 | if (TARGET_64BIT) |
6018 | { | |
6019 | int i, off; | |
9840d99d | 6020 | |
5e3c5739 | 6021 | /* Adjust for varargs/stdarg differences. */ |
6022 | if (argadj) | |
abe32cce | 6023 | offset = plus_constant (crtl->args.arg_offset_rtx, -argadj); |
5e3c5739 | 6024 | else |
abe32cce | 6025 | offset = crtl->args.arg_offset_rtx; |
5e3c5739 | 6026 | |
6027 | /* We need to save %r26 .. %r19 inclusive starting at offset -64 | |
6028 | from the incoming arg pointer and growing to larger addresses. */ | |
6029 | for (i = 26, off = -64; i >= 19; i--, off += 8) | |
6030 | emit_move_insn (gen_rtx_MEM (word_mode, | |
6031 | plus_constant (arg_pointer_rtx, off)), | |
6032 | gen_rtx_REG (word_mode, i)); | |
6033 | ||
6034 | /* The incoming args pointer points just beyond the flushback area; | |
8ef587dc | 6035 | normally this is not a serious concern. However, when we are doing |
5e3c5739 | 6036 | varargs/stdargs we want to make the arg pointer point to the start |
6037 | of the incoming argument area. */ | |
6038 | emit_move_insn (virtual_incoming_args_rtx, | |
6039 | plus_constant (arg_pointer_rtx, -64)); | |
6040 | ||
6041 | /* Now return a pointer to the first anonymous argument. */ | |
6042 | return copy_to_reg (expand_binop (Pmode, add_optab, | |
6043 | virtual_incoming_args_rtx, | |
6044 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
6045 | } | |
6046 | ||
6dc3b0d9 | 6047 | /* Store general registers on the stack. */ |
ad851752 | 6048 | dest = gen_rtx_MEM (BLKmode, |
abe32cce | 6049 | plus_constant (crtl->args.internal_arg_pointer, |
ad851752 | 6050 | -16)); |
ab6ab77e | 6051 | set_mem_alias_set (dest, get_varargs_alias_set ()); |
2a631e19 | 6052 | set_mem_align (dest, BITS_PER_WORD); |
530178a9 | 6053 | move_block_from_reg (23, dest, 4); |
01251cbc | 6054 | |
76a0ced5 | 6055 | /* move_block_from_reg will emit code to store the argument registers |
6056 | individually as scalar stores. | |
6057 | ||
6058 | However, other insns may later load from the same addresses for | |
ad87de1e | 6059 | a structure load (passing a struct to a varargs routine). |
76a0ced5 | 6060 | |
6061 | The alias code assumes that such aliasing can never happen, so we | |
6062 | have to keep memory referencing insns from moving up beyond the | |
6063 | last argument register store. So we emit a blockage insn here. */ | |
6064 | emit_insn (gen_blockage ()); | |
6065 | ||
9c6d4825 | 6066 | return copy_to_reg (expand_binop (Pmode, add_optab, |
abe32cce | 6067 | crtl->args.internal_arg_pointer, |
9c6d4825 | 6068 | offset, 0, 0, OPTAB_LIB_WIDEN)); |
87ad11b0 | 6069 | } |
d6f01525 | 6070 | |
8a58ed0a | 6071 | static void |
5c1d8983 | 6072 | hppa_va_start (tree valist, rtx nextarg) |
72899a61 | 6073 | { |
6074 | nextarg = expand_builtin_saveregs (); | |
7df226a2 | 6075 | std_expand_builtin_va_start (valist, nextarg); |
72899a61 | 6076 | } |
6077 | ||
4c33eb68 | 6078 | static tree |
75a70cf9 | 6079 | hppa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
6080 | gimple_seq *post_p) | |
72899a61 | 6081 | { |
5e3c5739 | 6082 | if (TARGET_64BIT) |
6083 | { | |
4c33eb68 | 6084 | /* Args grow upward. We can use the generic routines. */ |
bef380a4 | 6085 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
72899a61 | 6086 | } |
ac965869 | 6087 | else /* !TARGET_64BIT */ |
72899a61 | 6088 | { |
4c33eb68 | 6089 | tree ptr = build_pointer_type (type); |
6090 | tree valist_type; | |
6091 | tree t, u; | |
6092 | unsigned int size, ofs; | |
bef380a4 | 6093 | bool indirect; |
72899a61 | 6094 | |
bef380a4 | 6095 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0); |
4c33eb68 | 6096 | if (indirect) |
ac965869 | 6097 | { |
4c33eb68 | 6098 | type = ptr; |
6099 | ptr = build_pointer_type (type); | |
72899a61 | 6100 | } |
4c33eb68 | 6101 | size = int_size_in_bytes (type); |
6102 | valist_type = TREE_TYPE (valist); | |
ac965869 | 6103 | |
4c33eb68 | 6104 | /* Args grow down. Not handled by generic routines. */ |
ac965869 | 6105 | |
0de36bdb | 6106 | u = fold_convert (sizetype, size_in_bytes (type)); |
6107 | u = fold_build1 (NEGATE_EXPR, sizetype, u); | |
6108 | t = build2 (POINTER_PLUS_EXPR, valist_type, valist, u); | |
ac965869 | 6109 | |
175fd0a9 | 6110 | /* Align to 4 or 8 byte boundary depending on argument size. */ |
6111 | ||
6112 | u = build_int_cst (TREE_TYPE (t), (HOST_WIDE_INT)(size > 4 ? -8 : -4)); | |
6113 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u); | |
0de36bdb | 6114 | t = fold_convert (valist_type, t); |
4c33eb68 | 6115 | |
33b1284b | 6116 | t = build2 (MODIFY_EXPR, valist_type, valist, t); |
72899a61 | 6117 | |
4c33eb68 | 6118 | ofs = (8 - size) % 4; |
6119 | if (ofs != 0) | |
6120 | { | |
0de36bdb | 6121 | u = size_int (ofs); |
6122 | t = build2 (POINTER_PLUS_EXPR, valist_type, t, u); | |
ac965869 | 6123 | } |
72899a61 | 6124 | |
4c33eb68 | 6125 | t = fold_convert (ptr, t); |
063f5fdd | 6126 | t = build_va_arg_indirect_ref (t); |
72899a61 | 6127 | |
4c33eb68 | 6128 | if (indirect) |
063f5fdd | 6129 | t = build_va_arg_indirect_ref (t); |
72899a61 | 6130 | |
4c33eb68 | 6131 | return t; |
6132 | } | |
6133 | } | |
72899a61 | 6134 | |
2b1e7cc3 | 6135 | /* True if MODE is valid for the target. By "valid", we mean able to |
6136 | be manipulated in non-trivial ways. In particular, this means all | |
6137 | the arithmetic is supported. | |
6138 | ||
6139 | Currently, TImode is not valid as the HP 64-bit runtime documentation | |
6140 | doesn't document the alignment and calling conventions for this type. | |
6141 | Thus, we return false when PRECISION is 2 * BITS_PER_WORD and | |
6142 | 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */ | |
6143 | ||
6144 | static bool | |
6145 | pa_scalar_mode_supported_p (enum machine_mode mode) | |
6146 | { | |
6147 | int precision = GET_MODE_PRECISION (mode); | |
6148 | ||
6149 | switch (GET_MODE_CLASS (mode)) | |
6150 | { | |
6151 | case MODE_PARTIAL_INT: | |
6152 | case MODE_INT: | |
6153 | if (precision == CHAR_TYPE_SIZE) | |
6154 | return true; | |
6155 | if (precision == SHORT_TYPE_SIZE) | |
6156 | return true; | |
6157 | if (precision == INT_TYPE_SIZE) | |
6158 | return true; | |
6159 | if (precision == LONG_TYPE_SIZE) | |
6160 | return true; | |
6161 | if (precision == LONG_LONG_TYPE_SIZE) | |
6162 | return true; | |
6163 | return false; | |
6164 | ||
6165 | case MODE_FLOAT: | |
6166 | if (precision == FLOAT_TYPE_SIZE) | |
6167 | return true; | |
6168 | if (precision == DOUBLE_TYPE_SIZE) | |
6169 | return true; | |
6170 | if (precision == LONG_DOUBLE_TYPE_SIZE) | |
6171 | return true; | |
6172 | return false; | |
6173 | ||
2af936a9 | 6174 | case MODE_DECIMAL_FLOAT: |
6175 | return false; | |
6176 | ||
2b1e7cc3 | 6177 | default: |
6178 | gcc_unreachable (); | |
6179 | } | |
6180 | } | |
6181 | ||
317754f4 | 6182 | /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and |
6183 | it branches to the next real instruction. Otherwise, return FALSE. */ | |
6184 | ||
6185 | static bool | |
6186 | branch_to_delay_slot_p (rtx insn) | |
6187 | { | |
6188 | if (dbr_sequence_length ()) | |
6189 | return FALSE; | |
6190 | ||
6191 | return next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn); | |
6192 | } | |
6193 | ||
6194 | /* Return TRUE if INSN, a jump insn, needs a nop in its delay slot. | |
6195 | ||
6196 | This occurs when INSN has an unfilled delay slot and is followed | |
6197 | by an ASM_INPUT. Disaster can occur if the ASM_INPUT is empty and | |
6198 | the jump branches into the delay slot. So, we add a nop in the delay | |
6199 | slot just to be safe. This messes up our instruction count, but we | |
6200 | don't know how big the ASM_INPUT insn is anyway. */ | |
6201 | ||
6202 | static bool | |
6203 | branch_needs_nop_p (rtx insn) | |
6204 | { | |
6205 | rtx next_insn; | |
6206 | ||
6207 | if (dbr_sequence_length ()) | |
6208 | return FALSE; | |
6209 | ||
6210 | next_insn = next_real_insn (insn); | |
6211 | return GET_CODE (PATTERN (next_insn)) == ASM_INPUT; | |
6212 | } | |
6213 | ||
6d36483b | 6214 | /* This routine handles all the normal conditional branch sequences we |
6215 | might need to generate. It handles compare immediate vs compare | |
6216 | register, nullification of delay slots, varying length branches, | |
0d986529 | 6217 | negated branches, and all combinations of the above. It returns the |
6d36483b | 6218 | output appropriate to emit the branch corresponding to all given |
0d986529 | 6219 | parameters. */ |
6220 | ||
611a88e1 | 6221 | const char * |
f26036bb | 6222 | output_cbranch (rtx *operands, int negated, rtx insn) |
29a4502c | 6223 | { |
0d986529 | 6224 | static char buf[100]; |
6225 | int useskip = 0; | |
f26036bb | 6226 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6227 | int length = get_attr_length (insn); | |
6228 | int xdelay; | |
0d986529 | 6229 | |
a361b456 | 6230 | /* A conditional branch to the following instruction (e.g. the delay slot) |
ece0fa59 | 6231 | is asking for a disaster. This can happen when not optimizing and |
6232 | when jump optimization fails. | |
29a4502c | 6233 | |
38efba6c | 6234 | While it is usually safe to emit nothing, this can fail if the |
6235 | preceding instruction is a nullified branch with an empty delay | |
6236 | slot and the same branch target as this branch. We could check | |
6237 | for this but jump optimization should eliminate nop jumps. It | |
6238 | is always safe to emit a nop. */ | |
317754f4 | 6239 | if (branch_to_delay_slot_p (insn)) |
ece0fa59 | 6240 | return "nop"; |
6d36483b | 6241 | |
22699a7e | 6242 | /* The doubleword form of the cmpib instruction doesn't have the LEU |
6243 | and GTU conditions while the cmpb instruction does. Since we accept | |
6244 | zero for cmpb, we must ensure that we use cmpb for the comparison. */ | |
6245 | if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx) | |
6246 | operands[2] = gen_rtx_REG (DImode, 0); | |
d65b8df8 | 6247 | if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx) |
6248 | operands[1] = gen_rtx_REG (DImode, 0); | |
22699a7e | 6249 | |
5fbd5940 | 6250 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6251 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6252 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6253 | nullify = 1; |
6254 | ||
6255 | /* If this is a short forward conditional branch which did not get | |
6256 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6257 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6258 | nullify = forward_branch_p (insn); |
6259 | ||
6d36483b | 6260 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6261 | comclr instruction. This avoids a single cycle penalty due to |
6262 | mis-predicted branch if we fall through (branch not taken). */ | |
5a1231ef | 6263 | if (length == 4 |
5fbd5940 | 6264 | && next_real_insn (insn) != 0 |
5a1231ef | 6265 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 6266 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 6267 | && nullify) |
6268 | useskip = 1; | |
6269 | ||
6270 | switch (length) | |
6271 | { | |
5fbd5940 | 6272 | /* All short conditional branches except backwards with an unfilled |
6273 | delay slot. */ | |
5a1231ef | 6274 | case 4: |
0d986529 | 6275 | if (useskip) |
e4065f95 | 6276 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
0d986529 | 6277 | else |
e4065f95 | 6278 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6279 | if (GET_MODE (operands[1]) == DImode) |
6280 | strcat (buf, "*"); | |
0d986529 | 6281 | if (negated) |
6282 | strcat (buf, "%B3"); | |
6283 | else | |
6284 | strcat (buf, "%S3"); | |
6285 | if (useskip) | |
5a811d43 | 6286 | strcat (buf, " %2,%r1,%%r0"); |
0d986529 | 6287 | else if (nullify) |
317754f4 | 6288 | { |
6289 | if (branch_needs_nop_p (insn)) | |
6290 | strcat (buf, ",n %2,%r1,%0%#"); | |
6291 | else | |
6292 | strcat (buf, ",n %2,%r1,%0"); | |
6293 | } | |
6d36483b | 6294 | else |
9e49be0e | 6295 | strcat (buf, " %2,%r1,%0"); |
0d986529 | 6296 | break; |
6297 | ||
87fcb603 | 6298 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6299 | unfilled delay slot is treated just like a long backward branch |
6300 | with an unfilled delay slot. */ | |
5a1231ef | 6301 | case 8: |
5fbd5940 | 6302 | /* Handle weird backwards branch with a filled delay slot |
f26036bb | 6303 | which is nullified. */ |
5fbd5940 | 6304 | if (dbr_sequence_length () != 0 |
6305 | && ! forward_branch_p (insn) | |
6306 | && nullify) | |
6307 | { | |
e4065f95 | 6308 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6309 | if (GET_MODE (operands[1]) == DImode) |
6310 | strcat (buf, "*"); | |
5fbd5940 | 6311 | if (negated) |
6312 | strcat (buf, "%S3"); | |
6313 | else | |
6314 | strcat (buf, "%B3"); | |
5a811d43 | 6315 | strcat (buf, ",n %2,%r1,.+12\n\tb %0"); |
5fbd5940 | 6316 | } |
43f0c1f2 | 6317 | /* Handle short backwards branch with an unfilled delay slot. |
6318 | Using a comb;nop rather than comiclr;bl saves 1 cycle for both | |
6319 | taken and untaken branches. */ | |
6320 | else if (dbr_sequence_length () == 0 | |
6321 | && ! forward_branch_p (insn) | |
47fc0706 | 6322 | && INSN_ADDRESSES_SET_P () |
6323 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6324 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6325 | { |
e4065f95 | 6326 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6327 | if (GET_MODE (operands[1]) == DImode) |
6328 | strcat (buf, "*"); | |
43f0c1f2 | 6329 | if (negated) |
9e49be0e | 6330 | strcat (buf, "%B3 %2,%r1,%0%#"); |
43f0c1f2 | 6331 | else |
9e49be0e | 6332 | strcat (buf, "%S3 %2,%r1,%0%#"); |
43f0c1f2 | 6333 | } |
0d986529 | 6334 | else |
5fbd5940 | 6335 | { |
e4065f95 | 6336 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
5e3c5739 | 6337 | if (GET_MODE (operands[1]) == DImode) |
6338 | strcat (buf, "*"); | |
5fbd5940 | 6339 | if (negated) |
6340 | strcat (buf, "%S3"); | |
6341 | else | |
6342 | strcat (buf, "%B3"); | |
6343 | if (nullify) | |
5a811d43 | 6344 | strcat (buf, " %2,%r1,%%r0\n\tb,n %0"); |
5fbd5940 | 6345 | else |
5a811d43 | 6346 | strcat (buf, " %2,%r1,%%r0\n\tb %0"); |
5fbd5940 | 6347 | } |
0d986529 | 6348 | break; |
6349 | ||
f26036bb | 6350 | default: |
e9ec370e | 6351 | /* The reversed conditional branch must branch over one additional |
f26036bb | 6352 | instruction if the delay slot is filled and needs to be extracted |
6353 | by output_lbranch. If the delay slot is empty or this is a | |
6354 | nullified forward branch, the instruction after the reversed | |
6355 | condition branch must be nullified. */ | |
6356 | if (dbr_sequence_length () == 0 | |
6357 | || (nullify && forward_branch_p (insn))) | |
6358 | { | |
6359 | nullify = 1; | |
6360 | xdelay = 0; | |
6361 | operands[4] = GEN_INT (length); | |
6362 | } | |
6363 | else | |
6364 | { | |
6365 | xdelay = 1; | |
6366 | operands[4] = GEN_INT (length + 4); | |
6367 | } | |
c8a0e52b | 6368 | |
6369 | /* Create a reversed conditional branch which branches around | |
6370 | the following insns. */ | |
e9ec370e | 6371 | if (GET_MODE (operands[1]) != DImode) |
6372 | { | |
6373 | if (nullify) | |
6374 | { | |
6375 | if (negated) | |
6376 | strcpy (buf, | |
6377 | "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}"); | |
6378 | else | |
6379 | strcpy (buf, | |
6380 | "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}"); | |
6381 | } | |
6382 | else | |
6383 | { | |
6384 | if (negated) | |
6385 | strcpy (buf, | |
6386 | "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}"); | |
6387 | else | |
6388 | strcpy (buf, | |
6389 | "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}"); | |
6390 | } | |
6391 | } | |
c8a0e52b | 6392 | else |
5e3c5739 | 6393 | { |
e9ec370e | 6394 | if (nullify) |
6395 | { | |
6396 | if (negated) | |
6397 | strcpy (buf, | |
6398 | "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}"); | |
6399 | else | |
6400 | strcpy (buf, | |
6401 | "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}"); | |
6402 | } | |
5e3c5739 | 6403 | else |
e9ec370e | 6404 | { |
6405 | if (negated) | |
6406 | strcpy (buf, | |
6407 | "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}"); | |
6408 | else | |
6409 | strcpy (buf, | |
6410 | "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}"); | |
6411 | } | |
5e3c5739 | 6412 | } |
c8a0e52b | 6413 | |
f26036bb | 6414 | output_asm_insn (buf, operands); |
6415 | return output_lbranch (operands[0], insn, xdelay); | |
e9ec370e | 6416 | } |
6417 | return buf; | |
6418 | } | |
c8a0e52b | 6419 | |
f26036bb | 6420 | /* This routine handles output of long unconditional branches that |
6421 | exceed the maximum range of a simple branch instruction. Since | |
6422 | we don't have a register available for the branch, we save register | |
6423 | %r1 in the frame marker, load the branch destination DEST into %r1, | |
6424 | execute the branch, and restore %r1 in the delay slot of the branch. | |
6425 | ||
6426 | Since long branches may have an insn in the delay slot and the | |
6427 | delay slot is used to restore %r1, we in general need to extract | |
6428 | this insn and execute it before the branch. However, to facilitate | |
6429 | use of this function by conditional branches, we also provide an | |
6430 | option to not extract the delay insn so that it will be emitted | |
6431 | after the long branch. So, if there is an insn in the delay slot, | |
6432 | it is extracted if XDELAY is nonzero. | |
6433 | ||
6434 | The lengths of the various long-branch sequences are 20, 16 and 24 | |
6435 | bytes for the portable runtime, non-PIC and PIC cases, respectively. */ | |
c8a0e52b | 6436 | |
e9ec370e | 6437 | const char * |
f26036bb | 6438 | output_lbranch (rtx dest, rtx insn, int xdelay) |
e9ec370e | 6439 | { |
6440 | rtx xoperands[2]; | |
6441 | ||
6442 | xoperands[0] = dest; | |
c8a0e52b | 6443 | |
e9ec370e | 6444 | /* First, free up the delay slot. */ |
f26036bb | 6445 | if (xdelay && dbr_sequence_length () != 0) |
e9ec370e | 6446 | { |
6447 | /* We can't handle a jump in the delay slot. */ | |
ecf2283d | 6448 | gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN); |
c8a0e52b | 6449 | |
e9ec370e | 6450 | final_scan_insn (NEXT_INSN (insn), asm_out_file, |
4bf029b0 | 6451 | optimize, 0, NULL); |
c8a0e52b | 6452 | |
e9ec370e | 6453 | /* Now delete the delay insn. */ |
ad4583d9 | 6454 | SET_INSN_DELETED (NEXT_INSN (insn)); |
e9ec370e | 6455 | } |
c8a0e52b | 6456 | |
e9ec370e | 6457 | /* Output an insn to save %r1. The runtime documentation doesn't |
6458 | specify whether the "Clean Up" slot in the callers frame can | |
6459 | be clobbered by the callee. It isn't copied by HP's builtin | |
6460 | alloca, so this suggests that it can be clobbered if necessary. | |
6461 | The "Static Link" location is copied by HP builtin alloca, so | |
6462 | we avoid using it. Using the cleanup slot might be a problem | |
6463 | if we have to interoperate with languages that pass cleanup | |
6464 | information. However, it should be possible to handle these | |
6465 | situations with GCC's asm feature. | |
6466 | ||
6467 | The "Current RP" slot is reserved for the called procedure, so | |
6468 | we try to use it when we don't have a frame of our own. It's | |
6469 | rather unlikely that we won't have a frame when we need to emit | |
6470 | a very long branch. | |
6471 | ||
6472 | Really the way to go long term is a register scavenger; goto | |
6473 | the target of the jump and find a register which we can use | |
6474 | as a scratch to hold the value in %r1. Then, we wouldn't have | |
6475 | to free up the delay slot or clobber a slot that may be needed | |
6476 | for other purposes. */ | |
6477 | if (TARGET_64BIT) | |
6478 | { | |
3072d30e | 6479 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6480 | /* Use the return pointer slot in the frame marker. */ |
6481 | output_asm_insn ("std %%r1,-16(%%r30)", xoperands); | |
6482 | else | |
6483 | /* Use the slot at -40 in the frame marker since HP builtin | |
6484 | alloca doesn't copy it. */ | |
6485 | output_asm_insn ("std %%r1,-40(%%r30)", xoperands); | |
6486 | } | |
6487 | else | |
6488 | { | |
3072d30e | 6489 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6490 | /* Use the return pointer slot in the frame marker. */ |
6491 | output_asm_insn ("stw %%r1,-20(%%r30)", xoperands); | |
6492 | else | |
6493 | /* Use the "Clean Up" slot in the frame marker. In GCC, | |
6494 | the only other use of this location is for copying a | |
6495 | floating point double argument from a floating-point | |
6496 | register to two general registers. The copy is done | |
19ee40ed | 6497 | as an "atomic" operation when outputting a call, so it |
e9ec370e | 6498 | won't interfere with our using the location here. */ |
6499 | output_asm_insn ("stw %%r1,-12(%%r30)", xoperands); | |
6500 | } | |
b70ea764 | 6501 | |
2247cc5f | 6502 | if (TARGET_PORTABLE_RUNTIME) |
6503 | { | |
6504 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6505 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
6506 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6507 | } | |
6508 | else if (flag_pic) | |
e9ec370e | 6509 | { |
6510 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
6511 | if (TARGET_SOM || !TARGET_GAS) | |
6512 | { | |
6513 | xoperands[1] = gen_label_rtx (); | |
6514 | output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands); | |
c5559ed4 | 6515 | targetm.asm_out.internal_label (asm_out_file, "L", |
6516 | CODE_LABEL_NUMBER (xoperands[1])); | |
e9ec370e | 6517 | output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands); |
c8a0e52b | 6518 | } |
e9ec370e | 6519 | else |
6520 | { | |
6521 | output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6522 | output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6523 | } | |
6524 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6525 | } | |
6526 | else | |
6527 | /* Now output a very long branch to the original target. */ | |
6528 | output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands); | |
c8a0e52b | 6529 | |
e9ec370e | 6530 | /* Now restore the value of %r1 in the delay slot. */ |
6531 | if (TARGET_64BIT) | |
6532 | { | |
3072d30e | 6533 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6534 | return "ldd -16(%%r30),%%r1"; |
6535 | else | |
6536 | return "ldd -40(%%r30),%%r1"; | |
6537 | } | |
6538 | else | |
6539 | { | |
3072d30e | 6540 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6541 | return "ldw -20(%%r30),%%r1"; |
6542 | else | |
6543 | return "ldw -12(%%r30),%%r1"; | |
5fbd5940 | 6544 | } |
0d986529 | 6545 | } |
6546 | ||
6d36483b | 6547 | /* This routine handles all the branch-on-bit conditional branch sequences we |
0d986529 | 6548 | might need to generate. It handles nullification of delay slots, |
6549 | varying length branches, negated branches and all combinations of the | |
6550 | above. it returns the appropriate output template to emit the branch. */ | |
6551 | ||
611a88e1 | 6552 | const char * |
f26036bb | 6553 | output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
29a4502c | 6554 | { |
0d986529 | 6555 | static char buf[100]; |
6556 | int useskip = 0; | |
f26036bb | 6557 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6558 | int length = get_attr_length (insn); | |
6559 | int xdelay; | |
0d986529 | 6560 | |
a361b456 | 6561 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 6562 | asking for a disaster. I do not think this can happen as this pattern |
6d36483b | 6563 | is only used when optimizing; jump optimization should eliminate the |
29a4502c | 6564 | jump. But be prepared just in case. */ |
6d36483b | 6565 | |
317754f4 | 6566 | if (branch_to_delay_slot_p (insn)) |
ece0fa59 | 6567 | return "nop"; |
6d36483b | 6568 | |
5fbd5940 | 6569 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6570 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6571 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6572 | nullify = 1; |
6573 | ||
6574 | /* If this is a short forward conditional branch which did not get | |
6575 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6576 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6577 | nullify = forward_branch_p (insn); |
6578 | ||
6d36483b | 6579 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6580 | extrs instruction. This avoids a single cycle penalty due to |
6581 | mis-predicted branch if we fall through (branch not taken). */ | |
6582 | ||
5a1231ef | 6583 | if (length == 4 |
5fbd5940 | 6584 | && next_real_insn (insn) != 0 |
5a1231ef | 6585 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 6586 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 6587 | && nullify) |
6588 | useskip = 1; | |
6589 | ||
6590 | switch (length) | |
6591 | { | |
6592 | ||
5fbd5940 | 6593 | /* All short conditional branches except backwards with an unfilled |
6594 | delay slot. */ | |
5a1231ef | 6595 | case 4: |
0d986529 | 6596 | if (useskip) |
e4065f95 | 6597 | strcpy (buf, "{extrs,|extrw,s,}"); |
6d36483b | 6598 | else |
0d986529 | 6599 | strcpy (buf, "bb,"); |
5e3c5739 | 6600 | if (useskip && GET_MODE (operands[0]) == DImode) |
6601 | strcpy (buf, "extrd,s,*"); | |
6602 | else if (GET_MODE (operands[0]) == DImode) | |
6603 | strcpy (buf, "bb,*"); | |
0d986529 | 6604 | if ((which == 0 && negated) |
6605 | || (which == 1 && ! negated)) | |
6606 | strcat (buf, ">="); | |
6607 | else | |
6608 | strcat (buf, "<"); | |
6609 | if (useskip) | |
5a811d43 | 6610 | strcat (buf, " %0,%1,1,%%r0"); |
0d986529 | 6611 | else if (nullify && negated) |
317754f4 | 6612 | { |
6613 | if (branch_needs_nop_p (insn)) | |
6614 | strcat (buf, ",n %0,%1,%3%#"); | |
6615 | else | |
6616 | strcat (buf, ",n %0,%1,%3"); | |
6617 | } | |
0d986529 | 6618 | else if (nullify && ! negated) |
317754f4 | 6619 | { |
6620 | if (branch_needs_nop_p (insn)) | |
6621 | strcat (buf, ",n %0,%1,%2%#"); | |
6622 | else | |
6623 | strcat (buf, ",n %0,%1,%2"); | |
6624 | } | |
0d986529 | 6625 | else if (! nullify && negated) |
317754f4 | 6626 | strcat (buf, " %0,%1,%3"); |
0d986529 | 6627 | else if (! nullify && ! negated) |
5fbd5940 | 6628 | strcat (buf, " %0,%1,%2"); |
0d986529 | 6629 | break; |
6630 | ||
87fcb603 | 6631 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6632 | unfilled delay slot is treated just like a long backward branch |
6633 | with an unfilled delay slot. */ | |
5a1231ef | 6634 | case 8: |
5fbd5940 | 6635 | /* Handle weird backwards branch with a filled delay slot |
f26036bb | 6636 | which is nullified. */ |
5fbd5940 | 6637 | if (dbr_sequence_length () != 0 |
6638 | && ! forward_branch_p (insn) | |
6639 | && nullify) | |
6640 | { | |
6641 | strcpy (buf, "bb,"); | |
5e3c5739 | 6642 | if (GET_MODE (operands[0]) == DImode) |
6643 | strcat (buf, "*"); | |
5fbd5940 | 6644 | if ((which == 0 && negated) |
6645 | || (which == 1 && ! negated)) | |
6646 | strcat (buf, "<"); | |
6647 | else | |
6648 | strcat (buf, ">="); | |
6649 | if (negated) | |
5a811d43 | 6650 | strcat (buf, ",n %0,%1,.+12\n\tb %3"); |
5fbd5940 | 6651 | else |
5a811d43 | 6652 | strcat (buf, ",n %0,%1,.+12\n\tb %2"); |
5fbd5940 | 6653 | } |
43f0c1f2 | 6654 | /* Handle short backwards branch with an unfilled delay slot. |
6655 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6656 | taken and untaken branches. */ | |
6657 | else if (dbr_sequence_length () == 0 | |
6658 | && ! forward_branch_p (insn) | |
47fc0706 | 6659 | && INSN_ADDRESSES_SET_P () |
6660 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6661 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6662 | { |
6663 | strcpy (buf, "bb,"); | |
5e3c5739 | 6664 | if (GET_MODE (operands[0]) == DImode) |
6665 | strcat (buf, "*"); | |
43f0c1f2 | 6666 | if ((which == 0 && negated) |
6667 | || (which == 1 && ! negated)) | |
6668 | strcat (buf, ">="); | |
6669 | else | |
6670 | strcat (buf, "<"); | |
6671 | if (negated) | |
6672 | strcat (buf, " %0,%1,%3%#"); | |
6673 | else | |
6674 | strcat (buf, " %0,%1,%2%#"); | |
6675 | } | |
0d986529 | 6676 | else |
5fbd5940 | 6677 | { |
5e3c5739 | 6678 | if (GET_MODE (operands[0]) == DImode) |
6679 | strcpy (buf, "extrd,s,*"); | |
f26036bb | 6680 | else |
6681 | strcpy (buf, "{extrs,|extrw,s,}"); | |
5fbd5940 | 6682 | if ((which == 0 && negated) |
6683 | || (which == 1 && ! negated)) | |
6684 | strcat (buf, "<"); | |
6685 | else | |
6686 | strcat (buf, ">="); | |
6687 | if (nullify && negated) | |
c6ae275c | 6688 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %3"); |
5fbd5940 | 6689 | else if (nullify && ! negated) |
c6ae275c | 6690 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %2"); |
5fbd5940 | 6691 | else if (negated) |
5a811d43 | 6692 | strcat (buf, " %0,%1,1,%%r0\n\tb %3"); |
6d36483b | 6693 | else |
5a811d43 | 6694 | strcat (buf, " %0,%1,1,%%r0\n\tb %2"); |
5fbd5940 | 6695 | } |
0d986529 | 6696 | break; |
6697 | ||
6698 | default: | |
f26036bb | 6699 | /* The reversed conditional branch must branch over one additional |
6700 | instruction if the delay slot is filled and needs to be extracted | |
6701 | by output_lbranch. If the delay slot is empty or this is a | |
6702 | nullified forward branch, the instruction after the reversed | |
6703 | condition branch must be nullified. */ | |
6704 | if (dbr_sequence_length () == 0 | |
6705 | || (nullify && forward_branch_p (insn))) | |
6706 | { | |
6707 | nullify = 1; | |
6708 | xdelay = 0; | |
d9e3874e | 6709 | operands[4] = GEN_INT (length); |
f26036bb | 6710 | } |
6711 | else | |
6712 | { | |
6713 | xdelay = 1; | |
d9e3874e | 6714 | operands[4] = GEN_INT (length + 4); |
f26036bb | 6715 | } |
6716 | ||
6717 | if (GET_MODE (operands[0]) == DImode) | |
d9e3874e | 6718 | strcpy (buf, "bb,*"); |
f26036bb | 6719 | else |
d9e3874e | 6720 | strcpy (buf, "bb,"); |
f26036bb | 6721 | if ((which == 0 && negated) |
6722 | || (which == 1 && !negated)) | |
d9e3874e | 6723 | strcat (buf, "<"); |
f26036bb | 6724 | else |
d9e3874e | 6725 | strcat (buf, ">="); |
f26036bb | 6726 | if (nullify) |
d9e3874e | 6727 | strcat (buf, ",n %0,%1,.+%4"); |
f26036bb | 6728 | else |
d9e3874e | 6729 | strcat (buf, " %0,%1,.+%4"); |
f26036bb | 6730 | output_asm_insn (buf, operands); |
6731 | return output_lbranch (negated ? operands[3] : operands[2], | |
6732 | insn, xdelay); | |
5fbd5940 | 6733 | } |
0d986529 | 6734 | return buf; |
6735 | } | |
6736 | ||
c7a4e712 | 6737 | /* This routine handles all the branch-on-variable-bit conditional branch |
6738 | sequences we might need to generate. It handles nullification of delay | |
6739 | slots, varying length branches, negated branches and all combinations | |
6740 | of the above. it returns the appropriate output template to emit the | |
6741 | branch. */ | |
6742 | ||
611a88e1 | 6743 | const char * |
f26036bb | 6744 | output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
c7a4e712 | 6745 | { |
6746 | static char buf[100]; | |
6747 | int useskip = 0; | |
f26036bb | 6748 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6749 | int length = get_attr_length (insn); | |
6750 | int xdelay; | |
c7a4e712 | 6751 | |
a361b456 | 6752 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
c7a4e712 | 6753 | asking for a disaster. I do not think this can happen as this pattern |
6754 | is only used when optimizing; jump optimization should eliminate the | |
6755 | jump. But be prepared just in case. */ | |
6756 | ||
317754f4 | 6757 | if (branch_to_delay_slot_p (insn)) |
ece0fa59 | 6758 | return "nop"; |
c7a4e712 | 6759 | |
6760 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6761 | as it can nullify the delay slot and save a nop. */ | |
6762 | if (length == 8 && dbr_sequence_length () == 0) | |
6763 | nullify = 1; | |
6764 | ||
6765 | /* If this is a short forward conditional branch which did not get | |
6766 | its delay slot filled, the delay slot can still be nullified. */ | |
6767 | if (! nullify && length == 4 && dbr_sequence_length () == 0) | |
6768 | nullify = forward_branch_p (insn); | |
6769 | ||
6770 | /* A forward branch over a single nullified insn can be done with a | |
6771 | extrs instruction. This avoids a single cycle penalty due to | |
6772 | mis-predicted branch if we fall through (branch not taken). */ | |
6773 | ||
6774 | if (length == 4 | |
6775 | && next_real_insn (insn) != 0 | |
6776 | && get_attr_length (next_real_insn (insn)) == 4 | |
6777 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) | |
6778 | && nullify) | |
6779 | useskip = 1; | |
6780 | ||
6781 | switch (length) | |
6782 | { | |
6783 | ||
6784 | /* All short conditional branches except backwards with an unfilled | |
6785 | delay slot. */ | |
6786 | case 4: | |
6787 | if (useskip) | |
e4065f95 | 6788 | strcpy (buf, "{vextrs,|extrw,s,}"); |
c7a4e712 | 6789 | else |
e4065f95 | 6790 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6791 | if (useskip && GET_MODE (operands[0]) == DImode) |
e75269fd | 6792 | strcpy (buf, "extrd,s,*"); |
5e3c5739 | 6793 | else if (GET_MODE (operands[0]) == DImode) |
6794 | strcpy (buf, "bb,*"); | |
c7a4e712 | 6795 | if ((which == 0 && negated) |
6796 | || (which == 1 && ! negated)) | |
6797 | strcat (buf, ">="); | |
6798 | else | |
6799 | strcat (buf, "<"); | |
6800 | if (useskip) | |
e4065f95 | 6801 | strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}"); |
c7a4e712 | 6802 | else if (nullify && negated) |
317754f4 | 6803 | { |
6804 | if (branch_needs_nop_p (insn)) | |
6805 | strcat (buf, "{,n %0,%3%#|,n %0,%%sar,%3%#}"); | |
6806 | else | |
6807 | strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}"); | |
6808 | } | |
c7a4e712 | 6809 | else if (nullify && ! negated) |
317754f4 | 6810 | { |
6811 | if (branch_needs_nop_p (insn)) | |
6812 | strcat (buf, "{,n %0,%2%#|,n %0,%%sar,%2%#}"); | |
6813 | else | |
6814 | strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}"); | |
6815 | } | |
c7a4e712 | 6816 | else if (! nullify && negated) |
317754f4 | 6817 | strcat (buf, "{ %0,%3| %0,%%sar,%3}"); |
c7a4e712 | 6818 | else if (! nullify && ! negated) |
e4065f95 | 6819 | strcat (buf, "{ %0,%2| %0,%%sar,%2}"); |
c7a4e712 | 6820 | break; |
6821 | ||
87fcb603 | 6822 | /* All long conditionals. Note a short backward branch with an |
c7a4e712 | 6823 | unfilled delay slot is treated just like a long backward branch |
6824 | with an unfilled delay slot. */ | |
6825 | case 8: | |
6826 | /* Handle weird backwards branch with a filled delay slot | |
f26036bb | 6827 | which is nullified. */ |
c7a4e712 | 6828 | if (dbr_sequence_length () != 0 |
6829 | && ! forward_branch_p (insn) | |
6830 | && nullify) | |
6831 | { | |
e4065f95 | 6832 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6833 | if (GET_MODE (operands[0]) == DImode) |
6834 | strcat (buf, "*"); | |
c7a4e712 | 6835 | if ((which == 0 && negated) |
6836 | || (which == 1 && ! negated)) | |
6837 | strcat (buf, "<"); | |
6838 | else | |
6839 | strcat (buf, ">="); | |
6840 | if (negated) | |
e4065f95 | 6841 | strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}"); |
c7a4e712 | 6842 | else |
e4065f95 | 6843 | strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}"); |
c7a4e712 | 6844 | } |
6845 | /* Handle short backwards branch with an unfilled delay slot. | |
6846 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6847 | taken and untaken branches. */ | |
6848 | else if (dbr_sequence_length () == 0 | |
6849 | && ! forward_branch_p (insn) | |
47fc0706 | 6850 | && INSN_ADDRESSES_SET_P () |
6851 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6852 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
c7a4e712 | 6853 | { |
e4065f95 | 6854 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6855 | if (GET_MODE (operands[0]) == DImode) |
6856 | strcat (buf, "*"); | |
c7a4e712 | 6857 | if ((which == 0 && negated) |
6858 | || (which == 1 && ! negated)) | |
6859 | strcat (buf, ">="); | |
6860 | else | |
6861 | strcat (buf, "<"); | |
6862 | if (negated) | |
e4065f95 | 6863 | strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}"); |
c7a4e712 | 6864 | else |
e4065f95 | 6865 | strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}"); |
c7a4e712 | 6866 | } |
6867 | else | |
6868 | { | |
e4065f95 | 6869 | strcpy (buf, "{vextrs,|extrw,s,}"); |
5e3c5739 | 6870 | if (GET_MODE (operands[0]) == DImode) |
6871 | strcpy (buf, "extrd,s,*"); | |
c7a4e712 | 6872 | if ((which == 0 && negated) |
6873 | || (which == 1 && ! negated)) | |
6874 | strcat (buf, "<"); | |
6875 | else | |
6876 | strcat (buf, ">="); | |
6877 | if (nullify && negated) | |
e4065f95 | 6878 | strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}"); |
c7a4e712 | 6879 | else if (nullify && ! negated) |
e4065f95 | 6880 | strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}"); |
c7a4e712 | 6881 | else if (negated) |
e4065f95 | 6882 | strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}"); |
c7a4e712 | 6883 | else |
e4065f95 | 6884 | strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}"); |
c7a4e712 | 6885 | } |
6886 | break; | |
6887 | ||
6888 | default: | |
f26036bb | 6889 | /* The reversed conditional branch must branch over one additional |
6890 | instruction if the delay slot is filled and needs to be extracted | |
6891 | by output_lbranch. If the delay slot is empty or this is a | |
6892 | nullified forward branch, the instruction after the reversed | |
6893 | condition branch must be nullified. */ | |
6894 | if (dbr_sequence_length () == 0 | |
6895 | || (nullify && forward_branch_p (insn))) | |
6896 | { | |
6897 | nullify = 1; | |
6898 | xdelay = 0; | |
d9e3874e | 6899 | operands[4] = GEN_INT (length); |
f26036bb | 6900 | } |
6901 | else | |
6902 | { | |
6903 | xdelay = 1; | |
d9e3874e | 6904 | operands[4] = GEN_INT (length + 4); |
f26036bb | 6905 | } |
6906 | ||
6907 | if (GET_MODE (operands[0]) == DImode) | |
d9e3874e | 6908 | strcpy (buf, "bb,*"); |
f26036bb | 6909 | else |
d9e3874e | 6910 | strcpy (buf, "{bvb,|bb,}"); |
f26036bb | 6911 | if ((which == 0 && negated) |
6912 | || (which == 1 && !negated)) | |
d9e3874e | 6913 | strcat (buf, "<"); |
f26036bb | 6914 | else |
d9e3874e | 6915 | strcat (buf, ">="); |
f26036bb | 6916 | if (nullify) |
d9e3874e | 6917 | strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}"); |
f26036bb | 6918 | else |
d9e3874e | 6919 | strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}"); |
f26036bb | 6920 | output_asm_insn (buf, operands); |
6921 | return output_lbranch (negated ? operands[3] : operands[2], | |
6922 | insn, xdelay); | |
c7a4e712 | 6923 | } |
6924 | return buf; | |
6925 | } | |
6926 | ||
29a4502c | 6927 | /* Return the output template for emitting a dbra type insn. |
6928 | ||
6929 | Note it may perform some output operations on its own before | |
6930 | returning the final output string. */ | |
611a88e1 | 6931 | const char * |
5c1d8983 | 6932 | output_dbra (rtx *operands, rtx insn, int which_alternative) |
29a4502c | 6933 | { |
f26036bb | 6934 | int length = get_attr_length (insn); |
29a4502c | 6935 | |
a361b456 | 6936 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 6937 | asking for a disaster. Be prepared! */ |
6938 | ||
317754f4 | 6939 | if (branch_to_delay_slot_p (insn)) |
29a4502c | 6940 | { |
6941 | if (which_alternative == 0) | |
6942 | return "ldo %1(%0),%0"; | |
6943 | else if (which_alternative == 1) | |
6944 | { | |
ea52c577 | 6945 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands); |
6946 | output_asm_insn ("ldw -16(%%r30),%4", operands); | |
34940871 | 6947 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
e4065f95 | 6948 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6949 | } |
6950 | else | |
6951 | { | |
6952 | output_asm_insn ("ldw %0,%4", operands); | |
6953 | return "ldo %1(%4),%4\n\tstw %4,%0"; | |
6954 | } | |
6955 | } | |
6956 | ||
6957 | if (which_alternative == 0) | |
6958 | { | |
6959 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
f26036bb | 6960 | int xdelay; |
29a4502c | 6961 | |
6962 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6963 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6964 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 6965 | nullify = 1; |
6966 | ||
6967 | /* If this is a short forward conditional branch which did not get | |
6968 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6969 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 6970 | nullify = forward_branch_p (insn); |
6971 | ||
ecf2283d | 6972 | switch (length) |
29a4502c | 6973 | { |
ecf2283d | 6974 | case 4: |
6975 | if (nullify) | |
317754f4 | 6976 | { |
6977 | if (branch_needs_nop_p (insn)) | |
6978 | return "addib,%C2,n %1,%0,%3%#"; | |
6979 | else | |
6980 | return "addib,%C2,n %1,%0,%3"; | |
6981 | } | |
ecf2283d | 6982 | else |
6983 | return "addib,%C2 %1,%0,%3"; | |
6984 | ||
6985 | case 8: | |
6d36483b | 6986 | /* Handle weird backwards branch with a fulled delay slot |
29a4502c | 6987 | which is nullified. */ |
6988 | if (dbr_sequence_length () != 0 | |
6989 | && ! forward_branch_p (insn) | |
6990 | && nullify) | |
5a811d43 | 6991 | return "addib,%N2,n %1,%0,.+12\n\tb %3"; |
43f0c1f2 | 6992 | /* Handle short backwards branch with an unfilled delay slot. |
6993 | Using a addb;nop rather than addi;bl saves 1 cycle for both | |
6994 | taken and untaken branches. */ | |
6995 | else if (dbr_sequence_length () == 0 | |
6996 | && ! forward_branch_p (insn) | |
47fc0706 | 6997 | && INSN_ADDRESSES_SET_P () |
6998 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6999 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 7000 | return "addib,%C2 %1,%0,%3%#"; |
6d36483b | 7001 | |
7002 | /* Handle normal cases. */ | |
29a4502c | 7003 | if (nullify) |
5a811d43 | 7004 | return "addi,%N2 %1,%0,%0\n\tb,n %3"; |
29a4502c | 7005 | else |
5a811d43 | 7006 | return "addi,%N2 %1,%0,%0\n\tb %3"; |
ecf2283d | 7007 | |
7008 | default: | |
f26036bb | 7009 | /* The reversed conditional branch must branch over one additional |
7010 | instruction if the delay slot is filled and needs to be extracted | |
7011 | by output_lbranch. If the delay slot is empty or this is a | |
7012 | nullified forward branch, the instruction after the reversed | |
7013 | condition branch must be nullified. */ | |
7014 | if (dbr_sequence_length () == 0 | |
7015 | || (nullify && forward_branch_p (insn))) | |
7016 | { | |
7017 | nullify = 1; | |
7018 | xdelay = 0; | |
7019 | operands[4] = GEN_INT (length); | |
7020 | } | |
7021 | else | |
7022 | { | |
7023 | xdelay = 1; | |
7024 | operands[4] = GEN_INT (length + 4); | |
7025 | } | |
7026 | ||
7027 | if (nullify) | |
7028 | output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands); | |
7029 | else | |
7030 | output_asm_insn ("addib,%N2 %1,%0,.+%4", operands); | |
7031 | ||
7032 | return output_lbranch (operands[3], insn, xdelay); | |
29a4502c | 7033 | } |
ecf2283d | 7034 | |
29a4502c | 7035 | } |
7036 | /* Deal with gross reload from FP register case. */ | |
7037 | else if (which_alternative == 1) | |
7038 | { | |
7039 | /* Move loop counter from FP register to MEM then into a GR, | |
7040 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 7041 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 7042 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4", |
7043 | operands); | |
34940871 | 7044 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
f26036bb | 7045 | if (length == 24) |
e4065f95 | 7046 | return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7047 | else if (length == 28) |
e4065f95 | 7048 | return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7049 | else |
7050 | { | |
d9e3874e | 7051 | operands[5] = GEN_INT (length - 16); |
7052 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands); | |
f26036bb | 7053 | output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands); |
7054 | return output_lbranch (operands[3], insn, 0); | |
7055 | } | |
29a4502c | 7056 | } |
7057 | /* Deal with gross reload from memory case. */ | |
7058 | else | |
7059 | { | |
7060 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 7061 | happens in the branch's delay slot. */ |
29a4502c | 7062 | output_asm_insn ("ldw %0,%4", operands); |
f26036bb | 7063 | if (length == 12) |
29a4502c | 7064 | return "addib,%C2 %1,%4,%3\n\tstw %4,%0"; |
f26036bb | 7065 | else if (length == 16) |
5a811d43 | 7066 | return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0"; |
f26036bb | 7067 | else |
7068 | { | |
d9e3874e | 7069 | operands[5] = GEN_INT (length - 4); |
7070 | output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands); | |
f26036bb | 7071 | return output_lbranch (operands[3], insn, 0); |
7072 | } | |
29a4502c | 7073 | } |
7074 | } | |
7075 | ||
f26036bb | 7076 | /* Return the output template for emitting a movb type insn. |
29a4502c | 7077 | |
7078 | Note it may perform some output operations on its own before | |
7079 | returning the final output string. */ | |
611a88e1 | 7080 | const char * |
5c1d8983 | 7081 | output_movb (rtx *operands, rtx insn, int which_alternative, |
7082 | int reverse_comparison) | |
29a4502c | 7083 | { |
f26036bb | 7084 | int length = get_attr_length (insn); |
29a4502c | 7085 | |
a361b456 | 7086 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 7087 | asking for a disaster. Be prepared! */ |
7088 | ||
317754f4 | 7089 | if (branch_to_delay_slot_p (insn)) |
29a4502c | 7090 | { |
7091 | if (which_alternative == 0) | |
7092 | return "copy %1,%0"; | |
7093 | else if (which_alternative == 1) | |
7094 | { | |
ea52c577 | 7095 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
e4065f95 | 7096 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 7097 | } |
546a40bd | 7098 | else if (which_alternative == 2) |
29a4502c | 7099 | return "stw %1,%0"; |
546a40bd | 7100 | else |
7101 | return "mtsar %r1"; | |
29a4502c | 7102 | } |
7103 | ||
7104 | /* Support the second variant. */ | |
7105 | if (reverse_comparison) | |
7106 | PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2]))); | |
7107 | ||
7108 | if (which_alternative == 0) | |
7109 | { | |
7110 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
f26036bb | 7111 | int xdelay; |
29a4502c | 7112 | |
7113 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
7114 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 7115 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 7116 | nullify = 1; |
7117 | ||
7118 | /* If this is a short forward conditional branch which did not get | |
7119 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 7120 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 7121 | nullify = forward_branch_p (insn); |
7122 | ||
ecf2283d | 7123 | switch (length) |
29a4502c | 7124 | { |
ecf2283d | 7125 | case 4: |
7126 | if (nullify) | |
317754f4 | 7127 | { |
7128 | if (branch_needs_nop_p (insn)) | |
7129 | return "movb,%C2,n %1,%0,%3%#"; | |
7130 | else | |
7131 | return "movb,%C2,n %1,%0,%3"; | |
7132 | } | |
ecf2283d | 7133 | else |
7134 | return "movb,%C2 %1,%0,%3"; | |
7135 | ||
7136 | case 8: | |
6d36483b | 7137 | /* Handle weird backwards branch with a filled delay slot |
29a4502c | 7138 | which is nullified. */ |
7139 | if (dbr_sequence_length () != 0 | |
7140 | && ! forward_branch_p (insn) | |
7141 | && nullify) | |
5a811d43 | 7142 | return "movb,%N2,n %1,%0,.+12\n\tb %3"; |
6d36483b | 7143 | |
43f0c1f2 | 7144 | /* Handle short backwards branch with an unfilled delay slot. |
7145 | Using a movb;nop rather than or;bl saves 1 cycle for both | |
7146 | taken and untaken branches. */ | |
7147 | else if (dbr_sequence_length () == 0 | |
7148 | && ! forward_branch_p (insn) | |
47fc0706 | 7149 | && INSN_ADDRESSES_SET_P () |
7150 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
7151 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 7152 | return "movb,%C2 %1,%0,%3%#"; |
6d36483b | 7153 | /* Handle normal cases. */ |
29a4502c | 7154 | if (nullify) |
5a811d43 | 7155 | return "or,%N2 %1,%%r0,%0\n\tb,n %3"; |
29a4502c | 7156 | else |
5a811d43 | 7157 | return "or,%N2 %1,%%r0,%0\n\tb %3"; |
ecf2283d | 7158 | |
7159 | default: | |
f26036bb | 7160 | /* The reversed conditional branch must branch over one additional |
7161 | instruction if the delay slot is filled and needs to be extracted | |
7162 | by output_lbranch. If the delay slot is empty or this is a | |
7163 | nullified forward branch, the instruction after the reversed | |
7164 | condition branch must be nullified. */ | |
7165 | if (dbr_sequence_length () == 0 | |
7166 | || (nullify && forward_branch_p (insn))) | |
7167 | { | |
7168 | nullify = 1; | |
7169 | xdelay = 0; | |
7170 | operands[4] = GEN_INT (length); | |
7171 | } | |
7172 | else | |
7173 | { | |
7174 | xdelay = 1; | |
7175 | operands[4] = GEN_INT (length + 4); | |
7176 | } | |
7177 | ||
7178 | if (nullify) | |
7179 | output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands); | |
7180 | else | |
7181 | output_asm_insn ("movb,%N2 %1,%0,.+%4", operands); | |
7182 | ||
7183 | return output_lbranch (operands[3], insn, xdelay); | |
29a4502c | 7184 | } |
29a4502c | 7185 | } |
f26036bb | 7186 | /* Deal with gross reload for FP destination register case. */ |
29a4502c | 7187 | else if (which_alternative == 1) |
7188 | { | |
f26036bb | 7189 | /* Move source register to MEM, perform the branch test, then |
7190 | finally load the FP register from MEM from within the branch's | |
7191 | delay slot. */ | |
ea52c577 | 7192 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
f26036bb | 7193 | if (length == 12) |
e4065f95 | 7194 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7195 | else if (length == 16) |
e4065f95 | 7196 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7197 | else |
7198 | { | |
d9e3874e | 7199 | operands[4] = GEN_INT (length - 4); |
7200 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands); | |
f26036bb | 7201 | output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands); |
7202 | return output_lbranch (operands[3], insn, 0); | |
7203 | } | |
29a4502c | 7204 | } |
7205 | /* Deal with gross reload from memory case. */ | |
546a40bd | 7206 | else if (which_alternative == 2) |
29a4502c | 7207 | { |
7208 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 7209 | happens in the branch's delay slot. */ |
f26036bb | 7210 | if (length == 8) |
e4065f95 | 7211 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0"; |
f26036bb | 7212 | else if (length == 12) |
e4065f95 | 7213 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0"; |
f26036bb | 7214 | else |
7215 | { | |
d9e3874e | 7216 | operands[4] = GEN_INT (length); |
7217 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0", | |
7218 | operands); | |
f26036bb | 7219 | return output_lbranch (operands[3], insn, 0); |
7220 | } | |
29a4502c | 7221 | } |
546a40bd | 7222 | /* Handle SAR as a destination. */ |
7223 | else | |
7224 | { | |
f26036bb | 7225 | if (length == 8) |
e4065f95 | 7226 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1"; |
f26036bb | 7227 | else if (length == 12) |
be7770ad | 7228 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1"; |
f26036bb | 7229 | else |
7230 | { | |
d9e3874e | 7231 | operands[4] = GEN_INT (length); |
7232 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1", | |
7233 | operands); | |
f26036bb | 7234 | return output_lbranch (operands[3], insn, 0); |
7235 | } | |
546a40bd | 7236 | } |
29a4502c | 7237 | } |
7238 | ||
ece88821 | 7239 | /* Copy any FP arguments in INSN into integer registers. */ |
7240 | static void | |
5c1d8983 | 7241 | copy_fp_args (rtx insn) |
ece88821 | 7242 | { |
7243 | rtx link; | |
7244 | rtx xoperands[2]; | |
29a4502c | 7245 | |
ece88821 | 7246 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
7247 | { | |
7248 | int arg_mode, regno; | |
7249 | rtx use = XEXP (link, 0); | |
3683f840 | 7250 | |
ece88821 | 7251 | if (! (GET_CODE (use) == USE |
7252 | && GET_CODE (XEXP (use, 0)) == REG | |
7253 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
7254 | continue; | |
d6686e21 | 7255 | |
ece88821 | 7256 | arg_mode = GET_MODE (XEXP (use, 0)); |
7257 | regno = REGNO (XEXP (use, 0)); | |
5e3c5739 | 7258 | |
ece88821 | 7259 | /* Is it a floating point register? */ |
7260 | if (regno >= 32 && regno <= 39) | |
7261 | { | |
7262 | /* Copy the FP register into an integer register via memory. */ | |
7263 | if (arg_mode == SFmode) | |
7264 | { | |
7265 | xoperands[0] = XEXP (use, 0); | |
7266 | xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2); | |
7267 | output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands); | |
7268 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
7269 | } | |
7270 | else | |
7271 | { | |
7272 | xoperands[0] = XEXP (use, 0); | |
7273 | xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2); | |
7274 | output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands); | |
7275 | output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands); | |
7276 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
7277 | } | |
7278 | } | |
06ddb6f8 | 7279 | } |
ece88821 | 7280 | } |
7281 | ||
7282 | /* Compute length of the FP argument copy sequence for INSN. */ | |
7283 | static int | |
5c1d8983 | 7284 | length_fp_args (rtx insn) |
ece88821 | 7285 | { |
7286 | int length = 0; | |
7287 | rtx link; | |
06ddb6f8 | 7288 | |
ece88821 | 7289 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
c7a4e712 | 7290 | { |
ece88821 | 7291 | int arg_mode, regno; |
7292 | rtx use = XEXP (link, 0); | |
7293 | ||
7294 | if (! (GET_CODE (use) == USE | |
7295 | && GET_CODE (XEXP (use, 0)) == REG | |
7296 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
7297 | continue; | |
c7a4e712 | 7298 | |
ece88821 | 7299 | arg_mode = GET_MODE (XEXP (use, 0)); |
7300 | regno = REGNO (XEXP (use, 0)); | |
7301 | ||
7302 | /* Is it a floating point register? */ | |
7303 | if (regno >= 32 && regno <= 39) | |
c7a4e712 | 7304 | { |
ece88821 | 7305 | if (arg_mode == SFmode) |
7306 | length += 8; | |
7307 | else | |
7308 | length += 12; | |
c7a4e712 | 7309 | } |
ece88821 | 7310 | } |
c7a4e712 | 7311 | |
ece88821 | 7312 | return length; |
7313 | } | |
b70ea764 | 7314 | |
cd0dfcc5 | 7315 | /* Return the attribute length for the millicode call instruction INSN. |
7316 | The length must match the code generated by output_millicode_call. | |
7317 | We include the delay slot in the returned length as it is better to | |
ece88821 | 7318 | over estimate the length than to under estimate it. */ |
b29897dd | 7319 | |
ece88821 | 7320 | int |
5c1d8983 | 7321 | attr_length_millicode_call (rtx insn) |
ece88821 | 7322 | { |
cd0dfcc5 | 7323 | unsigned long distance = -1; |
8a05c3c2 | 7324 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
ece88821 | 7325 | |
cd0dfcc5 | 7326 | if (INSN_ADDRESSES_SET_P ()) |
7327 | { | |
2247cc5f | 7328 | distance = (total + insn_current_reference_address (insn)); |
7329 | if (distance < total) | |
cd0dfcc5 | 7330 | distance = -1; |
7331 | } | |
ece88821 | 7332 | |
7333 | if (TARGET_64BIT) | |
7334 | { | |
7335 | if (!TARGET_LONG_CALLS && distance < 7600000) | |
cd0dfcc5 | 7336 | return 8; |
ece88821 | 7337 | |
cd0dfcc5 | 7338 | return 20; |
ece88821 | 7339 | } |
7340 | else if (TARGET_PORTABLE_RUNTIME) | |
cd0dfcc5 | 7341 | return 24; |
ece88821 | 7342 | else |
7343 | { | |
7344 | if (!TARGET_LONG_CALLS && distance < 240000) | |
cd0dfcc5 | 7345 | return 8; |
ece88821 | 7346 | |
7347 | if (TARGET_LONG_ABS_CALL && !flag_pic) | |
cd0dfcc5 | 7348 | return 12; |
ece88821 | 7349 | |
cd0dfcc5 | 7350 | return 24; |
ece88821 | 7351 | } |
7352 | } | |
7353 | ||
7354 | /* INSN is a function call. It may have an unconditional jump | |
7355 | in its delay slot. | |
b29897dd | 7356 | |
ece88821 | 7357 | CALL_DEST is the routine we are calling. */ |
b29897dd | 7358 | |
ece88821 | 7359 | const char * |
5c1d8983 | 7360 | output_millicode_call (rtx insn, rtx call_dest) |
ece88821 | 7361 | { |
7362 | int attr_length = get_attr_length (insn); | |
7363 | int seq_length = dbr_sequence_length (); | |
7364 | int distance; | |
7365 | rtx seq_insn; | |
7366 | rtx xoperands[3]; | |
b29897dd | 7367 | |
ece88821 | 7368 | xoperands[0] = call_dest; |
7369 | xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31); | |
7370 | ||
7371 | /* Handle the common case where we are sure that the branch will | |
7372 | reach the beginning of the $CODE$ subspace. The within reach | |
7373 | form of the $$sh_func_adrs call has a length of 28. Because | |
a8b24921 | 7374 | it has an attribute type of multi, it never has a nonzero |
ece88821 | 7375 | sequence length. The length of the $$sh_func_adrs is the same |
7376 | as certain out of reach PIC calls to other routines. */ | |
7377 | if (!TARGET_LONG_CALLS | |
7378 | && ((seq_length == 0 | |
7379 | && (attr_length == 12 | |
7380 | || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI))) | |
7381 | || (seq_length != 0 && attr_length == 8))) | |
7382 | { | |
7383 | output_asm_insn ("{bl|b,l} %0,%2", xoperands); | |
7384 | } | |
7385 | else | |
7386 | { | |
7387 | if (TARGET_64BIT) | |
7388 | { | |
7389 | /* It might seem that one insn could be saved by accessing | |
7390 | the millicode function using the linkage table. However, | |
7391 | this doesn't work in shared libraries and other dynamically | |
7392 | loaded objects. Using a pc-relative sequence also avoids | |
7393 | problems related to the implicit use of the gp register. */ | |
7394 | output_asm_insn ("b,l .+8,%%r1", xoperands); | |
9bd9af5d | 7395 | |
7396 | if (TARGET_GAS) | |
7397 | { | |
7398 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); | |
7399 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
7400 | } | |
7401 | else | |
7402 | { | |
7403 | xoperands[1] = gen_label_rtx (); | |
7404 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
c5559ed4 | 7405 | targetm.asm_out.internal_label (asm_out_file, "L", |
9bd9af5d | 7406 | CODE_LABEL_NUMBER (xoperands[1])); |
7407 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
7408 | } | |
7409 | ||
ece88821 | 7410 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); |
c7a4e712 | 7411 | } |
c7a4e712 | 7412 | else if (TARGET_PORTABLE_RUNTIME) |
7413 | { | |
ece88821 | 7414 | /* Pure portable runtime doesn't allow be/ble; we also don't |
7415 | have PIC support in the assembler/linker, so this sequence | |
7416 | is needed. */ | |
c7a4e712 | 7417 | |
ece88821 | 7418 | /* Get the address of our target into %r1. */ |
7419 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
7420 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
c7a4e712 | 7421 | |
ece88821 | 7422 | /* Get our return address into %r31. */ |
7423 | output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands); | |
7424 | output_asm_insn ("addi 8,%%r31,%%r31", xoperands); | |
c7a4e712 | 7425 | |
ece88821 | 7426 | /* Jump to our target address in %r1. */ |
7427 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 7428 | } |
ece88821 | 7429 | else if (!flag_pic) |
c7a4e712 | 7430 | { |
ece88821 | 7431 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
356267e0 | 7432 | if (TARGET_PA_20) |
ece88821 | 7433 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands); |
356267e0 | 7434 | else |
ece88821 | 7435 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); |
c7a4e712 | 7436 | } |
ece88821 | 7437 | else |
c7a4e712 | 7438 | { |
9bd9af5d | 7439 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
7440 | output_asm_insn ("addi 16,%%r1,%%r31", xoperands); | |
7441 | ||
ece88821 | 7442 | if (TARGET_SOM || !TARGET_GAS) |
7443 | { | |
7444 | /* The HP assembler can generate relocations for the | |
7445 | difference of two symbols. GAS can do this for a | |
7446 | millicode symbol but not an arbitrary external | |
7447 | symbol when generating SOM output. */ | |
7448 | xoperands[1] = gen_label_rtx (); | |
c5559ed4 | 7449 | targetm.asm_out.internal_label (asm_out_file, "L", |
ece88821 | 7450 | CODE_LABEL_NUMBER (xoperands[1])); |
7451 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
7452 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
7453 | } | |
7454 | else | |
7455 | { | |
ece88821 | 7456 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands); |
7457 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1", | |
7458 | xoperands); | |
7459 | } | |
c7a4e712 | 7460 | |
ece88821 | 7461 | /* Jump to our target address in %r1. */ |
7462 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 7463 | } |
c7a4e712 | 7464 | } |
7465 | ||
ece88821 | 7466 | if (seq_length == 0) |
7467 | output_asm_insn ("nop", xoperands); | |
c7a4e712 | 7468 | |
ece88821 | 7469 | /* We are done if there isn't a jump in the delay slot. */ |
7470 | if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7471 | return ""; | |
c7a4e712 | 7472 | |
ece88821 | 7473 | /* This call has an unconditional jump in its delay slot. */ |
7474 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
c7a4e712 | 7475 | |
ece88821 | 7476 | /* See if the return address can be adjusted. Use the containing |
7477 | sequence insn's address. */ | |
cd0dfcc5 | 7478 | if (INSN_ADDRESSES_SET_P ()) |
c7a4e712 | 7479 | { |
cd0dfcc5 | 7480 | seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); |
7481 | distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7482 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7483 | ||
7484 | if (VAL_14_BITS_P (distance)) | |
7485 | { | |
7486 | xoperands[1] = gen_label_rtx (); | |
7487 | output_asm_insn ("ldo %0-%1(%2),%2", xoperands); | |
c5559ed4 | 7488 | targetm.asm_out.internal_label (asm_out_file, "L", |
7489 | CODE_LABEL_NUMBER (xoperands[1])); | |
cd0dfcc5 | 7490 | } |
7491 | else | |
7492 | /* ??? This branch may not reach its target. */ | |
7493 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 7494 | } |
ece88821 | 7495 | else |
7496 | /* ??? This branch may not reach its target. */ | |
7497 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 7498 | |
7499 | /* Delete the jump. */ | |
ad4583d9 | 7500 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 7501 | |
c7a4e712 | 7502 | return ""; |
7503 | } | |
7504 | ||
cd0dfcc5 | 7505 | /* Return the attribute length of the call instruction INSN. The SIBCALL |
7506 | flag indicates whether INSN is a regular call or a sibling call. The | |
faf3f8c1 | 7507 | length returned must be longer than the code actually generated by |
7508 | output_call. Since branch shortening is done before delay branch | |
7509 | sequencing, there is no way to determine whether or not the delay | |
7510 | slot will be filled during branch shortening. Even when the delay | |
7511 | slot is filled, we may have to add a nop if the delay slot contains | |
7512 | a branch that can't reach its target. Thus, we always have to include | |
7513 | the delay slot in the length estimate. This used to be done in | |
7514 | pa_adjust_insn_length but we do it here now as some sequences always | |
7515 | fill the delay slot and we can save four bytes in the estimate for | |
7516 | these sequences. */ | |
ece88821 | 7517 | |
7518 | int | |
5c1d8983 | 7519 | attr_length_call (rtx insn, int sibcall) |
ece88821 | 7520 | { |
faf3f8c1 | 7521 | int local_call; |
f7bb6501 | 7522 | rtx call, call_dest; |
faf3f8c1 | 7523 | tree call_decl; |
7524 | int length = 0; | |
7525 | rtx pat = PATTERN (insn); | |
cd0dfcc5 | 7526 | unsigned long distance = -1; |
ece88821 | 7527 | |
f7bb6501 | 7528 | gcc_assert (GET_CODE (insn) == CALL_INSN); |
7529 | ||
cd0dfcc5 | 7530 | if (INSN_ADDRESSES_SET_P ()) |
7531 | { | |
faf3f8c1 | 7532 | unsigned long total; |
7533 | ||
7534 | total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; | |
2247cc5f | 7535 | distance = (total + insn_current_reference_address (insn)); |
7536 | if (distance < total) | |
cd0dfcc5 | 7537 | distance = -1; |
7538 | } | |
ece88821 | 7539 | |
f7bb6501 | 7540 | gcc_assert (GET_CODE (pat) == PARALLEL); |
ece88821 | 7541 | |
f7bb6501 | 7542 | /* Get the call rtx. */ |
7543 | call = XVECEXP (pat, 0, 0); | |
7544 | if (GET_CODE (call) == SET) | |
7545 | call = SET_SRC (call); | |
7546 | ||
7547 | gcc_assert (GET_CODE (call) == CALL); | |
7548 | ||
7549 | /* Determine if this is a local call. */ | |
7550 | call_dest = XEXP (XEXP (call, 0), 0); | |
faf3f8c1 | 7551 | call_decl = SYMBOL_REF_DECL (call_dest); |
c5559ed4 | 7552 | local_call = call_decl && targetm.binds_local_p (call_decl); |
ece88821 | 7553 | |
faf3f8c1 | 7554 | /* pc-relative branch. */ |
7555 | if (!TARGET_LONG_CALLS | |
7556 | && ((TARGET_PA_20 && !sibcall && distance < 7600000) | |
7557 | || distance < 240000)) | |
7558 | length += 8; | |
ece88821 | 7559 | |
faf3f8c1 | 7560 | /* 64-bit plabel sequence. */ |
7561 | else if (TARGET_64BIT && !local_call) | |
7562 | length += sibcall ? 28 : 24; | |
ece88821 | 7563 | |
faf3f8c1 | 7564 | /* non-pic long absolute branch sequence. */ |
7565 | else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) | |
7566 | length += 12; | |
ece88821 | 7567 | |
faf3f8c1 | 7568 | /* long pc-relative branch sequence. */ |
feb01ed5 | 7569 | else if (TARGET_LONG_PIC_SDIFF_CALL |
ea24f9f4 | 7570 | || (TARGET_GAS && !TARGET_SOM |
7571 | && (TARGET_LONG_PIC_PCREL_CALL || local_call))) | |
faf3f8c1 | 7572 | { |
7573 | length += 20; | |
ece88821 | 7574 | |
226f6453 | 7575 | if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS && (!local_call || flag_pic)) |
faf3f8c1 | 7576 | length += 8; |
7577 | } | |
8a05c3c2 | 7578 | |
faf3f8c1 | 7579 | /* 32-bit plabel sequence. */ |
7580 | else | |
7581 | { | |
7582 | length += 32; | |
ece88821 | 7583 | |
faf3f8c1 | 7584 | if (TARGET_SOM) |
7585 | length += length_fp_args (insn); | |
7586 | ||
7587 | if (flag_pic) | |
7588 | length += 4; | |
ee376abe | 7589 | |
faf3f8c1 | 7590 | if (!TARGET_PA_20) |
7591 | { | |
ece88821 | 7592 | if (!sibcall) |
7593 | length += 8; | |
7594 | ||
226f6453 | 7595 | if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic)) |
faf3f8c1 | 7596 | length += 8; |
ece88821 | 7597 | } |
7598 | } | |
faf3f8c1 | 7599 | |
7600 | return length; | |
ece88821 | 7601 | } |
7602 | ||
7603 | /* INSN is a function call. It may have an unconditional jump | |
c7a4e712 | 7604 | in its delay slot. |
7605 | ||
7606 | CALL_DEST is the routine we are calling. */ | |
7607 | ||
611a88e1 | 7608 | const char * |
5c1d8983 | 7609 | output_call (rtx insn, rtx call_dest, int sibcall) |
c7a4e712 | 7610 | { |
ece88821 | 7611 | int delay_insn_deleted = 0; |
7612 | int delay_slot_filled = 0; | |
b70ea764 | 7613 | int seq_length = dbr_sequence_length (); |
2247cc5f | 7614 | tree call_decl = SYMBOL_REF_DECL (call_dest); |
c5559ed4 | 7615 | int local_call = call_decl && targetm.binds_local_p (call_decl); |
ece88821 | 7616 | rtx xoperands[2]; |
7617 | ||
7618 | xoperands[0] = call_dest; | |
c7a4e712 | 7619 | |
ece88821 | 7620 | /* Handle the common case where we're sure that the branch will reach |
2247cc5f | 7621 | the beginning of the "$CODE$" subspace. This is the beginning of |
7622 | the current function if we are in a named section. */ | |
cd0dfcc5 | 7623 | if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8) |
d6686e21 | 7624 | { |
5e3c5739 | 7625 | xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2); |
ece88821 | 7626 | output_asm_insn ("{bl|b,l} %0,%1", xoperands); |
06ddb6f8 | 7627 | } |
ece88821 | 7628 | else |
06ddb6f8 | 7629 | { |
2247cc5f | 7630 | if (TARGET_64BIT && !local_call) |
3683f840 | 7631 | { |
ece88821 | 7632 | /* ??? As far as I can tell, the HP linker doesn't support the |
7633 | long pc-relative sequence described in the 64-bit runtime | |
7634 | architecture. So, we use a slightly longer indirect call. */ | |
4e75439e | 7635 | xoperands[0] = get_deferred_plabel (call_dest); |
ece88821 | 7636 | xoperands[1] = gen_label_rtx (); |
7637 | ||
7638 | /* If this isn't a sibcall, we put the load of %r27 into the | |
7639 | delay slot. We can't do this in a sibcall as we don't | |
7640 | have a second call-clobbered scratch register available. */ | |
7641 | if (seq_length != 0 | |
7642 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7643 | && !sibcall) | |
7644 | { | |
7645 | final_scan_insn (NEXT_INSN (insn), asm_out_file, | |
4bf029b0 | 7646 | optimize, 0, NULL); |
ece88821 | 7647 | |
7648 | /* Now delete the delay insn. */ | |
ad4583d9 | 7649 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 7650 | delay_insn_deleted = 1; |
7651 | } | |
06ddb6f8 | 7652 | |
ece88821 | 7653 | output_asm_insn ("addil LT'%0,%%r27", xoperands); |
7654 | output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands); | |
7655 | output_asm_insn ("ldd 0(%%r1),%%r1", xoperands); | |
06ddb6f8 | 7656 | |
ece88821 | 7657 | if (sibcall) |
06ddb6f8 | 7658 | { |
ece88821 | 7659 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); |
7660 | output_asm_insn ("ldd 16(%%r1),%%r1", xoperands); | |
7661 | output_asm_insn ("bve (%%r1)", xoperands); | |
7662 | } | |
7663 | else | |
7664 | { | |
7665 | output_asm_insn ("ldd 16(%%r1),%%r2", xoperands); | |
7666 | output_asm_insn ("bve,l (%%r2),%%r2", xoperands); | |
7667 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); | |
7668 | delay_slot_filled = 1; | |
06ddb6f8 | 7669 | } |
7670 | } | |
ece88821 | 7671 | else |
e3f53689 | 7672 | { |
ece88821 | 7673 | int indirect_call = 0; |
7674 | ||
7675 | /* Emit a long call. There are several different sequences | |
7676 | of increasing length and complexity. In most cases, | |
7677 | they don't allow an instruction in the delay slot. */ | |
2247cc5f | 7678 | if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
feb01ed5 | 7679 | && !TARGET_LONG_PIC_SDIFF_CALL |
ea24f9f4 | 7680 | && !(TARGET_GAS && !TARGET_SOM |
7681 | && (TARGET_LONG_PIC_PCREL_CALL || local_call)) | |
2247cc5f | 7682 | && !TARGET_64BIT) |
ece88821 | 7683 | indirect_call = 1; |
7684 | ||
7685 | if (seq_length != 0 | |
7686 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7687 | && !sibcall | |
c4b36071 | 7688 | && (!TARGET_PA_20 |
7689 | || indirect_call | |
7690 | || ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic))) | |
5cc6b2bc | 7691 | { |
ece88821 | 7692 | /* A non-jump insn in the delay slot. By definition we can |
7693 | emit this insn before the call (and in fact before argument | |
7694 | relocating. */ | |
4bf029b0 | 7695 | final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, |
fbf5169c | 7696 | NULL); |
ece88821 | 7697 | |
7698 | /* Now delete the delay insn. */ | |
ad4583d9 | 7699 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 7700 | delay_insn_deleted = 1; |
5cc6b2bc | 7701 | } |
e3f53689 | 7702 | |
2247cc5f | 7703 | if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
5cc6b2bc | 7704 | { |
ece88821 | 7705 | /* This is the best sequence for making long calls in |
7706 | non-pic code. Unfortunately, GNU ld doesn't provide | |
7707 | the stub needed for external calls, and GAS's support | |
2247cc5f | 7708 | for this with the SOM linker is buggy. It is safe |
7709 | to use this for local calls. */ | |
ece88821 | 7710 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
7711 | if (sibcall) | |
7712 | output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands); | |
7713 | else | |
7714 | { | |
7715 | if (TARGET_PA_20) | |
7716 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", | |
7717 | xoperands); | |
7718 | else | |
7719 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); | |
c7a4e712 | 7720 | |
ece88821 | 7721 | output_asm_insn ("copy %%r31,%%r2", xoperands); |
7722 | delay_slot_filled = 1; | |
7723 | } | |
7724 | } | |
7725 | else | |
7726 | { | |
feb01ed5 | 7727 | if (TARGET_LONG_PIC_SDIFF_CALL) |
b70ea764 | 7728 | { |
ece88821 | 7729 | /* The HP assembler and linker can handle relocations |
feb01ed5 | 7730 | for the difference of two symbols. The HP assembler |
7731 | recognizes the sequence as a pc-relative call and | |
7732 | the linker provides stubs when needed. */ | |
ece88821 | 7733 | xoperands[1] = gen_label_rtx (); |
7734 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7735 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
c5559ed4 | 7736 | targetm.asm_out.internal_label (asm_out_file, "L", |
b70ea764 | 7737 | CODE_LABEL_NUMBER (xoperands[1])); |
ece88821 | 7738 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); |
7739 | } | |
ea24f9f4 | 7740 | else if (TARGET_GAS && !TARGET_SOM |
7741 | && (TARGET_LONG_PIC_PCREL_CALL || local_call)) | |
b70ea764 | 7742 | { |
ece88821 | 7743 | /* GAS currently can't generate the relocations that |
7744 | are needed for the SOM linker under HP-UX using this | |
7745 | sequence. The GNU linker doesn't generate the stubs | |
7746 | that are needed for external calls on TARGET_ELF32 | |
7747 | with this sequence. For now, we have to use a | |
7748 | longer plabel sequence when using GAS. */ | |
7749 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7750 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", | |
b70ea764 | 7751 | xoperands); |
ece88821 | 7752 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", |
b70ea764 | 7753 | xoperands); |
7754 | } | |
5e3c5739 | 7755 | else |
7756 | { | |
ece88821 | 7757 | /* Emit a long plabel-based call sequence. This is |
7758 | essentially an inline implementation of $$dyncall. | |
7759 | We don't actually try to call $$dyncall as this is | |
7760 | as difficult as calling the function itself. */ | |
4e75439e | 7761 | xoperands[0] = get_deferred_plabel (call_dest); |
ece88821 | 7762 | xoperands[1] = gen_label_rtx (); |
7763 | ||
7764 | /* Since the call is indirect, FP arguments in registers | |
7765 | need to be copied to the general registers. Then, the | |
7766 | argument relocation stub will copy them back. */ | |
7767 | if (TARGET_SOM) | |
7768 | copy_fp_args (insn); | |
7769 | ||
7770 | if (flag_pic) | |
7771 | { | |
7772 | output_asm_insn ("addil LT'%0,%%r19", xoperands); | |
7773 | output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands); | |
7774 | output_asm_insn ("ldw 0(%%r1),%%r1", xoperands); | |
7775 | } | |
7776 | else | |
7777 | { | |
7778 | output_asm_insn ("addil LR'%0-$global$,%%r27", | |
7779 | xoperands); | |
7780 | output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1", | |
7781 | xoperands); | |
7782 | } | |
06ddb6f8 | 7783 | |
ece88821 | 7784 | output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands); |
7785 | output_asm_insn ("depi 0,31,2,%%r1", xoperands); | |
7786 | output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands); | |
7787 | output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands); | |
c7a4e712 | 7788 | |
ece88821 | 7789 | if (!sibcall && !TARGET_PA_20) |
7790 | { | |
7791 | output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands); | |
226f6453 | 7792 | if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic)) |
ee376abe | 7793 | output_asm_insn ("addi 8,%%r2,%%r2", xoperands); |
7794 | else | |
7795 | output_asm_insn ("addi 16,%%r2,%%r2", xoperands); | |
ece88821 | 7796 | } |
7797 | } | |
c7a4e712 | 7798 | |
ece88821 | 7799 | if (TARGET_PA_20) |
5e3c5739 | 7800 | { |
ece88821 | 7801 | if (sibcall) |
7802 | output_asm_insn ("bve (%%r1)", xoperands); | |
7803 | else | |
7804 | { | |
7805 | if (indirect_call) | |
7806 | { | |
7807 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7808 | output_asm_insn ("stw %%r2,-24(%%sp)", xoperands); | |
7809 | delay_slot_filled = 1; | |
7810 | } | |
7811 | else | |
7812 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7813 | } | |
5e3c5739 | 7814 | } |
7815 | else | |
7816 | { | |
226f6453 | 7817 | if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic)) |
ee376abe | 7818 | output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0", |
7819 | xoperands); | |
06ddb6f8 | 7820 | |
ece88821 | 7821 | if (sibcall) |
ee376abe | 7822 | { |
226f6453 | 7823 | if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic)) |
ee376abe | 7824 | output_asm_insn ("be 0(%%sr4,%%r1)", xoperands); |
7825 | else | |
7826 | output_asm_insn ("be 0(%%sr0,%%r1)", xoperands); | |
7827 | } | |
ece88821 | 7828 | else |
7829 | { | |
226f6453 | 7830 | if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic)) |
ee376abe | 7831 | output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands); |
7832 | else | |
7833 | output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands); | |
06ddb6f8 | 7834 | |
ece88821 | 7835 | if (indirect_call) |
7836 | output_asm_insn ("stw %%r31,-24(%%sp)", xoperands); | |
7837 | else | |
7838 | output_asm_insn ("copy %%r31,%%r2", xoperands); | |
7839 | delay_slot_filled = 1; | |
7840 | } | |
7841 | } | |
7842 | } | |
06ddb6f8 | 7843 | } |
d6686e21 | 7844 | } |
6d36483b | 7845 | |
8a05c3c2 | 7846 | if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted)) |
ece88821 | 7847 | output_asm_insn ("nop", xoperands); |
d6686e21 | 7848 | |
ece88821 | 7849 | /* We are done if there isn't a jump in the delay slot. */ |
7850 | if (seq_length == 0 | |
7851 | || delay_insn_deleted | |
7852 | || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7853 | return ""; | |
d6686e21 | 7854 | |
ece88821 | 7855 | /* A sibcall should never have a branch in the delay slot. */ |
ecf2283d | 7856 | gcc_assert (!sibcall); |
d6686e21 | 7857 | |
ece88821 | 7858 | /* This call has an unconditional jump in its delay slot. */ |
7859 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
d6686e21 | 7860 | |
cd0dfcc5 | 7861 | if (!delay_slot_filled && INSN_ADDRESSES_SET_P ()) |
d6686e21 | 7862 | { |
ece88821 | 7863 | /* See if the return address can be adjusted. Use the containing |
1b448af3 | 7864 | sequence insn's address. This would break the regular call/return@ |
7865 | relationship assumed by the table based eh unwinder, so only do that | |
7866 | if the call is not possibly throwing. */ | |
ece88821 | 7867 | rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); |
7868 | int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7869 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7870 | ||
1b448af3 | 7871 | if (VAL_14_BITS_P (distance) |
7872 | && !(can_throw_internal (insn) || can_throw_external (insn))) | |
ece88821 | 7873 | { |
7874 | xoperands[1] = gen_label_rtx (); | |
7875 | output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands); | |
c5559ed4 | 7876 | targetm.asm_out.internal_label (asm_out_file, "L", |
7877 | CODE_LABEL_NUMBER (xoperands[1])); | |
ece88821 | 7878 | } |
7879 | else | |
ece88821 | 7880 | output_asm_insn ("nop\n\tb,n %0", xoperands); |
d6686e21 | 7881 | } |
ece88821 | 7882 | else |
ece88821 | 7883 | output_asm_insn ("b,n %0", xoperands); |
d6686e21 | 7884 | |
7885 | /* Delete the jump. */ | |
ad4583d9 | 7886 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 7887 | |
d6686e21 | 7888 | return ""; |
7889 | } | |
7890 | ||
cd0dfcc5 | 7891 | /* Return the attribute length of the indirect call instruction INSN. |
7892 | The length must match the code generated by output_indirect call. | |
7893 | The returned length includes the delay slot. Currently, the delay | |
7894 | slot of an indirect call sequence is not exposed and it is used by | |
7895 | the sequence itself. */ | |
7896 | ||
7897 | int | |
5c1d8983 | 7898 | attr_length_indirect_call (rtx insn) |
cd0dfcc5 | 7899 | { |
7900 | unsigned long distance = -1; | |
8a05c3c2 | 7901 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
cd0dfcc5 | 7902 | |
7903 | if (INSN_ADDRESSES_SET_P ()) | |
7904 | { | |
2247cc5f | 7905 | distance = (total + insn_current_reference_address (insn)); |
7906 | if (distance < total) | |
cd0dfcc5 | 7907 | distance = -1; |
7908 | } | |
7909 | ||
7910 | if (TARGET_64BIT) | |
7911 | return 12; | |
7912 | ||
7913 | if (TARGET_FAST_INDIRECT_CALLS | |
7914 | || (!TARGET_PORTABLE_RUNTIME | |
5925d47a | 7915 | && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000) |
7916 | || distance < 240000))) | |
cd0dfcc5 | 7917 | return 8; |
7918 | ||
7919 | if (flag_pic) | |
7920 | return 24; | |
7921 | ||
7922 | if (TARGET_PORTABLE_RUNTIME) | |
7923 | return 20; | |
7924 | ||
7925 | /* Out of reach, can use ble. */ | |
7926 | return 12; | |
7927 | } | |
7928 | ||
7929 | const char * | |
5c1d8983 | 7930 | output_indirect_call (rtx insn, rtx call_dest) |
cd0dfcc5 | 7931 | { |
7932 | rtx xoperands[1]; | |
7933 | ||
7934 | if (TARGET_64BIT) | |
7935 | { | |
7936 | xoperands[0] = call_dest; | |
7937 | output_asm_insn ("ldd 16(%0),%%r2", xoperands); | |
7938 | output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands); | |
7939 | return ""; | |
7940 | } | |
7941 | ||
7942 | /* First the special case for kernels, level 0 systems, etc. */ | |
7943 | if (TARGET_FAST_INDIRECT_CALLS) | |
7944 | return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2"; | |
7945 | ||
7946 | /* Now the normal case -- we can reach $$dyncall directly or | |
7947 | we're sure that we can get there via a long-branch stub. | |
7948 | ||
7949 | No need to check target flags as the length uniquely identifies | |
7950 | the remaining cases. */ | |
7951 | if (attr_length_indirect_call (insn) == 8) | |
f707acb9 | 7952 | { |
5925d47a | 7953 | /* The HP linker sometimes substitutes a BLE for BL/B,L calls to |
7954 | $$dyncall. Since BLE uses %r31 as the link register, the 22-bit | |
7955 | variant of the B,L instruction can't be used on the SOM target. */ | |
7956 | if (TARGET_PA_20 && !TARGET_SOM) | |
f707acb9 | 7957 | return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31"; |
7958 | else | |
7959 | return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2"; | |
7960 | } | |
cd0dfcc5 | 7961 | |
7962 | /* Long millicode call, but we are not generating PIC or portable runtime | |
7963 | code. */ | |
7964 | if (attr_length_indirect_call (insn) == 12) | |
7965 | return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2"; | |
7966 | ||
7967 | /* Long millicode call for portable runtime. */ | |
7968 | if (attr_length_indirect_call (insn) == 20) | |
7969 | return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop"; | |
7970 | ||
7971 | /* We need a long PIC call to $$dyncall. */ | |
7972 | xoperands[0] = NULL_RTX; | |
7973 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7974 | if (TARGET_SOM || !TARGET_GAS) | |
7975 | { | |
7976 | xoperands[0] = gen_label_rtx (); | |
7977 | output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands); | |
c5559ed4 | 7978 | targetm.asm_out.internal_label (asm_out_file, "L", |
7979 | CODE_LABEL_NUMBER (xoperands[0])); | |
cd0dfcc5 | 7980 | output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands); |
7981 | } | |
7982 | else | |
7983 | { | |
7984 | output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands); | |
7985 | output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1", | |
7986 | xoperands); | |
7987 | } | |
7988 | output_asm_insn ("blr %%r0,%%r2", xoperands); | |
7989 | output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands); | |
7990 | return ""; | |
7991 | } | |
7992 | ||
7993 | /* Return the total length of the save and restore instructions needed for | |
7994 | the data linkage table pointer (i.e., the PIC register) across the call | |
7995 | instruction INSN. No-return calls do not require a save and restore. | |
7996 | In addition, we may be able to avoid the save and restore for calls | |
7997 | within the same translation unit. */ | |
7998 | ||
7999 | int | |
5c1d8983 | 8000 | attr_length_save_restore_dltp (rtx insn) |
cd0dfcc5 | 8001 | { |
8002 | if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
8003 | return 0; | |
8004 | ||
8005 | return 8; | |
8006 | } | |
8007 | ||
d6f01525 | 8008 | /* In HPUX 8.0's shared library scheme, special relocations are needed |
6d36483b | 8009 | for function labels if they might be passed to a function |
d6f01525 | 8010 | in a shared library (because shared libraries don't live in code |
44acf429 | 8011 | space), and special magic is needed to construct their address. */ |
d6f01525 | 8012 | |
8013 | void | |
5c1d8983 | 8014 | hppa_encode_label (rtx sym) |
d6f01525 | 8015 | { |
611a88e1 | 8016 | const char *str = XSTR (sym, 0); |
cccfb31e | 8017 | int len = strlen (str) + 1; |
8018 | char *newstr, *p; | |
d6f01525 | 8019 | |
225ab426 | 8020 | p = newstr = XALLOCAVEC (char, len + 1); |
cccfb31e | 8021 | *p++ = '@'; |
8022 | strcpy (p, str); | |
74d80a9a | 8023 | |
ea52c577 | 8024 | XSTR (sym, 0) = ggc_alloc_string (newstr, len); |
d6f01525 | 8025 | } |
6d36483b | 8026 | |
7811991d | 8027 | static void |
5c1d8983 | 8028 | pa_encode_section_info (tree decl, rtx rtl, int first) |
7811991d | 8029 | { |
54d7a10c | 8030 | int old_referenced = 0; |
8031 | ||
8032 | if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF) | |
8033 | old_referenced | |
8034 | = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED; | |
8035 | ||
716b2c5a | 8036 | default_encode_section_info (decl, rtl, first); |
8037 | ||
7811991d | 8038 | if (first && TEXT_SPACE_P (decl)) |
8039 | { | |
7811991d | 8040 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
8041 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2c129d70 | 8042 | hppa_encode_label (XEXP (rtl, 0)); |
7811991d | 8043 | } |
54d7a10c | 8044 | else if (old_referenced) |
8045 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced; | |
7811991d | 8046 | } |
8047 | ||
7b4a38a6 | 8048 | /* This is sort of inverse to pa_encode_section_info. */ |
8049 | ||
8050 | static const char * | |
5c1d8983 | 8051 | pa_strip_name_encoding (const char *str) |
7b4a38a6 | 8052 | { |
c0264367 | 8053 | str += (*str == '@'); |
8054 | str += (*str == '*'); | |
8055 | return str; | |
7b4a38a6 | 8056 | } |
8057 | ||
d6f01525 | 8058 | int |
5c1d8983 | 8059 | function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d6f01525 | 8060 | { |
c1b3411e | 8061 | return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0)); |
d6f01525 | 8062 | } |
f33e3942 | 8063 | |
166bf021 | 8064 | /* Returns 1 if OP is a function label involved in a simple addition |
8065 | with a constant. Used to keep certain patterns from matching | |
8066 | during instruction combination. */ | |
8067 | int | |
5c1d8983 | 8068 | is_function_label_plus_const (rtx op) |
166bf021 | 8069 | { |
8070 | /* Strip off any CONST. */ | |
8071 | if (GET_CODE (op) == CONST) | |
8072 | op = XEXP (op, 0); | |
8073 | ||
8074 | return (GET_CODE (op) == PLUS | |
8075 | && function_label_operand (XEXP (op, 0), Pmode) | |
8076 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
8077 | } | |
8078 | ||
f1752b7e | 8079 | /* Output assembly code for a thunk to FUNCTION. */ |
8080 | ||
6988553d | 8081 | static void |
5c1d8983 | 8082 | pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, |
8083 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
8084 | tree function) | |
f1752b7e | 8085 | { |
e678758c | 8086 | static unsigned int current_thunk_number; |
2247cc5f | 8087 | int val_14 = VAL_14_BITS_P (delta); |
21a47bc9 | 8088 | unsigned int old_last_address = last_address, nbytes = 0; |
f1752b7e | 8089 | char label[16]; |
e678758c | 8090 | rtx xoperands[4]; |
2247cc5f | 8091 | |
e678758c | 8092 | xoperands[0] = XEXP (DECL_RTL (function), 0); |
8093 | xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0); | |
8094 | xoperands[2] = GEN_INT (delta); | |
2247cc5f | 8095 | |
e678758c | 8096 | ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0)); |
8097 | fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); | |
2247cc5f | 8098 | |
8099 | /* Output the thunk. We know that the function is in the same | |
8100 | translation unit (i.e., the same space) as the thunk, and that | |
8101 | thunks are output after their method. Thus, we don't need an | |
8102 | external branch to reach the function. With SOM and GAS, | |
8103 | functions and thunks are effectively in different sections. | |
8104 | Thus, we can always use a IA-relative branch and the linker | |
8105 | will add a long branch stub if necessary. | |
8106 | ||
8107 | However, we have to be careful when generating PIC code on the | |
8108 | SOM port to ensure that the sequence does not transfer to an | |
8109 | import stub for the target function as this could clobber the | |
8110 | return value saved at SP-24. This would also apply to the | |
8111 | 32-bit linux port if the multi-space model is implemented. */ | |
8112 | if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
8113 | && !(flag_pic && TREE_PUBLIC (function)) | |
8114 | && (TARGET_GAS || last_address < 262132)) | |
8115 | || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
8116 | && ((targetm.have_named_sections | |
8117 | && DECL_SECTION_NAME (thunk_fndecl) != NULL | |
8118 | /* The GNU 64-bit linker has rather poor stub management. | |
8119 | So, we use a long branch from thunks that aren't in | |
8120 | the same section as the target function. */ | |
8121 | && ((!TARGET_64BIT | |
8122 | && (DECL_SECTION_NAME (thunk_fndecl) | |
8123 | != DECL_SECTION_NAME (function))) | |
8124 | || ((DECL_SECTION_NAME (thunk_fndecl) | |
8125 | == DECL_SECTION_NAME (function)) | |
8126 | && last_address < 262132))) | |
55e0e460 | 8127 | || (targetm.have_named_sections |
8128 | && DECL_SECTION_NAME (thunk_fndecl) == NULL | |
8129 | && DECL_SECTION_NAME (function) == NULL | |
8130 | && last_address < 262132) | |
2247cc5f | 8131 | || (!targetm.have_named_sections && last_address < 262132)))) |
8132 | { | |
e678758c | 8133 | if (!val_14) |
8134 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8135 | ||
8136 | output_asm_insn ("b %0", xoperands); | |
8137 | ||
2247cc5f | 8138 | if (val_14) |
8139 | { | |
e678758c | 8140 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8141 | nbytes += 8; |
8142 | } | |
8143 | else | |
8144 | { | |
e678758c | 8145 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8146 | nbytes += 12; |
8147 | } | |
8148 | } | |
8149 | else if (TARGET_64BIT) | |
8150 | { | |
8151 | /* We only have one call-clobbered scratch register, so we can't | |
8152 | make use of the delay slot if delta doesn't fit in 14 bits. */ | |
8153 | if (!val_14) | |
e678758c | 8154 | { |
8155 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8156 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); | |
8157 | } | |
2247cc5f | 8158 | |
e678758c | 8159 | output_asm_insn ("b,l .+8,%%r1", xoperands); |
2247cc5f | 8160 | |
8161 | if (TARGET_GAS) | |
8162 | { | |
e678758c | 8163 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
8164 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
2247cc5f | 8165 | } |
8166 | else | |
8167 | { | |
e678758c | 8168 | xoperands[3] = GEN_INT (val_14 ? 8 : 16); |
8169 | output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands); | |
2247cc5f | 8170 | } |
8171 | ||
8172 | if (val_14) | |
8173 | { | |
e678758c | 8174 | output_asm_insn ("bv %%r0(%%r1)", xoperands); |
8175 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); | |
2247cc5f | 8176 | nbytes += 20; |
8177 | } | |
8178 | else | |
8179 | { | |
e678758c | 8180 | output_asm_insn ("bv,n %%r0(%%r1)", xoperands); |
2247cc5f | 8181 | nbytes += 24; |
8182 | } | |
8183 | } | |
8184 | else if (TARGET_PORTABLE_RUNTIME) | |
8185 | { | |
e678758c | 8186 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
8187 | output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands); | |
8188 | ||
8189 | if (!val_14) | |
8190 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8191 | ||
8192 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
2247cc5f | 8193 | |
8194 | if (val_14) | |
8195 | { | |
e678758c | 8196 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8197 | nbytes += 16; |
8198 | } | |
8199 | else | |
8200 | { | |
e678758c | 8201 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8202 | nbytes += 20; |
8203 | } | |
8204 | } | |
8205 | else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
8206 | { | |
8207 | /* The function is accessible from outside this module. The only | |
8208 | way to avoid an import stub between the thunk and function is to | |
8209 | call the function directly with an indirect sequence similar to | |
8210 | that used by $$dyncall. This is possible because $$dyncall acts | |
8211 | as the import stub in an indirect call. */ | |
2247cc5f | 8212 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number); |
e678758c | 8213 | xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label); |
8214 | output_asm_insn ("addil LT'%3,%%r19", xoperands); | |
8215 | output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands); | |
8216 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
8217 | output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands); | |
8218 | output_asm_insn ("depi 0,31,2,%%r22", xoperands); | |
8219 | output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands); | |
8220 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
8221 | ||
2247cc5f | 8222 | if (!val_14) |
8223 | { | |
e678758c | 8224 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
2247cc5f | 8225 | nbytes += 4; |
8226 | } | |
e678758c | 8227 | |
2247cc5f | 8228 | if (TARGET_PA_20) |
8229 | { | |
e678758c | 8230 | output_asm_insn ("bve (%%r22)", xoperands); |
8231 | nbytes += 36; | |
8232 | } | |
8233 | else if (TARGET_NO_SPACE_REGS) | |
8234 | { | |
8235 | output_asm_insn ("be 0(%%sr4,%%r22)", xoperands); | |
2247cc5f | 8236 | nbytes += 36; |
8237 | } | |
8238 | else | |
f1752b7e | 8239 | { |
e678758c | 8240 | output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands); |
8241 | output_asm_insn ("mtsp %%r21,%%sr0", xoperands); | |
8242 | output_asm_insn ("be 0(%%sr0,%%r22)", xoperands); | |
8243 | nbytes += 44; | |
2247cc5f | 8244 | } |
8245 | ||
8246 | if (val_14) | |
e678758c | 8247 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8248 | else |
e678758c | 8249 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8250 | } |
8251 | else if (flag_pic) | |
8252 | { | |
e678758c | 8253 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
2247cc5f | 8254 | |
8255 | if (TARGET_SOM || !TARGET_GAS) | |
8256 | { | |
e678758c | 8257 | output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands); |
8258 | output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands); | |
2247cc5f | 8259 | } |
8260 | else | |
8261 | { | |
e678758c | 8262 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
8263 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands); | |
2247cc5f | 8264 | } |
8265 | ||
e678758c | 8266 | if (!val_14) |
8267 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8268 | ||
8269 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
8270 | ||
2247cc5f | 8271 | if (val_14) |
8272 | { | |
e678758c | 8273 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8274 | nbytes += 20; |
f1752b7e | 8275 | } |
8276 | else | |
2247cc5f | 8277 | { |
e678758c | 8278 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8279 | nbytes += 24; |
8280 | } | |
f1752b7e | 8281 | } |
8282 | else | |
8283 | { | |
2247cc5f | 8284 | if (!val_14) |
e678758c | 8285 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
2247cc5f | 8286 | |
e678758c | 8287 | output_asm_insn ("ldil L'%0,%%r22", xoperands); |
8288 | output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands); | |
2247cc5f | 8289 | |
8290 | if (val_14) | |
f1752b7e | 8291 | { |
e678758c | 8292 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8293 | nbytes += 12; |
f1752b7e | 8294 | } |
8295 | else | |
2247cc5f | 8296 | { |
e678758c | 8297 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8298 | nbytes += 16; |
8299 | } | |
f1752b7e | 8300 | } |
2247cc5f | 8301 | |
f1752b7e | 8302 | fprintf (file, "\t.EXIT\n\t.PROCEND\n"); |
2247cc5f | 8303 | |
78962d38 | 8304 | if (TARGET_SOM && TARGET_GAS) |
8305 | { | |
8306 | /* We done with this subspace except possibly for some additional | |
8307 | debug information. Forget that we are in this subspace to ensure | |
8308 | that the next function is output in its own subspace. */ | |
8309 | in_section = NULL; | |
8310 | cfun->machine->in_nsubspa = 2; | |
8311 | } | |
8312 | ||
2247cc5f | 8313 | if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) |
f1752b7e | 8314 | { |
2f14b1f9 | 8315 | switch_to_section (data_section); |
e678758c | 8316 | output_asm_insn (".align 4", xoperands); |
2247cc5f | 8317 | ASM_OUTPUT_LABEL (file, label); |
e678758c | 8318 | output_asm_insn (".word P'%0", xoperands); |
f1752b7e | 8319 | } |
2247cc5f | 8320 | |
f1752b7e | 8321 | current_thunk_number++; |
2247cc5f | 8322 | nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) |
8323 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
8324 | last_address += nbytes; | |
21a47bc9 | 8325 | if (old_last_address > last_address) |
8326 | last_address = UINT_MAX; | |
2247cc5f | 8327 | update_total_code_bytes (nbytes); |
f1752b7e | 8328 | } |
8329 | ||
805e22b2 | 8330 | /* Only direct calls to static functions are allowed to be sibling (tail) |
8331 | call optimized. | |
8332 | ||
8333 | This restriction is necessary because some linker generated stubs will | |
8334 | store return pointers into rp' in some cases which might clobber a | |
8335 | live value already in rp'. | |
8336 | ||
8337 | In a sibcall the current function and the target function share stack | |
8338 | space. Thus if the path to the current function and the path to the | |
8339 | target function save a value in rp', they save the value into the | |
8340 | same stack slot, which has undesirable consequences. | |
8341 | ||
8342 | Because of the deferred binding nature of shared libraries any function | |
8343 | with external scope could be in a different load module and thus require | |
8344 | rp' to be saved when calling that function. So sibcall optimizations | |
8345 | can only be safe for static function. | |
8346 | ||
8347 | Note that GCC never needs return value relocations, so we don't have to | |
8348 | worry about static calls with return value relocations (which require | |
8349 | saving rp'). | |
8350 | ||
8351 | It is safe to perform a sibcall optimization when the target function | |
8352 | will never return. */ | |
8353 | static bool | |
5c1d8983 | 8354 | pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
805e22b2 | 8355 | { |
e11e9ae3 | 8356 | if (TARGET_PORTABLE_RUNTIME) |
8357 | return false; | |
8358 | ||
f62b73b6 | 8359 | /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in |
8360 | single subspace mode and the call is not indirect. As far as I know, | |
8361 | there is no operating system support for the multiple subspace mode. | |
8362 | It might be possible to support indirect calls if we didn't use | |
8363 | $$dyncall (see the indirect sequence generated in output_call). */ | |
8364 | if (TARGET_ELF32) | |
8365 | return (decl != NULL_TREE); | |
8366 | ||
8367 | /* Sibcalls are not ok because the arg pointer register is not a fixed | |
2cecd772 | 8368 | register. This prevents the sibcall optimization from occurring. In |
f62b73b6 | 8369 | addition, there are problems with stub placement using GNU ld. This |
8370 | is because a normal sibcall branch uses a 17-bit relocation while | |
8371 | a regular call branch uses a 22-bit relocation. As a result, more | |
8372 | care needs to be taken in the placement of long-branch stubs. */ | |
8373 | if (TARGET_64BIT) | |
8374 | return false; | |
8375 | ||
e11e9ae3 | 8376 | /* Sibcalls are only ok within a translation unit. */ |
8377 | return (decl && !TREE_PUBLIC (decl)); | |
805e22b2 | 8378 | } |
8379 | ||
280566a7 | 8380 | /* ??? Addition is not commutative on the PA due to the weird implicit |
8381 | space register selection rules for memory addresses. Therefore, we | |
8382 | don't consider a + b == b + a, as this might be inside a MEM. */ | |
8383 | static bool | |
a9f1838b | 8384 | pa_commutative_p (const_rtx x, int outer_code) |
280566a7 | 8385 | { |
8386 | return (COMMUTATIVE_P (x) | |
55e3fa6d | 8387 | && (TARGET_NO_SPACE_REGS |
8388 | || (outer_code != UNKNOWN && outer_code != MEM) | |
280566a7 | 8389 | || GET_CODE (x) != PLUS)); |
8390 | } | |
8391 | ||
37580c80 | 8392 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
8393 | use in fmpyadd instructions. */ | |
4ed6ee50 | 8394 | int |
5c1d8983 | 8395 | fmpyaddoperands (rtx *operands) |
4ed6ee50 | 8396 | { |
201f01e9 | 8397 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 8398 | |
ab449421 | 8399 | /* Must be a floating point mode. */ |
8400 | if (mode != SFmode && mode != DFmode) | |
8401 | return 0; | |
8402 | ||
4ed6ee50 | 8403 | /* All modes must be the same. */ |
201f01e9 | 8404 | if (! (mode == GET_MODE (operands[1]) |
8405 | && mode == GET_MODE (operands[2]) | |
8406 | && mode == GET_MODE (operands[3]) | |
8407 | && mode == GET_MODE (operands[4]) | |
8408 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 8409 | return 0; |
8410 | ||
ab449421 | 8411 | /* All operands must be registers. */ |
8412 | if (! (GET_CODE (operands[1]) == REG | |
8413 | && GET_CODE (operands[2]) == REG | |
8414 | && GET_CODE (operands[3]) == REG | |
8415 | && GET_CODE (operands[4]) == REG | |
8416 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 8417 | return 0; |
8418 | ||
37580c80 | 8419 | /* Only 2 real operands to the addition. One of the input operands must |
8420 | be the same as the output operand. */ | |
4ed6ee50 | 8421 | if (! rtx_equal_p (operands[3], operands[4]) |
8422 | && ! rtx_equal_p (operands[3], operands[5])) | |
8423 | return 0; | |
8424 | ||
33f88b1c | 8425 | /* Inout operand of add cannot conflict with any operands from multiply. */ |
4ed6ee50 | 8426 | if (rtx_equal_p (operands[3], operands[0]) |
8427 | || rtx_equal_p (operands[3], operands[1]) | |
8428 | || rtx_equal_p (operands[3], operands[2])) | |
8429 | return 0; | |
8430 | ||
33f88b1c | 8431 | /* multiply cannot feed into addition operands. */ |
4ed6ee50 | 8432 | if (rtx_equal_p (operands[4], operands[0]) |
8433 | || rtx_equal_p (operands[5], operands[0])) | |
8434 | return 0; | |
8435 | ||
ab449421 | 8436 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8437 | if (mode == SFmode | |
bac38c40 | 8438 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8439 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8440 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8441 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8442 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8443 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 8444 | return 0; |
8445 | ||
4ed6ee50 | 8446 | /* Passed. Operands are suitable for fmpyadd. */ |
8447 | return 1; | |
8448 | } | |
8449 | ||
de419443 | 8450 | #if !defined(USE_COLLECT2) |
8451 | static void | |
5c1d8983 | 8452 | pa_asm_out_constructor (rtx symbol, int priority) |
de419443 | 8453 | { |
8454 | if (!function_label_operand (symbol, VOIDmode)) | |
8455 | hppa_encode_label (symbol); | |
8456 | ||
8457 | #ifdef CTORS_SECTION_ASM_OP | |
8458 | default_ctor_section_asm_out_constructor (symbol, priority); | |
8459 | #else | |
8460 | # ifdef TARGET_ASM_NAMED_SECTION | |
8461 | default_named_section_asm_out_constructor (symbol, priority); | |
8462 | # else | |
8463 | default_stabs_asm_out_constructor (symbol, priority); | |
8464 | # endif | |
8465 | #endif | |
8466 | } | |
8467 | ||
8468 | static void | |
5c1d8983 | 8469 | pa_asm_out_destructor (rtx symbol, int priority) |
de419443 | 8470 | { |
8471 | if (!function_label_operand (symbol, VOIDmode)) | |
8472 | hppa_encode_label (symbol); | |
8473 | ||
8474 | #ifdef DTORS_SECTION_ASM_OP | |
8475 | default_dtor_section_asm_out_destructor (symbol, priority); | |
8476 | #else | |
8477 | # ifdef TARGET_ASM_NAMED_SECTION | |
8478 | default_named_section_asm_out_destructor (symbol, priority); | |
8479 | # else | |
8480 | default_stabs_asm_out_destructor (symbol, priority); | |
8481 | # endif | |
8482 | #endif | |
8483 | } | |
8484 | #endif | |
8485 | ||
ff59d376 | 8486 | /* This function places uninitialized global data in the bss section. |
8487 | The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this | |
8488 | function on the SOM port to prevent uninitialized global data from | |
8489 | being placed in the data section. */ | |
8490 | ||
8491 | void | |
8492 | pa_asm_output_aligned_bss (FILE *stream, | |
8493 | const char *name, | |
8494 | unsigned HOST_WIDE_INT size, | |
8495 | unsigned int align) | |
8496 | { | |
2f14b1f9 | 8497 | switch_to_section (bss_section); |
ff59d376 | 8498 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); |
8499 | ||
8500 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
8501 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); | |
8502 | #endif | |
8503 | ||
8504 | #ifdef ASM_OUTPUT_SIZE_DIRECTIVE | |
8505 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
8506 | #endif | |
8507 | ||
8508 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); | |
8509 | ASM_OUTPUT_LABEL (stream, name); | |
8510 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
8511 | } | |
8512 | ||
8513 | /* Both the HP and GNU assemblers under HP-UX provide a .comm directive | |
8514 | that doesn't allow the alignment of global common storage to be directly | |
8515 | specified. The SOM linker aligns common storage based on the rounded | |
8516 | value of the NUM_BYTES parameter in the .comm directive. It's not | |
8517 | possible to use the .align directive as it doesn't affect the alignment | |
8518 | of the label associated with a .comm directive. */ | |
8519 | ||
8520 | void | |
8521 | pa_asm_output_aligned_common (FILE *stream, | |
8522 | const char *name, | |
8523 | unsigned HOST_WIDE_INT size, | |
8524 | unsigned int align) | |
8525 | { | |
33cd7888 | 8526 | unsigned int max_common_align; |
8527 | ||
8528 | max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64); | |
8529 | if (align > max_common_align) | |
8530 | { | |
c3ceba8e | 8531 | warning (0, "alignment (%u) for %s exceeds maximum alignment " |
33cd7888 | 8532 | "for global common data. Using %u", |
8533 | align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT); | |
8534 | align = max_common_align; | |
8535 | } | |
8536 | ||
2f14b1f9 | 8537 | switch_to_section (bss_section); |
ff59d376 | 8538 | |
8539 | assemble_name (stream, name); | |
8540 | fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n", | |
8541 | MAX (size, align / BITS_PER_UNIT)); | |
8542 | } | |
8543 | ||
8544 | /* We can't use .comm for local common storage as the SOM linker effectively | |
8545 | treats the symbol as universal and uses the same storage for local symbols | |
8546 | with the same name in different object files. The .block directive | |
8547 | reserves an uninitialized block of storage. However, it's not common | |
8548 | storage. Fortunately, GCC never requests common storage with the same | |
8549 | name in any given translation unit. */ | |
8550 | ||
8551 | void | |
8552 | pa_asm_output_aligned_local (FILE *stream, | |
8553 | const char *name, | |
8554 | unsigned HOST_WIDE_INT size, | |
8555 | unsigned int align) | |
8556 | { | |
2f14b1f9 | 8557 | switch_to_section (bss_section); |
ff59d376 | 8558 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); |
8559 | ||
8560 | #ifdef LOCAL_ASM_OP | |
8561 | fprintf (stream, "%s", LOCAL_ASM_OP); | |
8562 | assemble_name (stream, name); | |
8563 | fprintf (stream, "\n"); | |
8564 | #endif | |
8565 | ||
8566 | ASM_OUTPUT_LABEL (stream, name); | |
8567 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
8568 | } | |
8569 | ||
37580c80 | 8570 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
8571 | use in fmpysub instructions. */ | |
4ed6ee50 | 8572 | int |
5c1d8983 | 8573 | fmpysuboperands (rtx *operands) |
4ed6ee50 | 8574 | { |
201f01e9 | 8575 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 8576 | |
ab449421 | 8577 | /* Must be a floating point mode. */ |
8578 | if (mode != SFmode && mode != DFmode) | |
8579 | return 0; | |
8580 | ||
4ed6ee50 | 8581 | /* All modes must be the same. */ |
201f01e9 | 8582 | if (! (mode == GET_MODE (operands[1]) |
8583 | && mode == GET_MODE (operands[2]) | |
8584 | && mode == GET_MODE (operands[3]) | |
8585 | && mode == GET_MODE (operands[4]) | |
8586 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 8587 | return 0; |
8588 | ||
ab449421 | 8589 | /* All operands must be registers. */ |
8590 | if (! (GET_CODE (operands[1]) == REG | |
8591 | && GET_CODE (operands[2]) == REG | |
8592 | && GET_CODE (operands[3]) == REG | |
8593 | && GET_CODE (operands[4]) == REG | |
8594 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 8595 | return 0; |
8596 | ||
37580c80 | 8597 | /* Only 2 real operands to the subtraction. Subtraction is not a commutative |
8598 | operation, so operands[4] must be the same as operand[3]. */ | |
4ed6ee50 | 8599 | if (! rtx_equal_p (operands[3], operands[4])) |
8600 | return 0; | |
8601 | ||
33f88b1c | 8602 | /* multiply cannot feed into subtraction. */ |
37580c80 | 8603 | if (rtx_equal_p (operands[5], operands[0])) |
4ed6ee50 | 8604 | return 0; |
8605 | ||
33f88b1c | 8606 | /* Inout operand of sub cannot conflict with any operands from multiply. */ |
4ed6ee50 | 8607 | if (rtx_equal_p (operands[3], operands[0]) |
8608 | || rtx_equal_p (operands[3], operands[1]) | |
8609 | || rtx_equal_p (operands[3], operands[2])) | |
8610 | return 0; | |
8611 | ||
ab449421 | 8612 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8613 | if (mode == SFmode | |
bac38c40 | 8614 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8615 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8616 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8617 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8618 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8619 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 8620 | return 0; |
8621 | ||
4ed6ee50 | 8622 | /* Passed. Operands are suitable for fmpysub. */ |
8623 | return 1; | |
8624 | } | |
8625 | ||
6720f95e | 8626 | /* Return 1 if the given constant is 2, 4, or 8. These are the valid |
8627 | constants for shadd instructions. */ | |
913de4b4 | 8628 | int |
5c1d8983 | 8629 | shadd_constant_p (int val) |
6720f95e | 8630 | { |
8631 | if (val == 2 || val == 4 || val == 8) | |
8632 | return 1; | |
8633 | else | |
8634 | return 0; | |
8635 | } | |
3a16146d | 8636 | |
dbd3d89d | 8637 | /* Return 1 if OP is valid as a base or index register in a |
8638 | REG+REG address. */ | |
42819d4e | 8639 | |
8640 | int | |
dbd3d89d | 8641 | borx_reg_operand (rtx op, enum machine_mode mode) |
42819d4e | 8642 | { |
dbd3d89d | 8643 | if (GET_CODE (op) != REG) |
21f3ee9c | 8644 | return 0; |
8645 | ||
dbd3d89d | 8646 | /* We must reject virtual registers as the only expressions that |
8647 | can be instantiated are REG and REG+CONST. */ | |
8648 | if (op == virtual_incoming_args_rtx | |
8649 | || op == virtual_stack_vars_rtx | |
8650 | || op == virtual_stack_dynamic_rtx | |
8651 | || op == virtual_outgoing_args_rtx | |
8652 | || op == virtual_cfa_rtx) | |
8653 | return 0; | |
42819d4e | 8654 | |
21f3ee9c | 8655 | /* While it's always safe to index off the frame pointer, it's not |
dbd3d89d | 8656 | profitable to do so when the frame pointer is being eliminated. */ |
8657 | if (!reload_completed | |
8658 | && flag_omit_frame_pointer | |
18d50ae6 | 8659 | && !cfun->calls_alloca |
dbd3d89d | 8660 | && op == frame_pointer_rtx) |
8661 | return 0; | |
42819d4e | 8662 | |
dbd3d89d | 8663 | return register_operand (op, mode); |
42819d4e | 8664 | } |
8665 | ||
51987f90 | 8666 | /* Return 1 if this operand is anything other than a hard register. */ |
8667 | ||
8668 | int | |
5c1d8983 | 8669 | non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
51987f90 | 8670 | { |
8671 | return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER); | |
8672 | } | |
8673 | ||
372b3fe2 | 8674 | /* Return TRUE if INSN branches forward. */ |
8675 | ||
8676 | static bool | |
5c1d8983 | 8677 | forward_branch_p (rtx insn) |
5fbd5940 | 8678 | { |
372b3fe2 | 8679 | rtx lab = JUMP_LABEL (insn); |
8680 | ||
8681 | /* The INSN must have a jump label. */ | |
8682 | gcc_assert (lab != NULL_RTX); | |
8683 | ||
8684 | if (INSN_ADDRESSES_SET_P ()) | |
8685 | return INSN_ADDRESSES (INSN_UID (lab)) > INSN_ADDRESSES (INSN_UID (insn)); | |
5fbd5940 | 8686 | |
8687 | while (insn) | |
8688 | { | |
372b3fe2 | 8689 | if (insn == lab) |
8690 | return true; | |
5fbd5940 | 8691 | else |
8692 | insn = NEXT_INSN (insn); | |
8693 | } | |
8694 | ||
372b3fe2 | 8695 | return false; |
5fbd5940 | 8696 | } |
8697 | ||
29a4502c | 8698 | /* Return 1 if OP is an equality comparison, else return 0. */ |
8699 | int | |
5c1d8983 | 8700 | eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
29a4502c | 8701 | { |
8702 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
8703 | } | |
8704 | ||
d6686e21 | 8705 | /* Return 1 if INSN is in the delay slot of a call instruction. */ |
8706 | int | |
5c1d8983 | 8707 | jump_in_call_delay (rtx insn) |
d6686e21 | 8708 | { |
8709 | ||
8710 | if (GET_CODE (insn) != JUMP_INSN) | |
8711 | return 0; | |
8712 | ||
8713 | if (PREV_INSN (insn) | |
8714 | && PREV_INSN (PREV_INSN (insn)) | |
ece0fa59 | 8715 | && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN) |
d6686e21 | 8716 | { |
ece0fa59 | 8717 | rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn))); |
d6686e21 | 8718 | |
8719 | return (GET_CODE (PATTERN (test_insn)) == SEQUENCE | |
8720 | && XVECEXP (PATTERN (test_insn), 0, 1) == insn); | |
8721 | ||
8722 | } | |
8723 | else | |
8724 | return 0; | |
8725 | } | |
3b1e673e | 8726 | |
546a40bd | 8727 | /* Output an unconditional move and branch insn. */ |
8728 | ||
611a88e1 | 8729 | const char * |
f26036bb | 8730 | output_parallel_movb (rtx *operands, rtx insn) |
546a40bd | 8731 | { |
f26036bb | 8732 | int length = get_attr_length (insn); |
8733 | ||
546a40bd | 8734 | /* These are the cases in which we win. */ |
8735 | if (length == 4) | |
8736 | return "mov%I1b,tr %1,%0,%2"; | |
8737 | ||
f26036bb | 8738 | /* None of the following cases win, but they don't lose either. */ |
8739 | if (length == 8) | |
546a40bd | 8740 | { |
f26036bb | 8741 | if (dbr_sequence_length () == 0) |
8742 | { | |
8743 | /* Nothing in the delay slot, fake it by putting the combined | |
8744 | insn (the copy or add) in the delay slot of a bl. */ | |
8745 | if (GET_CODE (operands[1]) == CONST_INT) | |
8746 | return "b %2\n\tldi %1,%0"; | |
8747 | else | |
8748 | return "b %2\n\tcopy %1,%0"; | |
8749 | } | |
546a40bd | 8750 | else |
f26036bb | 8751 | { |
8752 | /* Something in the delay slot, but we've got a long branch. */ | |
8753 | if (GET_CODE (operands[1]) == CONST_INT) | |
8754 | return "ldi %1,%0\n\tb %2"; | |
8755 | else | |
8756 | return "copy %1,%0\n\tb %2"; | |
8757 | } | |
546a40bd | 8758 | } |
f26036bb | 8759 | |
8760 | if (GET_CODE (operands[1]) == CONST_INT) | |
8761 | output_asm_insn ("ldi %1,%0", operands); | |
546a40bd | 8762 | else |
f26036bb | 8763 | output_asm_insn ("copy %1,%0", operands); |
8764 | return output_lbranch (operands[2], insn, 1); | |
546a40bd | 8765 | } |
8766 | ||
8767 | /* Output an unconditional add and branch insn. */ | |
8768 | ||
611a88e1 | 8769 | const char * |
f26036bb | 8770 | output_parallel_addb (rtx *operands, rtx insn) |
546a40bd | 8771 | { |
f26036bb | 8772 | int length = get_attr_length (insn); |
8773 | ||
546a40bd | 8774 | /* To make life easy we want operand0 to be the shared input/output |
8775 | operand and operand1 to be the readonly operand. */ | |
8776 | if (operands[0] == operands[1]) | |
8777 | operands[1] = operands[2]; | |
8778 | ||
8779 | /* These are the cases in which we win. */ | |
8780 | if (length == 4) | |
8781 | return "add%I1b,tr %1,%0,%3"; | |
8782 | ||
f26036bb | 8783 | /* None of the following cases win, but they don't lose either. */ |
8784 | if (length == 8) | |
546a40bd | 8785 | { |
f26036bb | 8786 | if (dbr_sequence_length () == 0) |
8787 | /* Nothing in the delay slot, fake it by putting the combined | |
8788 | insn (the copy or add) in the delay slot of a bl. */ | |
8789 | return "b %3\n\tadd%I1 %1,%0,%0"; | |
8790 | else | |
8791 | /* Something in the delay slot, but we've got a long branch. */ | |
8792 | return "add%I1 %1,%0,%0\n\tb %3"; | |
546a40bd | 8793 | } |
f26036bb | 8794 | |
8795 | output_asm_insn ("add%I1 %1,%0,%0", operands); | |
8796 | return output_lbranch (operands[3], insn, 1); | |
546a40bd | 8797 | } |
8798 | ||
7c5101fc | 8799 | /* Return nonzero if INSN (a jump insn) immediately follows a call |
8800 | to a named function. This is used to avoid filling the delay slot | |
8801 | of the jump since it can usually be eliminated by modifying RP in | |
8802 | the delay slot of the call. */ | |
9840d99d | 8803 | |
7d27e4c9 | 8804 | int |
5c1d8983 | 8805 | following_call (rtx insn) |
546a40bd | 8806 | { |
ed1b0769 | 8807 | if (! TARGET_JUMP_IN_DELAY) |
1b6f11e2 | 8808 | return 0; |
8809 | ||
546a40bd | 8810 | /* Find the previous real insn, skipping NOTEs. */ |
8811 | insn = PREV_INSN (insn); | |
8812 | while (insn && GET_CODE (insn) == NOTE) | |
8813 | insn = PREV_INSN (insn); | |
8814 | ||
8815 | /* Check for CALL_INSNs and millicode calls. */ | |
8816 | if (insn | |
1d2e016c | 8817 | && ((GET_CODE (insn) == CALL_INSN |
8818 | && get_attr_type (insn) != TYPE_DYNCALL) | |
546a40bd | 8819 | || (GET_CODE (insn) == INSN |
8820 | && GET_CODE (PATTERN (insn)) != SEQUENCE | |
8821 | && GET_CODE (PATTERN (insn)) != USE | |
8822 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8823 | && get_attr_type (insn) == TYPE_MILLI))) | |
8824 | return 1; | |
8825 | ||
8826 | return 0; | |
8827 | } | |
8828 | ||
3b1e673e | 8829 | /* We use this hook to perform a PA specific optimization which is difficult |
8830 | to do in earlier passes. | |
8831 | ||
8832 | We want the delay slots of branches within jump tables to be filled. | |
8833 | None of the compiler passes at the moment even has the notion that a | |
8834 | PA jump table doesn't contain addresses, but instead contains actual | |
8835 | instructions! | |
8836 | ||
8837 | Because we actually jump into the table, the addresses of each entry | |
01cc3b75 | 8838 | must stay constant in relation to the beginning of the table (which |
3b1e673e | 8839 | itself must stay constant relative to the instruction to jump into |
8840 | it). I don't believe we can guarantee earlier passes of the compiler | |
8841 | will adhere to those rules. | |
8842 | ||
8843 | So, late in the compilation process we find all the jump tables, and | |
a361b456 | 8844 | expand them into real code -- e.g. each entry in the jump table vector |
3b1e673e | 8845 | will get an appropriate label followed by a jump to the final target. |
8846 | ||
8847 | Reorg and the final jump pass can then optimize these branches and | |
8848 | fill their delay slots. We end up with smaller, more efficient code. | |
8849 | ||
9840d99d | 8850 | The jump instructions within the table are special; we must be able |
3b1e673e | 8851 | to identify them during assembly output (if the jumps don't get filled |
8852 | we need to emit a nop rather than nullifying the delay slot)). We | |
b932f66c | 8853 | identify jumps in switch tables by using insns with the attribute |
8854 | type TYPE_BTABLE_BRANCH. | |
9239127b | 8855 | |
8856 | We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB | |
8857 | insns. This serves two purposes, first it prevents jump.c from | |
8858 | noticing that the last N entries in the table jump to the instruction | |
8859 | immediately after the table and deleting the jumps. Second, those | |
8860 | insns mark where we should emit .begin_brtab and .end_brtab directives | |
8861 | when using GAS (allows for better link time optimizations). */ | |
3b1e673e | 8862 | |
2efea8c0 | 8863 | static void |
5c1d8983 | 8864 | pa_reorg (void) |
3b1e673e | 8865 | { |
8866 | rtx insn; | |
8867 | ||
2efea8c0 | 8868 | remove_useless_addtr_insns (1); |
3d457930 | 8869 | |
342aabd9 | 8870 | if (pa_cpu < PROCESSOR_8000) |
2efea8c0 | 8871 | pa_combine_instructions (); |
342aabd9 | 8872 | |
bd49d362 | 8873 | |
3d457930 | 8874 | /* This is fairly cheap, so always run it if optimizing. */ |
a66555b2 | 8875 | if (optimize > 0 && !TARGET_BIG_SWITCH) |
3b1e673e | 8876 | { |
b41266d4 | 8877 | /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */ |
2efea8c0 | 8878 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
3b1e673e | 8879 | { |
b932f66c | 8880 | rtx pattern, tmp, location, label; |
3b1e673e | 8881 | unsigned int length, i; |
8882 | ||
b41266d4 | 8883 | /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */ |
3b1e673e | 8884 | if (GET_CODE (insn) != JUMP_INSN |
b41266d4 | 8885 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8886 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
3b1e673e | 8887 | continue; |
8888 | ||
9239127b | 8889 | /* Emit marker for the beginning of the branch table. */ |
8890 | emit_insn_before (gen_begin_brtab (), insn); | |
f9333726 | 8891 | |
3b1e673e | 8892 | pattern = PATTERN (insn); |
8893 | location = PREV_INSN (insn); | |
b41266d4 | 8894 | length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC); |
f9333726 | 8895 | |
3b1e673e | 8896 | for (i = 0; i < length; i++) |
8897 | { | |
a66555b2 | 8898 | /* Emit a label before each jump to keep jump.c from |
8899 | removing this code. */ | |
8900 | tmp = gen_label_rtx (); | |
8901 | LABEL_NUSES (tmp) = 1; | |
8902 | emit_label_after (tmp, location); | |
8903 | location = NEXT_INSN (location); | |
8904 | ||
b41266d4 | 8905 | if (GET_CODE (pattern) == ADDR_VEC) |
b932f66c | 8906 | label = XEXP (XVECEXP (pattern, 0, i), 0); |
b41266d4 | 8907 | else |
b932f66c | 8908 | label = XEXP (XVECEXP (pattern, 1, i), 0); |
8909 | ||
8910 | tmp = gen_short_jump (label); | |
8911 | ||
8912 | /* Emit the jump itself. */ | |
8913 | tmp = emit_jump_insn_after (tmp, location); | |
8914 | JUMP_LABEL (tmp) = label; | |
8915 | LABEL_NUSES (label)++; | |
8916 | location = NEXT_INSN (location); | |
3b1e673e | 8917 | |
8918 | /* Emit a BARRIER after the jump. */ | |
3b1e673e | 8919 | emit_barrier_after (location); |
3b1e673e | 8920 | location = NEXT_INSN (location); |
8921 | } | |
f9333726 | 8922 | |
9239127b | 8923 | /* Emit marker for the end of the branch table. */ |
8924 | emit_insn_before (gen_end_brtab (), location); | |
8925 | location = NEXT_INSN (location); | |
8926 | emit_barrier_after (location); | |
a66555b2 | 8927 | |
b41266d4 | 8928 | /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */ |
3b1e673e | 8929 | delete_insn (insn); |
8930 | } | |
8931 | } | |
9239127b | 8932 | else |
f9333726 | 8933 | { |
b932f66c | 8934 | /* Still need brtab marker insns. FIXME: the presence of these |
8935 | markers disables output of the branch table to readonly memory, | |
8936 | and any alignment directives that might be needed. Possibly, | |
8937 | the begin_brtab insn should be output before the label for the | |
7bd28bba | 8938 | table. This doesn't matter at the moment since the tables are |
b932f66c | 8939 | always output in the text section. */ |
2efea8c0 | 8940 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
f9333726 | 8941 | { |
8942 | /* Find an ADDR_VEC insn. */ | |
8943 | if (GET_CODE (insn) != JUMP_INSN | |
b41266d4 | 8944 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8945 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
f9333726 | 8946 | continue; |
8947 | ||
8948 | /* Now generate markers for the beginning and end of the | |
ad87de1e | 8949 | branch table. */ |
f9333726 | 8950 | emit_insn_before (gen_begin_brtab (), insn); |
8951 | emit_insn_after (gen_end_brtab (), insn); | |
8952 | } | |
8953 | } | |
d3287673 | 8954 | } |
bd49d362 | 8955 | |
8956 | /* The PA has a number of odd instructions which can perform multiple | |
8957 | tasks at once. On first generation PA machines (PA1.0 and PA1.1) | |
8958 | it may be profitable to combine two instructions into one instruction | |
8959 | with two outputs. It's not profitable PA2.0 machines because the | |
8960 | two outputs would take two slots in the reorder buffers. | |
8961 | ||
8962 | This routine finds instructions which can be combined and combines | |
8963 | them. We only support some of the potential combinations, and we | |
8964 | only try common ways to find suitable instructions. | |
8965 | ||
8966 | * addb can add two registers or a register and a small integer | |
8967 | and jump to a nearby (+-8k) location. Normally the jump to the | |
8968 | nearby location is conditional on the result of the add, but by | |
8969 | using the "true" condition we can make the jump unconditional. | |
8970 | Thus addb can perform two independent operations in one insn. | |
8971 | ||
8972 | * movb is similar to addb in that it can perform a reg->reg | |
8973 | or small immediate->reg copy and jump to a nearby (+-8k location). | |
8974 | ||
8975 | * fmpyadd and fmpysub can perform a FP multiply and either an | |
8976 | FP add or FP sub if the operands of the multiply and add/sub are | |
8977 | independent (there are other minor restrictions). Note both | |
8978 | the fmpy and fadd/fsub can in theory move to better spots according | |
8979 | to data dependencies, but for now we require the fmpy stay at a | |
8980 | fixed location. | |
8981 | ||
8982 | * Many of the memory operations can perform pre & post updates | |
8983 | of index registers. GCC's pre/post increment/decrement addressing | |
8984 | is far too simple to take advantage of all the possibilities. This | |
8985 | pass may not be suitable since those insns may not be independent. | |
8986 | ||
8987 | * comclr can compare two ints or an int and a register, nullify | |
8988 | the following instruction and zero some other register. This | |
8989 | is more difficult to use as it's harder to find an insn which | |
8990 | will generate a comclr than finding something like an unconditional | |
8991 | branch. (conditional moves & long branches create comclr insns). | |
8992 | ||
8993 | * Most arithmetic operations can conditionally skip the next | |
8994 | instruction. They can be viewed as "perform this operation | |
8995 | and conditionally jump to this nearby location" (where nearby | |
8996 | is an insns away). These are difficult to use due to the | |
8997 | branch length restrictions. */ | |
8998 | ||
7d27e4c9 | 8999 | static void |
5c1d8983 | 9000 | pa_combine_instructions (void) |
bd49d362 | 9001 | { |
8deb3959 | 9002 | rtx anchor, new_rtx; |
bd49d362 | 9003 | |
9004 | /* This can get expensive since the basic algorithm is on the | |
9005 | order of O(n^2) (or worse). Only do it for -O2 or higher | |
ad87de1e | 9006 | levels of optimization. */ |
bd49d362 | 9007 | if (optimize < 2) |
9008 | return; | |
9009 | ||
9010 | /* Walk down the list of insns looking for "anchor" insns which | |
9011 | may be combined with "floating" insns. As the name implies, | |
9012 | "anchor" instructions don't move, while "floating" insns may | |
9013 | move around. */ | |
8deb3959 | 9014 | new_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX)); |
9015 | new_rtx = make_insn_raw (new_rtx); | |
bd49d362 | 9016 | |
9017 | for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor)) | |
9018 | { | |
9019 | enum attr_pa_combine_type anchor_attr; | |
9020 | enum attr_pa_combine_type floater_attr; | |
9021 | ||
9022 | /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs. | |
9023 | Also ignore any special USE insns. */ | |
7d27e4c9 | 9024 | if ((GET_CODE (anchor) != INSN |
bd49d362 | 9025 | && GET_CODE (anchor) != JUMP_INSN |
7d27e4c9 | 9026 | && GET_CODE (anchor) != CALL_INSN) |
bd49d362 | 9027 | || GET_CODE (PATTERN (anchor)) == USE |
9028 | || GET_CODE (PATTERN (anchor)) == CLOBBER | |
9029 | || GET_CODE (PATTERN (anchor)) == ADDR_VEC | |
9030 | || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC) | |
9031 | continue; | |
9032 | ||
9033 | anchor_attr = get_attr_pa_combine_type (anchor); | |
9034 | /* See if anchor is an insn suitable for combination. */ | |
9035 | if (anchor_attr == PA_COMBINE_TYPE_FMPY | |
9036 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9037 | || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
9038 | && ! forward_branch_p (anchor))) | |
9039 | { | |
9040 | rtx floater; | |
9041 | ||
9042 | for (floater = PREV_INSN (anchor); | |
9043 | floater; | |
9044 | floater = PREV_INSN (floater)) | |
9045 | { | |
9046 | if (GET_CODE (floater) == NOTE | |
9047 | || (GET_CODE (floater) == INSN | |
9048 | && (GET_CODE (PATTERN (floater)) == USE | |
9049 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
9050 | continue; | |
9051 | ||
9052 | /* Anything except a regular INSN will stop our search. */ | |
9053 | if (GET_CODE (floater) != INSN | |
9054 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
9055 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
9056 | { | |
9057 | floater = NULL_RTX; | |
9058 | break; | |
9059 | } | |
9060 | ||
9061 | /* See if FLOATER is suitable for combination with the | |
9062 | anchor. */ | |
9063 | floater_attr = get_attr_pa_combine_type (floater); | |
9064 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
9065 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
9066 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9067 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
9068 | { | |
9069 | /* If ANCHOR and FLOATER can be combined, then we're | |
9070 | done with this pass. */ | |
8deb3959 | 9071 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
bd49d362 | 9072 | SET_DEST (PATTERN (floater)), |
9073 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
9074 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
9075 | break; | |
9076 | } | |
9077 | ||
9078 | else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
9079 | && floater_attr == PA_COMBINE_TYPE_ADDMOVE) | |
9080 | { | |
9081 | if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS) | |
9082 | { | |
8deb3959 | 9083 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
bd49d362 | 9084 | SET_DEST (PATTERN (floater)), |
9085 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
9086 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
9087 | break; | |
9088 | } | |
9089 | else | |
9090 | { | |
8deb3959 | 9091 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
bd49d362 | 9092 | SET_DEST (PATTERN (floater)), |
9093 | SET_SRC (PATTERN (floater)), | |
9094 | SET_SRC (PATTERN (floater)))) | |
9095 | break; | |
9096 | } | |
9097 | } | |
9098 | } | |
9099 | ||
9100 | /* If we didn't find anything on the backwards scan try forwards. */ | |
9101 | if (!floater | |
9102 | && (anchor_attr == PA_COMBINE_TYPE_FMPY | |
9103 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB)) | |
9104 | { | |
9105 | for (floater = anchor; floater; floater = NEXT_INSN (floater)) | |
9106 | { | |
9107 | if (GET_CODE (floater) == NOTE | |
9108 | || (GET_CODE (floater) == INSN | |
9109 | && (GET_CODE (PATTERN (floater)) == USE | |
9110 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
9840d99d | 9111 | |
bd49d362 | 9112 | continue; |
9113 | ||
9114 | /* Anything except a regular INSN will stop our search. */ | |
9115 | if (GET_CODE (floater) != INSN | |
9116 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
9117 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
9118 | { | |
9119 | floater = NULL_RTX; | |
9120 | break; | |
9121 | } | |
9122 | ||
9123 | /* See if FLOATER is suitable for combination with the | |
9124 | anchor. */ | |
9125 | floater_attr = get_attr_pa_combine_type (floater); | |
9126 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
9127 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
9128 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9129 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
9130 | { | |
9131 | /* If ANCHOR and FLOATER can be combined, then we're | |
9132 | done with this pass. */ | |
8deb3959 | 9133 | if (pa_can_combine_p (new_rtx, anchor, floater, 1, |
bd49d362 | 9134 | SET_DEST (PATTERN (floater)), |
ea52c577 | 9135 | XEXP (SET_SRC (PATTERN (floater)), |
9136 | 0), | |
9137 | XEXP (SET_SRC (PATTERN (floater)), | |
9138 | 1))) | |
bd49d362 | 9139 | break; |
9140 | } | |
9141 | } | |
9142 | } | |
9143 | ||
9144 | /* FLOATER will be nonzero if we found a suitable floating | |
9145 | insn for combination with ANCHOR. */ | |
9146 | if (floater | |
9147 | && (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9148 | || anchor_attr == PA_COMBINE_TYPE_FMPY)) | |
9149 | { | |
9150 | /* Emit the new instruction and delete the old anchor. */ | |
7014838c | 9151 | emit_insn_before (gen_rtx_PARALLEL |
9152 | (VOIDmode, | |
9153 | gen_rtvec (2, PATTERN (anchor), | |
9154 | PATTERN (floater))), | |
9155 | anchor); | |
9156 | ||
ad4583d9 | 9157 | SET_INSN_DELETED (anchor); |
bd49d362 | 9158 | |
9159 | /* Emit a special USE insn for FLOATER, then delete | |
9160 | the floating insn. */ | |
ad851752 | 9161 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 9162 | delete_insn (floater); |
9163 | ||
9164 | continue; | |
9165 | } | |
9166 | else if (floater | |
9167 | && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH) | |
9168 | { | |
9169 | rtx temp; | |
9170 | /* Emit the new_jump instruction and delete the old anchor. */ | |
7014838c | 9171 | temp |
9172 | = emit_jump_insn_before (gen_rtx_PARALLEL | |
9173 | (VOIDmode, | |
9174 | gen_rtvec (2, PATTERN (anchor), | |
9175 | PATTERN (floater))), | |
9176 | anchor); | |
9177 | ||
bd49d362 | 9178 | JUMP_LABEL (temp) = JUMP_LABEL (anchor); |
ad4583d9 | 9179 | SET_INSN_DELETED (anchor); |
bd49d362 | 9180 | |
9181 | /* Emit a special USE insn for FLOATER, then delete | |
9182 | the floating insn. */ | |
ad851752 | 9183 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 9184 | delete_insn (floater); |
9185 | continue; | |
9186 | } | |
9187 | } | |
9188 | } | |
9189 | } | |
9190 | ||
9aadea62 | 9191 | static int |
8deb3959 | 9192 | pa_can_combine_p (rtx new_rtx, rtx anchor, rtx floater, int reversed, rtx dest, |
5c1d8983 | 9193 | rtx src1, rtx src2) |
bd49d362 | 9194 | { |
9195 | int insn_code_number; | |
9196 | rtx start, end; | |
9197 | ||
9198 | /* Create a PARALLEL with the patterns of ANCHOR and | |
9199 | FLOATER, try to recognize it, then test constraints | |
9200 | for the resulting pattern. | |
9201 | ||
9202 | If the pattern doesn't match or the constraints | |
9203 | aren't met keep searching for a suitable floater | |
9204 | insn. */ | |
8deb3959 | 9205 | XVECEXP (PATTERN (new_rtx), 0, 0) = PATTERN (anchor); |
9206 | XVECEXP (PATTERN (new_rtx), 0, 1) = PATTERN (floater); | |
9207 | INSN_CODE (new_rtx) = -1; | |
9208 | insn_code_number = recog_memoized (new_rtx); | |
bd49d362 | 9209 | if (insn_code_number < 0 |
8deb3959 | 9210 | || (extract_insn (new_rtx), ! constrain_operands (1))) |
bd49d362 | 9211 | return 0; |
9212 | ||
9213 | if (reversed) | |
9214 | { | |
9215 | start = anchor; | |
9216 | end = floater; | |
9217 | } | |
9218 | else | |
9219 | { | |
9220 | start = floater; | |
9221 | end = anchor; | |
9222 | } | |
9223 | ||
9224 | /* There's up to three operands to consider. One | |
9225 | output and two inputs. | |
9226 | ||
9227 | The output must not be used between FLOATER & ANCHOR | |
9228 | exclusive. The inputs must not be set between | |
9229 | FLOATER and ANCHOR exclusive. */ | |
9230 | ||
9231 | if (reg_used_between_p (dest, start, end)) | |
9232 | return 0; | |
9233 | ||
9234 | if (reg_set_between_p (src1, start, end)) | |
9235 | return 0; | |
9236 | ||
9237 | if (reg_set_between_p (src2, start, end)) | |
9238 | return 0; | |
9239 | ||
9240 | /* If we get here, then everything is good. */ | |
9241 | return 1; | |
9242 | } | |
14d18de3 | 9243 | |
a6582a53 | 9244 | /* Return nonzero if references for INSN are delayed. |
14d18de3 | 9245 | |
9246 | Millicode insns are actually function calls with some special | |
9247 | constraints on arguments and register usage. | |
9248 | ||
9249 | Millicode calls always expect their arguments in the integer argument | |
9250 | registers, and always return their result in %r29 (ret1). They | |
2013ddf6 | 9251 | are expected to clobber their arguments, %r1, %r29, and the return |
9252 | pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else. | |
9253 | ||
9254 | This function tells reorg that the references to arguments and | |
9255 | millicode calls do not appear to happen until after the millicode call. | |
9256 | This allows reorg to put insns which set the argument registers into the | |
9257 | delay slot of the millicode call -- thus they act more like traditional | |
9258 | CALL_INSNs. | |
9259 | ||
33f88b1c | 9260 | Note we cannot consider side effects of the insn to be delayed because |
2013ddf6 | 9261 | the branch and link insn will clobber the return pointer. If we happened |
9262 | to use the return pointer in the delay slot of the call, then we lose. | |
14d18de3 | 9263 | |
9264 | get_attr_type will try to recognize the given insn, so make sure to | |
9265 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
9266 | in particular. */ | |
9267 | int | |
5c1d8983 | 9268 | insn_refs_are_delayed (rtx insn) |
14d18de3 | 9269 | { |
9840d99d | 9270 | return ((GET_CODE (insn) == INSN |
14d18de3 | 9271 | && GET_CODE (PATTERN (insn)) != SEQUENCE |
9272 | && GET_CODE (PATTERN (insn)) != USE | |
9273 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
9274 | && get_attr_type (insn) == TYPE_MILLI)); | |
9275 | } | |
5cb4669a | 9276 | |
3b2411a8 | 9277 | /* Promote the return value, but not the arguments. */ |
9278 | ||
a6b21a58 | 9279 | static enum machine_mode |
3b2411a8 | 9280 | pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, |
9281 | enum machine_mode mode, | |
9282 | int *punsignedp ATTRIBUTE_UNUSED, | |
9283 | const_tree fntype ATTRIBUTE_UNUSED, | |
9284 | int for_return) | |
9285 | { | |
c879dbcf | 9286 | if (for_return == 0) |
3b2411a8 | 9287 | return mode; |
a6b21a58 | 9288 | return promote_mode (type, mode, punsignedp); |
3b2411a8 | 9289 | } |
9290 | ||
58a72cce | 9291 | /* On the HP-PA the value is found in register(s) 28(-29), unless |
9292 | the mode is SF or DF. Then the value is returned in fr4 (32). | |
9293 | ||
3b2411a8 | 9294 | This must perform the same promotions as PROMOTE_MODE, else promoting |
9295 | return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly. | |
58a72cce | 9296 | |
9297 | Small structures must be returned in a PARALLEL on PA64 in order | |
9298 | to match the HP Compiler ABI. */ | |
9299 | ||
93d3ee56 | 9300 | static rtx |
cb0b8817 | 9301 | pa_function_value (const_tree valtype, |
9302 | const_tree func ATTRIBUTE_UNUSED, | |
9303 | bool outgoing ATTRIBUTE_UNUSED) | |
58a72cce | 9304 | { |
9305 | enum machine_mode valmode; | |
9306 | ||
4779159e | 9307 | if (AGGREGATE_TYPE_P (valtype) |
9308 | || TREE_CODE (valtype) == COMPLEX_TYPE | |
9309 | || TREE_CODE (valtype) == VECTOR_TYPE) | |
58a72cce | 9310 | { |
b105ef41 | 9311 | if (TARGET_64BIT) |
9312 | { | |
9313 | /* Aggregates with a size less than or equal to 128 bits are | |
9314 | returned in GR 28(-29). They are left justified. The pad | |
9315 | bits are undefined. Larger aggregates are returned in | |
9316 | memory. */ | |
9317 | rtx loc[2]; | |
9318 | int i, offset = 0; | |
9319 | int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2; | |
9320 | ||
9321 | for (i = 0; i < ub; i++) | |
9322 | { | |
9323 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
9324 | gen_rtx_REG (DImode, 28 + i), | |
9325 | GEN_INT (offset)); | |
9326 | offset += 8; | |
9327 | } | |
58a72cce | 9328 | |
b105ef41 | 9329 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc)); |
9330 | } | |
9331 | else if (int_size_in_bytes (valtype) > UNITS_PER_WORD) | |
58a72cce | 9332 | { |
b105ef41 | 9333 | /* Aggregates 5 to 8 bytes in size are returned in general |
9334 | registers r28-r29 in the same manner as other non | |
9335 | floating-point objects. The data is right-justified and | |
9336 | zero-extended to 64 bits. This is opposite to the normal | |
9337 | justification used on big endian targets and requires | |
9338 | special treatment. */ | |
9339 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, | |
9340 | gen_rtx_REG (DImode, 28), const0_rtx); | |
9341 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc)); | |
58a72cce | 9342 | } |
58a72cce | 9343 | } |
9344 | ||
9345 | if ((INTEGRAL_TYPE_P (valtype) | |
eb46b0b6 | 9346 | && GET_MODE_BITSIZE (TYPE_MODE (valtype)) < BITS_PER_WORD) |
58a72cce | 9347 | || POINTER_TYPE_P (valtype)) |
9348 | valmode = word_mode; | |
9349 | else | |
9350 | valmode = TYPE_MODE (valtype); | |
9351 | ||
9352 | if (TREE_CODE (valtype) == REAL_TYPE | |
b105ef41 | 9353 | && !AGGREGATE_TYPE_P (valtype) |
58a72cce | 9354 | && TYPE_MODE (valtype) != TFmode |
9355 | && !TARGET_SOFT_FLOAT) | |
9356 | return gen_rtx_REG (valmode, 32); | |
9357 | ||
9358 | return gen_rtx_REG (valmode, 28); | |
9359 | } | |
9360 | ||
93d3ee56 | 9361 | /* Implement the TARGET_LIBCALL_VALUE hook. */ |
9362 | ||
9363 | static rtx | |
9364 | pa_libcall_value (enum machine_mode mode, | |
9365 | const_rtx fun ATTRIBUTE_UNUSED) | |
9366 | { | |
9367 | if (! TARGET_SOFT_FLOAT | |
9368 | && (mode == SFmode || mode == DFmode)) | |
9369 | return gen_rtx_REG (mode, 32); | |
9370 | else | |
9371 | return gen_rtx_REG (mode, 28); | |
9372 | } | |
9373 | ||
9374 | /* Implement the TARGET_FUNCTION_VALUE_REGNO_P hook. */ | |
9375 | ||
9376 | static bool | |
9377 | pa_function_value_regno_p (const unsigned int regno) | |
9378 | { | |
9379 | if (regno == 28 | |
9380 | || (! TARGET_SOFT_FLOAT && regno == 32)) | |
9381 | return true; | |
9382 | ||
9383 | return false; | |
9384 | } | |
9385 | ||
5e3c5739 | 9386 | /* Return the location of a parameter that is passed in a register or NULL |
9387 | if the parameter has any component that is passed in memory. | |
9388 | ||
9389 | This is new code and will be pushed to into the net sources after | |
9840d99d | 9390 | further testing. |
5e3c5739 | 9391 | |
9392 | ??? We might want to restructure this so that it looks more like other | |
9393 | ports. */ | |
9394 | rtx | |
5c1d8983 | 9395 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, |
9396 | int named ATTRIBUTE_UNUSED) | |
5e3c5739 | 9397 | { |
9398 | int max_arg_words = (TARGET_64BIT ? 8 : 4); | |
2a075f91 | 9399 | int alignment = 0; |
ac965869 | 9400 | int arg_size; |
5e3c5739 | 9401 | int fpr_reg_base; |
9402 | int gpr_reg_base; | |
9403 | rtx retval; | |
9404 | ||
ac965869 | 9405 | if (mode == VOIDmode) |
9406 | return NULL_RTX; | |
9407 | ||
9408 | arg_size = FUNCTION_ARG_SIZE (mode, type); | |
9409 | ||
9410 | /* If this arg would be passed partially or totally on the stack, then | |
f054eb3c | 9411 | this routine should return zero. pa_arg_partial_bytes will |
ac965869 | 9412 | handle arguments which are split between regs and stack slots if |
9413 | the ABI mandates split arguments. */ | |
4779159e | 9414 | if (!TARGET_64BIT) |
5e3c5739 | 9415 | { |
ac965869 | 9416 | /* The 32-bit ABI does not split arguments. */ |
9417 | if (cum->words + arg_size > max_arg_words) | |
5e3c5739 | 9418 | return NULL_RTX; |
9419 | } | |
9420 | else | |
9421 | { | |
2a075f91 | 9422 | if (arg_size > 1) |
9423 | alignment = cum->words & 1; | |
ac965869 | 9424 | if (cum->words + alignment >= max_arg_words) |
5e3c5739 | 9425 | return NULL_RTX; |
9426 | } | |
9427 | ||
9428 | /* The 32bit ABIs and the 64bit ABIs are rather different, | |
9429 | particularly in their handling of FP registers. We might | |
9430 | be able to cleverly share code between them, but I'm not | |
9aadea62 | 9431 | going to bother in the hope that splitting them up results |
2a075f91 | 9432 | in code that is more easily understood. */ |
5e3c5739 | 9433 | |
5e3c5739 | 9434 | if (TARGET_64BIT) |
9435 | { | |
9436 | /* Advance the base registers to their current locations. | |
9437 | ||
9438 | Remember, gprs grow towards smaller register numbers while | |
2a075f91 | 9439 | fprs grow to higher register numbers. Also remember that |
9440 | although FP regs are 32-bit addressable, we pretend that | |
9441 | the registers are 64-bits wide. */ | |
5e3c5739 | 9442 | gpr_reg_base = 26 - cum->words; |
9443 | fpr_reg_base = 32 + cum->words; | |
9840d99d | 9444 | |
ac965869 | 9445 | /* Arguments wider than one word and small aggregates need special |
9446 | treatment. */ | |
9447 | if (arg_size > 1 | |
9448 | || mode == BLKmode | |
4779159e | 9449 | || (type && (AGGREGATE_TYPE_P (type) |
9450 | || TREE_CODE (type) == COMPLEX_TYPE | |
9451 | || TREE_CODE (type) == VECTOR_TYPE))) | |
5e3c5739 | 9452 | { |
2a075f91 | 9453 | /* Double-extended precision (80-bit), quad-precision (128-bit) |
9454 | and aggregates including complex numbers are aligned on | |
9455 | 128-bit boundaries. The first eight 64-bit argument slots | |
9456 | are associated one-to-one, with general registers r26 | |
9457 | through r19, and also with floating-point registers fr4 | |
9458 | through fr11. Arguments larger than one word are always | |
ac965869 | 9459 | passed in general registers. |
9460 | ||
9461 | Using a PARALLEL with a word mode register results in left | |
9462 | justified data on a big-endian target. */ | |
2a075f91 | 9463 | |
9464 | rtx loc[8]; | |
9465 | int i, offset = 0, ub = arg_size; | |
9466 | ||
9467 | /* Align the base register. */ | |
9468 | gpr_reg_base -= alignment; | |
9469 | ||
9470 | ub = MIN (ub, max_arg_words - cum->words - alignment); | |
9471 | for (i = 0; i < ub; i++) | |
5e3c5739 | 9472 | { |
2a075f91 | 9473 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, |
9474 | gen_rtx_REG (DImode, gpr_reg_base), | |
9475 | GEN_INT (offset)); | |
9476 | gpr_reg_base -= 1; | |
9477 | offset += 8; | |
5e3c5739 | 9478 | } |
2a075f91 | 9479 | |
e2810de9 | 9480 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc)); |
5e3c5739 | 9481 | } |
ac965869 | 9482 | } |
5e3c5739 | 9483 | else |
9484 | { | |
9485 | /* If the argument is larger than a word, then we know precisely | |
9486 | which registers we must use. */ | |
2a075f91 | 9487 | if (arg_size > 1) |
5e3c5739 | 9488 | { |
9489 | if (cum->words) | |
9490 | { | |
9491 | gpr_reg_base = 23; | |
9492 | fpr_reg_base = 38; | |
9493 | } | |
9494 | else | |
9495 | { | |
9496 | gpr_reg_base = 25; | |
9497 | fpr_reg_base = 34; | |
9498 | } | |
ac965869 | 9499 | |
9500 | /* Structures 5 to 8 bytes in size are passed in the general | |
9501 | registers in the same manner as other non floating-point | |
9502 | objects. The data is right-justified and zero-extended | |
9f0b40a7 | 9503 | to 64 bits. This is opposite to the normal justification |
9504 | used on big endian targets and requires special treatment. | |
4779159e | 9505 | We now define BLOCK_REG_PADDING to pad these objects. |
9506 | Aggregates, complex and vector types are passed in the same | |
9507 | manner as structures. */ | |
9508 | if (mode == BLKmode | |
9509 | || (type && (AGGREGATE_TYPE_P (type) | |
9510 | || TREE_CODE (type) == COMPLEX_TYPE | |
9511 | || TREE_CODE (type) == VECTOR_TYPE))) | |
ac965869 | 9512 | { |
58a72cce | 9513 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, |
9514 | gen_rtx_REG (DImode, gpr_reg_base), | |
9515 | const0_rtx); | |
b105ef41 | 9516 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc)); |
ac965869 | 9517 | } |
5e3c5739 | 9518 | } |
9519 | else | |
9520 | { | |
9521 | /* We have a single word (32 bits). A simple computation | |
9522 | will get us the register #s we need. */ | |
9523 | gpr_reg_base = 26 - cum->words; | |
9524 | fpr_reg_base = 32 + 2 * cum->words; | |
9525 | } | |
9526 | } | |
9527 | ||
9503b0f7 | 9528 | /* Determine if the argument needs to be passed in both general and |
5e3c5739 | 9529 | floating point registers. */ |
9503b0f7 | 9530 | if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32) |
9531 | /* If we are doing soft-float with portable runtime, then there | |
9532 | is no need to worry about FP regs. */ | |
f336e0bc | 9533 | && !TARGET_SOFT_FLOAT |
4779159e | 9534 | /* The parameter must be some kind of scalar float, else we just |
9503b0f7 | 9535 | pass it in integer registers. */ |
4779159e | 9536 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
9503b0f7 | 9537 | /* The target function must not have a prototype. */ |
9538 | && cum->nargs_prototype <= 0 | |
9539 | /* libcalls do not need to pass items in both FP and general | |
9540 | registers. */ | |
9541 | && type != NULL_TREE | |
f336e0bc | 9542 | /* All this hair applies to "outgoing" args only. This includes |
9543 | sibcall arguments setup with FUNCTION_INCOMING_ARG. */ | |
9544 | && !cum->incoming) | |
9503b0f7 | 9545 | /* Also pass outgoing floating arguments in both registers in indirect |
9546 | calls with the 32 bit ABI and the HP assembler since there is no | |
9547 | way to the specify argument locations in static functions. */ | |
f336e0bc | 9548 | || (!TARGET_64BIT |
9549 | && !TARGET_GAS | |
9550 | && !cum->incoming | |
9503b0f7 | 9551 | && cum->indirect |
4779159e | 9552 | && GET_MODE_CLASS (mode) == MODE_FLOAT)) |
5e3c5739 | 9553 | { |
9554 | retval | |
9555 | = gen_rtx_PARALLEL | |
9556 | (mode, | |
9557 | gen_rtvec (2, | |
9558 | gen_rtx_EXPR_LIST (VOIDmode, | |
9559 | gen_rtx_REG (mode, fpr_reg_base), | |
9560 | const0_rtx), | |
9561 | gen_rtx_EXPR_LIST (VOIDmode, | |
9562 | gen_rtx_REG (mode, gpr_reg_base), | |
9563 | const0_rtx))); | |
9564 | } | |
9565 | else | |
9566 | { | |
9567 | /* See if we should pass this parameter in a general register. */ | |
9568 | if (TARGET_SOFT_FLOAT | |
9569 | /* Indirect calls in the normal 32bit ABI require all arguments | |
9570 | to be passed in general registers. */ | |
9571 | || (!TARGET_PORTABLE_RUNTIME | |
9572 | && !TARGET_64BIT | |
a052da6f | 9573 | && !TARGET_ELF32 |
5e3c5739 | 9574 | && cum->indirect) |
4779159e | 9575 | /* If the parameter is not a scalar floating-point parameter, |
9576 | then it belongs in GPRs. */ | |
9577 | || GET_MODE_CLASS (mode) != MODE_FLOAT | |
b105ef41 | 9578 | /* Structure with single SFmode field belongs in GPR. */ |
9579 | || (type && AGGREGATE_TYPE_P (type))) | |
5e3c5739 | 9580 | retval = gen_rtx_REG (mode, gpr_reg_base); |
9581 | else | |
9582 | retval = gen_rtx_REG (mode, fpr_reg_base); | |
9583 | } | |
9584 | return retval; | |
9585 | } | |
9586 | ||
9587 | ||
9588 | /* If this arg would be passed totally in registers or totally on the stack, | |
f054eb3c | 9589 | then this routine should return zero. */ |
9590 | ||
9591 | static int | |
9592 | pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
9593 | tree type, bool named ATTRIBUTE_UNUSED) | |
5e3c5739 | 9594 | { |
b7d86581 | 9595 | unsigned int max_arg_words = 8; |
9596 | unsigned int offset = 0; | |
5e3c5739 | 9597 | |
f054eb3c | 9598 | if (!TARGET_64BIT) |
9599 | return 0; | |
9600 | ||
b7d86581 | 9601 | if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1)) |
5e3c5739 | 9602 | offset = 1; |
9603 | ||
b7d86581 | 9604 | if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words) |
6dc3b0d9 | 9605 | /* Arg fits fully into registers. */ |
5e3c5739 | 9606 | return 0; |
9840d99d | 9607 | else if (cum->words + offset >= max_arg_words) |
6dc3b0d9 | 9608 | /* Arg fully on the stack. */ |
5e3c5739 | 9609 | return 0; |
9610 | else | |
6dc3b0d9 | 9611 | /* Arg is split. */ |
f054eb3c | 9612 | return (max_arg_words - cum->words - offset) * UNITS_PER_WORD; |
5e3c5739 | 9613 | } |
9614 | ||
9615 | ||
2f14b1f9 | 9616 | /* A get_unnamed_section callback for switching to the text section. |
916c9cef | 9617 | |
9618 | This function is only used with SOM. Because we don't support | |
9619 | named subspaces, we can only create a new subspace or switch back | |
99c11254 | 9620 | to the default text subspace. */ |
99c11254 | 9621 | |
2f14b1f9 | 9622 | static void |
9623 | som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
9624 | { | |
9625 | gcc_assert (TARGET_SOM); | |
99c11254 | 9626 | if (TARGET_GAS) |
916c9cef | 9627 | { |
9f4a0384 | 9628 | if (cfun && cfun->machine && !cfun->machine->in_nsubspa) |
916c9cef | 9629 | { |
9630 | /* We only want to emit a .nsubspa directive once at the | |
9631 | start of the function. */ | |
9632 | cfun->machine->in_nsubspa = 1; | |
9633 | ||
9634 | /* Create a new subspace for the text. This provides | |
9635 | better stub placement and one-only functions. */ | |
9636 | if (cfun->decl | |
9637 | && DECL_ONE_ONLY (cfun->decl) | |
9638 | && !DECL_WEAK (cfun->decl)) | |
78962d38 | 9639 | { |
9640 | output_section_asm_op ("\t.SPACE $TEXT$\n" | |
9641 | "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8," | |
9642 | "ACCESS=44,SORT=24,COMDAT"); | |
9643 | return; | |
9644 | } | |
916c9cef | 9645 | } |
9646 | else | |
9647 | { | |
9648 | /* There isn't a current function or the body of the current | |
9649 | function has been completed. So, we are changing to the | |
78962d38 | 9650 | text section to output debugging information. Thus, we |
9651 | need to forget that we are in the text section so that | |
9652 | varasm.c will call us when text_section is selected again. */ | |
9f4a0384 | 9653 | gcc_assert (!cfun || !cfun->machine |
9654 | || cfun->machine->in_nsubspa == 2); | |
2f14b1f9 | 9655 | in_section = NULL; |
916c9cef | 9656 | } |
78962d38 | 9657 | output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$"); |
9658 | return; | |
916c9cef | 9659 | } |
2f14b1f9 | 9660 | output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$"); |
9661 | } | |
9662 | ||
78962d38 | 9663 | /* A get_unnamed_section callback for switching to comdat data |
9664 | sections. This function is only used with SOM. */ | |
9665 | ||
9666 | static void | |
9667 | som_output_comdat_data_section_asm_op (const void *data) | |
9668 | { | |
9669 | in_section = NULL; | |
9670 | output_section_asm_op (data); | |
9671 | } | |
9672 | ||
2f14b1f9 | 9673 | /* Implement TARGET_ASM_INITIALIZE_SECTIONS */ |
916c9cef | 9674 | |
2f14b1f9 | 9675 | static void |
9676 | pa_som_asm_init_sections (void) | |
9677 | { | |
9678 | text_section | |
9679 | = get_unnamed_section (0, som_output_text_section_asm_op, NULL); | |
9680 | ||
9681 | /* SOM puts readonly data in the default $LIT$ subspace when PIC code | |
9682 | is not being generated. */ | |
9683 | som_readonly_data_section | |
9684 | = get_unnamed_section (0, output_section_asm_op, | |
9685 | "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$"); | |
9686 | ||
9687 | /* When secondary definitions are not supported, SOM makes readonly | |
9688 | data one-only by creating a new $LIT$ subspace in $TEXT$ with | |
9689 | the comdat flag. */ | |
9690 | som_one_only_readonly_data_section | |
78962d38 | 9691 | = get_unnamed_section (0, som_output_comdat_data_section_asm_op, |
2f14b1f9 | 9692 | "\t.SPACE $TEXT$\n" |
9693 | "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8," | |
9694 | "ACCESS=0x2c,SORT=16,COMDAT"); | |
9695 | ||
9696 | ||
9697 | /* When secondary definitions are not supported, SOM makes data one-only | |
9698 | by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */ | |
9699 | som_one_only_data_section | |
78962d38 | 9700 | = get_unnamed_section (SECTION_WRITE, |
9701 | som_output_comdat_data_section_asm_op, | |
2f14b1f9 | 9702 | "\t.SPACE $PRIVATE$\n" |
9703 | "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8," | |
9704 | "ACCESS=31,SORT=24,COMDAT"); | |
9705 | ||
9706 | /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups | |
9707 | which reference data within the $TEXT$ space (for example constant | |
9708 | strings in the $LIT$ subspace). | |
9709 | ||
9710 | The assemblers (GAS and HP as) both have problems with handling | |
9711 | the difference of two symbols which is the other correct way to | |
9712 | reference constant data during PIC code generation. | |
9713 | ||
9714 | So, there's no way to reference constant data which is in the | |
9715 | $TEXT$ space during PIC generation. Instead place all constant | |
9716 | data into the $PRIVATE$ subspace (this reduces sharing, but it | |
9717 | works correctly). */ | |
9718 | readonly_data_section = flag_pic ? data_section : som_readonly_data_section; | |
9719 | ||
9720 | /* We must not have a reference to an external symbol defined in a | |
9721 | shared library in a readonly section, else the SOM linker will | |
9722 | complain. | |
9723 | ||
9724 | So, we force exception information into the data section. */ | |
9725 | exception_section = data_section; | |
916c9cef | 9726 | } |
9727 | ||
52470889 | 9728 | /* On hpux10, the linker will give an error if we have a reference |
9729 | in the read-only data section to a symbol defined in a shared | |
9730 | library. Therefore, expressions that might require a reloc can | |
9731 | not be placed in the read-only data section. */ | |
9732 | ||
2f14b1f9 | 9733 | static section * |
b572d1a5 | 9734 | pa_select_section (tree exp, int reloc, |
9735 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
52470889 | 9736 | { |
9737 | if (TREE_CODE (exp) == VAR_DECL | |
9738 | && TREE_READONLY (exp) | |
9739 | && !TREE_THIS_VOLATILE (exp) | |
9740 | && DECL_INITIAL (exp) | |
9741 | && (DECL_INITIAL (exp) == error_mark_node | |
9742 | || TREE_CONSTANT (DECL_INITIAL (exp))) | |
9743 | && !reloc) | |
916c9cef | 9744 | { |
9745 | if (TARGET_SOM | |
9746 | && DECL_ONE_ONLY (exp) | |
9747 | && !DECL_WEAK (exp)) | |
2f14b1f9 | 9748 | return som_one_only_readonly_data_section; |
916c9cef | 9749 | else |
2f14b1f9 | 9750 | return readonly_data_section; |
916c9cef | 9751 | } |
ce45a448 | 9752 | else if (CONSTANT_CLASS_P (exp) && !reloc) |
2f14b1f9 | 9753 | return readonly_data_section; |
916c9cef | 9754 | else if (TARGET_SOM |
9755 | && TREE_CODE (exp) == VAR_DECL | |
9756 | && DECL_ONE_ONLY (exp) | |
2455c36b | 9757 | && !DECL_WEAK (exp)) |
2f14b1f9 | 9758 | return som_one_only_data_section; |
52470889 | 9759 | else |
2f14b1f9 | 9760 | return data_section; |
52470889 | 9761 | } |
1f3233d1 | 9762 | |
67c1e638 | 9763 | static void |
5c1d8983 | 9764 | pa_globalize_label (FILE *stream, const char *name) |
67c1e638 | 9765 | { |
9766 | /* We only handle DATA objects here, functions are globalized in | |
9767 | ASM_DECLARE_FUNCTION_NAME. */ | |
9768 | if (! FUNCTION_NAME_P (name)) | |
9769 | { | |
9770 | fputs ("\t.EXPORT ", stream); | |
9771 | assemble_name (stream, name); | |
9772 | fputs (",DATA\n", stream); | |
9773 | } | |
9774 | } | |
b8debbe8 | 9775 | |
6644435d | 9776 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
9777 | ||
b8debbe8 | 9778 | static rtx |
9779 | pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
9780 | int incoming ATTRIBUTE_UNUSED) | |
9781 | { | |
9782 | return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM); | |
9783 | } | |
9784 | ||
6644435d | 9785 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
9786 | ||
b8debbe8 | 9787 | bool |
fb80456a | 9788 | pa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
b8debbe8 | 9789 | { |
9790 | /* SOM ABI says that objects larger than 64 bits are returned in memory. | |
9791 | PA64 ABI says that objects larger than 128 bits are returned in memory. | |
9792 | Note, int_size_in_bytes can return -1 if the size of the object is | |
9793 | variable or larger than the maximum value that can be expressed as | |
9794 | a HOST_WIDE_INT. It can also return zero for an empty type. The | |
9795 | simplest way to handle variable and empty types is to pass them in | |
9796 | memory. This avoids problems in defining the boundaries of argument | |
9797 | slots, allocating registers, etc. */ | |
9798 | return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8) | |
9799 | || int_size_in_bytes (type) <= 0); | |
9800 | } | |
9801 | ||
5f43b4f6 | 9802 | /* Structure to hold declaration and name of external symbols that are |
9803 | emitted by GCC. We generate a vector of these symbols and output them | |
9804 | at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true. | |
9805 | This avoids putting out names that are never really used. */ | |
9806 | ||
fb1e4f4a | 9807 | typedef struct GTY(()) extern_symbol |
5f43b4f6 | 9808 | { |
9809 | tree decl; | |
9810 | const char *name; | |
046bfc77 | 9811 | } extern_symbol; |
5f43b4f6 | 9812 | |
9813 | /* Define gc'd vector type for extern_symbol. */ | |
046bfc77 | 9814 | DEF_VEC_O(extern_symbol); |
9815 | DEF_VEC_ALLOC_O(extern_symbol,gc); | |
5f43b4f6 | 9816 | |
9817 | /* Vector of extern_symbol pointers. */ | |
046bfc77 | 9818 | static GTY(()) VEC(extern_symbol,gc) *extern_symbols; |
5f43b4f6 | 9819 | |
9820 | #ifdef ASM_OUTPUT_EXTERNAL_REAL | |
9821 | /* Mark DECL (name NAME) as an external reference (assembler output | |
9822 | file FILE). This saves the names to output at the end of the file | |
9823 | if actually referenced. */ | |
9824 | ||
9825 | void | |
9826 | pa_hpux_asm_output_external (FILE *file, tree decl, const char *name) | |
9827 | { | |
046bfc77 | 9828 | extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL); |
5f43b4f6 | 9829 | |
9830 | gcc_assert (file == asm_out_file); | |
9831 | p->decl = decl; | |
9832 | p->name = name; | |
5f43b4f6 | 9833 | } |
9834 | ||
9835 | /* Output text required at the end of an assembler file. | |
9836 | This includes deferred plabels and .import directives for | |
9837 | all external symbols that were actually referenced. */ | |
9838 | ||
9839 | static void | |
9840 | pa_hpux_file_end (void) | |
9841 | { | |
9842 | unsigned int i; | |
046bfc77 | 9843 | extern_symbol *p; |
5f43b4f6 | 9844 | |
bb1bc2ca | 9845 | if (!NO_DEFERRED_PROFILE_COUNTERS) |
9846 | output_deferred_profile_counters (); | |
9847 | ||
5f43b4f6 | 9848 | output_deferred_plabels (); |
9849 | ||
9850 | for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++) | |
9851 | { | |
9852 | tree decl = p->decl; | |
9853 | ||
9854 | if (!TREE_ASM_WRITTEN (decl) | |
9855 | && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0))) | |
9856 | ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name); | |
9857 | } | |
9858 | ||
046bfc77 | 9859 | VEC_free (extern_symbol, gc, extern_symbols); |
5f43b4f6 | 9860 | } |
9861 | #endif | |
9862 | ||
7050ff73 | 9863 | /* Return true if a change from mode FROM to mode TO for a register |
8deb3959 | 9864 | in register class RCLASS is invalid. */ |
7050ff73 | 9865 | |
9866 | bool | |
9867 | pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to, | |
8deb3959 | 9868 | enum reg_class rclass) |
7050ff73 | 9869 | { |
9870 | if (from == to) | |
9871 | return false; | |
9872 | ||
9873 | /* Reject changes to/from complex and vector modes. */ | |
9874 | if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from) | |
9875 | || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to)) | |
9876 | return true; | |
9877 | ||
9878 | if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to)) | |
9879 | return false; | |
9880 | ||
9881 | /* There is no way to load QImode or HImode values directly from | |
9882 | memory. SImode loads to the FP registers are not zero extended. | |
9883 | On the 64-bit target, this conflicts with the definition of | |
9884 | LOAD_EXTEND_OP. Thus, we can't allow changing between modes | |
9885 | with different sizes in the floating-point registers. */ | |
8deb3959 | 9886 | if (MAYBE_FP_REG_CLASS_P (rclass)) |
7050ff73 | 9887 | return true; |
9888 | ||
9889 | /* HARD_REGNO_MODE_OK places modes with sizes larger than a word | |
9890 | in specific sets of registers. Thus, we cannot allow changing | |
9891 | to a larger mode when it's larger than a word. */ | |
9892 | if (GET_MODE_SIZE (to) > UNITS_PER_WORD | |
9893 | && GET_MODE_SIZE (to) > GET_MODE_SIZE (from)) | |
9894 | return true; | |
9895 | ||
9896 | return false; | |
9897 | } | |
9898 | ||
9899 | /* Returns TRUE if it is a good idea to tie two pseudo registers | |
9900 | when one has mode MODE1 and one has mode MODE2. | |
9901 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
9902 | for any hard reg, then this must be FALSE for correct output. | |
9903 | ||
9904 | We should return FALSE for QImode and HImode because these modes | |
9905 | are not ok in the floating-point registers. However, this prevents | |
9906 | tieing these modes to SImode and DImode in the general registers. | |
9907 | So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and | |
9908 | CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used | |
9909 | in the floating-point registers. */ | |
9910 | ||
9911 | bool | |
9912 | pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) | |
9913 | { | |
9914 | /* Don't tie modes in different classes. */ | |
9915 | if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2)) | |
9916 | return false; | |
9917 | ||
9918 | return true; | |
9919 | } | |
9920 | ||
623a97bc | 9921 | \f |
9922 | /* Length in units of the trampoline instruction code. */ | |
9923 | ||
9924 | #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40)) | |
9925 | ||
9926 | ||
9927 | /* Output assembler code for a block containing the constant parts | |
9928 | of a trampoline, leaving space for the variable parts.\ | |
9929 | ||
9930 | The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM | |
9931 | and then branches to the specified routine. | |
9932 | ||
9933 | This code template is copied from text segment to stack location | |
9934 | and then patched with pa_trampoline_init to contain valid values, | |
9935 | and then entered as a subroutine. | |
9936 | ||
9937 | It is best to keep this as small as possible to avoid having to | |
9938 | flush multiple lines in the cache. */ | |
9939 | ||
9940 | static void | |
9941 | pa_asm_trampoline_template (FILE *f) | |
9942 | { | |
9943 | if (!TARGET_64BIT) | |
9944 | { | |
9945 | fputs ("\tldw 36(%r22),%r21\n", f); | |
9946 | fputs ("\tbb,>=,n %r21,30,.+16\n", f); | |
9947 | if (ASSEMBLER_DIALECT == 0) | |
9948 | fputs ("\tdepi 0,31,2,%r21\n", f); | |
9949 | else | |
9950 | fputs ("\tdepwi 0,31,2,%r21\n", f); | |
9951 | fputs ("\tldw 4(%r21),%r19\n", f); | |
9952 | fputs ("\tldw 0(%r21),%r21\n", f); | |
9953 | if (TARGET_PA_20) | |
9954 | { | |
9955 | fputs ("\tbve (%r21)\n", f); | |
9956 | fputs ("\tldw 40(%r22),%r29\n", f); | |
9957 | fputs ("\t.word 0\n", f); | |
9958 | fputs ("\t.word 0\n", f); | |
9959 | } | |
9960 | else | |
9961 | { | |
9962 | fputs ("\tldsid (%r21),%r1\n", f); | |
9963 | fputs ("\tmtsp %r1,%sr0\n", f); | |
9964 | fputs ("\tbe 0(%sr0,%r21)\n", f); | |
9965 | fputs ("\tldw 40(%r22),%r29\n", f); | |
9966 | } | |
9967 | fputs ("\t.word 0\n", f); | |
9968 | fputs ("\t.word 0\n", f); | |
9969 | fputs ("\t.word 0\n", f); | |
9970 | fputs ("\t.word 0\n", f); | |
9971 | } | |
9972 | else | |
9973 | { | |
9974 | fputs ("\t.dword 0\n", f); | |
9975 | fputs ("\t.dword 0\n", f); | |
9976 | fputs ("\t.dword 0\n", f); | |
9977 | fputs ("\t.dword 0\n", f); | |
9978 | fputs ("\tmfia %r31\n", f); | |
9979 | fputs ("\tldd 24(%r31),%r1\n", f); | |
9980 | fputs ("\tldd 24(%r1),%r27\n", f); | |
9981 | fputs ("\tldd 16(%r1),%r1\n", f); | |
9982 | fputs ("\tbve (%r1)\n", f); | |
9983 | fputs ("\tldd 32(%r31),%r31\n", f); | |
9984 | fputs ("\t.dword 0 ; fptr\n", f); | |
9985 | fputs ("\t.dword 0 ; static link\n", f); | |
9986 | } | |
9987 | } | |
9988 | ||
9989 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
9990 | FNADDR is an RTX for the address of the function's pure code. | |
9991 | CXT is an RTX for the static chain value for the function. | |
9992 | ||
9993 | Move the function address to the trampoline template at offset 36. | |
9994 | Move the static chain value to trampoline template at offset 40. | |
9995 | Move the trampoline address to trampoline template at offset 44. | |
9996 | Move r19 to trampoline template at offset 48. The latter two | |
9997 | words create a plabel for the indirect call to the trampoline. | |
9998 | ||
9999 | A similar sequence is used for the 64-bit port but the plabel is | |
10000 | at the beginning of the trampoline. | |
10001 | ||
10002 | Finally, the cache entries for the trampoline code are flushed. | |
10003 | This is necessary to ensure that the trampoline instruction sequence | |
10004 | is written to memory prior to any attempts at prefetching the code | |
10005 | sequence. */ | |
10006 | ||
10007 | static void | |
10008 | pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
10009 | { | |
10010 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
10011 | rtx start_addr = gen_reg_rtx (Pmode); | |
10012 | rtx end_addr = gen_reg_rtx (Pmode); | |
10013 | rtx line_length = gen_reg_rtx (Pmode); | |
10014 | rtx r_tramp, tmp; | |
10015 | ||
10016 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
10017 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
10018 | r_tramp = force_reg (Pmode, XEXP (m_tramp, 0)); | |
10019 | ||
10020 | if (!TARGET_64BIT) | |
10021 | { | |
10022 | tmp = adjust_address (m_tramp, Pmode, 36); | |
10023 | emit_move_insn (tmp, fnaddr); | |
10024 | tmp = adjust_address (m_tramp, Pmode, 40); | |
10025 | emit_move_insn (tmp, chain_value); | |
10026 | ||
10027 | /* Create a fat pointer for the trampoline. */ | |
10028 | tmp = adjust_address (m_tramp, Pmode, 44); | |
10029 | emit_move_insn (tmp, r_tramp); | |
10030 | tmp = adjust_address (m_tramp, Pmode, 48); | |
10031 | emit_move_insn (tmp, gen_rtx_REG (Pmode, 19)); | |
10032 | ||
10033 | /* fdc and fic only use registers for the address to flush, | |
10034 | they do not accept integer displacements. We align the | |
10035 | start and end addresses to the beginning of their respective | |
10036 | cache lines to minimize the number of lines flushed. */ | |
10037 | emit_insn (gen_andsi3 (start_addr, r_tramp, | |
10038 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
10039 | tmp = force_reg (Pmode, plus_constant (r_tramp, TRAMPOLINE_CODE_SIZE-1)); | |
10040 | emit_insn (gen_andsi3 (end_addr, tmp, | |
10041 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
10042 | emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); | |
10043 | emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length)); | |
10044 | emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length, | |
10045 | gen_reg_rtx (Pmode), | |
10046 | gen_reg_rtx (Pmode))); | |
10047 | } | |
10048 | else | |
10049 | { | |
10050 | tmp = adjust_address (m_tramp, Pmode, 56); | |
10051 | emit_move_insn (tmp, fnaddr); | |
10052 | tmp = adjust_address (m_tramp, Pmode, 64); | |
10053 | emit_move_insn (tmp, chain_value); | |
10054 | ||
10055 | /* Create a fat pointer for the trampoline. */ | |
10056 | tmp = adjust_address (m_tramp, Pmode, 16); | |
10057 | emit_move_insn (tmp, force_reg (Pmode, plus_constant (r_tramp, 32))); | |
10058 | tmp = adjust_address (m_tramp, Pmode, 24); | |
10059 | emit_move_insn (tmp, gen_rtx_REG (Pmode, 27)); | |
10060 | ||
10061 | /* fdc and fic only use registers for the address to flush, | |
10062 | they do not accept integer displacements. We align the | |
10063 | start and end addresses to the beginning of their respective | |
10064 | cache lines to minimize the number of lines flushed. */ | |
10065 | tmp = force_reg (Pmode, plus_constant (r_tramp, 32)); | |
10066 | emit_insn (gen_anddi3 (start_addr, tmp, | |
10067 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
10068 | tmp = force_reg (Pmode, plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); | |
10069 | emit_insn (gen_anddi3 (end_addr, tmp, | |
10070 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
10071 | emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); | |
10072 | emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length)); | |
10073 | emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length, | |
10074 | gen_reg_rtx (Pmode), | |
10075 | gen_reg_rtx (Pmode))); | |
10076 | } | |
10077 | } | |
10078 | ||
10079 | /* Perform any machine-specific adjustment in the address of the trampoline. | |
10080 | ADDR contains the address that was passed to pa_trampoline_init. | |
10081 | Adjust the trampoline address to point to the plabel at offset 44. */ | |
10082 | ||
10083 | static rtx | |
10084 | pa_trampoline_adjust_address (rtx addr) | |
10085 | { | |
10086 | if (!TARGET_64BIT) | |
10087 | addr = memory_address (Pmode, plus_constant (addr, 46)); | |
10088 | return addr; | |
10089 | } | |
c731c4f5 | 10090 | |
10091 | static rtx | |
10092 | pa_delegitimize_address (rtx orig_x) | |
10093 | { | |
10094 | rtx x = delegitimize_mem_from_attrs (orig_x); | |
10095 | ||
10096 | if (GET_CODE (x) == LO_SUM | |
10097 | && GET_CODE (XEXP (x, 1)) == UNSPEC | |
10098 | && XINT (XEXP (x, 1), 1) == UNSPEC_DLTIND14R) | |
10099 | return gen_const_mem (Pmode, XVECEXP (XEXP (x, 1), 0, 0)); | |
10100 | return x; | |
10101 | } | |
623a97bc | 10102 | \f |
1f3233d1 | 10103 | #include "gt-pa.h" |