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188538df | 1 | /* Subroutines for insn-output.c for HPPA. |
8f949e7e | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
66647d44 JJ |
3 | 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
4 | Free Software Foundation, Inc. | |
188538df TG |
5 | Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c |
6 | ||
b7849684 | 7 | This file is part of GCC. |
188538df | 8 | |
b7849684 | 9 | GCC is free software; you can redistribute it and/or modify |
188538df | 10 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 11 | the Free Software Foundation; either version 3, or (at your option) |
188538df TG |
12 | any later version. |
13 | ||
b7849684 | 14 | GCC is distributed in the hope that it will be useful, |
188538df TG |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
188538df | 22 | |
188538df | 23 | #include "config.h" |
0b17dd98 | 24 | #include "system.h" |
4977bab6 ZW |
25 | #include "coretypes.h" |
26 | #include "tm.h" | |
188538df TG |
27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
188538df TG |
33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "tree.h" | |
d499455b | 36 | #include "output.h" |
823fbbce | 37 | #include "except.h" |
becf1647 | 38 | #include "expr.h" |
e78d8e51 | 39 | #include "optabs.h" |
e78d8e51 | 40 | #include "reload.h" |
d777856d | 41 | #include "integrate.h" |
49ad7cfa | 42 | #include "function.h" |
0b17dd98 | 43 | #include "toplev.h" |
d07d525a | 44 | #include "ggc.h" |
519104fe | 45 | #include "recog.h" |
823fbbce | 46 | #include "predict.h" |
519104fe | 47 | #include "tm_p.h" |
672a6f42 NB |
48 | #include "target.h" |
49 | #include "target-def.h" | |
62a53968 | 50 | #include "df.h" |
188538df | 51 | |
5d50fab3 JL |
52 | /* Return nonzero if there is a bypass for the output of |
53 | OUT_INSN and the fp store IN_INSN. */ | |
54 | int | |
b7849684 | 55 | hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn) |
5d50fab3 JL |
56 | { |
57 | enum machine_mode store_mode; | |
58 | enum machine_mode other_mode; | |
59 | rtx set; | |
60 | ||
61 | if (recog_memoized (in_insn) < 0 | |
d4f2728a JDA |
62 | || (get_attr_type (in_insn) != TYPE_FPSTORE |
63 | && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD) | |
5d50fab3 JL |
64 | || recog_memoized (out_insn) < 0) |
65 | return 0; | |
66 | ||
67 | store_mode = GET_MODE (SET_SRC (PATTERN (in_insn))); | |
68 | ||
69 | set = single_set (out_insn); | |
70 | if (!set) | |
71 | return 0; | |
72 | ||
73 | other_mode = GET_MODE (SET_SRC (set)); | |
74 | ||
75 | return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode)); | |
76 | } | |
77 | ||
78 | ||
19ec6a36 AM |
79 | #ifndef DO_FRAME_NOTES |
80 | #ifdef INCOMING_RETURN_ADDR_RTX | |
81 | #define DO_FRAME_NOTES 1 | |
82 | #else | |
83 | #define DO_FRAME_NOTES 0 | |
84 | #endif | |
85 | #endif | |
86 | ||
d8f95bed | 87 | static void copy_reg_pointer (rtx, rtx); |
a2017852 | 88 | static void fix_range (const char *); |
66617831 | 89 | static bool pa_handle_option (size_t, const char *, int); |
f40751dd JH |
90 | static int hppa_address_cost (rtx, bool); |
91 | static bool hppa_rtx_costs (rtx, int, int, int *, bool); | |
b7849684 JE |
92 | static inline rtx force_mode (enum machine_mode, rtx); |
93 | static void pa_reorg (void); | |
94 | static void pa_combine_instructions (void); | |
95 | static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx); | |
96 | static int forward_branch_p (rtx); | |
b7849684 | 97 | static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *); |
70128ad9 AO |
98 | static int compute_movmem_length (rtx); |
99 | static int compute_clrmem_length (rtx); | |
b7849684 JE |
100 | static bool pa_assemble_integer (rtx, unsigned int, int); |
101 | static void remove_useless_addtr_insns (int); | |
a4295210 JDA |
102 | static void store_reg (int, HOST_WIDE_INT, int); |
103 | static void store_reg_modify (int, int, HOST_WIDE_INT); | |
104 | static void load_reg (int, HOST_WIDE_INT, int); | |
105 | static void set_reg_plus_d (int, int, HOST_WIDE_INT, int); | |
b7849684 | 106 | static void pa_output_function_prologue (FILE *, HOST_WIDE_INT); |
67b846fa | 107 | static void update_total_code_bytes (unsigned int); |
b7849684 JE |
108 | static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT); |
109 | static int pa_adjust_cost (rtx, rtx, rtx, int); | |
110 | static int pa_adjust_priority (rtx, int); | |
111 | static int pa_issue_rate (void); | |
d6b5193b RS |
112 | static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED; |
113 | static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT) | |
ae46c4e0 | 114 | ATTRIBUTE_UNUSED; |
b7849684 JE |
115 | static void pa_encode_section_info (tree, rtx, int); |
116 | static const char *pa_strip_name_encoding (const char *); | |
117 | static bool pa_function_ok_for_sibcall (tree, tree); | |
118 | static void pa_globalize_label (FILE *, const char *) | |
a5f3f0ab | 119 | ATTRIBUTE_UNUSED; |
b7849684 JE |
120 | static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
121 | HOST_WIDE_INT, tree); | |
35d434ed | 122 | #if !defined(USE_COLLECT2) |
b7849684 JE |
123 | static void pa_asm_out_constructor (rtx, int); |
124 | static void pa_asm_out_destructor (rtx, int); | |
35d434ed | 125 | #endif |
b7849684 | 126 | static void pa_init_builtins (void); |
3f12cd9b | 127 | static rtx hppa_builtin_saveregs (void); |
d7bd8aeb | 128 | static void hppa_va_start (tree, rtx); |
726a989a | 129 | static tree hppa_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); |
83c32f2e | 130 | static bool pa_scalar_mode_supported_p (enum machine_mode); |
3101faab | 131 | static bool pa_commutative_p (const_rtx x, int outer_code); |
b7849684 JE |
132 | static void copy_fp_args (rtx) ATTRIBUTE_UNUSED; |
133 | static int length_fp_args (rtx) ATTRIBUTE_UNUSED; | |
506d7b68 | 134 | static rtx hppa_legitimize_address (rtx, rtx, enum machine_mode); |
b7849684 JE |
135 | static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED; |
136 | static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED; | |
137 | static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED; | |
138 | static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED; | |
139 | static void pa_elf_file_start (void) ATTRIBUTE_UNUSED; | |
140 | static void pa_som_file_start (void) ATTRIBUTE_UNUSED; | |
141 | static void pa_linux_file_start (void) ATTRIBUTE_UNUSED; | |
142 | static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED; | |
143 | static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED; | |
144 | static void output_deferred_plabels (void); | |
3674b34d | 145 | static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED; |
744b2d61 JDA |
146 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
147 | static void pa_hpux_file_end (void); | |
148 | #endif | |
c15c90bb ZW |
149 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
150 | static void pa_hpux_init_libfuncs (void); | |
151 | #endif | |
3f12cd9b | 152 | static rtx pa_struct_value_rtx (tree, int); |
78a52f11 | 153 | static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
586de218 | 154 | const_tree, bool); |
78a52f11 RH |
155 | static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
156 | tree, bool); | |
9a55eab3 | 157 | static struct machine_function * pa_init_machine_status (void); |
ec963611 JDA |
158 | static enum reg_class pa_secondary_reload (bool, rtx, enum reg_class, |
159 | enum machine_mode, | |
160 | secondary_reload_info *); | |
16c16a24 | 161 | static void pa_extra_live_on_entry (bitmap); |
2eddfed1 | 162 | |
d6b5193b RS |
163 | /* The following extra sections are only used for SOM. */ |
164 | static GTY(()) section *som_readonly_data_section; | |
165 | static GTY(()) section *som_one_only_readonly_data_section; | |
166 | static GTY(()) section *som_one_only_data_section; | |
167 | ||
a2017852 | 168 | /* Which cpu we are scheduling for. */ |
66617831 | 169 | enum processor_type pa_cpu = TARGET_SCHED_DEFAULT; |
d711cf67 JDA |
170 | |
171 | /* The UNIX standard to use for predefines and linking. */ | |
66617831 | 172 | int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993; |
d711cf67 | 173 | |
68386e1e JL |
174 | /* Counts for the number of callee-saved general and floating point |
175 | registers which were saved by the current function's prologue. */ | |
176 | static int gr_saved, fr_saved; | |
177 | ||
16c16a24 JDA |
178 | /* Boolean indicating whether the return pointer was saved by the |
179 | current function's prologue. */ | |
180 | static bool rp_saved; | |
181 | ||
b7849684 | 182 | static rtx find_addr_reg (rtx); |
188538df | 183 | |
5fad1c24 | 184 | /* Keep track of the number of bytes we have output in the CODE subspace |
279c9bde | 185 | during this compilation so we'll know when to emit inline long-calls. */ |
a02aa5b0 | 186 | unsigned long total_code_bytes; |
279c9bde | 187 | |
5fad1c24 JDA |
188 | /* The last address of the previous function plus the number of bytes in |
189 | associated thunks that have been output. This is used to determine if | |
190 | a thunk can use an IA-relative branch to reach its target function. */ | |
67b846fa | 191 | static unsigned int last_address; |
5fad1c24 | 192 | |
93ae92c1 | 193 | /* Variables to handle plabels that we discover are necessary at assembly |
ddd5a7c1 | 194 | output time. They are output after the current function. */ |
d1b38208 | 195 | struct GTY(()) deferred_plabel |
93ae92c1 JL |
196 | { |
197 | rtx internal_label; | |
744b2d61 | 198 | rtx symbol; |
e2500fed GK |
199 | }; |
200 | static GTY((length ("n_deferred_plabels"))) struct deferred_plabel * | |
201 | deferred_plabels; | |
0f8e3849 | 202 | static size_t n_deferred_plabels = 0; |
a5fe455b | 203 | |
672a6f42 NB |
204 | \f |
205 | /* Initialize the GCC target structure. */ | |
301d03af RS |
206 | |
207 | #undef TARGET_ASM_ALIGNED_HI_OP | |
208 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
209 | #undef TARGET_ASM_ALIGNED_SI_OP | |
210 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
211 | #undef TARGET_ASM_ALIGNED_DI_OP | |
212 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
213 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
214 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
215 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
216 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
217 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
218 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
219 | #undef TARGET_ASM_INTEGER | |
220 | #define TARGET_ASM_INTEGER pa_assemble_integer | |
221 | ||
08c148a8 NB |
222 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
223 | #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue | |
224 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
225 | #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue | |
93ae92c1 | 226 | |
506d7b68 PB |
227 | #undef TARGET_LEGITIMIZE_ADDRESS |
228 | #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address | |
229 | ||
c237e94a ZW |
230 | #undef TARGET_SCHED_ADJUST_COST |
231 | #define TARGET_SCHED_ADJUST_COST pa_adjust_cost | |
232 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
233 | #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority | |
234 | #undef TARGET_SCHED_ISSUE_RATE | |
235 | #define TARGET_SCHED_ISSUE_RATE pa_issue_rate | |
236 | ||
fb49053f RH |
237 | #undef TARGET_ENCODE_SECTION_INFO |
238 | #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info | |
772c5265 RH |
239 | #undef TARGET_STRIP_NAME_ENCODING |
240 | #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding | |
fb49053f | 241 | |
4977bab6 ZW |
242 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
243 | #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall | |
244 | ||
8ddf681a R |
245 | #undef TARGET_COMMUTATIVE_P |
246 | #define TARGET_COMMUTATIVE_P pa_commutative_p | |
247 | ||
c590b625 RH |
248 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
249 | #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk | |
3961e8fe RH |
250 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
251 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
c590b625 | 252 | |
a5fe455b | 253 | #undef TARGET_ASM_FILE_END |
744b2d61 JDA |
254 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
255 | #define TARGET_ASM_FILE_END pa_hpux_file_end | |
256 | #else | |
a5fe455b | 257 | #define TARGET_ASM_FILE_END output_deferred_plabels |
744b2d61 | 258 | #endif |
a5fe455b | 259 | |
35d434ed JDA |
260 | #if !defined(USE_COLLECT2) |
261 | #undef TARGET_ASM_CONSTRUCTOR | |
262 | #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor | |
263 | #undef TARGET_ASM_DESTRUCTOR | |
264 | #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor | |
265 | #endif | |
266 | ||
66617831 RS |
267 | #undef TARGET_DEFAULT_TARGET_FLAGS |
268 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT) | |
269 | #undef TARGET_HANDLE_OPTION | |
270 | #define TARGET_HANDLE_OPTION pa_handle_option | |
271 | ||
4677862a JDA |
272 | #undef TARGET_INIT_BUILTINS |
273 | #define TARGET_INIT_BUILTINS pa_init_builtins | |
274 | ||
3c50106f RH |
275 | #undef TARGET_RTX_COSTS |
276 | #define TARGET_RTX_COSTS hppa_rtx_costs | |
dcefdf67 RH |
277 | #undef TARGET_ADDRESS_COST |
278 | #define TARGET_ADDRESS_COST hppa_address_cost | |
3c50106f | 279 | |
18dbd950 RS |
280 | #undef TARGET_MACHINE_DEPENDENT_REORG |
281 | #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg | |
282 | ||
c15c90bb ZW |
283 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
284 | #undef TARGET_INIT_LIBFUNCS | |
285 | #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs | |
286 | #endif | |
287 | ||
3f12cd9b | 288 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
586de218 | 289 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true |
3f12cd9b | 290 | #undef TARGET_PROMOTE_PROTOTYPES |
586de218 | 291 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
3f12cd9b KH |
292 | |
293 | #undef TARGET_STRUCT_VALUE_RTX | |
294 | #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx | |
295 | #undef TARGET_RETURN_IN_MEMORY | |
296 | #define TARGET_RETURN_IN_MEMORY pa_return_in_memory | |
fe984136 RH |
297 | #undef TARGET_MUST_PASS_IN_STACK |
298 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
8cd5a4e0 RH |
299 | #undef TARGET_PASS_BY_REFERENCE |
300 | #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference | |
6cdd5672 RH |
301 | #undef TARGET_CALLEE_COPIES |
302 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
78a52f11 RH |
303 | #undef TARGET_ARG_PARTIAL_BYTES |
304 | #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes | |
3f12cd9b KH |
305 | |
306 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
307 | #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs | |
d7bd8aeb JJ |
308 | #undef TARGET_EXPAND_BUILTIN_VA_START |
309 | #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start | |
8101c928 RH |
310 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
311 | #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr | |
3f12cd9b | 312 | |
83c32f2e JDA |
313 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
314 | #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p | |
315 | ||
51076f96 RC |
316 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
317 | #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p | |
318 | ||
ec963611 JDA |
319 | #undef TARGET_SECONDARY_RELOAD |
320 | #define TARGET_SECONDARY_RELOAD pa_secondary_reload | |
321 | ||
16c16a24 JDA |
322 | #undef TARGET_EXTRA_LIVE_ON_ENTRY |
323 | #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry | |
324 | ||
f6897b10 | 325 | struct gcc_target targetm = TARGET_INITIALIZER; |
672a6f42 | 326 | \f |
a2017852 JDA |
327 | /* Parse the -mfixed-range= option string. */ |
328 | ||
329 | static void | |
330 | fix_range (const char *const_str) | |
331 | { | |
332 | int i, first, last; | |
333 | char *str, *dash, *comma; | |
334 | ||
335 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and | |
336 | REG2 are either register names or register numbers. The effect | |
337 | of this option is to mark the registers in the range from REG1 to | |
338 | REG2 as ``fixed'' so they won't be used by the compiler. This is | |
419df6a2 | 339 | used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */ |
a2017852 JDA |
340 | |
341 | i = strlen (const_str); | |
342 | str = (char *) alloca (i + 1); | |
343 | memcpy (str, const_str, i + 1); | |
344 | ||
345 | while (1) | |
346 | { | |
347 | dash = strchr (str, '-'); | |
348 | if (!dash) | |
349 | { | |
d4ee4d25 | 350 | warning (0, "value of -mfixed-range must have form REG1-REG2"); |
a2017852 JDA |
351 | return; |
352 | } | |
353 | *dash = '\0'; | |
354 | ||
355 | comma = strchr (dash + 1, ','); | |
356 | if (comma) | |
357 | *comma = '\0'; | |
358 | ||
359 | first = decode_reg_name (str); | |
360 | if (first < 0) | |
361 | { | |
d4ee4d25 | 362 | warning (0, "unknown register name: %s", str); |
a2017852 JDA |
363 | return; |
364 | } | |
365 | ||
366 | last = decode_reg_name (dash + 1); | |
367 | if (last < 0) | |
368 | { | |
d4ee4d25 | 369 | warning (0, "unknown register name: %s", dash + 1); |
a2017852 JDA |
370 | return; |
371 | } | |
372 | ||
373 | *dash = '-'; | |
374 | ||
375 | if (first > last) | |
376 | { | |
d4ee4d25 | 377 | warning (0, "%s-%s is an empty range", str, dash + 1); |
a2017852 JDA |
378 | return; |
379 | } | |
380 | ||
381 | for (i = first; i <= last; ++i) | |
382 | fixed_regs[i] = call_used_regs[i] = 1; | |
383 | ||
384 | if (!comma) | |
385 | break; | |
386 | ||
387 | *comma = ','; | |
388 | str = comma + 1; | |
389 | } | |
390 | ||
391 | /* Check if all floating point registers have been fixed. */ | |
392 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
393 | if (!fixed_regs[i]) | |
394 | break; | |
395 | ||
396 | if (i > FP_REG_LAST) | |
397 | target_flags |= MASK_DISABLE_FPREGS; | |
398 | } | |
399 | ||
66617831 | 400 | /* Implement TARGET_HANDLE_OPTION. */ |
6a73009d | 401 | |
66617831 RS |
402 | static bool |
403 | pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
404 | { | |
405 | switch (code) | |
ea3bfbfe | 406 | { |
66617831 RS |
407 | case OPT_mnosnake: |
408 | case OPT_mpa_risc_1_0: | |
409 | case OPT_march_1_0: | |
ea3bfbfe | 410 | target_flags &= ~(MASK_PA_11 | MASK_PA_20); |
66617831 RS |
411 | return true; |
412 | ||
413 | case OPT_msnake: | |
414 | case OPT_mpa_risc_1_1: | |
415 | case OPT_march_1_1: | |
ea3bfbfe JQ |
416 | target_flags &= ~MASK_PA_20; |
417 | target_flags |= MASK_PA_11; | |
66617831 | 418 | return true; |
ea3bfbfe | 419 | |
66617831 RS |
420 | case OPT_mpa_risc_2_0: |
421 | case OPT_march_2_0: | |
422 | target_flags |= MASK_PA_11 | MASK_PA_20; | |
423 | return true; | |
424 | ||
425 | case OPT_mschedule_: | |
426 | if (strcmp (arg, "8000") == 0) | |
427 | pa_cpu = PROCESSOR_8000; | |
428 | else if (strcmp (arg, "7100") == 0) | |
429 | pa_cpu = PROCESSOR_7100; | |
430 | else if (strcmp (arg, "700") == 0) | |
431 | pa_cpu = PROCESSOR_700; | |
432 | else if (strcmp (arg, "7100LC") == 0) | |
433 | pa_cpu = PROCESSOR_7100LC; | |
434 | else if (strcmp (arg, "7200") == 0) | |
435 | pa_cpu = PROCESSOR_7200; | |
436 | else if (strcmp (arg, "7300") == 0) | |
437 | pa_cpu = PROCESSOR_7300; | |
d711cf67 | 438 | else |
66617831 RS |
439 | return false; |
440 | return true; | |
d711cf67 | 441 | |
66617831 RS |
442 | case OPT_mfixed_range_: |
443 | fix_range (arg); | |
444 | return true; | |
a2017852 | 445 | |
66617831 RS |
446 | #if TARGET_HPUX |
447 | case OPT_munix_93: | |
448 | flag_pa_unix = 1993; | |
449 | return true; | |
450 | #endif | |
451 | ||
452 | #if TARGET_HPUX_10_10 | |
453 | case OPT_munix_95: | |
454 | flag_pa_unix = 1995; | |
455 | return true; | |
456 | #endif | |
457 | ||
458 | #if TARGET_HPUX_11_11 | |
459 | case OPT_munix_98: | |
460 | flag_pa_unix = 1998; | |
461 | return true; | |
462 | #endif | |
463 | ||
464 | default: | |
465 | return true; | |
466 | } | |
467 | } | |
468 | ||
469 | void | |
470 | override_options (void) | |
471 | { | |
1c31ecf6 JDA |
472 | /* Unconditional branches in the delay slot are not compatible with dwarf2 |
473 | call frame information. There is no benefit in using this optimization | |
474 | on PA8000 and later processors. */ | |
475 | if (pa_cpu >= PROCESSOR_8000 | |
476 | || (! USING_SJLJ_EXCEPTIONS && flag_exceptions) | |
477 | || flag_unwind_tables) | |
478 | target_flags &= ~MASK_JUMP_IN_DELAY; | |
479 | ||
6a73009d JL |
480 | if (flag_pic && TARGET_PORTABLE_RUNTIME) |
481 | { | |
ab532386 | 482 | warning (0, "PIC code generation is not supported in the portable runtime model"); |
6a73009d JL |
483 | } |
484 | ||
a7721dc0 | 485 | if (flag_pic && TARGET_FAST_INDIRECT_CALLS) |
6a73009d | 486 | { |
ab532386 | 487 | warning (0, "PIC code generation is not compatible with fast indirect calls"); |
6a73009d | 488 | } |
0eba3d30 | 489 | |
54eef932 JL |
490 | if (! TARGET_GAS && write_symbols != NO_DEBUG) |
491 | { | |
d4ee4d25 DD |
492 | warning (0, "-g is only supported when using GAS on this processor,"); |
493 | warning (0, "-g option disabled"); | |
54eef932 JL |
494 | write_symbols = NO_DEBUG; |
495 | } | |
d07d525a | 496 | |
7ee72796 JL |
497 | /* We only support the "big PIC" model now. And we always generate PIC |
498 | code when in 64bit mode. */ | |
499 | if (flag_pic == 1 || TARGET_64BIT) | |
520babc7 JL |
500 | flag_pic = 2; |
501 | ||
301d03af RS |
502 | /* We can't guarantee that .dword is available for 32-bit targets. */ |
503 | if (UNITS_PER_WORD == 4) | |
504 | targetm.asm_out.aligned_op.di = NULL; | |
505 | ||
506 | /* The unaligned ops are only available when using GAS. */ | |
507 | if (!TARGET_GAS) | |
508 | { | |
509 | targetm.asm_out.unaligned_op.hi = NULL; | |
510 | targetm.asm_out.unaligned_op.si = NULL; | |
511 | targetm.asm_out.unaligned_op.di = NULL; | |
512 | } | |
9a55eab3 JDA |
513 | |
514 | init_machine_status = pa_init_machine_status; | |
c47decad JL |
515 | } |
516 | ||
eab9e742 | 517 | static void |
b7849684 | 518 | pa_init_builtins (void) |
4677862a JDA |
519 | { |
520 | #ifdef DONT_HAVE_FPUTC_UNLOCKED | |
b53b5aa5 KG |
521 | built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = |
522 | built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED]; | |
523 | implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] | |
524 | = implicit_built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED]; | |
4677862a | 525 | #endif |
dfcb2b51 | 526 | #if TARGET_HPUX_11 |
7d522000 SE |
527 | if (built_in_decls [BUILT_IN_FINITE]) |
528 | set_user_assembler_name (built_in_decls [BUILT_IN_FINITE], "_Isfinite"); | |
529 | if (built_in_decls [BUILT_IN_FINITEF]) | |
530 | set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF], "_Isfinitef"); | |
531 | #endif | |
4677862a JDA |
532 | } |
533 | ||
9a55eab3 JDA |
534 | /* Function to init struct machine_function. |
535 | This will be called, via a pointer variable, | |
536 | from push_function_context. */ | |
537 | ||
538 | static struct machine_function * | |
539 | pa_init_machine_status (void) | |
540 | { | |
5ead67f6 | 541 | return GGC_CNEW (machine_function); |
9a55eab3 JDA |
542 | } |
543 | ||
d8f95bed JDA |
544 | /* If FROM is a probable pointer register, mark TO as a probable |
545 | pointer register with the same pointer alignment as FROM. */ | |
546 | ||
547 | static void | |
548 | copy_reg_pointer (rtx to, rtx from) | |
549 | { | |
550 | if (REG_POINTER (from)) | |
551 | mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from))); | |
552 | } | |
553 | ||
23f6f34f TG |
554 | /* Return 1 if X contains a symbolic expression. We know these |
555 | expressions will have one of a few well defined forms, so | |
c1d1b3f0 JL |
556 | we need only check those forms. */ |
557 | int | |
b7849684 | 558 | symbolic_expression_p (rtx x) |
c1d1b3f0 JL |
559 | { |
560 | ||
fe19a83d | 561 | /* Strip off any HIGH. */ |
c1d1b3f0 JL |
562 | if (GET_CODE (x) == HIGH) |
563 | x = XEXP (x, 0); | |
564 | ||
565 | return (symbolic_operand (x, VOIDmode)); | |
566 | } | |
567 | ||
47abc309 | 568 | /* Accept any constant that can be moved in one instruction into a |
6746a52e | 569 | general register. */ |
23f6f34f | 570 | int |
5b281141 | 571 | cint_ok_for_move (HOST_WIDE_INT ival) |
6746a52e JL |
572 | { |
573 | /* OK if ldo, ldil, or zdepi, can be used. */ | |
5b281141 JDA |
574 | return (VAL_14_BITS_P (ival) |
575 | || ldil_cint_p (ival) | |
576 | || zdepi_cint_p (ival)); | |
6746a52e | 577 | } |
188538df | 578 | \f |
a18c2c5f JDA |
579 | /* Return truth value of whether OP can be used as an operand in a |
580 | adddi3 insn. */ | |
581 | int | |
b7849684 | 582 | adddi3_operand (rtx op, enum machine_mode mode) |
a18c2c5f JDA |
583 | { |
584 | return (register_operand (op, mode) | |
585 | || (GET_CODE (op) == CONST_INT | |
586 | && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op)))); | |
587 | } | |
588 | ||
5b281141 JDA |
589 | /* True iff the operand OP can be used as the destination operand of |
590 | an integer store. This also implies the operand could be used as | |
591 | the source operand of an integer load. Symbolic, lo_sum and indexed | |
592 | memory operands are not allowed. We accept reloading pseudos and | |
593 | other memory operands. */ | |
594 | int | |
595 | integer_store_memory_operand (rtx op, enum machine_mode mode) | |
596 | { | |
597 | return ((reload_in_progress | |
598 | && REG_P (op) | |
599 | && REGNO (op) >= FIRST_PSEUDO_REGISTER | |
600 | && reg_renumber [REGNO (op)] < 0) | |
601 | || (GET_CODE (op) == MEM | |
602 | && (reload_in_progress || memory_address_p (mode, XEXP (op, 0))) | |
603 | && !symbolic_memory_operand (op, VOIDmode) | |
604 | && !IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0)) | |
605 | && !IS_INDEX_ADDR_P (XEXP (op, 0)))); | |
606 | } | |
607 | ||
608 | /* True iff ldil can be used to load this CONST_INT. The least | |
609 | significant 11 bits of the value must be zero and the value must | |
610 | not change sign when extended from 32 to 64 bits. */ | |
611 | int | |
612 | ldil_cint_p (HOST_WIDE_INT ival) | |
613 | { | |
614 | HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff); | |
615 | ||
616 | return x == 0 || x == ((HOST_WIDE_INT) -1 << 31); | |
617 | } | |
618 | ||
831c1763 | 619 | /* True iff zdepi can be used to generate this CONST_INT. |
a7b376ee | 620 | zdepi first sign extends a 5-bit signed number to a given field |
831c1763 | 621 | length, then places this field anywhere in a zero. */ |
0e7f4c19 | 622 | int |
b7849684 | 623 | zdepi_cint_p (unsigned HOST_WIDE_INT x) |
3a5babac | 624 | { |
0c235d7e | 625 | unsigned HOST_WIDE_INT lsb_mask, t; |
3a5babac TG |
626 | |
627 | /* This might not be obvious, but it's at least fast. | |
ddd5a7c1 | 628 | This function is critical; we don't have the time loops would take. */ |
a1747d2c TG |
629 | lsb_mask = x & -x; |
630 | t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1); | |
631 | /* Return true iff t is a power of two. */ | |
3a5babac TG |
632 | return ((t & (t - 1)) == 0); |
633 | } | |
634 | ||
23f6f34f TG |
635 | /* True iff depi or extru can be used to compute (reg & mask). |
636 | Accept bit pattern like these: | |
637 | 0....01....1 | |
638 | 1....10....0 | |
639 | 1..10..01..1 */ | |
0e7f4c19 | 640 | int |
b7849684 | 641 | and_mask_p (unsigned HOST_WIDE_INT mask) |
0e7f4c19 TG |
642 | { |
643 | mask = ~mask; | |
644 | mask += mask & -mask; | |
645 | return (mask & (mask - 1)) == 0; | |
646 | } | |
647 | ||
0e7f4c19 TG |
648 | /* True iff depi can be used to compute (reg | MASK). */ |
649 | int | |
b7849684 | 650 | ior_mask_p (unsigned HOST_WIDE_INT mask) |
0e7f4c19 TG |
651 | { |
652 | mask += mask & -mask; | |
653 | return (mask & (mask - 1)) == 0; | |
654 | } | |
188538df TG |
655 | \f |
656 | /* Legitimize PIC addresses. If the address is already | |
657 | position-independent, we return ORIG. Newly generated | |
658 | position-independent addresses go to REG. If we need more | |
659 | than one register, we lose. */ | |
660 | ||
661 | rtx | |
b7849684 | 662 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
188538df TG |
663 | { |
664 | rtx pic_ref = orig; | |
665 | ||
06ae7eb1 | 666 | gcc_assert (!PA_SYMBOL_REF_TLS_P (orig)); |
51076f96 | 667 | |
abc95ed3 | 668 | /* Labels need special handling. */ |
519104fe | 669 | if (pic_label_operand (orig, mode)) |
6bb36601 | 670 | { |
4d811a05 JDA |
671 | rtx insn; |
672 | ||
b3d9ecf0 JL |
673 | /* We do not want to go through the movXX expanders here since that |
674 | would create recursion. | |
675 | ||
676 | Nor do we really want to call a generator for a named pattern | |
677 | since that requires multiple patterns if we want to support | |
678 | multiple word sizes. | |
679 | ||
680 | So instead we just emit the raw set, which avoids the movXX | |
681 | expanders completely. */ | |
d8f95bed | 682 | mark_reg_pointer (reg, BITS_PER_UNIT); |
4d811a05 JDA |
683 | insn = emit_insn (gen_rtx_SET (VOIDmode, reg, orig)); |
684 | ||
685 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
bbbbb16a | 686 | add_reg_note (insn, REG_EQUAL, orig); |
4d811a05 JDA |
687 | |
688 | /* During and after reload, we need to generate a REG_LABEL_OPERAND note | |
689 | and update LABEL_NUSES because this is not done automatically. */ | |
690 | if (reload_in_progress || reload_completed) | |
691 | { | |
692 | /* Extract LABEL_REF. */ | |
693 | if (GET_CODE (orig) == CONST) | |
694 | orig = XEXP (XEXP (orig, 0), 0); | |
695 | /* Extract CODE_LABEL. */ | |
696 | orig = XEXP (orig, 0); | |
65c5f2a6 | 697 | add_reg_note (insn, REG_LABEL_OPERAND, orig); |
4d811a05 JDA |
698 | LABEL_NUSES (orig)++; |
699 | } | |
e3b5732b | 700 | crtl->uses_pic_offset_table = 1; |
6bb36601 JL |
701 | return reg; |
702 | } | |
188538df TG |
703 | if (GET_CODE (orig) == SYMBOL_REF) |
704 | { | |
9ab81df2 JDA |
705 | rtx insn, tmp_reg; |
706 | ||
144d51f9 | 707 | gcc_assert (reg); |
188538df | 708 | |
9ab81df2 JDA |
709 | /* Before reload, allocate a temporary register for the intermediate |
710 | result. This allows the sequence to be deleted when the final | |
711 | result is unused and the insns are trivially dead. */ | |
712 | tmp_reg = ((reload_in_progress || reload_completed) | |
713 | ? reg : gen_reg_rtx (Pmode)); | |
714 | ||
f946206c | 715 | if (function_label_operand (orig, mode)) |
7813231b | 716 | { |
0b076fea JDA |
717 | /* Force function label into memory in word mode. */ |
718 | orig = XEXP (force_const_mem (word_mode, orig), 0); | |
7813231b JDA |
719 | /* Load plabel address from DLT. */ |
720 | emit_move_insn (tmp_reg, | |
721 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, | |
722 | gen_rtx_HIGH (word_mode, orig))); | |
723 | pic_ref | |
724 | = gen_const_mem (Pmode, | |
725 | gen_rtx_LO_SUM (Pmode, tmp_reg, | |
726 | gen_rtx_UNSPEC (Pmode, | |
542a8afa RH |
727 | gen_rtvec (1, orig), |
728 | UNSPEC_DLTIND14R))); | |
7813231b JDA |
729 | emit_move_insn (reg, pic_ref); |
730 | /* Now load address of function descriptor. */ | |
731 | pic_ref = gen_rtx_MEM (Pmode, reg); | |
732 | } | |
733 | else | |
734 | { | |
735 | /* Load symbol reference from DLT. */ | |
736 | emit_move_insn (tmp_reg, | |
737 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, | |
738 | gen_rtx_HIGH (word_mode, orig))); | |
739 | pic_ref | |
740 | = gen_const_mem (Pmode, | |
741 | gen_rtx_LO_SUM (Pmode, tmp_reg, | |
742 | gen_rtx_UNSPEC (Pmode, | |
743 | gen_rtvec (1, orig), | |
744 | UNSPEC_DLTIND14R))); | |
745 | } | |
c5c76735 | 746 | |
e3b5732b | 747 | crtl->uses_pic_offset_table = 1; |
d8f95bed | 748 | mark_reg_pointer (reg, BITS_PER_UNIT); |
9ab81df2 JDA |
749 | insn = emit_move_insn (reg, pic_ref); |
750 | ||
751 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
bd94cb6e | 752 | set_unique_reg_note (insn, REG_EQUAL, orig); |
9ab81df2 | 753 | |
188538df TG |
754 | return reg; |
755 | } | |
756 | else if (GET_CODE (orig) == CONST) | |
757 | { | |
f1c7ce82 | 758 | rtx base; |
188538df TG |
759 | |
760 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
761 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
762 | return orig; | |
763 | ||
144d51f9 NS |
764 | gcc_assert (reg); |
765 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); | |
766 | ||
767 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
768 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
769 | base == reg ? 0 : reg); | |
d8f95bed | 770 | |
188538df TG |
771 | if (GET_CODE (orig) == CONST_INT) |
772 | { | |
a1747d2c | 773 | if (INT_14_BITS (orig)) |
ed8908e7 | 774 | return plus_constant (base, INTVAL (orig)); |
188538df TG |
775 | orig = force_reg (Pmode, orig); |
776 | } | |
ad2c71b7 | 777 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
188538df TG |
778 | /* Likewise, should we set special REG_NOTEs here? */ |
779 | } | |
d8f95bed | 780 | |
188538df TG |
781 | return pic_ref; |
782 | } | |
783 | ||
51076f96 RC |
784 | static GTY(()) rtx gen_tls_tga; |
785 | ||
786 | static rtx | |
787 | gen_tls_get_addr (void) | |
788 | { | |
789 | if (!gen_tls_tga) | |
790 | gen_tls_tga = init_one_libfunc ("__tls_get_addr"); | |
791 | return gen_tls_tga; | |
792 | } | |
793 | ||
794 | static rtx | |
795 | hppa_tls_call (rtx arg) | |
796 | { | |
797 | rtx ret; | |
798 | ||
799 | ret = gen_reg_rtx (Pmode); | |
800 | emit_library_call_value (gen_tls_get_addr (), ret, | |
801 | LCT_CONST, Pmode, 1, arg, Pmode); | |
802 | ||
803 | return ret; | |
804 | } | |
805 | ||
806 | static rtx | |
807 | legitimize_tls_address (rtx addr) | |
808 | { | |
809 | rtx ret, insn, tmp, t1, t2, tp; | |
810 | enum tls_model model = SYMBOL_REF_TLS_MODEL (addr); | |
811 | ||
812 | switch (model) | |
813 | { | |
814 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
815 | tmp = gen_reg_rtx (Pmode); | |
a758fa89 AJ |
816 | if (flag_pic) |
817 | emit_insn (gen_tgd_load_pic (tmp, addr)); | |
818 | else | |
819 | emit_insn (gen_tgd_load (tmp, addr)); | |
51076f96 RC |
820 | ret = hppa_tls_call (tmp); |
821 | break; | |
822 | ||
823 | case TLS_MODEL_LOCAL_DYNAMIC: | |
824 | ret = gen_reg_rtx (Pmode); | |
825 | tmp = gen_reg_rtx (Pmode); | |
826 | start_sequence (); | |
a758fa89 AJ |
827 | if (flag_pic) |
828 | emit_insn (gen_tld_load_pic (tmp, addr)); | |
829 | else | |
830 | emit_insn (gen_tld_load (tmp, addr)); | |
51076f96 RC |
831 | t1 = hppa_tls_call (tmp); |
832 | insn = get_insns (); | |
833 | end_sequence (); | |
834 | t2 = gen_reg_rtx (Pmode); | |
835 | emit_libcall_block (insn, t2, t1, | |
836 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
837 | UNSPEC_TLSLDBASE)); | |
838 | emit_insn (gen_tld_offset_load (ret, addr, t2)); | |
839 | break; | |
840 | ||
841 | case TLS_MODEL_INITIAL_EXEC: | |
842 | tp = gen_reg_rtx (Pmode); | |
843 | tmp = gen_reg_rtx (Pmode); | |
844 | ret = gen_reg_rtx (Pmode); | |
845 | emit_insn (gen_tp_load (tp)); | |
a758fa89 AJ |
846 | if (flag_pic) |
847 | emit_insn (gen_tie_load_pic (tmp, addr)); | |
848 | else | |
849 | emit_insn (gen_tie_load (tmp, addr)); | |
51076f96 RC |
850 | emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp)); |
851 | break; | |
852 | ||
853 | case TLS_MODEL_LOCAL_EXEC: | |
854 | tp = gen_reg_rtx (Pmode); | |
855 | ret = gen_reg_rtx (Pmode); | |
856 | emit_insn (gen_tp_load (tp)); | |
857 | emit_insn (gen_tle_load (ret, addr, tp)); | |
858 | break; | |
859 | ||
860 | default: | |
06ae7eb1 | 861 | gcc_unreachable (); |
51076f96 RC |
862 | } |
863 | ||
864 | return ret; | |
865 | } | |
866 | ||
c1d1b3f0 JL |
867 | /* Try machine-dependent ways of modifying an illegitimate address |
868 | to be legitimate. If we find one, return the new, valid address. | |
869 | This macro is used in only one place: `memory_address' in explow.c. | |
870 | ||
871 | OLDX is the address as it was before break_out_memory_refs was called. | |
872 | In some cases it is useful to look at this to decide what needs to be done. | |
873 | ||
c1d1b3f0 | 874 | It is always safe for this macro to do nothing. It exists to recognize |
23f6f34f | 875 | opportunities to optimize the output. |
c1d1b3f0 JL |
876 | |
877 | For the PA, transform: | |
878 | ||
879 | memory(X + <large int>) | |
880 | ||
881 | into: | |
882 | ||
883 | if (<large int> & mask) >= 16 | |
884 | Y = (<large int> & ~mask) + mask + 1 Round up. | |
885 | else | |
886 | Y = (<large int> & ~mask) Round down. | |
887 | Z = X + Y | |
888 | memory (Z + (<large int> - Y)); | |
889 | ||
23f6f34f | 890 | This is for CSE to find several similar references, and only use one Z. |
c1d1b3f0 | 891 | |
1e5f1716 | 892 | X can either be a SYMBOL_REF or REG, but because combine cannot |
c1d1b3f0 JL |
893 | perform a 4->2 combination we do nothing for SYMBOL_REF + D where |
894 | D will not fit in 14 bits. | |
895 | ||
896 | MODE_FLOAT references allow displacements which fit in 5 bits, so use | |
23f6f34f | 897 | 0x1f as the mask. |
c1d1b3f0 JL |
898 | |
899 | MODE_INT references allow displacements which fit in 14 bits, so use | |
23f6f34f | 900 | 0x3fff as the mask. |
c1d1b3f0 JL |
901 | |
902 | This relies on the fact that most mode MODE_FLOAT references will use FP | |
903 | registers and most mode MODE_INT references will use integer registers. | |
904 | (In the rare case of an FP register used in an integer MODE, we depend | |
905 | on secondary reloads to clean things up.) | |
906 | ||
907 | ||
908 | It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special | |
909 | manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed | |
ddd5a7c1 | 910 | addressing modes to be used). |
c1d1b3f0 JL |
911 | |
912 | Put X and Z into registers. Then put the entire expression into | |
913 | a register. */ | |
914 | ||
915 | rtx | |
b7849684 JE |
916 | hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
917 | enum machine_mode mode) | |
c1d1b3f0 | 918 | { |
c1d1b3f0 JL |
919 | rtx orig = x; |
920 | ||
d8f95bed JDA |
921 | /* We need to canonicalize the order of operands in unscaled indexed |
922 | addresses since the code that checks if an address is valid doesn't | |
923 | always try both orders. */ | |
924 | if (!TARGET_NO_SPACE_REGS | |
925 | && GET_CODE (x) == PLUS | |
926 | && GET_MODE (x) == Pmode | |
927 | && REG_P (XEXP (x, 0)) | |
928 | && REG_P (XEXP (x, 1)) | |
929 | && REG_POINTER (XEXP (x, 0)) | |
930 | && !REG_POINTER (XEXP (x, 1))) | |
931 | return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0)); | |
932 | ||
51076f96 RC |
933 | if (PA_SYMBOL_REF_TLS_P (x)) |
934 | return legitimize_tls_address (x); | |
935 | else if (flag_pic) | |
6bb36601 JL |
936 | return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); |
937 | ||
fe19a83d | 938 | /* Strip off CONST. */ |
c1d1b3f0 JL |
939 | if (GET_CODE (x) == CONST) |
940 | x = XEXP (x, 0); | |
941 | ||
68944452 JL |
942 | /* Special case. Get the SYMBOL_REF into a register and use indexing. |
943 | That should always be safe. */ | |
944 | if (GET_CODE (x) == PLUS | |
945 | && GET_CODE (XEXP (x, 0)) == REG | |
946 | && GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
947 | { | |
690d4228 JL |
948 | rtx reg = force_reg (Pmode, XEXP (x, 1)); |
949 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0))); | |
68944452 JL |
950 | } |
951 | ||
326bc2de JL |
952 | /* Note we must reject symbols which represent function addresses |
953 | since the assembler/linker can't handle arithmetic on plabels. */ | |
c1d1b3f0 JL |
954 | if (GET_CODE (x) == PLUS |
955 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
326bc2de JL |
956 | && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF |
957 | && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0))) | |
c1d1b3f0 JL |
958 | || GET_CODE (XEXP (x, 0)) == REG)) |
959 | { | |
960 | rtx int_part, ptr_reg; | |
961 | int newoffset; | |
962 | int offset = INTVAL (XEXP (x, 1)); | |
f9bd8d8e JL |
963 | int mask; |
964 | ||
965 | mask = (GET_MODE_CLASS (mode) == MODE_FLOAT | |
94919bd2 | 966 | ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff); |
c1d1b3f0 | 967 | |
23f6f34f | 968 | /* Choose which way to round the offset. Round up if we |
c1d1b3f0 JL |
969 | are >= halfway to the next boundary. */ |
970 | if ((offset & mask) >= ((mask + 1) / 2)) | |
971 | newoffset = (offset & ~ mask) + mask + 1; | |
972 | else | |
973 | newoffset = (offset & ~ mask); | |
974 | ||
975 | /* If the newoffset will not fit in 14 bits (ldo), then | |
976 | handling this would take 4 or 5 instructions (2 to load | |
977 | the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to | |
978 | add the new offset and the SYMBOL_REF.) Combine can | |
979 | not handle 4->2 or 5->2 combinations, so do not create | |
980 | them. */ | |
981 | if (! VAL_14_BITS_P (newoffset) | |
982 | && GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
983 | { | |
c5c76735 | 984 | rtx const_part = plus_constant (XEXP (x, 0), newoffset); |
c1d1b3f0 | 985 | rtx tmp_reg |
e5e28962 | 986 | = force_reg (Pmode, |
ad2c71b7 | 987 | gen_rtx_HIGH (Pmode, const_part)); |
c1d1b3f0 | 988 | ptr_reg |
e5e28962 | 989 | = force_reg (Pmode, |
c5c76735 JL |
990 | gen_rtx_LO_SUM (Pmode, |
991 | tmp_reg, const_part)); | |
c1d1b3f0 JL |
992 | } |
993 | else | |
994 | { | |
995 | if (! VAL_14_BITS_P (newoffset)) | |
e5e28962 | 996 | int_part = force_reg (Pmode, GEN_INT (newoffset)); |
c1d1b3f0 JL |
997 | else |
998 | int_part = GEN_INT (newoffset); | |
999 | ||
e5e28962 | 1000 | ptr_reg = force_reg (Pmode, |
ad2c71b7 JL |
1001 | gen_rtx_PLUS (Pmode, |
1002 | force_reg (Pmode, XEXP (x, 0)), | |
1003 | int_part)); | |
c1d1b3f0 JL |
1004 | } |
1005 | return plus_constant (ptr_reg, offset - newoffset); | |
1006 | } | |
7426c959 | 1007 | |
78c0acfd | 1008 | /* Handle (plus (mult (a) (shadd_constant)) (b)). */ |
7426c959 | 1009 | |
c1d1b3f0 JL |
1010 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT |
1011 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
7426c959 | 1012 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))) |
ec8e098d | 1013 | && (OBJECT_P (XEXP (x, 1)) |
7426c959 JL |
1014 | || GET_CODE (XEXP (x, 1)) == SUBREG) |
1015 | && GET_CODE (XEXP (x, 1)) != CONST) | |
c1d1b3f0 JL |
1016 | { |
1017 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1018 | rtx reg1, reg2; | |
78c0acfd JL |
1019 | |
1020 | reg1 = XEXP (x, 1); | |
1021 | if (GET_CODE (reg1) != REG) | |
1022 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1023 | ||
1024 | reg2 = XEXP (XEXP (x, 0), 0); | |
1025 | if (GET_CODE (reg2) != REG) | |
1026 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1027 | ||
ad2c71b7 | 1028 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
c5c76735 JL |
1029 | gen_rtx_MULT (Pmode, |
1030 | reg2, | |
1031 | GEN_INT (val)), | |
ad2c71b7 | 1032 | reg1)); |
c1d1b3f0 | 1033 | } |
7426c959 | 1034 | |
305123ba JL |
1035 | /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)). |
1036 | ||
1037 | Only do so for floating point modes since this is more speculative | |
1038 | and we lose if it's an integer store. */ | |
78c0acfd | 1039 | if (GET_CODE (x) == PLUS |
305123ba JL |
1040 | && GET_CODE (XEXP (x, 0)) == PLUS |
1041 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
1042 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
78c0acfd JL |
1043 | && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) |
1044 | && (mode == SFmode || mode == DFmode)) | |
305123ba | 1045 | { |
78c0acfd JL |
1046 | |
1047 | /* First, try and figure out what to use as a base register. */ | |
1048 | rtx reg1, reg2, base, idx, orig_base; | |
1049 | ||
1050 | reg1 = XEXP (XEXP (x, 0), 1); | |
1051 | reg2 = XEXP (x, 1); | |
1052 | base = NULL_RTX; | |
1053 | idx = NULL_RTX; | |
1054 | ||
1055 | /* Make sure they're both regs. If one was a SYMBOL_REF [+ const], | |
3502dc9c JDA |
1056 | then emit_move_sequence will turn on REG_POINTER so we'll know |
1057 | it's a base register below. */ | |
78c0acfd JL |
1058 | if (GET_CODE (reg1) != REG) |
1059 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1060 | ||
1061 | if (GET_CODE (reg2) != REG) | |
1062 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1063 | ||
1064 | /* Figure out what the base and index are. */ | |
6619e96c | 1065 | |
78c0acfd | 1066 | if (GET_CODE (reg1) == REG |
3502dc9c | 1067 | && REG_POINTER (reg1)) |
78c0acfd JL |
1068 | { |
1069 | base = reg1; | |
1070 | orig_base = XEXP (XEXP (x, 0), 1); | |
ad2c71b7 JL |
1071 | idx = gen_rtx_PLUS (Pmode, |
1072 | gen_rtx_MULT (Pmode, | |
1073 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
1074 | XEXP (XEXP (XEXP (x, 0), 0), 1)), | |
1075 | XEXP (x, 1)); | |
78c0acfd JL |
1076 | } |
1077 | else if (GET_CODE (reg2) == REG | |
3502dc9c | 1078 | && REG_POINTER (reg2)) |
78c0acfd JL |
1079 | { |
1080 | base = reg2; | |
1081 | orig_base = XEXP (x, 1); | |
1082 | idx = XEXP (x, 0); | |
1083 | } | |
1084 | ||
1085 | if (base == 0) | |
31d4f31f | 1086 | return orig; |
78c0acfd JL |
1087 | |
1088 | /* If the index adds a large constant, try to scale the | |
1089 | constant so that it can be loaded with only one insn. */ | |
1090 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1091 | && VAL_14_BITS_P (INTVAL (XEXP (idx, 1)) | |
1092 | / INTVAL (XEXP (XEXP (idx, 0), 1))) | |
1093 | && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0) | |
1094 | { | |
1095 | /* Divide the CONST_INT by the scale factor, then add it to A. */ | |
1096 | int val = INTVAL (XEXP (idx, 1)); | |
1097 | ||
1098 | val /= INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1099 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1100 | if (GET_CODE (reg1) != REG) | |
1101 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1102 | ||
ad2c71b7 | 1103 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val))); |
78c0acfd JL |
1104 | |
1105 | /* We can now generate a simple scaled indexed address. */ | |
c5c76735 JL |
1106 | return |
1107 | force_reg | |
1108 | (Pmode, gen_rtx_PLUS (Pmode, | |
1109 | gen_rtx_MULT (Pmode, reg1, | |
1110 | XEXP (XEXP (idx, 0), 1)), | |
1111 | base)); | |
78c0acfd JL |
1112 | } |
1113 | ||
1114 | /* If B + C is still a valid base register, then add them. */ | |
1115 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1116 | && INTVAL (XEXP (idx, 1)) <= 4096 | |
1117 | && INTVAL (XEXP (idx, 1)) >= -4096) | |
1118 | { | |
1119 | int val = INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1120 | rtx reg1, reg2; | |
1121 | ||
ad2c71b7 | 1122 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1))); |
78c0acfd JL |
1123 | |
1124 | reg2 = XEXP (XEXP (idx, 0), 0); | |
1125 | if (GET_CODE (reg2) != CONST_INT) | |
1126 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1127 | ||
ad2c71b7 | 1128 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
c5c76735 JL |
1129 | gen_rtx_MULT (Pmode, |
1130 | reg2, | |
ad2c71b7 JL |
1131 | GEN_INT (val)), |
1132 | reg1)); | |
78c0acfd JL |
1133 | } |
1134 | ||
1135 | /* Get the index into a register, then add the base + index and | |
1136 | return a register holding the result. */ | |
1137 | ||
1138 | /* First get A into a register. */ | |
1139 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1140 | if (GET_CODE (reg1) != REG) | |
1141 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1142 | ||
1143 | /* And get B into a register. */ | |
1144 | reg2 = XEXP (idx, 1); | |
1145 | if (GET_CODE (reg2) != REG) | |
1146 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1147 | ||
ad2c71b7 JL |
1148 | reg1 = force_reg (Pmode, |
1149 | gen_rtx_PLUS (Pmode, | |
1150 | gen_rtx_MULT (Pmode, reg1, | |
1151 | XEXP (XEXP (idx, 0), 1)), | |
1152 | reg2)); | |
78c0acfd JL |
1153 | |
1154 | /* Add the result to our base register and return. */ | |
ad2c71b7 | 1155 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1)); |
6619e96c | 1156 | |
305123ba JL |
1157 | } |
1158 | ||
23f6f34f | 1159 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
c2827c50 JL |
1160 | special handling to avoid creating an indexed memory address |
1161 | with x-100000 as the base. | |
6619e96c | 1162 | |
c2827c50 JL |
1163 | If the constant part is small enough, then it's still safe because |
1164 | there is a guard page at the beginning and end of the data segment. | |
1165 | ||
1166 | Scaled references are common enough that we want to try and rearrange the | |
1167 | terms so that we can use indexing for these addresses too. Only | |
305123ba | 1168 | do the optimization for floatint point modes. */ |
7426c959 | 1169 | |
c2827c50 JL |
1170 | if (GET_CODE (x) == PLUS |
1171 | && symbolic_expression_p (XEXP (x, 1))) | |
7426c959 JL |
1172 | { |
1173 | /* Ugly. We modify things here so that the address offset specified | |
1174 | by the index expression is computed first, then added to x to form | |
c2827c50 | 1175 | the entire address. */ |
7426c959 | 1176 | |
305123ba | 1177 | rtx regx1, regx2, regy1, regy2, y; |
7426c959 JL |
1178 | |
1179 | /* Strip off any CONST. */ | |
1180 | y = XEXP (x, 1); | |
1181 | if (GET_CODE (y) == CONST) | |
1182 | y = XEXP (y, 0); | |
1183 | ||
77fc9313 RK |
1184 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1185 | { | |
305123ba JL |
1186 | /* See if this looks like |
1187 | (plus (mult (reg) (shadd_const)) | |
1188 | (const (plus (symbol_ref) (const_int)))) | |
1189 | ||
78c0acfd | 1190 | Where const_int is small. In that case the const |
6619e96c | 1191 | expression is a valid pointer for indexing. |
78c0acfd JL |
1192 | |
1193 | If const_int is big, but can be divided evenly by shadd_const | |
1194 | and added to (reg). This allows more scaled indexed addresses. */ | |
1195 | if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1196 | && GET_CODE (XEXP (x, 0)) == MULT | |
305123ba | 1197 | && GET_CODE (XEXP (y, 1)) == CONST_INT |
78c0acfd JL |
1198 | && INTVAL (XEXP (y, 1)) >= -4096 |
1199 | && INTVAL (XEXP (y, 1)) <= 4095 | |
1200 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1201 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
1202 | { | |
1203 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1204 | rtx reg1, reg2; | |
1205 | ||
1206 | reg1 = XEXP (x, 1); | |
1207 | if (GET_CODE (reg1) != REG) | |
1208 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1209 | ||
1210 | reg2 = XEXP (XEXP (x, 0), 0); | |
1211 | if (GET_CODE (reg2) != REG) | |
1212 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1213 | ||
ad2c71b7 JL |
1214 | return force_reg (Pmode, |
1215 | gen_rtx_PLUS (Pmode, | |
c5c76735 JL |
1216 | gen_rtx_MULT (Pmode, |
1217 | reg2, | |
ad2c71b7 | 1218 | GEN_INT (val)), |
c5c76735 | 1219 | reg1)); |
78c0acfd JL |
1220 | } |
1221 | else if ((mode == DFmode || mode == SFmode) | |
1222 | && GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1223 | && GET_CODE (XEXP (x, 0)) == MULT | |
1224 | && GET_CODE (XEXP (y, 1)) == CONST_INT | |
1225 | && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0 | |
1226 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1227 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
305123ba JL |
1228 | { |
1229 | regx1 | |
1230 | = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1)) | |
1231 | / INTVAL (XEXP (XEXP (x, 0), 1)))); | |
1232 | regx2 = XEXP (XEXP (x, 0), 0); | |
1233 | if (GET_CODE (regx2) != REG) | |
1234 | regx2 = force_reg (Pmode, force_operand (regx2, 0)); | |
ad2c71b7 JL |
1235 | regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1236 | regx2, regx1)); | |
c5c76735 JL |
1237 | return |
1238 | force_reg (Pmode, | |
1239 | gen_rtx_PLUS (Pmode, | |
1240 | gen_rtx_MULT (Pmode, regx2, | |
1241 | XEXP (XEXP (x, 0), 1)), | |
1242 | force_reg (Pmode, XEXP (y, 0)))); | |
305123ba | 1243 | } |
c2827c50 JL |
1244 | else if (GET_CODE (XEXP (y, 1)) == CONST_INT |
1245 | && INTVAL (XEXP (y, 1)) >= -4096 | |
1246 | && INTVAL (XEXP (y, 1)) <= 4095) | |
1247 | { | |
1248 | /* This is safe because of the guard page at the | |
1249 | beginning and end of the data space. Just | |
1250 | return the original address. */ | |
1251 | return orig; | |
1252 | } | |
305123ba JL |
1253 | else |
1254 | { | |
1255 | /* Doesn't look like one we can optimize. */ | |
1256 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1257 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1258 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1259 | regx1 = force_reg (Pmode, | |
ad2c71b7 JL |
1260 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1261 | regx1, regy2)); | |
1262 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); | |
305123ba | 1263 | } |
77fc9313 | 1264 | } |
7426c959 JL |
1265 | } |
1266 | ||
c1d1b3f0 JL |
1267 | return orig; |
1268 | } | |
1269 | ||
188538df TG |
1270 | /* For the HPPA, REG and REG+CONST is cost 0 |
1271 | and addresses involving symbolic constants are cost 2. | |
1272 | ||
1273 | PIC addresses are very expensive. | |
1274 | ||
1275 | It is no coincidence that this has the same structure | |
1276 | as GO_IF_LEGITIMATE_ADDRESS. */ | |
dcefdf67 RH |
1277 | |
1278 | static int | |
f40751dd JH |
1279 | hppa_address_cost (rtx X, |
1280 | bool speed ATTRIBUTE_UNUSED) | |
188538df | 1281 | { |
dcefdf67 RH |
1282 | switch (GET_CODE (X)) |
1283 | { | |
1284 | case REG: | |
1285 | case PLUS: | |
1286 | case LO_SUM: | |
188538df | 1287 | return 1; |
dcefdf67 RH |
1288 | case HIGH: |
1289 | return 2; | |
1290 | default: | |
1291 | return 4; | |
1292 | } | |
188538df TG |
1293 | } |
1294 | ||
3c50106f RH |
1295 | /* Compute a (partial) cost for rtx X. Return true if the complete |
1296 | cost has been computed, and false if subexpressions should be | |
1297 | scanned. In either case, *TOTAL contains the cost result. */ | |
1298 | ||
1299 | static bool | |
f40751dd JH |
1300 | hppa_rtx_costs (rtx x, int code, int outer_code, int *total, |
1301 | bool speed ATTRIBUTE_UNUSED) | |
3c50106f RH |
1302 | { |
1303 | switch (code) | |
1304 | { | |
1305 | case CONST_INT: | |
1306 | if (INTVAL (x) == 0) | |
1307 | *total = 0; | |
1308 | else if (INT_14_BITS (x)) | |
1309 | *total = 1; | |
1310 | else | |
1311 | *total = 2; | |
1312 | return true; | |
1313 | ||
1314 | case HIGH: | |
1315 | *total = 2; | |
1316 | return true; | |
1317 | ||
1318 | case CONST: | |
1319 | case LABEL_REF: | |
1320 | case SYMBOL_REF: | |
1321 | *total = 4; | |
1322 | return true; | |
1323 | ||
1324 | case CONST_DOUBLE: | |
1325 | if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode)) | |
1326 | && outer_code != SET) | |
1327 | *total = 0; | |
1328 | else | |
1329 | *total = 8; | |
1330 | return true; | |
1331 | ||
1332 | case MULT: | |
1333 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1334 | *total = COSTS_N_INSNS (3); | |
1335 | else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT) | |
1336 | *total = COSTS_N_INSNS (8); | |
1337 | else | |
1338 | *total = COSTS_N_INSNS (20); | |
1339 | return true; | |
1340 | ||
1341 | case DIV: | |
1342 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1343 | { | |
1344 | *total = COSTS_N_INSNS (14); | |
1345 | return true; | |
1346 | } | |
5efb1046 | 1347 | /* FALLTHRU */ |
3c50106f RH |
1348 | |
1349 | case UDIV: | |
1350 | case MOD: | |
1351 | case UMOD: | |
1352 | *total = COSTS_N_INSNS (60); | |
1353 | return true; | |
1354 | ||
1355 | case PLUS: /* this includes shNadd insns */ | |
1356 | case MINUS: | |
1357 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1358 | *total = COSTS_N_INSNS (3); | |
1359 | else | |
1360 | *total = COSTS_N_INSNS (1); | |
1361 | return true; | |
1362 | ||
1363 | case ASHIFT: | |
1364 | case ASHIFTRT: | |
1365 | case LSHIFTRT: | |
1366 | *total = COSTS_N_INSNS (1); | |
1367 | return true; | |
1368 | ||
1369 | default: | |
1370 | return false; | |
1371 | } | |
1372 | } | |
1373 | ||
6619e96c AM |
1374 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a |
1375 | new rtx with the correct mode. */ | |
1376 | static inline rtx | |
b7849684 | 1377 | force_mode (enum machine_mode mode, rtx orig) |
6619e96c AM |
1378 | { |
1379 | if (mode == GET_MODE (orig)) | |
1380 | return orig; | |
1381 | ||
144d51f9 | 1382 | gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER); |
6619e96c AM |
1383 | |
1384 | return gen_rtx_REG (mode, REGNO (orig)); | |
1385 | } | |
1386 | ||
51076f96 RC |
1387 | /* Return 1 if *X is a thread-local symbol. */ |
1388 | ||
1389 | static int | |
1390 | pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
1391 | { | |
1392 | return PA_SYMBOL_REF_TLS_P (*x); | |
1393 | } | |
1394 | ||
1395 | /* Return 1 if X contains a thread-local symbol. */ | |
1396 | ||
1397 | bool | |
1398 | pa_tls_referenced_p (rtx x) | |
1399 | { | |
1400 | if (!TARGET_HAVE_TLS) | |
1401 | return false; | |
1402 | ||
1403 | return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0); | |
1404 | } | |
1405 | ||
188538df TG |
1406 | /* Emit insns to move operands[1] into operands[0]. |
1407 | ||
1408 | Return 1 if we have written out everything that needs to be done to | |
1409 | do the move. Otherwise, return 0 and the caller will emit the move | |
6619e96c | 1410 | normally. |
1b8ad134 JL |
1411 | |
1412 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
c1207243 | 1413 | will be used. This routine is responsible for creating a new copy |
1b8ad134 | 1414 | of SCRATCH_REG in the proper mode. */ |
188538df TG |
1415 | |
1416 | int | |
b7849684 | 1417 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) |
188538df TG |
1418 | { |
1419 | register rtx operand0 = operands[0]; | |
1420 | register rtx operand1 = operands[1]; | |
428be702 | 1421 | register rtx tem; |
188538df | 1422 | |
d8f95bed JDA |
1423 | /* We can only handle indexed addresses in the destination operand |
1424 | of floating point stores. Thus, we need to break out indexed | |
1425 | addresses from the destination operand. */ | |
1426 | if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0))) | |
1427 | { | |
b3a13419 | 1428 | gcc_assert (can_create_pseudo_p ()); |
d8f95bed JDA |
1429 | |
1430 | tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0)); | |
1431 | operand0 = replace_equiv_address (operand0, tem); | |
1432 | } | |
1433 | ||
1434 | /* On targets with non-equivalent space registers, break out unscaled | |
1435 | indexed addresses from the source operand before the final CSE. | |
1436 | We have to do this because the REG_POINTER flag is not correctly | |
1437 | carried through various optimization passes and CSE may substitute | |
1438 | a pseudo without the pointer set for one with the pointer set. As | |
71cc389b | 1439 | a result, we loose various opportunities to create insns with |
d8f95bed JDA |
1440 | unscaled indexed addresses. */ |
1441 | if (!TARGET_NO_SPACE_REGS | |
1442 | && !cse_not_expected | |
1443 | && GET_CODE (operand1) == MEM | |
1444 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1445 | && REG_P (XEXP (XEXP (operand1, 0), 0)) | |
1446 | && REG_P (XEXP (XEXP (operand1, 0), 1))) | |
1447 | operand1 | |
1448 | = replace_equiv_address (operand1, | |
1449 | copy_to_mode_reg (Pmode, XEXP (operand1, 0))); | |
1450 | ||
54d65918 JL |
1451 | if (scratch_reg |
1452 | && reload_in_progress && GET_CODE (operand0) == REG | |
8a642d97 RK |
1453 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) |
1454 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
54d65918 JL |
1455 | else if (scratch_reg |
1456 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
8a642d97 RK |
1457 | && GET_CODE (SUBREG_REG (operand0)) == REG |
1458 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
27a2c2b5 | 1459 | { |
ddef6bc7 | 1460 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
71443006 JL |
1461 | the code which tracks sets/uses for delete_output_reload. */ |
1462 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
1463 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
ddef6bc7 | 1464 | SUBREG_BYTE (operand0)); |
847898f6 | 1465 | operand0 = alter_subreg (&temp); |
27a2c2b5 | 1466 | } |
8a642d97 | 1467 | |
54d65918 JL |
1468 | if (scratch_reg |
1469 | && reload_in_progress && GET_CODE (operand1) == REG | |
8a642d97 RK |
1470 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) |
1471 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
54d65918 JL |
1472 | else if (scratch_reg |
1473 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
8a642d97 RK |
1474 | && GET_CODE (SUBREG_REG (operand1)) == REG |
1475 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
27a2c2b5 | 1476 | { |
ddef6bc7 | 1477 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
71443006 JL |
1478 | the code which tracks sets/uses for delete_output_reload. */ |
1479 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
1480 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
ddef6bc7 | 1481 | SUBREG_BYTE (operand1)); |
847898f6 | 1482 | operand1 = alter_subreg (&temp); |
27a2c2b5 | 1483 | } |
8a642d97 | 1484 | |
54d65918 | 1485 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM |
428be702 RK |
1486 | && ((tem = find_replacement (&XEXP (operand0, 0))) |
1487 | != XEXP (operand0, 0))) | |
7c95bbfb | 1488 | operand0 = replace_equiv_address (operand0, tem); |
d8f95bed | 1489 | |
54d65918 | 1490 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM |
428be702 RK |
1491 | && ((tem = find_replacement (&XEXP (operand1, 0))) |
1492 | != XEXP (operand1, 0))) | |
7c95bbfb | 1493 | operand1 = replace_equiv_address (operand1, tem); |
428be702 | 1494 | |
4d3cea21 | 1495 | /* Handle secondary reloads for loads/stores of FP registers from |
cae80939 | 1496 | REG+D addresses where D does not fit in 5 or 14 bits, including |
68944452 | 1497 | (subreg (mem (addr))) cases. */ |
a4295210 JDA |
1498 | if (scratch_reg |
1499 | && fp_reg_operand (operand0, mode) | |
42fbe27f | 1500 | && ((GET_CODE (operand1) == MEM |
cae80939 JDA |
1501 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode), |
1502 | XEXP (operand1, 0))) | |
42fbe27f JL |
1503 | || ((GET_CODE (operand1) == SUBREG |
1504 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
cae80939 JDA |
1505 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1506 | ? SFmode : DFmode), | |
1507 | XEXP (XEXP (operand1, 0), 0)))))) | |
d2a94ec0 | 1508 | { |
42fbe27f JL |
1509 | if (GET_CODE (operand1) == SUBREG) |
1510 | operand1 = XEXP (operand1, 0); | |
1511 | ||
1b8ad134 JL |
1512 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1513 | it in WORD_MODE regardless of what mode it was originally given | |
1514 | to us. */ | |
6619e96c | 1515 | scratch_reg = force_mode (word_mode, scratch_reg); |
2d7b2c36 JL |
1516 | |
1517 | /* D might not fit in 14 bits either; for such cases load D into | |
1518 | scratch reg. */ | |
690d4228 | 1519 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) |
2d7b2c36 JL |
1520 | { |
1521 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
d8f95bed JDA |
1522 | emit_move_insn (scratch_reg, |
1523 | gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
1524 | Pmode, | |
1525 | XEXP (XEXP (operand1, 0), 0), | |
1526 | scratch_reg)); | |
2d7b2c36 JL |
1527 | } |
1528 | else | |
1529 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
c5c76735 | 1530 | emit_insn (gen_rtx_SET (VOIDmode, operand0, |
7c95bbfb | 1531 | replace_equiv_address (operand1, scratch_reg))); |
d2a94ec0 TM |
1532 | return 1; |
1533 | } | |
a4295210 JDA |
1534 | else if (scratch_reg |
1535 | && fp_reg_operand (operand1, mode) | |
42fbe27f | 1536 | && ((GET_CODE (operand0) == MEM |
cae80939 JDA |
1537 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1538 | ? SFmode : DFmode), | |
1539 | XEXP (operand0, 0))) | |
42fbe27f JL |
1540 | || ((GET_CODE (operand0) == SUBREG) |
1541 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
cae80939 JDA |
1542 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1543 | ? SFmode : DFmode), | |
a4295210 | 1544 | XEXP (XEXP (operand0, 0), 0))))) |
d2a94ec0 | 1545 | { |
42fbe27f JL |
1546 | if (GET_CODE (operand0) == SUBREG) |
1547 | operand0 = XEXP (operand0, 0); | |
1548 | ||
1b8ad134 JL |
1549 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1550 | it in WORD_MODE regardless of what mode it was originally given | |
1551 | to us. */ | |
6619e96c | 1552 | scratch_reg = force_mode (word_mode, scratch_reg); |
1b8ad134 | 1553 | |
2d7b2c36 JL |
1554 | /* D might not fit in 14 bits either; for such cases load D into |
1555 | scratch reg. */ | |
690d4228 | 1556 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) |
2d7b2c36 JL |
1557 | { |
1558 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
ad2c71b7 JL |
1559 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, |
1560 | 0)), | |
690d4228 | 1561 | Pmode, |
ad2c71b7 JL |
1562 | XEXP (XEXP (operand0, 0), |
1563 | 0), | |
1564 | scratch_reg)); | |
2d7b2c36 JL |
1565 | } |
1566 | else | |
1567 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
7c95bbfb RH |
1568 | emit_insn (gen_rtx_SET (VOIDmode, |
1569 | replace_equiv_address (operand0, scratch_reg), | |
ad2c71b7 | 1570 | operand1)); |
d2a94ec0 TM |
1571 | return 1; |
1572 | } | |
c063ad75 JL |
1573 | /* Handle secondary reloads for loads of FP registers from constant |
1574 | expressions by forcing the constant into memory. | |
1575 | ||
a4295210 | 1576 | Use scratch_reg to hold the address of the memory location. |
c063ad75 | 1577 | |
8c417c25 | 1578 | The proper fix is to change PREFERRED_RELOAD_CLASS to return |
5bdc5878 | 1579 | NO_REGS when presented with a const_int and a register class |
c063ad75 JL |
1580 | containing only FP registers. Doing so unfortunately creates |
1581 | more problems than it solves. Fix this for 2.5. */ | |
a4295210 | 1582 | else if (scratch_reg |
c063ad75 | 1583 | && CONSTANT_P (operand1) |
a4295210 | 1584 | && fp_reg_operand (operand0, mode)) |
c063ad75 | 1585 | { |
7c95bbfb | 1586 | rtx const_mem, xoperands[2]; |
c063ad75 | 1587 | |
1b8ad134 JL |
1588 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1589 | it in WORD_MODE regardless of what mode it was originally given | |
1590 | to us. */ | |
6619e96c | 1591 | scratch_reg = force_mode (word_mode, scratch_reg); |
1b8ad134 | 1592 | |
c063ad75 JL |
1593 | /* Force the constant into memory and put the address of the |
1594 | memory location into scratch_reg. */ | |
7c95bbfb | 1595 | const_mem = force_const_mem (mode, operand1); |
c063ad75 | 1596 | xoperands[0] = scratch_reg; |
7c95bbfb | 1597 | xoperands[1] = XEXP (const_mem, 0); |
669054c1 | 1598 | emit_move_sequence (xoperands, Pmode, 0); |
c063ad75 JL |
1599 | |
1600 | /* Now load the destination register. */ | |
c5c76735 | 1601 | emit_insn (gen_rtx_SET (mode, operand0, |
7c95bbfb | 1602 | replace_equiv_address (const_mem, scratch_reg))); |
c063ad75 JL |
1603 | return 1; |
1604 | } | |
4d3cea21 | 1605 | /* Handle secondary reloads for SAR. These occur when trying to load |
9c1eed37 | 1606 | the SAR from memory, FP register, or with a constant. */ |
a4295210 JDA |
1607 | else if (scratch_reg |
1608 | && GET_CODE (operand0) == REG | |
9c1eed37 | 1609 | && REGNO (operand0) < FIRST_PSEUDO_REGISTER |
4d3cea21 JL |
1610 | && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS |
1611 | && (GET_CODE (operand1) == MEM | |
2c51d187 | 1612 | || GET_CODE (operand1) == CONST_INT |
4d3cea21 | 1613 | || (GET_CODE (operand1) == REG |
a4295210 | 1614 | && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))) |
4d3cea21 | 1615 | { |
09ece7b5 JL |
1616 | /* D might not fit in 14 bits either; for such cases load D into |
1617 | scratch reg. */ | |
1618 | if (GET_CODE (operand1) == MEM | |
690d4228 | 1619 | && !memory_address_p (Pmode, XEXP (operand1, 0))) |
09ece7b5 | 1620 | { |
dd8c13e3 JL |
1621 | /* We are reloading the address into the scratch register, so we |
1622 | want to make sure the scratch register is a full register. */ | |
6619e96c | 1623 | scratch_reg = force_mode (word_mode, scratch_reg); |
dd8c13e3 | 1624 | |
6619e96c | 1625 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); |
ad2c71b7 JL |
1626 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, |
1627 | 0)), | |
690d4228 | 1628 | Pmode, |
ad2c71b7 JL |
1629 | XEXP (XEXP (operand1, 0), |
1630 | 0), | |
1631 | scratch_reg)); | |
dd8c13e3 JL |
1632 | |
1633 | /* Now we are going to load the scratch register from memory, | |
1634 | we want to load it in the same width as the original MEM, | |
1635 | which must be the same as the width of the ultimate destination, | |
1636 | OPERAND0. */ | |
6619e96c AM |
1637 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1638 | ||
7c95bbfb RH |
1639 | emit_move_insn (scratch_reg, |
1640 | replace_equiv_address (operand1, scratch_reg)); | |
09ece7b5 JL |
1641 | } |
1642 | else | |
dd8c13e3 JL |
1643 | { |
1644 | /* We want to load the scratch register using the same mode as | |
1645 | the ultimate destination. */ | |
6619e96c AM |
1646 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1647 | ||
dd8c13e3 JL |
1648 | emit_move_insn (scratch_reg, operand1); |
1649 | } | |
1650 | ||
1651 | /* And emit the insn to set the ultimate destination. We know that | |
1652 | the scratch register has the same mode as the destination at this | |
1653 | point. */ | |
4d3cea21 JL |
1654 | emit_move_insn (operand0, scratch_reg); |
1655 | return 1; | |
1656 | } | |
d8f95bed | 1657 | /* Handle the most common case: storing into a register. */ |
d2a94ec0 | 1658 | else if (register_operand (operand0, mode)) |
188538df TG |
1659 | { |
1660 | if (register_operand (operand1, mode) | |
b8e42321 JDA |
1661 | || (GET_CODE (operand1) == CONST_INT |
1662 | && cint_ok_for_move (INTVAL (operand1))) | |
f048ca47 | 1663 | || (operand1 == CONST0_RTX (mode)) |
188538df | 1664 | || (GET_CODE (operand1) == HIGH |
80225b66 | 1665 | && !symbolic_operand (XEXP (operand1, 0), VOIDmode)) |
188538df TG |
1666 | /* Only `general_operands' can come here, so MEM is ok. */ |
1667 | || GET_CODE (operand1) == MEM) | |
1668 | { | |
d8f95bed JDA |
1669 | /* Various sets are created during RTL generation which don't |
1670 | have the REG_POINTER flag correctly set. After the CSE pass, | |
1671 | instruction recognition can fail if we don't consistently | |
1672 | set this flag when performing register copies. This should | |
1673 | also improve the opportunities for creating insns that use | |
1674 | unscaled indexing. */ | |
1675 | if (REG_P (operand0) && REG_P (operand1)) | |
1676 | { | |
1677 | if (REG_POINTER (operand1) | |
1678 | && !REG_POINTER (operand0) | |
1679 | && !HARD_REGISTER_P (operand0)) | |
1680 | copy_reg_pointer (operand0, operand1); | |
1681 | else if (REG_POINTER (operand0) | |
1682 | && !REG_POINTER (operand1) | |
1683 | && !HARD_REGISTER_P (operand1)) | |
1684 | copy_reg_pointer (operand1, operand0); | |
1685 | } | |
1686 | ||
1687 | /* When MEMs are broken out, the REG_POINTER flag doesn't | |
1688 | get set. In some cases, we can set the REG_POINTER flag | |
1689 | from the declaration for the MEM. */ | |
1690 | if (REG_P (operand0) | |
1691 | && GET_CODE (operand1) == MEM | |
1692 | && !REG_POINTER (operand0)) | |
1693 | { | |
1694 | tree decl = MEM_EXPR (operand1); | |
1695 | ||
1696 | /* Set the register pointer flag and register alignment | |
1697 | if the declaration for this memory reference is a | |
1698 | pointer type. Fortran indirect argument references | |
1699 | are ignored. */ | |
1700 | if (decl | |
1701 | && !(flag_argument_noalias > 1 | |
1702 | && TREE_CODE (decl) == INDIRECT_REF | |
1703 | && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL)) | |
1704 | { | |
1705 | tree type; | |
1706 | ||
1707 | /* If this is a COMPONENT_REF, use the FIELD_DECL from | |
1708 | tree operand 1. */ | |
1709 | if (TREE_CODE (decl) == COMPONENT_REF) | |
1710 | decl = TREE_OPERAND (decl, 1); | |
1711 | ||
1712 | type = TREE_TYPE (decl); | |
dd25a747 | 1713 | type = strip_array_types (type); |
d8f95bed JDA |
1714 | |
1715 | if (POINTER_TYPE_P (type)) | |
1716 | { | |
1717 | int align; | |
1718 | ||
1719 | type = TREE_TYPE (type); | |
1720 | /* Using TYPE_ALIGN_OK is rather conservative as | |
1721 | only the ada frontend actually sets it. */ | |
1722 | align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type) | |
1723 | : BITS_PER_UNIT); | |
1724 | mark_reg_pointer (operand0, align); | |
1725 | } | |
1726 | } | |
1727 | } | |
1728 | ||
ad2c71b7 | 1729 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
188538df TG |
1730 | return 1; |
1731 | } | |
1732 | } | |
1733 | else if (GET_CODE (operand0) == MEM) | |
1734 | { | |
d66dec28 JL |
1735 | if (mode == DFmode && operand1 == CONST0_RTX (mode) |
1736 | && !(reload_in_progress || reload_completed)) | |
1737 | { | |
1738 | rtx temp = gen_reg_rtx (DFmode); | |
1739 | ||
ad2c71b7 JL |
1740 | emit_insn (gen_rtx_SET (VOIDmode, temp, operand1)); |
1741 | emit_insn (gen_rtx_SET (VOIDmode, operand0, temp)); | |
d66dec28 JL |
1742 | return 1; |
1743 | } | |
f048ca47 | 1744 | if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode)) |
188538df TG |
1745 | { |
1746 | /* Run this case quickly. */ | |
ad2c71b7 | 1747 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
188538df TG |
1748 | return 1; |
1749 | } | |
1bc695cd | 1750 | if (! (reload_in_progress || reload_completed)) |
188538df TG |
1751 | { |
1752 | operands[0] = validize_mem (operand0); | |
1753 | operands[1] = operand1 = force_reg (mode, operand1); | |
1754 | } | |
1755 | } | |
1756 | ||
44201dba JL |
1757 | /* Simplify the source if we need to. |
1758 | Note we do have to handle function labels here, even though we do | |
1759 | not consider them legitimate constants. Loop optimizations can | |
06387d7c | 1760 | call the emit_move_xxx with one as a source. */ |
f1c7ce82 | 1761 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) |
44201dba | 1762 | || function_label_operand (operand1, mode) |
43940f6b | 1763 | || (GET_CODE (operand1) == HIGH |
ba365a19 | 1764 | && symbolic_operand (XEXP (operand1, 0), mode))) |
188538df | 1765 | { |
43940f6b JL |
1766 | int ishighonly = 0; |
1767 | ||
1768 | if (GET_CODE (operand1) == HIGH) | |
1769 | { | |
1770 | ishighonly = 1; | |
1771 | operand1 = XEXP (operand1, 0); | |
1772 | } | |
188538df TG |
1773 | if (symbolic_operand (operand1, mode)) |
1774 | { | |
5eceed92 | 1775 | /* Argh. The assembler and linker can't handle arithmetic |
b0fabad3 | 1776 | involving plabels. |
5eceed92 | 1777 | |
b0fabad3 JL |
1778 | So we force the plabel into memory, load operand0 from |
1779 | the memory location, then add in the constant part. */ | |
44201dba JL |
1780 | if ((GET_CODE (operand1) == CONST |
1781 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1782 | && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode)) | |
1783 | || function_label_operand (operand1, mode)) | |
5eceed92 | 1784 | { |
8e64b41a | 1785 | rtx temp, const_part; |
b0fabad3 JL |
1786 | |
1787 | /* Figure out what (if any) scratch register to use. */ | |
1788 | if (reload_in_progress || reload_completed) | |
1b8ad134 JL |
1789 | { |
1790 | scratch_reg = scratch_reg ? scratch_reg : operand0; | |
1791 | /* SCRATCH_REG will hold an address and maybe the actual | |
1792 | data. We want it in WORD_MODE regardless of what mode it | |
1793 | was originally given to us. */ | |
6619e96c | 1794 | scratch_reg = force_mode (word_mode, scratch_reg); |
1b8ad134 | 1795 | } |
b0fabad3 JL |
1796 | else if (flag_pic) |
1797 | scratch_reg = gen_reg_rtx (Pmode); | |
1798 | ||
44201dba JL |
1799 | if (GET_CODE (operand1) == CONST) |
1800 | { | |
1801 | /* Save away the constant part of the expression. */ | |
1802 | const_part = XEXP (XEXP (operand1, 0), 1); | |
144d51f9 | 1803 | gcc_assert (GET_CODE (const_part) == CONST_INT); |
44201dba JL |
1804 | |
1805 | /* Force the function label into memory. */ | |
1806 | temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0)); | |
1807 | } | |
1808 | else | |
1809 | { | |
1810 | /* No constant part. */ | |
1811 | const_part = NULL_RTX; | |
5eceed92 | 1812 | |
44201dba JL |
1813 | /* Force the function label into memory. */ |
1814 | temp = force_const_mem (mode, operand1); | |
1815 | } | |
6619e96c | 1816 | |
b0fabad3 JL |
1817 | |
1818 | /* Get the address of the memory location. PIC-ify it if | |
1819 | necessary. */ | |
1820 | temp = XEXP (temp, 0); | |
1821 | if (flag_pic) | |
1822 | temp = legitimize_pic_address (temp, mode, scratch_reg); | |
1823 | ||
1824 | /* Put the address of the memory location into our destination | |
1825 | register. */ | |
1826 | operands[1] = temp; | |
1827 | emit_move_sequence (operands, mode, scratch_reg); | |
1828 | ||
1829 | /* Now load from the memory location into our destination | |
1830 | register. */ | |
ad2c71b7 | 1831 | operands[1] = gen_rtx_MEM (Pmode, operands[0]); |
b0fabad3 JL |
1832 | emit_move_sequence (operands, mode, scratch_reg); |
1833 | ||
1834 | /* And add back in the constant part. */ | |
44201dba JL |
1835 | if (const_part != NULL_RTX) |
1836 | expand_inc (operand0, const_part); | |
b0fabad3 JL |
1837 | |
1838 | return 1; | |
5eceed92 JL |
1839 | } |
1840 | ||
188538df TG |
1841 | if (flag_pic) |
1842 | { | |
1bc695cd JL |
1843 | rtx temp; |
1844 | ||
1845 | if (reload_in_progress || reload_completed) | |
1b8ad134 JL |
1846 | { |
1847 | temp = scratch_reg ? scratch_reg : operand0; | |
1848 | /* TEMP will hold an address and maybe the actual | |
1849 | data. We want it in WORD_MODE regardless of what mode it | |
1850 | was originally given to us. */ | |
6619e96c | 1851 | temp = force_mode (word_mode, temp); |
1b8ad134 | 1852 | } |
1bc695cd JL |
1853 | else |
1854 | temp = gen_reg_rtx (Pmode); | |
23f6f34f | 1855 | |
b0fabad3 JL |
1856 | /* (const (plus (symbol) (const_int))) must be forced to |
1857 | memory during/after reload if the const_int will not fit | |
1858 | in 14 bits. */ | |
1859 | if (GET_CODE (operand1) == CONST | |
bc4a9f17 JL |
1860 | && GET_CODE (XEXP (operand1, 0)) == PLUS |
1861 | && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT | |
1862 | && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)) | |
1863 | && (reload_completed || reload_in_progress) | |
1864 | && flag_pic) | |
1865 | { | |
7c95bbfb | 1866 | rtx const_mem = force_const_mem (mode, operand1); |
1c9ef36d | 1867 | operands[1] = legitimize_pic_address (XEXP (const_mem, 0), |
bc4a9f17 | 1868 | mode, temp); |
7c95bbfb | 1869 | operands[1] = replace_equiv_address (const_mem, operands[1]); |
bc4a9f17 JL |
1870 | emit_move_sequence (operands, mode, temp); |
1871 | } | |
5eceed92 JL |
1872 | else |
1873 | { | |
1874 | operands[1] = legitimize_pic_address (operand1, mode, temp); | |
d8f95bed JDA |
1875 | if (REG_P (operand0) && REG_P (operands[1])) |
1876 | copy_reg_pointer (operand0, operands[1]); | |
ad2c71b7 | 1877 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1])); |
5eceed92 | 1878 | } |
188538df | 1879 | } |
6bb36601 JL |
1880 | /* On the HPPA, references to data space are supposed to use dp, |
1881 | register 27, but showing it in the RTL inhibits various cse | |
1882 | and loop optimizations. */ | |
23f6f34f | 1883 | else |
188538df | 1884 | { |
5eceed92 | 1885 | rtx temp, set; |
43940f6b | 1886 | |
23f6f34f | 1887 | if (reload_in_progress || reload_completed) |
1b8ad134 JL |
1888 | { |
1889 | temp = scratch_reg ? scratch_reg : operand0; | |
1890 | /* TEMP will hold an address and maybe the actual | |
1891 | data. We want it in WORD_MODE regardless of what mode it | |
1892 | was originally given to us. */ | |
6619e96c | 1893 | temp = force_mode (word_mode, temp); |
1b8ad134 | 1894 | } |
43940f6b JL |
1895 | else |
1896 | temp = gen_reg_rtx (mode); | |
1897 | ||
68944452 | 1898 | /* Loading a SYMBOL_REF into a register makes that register |
6619e96c | 1899 | safe to be used as the base in an indexed address. |
68944452 JL |
1900 | |
1901 | Don't mark hard registers though. That loses. */ | |
c34d858f RK |
1902 | if (GET_CODE (operand0) == REG |
1903 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
d8f95bed | 1904 | mark_reg_pointer (operand0, BITS_PER_UNIT); |
68944452 | 1905 | if (REGNO (temp) >= FIRST_PSEUDO_REGISTER) |
d8f95bed JDA |
1906 | mark_reg_pointer (temp, BITS_PER_UNIT); |
1907 | ||
43940f6b | 1908 | if (ishighonly) |
ad2c71b7 | 1909 | set = gen_rtx_SET (mode, operand0, temp); |
43940f6b | 1910 | else |
c5c76735 JL |
1911 | set = gen_rtx_SET (VOIDmode, |
1912 | operand0, | |
ad2c71b7 | 1913 | gen_rtx_LO_SUM (mode, temp, operand1)); |
23f6f34f | 1914 | |
ad2c71b7 JL |
1915 | emit_insn (gen_rtx_SET (VOIDmode, |
1916 | temp, | |
1917 | gen_rtx_HIGH (mode, operand1))); | |
b0ce651a | 1918 | emit_insn (set); |
326bc2de | 1919 | |
188538df | 1920 | } |
43940f6b | 1921 | return 1; |
188538df | 1922 | } |
51076f96 RC |
1923 | else if (pa_tls_referenced_p (operand1)) |
1924 | { | |
1925 | rtx tmp = operand1; | |
1926 | rtx addend = NULL; | |
1927 | ||
1928 | if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS) | |
1929 | { | |
1930 | addend = XEXP (XEXP (tmp, 0), 1); | |
1931 | tmp = XEXP (XEXP (tmp, 0), 0); | |
1932 | } | |
1933 | ||
1934 | gcc_assert (GET_CODE (tmp) == SYMBOL_REF); | |
1935 | tmp = legitimize_tls_address (tmp); | |
1936 | if (addend) | |
1937 | { | |
1938 | tmp = gen_rtx_PLUS (mode, tmp, addend); | |
1939 | tmp = force_operand (tmp, operands[0]); | |
1940 | } | |
1941 | operands[1] = tmp; | |
1942 | } | |
a1747d2c | 1943 | else if (GET_CODE (operand1) != CONST_INT |
a4295210 | 1944 | || !cint_ok_for_move (INTVAL (operand1))) |
188538df | 1945 | { |
a4295210 JDA |
1946 | rtx insn, temp; |
1947 | rtx op1 = operand1; | |
4cce9dd8 | 1948 | HOST_WIDE_INT value = 0; |
a4295210 JDA |
1949 | HOST_WIDE_INT insv = 0; |
1950 | int insert = 0; | |
1951 | ||
4cce9dd8 RS |
1952 | if (GET_CODE (operand1) == CONST_INT) |
1953 | value = INTVAL (operand1); | |
1954 | ||
a4295210 JDA |
1955 | if (TARGET_64BIT |
1956 | && GET_CODE (operand1) == CONST_INT | |
e0c556d3 | 1957 | && HOST_BITS_PER_WIDE_INT > 32 |
520babc7 JL |
1958 | && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32) |
1959 | { | |
e0c556d3 | 1960 | HOST_WIDE_INT nval; |
520babc7 | 1961 | |
b8e42321 JDA |
1962 | /* Extract the low order 32 bits of the value and sign extend. |
1963 | If the new value is the same as the original value, we can | |
1964 | can use the original value as-is. If the new value is | |
1965 | different, we use it and insert the most-significant 32-bits | |
1966 | of the original value into the final result. */ | |
a4295210 | 1967 | nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1)) |
e0c556d3 | 1968 | ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31); |
a4295210 | 1969 | if (value != nval) |
520babc7 | 1970 | { |
b8e42321 | 1971 | #if HOST_BITS_PER_WIDE_INT > 32 |
a4295210 | 1972 | insv = value >= 0 ? value >> 32 : ~(~value >> 32); |
b8e42321 | 1973 | #endif |
a4295210 JDA |
1974 | insert = 1; |
1975 | value = nval; | |
520babc7 JL |
1976 | operand1 = GEN_INT (nval); |
1977 | } | |
1978 | } | |
1bc695cd JL |
1979 | |
1980 | if (reload_in_progress || reload_completed) | |
a4295210 | 1981 | temp = scratch_reg ? scratch_reg : operand0; |
1bc695cd JL |
1982 | else |
1983 | temp = gen_reg_rtx (mode); | |
1984 | ||
47abc309 JDA |
1985 | /* We don't directly split DImode constants on 32-bit targets |
1986 | because PLUS uses an 11-bit immediate and the insn sequence | |
1987 | generated is not as efficient as the one using HIGH/LO_SUM. */ | |
1988 | if (GET_CODE (operand1) == CONST_INT | |
0eab7815 | 1989 | && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD |
a4295210 JDA |
1990 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
1991 | && !insert) | |
b8e42321 | 1992 | { |
47abc309 | 1993 | /* Directly break constant into high and low parts. This |
b8e42321 JDA |
1994 | provides better optimization opportunities because various |
1995 | passes recognize constants split with PLUS but not LO_SUM. | |
1996 | We use a 14-bit signed low part except when the addition | |
1997 | of 0x4000 to the high part might change the sign of the | |
1998 | high part. */ | |
b8e42321 JDA |
1999 | HOST_WIDE_INT low = value & 0x3fff; |
2000 | HOST_WIDE_INT high = value & ~ 0x3fff; | |
2001 | ||
2002 | if (low >= 0x2000) | |
2003 | { | |
2004 | if (high == 0x7fffc000 || (mode == HImode && high == 0x4000)) | |
2005 | high += 0x2000; | |
2006 | else | |
2007 | high += 0x4000; | |
2008 | } | |
2009 | ||
2010 | low = value - high; | |
520babc7 | 2011 | |
b8e42321 JDA |
2012 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high))); |
2013 | operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low)); | |
2014 | } | |
2015 | else | |
520babc7 | 2016 | { |
b8e42321 JDA |
2017 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
2018 | gen_rtx_HIGH (mode, operand1))); | |
2019 | operands[1] = gen_rtx_LO_SUM (mode, temp, operand1); | |
520babc7 | 2020 | } |
6619e96c | 2021 | |
a4295210 JDA |
2022 | insn = emit_move_insn (operands[0], operands[1]); |
2023 | ||
2024 | /* Now insert the most significant 32 bits of the value | |
2025 | into the register. When we don't have a second register | |
2026 | available, it could take up to nine instructions to load | |
2027 | a 64-bit integer constant. Prior to reload, we force | |
2028 | constants that would take more than three instructions | |
2029 | to load to the constant pool. During and after reload, | |
2030 | we have to handle all possible values. */ | |
2031 | if (insert) | |
2032 | { | |
2033 | /* Use a HIGH/LO_SUM/INSV sequence if we have a second | |
2034 | register and the value to be inserted is outside the | |
2035 | range that can be loaded with three depdi instructions. */ | |
2036 | if (temp != operand0 && (insv >= 16384 || insv < -16384)) | |
2037 | { | |
2038 | operand1 = GEN_INT (insv); | |
2039 | ||
2040 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
2041 | gen_rtx_HIGH (mode, operand1))); | |
2042 | emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1)); | |
2043 | emit_insn (gen_insv (operand0, GEN_INT (32), | |
2044 | const0_rtx, temp)); | |
2045 | } | |
2046 | else | |
2047 | { | |
2048 | int len = 5, pos = 27; | |
2049 | ||
2050 | /* Insert the bits using the depdi instruction. */ | |
2051 | while (pos >= 0) | |
2052 | { | |
2053 | HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16; | |
2054 | HOST_WIDE_INT sign = v5 < 0; | |
2055 | ||
2056 | /* Left extend the insertion. */ | |
2057 | insv = (insv >= 0 ? insv >> len : ~(~insv >> len)); | |
2058 | while (pos > 0 && (insv & 1) == sign) | |
2059 | { | |
2060 | insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1)); | |
2061 | len += 1; | |
2062 | pos -= 1; | |
2063 | } | |
2064 | ||
2065 | emit_insn (gen_insv (operand0, GEN_INT (len), | |
2066 | GEN_INT (pos), GEN_INT (v5))); | |
2067 | ||
2068 | len = pos > 0 && pos < 5 ? pos : 5; | |
2069 | pos -= len; | |
2070 | } | |
2071 | } | |
2072 | } | |
b8e42321 | 2073 | |
bd94cb6e | 2074 | set_unique_reg_note (insn, REG_EQUAL, op1); |
b8e42321 | 2075 | |
520babc7 | 2076 | return 1; |
188538df TG |
2077 | } |
2078 | } | |
2079 | /* Now have insn-emit do whatever it normally does. */ | |
2080 | return 0; | |
2081 | } | |
2082 | ||
c77c286a | 2083 | /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning |
c4bb6b38 | 2084 | it will need a link/runtime reloc). */ |
c77c286a JL |
2085 | |
2086 | int | |
b7849684 | 2087 | reloc_needed (tree exp) |
c77c286a JL |
2088 | { |
2089 | int reloc = 0; | |
2090 | ||
2091 | switch (TREE_CODE (exp)) | |
2092 | { | |
2093 | case ADDR_EXPR: | |
2094 | return 1; | |
2095 | ||
5be014d5 | 2096 | case POINTER_PLUS_EXPR: |
c77c286a JL |
2097 | case PLUS_EXPR: |
2098 | case MINUS_EXPR: | |
2099 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
2100 | reloc |= reloc_needed (TREE_OPERAND (exp, 1)); | |
2101 | break; | |
2102 | ||
1043771b | 2103 | CASE_CONVERT: |
c77c286a JL |
2104 | case NON_LVALUE_EXPR: |
2105 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
2106 | break; | |
2107 | ||
2108 | case CONSTRUCTOR: | |
2109 | { | |
28f155be GB |
2110 | tree value; |
2111 | unsigned HOST_WIDE_INT ix; | |
2112 | ||
2113 | FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value) | |
2114 | if (value) | |
2115 | reloc |= reloc_needed (value); | |
c77c286a JL |
2116 | } |
2117 | break; | |
2118 | ||
2119 | case ERROR_MARK: | |
2120 | break; | |
51723711 KG |
2121 | |
2122 | default: | |
2123 | break; | |
c77c286a JL |
2124 | } |
2125 | return reloc; | |
2126 | } | |
2127 | ||
fb49053f RH |
2128 | /* Does operand (which is a symbolic_operand) live in text space? |
2129 | If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info, | |
2130 | will be true. */ | |
188538df TG |
2131 | |
2132 | int | |
b7849684 | 2133 | read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED) |
188538df TG |
2134 | { |
2135 | if (GET_CODE (operand) == CONST) | |
2136 | operand = XEXP (XEXP (operand, 0), 0); | |
6bb36601 JL |
2137 | if (flag_pic) |
2138 | { | |
2139 | if (GET_CODE (operand) == SYMBOL_REF) | |
2140 | return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand); | |
2141 | } | |
2142 | else | |
2143 | { | |
2144 | if (GET_CODE (operand) == SYMBOL_REF) | |
2145 | return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand); | |
2146 | } | |
188538df TG |
2147 | return 1; |
2148 | } | |
23f6f34f | 2149 | |
188538df TG |
2150 | \f |
2151 | /* Return the best assembler insn template | |
71cc389b | 2152 | for moving operands[1] into operands[0] as a fullword. */ |
519104fe | 2153 | const char * |
b7849684 | 2154 | singlemove_string (rtx *operands) |
188538df | 2155 | { |
0c235d7e TG |
2156 | HOST_WIDE_INT intval; |
2157 | ||
188538df TG |
2158 | if (GET_CODE (operands[0]) == MEM) |
2159 | return "stw %r1,%0"; | |
0c235d7e | 2160 | if (GET_CODE (operands[1]) == MEM) |
188538df | 2161 | return "ldw %1,%0"; |
0c235d7e | 2162 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
e5c2baa1 | 2163 | { |
0c235d7e TG |
2164 | long i; |
2165 | REAL_VALUE_TYPE d; | |
e5c2baa1 | 2166 | |
144d51f9 | 2167 | gcc_assert (GET_MODE (operands[1]) == SFmode); |
e5c2baa1 | 2168 | |
0c235d7e TG |
2169 | /* Translate the CONST_DOUBLE to a CONST_INT with the same target |
2170 | bit pattern. */ | |
2171 | REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]); | |
2172 | REAL_VALUE_TO_TARGET_SINGLE (d, i); | |
e5c2baa1 | 2173 | |
0c235d7e TG |
2174 | operands[1] = GEN_INT (i); |
2175 | /* Fall through to CONST_INT case. */ | |
2176 | } | |
2177 | if (GET_CODE (operands[1]) == CONST_INT) | |
e5c2baa1 | 2178 | { |
0c235d7e TG |
2179 | intval = INTVAL (operands[1]); |
2180 | ||
2181 | if (VAL_14_BITS_P (intval)) | |
2182 | return "ldi %1,%0"; | |
2183 | else if ((intval & 0x7ff) == 0) | |
2184 | return "ldil L'%1,%0"; | |
2185 | else if (zdepi_cint_p (intval)) | |
f38b27c7 | 2186 | return "{zdepi %Z1,%0|depwi,z %Z1,%0}"; |
e5c2baa1 RS |
2187 | else |
2188 | return "ldil L'%1,%0\n\tldo R'%1(%0),%0"; | |
2189 | } | |
188538df TG |
2190 | return "copy %1,%0"; |
2191 | } | |
2192 | \f | |
2193 | ||
f133af4c TG |
2194 | /* Compute position (in OP[1]) and width (in OP[2]) |
2195 | useful for copying IMM to a register using the zdepi | |
2196 | instructions. Store the immediate value to insert in OP[0]. */ | |
519104fe | 2197 | static void |
b7849684 | 2198 | compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
c819adf2 | 2199 | { |
0e7f4c19 | 2200 | int lsb, len; |
c819adf2 | 2201 | |
0e7f4c19 TG |
2202 | /* Find the least significant set bit in IMM. */ |
2203 | for (lsb = 0; lsb < 32; lsb++) | |
c819adf2 | 2204 | { |
0e7f4c19 | 2205 | if ((imm & 1) != 0) |
c819adf2 | 2206 | break; |
0e7f4c19 | 2207 | imm >>= 1; |
c819adf2 TG |
2208 | } |
2209 | ||
0e7f4c19 TG |
2210 | /* Choose variants based on *sign* of the 5-bit field. */ |
2211 | if ((imm & 0x10) == 0) | |
2212 | len = (lsb <= 28) ? 4 : 32 - lsb; | |
c819adf2 TG |
2213 | else |
2214 | { | |
0e7f4c19 TG |
2215 | /* Find the width of the bitstring in IMM. */ |
2216 | for (len = 5; len < 32; len++) | |
c819adf2 | 2217 | { |
0e7f4c19 | 2218 | if ((imm & (1 << len)) == 0) |
c819adf2 | 2219 | break; |
c819adf2 TG |
2220 | } |
2221 | ||
0e7f4c19 TG |
2222 | /* Sign extend IMM as a 5-bit value. */ |
2223 | imm = (imm & 0xf) - 0x10; | |
c819adf2 TG |
2224 | } |
2225 | ||
a1747d2c TG |
2226 | op[0] = imm; |
2227 | op[1] = 31 - lsb; | |
2228 | op[2] = len; | |
c819adf2 TG |
2229 | } |
2230 | ||
520babc7 JL |
2231 | /* Compute position (in OP[1]) and width (in OP[2]) |
2232 | useful for copying IMM to a register using the depdi,z | |
2233 | instructions. Store the immediate value to insert in OP[0]. */ | |
2234 | void | |
b7849684 | 2235 | compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
520babc7 JL |
2236 | { |
2237 | HOST_WIDE_INT lsb, len; | |
2238 | ||
2239 | /* Find the least significant set bit in IMM. */ | |
2240 | for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++) | |
2241 | { | |
2242 | if ((imm & 1) != 0) | |
2243 | break; | |
2244 | imm >>= 1; | |
2245 | } | |
2246 | ||
2247 | /* Choose variants based on *sign* of the 5-bit field. */ | |
2248 | if ((imm & 0x10) == 0) | |
2249 | len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4) | |
2250 | ? 4 : HOST_BITS_PER_WIDE_INT - lsb); | |
2251 | else | |
2252 | { | |
2253 | /* Find the width of the bitstring in IMM. */ | |
2254 | for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++) | |
2255 | { | |
831c1763 | 2256 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
520babc7 JL |
2257 | break; |
2258 | } | |
2259 | ||
2260 | /* Sign extend IMM as a 5-bit value. */ | |
2261 | imm = (imm & 0xf) - 0x10; | |
2262 | } | |
2263 | ||
2264 | op[0] = imm; | |
2265 | op[1] = 63 - lsb; | |
2266 | op[2] = len; | |
2267 | } | |
2268 | ||
188538df TG |
2269 | /* Output assembler code to perform a doubleword move insn |
2270 | with operands OPERANDS. */ | |
2271 | ||
519104fe | 2272 | const char * |
b7849684 | 2273 | output_move_double (rtx *operands) |
188538df TG |
2274 | { |
2275 | enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1; | |
2276 | rtx latehalf[2]; | |
2277 | rtx addreg0 = 0, addreg1 = 0; | |
2278 | ||
2279 | /* First classify both operands. */ | |
2280 | ||
2281 | if (REG_P (operands[0])) | |
2282 | optype0 = REGOP; | |
2283 | else if (offsettable_memref_p (operands[0])) | |
2284 | optype0 = OFFSOP; | |
2285 | else if (GET_CODE (operands[0]) == MEM) | |
2286 | optype0 = MEMOP; | |
2287 | else | |
2288 | optype0 = RNDOP; | |
2289 | ||
2290 | if (REG_P (operands[1])) | |
2291 | optype1 = REGOP; | |
2292 | else if (CONSTANT_P (operands[1])) | |
2293 | optype1 = CNSTOP; | |
2294 | else if (offsettable_memref_p (operands[1])) | |
2295 | optype1 = OFFSOP; | |
2296 | else if (GET_CODE (operands[1]) == MEM) | |
2297 | optype1 = MEMOP; | |
2298 | else | |
2299 | optype1 = RNDOP; | |
2300 | ||
2301 | /* Check for the cases that the operand constraints are not | |
144d51f9 NS |
2302 | supposed to allow to happen. */ |
2303 | gcc_assert (optype0 == REGOP || optype1 == REGOP); | |
188538df | 2304 | |
5401050b JDA |
2305 | /* Handle copies between general and floating registers. */ |
2306 | ||
2307 | if (optype0 == REGOP && optype1 == REGOP | |
2308 | && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])) | |
2309 | { | |
2310 | if (FP_REG_P (operands[0])) | |
2311 | { | |
2312 | output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands); | |
2313 | output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands); | |
2314 | return "{fldds|fldd} -16(%%sp),%0"; | |
2315 | } | |
2316 | else | |
2317 | { | |
2318 | output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands); | |
2319 | output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands); | |
2320 | return "{ldws|ldw} -12(%%sp),%R0"; | |
2321 | } | |
2322 | } | |
2323 | ||
188538df TG |
2324 | /* Handle auto decrementing and incrementing loads and stores |
2325 | specifically, since the structure of the function doesn't work | |
2326 | for them without major modification. Do it better when we learn | |
2327 | this port about the general inc/dec addressing of PA. | |
2328 | (This was written by tege. Chide him if it doesn't work.) */ | |
2329 | ||
2330 | if (optype0 == MEMOP) | |
2331 | { | |
e37ce5f6 JL |
2332 | /* We have to output the address syntax ourselves, since print_operand |
2333 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2334 | ||
188538df | 2335 | rtx addr = XEXP (operands[0], 0); |
e37ce5f6 | 2336 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) |
188538df | 2337 | { |
ad2c71b7 | 2338 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
e37ce5f6 JL |
2339 | |
2340 | operands[0] = XEXP (addr, 0); | |
144d51f9 NS |
2341 | gcc_assert (GET_CODE (operands[1]) == REG |
2342 | && GET_CODE (operands[0]) == REG); | |
e37ce5f6 | 2343 | |
144d51f9 NS |
2344 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); |
2345 | ||
2346 | /* No overlap between high target register and address | |
2347 | register. (We do this in a non-obvious way to | |
2348 | save a register file writeback) */ | |
2349 | if (GET_CODE (addr) == POST_INC) | |
2350 | return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)"; | |
2351 | return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)"; | |
9682683d | 2352 | } |
e37ce5f6 | 2353 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) |
9682683d | 2354 | { |
ad2c71b7 | 2355 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
e37ce5f6 JL |
2356 | |
2357 | operands[0] = XEXP (addr, 0); | |
144d51f9 NS |
2358 | gcc_assert (GET_CODE (operands[1]) == REG |
2359 | && GET_CODE (operands[0]) == REG); | |
2360 | ||
2361 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); | |
2362 | /* No overlap between high target register and address | |
2363 | register. (We do this in a non-obvious way to save a | |
2364 | register file writeback) */ | |
2365 | if (GET_CODE (addr) == PRE_INC) | |
2366 | return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)"; | |
2367 | return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)"; | |
188538df TG |
2368 | } |
2369 | } | |
2370 | if (optype1 == MEMOP) | |
2371 | { | |
2372 | /* We have to output the address syntax ourselves, since print_operand | |
2373 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2374 | ||
2375 | rtx addr = XEXP (operands[1], 0); | |
2376 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) | |
2377 | { | |
ad2c71b7 | 2378 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
188538df TG |
2379 | |
2380 | operands[1] = XEXP (addr, 0); | |
144d51f9 NS |
2381 | gcc_assert (GET_CODE (operands[0]) == REG |
2382 | && GET_CODE (operands[1]) == REG); | |
188538df TG |
2383 | |
2384 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2385 | { | |
2386 | /* No overlap between high target register and address | |
dd605bb4 | 2387 | register. (We do this in a non-obvious way to |
188538df TG |
2388 | save a register file writeback) */ |
2389 | if (GET_CODE (addr) == POST_INC) | |
f38b27c7 | 2390 | return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0"; |
6126a380 | 2391 | return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0"; |
188538df TG |
2392 | } |
2393 | else | |
2394 | { | |
2395 | /* This is an undefined situation. We should load into the | |
2396 | address register *and* update that register. Probably | |
2397 | we don't need to handle this at all. */ | |
2398 | if (GET_CODE (addr) == POST_INC) | |
f38b27c7 JL |
2399 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0"; |
2400 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0"; | |
188538df TG |
2401 | } |
2402 | } | |
2403 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) | |
2404 | { | |
ad2c71b7 | 2405 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
188538df TG |
2406 | |
2407 | operands[1] = XEXP (addr, 0); | |
144d51f9 NS |
2408 | gcc_assert (GET_CODE (operands[0]) == REG |
2409 | && GET_CODE (operands[1]) == REG); | |
188538df TG |
2410 | |
2411 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2412 | { | |
2413 | /* No overlap between high target register and address | |
dd605bb4 | 2414 | register. (We do this in a non-obvious way to |
188538df TG |
2415 | save a register file writeback) */ |
2416 | if (GET_CODE (addr) == PRE_INC) | |
f38b27c7 JL |
2417 | return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0"; |
2418 | return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0"; | |
188538df TG |
2419 | } |
2420 | else | |
2421 | { | |
2422 | /* This is an undefined situation. We should load into the | |
2423 | address register *and* update that register. Probably | |
2424 | we don't need to handle this at all. */ | |
2425 | if (GET_CODE (addr) == PRE_INC) | |
f38b27c7 JL |
2426 | return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0"; |
2427 | return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0"; | |
188538df TG |
2428 | } |
2429 | } | |
a89974a2 JL |
2430 | else if (GET_CODE (addr) == PLUS |
2431 | && GET_CODE (XEXP (addr, 0)) == MULT) | |
2432 | { | |
4c6d8726 | 2433 | rtx xoperands[4]; |
ad2c71b7 | 2434 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
a89974a2 JL |
2435 | |
2436 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2437 | { | |
a89974a2 JL |
2438 | xoperands[0] = high_reg; |
2439 | xoperands[1] = XEXP (addr, 1); | |
2440 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2441 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
f38b27c7 JL |
2442 | output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}", |
2443 | xoperands); | |
d2d28085 | 2444 | return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; |
a89974a2 JL |
2445 | } |
2446 | else | |
2447 | { | |
a89974a2 JL |
2448 | xoperands[0] = high_reg; |
2449 | xoperands[1] = XEXP (addr, 1); | |
2450 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2451 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
f38b27c7 JL |
2452 | output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}", |
2453 | xoperands); | |
d2d28085 | 2454 | return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0"; |
a89974a2 | 2455 | } |
a89974a2 | 2456 | } |
188538df TG |
2457 | } |
2458 | ||
2459 | /* If an operand is an unoffsettable memory ref, find a register | |
2460 | we can increment temporarily to make it refer to the second word. */ | |
2461 | ||
2462 | if (optype0 == MEMOP) | |
2463 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2464 | ||
2465 | if (optype1 == MEMOP) | |
2466 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2467 | ||
2468 | /* Ok, we can do one word at a time. | |
2469 | Normally we do the low-numbered word first. | |
2470 | ||
2471 | In either case, set up in LATEHALF the operands to use | |
2472 | for the high-numbered word and in some cases alter the | |
2473 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2474 | ||
2475 | if (optype0 == REGOP) | |
ad2c71b7 | 2476 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
188538df | 2477 | else if (optype0 == OFFSOP) |
b72f00af | 2478 | latehalf[0] = adjust_address (operands[0], SImode, 4); |
188538df TG |
2479 | else |
2480 | latehalf[0] = operands[0]; | |
2481 | ||
2482 | if (optype1 == REGOP) | |
ad2c71b7 | 2483 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
188538df | 2484 | else if (optype1 == OFFSOP) |
b72f00af | 2485 | latehalf[1] = adjust_address (operands[1], SImode, 4); |
188538df TG |
2486 | else if (optype1 == CNSTOP) |
2487 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2488 | else | |
2489 | latehalf[1] = operands[1]; | |
2490 | ||
2491 | /* If the first move would clobber the source of the second one, | |
2492 | do them in the other order. | |
2493 | ||
bad883f8 | 2494 | This can happen in two cases: |
188538df | 2495 | |
bad883f8 JL |
2496 | mem -> register where the first half of the destination register |
2497 | is the same register used in the memory's address. Reload | |
2498 | can create such insns. | |
188538df | 2499 | |
bad883f8 | 2500 | mem in this case will be either register indirect or register |
6619e96c | 2501 | indirect plus a valid offset. |
bad883f8 JL |
2502 | |
2503 | register -> register move where REGNO(dst) == REGNO(src + 1) | |
6619e96c | 2504 | someone (Tim/Tege?) claimed this can happen for parameter loads. |
bad883f8 JL |
2505 | |
2506 | Handle mem -> register case first. */ | |
2507 | if (optype0 == REGOP | |
2508 | && (optype1 == MEMOP || optype1 == OFFSOP) | |
2509 | && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2510 | operands[1], 0)) | |
188538df | 2511 | { |
188538df TG |
2512 | /* Do the late half first. */ |
2513 | if (addreg1) | |
498ee10c | 2514 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
188538df | 2515 | output_asm_insn (singlemove_string (latehalf), latehalf); |
bad883f8 JL |
2516 | |
2517 | /* Then clobber. */ | |
188538df | 2518 | if (addreg1) |
498ee10c | 2519 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
188538df TG |
2520 | return singlemove_string (operands); |
2521 | } | |
2522 | ||
bad883f8 | 2523 | /* Now handle register -> register case. */ |
63a1f834 TG |
2524 | if (optype0 == REGOP && optype1 == REGOP |
2525 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
2526 | { | |
2527 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2528 | return singlemove_string (operands); | |
2529 | } | |
2530 | ||
188538df TG |
2531 | /* Normal case: do the two words, low-numbered first. */ |
2532 | ||
2533 | output_asm_insn (singlemove_string (operands), operands); | |
2534 | ||
2535 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2536 | if (addreg0) | |
498ee10c | 2537 | output_asm_insn ("ldo 4(%0),%0", &addreg0); |
188538df | 2538 | if (addreg1) |
498ee10c | 2539 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
188538df TG |
2540 | |
2541 | /* Do that word. */ | |
2542 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2543 | ||
2544 | /* Undo the adds we just did. */ | |
2545 | if (addreg0) | |
498ee10c | 2546 | output_asm_insn ("ldo -4(%0),%0", &addreg0); |
188538df | 2547 | if (addreg1) |
498ee10c | 2548 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
188538df TG |
2549 | |
2550 | return ""; | |
2551 | } | |
2552 | \f | |
519104fe | 2553 | const char * |
b7849684 | 2554 | output_fp_move_double (rtx *operands) |
188538df TG |
2555 | { |
2556 | if (FP_REG_P (operands[0])) | |
2557 | { | |
23f6f34f | 2558 | if (FP_REG_P (operands[1]) |
f048ca47 | 2559 | || operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
55abf18a | 2560 | output_asm_insn ("fcpy,dbl %f1,%0", operands); |
23f6f34f | 2561 | else |
2414e0e2 | 2562 | output_asm_insn ("fldd%F1 %1,%0", operands); |
188538df TG |
2563 | } |
2564 | else if (FP_REG_P (operands[1])) | |
2565 | { | |
2414e0e2 | 2566 | output_asm_insn ("fstd%F0 %1,%0", operands); |
188538df | 2567 | } |
144d51f9 | 2568 | else |
f048ca47 | 2569 | { |
144d51f9 NS |
2570 | rtx xoperands[2]; |
2571 | ||
2572 | gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0]))); | |
2573 | ||
23f6f34f | 2574 | /* This is a pain. You have to be prepared to deal with an |
ddd5a7c1 | 2575 | arbitrary address here including pre/post increment/decrement. |
f048ca47 JL |
2576 | |
2577 | so avoid this in the MD. */ | |
144d51f9 NS |
2578 | gcc_assert (GET_CODE (operands[0]) == REG); |
2579 | ||
2580 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2581 | xoperands[0] = operands[0]; | |
2582 | output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands); | |
f048ca47 | 2583 | } |
188538df TG |
2584 | return ""; |
2585 | } | |
2586 | \f | |
2587 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2588 | ADDR can be effectively incremented by incrementing REG. */ | |
2589 | ||
2590 | static rtx | |
b7849684 | 2591 | find_addr_reg (rtx addr) |
188538df TG |
2592 | { |
2593 | while (GET_CODE (addr) == PLUS) | |
2594 | { | |
2595 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2596 | addr = XEXP (addr, 0); | |
2597 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2598 | addr = XEXP (addr, 1); | |
2599 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2600 | addr = XEXP (addr, 1); | |
2601 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2602 | addr = XEXP (addr, 0); | |
2603 | else | |
144d51f9 | 2604 | gcc_unreachable (); |
188538df | 2605 | } |
144d51f9 NS |
2606 | gcc_assert (GET_CODE (addr) == REG); |
2607 | return addr; | |
188538df TG |
2608 | } |
2609 | ||
188538df TG |
2610 | /* Emit code to perform a block move. |
2611 | ||
188538df TG |
2612 | OPERANDS[0] is the destination pointer as a REG, clobbered. |
2613 | OPERANDS[1] is the source pointer as a REG, clobbered. | |
68944452 | 2614 | OPERANDS[2] is a register for temporary storage. |
188538df | 2615 | OPERANDS[3] is a register for temporary storage. |
cdc9103c | 2616 | OPERANDS[4] is the size as a CONST_INT |
6619e96c | 2617 | OPERANDS[5] is the alignment safe to use, as a CONST_INT. |
71cc389b | 2618 | OPERANDS[6] is another temporary register. */ |
188538df | 2619 | |
519104fe | 2620 | const char * |
b7849684 | 2621 | output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) |
188538df TG |
2622 | { |
2623 | int align = INTVAL (operands[5]); | |
68944452 | 2624 | unsigned long n_bytes = INTVAL (operands[4]); |
188538df | 2625 | |
cdc9103c | 2626 | /* We can't move more than a word at a time because the PA |
188538df | 2627 | has no longer integer move insns. (Could use fp mem ops?) */ |
cdc9103c JDA |
2628 | if (align > (TARGET_64BIT ? 8 : 4)) |
2629 | align = (TARGET_64BIT ? 8 : 4); | |
188538df | 2630 | |
68944452 JL |
2631 | /* Note that we know each loop below will execute at least twice |
2632 | (else we would have open-coded the copy). */ | |
2633 | switch (align) | |
188538df | 2634 | { |
cdc9103c JDA |
2635 | case 8: |
2636 | /* Pre-adjust the loop counter. */ | |
2637 | operands[4] = GEN_INT (n_bytes - 16); | |
2638 | output_asm_insn ("ldi %4,%2", operands); | |
2639 | ||
2640 | /* Copying loop. */ | |
2641 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2642 | output_asm_insn ("ldd,ma 8(%1),%6", operands); | |
2643 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2644 | output_asm_insn ("addib,>= -16,%2,.-12", operands); | |
2645 | output_asm_insn ("std,ma %6,8(%0)", operands); | |
2646 | ||
2647 | /* Handle the residual. There could be up to 7 bytes of | |
2648 | residual to copy! */ | |
2649 | if (n_bytes % 16 != 0) | |
2650 | { | |
2651 | operands[4] = GEN_INT (n_bytes % 8); | |
2652 | if (n_bytes % 16 >= 8) | |
2653 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2654 | if (n_bytes % 8 != 0) | |
2655 | output_asm_insn ("ldd 0(%1),%6", operands); | |
2656 | if (n_bytes % 16 >= 8) | |
2657 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2658 | if (n_bytes % 8 != 0) | |
2659 | output_asm_insn ("stdby,e %6,%4(%0)", operands); | |
2660 | } | |
2661 | return ""; | |
2662 | ||
68944452 JL |
2663 | case 4: |
2664 | /* Pre-adjust the loop counter. */ | |
2665 | operands[4] = GEN_INT (n_bytes - 8); | |
2666 | output_asm_insn ("ldi %4,%2", operands); | |
2667 | ||
2668 | /* Copying loop. */ | |
f38b27c7 JL |
2669 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
2670 | output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands); | |
2671 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); | |
68944452 | 2672 | output_asm_insn ("addib,>= -8,%2,.-12", operands); |
f38b27c7 | 2673 | output_asm_insn ("{stws|stw},ma %6,4(%0)", operands); |
68944452 JL |
2674 | |
2675 | /* Handle the residual. There could be up to 7 bytes of | |
2676 | residual to copy! */ | |
2677 | if (n_bytes % 8 != 0) | |
2678 | { | |
2679 | operands[4] = GEN_INT (n_bytes % 4); | |
2680 | if (n_bytes % 8 >= 4) | |
f38b27c7 | 2681 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
68944452 | 2682 | if (n_bytes % 4 != 0) |
d2d28085 | 2683 | output_asm_insn ("ldw 0(%1),%6", operands); |
68944452 | 2684 | if (n_bytes % 8 >= 4) |
f38b27c7 | 2685 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); |
68944452 | 2686 | if (n_bytes % 4 != 0) |
f38b27c7 | 2687 | output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands); |
68944452 JL |
2688 | } |
2689 | return ""; | |
188538df | 2690 | |
68944452 JL |
2691 | case 2: |
2692 | /* Pre-adjust the loop counter. */ | |
2693 | operands[4] = GEN_INT (n_bytes - 4); | |
2694 | output_asm_insn ("ldi %4,%2", operands); | |
188538df | 2695 | |
68944452 | 2696 | /* Copying loop. */ |
f38b27c7 JL |
2697 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
2698 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands); | |
2699 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); | |
68944452 | 2700 | output_asm_insn ("addib,>= -4,%2,.-12", operands); |
f38b27c7 | 2701 | output_asm_insn ("{sths|sth},ma %6,2(%0)", operands); |
188538df | 2702 | |
68944452 JL |
2703 | /* Handle the residual. */ |
2704 | if (n_bytes % 4 != 0) | |
2705 | { | |
2706 | if (n_bytes % 4 >= 2) | |
f38b27c7 | 2707 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
68944452 | 2708 | if (n_bytes % 2 != 0) |
d2d28085 | 2709 | output_asm_insn ("ldb 0(%1),%6", operands); |
68944452 | 2710 | if (n_bytes % 4 >= 2) |
f38b27c7 | 2711 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); |
68944452 | 2712 | if (n_bytes % 2 != 0) |
d2d28085 | 2713 | output_asm_insn ("stb %6,0(%0)", operands); |
68944452 JL |
2714 | } |
2715 | return ""; | |
188538df | 2716 | |
68944452 JL |
2717 | case 1: |
2718 | /* Pre-adjust the loop counter. */ | |
2719 | operands[4] = GEN_INT (n_bytes - 2); | |
2720 | output_asm_insn ("ldi %4,%2", operands); | |
188538df | 2721 | |
68944452 | 2722 | /* Copying loop. */ |
f38b27c7 JL |
2723 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands); |
2724 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands); | |
2725 | output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands); | |
68944452 | 2726 | output_asm_insn ("addib,>= -2,%2,.-12", operands); |
f38b27c7 | 2727 | output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands); |
188538df | 2728 | |
68944452 JL |
2729 | /* Handle the residual. */ |
2730 | if (n_bytes % 2 != 0) | |
2731 | { | |
d2d28085 JL |
2732 | output_asm_insn ("ldb 0(%1),%3", operands); |
2733 | output_asm_insn ("stb %3,0(%0)", operands); | |
68944452 JL |
2734 | } |
2735 | return ""; | |
188538df | 2736 | |
68944452 | 2737 | default: |
144d51f9 | 2738 | gcc_unreachable (); |
188538df | 2739 | } |
188538df | 2740 | } |
3673e996 RS |
2741 | |
2742 | /* Count the number of insns necessary to handle this block move. | |
2743 | ||
2744 | Basic structure is the same as emit_block_move, except that we | |
2745 | count insns rather than emit them. */ | |
2746 | ||
519104fe | 2747 | static int |
70128ad9 | 2748 | compute_movmem_length (rtx insn) |
3673e996 RS |
2749 | { |
2750 | rtx pat = PATTERN (insn); | |
a36a47ad GS |
2751 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0)); |
2752 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0)); | |
68944452 | 2753 | unsigned int n_insns = 0; |
3673e996 RS |
2754 | |
2755 | /* We can't move more than four bytes at a time because the PA | |
2756 | has no longer integer move insns. (Could use fp mem ops?) */ | |
cdc9103c JDA |
2757 | if (align > (TARGET_64BIT ? 8 : 4)) |
2758 | align = (TARGET_64BIT ? 8 : 4); | |
3673e996 | 2759 | |
90304f64 | 2760 | /* The basic copying loop. */ |
68944452 | 2761 | n_insns = 6; |
3673e996 | 2762 | |
68944452 JL |
2763 | /* Residuals. */ |
2764 | if (n_bytes % (2 * align) != 0) | |
3673e996 | 2765 | { |
90304f64 JL |
2766 | if ((n_bytes % (2 * align)) >= align) |
2767 | n_insns += 2; | |
2768 | ||
2769 | if ((n_bytes % align) != 0) | |
2770 | n_insns += 2; | |
3673e996 | 2771 | } |
68944452 JL |
2772 | |
2773 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2774 | return n_insns * 4; | |
3673e996 | 2775 | } |
cdc9103c JDA |
2776 | |
2777 | /* Emit code to perform a block clear. | |
2778 | ||
2779 | OPERANDS[0] is the destination pointer as a REG, clobbered. | |
2780 | OPERANDS[1] is a register for temporary storage. | |
2781 | OPERANDS[2] is the size as a CONST_INT | |
2782 | OPERANDS[3] is the alignment safe to use, as a CONST_INT. */ | |
2783 | ||
2784 | const char * | |
2785 | output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) | |
2786 | { | |
2787 | int align = INTVAL (operands[3]); | |
2788 | unsigned long n_bytes = INTVAL (operands[2]); | |
2789 | ||
2790 | /* We can't clear more than a word at a time because the PA | |
2791 | has no longer integer move insns. */ | |
2792 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2793 | align = (TARGET_64BIT ? 8 : 4); | |
2794 | ||
2795 | /* Note that we know each loop below will execute at least twice | |
2796 | (else we would have open-coded the copy). */ | |
2797 | switch (align) | |
2798 | { | |
2799 | case 8: | |
2800 | /* Pre-adjust the loop counter. */ | |
2801 | operands[2] = GEN_INT (n_bytes - 16); | |
2802 | output_asm_insn ("ldi %2,%1", operands); | |
2803 | ||
2804 | /* Loop. */ | |
2805 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2806 | output_asm_insn ("addib,>= -16,%1,.-4", operands); | |
2807 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2808 | ||
2809 | /* Handle the residual. There could be up to 7 bytes of | |
2810 | residual to copy! */ | |
2811 | if (n_bytes % 16 != 0) | |
2812 | { | |
2813 | operands[2] = GEN_INT (n_bytes % 8); | |
2814 | if (n_bytes % 16 >= 8) | |
2815 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2816 | if (n_bytes % 8 != 0) | |
2817 | output_asm_insn ("stdby,e %%r0,%2(%0)", operands); | |
2818 | } | |
2819 | return ""; | |
2820 | ||
2821 | case 4: | |
2822 | /* Pre-adjust the loop counter. */ | |
2823 | operands[2] = GEN_INT (n_bytes - 8); | |
2824 | output_asm_insn ("ldi %2,%1", operands); | |
2825 | ||
2826 | /* Loop. */ | |
2827 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2828 | output_asm_insn ("addib,>= -8,%1,.-4", operands); | |
2829 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2830 | ||
2831 | /* Handle the residual. There could be up to 7 bytes of | |
2832 | residual to copy! */ | |
2833 | if (n_bytes % 8 != 0) | |
2834 | { | |
2835 | operands[2] = GEN_INT (n_bytes % 4); | |
2836 | if (n_bytes % 8 >= 4) | |
2837 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2838 | if (n_bytes % 4 != 0) | |
2839 | output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands); | |
2840 | } | |
2841 | return ""; | |
2842 | ||
2843 | case 2: | |
2844 | /* Pre-adjust the loop counter. */ | |
2845 | operands[2] = GEN_INT (n_bytes - 4); | |
2846 | output_asm_insn ("ldi %2,%1", operands); | |
2847 | ||
2848 | /* Loop. */ | |
2849 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2850 | output_asm_insn ("addib,>= -4,%1,.-4", operands); | |
2851 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2852 | ||
2853 | /* Handle the residual. */ | |
2854 | if (n_bytes % 4 != 0) | |
2855 | { | |
2856 | if (n_bytes % 4 >= 2) | |
2857 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2858 | if (n_bytes % 2 != 0) | |
2859 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2860 | } | |
2861 | return ""; | |
2862 | ||
2863 | case 1: | |
2864 | /* Pre-adjust the loop counter. */ | |
2865 | operands[2] = GEN_INT (n_bytes - 2); | |
2866 | output_asm_insn ("ldi %2,%1", operands); | |
2867 | ||
2868 | /* Loop. */ | |
2869 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2870 | output_asm_insn ("addib,>= -2,%1,.-4", operands); | |
2871 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2872 | ||
2873 | /* Handle the residual. */ | |
2874 | if (n_bytes % 2 != 0) | |
2875 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2876 | ||
2877 | return ""; | |
2878 | ||
2879 | default: | |
144d51f9 | 2880 | gcc_unreachable (); |
cdc9103c JDA |
2881 | } |
2882 | } | |
2883 | ||
2884 | /* Count the number of insns necessary to handle this block move. | |
2885 | ||
2886 | Basic structure is the same as emit_block_move, except that we | |
2887 | count insns rather than emit them. */ | |
2888 | ||
2889 | static int | |
70128ad9 | 2890 | compute_clrmem_length (rtx insn) |
cdc9103c JDA |
2891 | { |
2892 | rtx pat = PATTERN (insn); | |
2893 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0)); | |
2894 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0)); | |
2895 | unsigned int n_insns = 0; | |
2896 | ||
2897 | /* We can't clear more than a word at a time because the PA | |
2898 | has no longer integer move insns. */ | |
2899 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2900 | align = (TARGET_64BIT ? 8 : 4); | |
2901 | ||
2902 | /* The basic loop. */ | |
2903 | n_insns = 4; | |
2904 | ||
2905 | /* Residuals. */ | |
2906 | if (n_bytes % (2 * align) != 0) | |
2907 | { | |
2908 | if ((n_bytes % (2 * align)) >= align) | |
2909 | n_insns++; | |
2910 | ||
2911 | if ((n_bytes % align) != 0) | |
2912 | n_insns++; | |
2913 | } | |
2914 | ||
2915 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2916 | return n_insns * 4; | |
2917 | } | |
188538df TG |
2918 | \f |
2919 | ||
519104fe | 2920 | const char * |
b7849684 | 2921 | output_and (rtx *operands) |
0e7f4c19 | 2922 | { |
d2a94ec0 | 2923 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) |
0e7f4c19 | 2924 | { |
0c235d7e | 2925 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
0e7f4c19 TG |
2926 | int ls0, ls1, ms0, p, len; |
2927 | ||
2928 | for (ls0 = 0; ls0 < 32; ls0++) | |
2929 | if ((mask & (1 << ls0)) == 0) | |
2930 | break; | |
2931 | ||
2932 | for (ls1 = ls0; ls1 < 32; ls1++) | |
2933 | if ((mask & (1 << ls1)) != 0) | |
2934 | break; | |
2935 | ||
2936 | for (ms0 = ls1; ms0 < 32; ms0++) | |
2937 | if ((mask & (1 << ms0)) == 0) | |
2938 | break; | |
2939 | ||
144d51f9 | 2940 | gcc_assert (ms0 == 32); |
0e7f4c19 TG |
2941 | |
2942 | if (ls1 == 32) | |
2943 | { | |
2944 | len = ls0; | |
2945 | ||
144d51f9 | 2946 | gcc_assert (len); |
0e7f4c19 | 2947 | |
8919037c | 2948 | operands[2] = GEN_INT (len); |
f38b27c7 | 2949 | return "{extru|extrw,u} %1,31,%2,%0"; |
0e7f4c19 TG |
2950 | } |
2951 | else | |
2952 | { | |
2953 | /* We could use this `depi' for the case above as well, but `depi' | |
2954 | requires one more register file access than an `extru'. */ | |
2955 | ||
2956 | p = 31 - ls0; | |
2957 | len = ls1 - ls0; | |
2958 | ||
8919037c TG |
2959 | operands[2] = GEN_INT (p); |
2960 | operands[3] = GEN_INT (len); | |
f38b27c7 | 2961 | return "{depi|depwi} 0,%2,%3,%0"; |
0e7f4c19 TG |
2962 | } |
2963 | } | |
2964 | else | |
2965 | return "and %1,%2,%0"; | |
2966 | } | |
2967 | ||
520babc7 JL |
2968 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] |
2969 | storing the result in operands[0]. */ | |
0952f89b | 2970 | const char * |
b7849684 | 2971 | output_64bit_and (rtx *operands) |
520babc7 JL |
2972 | { |
2973 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) | |
2974 | { | |
2975 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
e0c556d3 | 2976 | int ls0, ls1, ms0, p, len; |
520babc7 JL |
2977 | |
2978 | for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++) | |
e0c556d3 | 2979 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0) |
520babc7 JL |
2980 | break; |
2981 | ||
2982 | for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++) | |
e0c556d3 | 2983 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0) |
520babc7 JL |
2984 | break; |
2985 | ||
2986 | for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++) | |
e0c556d3 | 2987 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0) |
520babc7 JL |
2988 | break; |
2989 | ||
144d51f9 | 2990 | gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT); |
520babc7 JL |
2991 | |
2992 | if (ls1 == HOST_BITS_PER_WIDE_INT) | |
2993 | { | |
2994 | len = ls0; | |
2995 | ||
144d51f9 | 2996 | gcc_assert (len); |
520babc7 JL |
2997 | |
2998 | operands[2] = GEN_INT (len); | |
2999 | return "extrd,u %1,63,%2,%0"; | |
3000 | } | |
3001 | else | |
3002 | { | |
3003 | /* We could use this `depi' for the case above as well, but `depi' | |
3004 | requires one more register file access than an `extru'. */ | |
3005 | ||
3006 | p = 63 - ls0; | |
3007 | len = ls1 - ls0; | |
3008 | ||
3009 | operands[2] = GEN_INT (p); | |
3010 | operands[3] = GEN_INT (len); | |
3011 | return "depdi 0,%2,%3,%0"; | |
3012 | } | |
3013 | } | |
3014 | else | |
3015 | return "and %1,%2,%0"; | |
3016 | } | |
3017 | ||
519104fe | 3018 | const char * |
b7849684 | 3019 | output_ior (rtx *operands) |
0e7f4c19 | 3020 | { |
0c235d7e | 3021 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
f1c7ce82 | 3022 | int bs0, bs1, p, len; |
23f6f34f | 3023 | |
8365d59b TG |
3024 | if (INTVAL (operands[2]) == 0) |
3025 | return "copy %1,%0"; | |
0e7f4c19 | 3026 | |
8365d59b TG |
3027 | for (bs0 = 0; bs0 < 32; bs0++) |
3028 | if ((mask & (1 << bs0)) != 0) | |
3029 | break; | |
0e7f4c19 | 3030 | |
8365d59b TG |
3031 | for (bs1 = bs0; bs1 < 32; bs1++) |
3032 | if ((mask & (1 << bs1)) == 0) | |
3033 | break; | |
0e7f4c19 | 3034 | |
144d51f9 | 3035 | gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); |
0e7f4c19 | 3036 | |
8365d59b TG |
3037 | p = 31 - bs0; |
3038 | len = bs1 - bs0; | |
0e7f4c19 | 3039 | |
8919037c TG |
3040 | operands[2] = GEN_INT (p); |
3041 | operands[3] = GEN_INT (len); | |
f38b27c7 | 3042 | return "{depi|depwi} -1,%2,%3,%0"; |
0e7f4c19 | 3043 | } |
520babc7 JL |
3044 | |
3045 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] | |
3046 | storing the result in operands[0]. */ | |
0952f89b | 3047 | const char * |
b7849684 | 3048 | output_64bit_ior (rtx *operands) |
520babc7 JL |
3049 | { |
3050 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
e0c556d3 | 3051 | int bs0, bs1, p, len; |
520babc7 JL |
3052 | |
3053 | if (INTVAL (operands[2]) == 0) | |
3054 | return "copy %1,%0"; | |
3055 | ||
3056 | for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++) | |
e0c556d3 | 3057 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0) |
520babc7 JL |
3058 | break; |
3059 | ||
3060 | for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++) | |
e0c556d3 | 3061 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0) |
520babc7 JL |
3062 | break; |
3063 | ||
144d51f9 NS |
3064 | gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT |
3065 | || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); | |
520babc7 JL |
3066 | |
3067 | p = 63 - bs0; | |
3068 | len = bs1 - bs0; | |
3069 | ||
3070 | operands[2] = GEN_INT (p); | |
3071 | operands[3] = GEN_INT (len); | |
3072 | return "depdi -1,%2,%3,%0"; | |
3073 | } | |
0e7f4c19 | 3074 | \f |
301d03af | 3075 | /* Target hook for assembling integer objects. This code handles |
cdcb88d7 JDA |
3076 | aligned SI and DI integers specially since function references |
3077 | must be preceded by P%. */ | |
301d03af RS |
3078 | |
3079 | static bool | |
b7849684 | 3080 | pa_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af | 3081 | { |
cdcb88d7 JDA |
3082 | if (size == UNITS_PER_WORD |
3083 | && aligned_p | |
301d03af RS |
3084 | && function_label_operand (x, VOIDmode)) |
3085 | { | |
3086 | fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file); | |
3087 | output_addr_const (asm_out_file, x); | |
3088 | fputc ('\n', asm_out_file); | |
3089 | return true; | |
3090 | } | |
3091 | return default_assemble_integer (x, size, aligned_p); | |
3092 | } | |
3093 | \f | |
188538df | 3094 | /* Output an ascii string. */ |
f1c7ce82 | 3095 | void |
b7849684 | 3096 | output_ascii (FILE *file, const char *p, int size) |
188538df TG |
3097 | { |
3098 | int i; | |
3099 | int chars_output; | |
71cc389b | 3100 | unsigned char partial_output[16]; /* Max space 4 chars can occupy. */ |
188538df TG |
3101 | |
3102 | /* The HP assembler can only take strings of 256 characters at one | |
3103 | time. This is a limitation on input line length, *not* the | |
3104 | length of the string. Sigh. Even worse, it seems that the | |
3105 | restriction is in number of input characters (see \xnn & | |
3106 | \whatever). So we have to do this very carefully. */ | |
3107 | ||
e236a9ff | 3108 | fputs ("\t.STRING \"", file); |
188538df TG |
3109 | |
3110 | chars_output = 0; | |
3111 | for (i = 0; i < size; i += 4) | |
3112 | { | |
3113 | int co = 0; | |
3114 | int io = 0; | |
3115 | for (io = 0, co = 0; io < MIN (4, size - i); io++) | |
3116 | { | |
6b5ffd4e | 3117 | register unsigned int c = (unsigned char) p[i + io]; |
188538df TG |
3118 | |
3119 | if (c == '\"' || c == '\\') | |
3120 | partial_output[co++] = '\\'; | |
3121 | if (c >= ' ' && c < 0177) | |
3122 | partial_output[co++] = c; | |
3123 | else | |
3124 | { | |
3125 | unsigned int hexd; | |
3126 | partial_output[co++] = '\\'; | |
3127 | partial_output[co++] = 'x'; | |
3128 | hexd = c / 16 - 0 + '0'; | |
3129 | if (hexd > '9') | |
3130 | hexd -= '9' - 'a' + 1; | |
3131 | partial_output[co++] = hexd; | |
3132 | hexd = c % 16 - 0 + '0'; | |
3133 | if (hexd > '9') | |
3134 | hexd -= '9' - 'a' + 1; | |
3135 | partial_output[co++] = hexd; | |
3136 | } | |
3137 | } | |
3138 | if (chars_output + co > 243) | |
3139 | { | |
e236a9ff | 3140 | fputs ("\"\n\t.STRING \"", file); |
188538df TG |
3141 | chars_output = 0; |
3142 | } | |
823fbbce | 3143 | fwrite (partial_output, 1, (size_t) co, file); |
188538df TG |
3144 | chars_output += co; |
3145 | co = 0; | |
3146 | } | |
e236a9ff | 3147 | fputs ("\"\n", file); |
188538df | 3148 | } |
5621d717 JL |
3149 | |
3150 | /* Try to rewrite floating point comparisons & branches to avoid | |
3151 | useless add,tr insns. | |
3152 | ||
3153 | CHECK_NOTES is nonzero if we should examine REG_DEAD notes | |
3154 | to see if FPCC is dead. CHECK_NOTES is nonzero for the | |
3155 | first attempt to remove useless add,tr insns. It is zero | |
3156 | for the second pass as reorg sometimes leaves bogus REG_DEAD | |
3157 | notes lying around. | |
3158 | ||
3159 | When CHECK_NOTES is zero we can only eliminate add,tr insns | |
3160 | when there's a 1:1 correspondence between fcmp and ftest/fbranch | |
3161 | instructions. */ | |
519104fe | 3162 | static void |
b7849684 | 3163 | remove_useless_addtr_insns (int check_notes) |
5621d717 JL |
3164 | { |
3165 | rtx insn; | |
5621d717 JL |
3166 | static int pass = 0; |
3167 | ||
3168 | /* This is fairly cheap, so always run it when optimizing. */ | |
3169 | if (optimize > 0) | |
3170 | { | |
3171 | int fcmp_count = 0; | |
3172 | int fbranch_count = 0; | |
3173 | ||
3174 | /* Walk all the insns in this function looking for fcmp & fbranch | |
3175 | instructions. Keep track of how many of each we find. */ | |
18dbd950 | 3176 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
5621d717 JL |
3177 | { |
3178 | rtx tmp; | |
3179 | ||
3180 | /* Ignore anything that isn't an INSN or a JUMP_INSN. */ | |
3181 | if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
3182 | continue; | |
3183 | ||
3184 | tmp = PATTERN (insn); | |
3185 | ||
3186 | /* It must be a set. */ | |
3187 | if (GET_CODE (tmp) != SET) | |
3188 | continue; | |
3189 | ||
3190 | /* If the destination is CCFP, then we've found an fcmp insn. */ | |
3191 | tmp = SET_DEST (tmp); | |
3192 | if (GET_CODE (tmp) == REG && REGNO (tmp) == 0) | |
3193 | { | |
3194 | fcmp_count++; | |
3195 | continue; | |
3196 | } | |
6619e96c | 3197 | |
5621d717 JL |
3198 | tmp = PATTERN (insn); |
3199 | /* If this is an fbranch instruction, bump the fbranch counter. */ | |
3200 | if (GET_CODE (tmp) == SET | |
3201 | && SET_DEST (tmp) == pc_rtx | |
3202 | && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE | |
3203 | && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE | |
3204 | && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG | |
3205 | && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0) | |
3206 | { | |
3207 | fbranch_count++; | |
3208 | continue; | |
3209 | } | |
3210 | } | |
3211 | ||
3212 | ||
3213 | /* Find all floating point compare + branch insns. If possible, | |
3214 | reverse the comparison & the branch to avoid add,tr insns. */ | |
18dbd950 | 3215 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
5621d717 JL |
3216 | { |
3217 | rtx tmp, next; | |
3218 | ||
3219 | /* Ignore anything that isn't an INSN. */ | |
3220 | if (GET_CODE (insn) != INSN) | |
3221 | continue; | |
3222 | ||
3223 | tmp = PATTERN (insn); | |
3224 | ||
3225 | /* It must be a set. */ | |
3226 | if (GET_CODE (tmp) != SET) | |
3227 | continue; | |
3228 | ||
3229 | /* The destination must be CCFP, which is register zero. */ | |
3230 | tmp = SET_DEST (tmp); | |
3231 | if (GET_CODE (tmp) != REG || REGNO (tmp) != 0) | |
3232 | continue; | |
3233 | ||
3234 | /* INSN should be a set of CCFP. | |
3235 | ||
3236 | See if the result of this insn is used in a reversed FP | |
3237 | conditional branch. If so, reverse our condition and | |
3238 | the branch. Doing so avoids useless add,tr insns. */ | |
3239 | next = next_insn (insn); | |
3240 | while (next) | |
3241 | { | |
3242 | /* Jumps, calls and labels stop our search. */ | |
3243 | if (GET_CODE (next) == JUMP_INSN | |
3244 | || GET_CODE (next) == CALL_INSN | |
3245 | || GET_CODE (next) == CODE_LABEL) | |
3246 | break; | |
3247 | ||
3248 | /* As does another fcmp insn. */ | |
3249 | if (GET_CODE (next) == INSN | |
3250 | && GET_CODE (PATTERN (next)) == SET | |
3251 | && GET_CODE (SET_DEST (PATTERN (next))) == REG | |
3252 | && REGNO (SET_DEST (PATTERN (next))) == 0) | |
3253 | break; | |
3254 | ||
3255 | next = next_insn (next); | |
3256 | } | |
3257 | ||
3258 | /* Is NEXT_INSN a branch? */ | |
3259 | if (next | |
3260 | && GET_CODE (next) == JUMP_INSN) | |
3261 | { | |
3262 | rtx pattern = PATTERN (next); | |
3263 | ||
112cdef5 | 3264 | /* If it a reversed fp conditional branch (e.g. uses add,tr) |
5621d717 JL |
3265 | and CCFP dies, then reverse our conditional and the branch |
3266 | to avoid the add,tr. */ | |
3267 | if (GET_CODE (pattern) == SET | |
3268 | && SET_DEST (pattern) == pc_rtx | |
3269 | && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE | |
3270 | && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE | |
3271 | && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG | |
3272 | && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0 | |
3273 | && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC | |
3274 | && (fcmp_count == fbranch_count | |
3275 | || (check_notes | |
3276 | && find_regno_note (next, REG_DEAD, 0)))) | |
3277 | { | |
3278 | /* Reverse the branch. */ | |
3279 | tmp = XEXP (SET_SRC (pattern), 1); | |
3280 | XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2); | |
3281 | XEXP (SET_SRC (pattern), 2) = tmp; | |
3282 | INSN_CODE (next) = -1; | |
3283 | ||
3284 | /* Reverse our condition. */ | |
3285 | tmp = PATTERN (insn); | |
3286 | PUT_CODE (XEXP (tmp, 1), | |
831c1763 AM |
3287 | (reverse_condition_maybe_unordered |
3288 | (GET_CODE (XEXP (tmp, 1))))); | |
5621d717 JL |
3289 | } |
3290 | } | |
3291 | } | |
3292 | } | |
3293 | ||
3294 | pass = !pass; | |
3295 | ||
3296 | } | |
188538df | 3297 | \f |
831c1763 AM |
3298 | /* You may have trouble believing this, but this is the 32 bit HP-PA |
3299 | stack layout. Wow. | |
188538df TG |
3300 | |
3301 | Offset Contents | |
3302 | ||
3303 | Variable arguments (optional; any number may be allocated) | |
3304 | ||
3305 | SP-(4*(N+9)) arg word N | |
3306 | : : | |
3307 | SP-56 arg word 5 | |
3308 | SP-52 arg word 4 | |
3309 | ||
3310 | Fixed arguments (must be allocated; may remain unused) | |
3311 | ||
3312 | SP-48 arg word 3 | |
3313 | SP-44 arg word 2 | |
3314 | SP-40 arg word 1 | |
3315 | SP-36 arg word 0 | |
3316 | ||
3317 | Frame Marker | |
3318 | ||
3319 | SP-32 External Data Pointer (DP) | |
3320 | SP-28 External sr4 | |
3321 | SP-24 External/stub RP (RP') | |
3322 | SP-20 Current RP | |
3323 | SP-16 Static Link | |
3324 | SP-12 Clean up | |
3325 | SP-8 Calling Stub RP (RP'') | |
3326 | SP-4 Previous SP | |
3327 | ||
3328 | Top of Frame | |
3329 | ||
3330 | SP-0 Stack Pointer (points to next available address) | |
3331 | ||
3332 | */ | |
3333 | ||
3334 | /* This function saves registers as follows. Registers marked with ' are | |
3335 | this function's registers (as opposed to the previous function's). | |
3336 | If a frame_pointer isn't needed, r4 is saved as a general register; | |
3337 | the space for the frame pointer is still allocated, though, to keep | |
3338 | things simple. | |
3339 | ||
3340 | ||
3341 | Top of Frame | |
3342 | ||
3343 | SP (FP') Previous FP | |
3344 | SP + 4 Alignment filler (sigh) | |
3345 | SP + 8 Space for locals reserved here. | |
3346 | . | |
3347 | . | |
3348 | . | |
3349 | SP + n All call saved register used. | |
3350 | . | |
3351 | . | |
3352 | . | |
3353 | SP + o All call saved fp registers used. | |
3354 | . | |
3355 | . | |
3356 | . | |
3357 | SP + p (SP') points to next available address. | |
23f6f34f | 3358 | |
188538df TG |
3359 | */ |
3360 | ||
08c148a8 | 3361 | /* Global variables set by output_function_prologue(). */ |
19ec6a36 AM |
3362 | /* Size of frame. Need to know this to emit return insns from |
3363 | leaf procedures. */ | |
a4295210 JDA |
3364 | static HOST_WIDE_INT actual_fsize, local_fsize; |
3365 | static int save_fregs; | |
19ec6a36 | 3366 | |
aadcdb45 | 3367 | /* Emit RTL to store REG at the memory location specified by BASE+DISP. |
fc82f2f1 | 3368 | Handle case where DISP > 8k by using the add_high_const patterns. |
aadcdb45 JL |
3369 | |
3370 | Note in DISP > 8k case, we will leave the high part of the address | |
3371 | in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/ | |
c5c76735 | 3372 | |
f6bcf44c | 3373 | static void |
a4295210 | 3374 | store_reg (int reg, HOST_WIDE_INT disp, int base) |
188538df | 3375 | { |
f6bcf44c | 3376 | rtx insn, dest, src, basereg; |
19ec6a36 AM |
3377 | |
3378 | src = gen_rtx_REG (word_mode, reg); | |
3379 | basereg = gen_rtx_REG (Pmode, base); | |
188538df | 3380 | if (VAL_14_BITS_P (disp)) |
aadcdb45 | 3381 | { |
19ec6a36 | 3382 | dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
f6bcf44c | 3383 | insn = emit_move_insn (dest, src); |
aadcdb45 | 3384 | } |
a4295210 JDA |
3385 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3386 | { | |
3387 | rtx delta = GEN_INT (disp); | |
3388 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3389 | ||
3390 | emit_move_insn (tmpreg, delta); | |
5dcc9605 | 3391 | insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); |
a4295210 JDA |
3392 | if (DO_FRAME_NOTES) |
3393 | { | |
bbbbb16a ILT |
3394 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3395 | gen_rtx_SET (VOIDmode, tmpreg, | |
3396 | gen_rtx_PLUS (Pmode, basereg, delta))); | |
5dcc9605 | 3397 | RTX_FRAME_RELATED_P (insn) = 1; |
a4295210 | 3398 | } |
5dcc9605 JDA |
3399 | dest = gen_rtx_MEM (word_mode, tmpreg); |
3400 | insn = emit_move_insn (dest, src); | |
a4295210 | 3401 | } |
aadcdb45 JL |
3402 | else |
3403 | { | |
19ec6a36 AM |
3404 | rtx delta = GEN_INT (disp); |
3405 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3406 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
a4295210 | 3407 | |
19ec6a36 AM |
3408 | emit_move_insn (tmpreg, high); |
3409 | dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
f6bcf44c JDA |
3410 | insn = emit_move_insn (dest, src); |
3411 | if (DO_FRAME_NOTES) | |
bbbbb16a ILT |
3412 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3413 | gen_rtx_SET (VOIDmode, | |
3414 | gen_rtx_MEM (word_mode, | |
3415 | gen_rtx_PLUS (word_mode, | |
3416 | basereg, | |
3417 | delta)), | |
3418 | src)); | |
aadcdb45 | 3419 | } |
f6bcf44c JDA |
3420 | |
3421 | if (DO_FRAME_NOTES) | |
3422 | RTX_FRAME_RELATED_P (insn) = 1; | |
aadcdb45 JL |
3423 | } |
3424 | ||
823fbbce JDA |
3425 | /* Emit RTL to store REG at the memory location specified by BASE and then |
3426 | add MOD to BASE. MOD must be <= 8k. */ | |
aadcdb45 | 3427 | |
823fbbce | 3428 | static void |
a4295210 | 3429 | store_reg_modify (int base, int reg, HOST_WIDE_INT mod) |
823fbbce JDA |
3430 | { |
3431 | rtx insn, basereg, srcreg, delta; | |
3432 | ||
144d51f9 | 3433 | gcc_assert (VAL_14_BITS_P (mod)); |
823fbbce JDA |
3434 | |
3435 | basereg = gen_rtx_REG (Pmode, base); | |
3436 | srcreg = gen_rtx_REG (word_mode, reg); | |
3437 | delta = GEN_INT (mod); | |
3438 | ||
3439 | insn = emit_insn (gen_post_store (basereg, srcreg, delta)); | |
3440 | if (DO_FRAME_NOTES) | |
3441 | { | |
3442 | RTX_FRAME_RELATED_P (insn) = 1; | |
3443 | ||
3444 | /* RTX_FRAME_RELATED_P must be set on each frame related set | |
77c4f044 RH |
3445 | in a parallel with more than one element. */ |
3446 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1; | |
3447 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; | |
823fbbce JDA |
3448 | } |
3449 | } | |
3450 | ||
3451 | /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case | |
3452 | where DISP > 8k by using the add_high_const patterns. NOTE indicates | |
3453 | whether to add a frame note or not. | |
3454 | ||
3455 | In the DISP > 8k case, we leave the high part of the address in %r1. | |
3456 | There is code in expand_hppa_{prologue,epilogue} that knows about this. */ | |
c5c76735 | 3457 | |
f6bcf44c | 3458 | static void |
a4295210 | 3459 | set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note) |
188538df | 3460 | { |
f6bcf44c | 3461 | rtx insn; |
19ec6a36 | 3462 | |
188538df | 3463 | if (VAL_14_BITS_P (disp)) |
19ec6a36 | 3464 | { |
f6bcf44c JDA |
3465 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
3466 | plus_constant (gen_rtx_REG (Pmode, base), disp)); | |
19ec6a36 | 3467 | } |
a4295210 JDA |
3468 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3469 | { | |
3470 | rtx basereg = gen_rtx_REG (Pmode, base); | |
3471 | rtx delta = GEN_INT (disp); | |
3472 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3473 | ||
3474 | emit_move_insn (tmpreg, delta); | |
3475 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), | |
3476 | gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
5dcc9605 | 3477 | if (DO_FRAME_NOTES) |
bbbbb16a ILT |
3478 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3479 | gen_rtx_SET (VOIDmode, tmpreg, | |
3480 | gen_rtx_PLUS (Pmode, basereg, delta))); | |
a4295210 | 3481 | } |
188538df | 3482 | else |
aadcdb45 | 3483 | { |
f6bcf44c | 3484 | rtx basereg = gen_rtx_REG (Pmode, base); |
19ec6a36 | 3485 | rtx delta = GEN_INT (disp); |
a4295210 | 3486 | rtx tmpreg = gen_rtx_REG (Pmode, 1); |
f6bcf44c | 3487 | |
a4295210 | 3488 | emit_move_insn (tmpreg, |
f6bcf44c | 3489 | gen_rtx_PLUS (Pmode, basereg, |
19ec6a36 | 3490 | gen_rtx_HIGH (Pmode, delta))); |
f6bcf44c | 3491 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
a4295210 | 3492 | gen_rtx_LO_SUM (Pmode, tmpreg, delta)); |
aadcdb45 | 3493 | } |
f6bcf44c | 3494 | |
823fbbce | 3495 | if (DO_FRAME_NOTES && note) |
f6bcf44c | 3496 | RTX_FRAME_RELATED_P (insn) = 1; |
188538df TG |
3497 | } |
3498 | ||
a4295210 JDA |
3499 | HOST_WIDE_INT |
3500 | compute_frame_size (HOST_WIDE_INT size, int *fregs_live) | |
188538df | 3501 | { |
95f3f59e JDA |
3502 | int freg_saved = 0; |
3503 | int i, j; | |
3504 | ||
3505 | /* The code in hppa_expand_prologue and hppa_expand_epilogue must | |
3506 | be consistent with the rounding and size calculation done here. | |
3507 | Change them at the same time. */ | |
3508 | ||
3509 | /* We do our own stack alignment. First, round the size of the | |
3510 | stack locals up to a word boundary. */ | |
3511 | size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3512 | ||
3513 | /* Space for previous frame pointer + filler. If any frame is | |
3514 | allocated, we need to add in the STARTING_FRAME_OFFSET. We | |
3515 | waste some space here for the sake of HP compatibility. The | |
3516 | first slot is only used when the frame pointer is needed. */ | |
3517 | if (size || frame_pointer_needed) | |
3518 | size += STARTING_FRAME_OFFSET; | |
3519 | ||
823fbbce JDA |
3520 | /* If the current function calls __builtin_eh_return, then we need |
3521 | to allocate stack space for registers that will hold data for | |
3522 | the exception handler. */ | |
e3b5732b | 3523 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
823fbbce JDA |
3524 | { |
3525 | unsigned int i; | |
3526 | ||
3527 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
3528 | continue; | |
95f3f59e | 3529 | size += i * UNITS_PER_WORD; |
823fbbce JDA |
3530 | } |
3531 | ||
6261ede7 | 3532 | /* Account for space used by the callee general register saves. */ |
95f3f59e | 3533 | for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--) |
6fb5fa3c | 3534 | if (df_regs_ever_live_p (i)) |
95f3f59e | 3535 | size += UNITS_PER_WORD; |
80225b66 | 3536 | |
6261ede7 | 3537 | /* Account for space used by the callee floating point register saves. */ |
88624c0e | 3538 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
6fb5fa3c DB |
3539 | if (df_regs_ever_live_p (i) |
3540 | || (!TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
80225b66 | 3541 | { |
95f3f59e | 3542 | freg_saved = 1; |
9e18f575 | 3543 | |
6261ede7 JL |
3544 | /* We always save both halves of the FP register, so always |
3545 | increment the frame size by 8 bytes. */ | |
95f3f59e | 3546 | size += 8; |
80225b66 TG |
3547 | } |
3548 | ||
95f3f59e JDA |
3549 | /* If any of the floating registers are saved, account for the |
3550 | alignment needed for the floating point register save block. */ | |
3551 | if (freg_saved) | |
3552 | { | |
3553 | size = (size + 7) & ~7; | |
3554 | if (fregs_live) | |
3555 | *fregs_live = 1; | |
3556 | } | |
3557 | ||
6261ede7 | 3558 | /* The various ABIs include space for the outgoing parameters in the |
95f3f59e JDA |
3559 | size of the current function's stack frame. We don't need to align |
3560 | for the outgoing arguments as their alignment is set by the final | |
3561 | rounding for the frame as a whole. */ | |
38173d38 | 3562 | size += crtl->outgoing_args_size; |
6261ede7 JL |
3563 | |
3564 | /* Allocate space for the fixed frame marker. This space must be | |
685d0e07 | 3565 | allocated for any function that makes calls or allocates |
6261ede7 | 3566 | stack space. */ |
95f3f59e | 3567 | if (!current_function_is_leaf || size) |
685d0e07 | 3568 | size += TARGET_64BIT ? 48 : 32; |
520babc7 | 3569 | |
95f3f59e | 3570 | /* Finally, round to the preferred stack boundary. */ |
5fad1c24 JDA |
3571 | return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1) |
3572 | & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
188538df | 3573 | } |
23f6f34f | 3574 | |
08c148a8 NB |
3575 | /* Generate the assembly code for function entry. FILE is a stdio |
3576 | stream to output the code to. SIZE is an int: how many units of | |
3577 | temporary storage to allocate. | |
3578 | ||
3579 | Refer to the array `regs_ever_live' to determine which registers to | |
3580 | save; `regs_ever_live[I]' is nonzero if register number I is ever | |
3581 | used in the function. This function is responsible for knowing | |
3582 | which registers should not be saved even if used. */ | |
3583 | ||
3584 | /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block | |
3585 | of memory. If any fpu reg is used in the function, we allocate | |
3586 | such a block here, at the bottom of the frame, just in case it's needed. | |
3587 | ||
3588 | If this function is a leaf procedure, then we may choose not | |
3589 | to do a "save" insn. The decision about whether or not | |
3590 | to do this is made in regclass.c. */ | |
3591 | ||
c590b625 | 3592 | static void |
b7849684 | 3593 | pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
188538df | 3594 | { |
ba0bfdac JL |
3595 | /* The function's label and associated .PROC must never be |
3596 | separated and must be output *after* any profiling declarations | |
3597 | to avoid changing spaces/subspaces within a procedure. */ | |
3598 | ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3599 | fputs ("\t.PROC\n", file); | |
3600 | ||
aadcdb45 JL |
3601 | /* hppa_expand_prologue does the dirty work now. We just need |
3602 | to output the assembler directives which denote the start | |
3603 | of a function. */ | |
a4295210 | 3604 | fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize); |
16c16a24 | 3605 | if (current_function_is_leaf) |
e236a9ff | 3606 | fputs (",NO_CALLS", file); |
16c16a24 JDA |
3607 | else |
3608 | fputs (",CALLS", file); | |
3609 | if (rp_saved) | |
3610 | fputs (",SAVE_RP", file); | |
da3c3336 | 3611 | |
685d0e07 JDA |
3612 | /* The SAVE_SP flag is used to indicate that register %r3 is stored |
3613 | at the beginning of the frame and that it is used as the frame | |
3614 | pointer for the frame. We do this because our current frame | |
a4d05547 | 3615 | layout doesn't conform to that specified in the HP runtime |
685d0e07 JDA |
3616 | documentation and we need a way to indicate to programs such as |
3617 | GDB where %r3 is saved. The SAVE_SP flag was chosen because it | |
3618 | isn't used by HP compilers but is supported by the assembler. | |
3619 | However, SAVE_SP is supposed to indicate that the previous stack | |
3620 | pointer has been saved in the frame marker. */ | |
da3c3336 | 3621 | if (frame_pointer_needed) |
e236a9ff | 3622 | fputs (",SAVE_SP", file); |
da3c3336 | 3623 | |
68386e1e | 3624 | /* Pass on information about the number of callee register saves |
e8cfae5c JL |
3625 | performed in the prologue. |
3626 | ||
3627 | The compiler is supposed to pass the highest register number | |
23f6f34f | 3628 | saved, the assembler then has to adjust that number before |
e8cfae5c | 3629 | entering it into the unwind descriptor (to account for any |
23f6f34f | 3630 | caller saved registers with lower register numbers than the |
e8cfae5c JL |
3631 | first callee saved register). */ |
3632 | if (gr_saved) | |
3633 | fprintf (file, ",ENTRY_GR=%d", gr_saved + 2); | |
3634 | ||
3635 | if (fr_saved) | |
3636 | fprintf (file, ",ENTRY_FR=%d", fr_saved + 11); | |
68386e1e | 3637 | |
e236a9ff | 3638 | fputs ("\n\t.ENTRY\n", file); |
aadcdb45 | 3639 | |
18dbd950 | 3640 | remove_useless_addtr_insns (0); |
aadcdb45 JL |
3641 | } |
3642 | ||
f1c7ce82 | 3643 | void |
b7849684 | 3644 | hppa_expand_prologue (void) |
aadcdb45 | 3645 | { |
4971c587 | 3646 | int merge_sp_adjust_with_store = 0; |
a4295210 JDA |
3647 | HOST_WIDE_INT size = get_frame_size (); |
3648 | HOST_WIDE_INT offset; | |
3649 | int i; | |
823fbbce | 3650 | rtx insn, tmpreg; |
aadcdb45 | 3651 | |
68386e1e JL |
3652 | gr_saved = 0; |
3653 | fr_saved = 0; | |
8a9c76f3 | 3654 | save_fregs = 0; |
6261ede7 | 3655 | |
95f3f59e JDA |
3656 | /* Compute total size for frame pointer, filler, locals and rounding to |
3657 | the next word boundary. Similar code appears in compute_frame_size | |
3658 | and must be changed in tandem with this code. */ | |
3659 | local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3660 | if (local_fsize || frame_pointer_needed) | |
3661 | local_fsize += STARTING_FRAME_OFFSET; | |
6261ede7 | 3662 | |
2b41935c | 3663 | actual_fsize = compute_frame_size (size, &save_fregs); |
188538df | 3664 | |
aadcdb45 | 3665 | /* Compute a few things we will use often. */ |
690d4228 | 3666 | tmpreg = gen_rtx_REG (word_mode, 1); |
188538df | 3667 | |
23f6f34f | 3668 | /* Save RP first. The calling conventions manual states RP will |
19ec6a36 | 3669 | always be stored into the caller's frame at sp - 20 or sp - 16 |
520babc7 | 3670 | depending on which ABI is in use. */ |
e3b5732b | 3671 | if (df_regs_ever_live_p (2) || crtl->calls_eh_return) |
16c16a24 JDA |
3672 | { |
3673 | store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM); | |
3674 | rp_saved = true; | |
3675 | } | |
3676 | else | |
3677 | rp_saved = false; | |
23f6f34f | 3678 | |
aadcdb45 | 3679 | /* Allocate the local frame and set up the frame pointer if needed. */ |
31d68947 AM |
3680 | if (actual_fsize != 0) |
3681 | { | |
3682 | if (frame_pointer_needed) | |
3683 | { | |
3684 | /* Copy the old frame pointer temporarily into %r1. Set up the | |
3685 | new stack pointer, then store away the saved old frame pointer | |
823fbbce JDA |
3686 | into the stack at sp and at the same time update the stack |
3687 | pointer by actual_fsize bytes. Two versions, first | |
31d68947 AM |
3688 | handles small (<8k) frames. The second handles large (>=8k) |
3689 | frames. */ | |
823fbbce JDA |
3690 | insn = emit_move_insn (tmpreg, frame_pointer_rtx); |
3691 | if (DO_FRAME_NOTES) | |
77c4f044 | 3692 | RTX_FRAME_RELATED_P (insn) = 1; |
823fbbce JDA |
3693 | |
3694 | insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); | |
3695 | if (DO_FRAME_NOTES) | |
3696 | RTX_FRAME_RELATED_P (insn) = 1; | |
3697 | ||
3698 | if (VAL_14_BITS_P (actual_fsize)) | |
3699 | store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize); | |
31d68947 AM |
3700 | else |
3701 | { | |
3702 | /* It is incorrect to store the saved frame pointer at *sp, | |
3703 | then increment sp (writes beyond the current stack boundary). | |
3704 | ||
3705 | So instead use stwm to store at *sp and post-increment the | |
3706 | stack pointer as an atomic operation. Then increment sp to | |
3707 | finish allocating the new frame. */ | |
a4295210 JDA |
3708 | HOST_WIDE_INT adjust1 = 8192 - 64; |
3709 | HOST_WIDE_INT adjust2 = actual_fsize - adjust1; | |
19ec6a36 | 3710 | |
823fbbce | 3711 | store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1); |
f6bcf44c | 3712 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
823fbbce | 3713 | adjust2, 1); |
31d68947 | 3714 | } |
823fbbce | 3715 | |
685d0e07 JDA |
3716 | /* We set SAVE_SP in frames that need a frame pointer. Thus, |
3717 | we need to store the previous stack pointer (frame pointer) | |
3718 | into the frame marker on targets that use the HP unwind | |
3719 | library. This allows the HP unwind library to be used to | |
3720 | unwind GCC frames. However, we are not fully compatible | |
3721 | with the HP library because our frame layout differs from | |
3722 | that specified in the HP runtime specification. | |
3723 | ||
3724 | We don't want a frame note on this instruction as the frame | |
3725 | marker moves during dynamic stack allocation. | |
3726 | ||
3727 | This instruction also serves as a blockage to prevent | |
3728 | register spills from being scheduled before the stack | |
3729 | pointer is raised. This is necessary as we store | |
3730 | registers using the frame pointer as a base register, | |
3731 | and the frame pointer is set before sp is raised. */ | |
3732 | if (TARGET_HPUX_UNWIND_LIBRARY) | |
3733 | { | |
3734 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, | |
3735 | GEN_INT (TARGET_64BIT ? -8 : -4)); | |
3736 | ||
3737 | emit_move_insn (gen_rtx_MEM (word_mode, addr), | |
3738 | frame_pointer_rtx); | |
3739 | } | |
3740 | else | |
3741 | emit_insn (gen_blockage ()); | |
31d68947 AM |
3742 | } |
3743 | /* no frame pointer needed. */ | |
3744 | else | |
3745 | { | |
3746 | /* In some cases we can perform the first callee register save | |
3747 | and allocating the stack frame at the same time. If so, just | |
3748 | make a note of it and defer allocating the frame until saving | |
3749 | the callee registers. */ | |
1c7a8112 | 3750 | if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0) |
31d68947 AM |
3751 | merge_sp_adjust_with_store = 1; |
3752 | /* Can not optimize. Adjust the stack frame by actual_fsize | |
3753 | bytes. */ | |
3754 | else | |
f6bcf44c | 3755 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
823fbbce | 3756 | actual_fsize, 1); |
31d68947 | 3757 | } |
a9d91d6f RS |
3758 | } |
3759 | ||
23f6f34f | 3760 | /* Normal register save. |
aadcdb45 JL |
3761 | |
3762 | Do not save the frame pointer in the frame_pointer_needed case. It | |
3763 | was done earlier. */ | |
188538df TG |
3764 | if (frame_pointer_needed) |
3765 | { | |
823fbbce JDA |
3766 | offset = local_fsize; |
3767 | ||
3768 | /* Saving the EH return data registers in the frame is the simplest | |
3769 | way to get the frame unwind information emitted. We put them | |
3770 | just before the general registers. */ | |
e3b5732b | 3771 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
823fbbce JDA |
3772 | { |
3773 | unsigned int i, regno; | |
3774 | ||
3775 | for (i = 0; ; ++i) | |
3776 | { | |
3777 | regno = EH_RETURN_DATA_REGNO (i); | |
3778 | if (regno == INVALID_REGNUM) | |
3779 | break; | |
3780 | ||
3781 | store_reg (regno, offset, FRAME_POINTER_REGNUM); | |
3782 | offset += UNITS_PER_WORD; | |
3783 | } | |
3784 | } | |
3785 | ||
3786 | for (i = 18; i >= 4; i--) | |
6fb5fa3c | 3787 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
188538df | 3788 | { |
f6bcf44c | 3789 | store_reg (i, offset, FRAME_POINTER_REGNUM); |
d7735a07 | 3790 | offset += UNITS_PER_WORD; |
68386e1e | 3791 | gr_saved++; |
188538df | 3792 | } |
e63ffc38 | 3793 | /* Account for %r3 which is saved in a special place. */ |
e8cfae5c | 3794 | gr_saved++; |
188538df | 3795 | } |
aadcdb45 | 3796 | /* No frame pointer needed. */ |
188538df TG |
3797 | else |
3798 | { | |
823fbbce JDA |
3799 | offset = local_fsize - actual_fsize; |
3800 | ||
3801 | /* Saving the EH return data registers in the frame is the simplest | |
3802 | way to get the frame unwind information emitted. */ | |
e3b5732b | 3803 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
823fbbce JDA |
3804 | { |
3805 | unsigned int i, regno; | |
3806 | ||
3807 | for (i = 0; ; ++i) | |
3808 | { | |
3809 | regno = EH_RETURN_DATA_REGNO (i); | |
3810 | if (regno == INVALID_REGNUM) | |
3811 | break; | |
3812 | ||
3813 | /* If merge_sp_adjust_with_store is nonzero, then we can | |
3814 | optimize the first save. */ | |
3815 | if (merge_sp_adjust_with_store) | |
3816 | { | |
3817 | store_reg_modify (STACK_POINTER_REGNUM, regno, -offset); | |
3818 | merge_sp_adjust_with_store = 0; | |
3819 | } | |
3820 | else | |
3821 | store_reg (regno, offset, STACK_POINTER_REGNUM); | |
3822 | offset += UNITS_PER_WORD; | |
3823 | } | |
3824 | } | |
3825 | ||
3826 | for (i = 18; i >= 3; i--) | |
6fb5fa3c | 3827 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
188538df | 3828 | { |
23f6f34f | 3829 | /* If merge_sp_adjust_with_store is nonzero, then we can |
4971c587 | 3830 | optimize the first GR save. */ |
f133af4c | 3831 | if (merge_sp_adjust_with_store) |
4971c587 | 3832 | { |
823fbbce | 3833 | store_reg_modify (STACK_POINTER_REGNUM, i, -offset); |
4971c587 | 3834 | merge_sp_adjust_with_store = 0; |
4971c587 JL |
3835 | } |
3836 | else | |
f6bcf44c | 3837 | store_reg (i, offset, STACK_POINTER_REGNUM); |
d7735a07 | 3838 | offset += UNITS_PER_WORD; |
68386e1e | 3839 | gr_saved++; |
188538df | 3840 | } |
aadcdb45 | 3841 | |
4971c587 | 3842 | /* If we wanted to merge the SP adjustment with a GR save, but we never |
aadcdb45 | 3843 | did any GR saves, then just emit the adjustment here. */ |
f133af4c | 3844 | if (merge_sp_adjust_with_store) |
f6bcf44c | 3845 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
823fbbce | 3846 | actual_fsize, 1); |
188538df | 3847 | } |
23f6f34f | 3848 | |
1c7a8112 AM |
3849 | /* The hppa calling conventions say that %r19, the pic offset |
3850 | register, is saved at sp - 32 (in this function's frame) | |
3851 | when generating PIC code. FIXME: What is the correct thing | |
3852 | to do for functions which make no calls and allocate no | |
3853 | frame? Do we need to allocate a frame, or can we just omit | |
3ffa9dc1 JDA |
3854 | the save? For now we'll just omit the save. |
3855 | ||
3856 | We don't want a note on this insn as the frame marker can | |
3857 | move if there is a dynamic stack allocation. */ | |
1c7a8112 | 3858 | if (flag_pic && actual_fsize != 0 && !TARGET_64BIT) |
3ffa9dc1 JDA |
3859 | { |
3860 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32)); | |
3861 | ||
3862 | emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx); | |
3863 | ||
3864 | } | |
1c7a8112 | 3865 | |
188538df TG |
3866 | /* Align pointer properly (doubleword boundary). */ |
3867 | offset = (offset + 7) & ~7; | |
3868 | ||
3869 | /* Floating point register store. */ | |
3870 | if (save_fregs) | |
188538df | 3871 | { |
823fbbce JDA |
3872 | rtx base; |
3873 | ||
aadcdb45 JL |
3874 | /* First get the frame or stack pointer to the start of the FP register |
3875 | save area. */ | |
2b41935c | 3876 | if (frame_pointer_needed) |
823fbbce JDA |
3877 | { |
3878 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); | |
3879 | base = frame_pointer_rtx; | |
3880 | } | |
2b41935c | 3881 | else |
823fbbce JDA |
3882 | { |
3883 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); | |
3884 | base = stack_pointer_rtx; | |
3885 | } | |
aadcdb45 JL |
3886 | |
3887 | /* Now actually save the FP registers. */ | |
88624c0e | 3888 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
e63ffc38 | 3889 | { |
6fb5fa3c DB |
3890 | if (df_regs_ever_live_p (i) |
3891 | || (! TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
e63ffc38 | 3892 | { |
f6bcf44c | 3893 | rtx addr, insn, reg; |
19ec6a36 AM |
3894 | addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); |
3895 | reg = gen_rtx_REG (DFmode, i); | |
f6bcf44c JDA |
3896 | insn = emit_move_insn (addr, reg); |
3897 | if (DO_FRAME_NOTES) | |
3898 | { | |
3899 | RTX_FRAME_RELATED_P (insn) = 1; | |
823fbbce JDA |
3900 | if (TARGET_64BIT) |
3901 | { | |
3902 | rtx mem = gen_rtx_MEM (DFmode, | |
3903 | plus_constant (base, offset)); | |
bbbbb16a ILT |
3904 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3905 | gen_rtx_SET (VOIDmode, mem, reg)); | |
823fbbce JDA |
3906 | } |
3907 | else | |
3908 | { | |
3909 | rtx meml = gen_rtx_MEM (SFmode, | |
3910 | plus_constant (base, offset)); | |
3911 | rtx memr = gen_rtx_MEM (SFmode, | |
3912 | plus_constant (base, offset + 4)); | |
3913 | rtx regl = gen_rtx_REG (SFmode, i); | |
3914 | rtx regr = gen_rtx_REG (SFmode, i + 1); | |
3915 | rtx setl = gen_rtx_SET (VOIDmode, meml, regl); | |
3916 | rtx setr = gen_rtx_SET (VOIDmode, memr, regr); | |
3917 | rtvec vec; | |
3918 | ||
3919 | RTX_FRAME_RELATED_P (setl) = 1; | |
3920 | RTX_FRAME_RELATED_P (setr) = 1; | |
3921 | vec = gen_rtvec (2, setl, setr); | |
bbbbb16a ILT |
3922 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3923 | gen_rtx_SEQUENCE (VOIDmode, vec)); | |
823fbbce | 3924 | } |
f6bcf44c JDA |
3925 | } |
3926 | offset += GET_MODE_SIZE (DFmode); | |
e63ffc38 JL |
3927 | fr_saved++; |
3928 | } | |
3929 | } | |
188538df TG |
3930 | } |
3931 | } | |
3932 | ||
19ec6a36 AM |
3933 | /* Emit RTL to load REG from the memory location specified by BASE+DISP. |
3934 | Handle case where DISP > 8k by using the add_high_const patterns. */ | |
3935 | ||
f6bcf44c | 3936 | static void |
a4295210 | 3937 | load_reg (int reg, HOST_WIDE_INT disp, int base) |
19ec6a36 | 3938 | { |
a4295210 JDA |
3939 | rtx dest = gen_rtx_REG (word_mode, reg); |
3940 | rtx basereg = gen_rtx_REG (Pmode, base); | |
3941 | rtx src; | |
19ec6a36 | 3942 | |
19ec6a36 | 3943 | if (VAL_14_BITS_P (disp)) |
a4295210 JDA |
3944 | src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
3945 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) | |
19ec6a36 | 3946 | { |
a4295210 JDA |
3947 | rtx delta = GEN_INT (disp); |
3948 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3949 | ||
3950 | emit_move_insn (tmpreg, delta); | |
3951 | if (TARGET_DISABLE_INDEXING) | |
3952 | { | |
3953 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
3954 | src = gen_rtx_MEM (word_mode, tmpreg); | |
3955 | } | |
3956 | else | |
3957 | src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
19ec6a36 AM |
3958 | } |
3959 | else | |
3960 | { | |
3961 | rtx delta = GEN_INT (disp); | |
3962 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3963 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
a4295210 | 3964 | |
19ec6a36 AM |
3965 | emit_move_insn (tmpreg, high); |
3966 | src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
19ec6a36 | 3967 | } |
a4295210 JDA |
3968 | |
3969 | emit_move_insn (dest, src); | |
19ec6a36 | 3970 | } |
aadcdb45 | 3971 | |
5fad1c24 JDA |
3972 | /* Update the total code bytes output to the text section. */ |
3973 | ||
3974 | static void | |
67b846fa | 3975 | update_total_code_bytes (unsigned int nbytes) |
5fad1c24 JDA |
3976 | { |
3977 | if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM) | |
62910663 | 3978 | && !IN_NAMED_SECTION_P (cfun->decl)) |
5fad1c24 | 3979 | { |
67b846fa | 3980 | unsigned int old_total = total_code_bytes; |
5fad1c24 | 3981 | |
67b846fa | 3982 | total_code_bytes += nbytes; |
5fad1c24 | 3983 | |
67b846fa JDA |
3984 | /* Be prepared to handle overflows. */ |
3985 | if (old_total > total_code_bytes) | |
3986 | total_code_bytes = UINT_MAX; | |
5fad1c24 JDA |
3987 | } |
3988 | } | |
3989 | ||
08c148a8 NB |
3990 | /* This function generates the assembly code for function exit. |
3991 | Args are as for output_function_prologue (). | |
3992 | ||
3993 | The function epilogue should not depend on the current stack | |
3994 | pointer! It should use the frame pointer only. This is mandatory | |
3995 | because of alloca; we also take advantage of it to omit stack | |
fe19a83d | 3996 | adjustments before returning. */ |
08c148a8 NB |
3997 | |
3998 | static void | |
b7849684 | 3999 | pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
188538df | 4000 | { |
08a2b118 RS |
4001 | rtx insn = get_last_insn (); |
4002 | ||
5fad1c24 JDA |
4003 | last_address = 0; |
4004 | ||
aadcdb45 JL |
4005 | /* hppa_expand_epilogue does the dirty work now. We just need |
4006 | to output the assembler directives which denote the end | |
08a2b118 RS |
4007 | of a function. |
4008 | ||
4009 | To make debuggers happy, emit a nop if the epilogue was completely | |
4010 | eliminated due to a volatile call as the last insn in the | |
23f6f34f | 4011 | current function. That way the return address (in %r2) will |
08a2b118 RS |
4012 | always point to a valid instruction in the current function. */ |
4013 | ||
4014 | /* Get the last real insn. */ | |
4015 | if (GET_CODE (insn) == NOTE) | |
4016 | insn = prev_real_insn (insn); | |
4017 | ||
4018 | /* If it is a sequence, then look inside. */ | |
4019 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
4020 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
4021 | ||
23f6f34f | 4022 | /* If insn is a CALL_INSN, then it must be a call to a volatile |
08a2b118 RS |
4023 | function (otherwise there would be epilogue insns). */ |
4024 | if (insn && GET_CODE (insn) == CALL_INSN) | |
17e6098e JDA |
4025 | { |
4026 | fputs ("\tnop\n", file); | |
4027 | last_address += 4; | |
4028 | } | |
23f6f34f | 4029 | |
e236a9ff | 4030 | fputs ("\t.EXIT\n\t.PROCEND\n", file); |
17e6098e | 4031 | |
9a55eab3 JDA |
4032 | if (TARGET_SOM && TARGET_GAS) |
4033 | { | |
4034 | /* We done with this subspace except possibly for some additional | |
4035 | debug information. Forget that we are in this subspace to ensure | |
4036 | that the next function is output in its own subspace. */ | |
d6b5193b | 4037 | in_section = NULL; |
1a83bfc3 | 4038 | cfun->machine->in_nsubspa = 2; |
9a55eab3 JDA |
4039 | } |
4040 | ||
5fad1c24 | 4041 | if (INSN_ADDRESSES_SET_P ()) |
17e6098e | 4042 | { |
5fad1c24 JDA |
4043 | insn = get_last_nonnote_insn (); |
4044 | last_address += INSN_ADDRESSES (INSN_UID (insn)); | |
4045 | if (INSN_P (insn)) | |
4046 | last_address += insn_default_length (insn); | |
4047 | last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) | |
4048 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
17e6098e | 4049 | } |
67b846fa JDA |
4050 | else |
4051 | last_address = UINT_MAX; | |
5fad1c24 JDA |
4052 | |
4053 | /* Finally, update the total number of code bytes output so far. */ | |
4054 | update_total_code_bytes (last_address); | |
aadcdb45 | 4055 | } |
4971c587 | 4056 | |
aadcdb45 | 4057 | void |
b7849684 | 4058 | hppa_expand_epilogue (void) |
aadcdb45 | 4059 | { |
23f6f34f | 4060 | rtx tmpreg; |
a4295210 JDA |
4061 | HOST_WIDE_INT offset; |
4062 | HOST_WIDE_INT ret_off = 0; | |
4063 | int i; | |
31d68947 | 4064 | int merge_sp_adjust_with_load = 0; |
aadcdb45 JL |
4065 | |
4066 | /* We will use this often. */ | |
690d4228 | 4067 | tmpreg = gen_rtx_REG (word_mode, 1); |
aadcdb45 JL |
4068 | |
4069 | /* Try to restore RP early to avoid load/use interlocks when | |
4070 | RP gets used in the return (bv) instruction. This appears to still | |
fe19a83d | 4071 | be necessary even when we schedule the prologue and epilogue. */ |
16c16a24 | 4072 | if (rp_saved) |
31d68947 AM |
4073 | { |
4074 | ret_off = TARGET_64BIT ? -16 : -20; | |
4075 | if (frame_pointer_needed) | |
4076 | { | |
f6bcf44c | 4077 | load_reg (2, ret_off, FRAME_POINTER_REGNUM); |
31d68947 AM |
4078 | ret_off = 0; |
4079 | } | |
4080 | else | |
4081 | { | |
4082 | /* No frame pointer, and stack is smaller than 8k. */ | |
4083 | if (VAL_14_BITS_P (ret_off - actual_fsize)) | |
4084 | { | |
f6bcf44c | 4085 | load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM); |
31d68947 AM |
4086 | ret_off = 0; |
4087 | } | |
4088 | } | |
4089 | } | |
aadcdb45 JL |
4090 | |
4091 | /* General register restores. */ | |
188538df TG |
4092 | if (frame_pointer_needed) |
4093 | { | |
823fbbce JDA |
4094 | offset = local_fsize; |
4095 | ||
4096 | /* If the current function calls __builtin_eh_return, then we need | |
4097 | to restore the saved EH data registers. */ | |
e3b5732b | 4098 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
823fbbce JDA |
4099 | { |
4100 | unsigned int i, regno; | |
4101 | ||
4102 | for (i = 0; ; ++i) | |
4103 | { | |
4104 | regno = EH_RETURN_DATA_REGNO (i); | |
4105 | if (regno == INVALID_REGNUM) | |
4106 | break; | |
4107 | ||
4108 | load_reg (regno, offset, FRAME_POINTER_REGNUM); | |
4109 | offset += UNITS_PER_WORD; | |
4110 | } | |
4111 | } | |
4112 | ||
4113 | for (i = 18; i >= 4; i--) | |
6fb5fa3c | 4114 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
188538df | 4115 | { |
f6bcf44c | 4116 | load_reg (i, offset, FRAME_POINTER_REGNUM); |
d7735a07 | 4117 | offset += UNITS_PER_WORD; |
188538df | 4118 | } |
188538df TG |
4119 | } |
4120 | else | |
4121 | { | |
823fbbce JDA |
4122 | offset = local_fsize - actual_fsize; |
4123 | ||
4124 | /* If the current function calls __builtin_eh_return, then we need | |
4125 | to restore the saved EH data registers. */ | |
e3b5732b | 4126 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
823fbbce JDA |
4127 | { |
4128 | unsigned int i, regno; | |
4129 | ||
4130 | for (i = 0; ; ++i) | |
4131 | { | |
4132 | regno = EH_RETURN_DATA_REGNO (i); | |
4133 | if (regno == INVALID_REGNUM) | |
4134 | break; | |
4135 | ||
4136 | /* Only for the first load. | |
4137 | merge_sp_adjust_with_load holds the register load | |
4138 | with which we will merge the sp adjustment. */ | |
4139 | if (merge_sp_adjust_with_load == 0 | |
4140 | && local_fsize == 0 | |
4141 | && VAL_14_BITS_P (-actual_fsize)) | |
4142 | merge_sp_adjust_with_load = regno; | |
4143 | else | |
4144 | load_reg (regno, offset, STACK_POINTER_REGNUM); | |
4145 | offset += UNITS_PER_WORD; | |
4146 | } | |
4147 | } | |
4148 | ||
4149 | for (i = 18; i >= 3; i--) | |
e63ffc38 | 4150 | { |
6fb5fa3c | 4151 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
e63ffc38 | 4152 | { |
e63ffc38 JL |
4153 | /* Only for the first load. |
4154 | merge_sp_adjust_with_load holds the register load | |
4155 | with which we will merge the sp adjustment. */ | |
31d68947 | 4156 | if (merge_sp_adjust_with_load == 0 |
e63ffc38 | 4157 | && local_fsize == 0 |
31d68947 | 4158 | && VAL_14_BITS_P (-actual_fsize)) |
e63ffc38 JL |
4159 | merge_sp_adjust_with_load = i; |
4160 | else | |
f6bcf44c | 4161 | load_reg (i, offset, STACK_POINTER_REGNUM); |
d7735a07 | 4162 | offset += UNITS_PER_WORD; |
e63ffc38 JL |
4163 | } |
4164 | } | |
188538df | 4165 | } |
aadcdb45 | 4166 | |
188538df TG |
4167 | /* Align pointer properly (doubleword boundary). */ |
4168 | offset = (offset + 7) & ~7; | |
4169 | ||
aadcdb45 | 4170 | /* FP register restores. */ |
188538df | 4171 | if (save_fregs) |
188538df | 4172 | { |
aadcdb45 | 4173 | /* Adjust the register to index off of. */ |
2b41935c | 4174 | if (frame_pointer_needed) |
823fbbce | 4175 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); |
2b41935c | 4176 | else |
823fbbce | 4177 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); |
aadcdb45 JL |
4178 | |
4179 | /* Actually do the restores now. */ | |
88624c0e | 4180 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
6fb5fa3c DB |
4181 | if (df_regs_ever_live_p (i) |
4182 | || (! TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
19ec6a36 AM |
4183 | { |
4184 | rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); | |
4185 | rtx dest = gen_rtx_REG (DFmode, i); | |
f6bcf44c | 4186 | emit_move_insn (dest, src); |
19ec6a36 | 4187 | } |
188538df | 4188 | } |
aadcdb45 | 4189 | |
1144563f JL |
4190 | /* Emit a blockage insn here to keep these insns from being moved to |
4191 | an earlier spot in the epilogue, or into the main instruction stream. | |
4192 | ||
4193 | This is necessary as we must not cut the stack back before all the | |
4194 | restores are finished. */ | |
4195 | emit_insn (gen_blockage ()); | |
aadcdb45 | 4196 | |
6619e96c | 4197 | /* Reset stack pointer (and possibly frame pointer). The stack |
68944452 | 4198 | pointer is initially set to fp + 64 to avoid a race condition. */ |
31d68947 | 4199 | if (frame_pointer_needed) |
188538df | 4200 | { |
19ec6a36 | 4201 | rtx delta = GEN_INT (-64); |
823fbbce JDA |
4202 | |
4203 | set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0); | |
4204 | emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta)); | |
188538df | 4205 | } |
aadcdb45 | 4206 | /* If we were deferring a callee register restore, do it now. */ |
31d68947 AM |
4207 | else if (merge_sp_adjust_with_load) |
4208 | { | |
4209 | rtx delta = GEN_INT (-actual_fsize); | |
19ec6a36 | 4210 | rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load); |
823fbbce JDA |
4211 | |
4212 | emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)); | |
31d68947 | 4213 | } |
aadcdb45 | 4214 | else if (actual_fsize != 0) |
823fbbce JDA |
4215 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
4216 | - actual_fsize, 0); | |
31d68947 AM |
4217 | |
4218 | /* If we haven't restored %r2 yet (no frame pointer, and a stack | |
4219 | frame greater than 8k), do so now. */ | |
4220 | if (ret_off != 0) | |
f6bcf44c | 4221 | load_reg (2, ret_off, STACK_POINTER_REGNUM); |
823fbbce | 4222 | |
e3b5732b | 4223 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
823fbbce JDA |
4224 | { |
4225 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
4226 | ||
4227 | emit_insn (gen_blockage ()); | |
4228 | emit_insn (TARGET_64BIT | |
4229 | ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa) | |
4230 | : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa)); | |
4231 | } | |
188538df TG |
4232 | } |
4233 | ||
d777856d | 4234 | rtx |
b7849684 | 4235 | hppa_pic_save_rtx (void) |
824e7605 | 4236 | { |
d777856d | 4237 | return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM); |
1c7a8112 AM |
4238 | } |
4239 | ||
3674b34d JDA |
4240 | #ifndef NO_DEFERRED_PROFILE_COUNTERS |
4241 | #define NO_DEFERRED_PROFILE_COUNTERS 0 | |
4242 | #endif | |
4243 | ||
3674b34d JDA |
4244 | |
4245 | /* Vector of funcdef numbers. */ | |
4246 | static VEC(int,heap) *funcdef_nos; | |
4247 | ||
4248 | /* Output deferred profile counters. */ | |
4249 | static void | |
4250 | output_deferred_profile_counters (void) | |
4251 | { | |
4252 | unsigned int i; | |
4253 | int align, n; | |
4254 | ||
4255 | if (VEC_empty (int, funcdef_nos)) | |
4256 | return; | |
4257 | ||
d6b5193b | 4258 | switch_to_section (data_section); |
3674b34d JDA |
4259 | align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE); |
4260 | ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT)); | |
4261 | ||
4262 | for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++) | |
4263 | { | |
4264 | targetm.asm_out.internal_label (asm_out_file, "LP", n); | |
4265 | assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1); | |
4266 | } | |
4267 | ||
4268 | VEC_free (int, heap, funcdef_nos); | |
4269 | } | |
4270 | ||
1c7a8112 | 4271 | void |
b7849684 | 4272 | hppa_profile_hook (int label_no) |
1c7a8112 | 4273 | { |
a3d4c92f RC |
4274 | /* We use SImode for the address of the function in both 32 and |
4275 | 64-bit code to avoid having to provide DImode versions of the | |
4276 | lcla2 and load_offset_label_address insn patterns. */ | |
4277 | rtx reg = gen_reg_rtx (SImode); | |
4278 | rtx label_rtx = gen_label_rtx (); | |
8f949e7e JDA |
4279 | rtx begin_label_rtx, call_insn; |
4280 | char begin_label_name[16]; | |
1c7a8112 | 4281 | |
8f949e7e | 4282 | ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL, |
f6f315fe | 4283 | label_no); |
a3d4c92f | 4284 | begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name)); |
1c7a8112 AM |
4285 | |
4286 | if (TARGET_64BIT) | |
4287 | emit_move_insn (arg_pointer_rtx, | |
4288 | gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, | |
4289 | GEN_INT (64))); | |
4290 | ||
1c7a8112 AM |
4291 | emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2)); |
4292 | ||
110abdbc | 4293 | /* The address of the function is loaded into %r25 with an instruction- |
a3d4c92f RC |
4294 | relative sequence that avoids the use of relocations. The sequence |
4295 | is split so that the load_offset_label_address instruction can | |
4296 | occupy the delay slot of the call to _mcount. */ | |
4297 | if (TARGET_PA_20) | |
4298 | emit_insn (gen_lcla2 (reg, label_rtx)); | |
4299 | else | |
4300 | emit_insn (gen_lcla1 (reg, label_rtx)); | |
4301 | ||
4302 | emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25), | |
4303 | reg, begin_label_rtx, label_rtx)); | |
4304 | ||
3674b34d | 4305 | #if !NO_DEFERRED_PROFILE_COUNTERS |
1c7a8112 AM |
4306 | { |
4307 | rtx count_label_rtx, addr, r24; | |
8f949e7e | 4308 | char count_label_name[16]; |
1c7a8112 | 4309 | |
3674b34d | 4310 | VEC_safe_push (int, heap, funcdef_nos, label_no); |
8f949e7e JDA |
4311 | ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no); |
4312 | count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name)); | |
1c7a8112 | 4313 | |
bdad4be5 | 4314 | addr = force_reg (Pmode, count_label_rtx); |
1c7a8112 AM |
4315 | r24 = gen_rtx_REG (Pmode, 24); |
4316 | emit_move_insn (r24, addr); | |
4317 | ||
1c7a8112 | 4318 | call_insn = |
a3d4c92f RC |
4319 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4320 | gen_rtx_SYMBOL_REF (Pmode, | |
4321 | "_mcount")), | |
4322 | GEN_INT (TARGET_64BIT ? 24 : 12))); | |
1c7a8112 AM |
4323 | |
4324 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24); | |
4325 | } | |
4326 | #else | |
a3d4c92f | 4327 | |
1c7a8112 | 4328 | call_insn = |
a3d4c92f RC |
4329 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4330 | gen_rtx_SYMBOL_REF (Pmode, | |
4331 | "_mcount")), | |
4332 | GEN_INT (TARGET_64BIT ? 16 : 8))); | |
4333 | ||
1c7a8112 AM |
4334 | #endif |
4335 | ||
a3d4c92f RC |
4336 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25)); |
4337 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26)); | |
4338 | ||
1c7a8112 AM |
4339 | /* Indicate the _mcount call cannot throw, nor will it execute a |
4340 | non-local goto. */ | |
bbbbb16a | 4341 | add_reg_note (call_insn, REG_EH_REGION, constm1_rtx); |
824e7605 AM |
4342 | } |
4343 | ||
e99d6592 MS |
4344 | /* Fetch the return address for the frame COUNT steps up from |
4345 | the current frame, after the prologue. FRAMEADDR is the | |
4346 | frame pointer of the COUNT frame. | |
4347 | ||
cf3735b8 JDA |
4348 | We want to ignore any export stub remnants here. To handle this, |
4349 | we examine the code at the return address, and if it is an export | |
4350 | stub, we return a memory rtx for the stub return address stored | |
4351 | at frame-24. | |
c28eb6c2 JL |
4352 | |
4353 | The value returned is used in two different ways: | |
4354 | ||
4355 | 1. To find a function's caller. | |
4356 | ||
4357 | 2. To change the return address for a function. | |
4358 | ||
4359 | This function handles most instances of case 1; however, it will | |
4360 | fail if there are two levels of stubs to execute on the return | |
4361 | path. The only way I believe that can happen is if the return value | |
4362 | needs a parameter relocation, which never happens for C code. | |
4363 | ||
4364 | This function handles most instances of case 2; however, it will | |
4365 | fail if we did not originally have stub code on the return path | |
cf3735b8 | 4366 | but will need stub code on the new return path. This can happen if |
c28eb6c2 | 4367 | the caller & callee are both in the main program, but the new |
cf3735b8 | 4368 | return location is in a shared library. */ |
e99d6592 MS |
4369 | |
4370 | rtx | |
b7849684 | 4371 | return_addr_rtx (int count, rtx frameaddr) |
e99d6592 MS |
4372 | { |
4373 | rtx label; | |
cf3735b8 | 4374 | rtx rp; |
e99d6592 MS |
4375 | rtx saved_rp; |
4376 | rtx ins; | |
4377 | ||
f90b7a5a PB |
4378 | /* Instruction stream at the normal return address for the export stub: |
4379 | ||
4380 | 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp | |
4381 | 0x004010a1 | stub+12: ldsid (sr0,rp),r1 | |
4382 | 0x00011820 | stub+16: mtsp r1,sr0 | |
4383 | 0xe0400002 | stub+20: be,n 0(sr0,rp) | |
4384 | ||
4385 | 0xe0400002 must be specified as -532676606 so that it won't be | |
4386 | rejected as an invalid immediate operand on 64-bit hosts. */ | |
4387 | ||
4388 | HOST_WIDE_INT insns[4] = {0x4bc23fd1, 0x004010a1, 0x00011820, -532676606}; | |
4389 | int i; | |
4390 | ||
cf3735b8 JDA |
4391 | if (count != 0) |
4392 | return NULL_RTX; | |
a7721dc0 | 4393 | |
cf3735b8 | 4394 | rp = get_hard_reg_initial_val (Pmode, 2); |
e99d6592 | 4395 | |
cf3735b8 JDA |
4396 | if (TARGET_64BIT || TARGET_NO_SPACE_REGS) |
4397 | return rp; | |
e99d6592 | 4398 | |
f90b7a5a PB |
4399 | /* If there is no export stub then just use the value saved from |
4400 | the return pointer register. */ | |
4401 | ||
a7721dc0 | 4402 | saved_rp = gen_reg_rtx (Pmode); |
cf3735b8 | 4403 | emit_move_insn (saved_rp, rp); |
e99d6592 MS |
4404 | |
4405 | /* Get pointer to the instruction stream. We have to mask out the | |
4406 | privilege level from the two low order bits of the return address | |
4407 | pointer here so that ins will point to the start of the first | |
4408 | instruction that would have been executed if we returned. */ | |
cf3735b8 | 4409 | ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR)); |
e99d6592 MS |
4410 | label = gen_label_rtx (); |
4411 | ||
4412 | /* Check the instruction stream at the normal return address for the | |
f90b7a5a PB |
4413 | export stub. If it is an export stub, than our return address is |
4414 | really in -24[frameaddr]. */ | |
e99d6592 | 4415 | |
f90b7a5a PB |
4416 | for (i = 0; i < 3; i++) |
4417 | { | |
4418 | rtx op0 = gen_rtx_MEM (SImode, plus_constant (ins, i * 4)); | |
4419 | rtx op1 = GEN_INT (insns[i]); | |
4420 | emit_cmp_and_jump_insns (op0, op1, NE, NULL, SImode, 0, label); | |
4421 | } | |
e99d6592 | 4422 | |
cf3735b8 | 4423 | /* Here we know that our return address points to an export |
e99d6592 | 4424 | stub. We don't want to return the address of the export stub, |
cf3735b8 JDA |
4425 | but rather the return address of the export stub. That return |
4426 | address is stored at -24[frameaddr]. */ | |
e99d6592 | 4427 | |
cf3735b8 JDA |
4428 | emit_move_insn (saved_rp, |
4429 | gen_rtx_MEM (Pmode, | |
4430 | memory_address (Pmode, | |
4431 | plus_constant (frameaddr, | |
4432 | -24)))); | |
e99d6592 MS |
4433 | |
4434 | emit_label (label); | |
f90b7a5a | 4435 | |
cf3735b8 | 4436 | return saved_rp; |
e99d6592 MS |
4437 | } |
4438 | ||
188538df | 4439 | void |
f90b7a5a | 4440 | emit_bcond_fp (rtx operands[]) |
188538df | 4441 | { |
f90b7a5a PB |
4442 | enum rtx_code code = GET_CODE (operands[0]); |
4443 | rtx operand0 = operands[1]; | |
4444 | rtx operand1 = operands[2]; | |
4445 | rtx label = operands[3]; | |
4446 | ||
4447 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0), | |
4448 | gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1))); | |
4449 | ||
ad2c71b7 JL |
4450 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, |
4451 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
f90b7a5a | 4452 | gen_rtx_fmt_ee (NE, |
ad2c71b7 JL |
4453 | VOIDmode, |
4454 | gen_rtx_REG (CCFPmode, 0), | |
4455 | const0_rtx), | |
f90b7a5a | 4456 | gen_rtx_LABEL_REF (VOIDmode, label), |
ad2c71b7 | 4457 | pc_rtx))); |
188538df TG |
4458 | |
4459 | } | |
4460 | ||
780f491f TG |
4461 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
4462 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4463 | ||
c237e94a | 4464 | static int |
b7849684 | 4465 | pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
780f491f | 4466 | { |
b09fa787 JL |
4467 | enum attr_type attr_type; |
4468 | ||
5d50fab3 JL |
4469 | /* Don't adjust costs for a pa8000 chip, also do not adjust any |
4470 | true dependencies as they are described with bypasses now. */ | |
4471 | if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0) | |
86001391 JQ |
4472 | return cost; |
4473 | ||
e150ae4f TG |
4474 | if (! recog_memoized (insn)) |
4475 | return 0; | |
780f491f | 4476 | |
b09fa787 JL |
4477 | attr_type = get_attr_type (insn); |
4478 | ||
144d51f9 | 4479 | switch (REG_NOTE_KIND (link)) |
780f491f | 4480 | { |
144d51f9 | 4481 | case REG_DEP_ANTI: |
780f491f TG |
4482 | /* Anti dependency; DEP_INSN reads a register that INSN writes some |
4483 | cycles later. */ | |
4484 | ||
b09fa787 | 4485 | if (attr_type == TYPE_FPLOAD) |
780f491f | 4486 | { |
e150ae4f TG |
4487 | rtx pat = PATTERN (insn); |
4488 | rtx dep_pat = PATTERN (dep_insn); | |
4489 | if (GET_CODE (pat) == PARALLEL) | |
4490 | { | |
4491 | /* This happens for the fldXs,mb patterns. */ | |
4492 | pat = XVECEXP (pat, 0, 0); | |
4493 | } | |
4494 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
780f491f | 4495 | /* If this happens, we have to extend this to schedule |
e150ae4f TG |
4496 | optimally. Return 0 for now. */ |
4497 | return 0; | |
780f491f | 4498 | |
e150ae4f | 4499 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) |
780f491f | 4500 | { |
e150ae4f TG |
4501 | if (! recog_memoized (dep_insn)) |
4502 | return 0; | |
780f491f TG |
4503 | switch (get_attr_type (dep_insn)) |
4504 | { | |
4505 | case TYPE_FPALU: | |
c47decad JL |
4506 | case TYPE_FPMULSGL: |
4507 | case TYPE_FPMULDBL: | |
780f491f TG |
4508 | case TYPE_FPDIVSGL: |
4509 | case TYPE_FPDIVDBL: | |
4510 | case TYPE_FPSQRTSGL: | |
4511 | case TYPE_FPSQRTDBL: | |
e150ae4f | 4512 | /* A fpload can't be issued until one cycle before a |
ddd5a7c1 | 4513 | preceding arithmetic operation has finished if |
e150ae4f TG |
4514 | the target of the fpload is any of the sources |
4515 | (or destination) of the arithmetic operation. */ | |
5d50fab3 | 4516 | return insn_default_latency (dep_insn) - 1; |
c47decad JL |
4517 | |
4518 | default: | |
4519 | return 0; | |
4520 | } | |
4521 | } | |
4522 | } | |
b09fa787 | 4523 | else if (attr_type == TYPE_FPALU) |
c47decad JL |
4524 | { |
4525 | rtx pat = PATTERN (insn); | |
4526 | rtx dep_pat = PATTERN (dep_insn); | |
4527 | if (GET_CODE (pat) == PARALLEL) | |
4528 | { | |
4529 | /* This happens for the fldXs,mb patterns. */ | |
4530 | pat = XVECEXP (pat, 0, 0); | |
4531 | } | |
4532 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4533 | /* If this happens, we have to extend this to schedule | |
4534 | optimally. Return 0 for now. */ | |
4535 | return 0; | |
4536 | ||
4537 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) | |
4538 | { | |
4539 | if (! recog_memoized (dep_insn)) | |
4540 | return 0; | |
4541 | switch (get_attr_type (dep_insn)) | |
4542 | { | |
4543 | case TYPE_FPDIVSGL: | |
4544 | case TYPE_FPDIVDBL: | |
4545 | case TYPE_FPSQRTSGL: | |
4546 | case TYPE_FPSQRTDBL: | |
4547 | /* An ALU flop can't be issued until two cycles before a | |
ddd5a7c1 | 4548 | preceding divide or sqrt operation has finished if |
c47decad JL |
4549 | the target of the ALU flop is any of the sources |
4550 | (or destination) of the divide or sqrt operation. */ | |
5d50fab3 | 4551 | return insn_default_latency (dep_insn) - 2; |
780f491f TG |
4552 | |
4553 | default: | |
4554 | return 0; | |
4555 | } | |
4556 | } | |
4557 | } | |
4558 | ||
4559 | /* For other anti dependencies, the cost is 0. */ | |
4560 | return 0; | |
144d51f9 NS |
4561 | |
4562 | case REG_DEP_OUTPUT: | |
c47decad JL |
4563 | /* Output dependency; DEP_INSN writes a register that INSN writes some |
4564 | cycles later. */ | |
b09fa787 | 4565 | if (attr_type == TYPE_FPLOAD) |
c47decad JL |
4566 | { |
4567 | rtx pat = PATTERN (insn); | |
4568 | rtx dep_pat = PATTERN (dep_insn); | |
4569 | if (GET_CODE (pat) == PARALLEL) | |
4570 | { | |
4571 | /* This happens for the fldXs,mb patterns. */ | |
4572 | pat = XVECEXP (pat, 0, 0); | |
4573 | } | |
4574 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4575 | /* If this happens, we have to extend this to schedule | |
4576 | optimally. Return 0 for now. */ | |
4577 | return 0; | |
4578 | ||
4579 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4580 | { | |
4581 | if (! recog_memoized (dep_insn)) | |
4582 | return 0; | |
4583 | switch (get_attr_type (dep_insn)) | |
4584 | { | |
4585 | case TYPE_FPALU: | |
4586 | case TYPE_FPMULSGL: | |
4587 | case TYPE_FPMULDBL: | |
4588 | case TYPE_FPDIVSGL: | |
4589 | case TYPE_FPDIVDBL: | |
4590 | case TYPE_FPSQRTSGL: | |
4591 | case TYPE_FPSQRTDBL: | |
4592 | /* A fpload can't be issued until one cycle before a | |
ddd5a7c1 | 4593 | preceding arithmetic operation has finished if |
c47decad | 4594 | the target of the fpload is the destination of the |
fae15c93 VM |
4595 | arithmetic operation. |
4596 | ||
4597 | Exception: For PA7100LC, PA7200 and PA7300, the cost | |
4598 | is 3 cycles, unless they bundle together. We also | |
4599 | pay the penalty if the second insn is a fpload. */ | |
5d50fab3 | 4600 | return insn_default_latency (dep_insn) - 1; |
780f491f | 4601 | |
c47decad JL |
4602 | default: |
4603 | return 0; | |
4604 | } | |
4605 | } | |
4606 | } | |
b09fa787 | 4607 | else if (attr_type == TYPE_FPALU) |
c47decad JL |
4608 | { |
4609 | rtx pat = PATTERN (insn); | |
4610 | rtx dep_pat = PATTERN (dep_insn); | |
4611 | if (GET_CODE (pat) == PARALLEL) | |
4612 | { | |
4613 | /* This happens for the fldXs,mb patterns. */ | |
4614 | pat = XVECEXP (pat, 0, 0); | |
4615 | } | |
4616 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4617 | /* If this happens, we have to extend this to schedule | |
4618 | optimally. Return 0 for now. */ | |
4619 | return 0; | |
4620 | ||
4621 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4622 | { | |
4623 | if (! recog_memoized (dep_insn)) | |
4624 | return 0; | |
4625 | switch (get_attr_type (dep_insn)) | |
4626 | { | |
4627 | case TYPE_FPDIVSGL: | |
4628 | case TYPE_FPDIVDBL: | |
4629 | case TYPE_FPSQRTSGL: | |
4630 | case TYPE_FPSQRTDBL: | |
4631 | /* An ALU flop can't be issued until two cycles before a | |
ddd5a7c1 | 4632 | preceding divide or sqrt operation has finished if |
c47decad | 4633 | the target of the ALU flop is also the target of |
38e01259 | 4634 | the divide or sqrt operation. */ |
5d50fab3 | 4635 | return insn_default_latency (dep_insn) - 2; |
c47decad JL |
4636 | |
4637 | default: | |
4638 | return 0; | |
4639 | } | |
4640 | } | |
4641 | } | |
4642 | ||
4643 | /* For other output dependencies, the cost is 0. */ | |
4644 | return 0; | |
144d51f9 NS |
4645 | |
4646 | default: | |
4647 | gcc_unreachable (); | |
c47decad | 4648 | } |
780f491f | 4649 | } |
188538df | 4650 | |
c237e94a ZW |
4651 | /* Adjust scheduling priorities. We use this to try and keep addil |
4652 | and the next use of %r1 close together. */ | |
4653 | static int | |
b7849684 | 4654 | pa_adjust_priority (rtx insn, int priority) |
c237e94a ZW |
4655 | { |
4656 | rtx set = single_set (insn); | |
4657 | rtx src, dest; | |
4658 | if (set) | |
4659 | { | |
4660 | src = SET_SRC (set); | |
4661 | dest = SET_DEST (set); | |
4662 | if (GET_CODE (src) == LO_SUM | |
4663 | && symbolic_operand (XEXP (src, 1), VOIDmode) | |
4664 | && ! read_only_operand (XEXP (src, 1), VOIDmode)) | |
4665 | priority >>= 3; | |
4666 | ||
4667 | else if (GET_CODE (src) == MEM | |
4668 | && GET_CODE (XEXP (src, 0)) == LO_SUM | |
4669 | && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode) | |
4670 | && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode)) | |
4671 | priority >>= 1; | |
4672 | ||
4673 | else if (GET_CODE (dest) == MEM | |
4674 | && GET_CODE (XEXP (dest, 0)) == LO_SUM | |
4675 | && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode) | |
4676 | && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)) | |
4677 | priority >>= 3; | |
4678 | } | |
4679 | return priority; | |
4680 | } | |
4681 | ||
4682 | /* The 700 can only issue a single insn at a time. | |
4683 | The 7XXX processors can issue two insns at a time. | |
4684 | The 8000 can issue 4 insns at a time. */ | |
4685 | static int | |
b7849684 | 4686 | pa_issue_rate (void) |
c237e94a ZW |
4687 | { |
4688 | switch (pa_cpu) | |
4689 | { | |
4690 | case PROCESSOR_700: return 1; | |
4691 | case PROCESSOR_7100: return 2; | |
4692 | case PROCESSOR_7100LC: return 2; | |
4693 | case PROCESSOR_7200: return 2; | |
fae15c93 | 4694 | case PROCESSOR_7300: return 2; |
c237e94a ZW |
4695 | case PROCESSOR_8000: return 4; |
4696 | ||
4697 | default: | |
144d51f9 | 4698 | gcc_unreachable (); |
c237e94a ZW |
4699 | } |
4700 | } | |
4701 | ||
4702 | ||
4703 | ||
3673e996 | 4704 | /* Return any length adjustment needed by INSN which already has its length |
23f6f34f | 4705 | computed as LENGTH. Return zero if no adjustment is necessary. |
3673e996 | 4706 | |
b9821af8 | 4707 | For the PA: function calls, millicode calls, and backwards short |
23f6f34f | 4708 | conditional branches with unfilled delay slots need an adjustment by +1 |
b9821af8 | 4709 | (to account for the NOP which will be inserted into the instruction stream). |
3673e996 RS |
4710 | |
4711 | Also compute the length of an inline block move here as it is too | |
b9821af8 | 4712 | complicated to express as a length attribute in pa.md. */ |
3673e996 | 4713 | int |
b7849684 | 4714 | pa_adjust_insn_length (rtx insn, int length) |
3673e996 RS |
4715 | { |
4716 | rtx pat = PATTERN (insn); | |
4717 | ||
32562302 JDA |
4718 | /* Jumps inside switch tables which have unfilled delay slots need |
4719 | adjustment. */ | |
4720 | if (GET_CODE (insn) == JUMP_INSN | |
cb4d476c JDA |
4721 | && GET_CODE (pat) == PARALLEL |
4722 | && get_attr_type (insn) == TYPE_BTABLE_BRANCH) | |
746a9efa | 4723 | return 4; |
3673e996 RS |
4724 | /* Millicode insn with an unfilled delay slot. */ |
4725 | else if (GET_CODE (insn) == INSN | |
4726 | && GET_CODE (pat) != SEQUENCE | |
4727 | && GET_CODE (pat) != USE | |
4728 | && GET_CODE (pat) != CLOBBER | |
4729 | && get_attr_type (insn) == TYPE_MILLI) | |
a1b36964 | 4730 | return 4; |
3673e996 RS |
4731 | /* Block move pattern. */ |
4732 | else if (GET_CODE (insn) == INSN | |
4733 | && GET_CODE (pat) == PARALLEL | |
4096479e | 4734 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET |
3673e996 RS |
4735 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM |
4736 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM | |
4737 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode | |
4738 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode) | |
70128ad9 | 4739 | return compute_movmem_length (insn) - 4; |
cdc9103c JDA |
4740 | /* Block clear pattern. */ |
4741 | else if (GET_CODE (insn) == INSN | |
4742 | && GET_CODE (pat) == PARALLEL | |
4743 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET | |
4744 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM | |
4745 | && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx | |
4746 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode) | |
70128ad9 | 4747 | return compute_clrmem_length (insn) - 4; |
3673e996 | 4748 | /* Conditional branch with an unfilled delay slot. */ |
b9821af8 JL |
4749 | else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn)) |
4750 | { | |
4751 | /* Adjust a short backwards conditional with an unfilled delay slot. */ | |
4752 | if (GET_CODE (pat) == SET | |
a1b36964 | 4753 | && length == 4 |
b9821af8 | 4754 | && ! forward_branch_p (insn)) |
a1b36964 | 4755 | return 4; |
b1092901 JL |
4756 | else if (GET_CODE (pat) == PARALLEL |
4757 | && get_attr_type (insn) == TYPE_PARALLEL_BRANCH | |
4758 | && length == 4) | |
4759 | return 4; | |
b9821af8 | 4760 | /* Adjust dbra insn with short backwards conditional branch with |
23f6f34f | 4761 | unfilled delay slot -- only for case where counter is in a |
fe19a83d | 4762 | general register register. */ |
b9821af8 JL |
4763 | else if (GET_CODE (pat) == PARALLEL |
4764 | && GET_CODE (XVECEXP (pat, 0, 1)) == SET | |
4765 | && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG | |
23f6f34f | 4766 | && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0)) |
a1b36964 | 4767 | && length == 4 |
b9821af8 | 4768 | && ! forward_branch_p (insn)) |
a1b36964 | 4769 | return 4; |
b9821af8 JL |
4770 | else |
4771 | return 0; | |
4772 | } | |
b1092901 | 4773 | return 0; |
3673e996 RS |
4774 | } |
4775 | ||
188538df TG |
4776 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
4777 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
4778 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
4779 | ||
4780 | void | |
b7849684 | 4781 | print_operand (FILE *file, rtx x, int code) |
188538df TG |
4782 | { |
4783 | switch (code) | |
4784 | { | |
4785 | case '#': | |
4786 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
4787 | if (dbr_sequence_length () == 0) | |
4788 | fputs ("\n\tnop", file); | |
4789 | return; | |
4790 | case '*': | |
5bdc5878 | 4791 | /* Output a nullification completer if there's nothing for the */ |
23f6f34f | 4792 | /* delay slot or nullification is requested. */ |
188538df TG |
4793 | if (dbr_sequence_length () == 0 || |
4794 | (final_sequence && | |
4795 | INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))) | |
4796 | fputs (",n", file); | |
4797 | return; | |
4798 | case 'R': | |
4799 | /* Print out the second register name of a register pair. | |
4800 | I.e., R (6) => 7. */ | |
831c1763 | 4801 | fputs (reg_names[REGNO (x) + 1], file); |
188538df TG |
4802 | return; |
4803 | case 'r': | |
fe19a83d | 4804 | /* A register or zero. */ |
f048ca47 JL |
4805 | if (x == const0_rtx |
4806 | || (x == CONST0_RTX (DFmode)) | |
4807 | || (x == CONST0_RTX (SFmode))) | |
188538df | 4808 | { |
55abf18a JL |
4809 | fputs ("%r0", file); |
4810 | return; | |
4811 | } | |
4812 | else | |
4813 | break; | |
4814 | case 'f': | |
fe19a83d | 4815 | /* A register or zero (floating point). */ |
55abf18a JL |
4816 | if (x == const0_rtx |
4817 | || (x == CONST0_RTX (DFmode)) | |
4818 | || (x == CONST0_RTX (SFmode))) | |
4819 | { | |
4820 | fputs ("%fr0", file); | |
188538df TG |
4821 | return; |
4822 | } | |
4823 | else | |
4824 | break; | |
f8eb41cc JL |
4825 | case 'A': |
4826 | { | |
4827 | rtx xoperands[2]; | |
4828 | ||
4829 | xoperands[0] = XEXP (XEXP (x, 0), 0); | |
4830 | xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0); | |
4831 | output_global_address (file, xoperands[1], 0); | |
4832 | fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]); | |
4833 | return; | |
4834 | } | |
4835 | ||
c85b8963 | 4836 | case 'C': /* Plain (C)ondition */ |
188538df TG |
4837 | case 'X': |
4838 | switch (GET_CODE (x)) | |
23f6f34f | 4839 | { |
188538df | 4840 | case EQ: |
e236a9ff | 4841 | fputs ("=", file); break; |
188538df | 4842 | case NE: |
e236a9ff | 4843 | fputs ("<>", file); break; |
188538df | 4844 | case GT: |
e236a9ff | 4845 | fputs (">", file); break; |
188538df | 4846 | case GE: |
e236a9ff | 4847 | fputs (">=", file); break; |
188538df | 4848 | case GEU: |
e236a9ff | 4849 | fputs (">>=", file); break; |
188538df | 4850 | case GTU: |
e236a9ff | 4851 | fputs (">>", file); break; |
188538df | 4852 | case LT: |
e236a9ff | 4853 | fputs ("<", file); break; |
188538df | 4854 | case LE: |
e236a9ff | 4855 | fputs ("<=", file); break; |
188538df | 4856 | case LEU: |
e236a9ff | 4857 | fputs ("<<=", file); break; |
188538df | 4858 | case LTU: |
e236a9ff | 4859 | fputs ("<<", file); break; |
188538df | 4860 | default: |
144d51f9 | 4861 | gcc_unreachable (); |
188538df TG |
4862 | } |
4863 | return; | |
c85b8963 | 4864 | case 'N': /* Condition, (N)egated */ |
188538df TG |
4865 | switch (GET_CODE (x)) |
4866 | { | |
4867 | case EQ: | |
e236a9ff | 4868 | fputs ("<>", file); break; |
188538df | 4869 | case NE: |
e236a9ff | 4870 | fputs ("=", file); break; |
188538df | 4871 | case GT: |
e236a9ff | 4872 | fputs ("<=", file); break; |
188538df | 4873 | case GE: |
e236a9ff | 4874 | fputs ("<", file); break; |
188538df | 4875 | case GEU: |
e236a9ff | 4876 | fputs ("<<", file); break; |
188538df | 4877 | case GTU: |
e236a9ff | 4878 | fputs ("<<=", file); break; |
188538df | 4879 | case LT: |
e236a9ff | 4880 | fputs (">=", file); break; |
188538df | 4881 | case LE: |
e236a9ff | 4882 | fputs (">", file); break; |
188538df | 4883 | case LEU: |
e236a9ff | 4884 | fputs (">>", file); break; |
188538df | 4885 | case LTU: |
e236a9ff | 4886 | fputs (">>=", file); break; |
188538df | 4887 | default: |
144d51f9 | 4888 | gcc_unreachable (); |
188538df TG |
4889 | } |
4890 | return; | |
831c1763 | 4891 | /* For floating point comparisons. Note that the output |
69049ba0 JDA |
4892 | predicates are the complement of the desired mode. The |
4893 | conditions for GT, GE, LT, LE and LTGT cause an invalid | |
4894 | operation exception if the result is unordered and this | |
4895 | exception is enabled in the floating-point status register. */ | |
d6c0d377 JL |
4896 | case 'Y': |
4897 | switch (GET_CODE (x)) | |
4898 | { | |
4899 | case EQ: | |
e236a9ff | 4900 | fputs ("!=", file); break; |
d6c0d377 | 4901 | case NE: |
e236a9ff | 4902 | fputs ("=", file); break; |
d6c0d377 | 4903 | case GT: |
becf1647 | 4904 | fputs ("!>", file); break; |
d6c0d377 | 4905 | case GE: |
becf1647 | 4906 | fputs ("!>=", file); break; |
d6c0d377 | 4907 | case LT: |
becf1647 | 4908 | fputs ("!<", file); break; |
d6c0d377 | 4909 | case LE: |
becf1647 DA |
4910 | fputs ("!<=", file); break; |
4911 | case LTGT: | |
4912 | fputs ("!<>", file); break; | |
4913 | case UNLE: | |
69049ba0 | 4914 | fputs ("!?<=", file); break; |
becf1647 | 4915 | case UNLT: |
69049ba0 | 4916 | fputs ("!?<", file); break; |
becf1647 | 4917 | case UNGE: |
69049ba0 | 4918 | fputs ("!?>=", file); break; |
becf1647 | 4919 | case UNGT: |
69049ba0 | 4920 | fputs ("!?>", file); break; |
becf1647 | 4921 | case UNEQ: |
69049ba0 | 4922 | fputs ("!?=", file); break; |
becf1647 | 4923 | case UNORDERED: |
69049ba0 | 4924 | fputs ("!?", file); break; |
becf1647 | 4925 | case ORDERED: |
69049ba0 | 4926 | fputs ("?", file); break; |
d6c0d377 | 4927 | default: |
144d51f9 | 4928 | gcc_unreachable (); |
d6c0d377 JL |
4929 | } |
4930 | return; | |
c85b8963 TG |
4931 | case 'S': /* Condition, operands are (S)wapped. */ |
4932 | switch (GET_CODE (x)) | |
4933 | { | |
4934 | case EQ: | |
e236a9ff | 4935 | fputs ("=", file); break; |
c85b8963 | 4936 | case NE: |
e236a9ff | 4937 | fputs ("<>", file); break; |
c85b8963 | 4938 | case GT: |
e236a9ff | 4939 | fputs ("<", file); break; |
c85b8963 | 4940 | case GE: |
e236a9ff | 4941 | fputs ("<=", file); break; |
c85b8963 | 4942 | case GEU: |
e236a9ff | 4943 | fputs ("<<=", file); break; |
c85b8963 | 4944 | case GTU: |
e236a9ff | 4945 | fputs ("<<", file); break; |
c85b8963 | 4946 | case LT: |
e236a9ff | 4947 | fputs (">", file); break; |
c85b8963 | 4948 | case LE: |
e236a9ff | 4949 | fputs (">=", file); break; |
c85b8963 | 4950 | case LEU: |
e236a9ff | 4951 | fputs (">>=", file); break; |
c85b8963 | 4952 | case LTU: |
e236a9ff | 4953 | fputs (">>", file); break; |
c85b8963 | 4954 | default: |
144d51f9 | 4955 | gcc_unreachable (); |
23f6f34f | 4956 | } |
c85b8963 TG |
4957 | return; |
4958 | case 'B': /* Condition, (B)oth swapped and negate. */ | |
4959 | switch (GET_CODE (x)) | |
4960 | { | |
4961 | case EQ: | |
e236a9ff | 4962 | fputs ("<>", file); break; |
c85b8963 | 4963 | case NE: |
e236a9ff | 4964 | fputs ("=", file); break; |
c85b8963 | 4965 | case GT: |
e236a9ff | 4966 | fputs (">=", file); break; |
c85b8963 | 4967 | case GE: |
e236a9ff | 4968 | fputs (">", file); break; |
c85b8963 | 4969 | case GEU: |
e236a9ff | 4970 | fputs (">>", file); break; |
c85b8963 | 4971 | case GTU: |
e236a9ff | 4972 | fputs (">>=", file); break; |
c85b8963 | 4973 | case LT: |
e236a9ff | 4974 | fputs ("<=", file); break; |
c85b8963 | 4975 | case LE: |
e236a9ff | 4976 | fputs ("<", file); break; |
c85b8963 | 4977 | case LEU: |
e236a9ff | 4978 | fputs ("<<", file); break; |
c85b8963 | 4979 | case LTU: |
e236a9ff | 4980 | fputs ("<<=", file); break; |
c85b8963 | 4981 | default: |
144d51f9 | 4982 | gcc_unreachable (); |
23f6f34f | 4983 | } |
c85b8963 TG |
4984 | return; |
4985 | case 'k': | |
144d51f9 NS |
4986 | gcc_assert (GET_CODE (x) == CONST_INT); |
4987 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x)); | |
4988 | return; | |
520babc7 | 4989 | case 'Q': |
144d51f9 NS |
4990 | gcc_assert (GET_CODE (x) == CONST_INT); |
4991 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63)); | |
4992 | return; | |
c8d6697c | 4993 | case 'L': |
144d51f9 NS |
4994 | gcc_assert (GET_CODE (x) == CONST_INT); |
4995 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31)); | |
4996 | return; | |
4802a0d6 | 4997 | case 'O': |
144d51f9 NS |
4998 | gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0); |
4999 | fprintf (file, "%d", exact_log2 (INTVAL (x))); | |
5000 | return; | |
520babc7 | 5001 | case 'p': |
144d51f9 NS |
5002 | gcc_assert (GET_CODE (x) == CONST_INT); |
5003 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63)); | |
5004 | return; | |
c8d6697c | 5005 | case 'P': |
144d51f9 NS |
5006 | gcc_assert (GET_CODE (x) == CONST_INT); |
5007 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31)); | |
5008 | return; | |
c85b8963 TG |
5009 | case 'I': |
5010 | if (GET_CODE (x) == CONST_INT) | |
5011 | fputs ("i", file); | |
5012 | return; | |
188538df | 5013 | case 'M': |
2414e0e2 | 5014 | case 'F': |
188538df TG |
5015 | switch (GET_CODE (XEXP (x, 0))) |
5016 | { | |
5017 | case PRE_DEC: | |
5018 | case PRE_INC: | |
f38b27c7 JL |
5019 | if (ASSEMBLER_DIALECT == 0) |
5020 | fputs ("s,mb", file); | |
5021 | else | |
5022 | fputs (",mb", file); | |
188538df TG |
5023 | break; |
5024 | case POST_DEC: | |
5025 | case POST_INC: | |
f38b27c7 JL |
5026 | if (ASSEMBLER_DIALECT == 0) |
5027 | fputs ("s,ma", file); | |
5028 | else | |
5029 | fputs (",ma", file); | |
188538df | 5030 | break; |
2414e0e2 | 5031 | case PLUS: |
d8f95bed JDA |
5032 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5033 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5034 | { | |
5035 | if (ASSEMBLER_DIALECT == 0) | |
5036 | fputs ("x", file); | |
5037 | } | |
5038 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
5039 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) | |
f38b27c7 JL |
5040 | { |
5041 | if (ASSEMBLER_DIALECT == 0) | |
5042 | fputs ("x,s", file); | |
5043 | else | |
5044 | fputs (",s", file); | |
5045 | } | |
5046 | else if (code == 'F' && ASSEMBLER_DIALECT == 0) | |
2414e0e2 | 5047 | fputs ("s", file); |
188538df TG |
5048 | break; |
5049 | default: | |
f38b27c7 | 5050 | if (code == 'F' && ASSEMBLER_DIALECT == 0) |
2414e0e2 | 5051 | fputs ("s", file); |
188538df TG |
5052 | break; |
5053 | } | |
5054 | return; | |
5055 | case 'G': | |
ad238e4b JL |
5056 | output_global_address (file, x, 0); |
5057 | return; | |
5058 | case 'H': | |
5059 | output_global_address (file, x, 1); | |
188538df TG |
5060 | return; |
5061 | case 0: /* Don't do anything special */ | |
5062 | break; | |
a1747d2c TG |
5063 | case 'Z': |
5064 | { | |
5065 | unsigned op[3]; | |
6fda0f5b | 5066 | compute_zdepwi_operands (INTVAL (x), op); |
a1747d2c TG |
5067 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); |
5068 | return; | |
5069 | } | |
520babc7 JL |
5070 | case 'z': |
5071 | { | |
5072 | unsigned op[3]; | |
5073 | compute_zdepdi_operands (INTVAL (x), op); | |
5074 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); | |
5075 | return; | |
5076 | } | |
11881f37 AM |
5077 | case 'c': |
5078 | /* We can get here from a .vtable_inherit due to our | |
5079 | CONSTANT_ADDRESS_P rejecting perfectly good constant | |
5080 | addresses. */ | |
5081 | break; | |
188538df | 5082 | default: |
144d51f9 | 5083 | gcc_unreachable (); |
188538df TG |
5084 | } |
5085 | if (GET_CODE (x) == REG) | |
80225b66 | 5086 | { |
3ba1236f | 5087 | fputs (reg_names [REGNO (x)], file); |
520babc7 JL |
5088 | if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4) |
5089 | { | |
5090 | fputs ("R", file); | |
5091 | return; | |
5092 | } | |
5093 | if (FP_REG_P (x) | |
5094 | && GET_MODE_SIZE (GET_MODE (x)) <= 4 | |
5095 | && (REGNO (x) & 1) == 0) | |
3ba1236f | 5096 | fputs ("L", file); |
80225b66 | 5097 | } |
188538df TG |
5098 | else if (GET_CODE (x) == MEM) |
5099 | { | |
5100 | int size = GET_MODE_SIZE (GET_MODE (x)); | |
478a4495 | 5101 | rtx base = NULL_RTX; |
188538df TG |
5102 | switch (GET_CODE (XEXP (x, 0))) |
5103 | { | |
5104 | case PRE_DEC: | |
5105 | case POST_DEC: | |
520babc7 | 5106 | base = XEXP (XEXP (x, 0), 0); |
d2d28085 | 5107 | fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]); |
188538df TG |
5108 | break; |
5109 | case PRE_INC: | |
5110 | case POST_INC: | |
520babc7 | 5111 | base = XEXP (XEXP (x, 0), 0); |
d2d28085 | 5112 | fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]); |
188538df | 5113 | break; |
d8f95bed JDA |
5114 | case PLUS: |
5115 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT) | |
d2d28085 | 5116 | fprintf (file, "%s(%s)", |
2414e0e2 JL |
5117 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))], |
5118 | reg_names [REGNO (XEXP (XEXP (x, 0), 1))]); | |
d8f95bed | 5119 | else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) |
d2d28085 | 5120 | fprintf (file, "%s(%s)", |
2414e0e2 JL |
5121 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))], |
5122 | reg_names [REGNO (XEXP (XEXP (x, 0), 0))]); | |
d8f95bed JDA |
5123 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5124 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5125 | { | |
5126 | /* Because the REG_POINTER flag can get lost during reload, | |
5127 | GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the | |
5128 | index and base registers in the combined move patterns. */ | |
5129 | rtx base = XEXP (XEXP (x, 0), 1); | |
5130 | rtx index = XEXP (XEXP (x, 0), 0); | |
5131 | ||
5132 | fprintf (file, "%s(%s)", | |
5133 | reg_names [REGNO (index)], reg_names [REGNO (base)]); | |
5134 | } | |
2414e0e2 JL |
5135 | else |
5136 | output_address (XEXP (x, 0)); | |
188538df | 5137 | break; |
d8f95bed JDA |
5138 | default: |
5139 | output_address (XEXP (x, 0)); | |
5140 | break; | |
188538df TG |
5141 | } |
5142 | } | |
188538df TG |
5143 | else |
5144 | output_addr_const (file, x); | |
5145 | } | |
5146 | ||
fe19a83d | 5147 | /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */ |
188538df TG |
5148 | |
5149 | void | |
b7849684 | 5150 | output_global_address (FILE *file, rtx x, int round_constant) |
188538df | 5151 | { |
43940f6b JL |
5152 | |
5153 | /* Imagine (high (const (plus ...))). */ | |
5154 | if (GET_CODE (x) == HIGH) | |
5155 | x = XEXP (x, 0); | |
5156 | ||
519104fe | 5157 | if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode)) |
744b2d61 | 5158 | output_addr_const (file, x); |
6bb36601 | 5159 | else if (GET_CODE (x) == SYMBOL_REF && !flag_pic) |
188538df | 5160 | { |
744b2d61 | 5161 | output_addr_const (file, x); |
e236a9ff | 5162 | fputs ("-$global$", file); |
188538df TG |
5163 | } |
5164 | else if (GET_CODE (x) == CONST) | |
5165 | { | |
519104fe | 5166 | const char *sep = ""; |
188538df | 5167 | int offset = 0; /* assembler wants -$global$ at end */ |
516c2342 | 5168 | rtx base = NULL_RTX; |
23f6f34f | 5169 | |
144d51f9 | 5170 | switch (GET_CODE (XEXP (XEXP (x, 0), 0))) |
188538df | 5171 | { |
144d51f9 | 5172 | case SYMBOL_REF: |
188538df TG |
5173 | base = XEXP (XEXP (x, 0), 0); |
5174 | output_addr_const (file, base); | |
144d51f9 NS |
5175 | break; |
5176 | case CONST_INT: | |
5177 | offset = INTVAL (XEXP (XEXP (x, 0), 0)); | |
5178 | break; | |
5179 | default: | |
5180 | gcc_unreachable (); | |
188538df | 5181 | } |
188538df | 5182 | |
144d51f9 | 5183 | switch (GET_CODE (XEXP (XEXP (x, 0), 1))) |
188538df | 5184 | { |
144d51f9 | 5185 | case SYMBOL_REF: |
188538df TG |
5186 | base = XEXP (XEXP (x, 0), 1); |
5187 | output_addr_const (file, base); | |
144d51f9 NS |
5188 | break; |
5189 | case CONST_INT: | |
5190 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
5191 | break; | |
5192 | default: | |
5193 | gcc_unreachable (); | |
188538df | 5194 | } |
188538df | 5195 | |
ad238e4b JL |
5196 | /* How bogus. The compiler is apparently responsible for |
5197 | rounding the constant if it uses an LR field selector. | |
5198 | ||
5199 | The linker and/or assembler seem a better place since | |
5200 | they have to do this kind of thing already. | |
5201 | ||
5202 | If we fail to do this, HP's optimizing linker may eliminate | |
5203 | an addil, but not update the ldw/stw/ldo instruction that | |
5204 | uses the result of the addil. */ | |
5205 | if (round_constant) | |
5206 | offset = ((offset + 0x1000) & ~0x1fff); | |
5207 | ||
144d51f9 | 5208 | switch (GET_CODE (XEXP (x, 0))) |
188538df | 5209 | { |
144d51f9 | 5210 | case PLUS: |
188538df TG |
5211 | if (offset < 0) |
5212 | { | |
5213 | offset = -offset; | |
5214 | sep = "-"; | |
5215 | } | |
5216 | else | |
5217 | sep = "+"; | |
144d51f9 NS |
5218 | break; |
5219 | ||
5220 | case MINUS: | |
5221 | gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF); | |
5222 | sep = "-"; | |
5223 | break; | |
188538df | 5224 | |
144d51f9 NS |
5225 | default: |
5226 | gcc_unreachable (); | |
5227 | } | |
5228 | ||
519104fe | 5229 | if (!read_only_operand (base, VOIDmode) && !flag_pic) |
e236a9ff | 5230 | fputs ("-$global$", file); |
ad238e4b | 5231 | if (offset) |
831c1763 | 5232 | fprintf (file, "%s%d", sep, offset); |
188538df TG |
5233 | } |
5234 | else | |
5235 | output_addr_const (file, x); | |
5236 | } | |
5237 | ||
1bc7c5b6 ZW |
5238 | /* Output boilerplate text to appear at the beginning of the file. |
5239 | There are several possible versions. */ | |
5240 | #define aputs(x) fputs(x, asm_out_file) | |
5241 | static inline void | |
b7849684 | 5242 | pa_file_start_level (void) |
1bc7c5b6 ZW |
5243 | { |
5244 | if (TARGET_64BIT) | |
5245 | aputs ("\t.LEVEL 2.0w\n"); | |
5246 | else if (TARGET_PA_20) | |
5247 | aputs ("\t.LEVEL 2.0\n"); | |
5248 | else if (TARGET_PA_11) | |
5249 | aputs ("\t.LEVEL 1.1\n"); | |
5250 | else | |
5251 | aputs ("\t.LEVEL 1.0\n"); | |
5252 | } | |
5253 | ||
5254 | static inline void | |
b7849684 | 5255 | pa_file_start_space (int sortspace) |
1bc7c5b6 ZW |
5256 | { |
5257 | aputs ("\t.SPACE $PRIVATE$"); | |
5258 | if (sortspace) | |
5259 | aputs (",SORT=16"); | |
5260 | aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31" | |
5261 | "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82" | |
5262 | "\n\t.SPACE $TEXT$"); | |
5263 | if (sortspace) | |
5264 | aputs (",SORT=8"); | |
5265 | aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44" | |
5266 | "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n"); | |
5267 | } | |
5268 | ||
5269 | static inline void | |
b7849684 | 5270 | pa_file_start_file (int want_version) |
1bc7c5b6 ZW |
5271 | { |
5272 | if (write_symbols != NO_DEBUG) | |
5273 | { | |
5274 | output_file_directive (asm_out_file, main_input_filename); | |
5275 | if (want_version) | |
5276 | aputs ("\t.version\t\"01.01\"\n"); | |
5277 | } | |
5278 | } | |
5279 | ||
5280 | static inline void | |
b7849684 | 5281 | pa_file_start_mcount (const char *aswhat) |
1bc7c5b6 ZW |
5282 | { |
5283 | if (profile_flag) | |
5284 | fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat); | |
5285 | } | |
5286 | ||
5287 | static void | |
b7849684 | 5288 | pa_elf_file_start (void) |
1bc7c5b6 ZW |
5289 | { |
5290 | pa_file_start_level (); | |
5291 | pa_file_start_mcount ("ENTRY"); | |
5292 | pa_file_start_file (0); | |
5293 | } | |
5294 | ||
5295 | static void | |
b7849684 | 5296 | pa_som_file_start (void) |
1bc7c5b6 ZW |
5297 | { |
5298 | pa_file_start_level (); | |
5299 | pa_file_start_space (0); | |
5300 | aputs ("\t.IMPORT $global$,DATA\n" | |
5301 | "\t.IMPORT $$dyncall,MILLICODE\n"); | |
5302 | pa_file_start_mcount ("CODE"); | |
5303 | pa_file_start_file (0); | |
5304 | } | |
5305 | ||
5306 | static void | |
b7849684 | 5307 | pa_linux_file_start (void) |
1bc7c5b6 ZW |
5308 | { |
5309 | pa_file_start_file (1); | |
5310 | pa_file_start_level (); | |
5311 | pa_file_start_mcount ("CODE"); | |
5312 | } | |
5313 | ||
5314 | static void | |
b7849684 | 5315 | pa_hpux64_gas_file_start (void) |
1bc7c5b6 ZW |
5316 | { |
5317 | pa_file_start_level (); | |
5318 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
5319 | if (profile_flag) | |
5320 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function"); | |
5321 | #endif | |
5322 | pa_file_start_file (1); | |
5323 | } | |
5324 | ||
5325 | static void | |
b7849684 | 5326 | pa_hpux64_hpas_file_start (void) |
1bc7c5b6 ZW |
5327 | { |
5328 | pa_file_start_level (); | |
5329 | pa_file_start_space (1); | |
5330 | pa_file_start_mcount ("CODE"); | |
5331 | pa_file_start_file (0); | |
5332 | } | |
5333 | #undef aputs | |
5334 | ||
7aaf280e JDA |
5335 | /* Search the deferred plabel list for SYMBOL and return its internal |
5336 | label. If an entry for SYMBOL is not found, a new entry is created. */ | |
5337 | ||
5338 | rtx | |
5339 | get_deferred_plabel (rtx symbol) | |
a02aa5b0 | 5340 | { |
744b2d61 | 5341 | const char *fname = XSTR (symbol, 0); |
a02aa5b0 JDA |
5342 | size_t i; |
5343 | ||
5344 | /* See if we have already put this function on the list of deferred | |
5345 | plabels. This list is generally small, so a liner search is not | |
5346 | too ugly. If it proves too slow replace it with something faster. */ | |
5347 | for (i = 0; i < n_deferred_plabels; i++) | |
744b2d61 | 5348 | if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0) |
a02aa5b0 JDA |
5349 | break; |
5350 | ||
5351 | /* If the deferred plabel list is empty, or this entry was not found | |
5352 | on the list, create a new entry on the list. */ | |
5353 | if (deferred_plabels == NULL || i == n_deferred_plabels) | |
5354 | { | |
744b2d61 JDA |
5355 | tree id; |
5356 | ||
a02aa5b0 JDA |
5357 | if (deferred_plabels == 0) |
5358 | deferred_plabels = (struct deferred_plabel *) | |
5359 | ggc_alloc (sizeof (struct deferred_plabel)); | |
5360 | else | |
5361 | deferred_plabels = (struct deferred_plabel *) | |
5362 | ggc_realloc (deferred_plabels, | |
5363 | ((n_deferred_plabels + 1) | |
5364 | * sizeof (struct deferred_plabel))); | |
5365 | ||
5366 | i = n_deferred_plabels++; | |
5367 | deferred_plabels[i].internal_label = gen_label_rtx (); | |
744b2d61 | 5368 | deferred_plabels[i].symbol = symbol; |
a02aa5b0 | 5369 | |
744b2d61 JDA |
5370 | /* Gross. We have just implicitly taken the address of this |
5371 | function. Mark it in the same manner as assemble_name. */ | |
5372 | id = maybe_get_identifier (targetm.strip_name_encoding (fname)); | |
5373 | if (id) | |
5374 | mark_referenced (id); | |
a02aa5b0 JDA |
5375 | } |
5376 | ||
7aaf280e | 5377 | return deferred_plabels[i].internal_label; |
a02aa5b0 JDA |
5378 | } |
5379 | ||
a5fe455b | 5380 | static void |
b7849684 | 5381 | output_deferred_plabels (void) |
359255a9 | 5382 | { |
0f8e3849 | 5383 | size_t i; |
1a83bfc3 JDA |
5384 | |
5385 | /* If we have some deferred plabels, then we need to switch into the | |
5386 | data or readonly data section, and align it to a 4 byte boundary | |
6416ae7f | 5387 | before outputting the deferred plabels. */ |
359255a9 JL |
5388 | if (n_deferred_plabels) |
5389 | { | |
1a83bfc3 | 5390 | switch_to_section (flag_pic ? data_section : readonly_data_section); |
a5fe455b | 5391 | ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2); |
359255a9 JL |
5392 | } |
5393 | ||
5394 | /* Now output the deferred plabels. */ | |
5395 | for (i = 0; i < n_deferred_plabels; i++) | |
5396 | { | |
ecc418c4 | 5397 | targetm.asm_out.internal_label (asm_out_file, "L", |
a5fe455b | 5398 | CODE_LABEL_NUMBER (deferred_plabels[i].internal_label)); |
744b2d61 | 5399 | assemble_integer (deferred_plabels[i].symbol, |
3d9268b6 | 5400 | TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1); |
359255a9 JL |
5401 | } |
5402 | } | |
5403 | ||
c15c90bb ZW |
5404 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
5405 | /* Initialize optabs to point to HPUX long double emulation routines. */ | |
5406 | static void | |
5407 | pa_hpux_init_libfuncs (void) | |
5408 | { | |
5409 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
5410 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
5411 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
5412 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
5413 | set_optab_libfunc (smin_optab, TFmode, "_U_Qmin"); | |
5414 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
5415 | set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt"); | |
5416 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
5417 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
5418 | ||
c9034561 ZW |
5419 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); |
5420 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
5421 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
5422 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
5423 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
5424 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
e2ddd6ca | 5425 | set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord"); |
c15c90bb | 5426 | |
85363ca0 ZW |
5427 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); |
5428 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
5429 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
5430 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
5431 | ||
5432 | set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT | |
5433 | ? "__U_Qfcnvfxt_quad_to_sgl" | |
5434 | : "_U_Qfcnvfxt_quad_to_sgl"); | |
5435 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl"); | |
5436 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl"); | |
5437 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl"); | |
5438 | ||
5439 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad"); | |
5440 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad"); | |
7db0cc7e JDA |
5441 | set_conv_libfunc (ufloat_optab, TFmode, SImode, "_U_Qfcnvxf_usgl_to_quad"); |
5442 | set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxf_udbl_to_quad"); | |
c15c90bb ZW |
5443 | } |
5444 | #endif | |
5445 | ||
188538df TG |
5446 | /* HP's millicode routines mean something special to the assembler. |
5447 | Keep track of which ones we have used. */ | |
5448 | ||
f3a4e54e | 5449 | enum millicodes { remI, remU, divI, divU, mulI, end1000 }; |
b7849684 | 5450 | static void import_milli (enum millicodes); |
831c1763 | 5451 | static char imported[(int) end1000]; |
f3a4e54e | 5452 | static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"}; |
8b60264b | 5453 | static const char import_string[] = ".IMPORT $$....,MILLICODE"; |
188538df TG |
5454 | #define MILLI_START 10 |
5455 | ||
f1c7ce82 | 5456 | static void |
b7849684 | 5457 | import_milli (enum millicodes code) |
188538df TG |
5458 | { |
5459 | char str[sizeof (import_string)]; | |
23f6f34f | 5460 | |
831c1763 | 5461 | if (!imported[(int) code]) |
188538df | 5462 | { |
831c1763 | 5463 | imported[(int) code] = 1; |
188538df | 5464 | strcpy (str, import_string); |
831c1763 | 5465 | strncpy (str + MILLI_START, milli_names[(int) code], 4); |
188538df TG |
5466 | output_asm_insn (str, 0); |
5467 | } | |
5468 | } | |
5469 | ||
23f6f34f | 5470 | /* The register constraints have put the operands and return value in |
fe19a83d | 5471 | the proper registers. */ |
188538df | 5472 | |
519104fe | 5473 | const char * |
b7849684 | 5474 | output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn) |
188538df | 5475 | { |
9b38c2fa | 5476 | import_milli (mulI); |
690d4228 | 5477 | return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI")); |
188538df TG |
5478 | } |
5479 | ||
fe19a83d | 5480 | /* Emit the rtl for doing a division by a constant. */ |
188538df | 5481 | |
9b38c2fa | 5482 | /* Do magic division millicodes exist for this value? */ |
c9a88190 | 5483 | const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1}; |
188538df | 5484 | |
23f6f34f | 5485 | /* We'll use an array to keep track of the magic millicodes and |
188538df | 5486 | whether or not we've used them already. [n][0] is signed, [n][1] is |
fe19a83d | 5487 | unsigned. */ |
188538df | 5488 | |
188538df TG |
5489 | static int div_milli[16][2]; |
5490 | ||
188538df | 5491 | int |
b7849684 | 5492 | emit_hpdiv_const (rtx *operands, int unsignedp) |
188538df TG |
5493 | { |
5494 | if (GET_CODE (operands[2]) == CONST_INT | |
5495 | && INTVAL (operands[2]) > 0 | |
5496 | && INTVAL (operands[2]) < 16 | |
5497 | && magic_milli[INTVAL (operands[2])]) | |
5498 | { | |
7d8b1412 AM |
5499 | rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31); |
5500 | ||
ad2c71b7 | 5501 | emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]); |
188538df | 5502 | emit |
92fd5e41 KH |
5503 | (gen_rtx_PARALLEL |
5504 | (VOIDmode, | |
bd83f9a5 | 5505 | gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29), |
ad2c71b7 JL |
5506 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, |
5507 | SImode, | |
5508 | gen_rtx_REG (SImode, 26), | |
5509 | operands[2])), | |
bd83f9a5 | 5510 | gen_rtx_CLOBBER (VOIDmode, operands[4]), |
ad2c71b7 JL |
5511 | gen_rtx_CLOBBER (VOIDmode, operands[3]), |
5512 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)), | |
5513 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)), | |
7d8b1412 | 5514 | gen_rtx_CLOBBER (VOIDmode, ret)))); |
ad2c71b7 | 5515 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 29)); |
188538df TG |
5516 | return 1; |
5517 | } | |
5518 | return 0; | |
5519 | } | |
5520 | ||
519104fe | 5521 | const char * |
b7849684 | 5522 | output_div_insn (rtx *operands, int unsignedp, rtx insn) |
188538df TG |
5523 | { |
5524 | int divisor; | |
23f6f34f TG |
5525 | |
5526 | /* If the divisor is a constant, try to use one of the special | |
188538df TG |
5527 | opcodes .*/ |
5528 | if (GET_CODE (operands[0]) == CONST_INT) | |
5529 | { | |
2c4ff308 | 5530 | static char buf[100]; |
188538df TG |
5531 | divisor = INTVAL (operands[0]); |
5532 | if (!div_milli[divisor][unsignedp]) | |
5533 | { | |
2c4ff308 | 5534 | div_milli[divisor][unsignedp] = 1; |
188538df TG |
5535 | if (unsignedp) |
5536 | output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands); | |
5537 | else | |
5538 | output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands); | |
188538df TG |
5539 | } |
5540 | if (unsignedp) | |
2c4ff308 | 5541 | { |
4a0a75dd KG |
5542 | sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC, |
5543 | INTVAL (operands[0])); | |
6a73009d | 5544 | return output_millicode_call (insn, |
ad2c71b7 | 5545 | gen_rtx_SYMBOL_REF (SImode, buf)); |
2c4ff308 JL |
5546 | } |
5547 | else | |
5548 | { | |
4a0a75dd KG |
5549 | sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC, |
5550 | INTVAL (operands[0])); | |
6a73009d | 5551 | return output_millicode_call (insn, |
ad2c71b7 | 5552 | gen_rtx_SYMBOL_REF (SImode, buf)); |
2c4ff308 | 5553 | } |
188538df | 5554 | } |
fe19a83d | 5555 | /* Divisor isn't a special constant. */ |
188538df TG |
5556 | else |
5557 | { | |
5558 | if (unsignedp) | |
5559 | { | |
5560 | import_milli (divU); | |
6a73009d | 5561 | return output_millicode_call (insn, |
ad2c71b7 | 5562 | gen_rtx_SYMBOL_REF (SImode, "$$divU")); |
188538df TG |
5563 | } |
5564 | else | |
5565 | { | |
5566 | import_milli (divI); | |
6a73009d | 5567 | return output_millicode_call (insn, |
ad2c71b7 | 5568 | gen_rtx_SYMBOL_REF (SImode, "$$divI")); |
188538df TG |
5569 | } |
5570 | } | |
5571 | } | |
5572 | ||
fe19a83d | 5573 | /* Output a $$rem millicode to do mod. */ |
188538df | 5574 | |
519104fe | 5575 | const char * |
b7849684 | 5576 | output_mod_insn (int unsignedp, rtx insn) |
188538df TG |
5577 | { |
5578 | if (unsignedp) | |
5579 | { | |
5580 | import_milli (remU); | |
6a73009d | 5581 | return output_millicode_call (insn, |
ad2c71b7 | 5582 | gen_rtx_SYMBOL_REF (SImode, "$$remU")); |
188538df TG |
5583 | } |
5584 | else | |
5585 | { | |
5586 | import_milli (remI); | |
6a73009d | 5587 | return output_millicode_call (insn, |
ad2c71b7 | 5588 | gen_rtx_SYMBOL_REF (SImode, "$$remI")); |
188538df TG |
5589 | } |
5590 | } | |
5591 | ||
5592 | void | |
b7849684 | 5593 | output_arg_descriptor (rtx call_insn) |
188538df | 5594 | { |
519104fe | 5595 | const char *arg_regs[4]; |
188538df | 5596 | enum machine_mode arg_mode; |
80225b66 | 5597 | rtx link; |
188538df TG |
5598 | int i, output_flag = 0; |
5599 | int regno; | |
23f6f34f | 5600 | |
520babc7 | 5601 | /* We neither need nor want argument location descriptors for the |
e25724d8 AM |
5602 | 64bit runtime environment or the ELF32 environment. */ |
5603 | if (TARGET_64BIT || TARGET_ELF32) | |
520babc7 JL |
5604 | return; |
5605 | ||
188538df TG |
5606 | for (i = 0; i < 4; i++) |
5607 | arg_regs[i] = 0; | |
5608 | ||
2822d96e JL |
5609 | /* Specify explicitly that no argument relocations should take place |
5610 | if using the portable runtime calling conventions. */ | |
5611 | if (TARGET_PORTABLE_RUNTIME) | |
5612 | { | |
e236a9ff JL |
5613 | fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n", |
5614 | asm_out_file); | |
2822d96e JL |
5615 | return; |
5616 | } | |
5617 | ||
144d51f9 NS |
5618 | gcc_assert (GET_CODE (call_insn) == CALL_INSN); |
5619 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); | |
5620 | link; link = XEXP (link, 1)) | |
188538df | 5621 | { |
80225b66 | 5622 | rtx use = XEXP (link, 0); |
3529be83 | 5623 | |
80225b66 TG |
5624 | if (! (GET_CODE (use) == USE |
5625 | && GET_CODE (XEXP (use, 0)) == REG | |
5626 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
3529be83 RS |
5627 | continue; |
5628 | ||
80225b66 TG |
5629 | arg_mode = GET_MODE (XEXP (use, 0)); |
5630 | regno = REGNO (XEXP (use, 0)); | |
188538df | 5631 | if (regno >= 23 && regno <= 26) |
a9d91d6f RS |
5632 | { |
5633 | arg_regs[26 - regno] = "GR"; | |
5634 | if (arg_mode == DImode) | |
5635 | arg_regs[25 - regno] = "GR"; | |
5636 | } | |
80225b66 | 5637 | else if (regno >= 32 && regno <= 39) |
188538df TG |
5638 | { |
5639 | if (arg_mode == SFmode) | |
80225b66 | 5640 | arg_regs[(regno - 32) / 2] = "FR"; |
d0616842 | 5641 | else |
188538df | 5642 | { |
22d6e660 | 5643 | #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED |
80225b66 TG |
5644 | arg_regs[(regno - 34) / 2] = "FR"; |
5645 | arg_regs[(regno - 34) / 2 + 1] = "FU"; | |
188538df | 5646 | #else |
80225b66 TG |
5647 | arg_regs[(regno - 34) / 2] = "FU"; |
5648 | arg_regs[(regno - 34) / 2 + 1] = "FR"; | |
188538df TG |
5649 | #endif |
5650 | } | |
188538df TG |
5651 | } |
5652 | } | |
5653 | fputs ("\t.CALL ", asm_out_file); | |
5654 | for (i = 0; i < 4; i++) | |
5655 | { | |
5656 | if (arg_regs[i]) | |
5657 | { | |
5658 | if (output_flag++) | |
5659 | fputc (',', asm_out_file); | |
5660 | fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]); | |
5661 | } | |
5662 | } | |
5663 | fputc ('\n', asm_out_file); | |
5664 | } | |
5665 | \f | |
ec963611 | 5666 | static enum reg_class |
0a2aaacc | 5667 | pa_secondary_reload (bool in_p, rtx x, enum reg_class rclass, |
ec963611 JDA |
5668 | enum machine_mode mode, secondary_reload_info *sri) |
5669 | { | |
69f8a2d6 | 5670 | int is_symbolic, regno; |
e236a9ff | 5671 | |
ec963611 | 5672 | /* Handle the easy stuff first. */ |
0a2aaacc | 5673 | if (rclass == R1_REGS) |
ec963611 | 5674 | return NO_REGS; |
e236a9ff | 5675 | |
ec963611 JDA |
5676 | if (REG_P (x)) |
5677 | { | |
5678 | regno = REGNO (x); | |
0a2aaacc | 5679 | if (rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER) |
ec963611 JDA |
5680 | return NO_REGS; |
5681 | } | |
69f8a2d6 JDA |
5682 | else |
5683 | regno = -1; | |
188538df | 5684 | |
ec963611 JDA |
5685 | /* If we have something like (mem (mem (...)), we can safely assume the |
5686 | inner MEM will end up in a general register after reloading, so there's | |
5687 | no need for a secondary reload. */ | |
5688 | if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM) | |
5689 | return NO_REGS; | |
188538df | 5690 | |
6bb36601 | 5691 | /* Trying to load a constant into a FP register during PIC code |
ec963611 | 5692 | generation requires %r1 as a scratch register. */ |
7ee72796 | 5693 | if (flag_pic |
7e646101 | 5694 | && (mode == SImode || mode == DImode) |
0a2aaacc | 5695 | && FP_REG_CLASS_P (rclass) |
ec963611 | 5696 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
e236a9ff | 5697 | { |
ec963611 JDA |
5698 | sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1 |
5699 | : CODE_FOR_reload_indi_r1); | |
5700 | return NO_REGS; | |
e236a9ff | 5701 | } |
e236a9ff | 5702 | |
ec963611 JDA |
5703 | /* Profiling showed the PA port spends about 1.3% of its compilation |
5704 | time in true_regnum from calls inside pa_secondary_reload_class. */ | |
5705 | if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG) | |
5706 | regno = true_regnum (x); | |
39dfb55a | 5707 | |
6982c5d4 JDA |
5708 | /* In order to allow 14-bit displacements in integer loads and stores, |
5709 | we need to prevent reload from generating out of range integer mode | |
5710 | loads and stores to the floating point registers. Previously, we | |
5711 | used to call for a secondary reload and have emit_move_sequence() | |
5712 | fix the instruction sequence. However, reload occasionally wouldn't | |
5713 | generate the reload and we would end up with an invalid REG+D memory | |
5714 | address. So, now we use an intermediate general register for most | |
5715 | memory loads and stores. */ | |
5716 | if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1) | |
5717 | && GET_MODE_CLASS (mode) == MODE_INT | |
0a2aaacc | 5718 | && FP_REG_CLASS_P (rclass)) |
6982c5d4 JDA |
5719 | { |
5720 | /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check | |
5721 | the secondary reload needed for a pseudo. It never passes a | |
5722 | REG+D address. */ | |
5723 | if (GET_CODE (x) == MEM) | |
5724 | { | |
5725 | x = XEXP (x, 0); | |
5726 | ||
5727 | /* We don't need an intermediate for indexed and LO_SUM DLT | |
5728 | memory addresses. When INT14_OK_STRICT is true, it might | |
5729 | appear that we could directly allow register indirect | |
5730 | memory addresses. However, this doesn't work because we | |
5731 | don't support SUBREGs in floating-point register copies | |
5732 | and reload doesn't tell us when it's going to use a SUBREG. */ | |
5733 | if (IS_INDEX_ADDR_P (x) | |
5734 | || IS_LO_SUM_DLT_ADDR_P (x)) | |
5735 | return NO_REGS; | |
5736 | ||
5737 | /* Otherwise, we need an intermediate general register. */ | |
5738 | return GENERAL_REGS; | |
5739 | } | |
5740 | ||
5741 | /* Request a secondary reload with a general scratch register | |
5742 | for everthing else. ??? Could symbolic operands be handled | |
5743 | directly when generating non-pic PA 2.0 code? */ | |
5744 | sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode]; | |
5745 | return NO_REGS; | |
5746 | } | |
5747 | ||
5748 | /* We need a secondary register (GPR) for copies between the SAR | |
5749 | and anything other than a general register. */ | |
0a2aaacc | 5750 | if (rclass == SHIFT_REGS && (regno <= 0 || regno >= 32)) |
ec963611 JDA |
5751 | { |
5752 | sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode]; | |
5753 | return NO_REGS; | |
5754 | } | |
fa5e5c1e | 5755 | |
26ee120d JL |
5756 | /* A SAR<->FP register copy requires a secondary register (GPR) as |
5757 | well as secondary memory. */ | |
5758 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
6982c5d4 | 5759 | && (REGNO_REG_CLASS (regno) == SHIFT_REGS |
0a2aaacc | 5760 | && FP_REG_CLASS_P (rclass))) |
ec963611 JDA |
5761 | { |
5762 | sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode]; | |
5763 | return NO_REGS; | |
5764 | } | |
26ee120d | 5765 | |
ec963611 | 5766 | /* Secondary reloads of symbolic operands require %r1 as a scratch |
6982c5d4 | 5767 | register when we're generating PIC code and when the operand isn't |
ec963611 JDA |
5768 | readonly. */ |
5769 | if (GET_CODE (x) == HIGH) | |
5770 | x = XEXP (x, 0); | |
43940f6b | 5771 | |
e236a9ff | 5772 | /* Profiling has showed GCC spends about 2.6% of its compilation |
3c4774e0 | 5773 | time in symbolic_operand from calls inside pa_secondary_reload_class. |
ec963611 JDA |
5774 | So, we use an inline copy to avoid useless work. */ |
5775 | switch (GET_CODE (x)) | |
e236a9ff | 5776 | { |
ec963611 | 5777 | rtx op; |
e236a9ff JL |
5778 | |
5779 | case SYMBOL_REF: | |
ec963611 JDA |
5780 | is_symbolic = !SYMBOL_REF_TLS_MODEL (x); |
5781 | break; | |
e236a9ff JL |
5782 | case LABEL_REF: |
5783 | is_symbolic = 1; | |
5784 | break; | |
5785 | case CONST: | |
ec963611 JDA |
5786 | op = XEXP (x, 0); |
5787 | is_symbolic = (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF | |
5788 | && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0))) | |
5789 | || GET_CODE (XEXP (op, 0)) == LABEL_REF) | |
5790 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
e236a9ff JL |
5791 | break; |
5792 | default: | |
5793 | is_symbolic = 0; | |
5794 | break; | |
5795 | } | |
6619e96c | 5796 | |
ec963611 JDA |
5797 | if (is_symbolic && (flag_pic || !read_only_operand (x, VOIDmode))) |
5798 | { | |
5799 | gcc_assert (mode == SImode || mode == DImode); | |
5800 | sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1 | |
5801 | : CODE_FOR_reload_indi_r1); | |
5802 | } | |
43940f6b | 5803 | |
fa5e5c1e | 5804 | return NO_REGS; |
188538df TG |
5805 | } |
5806 | ||
16c16a24 JDA |
5807 | /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer |
5808 | is only marked as live on entry by df-scan when it is a fixed | |
5809 | register. It isn't a fixed register in the 64-bit runtime, | |
5810 | so we need to mark it here. */ | |
5811 | ||
5812 | static void | |
5813 | pa_extra_live_on_entry (bitmap regs) | |
5814 | { | |
5815 | if (TARGET_64BIT) | |
5816 | bitmap_set_bit (regs, ARG_POINTER_REGNUM); | |
5817 | } | |
5818 | ||
5819 | /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile | |
5820 | to prevent it from being deleted. */ | |
5821 | ||
5822 | rtx | |
5823 | pa_eh_return_handler_rtx (void) | |
5824 | { | |
5825 | rtx tmp; | |
5826 | ||
5827 | tmp = gen_rtx_PLUS (word_mode, frame_pointer_rtx, | |
5828 | TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)); | |
5829 | tmp = gen_rtx_MEM (word_mode, tmp); | |
5830 | tmp->volatil = 1; | |
5831 | return tmp; | |
5832 | } | |
5833 | ||
8cd5a4e0 RH |
5834 | /* In the 32-bit runtime, arguments larger than eight bytes are passed |
5835 | by invisible reference. As a GCC extension, we also pass anything | |
5836 | with a zero or variable size by reference. | |
5837 | ||
5838 | The 64-bit runtime does not describe passing any types by invisible | |
5839 | reference. The internals of GCC can't currently handle passing | |
5840 | empty structures, and zero or variable length arrays when they are | |
5841 | not passed entirely on the stack or by reference. Thus, as a GCC | |
5842 | extension, we pass these types by reference. The HP compiler doesn't | |
5843 | support these types, so hopefully there shouldn't be any compatibility | |
5844 | issues. This may have to be revisited when HP releases a C99 compiler | |
5845 | or updates the ABI. */ | |
5846 | ||
5847 | static bool | |
5848 | pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, | |
586de218 | 5849 | enum machine_mode mode, const_tree type, |
8cd5a4e0 RH |
5850 | bool named ATTRIBUTE_UNUSED) |
5851 | { | |
5852 | HOST_WIDE_INT size; | |
5853 | ||
5854 | if (type) | |
5855 | size = int_size_in_bytes (type); | |
5856 | else | |
5857 | size = GET_MODE_SIZE (mode); | |
5858 | ||
5859 | if (TARGET_64BIT) | |
5860 | return size <= 0; | |
5861 | else | |
5862 | return size <= 0 || size > 8; | |
5863 | } | |
5864 | ||
188538df | 5865 | enum direction |
586de218 | 5866 | function_arg_padding (enum machine_mode mode, const_tree type) |
188538df | 5867 | { |
9dff28ab | 5868 | if (mode == BLKmode |
c3e39a47 JDA |
5869 | || (TARGET_64BIT |
5870 | && type | |
5871 | && (AGGREGATE_TYPE_P (type) | |
5872 | || TREE_CODE (type) == COMPLEX_TYPE | |
5873 | || TREE_CODE (type) == VECTOR_TYPE))) | |
9dff28ab JDA |
5874 | { |
5875 | /* Return none if justification is not required. */ | |
5876 | if (type | |
5877 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
5878 | && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0) | |
5879 | return none; | |
5880 | ||
5881 | /* The directions set here are ignored when a BLKmode argument larger | |
5882 | than a word is placed in a register. Different code is used for | |
5883 | the stack and registers. This makes it difficult to have a | |
5884 | consistent data representation for both the stack and registers. | |
5885 | For both runtimes, the justification and padding for arguments on | |
5886 | the stack and in registers should be identical. */ | |
5887 | if (TARGET_64BIT) | |
5888 | /* The 64-bit runtime specifies left justification for aggregates. */ | |
5889 | return upward; | |
188538df | 5890 | else |
9dff28ab JDA |
5891 | /* The 32-bit runtime architecture specifies right justification. |
5892 | When the argument is passed on the stack, the argument is padded | |
5893 | with garbage on the left. The HP compiler pads with zeros. */ | |
5894 | return downward; | |
188538df | 5895 | } |
9dff28ab JDA |
5896 | |
5897 | if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
188538df | 5898 | return downward; |
188538df TG |
5899 | else |
5900 | return none; | |
5901 | } | |
5902 | ||
188538df | 5903 | \f |
648d2ffc RH |
5904 | /* Do what is necessary for `va_start'. We look at the current function |
5905 | to determine if stdargs or varargs is used and fill in an initial | |
5906 | va_list. A pointer to this constructor is returned. */ | |
188538df | 5907 | |
3f12cd9b | 5908 | static rtx |
b7849684 | 5909 | hppa_builtin_saveregs (void) |
188538df | 5910 | { |
5e32727c | 5911 | rtx offset, dest; |
188538df TG |
5912 | tree fntype = TREE_TYPE (current_function_decl); |
5913 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
5914 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
5915 | != void_type_node))) | |
5916 | ? UNITS_PER_WORD : 0); | |
5917 | ||
5918 | if (argadj) | |
38173d38 | 5919 | offset = plus_constant (crtl->args.arg_offset_rtx, argadj); |
188538df | 5920 | else |
38173d38 | 5921 | offset = crtl->args.arg_offset_rtx; |
17e1dfa2 | 5922 | |
520babc7 JL |
5923 | if (TARGET_64BIT) |
5924 | { | |
5925 | int i, off; | |
6619e96c | 5926 | |
520babc7 JL |
5927 | /* Adjust for varargs/stdarg differences. */ |
5928 | if (argadj) | |
38173d38 | 5929 | offset = plus_constant (crtl->args.arg_offset_rtx, -argadj); |
520babc7 | 5930 | else |
38173d38 | 5931 | offset = crtl->args.arg_offset_rtx; |
520babc7 JL |
5932 | |
5933 | /* We need to save %r26 .. %r19 inclusive starting at offset -64 | |
5934 | from the incoming arg pointer and growing to larger addresses. */ | |
5935 | for (i = 26, off = -64; i >= 19; i--, off += 8) | |
5936 | emit_move_insn (gen_rtx_MEM (word_mode, | |
5937 | plus_constant (arg_pointer_rtx, off)), | |
5938 | gen_rtx_REG (word_mode, i)); | |
5939 | ||
5940 | /* The incoming args pointer points just beyond the flushback area; | |
f710504c | 5941 | normally this is not a serious concern. However, when we are doing |
520babc7 JL |
5942 | varargs/stdargs we want to make the arg pointer point to the start |
5943 | of the incoming argument area. */ | |
5944 | emit_move_insn (virtual_incoming_args_rtx, | |
5945 | plus_constant (arg_pointer_rtx, -64)); | |
5946 | ||
5947 | /* Now return a pointer to the first anonymous argument. */ | |
5948 | return copy_to_reg (expand_binop (Pmode, add_optab, | |
5949 | virtual_incoming_args_rtx, | |
5950 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
5951 | } | |
5952 | ||
fe19a83d | 5953 | /* Store general registers on the stack. */ |
ad2c71b7 | 5954 | dest = gen_rtx_MEM (BLKmode, |
38173d38 | 5955 | plus_constant (crtl->args.internal_arg_pointer, |
ad2c71b7 | 5956 | -16)); |
ba4828e0 | 5957 | set_mem_alias_set (dest, get_varargs_alias_set ()); |
8ac61af7 | 5958 | set_mem_align (dest, BITS_PER_WORD); |
c6b97fac | 5959 | move_block_from_reg (23, dest, 4); |
5e32727c | 5960 | |
39dfb55a JL |
5961 | /* move_block_from_reg will emit code to store the argument registers |
5962 | individually as scalar stores. | |
5963 | ||
5964 | However, other insns may later load from the same addresses for | |
956d6950 | 5965 | a structure load (passing a struct to a varargs routine). |
39dfb55a JL |
5966 | |
5967 | The alias code assumes that such aliasing can never happen, so we | |
5968 | have to keep memory referencing insns from moving up beyond the | |
5969 | last argument register store. So we emit a blockage insn here. */ | |
5970 | emit_insn (gen_blockage ()); | |
5971 | ||
17e1dfa2 | 5972 | return copy_to_reg (expand_binop (Pmode, add_optab, |
38173d38 | 5973 | crtl->args.internal_arg_pointer, |
17e1dfa2 | 5974 | offset, 0, 0, OPTAB_LIB_WIDEN)); |
188538df | 5975 | } |
d2a94ec0 | 5976 | |
d7bd8aeb | 5977 | static void |
b7849684 | 5978 | hppa_va_start (tree valist, rtx nextarg) |
ca5f4364 RH |
5979 | { |
5980 | nextarg = expand_builtin_saveregs (); | |
e5faf155 | 5981 | std_expand_builtin_va_start (valist, nextarg); |
ca5f4364 RH |
5982 | } |
5983 | ||
8101c928 | 5984 | static tree |
726a989a RB |
5985 | hppa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
5986 | gimple_seq *post_p) | |
ca5f4364 | 5987 | { |
520babc7 JL |
5988 | if (TARGET_64BIT) |
5989 | { | |
8101c928 | 5990 | /* Args grow upward. We can use the generic routines. */ |
af064de5 | 5991 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
ca5f4364 | 5992 | } |
9dff28ab | 5993 | else /* !TARGET_64BIT */ |
ca5f4364 | 5994 | { |
8101c928 RH |
5995 | tree ptr = build_pointer_type (type); |
5996 | tree valist_type; | |
5997 | tree t, u; | |
5998 | unsigned int size, ofs; | |
af064de5 | 5999 | bool indirect; |
ca5f4364 | 6000 | |
af064de5 | 6001 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0); |
8101c928 | 6002 | if (indirect) |
9dff28ab | 6003 | { |
8101c928 RH |
6004 | type = ptr; |
6005 | ptr = build_pointer_type (type); | |
ca5f4364 | 6006 | } |
8101c928 RH |
6007 | size = int_size_in_bytes (type); |
6008 | valist_type = TREE_TYPE (valist); | |
9dff28ab | 6009 | |
8101c928 | 6010 | /* Args grow down. Not handled by generic routines. */ |
9dff28ab | 6011 | |
5be014d5 AP |
6012 | u = fold_convert (sizetype, size_in_bytes (type)); |
6013 | u = fold_build1 (NEGATE_EXPR, sizetype, u); | |
6014 | t = build2 (POINTER_PLUS_EXPR, valist_type, valist, u); | |
9dff28ab | 6015 | |
8101c928 RH |
6016 | /* Copied from va-pa.h, but we probably don't need to align to |
6017 | word size, since we generate and preserve that invariant. */ | |
5be014d5 AP |
6018 | u = size_int (size > 4 ? -8 : -4); |
6019 | t = fold_convert (sizetype, t); | |
6020 | t = build2 (BIT_AND_EXPR, sizetype, t, u); | |
6021 | t = fold_convert (valist_type, t); | |
8101c928 | 6022 | |
66863d89 | 6023 | t = build2 (MODIFY_EXPR, valist_type, valist, t); |
ca5f4364 | 6024 | |
8101c928 RH |
6025 | ofs = (8 - size) % 4; |
6026 | if (ofs != 0) | |
6027 | { | |
5be014d5 AP |
6028 | u = size_int (ofs); |
6029 | t = build2 (POINTER_PLUS_EXPR, valist_type, t, u); | |
9dff28ab | 6030 | } |
ca5f4364 | 6031 | |
8101c928 | 6032 | t = fold_convert (ptr, t); |
d6e9821f | 6033 | t = build_va_arg_indirect_ref (t); |
ca5f4364 | 6034 | |
8101c928 | 6035 | if (indirect) |
d6e9821f | 6036 | t = build_va_arg_indirect_ref (t); |
ca5f4364 | 6037 | |
8101c928 RH |
6038 | return t; |
6039 | } | |
6040 | } | |
ca5f4364 | 6041 | |
83c32f2e JDA |
6042 | /* True if MODE is valid for the target. By "valid", we mean able to |
6043 | be manipulated in non-trivial ways. In particular, this means all | |
6044 | the arithmetic is supported. | |
6045 | ||
6046 | Currently, TImode is not valid as the HP 64-bit runtime documentation | |
6047 | doesn't document the alignment and calling conventions for this type. | |
6048 | Thus, we return false when PRECISION is 2 * BITS_PER_WORD and | |
6049 | 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */ | |
6050 | ||
6051 | static bool | |
6052 | pa_scalar_mode_supported_p (enum machine_mode mode) | |
6053 | { | |
6054 | int precision = GET_MODE_PRECISION (mode); | |
6055 | ||
6056 | switch (GET_MODE_CLASS (mode)) | |
6057 | { | |
6058 | case MODE_PARTIAL_INT: | |
6059 | case MODE_INT: | |
6060 | if (precision == CHAR_TYPE_SIZE) | |
6061 | return true; | |
6062 | if (precision == SHORT_TYPE_SIZE) | |
6063 | return true; | |
6064 | if (precision == INT_TYPE_SIZE) | |
6065 | return true; | |
6066 | if (precision == LONG_TYPE_SIZE) | |
6067 | return true; | |
6068 | if (precision == LONG_LONG_TYPE_SIZE) | |
6069 | return true; | |
6070 | return false; | |
6071 | ||
6072 | case MODE_FLOAT: | |
6073 | if (precision == FLOAT_TYPE_SIZE) | |
6074 | return true; | |
6075 | if (precision == DOUBLE_TYPE_SIZE) | |
6076 | return true; | |
6077 | if (precision == LONG_DOUBLE_TYPE_SIZE) | |
6078 | return true; | |
6079 | return false; | |
6080 | ||
70c1d012 JDA |
6081 | case MODE_DECIMAL_FLOAT: |
6082 | return false; | |
6083 | ||
83c32f2e JDA |
6084 | default: |
6085 | gcc_unreachable (); | |
6086 | } | |
6087 | } | |
6088 | ||
23f6f34f TG |
6089 | /* This routine handles all the normal conditional branch sequences we |
6090 | might need to generate. It handles compare immediate vs compare | |
6091 | register, nullification of delay slots, varying length branches, | |
d2364a74 | 6092 | negated branches, and all combinations of the above. It returns the |
23f6f34f | 6093 | output appropriate to emit the branch corresponding to all given |
d2364a74 JL |
6094 | parameters. */ |
6095 | ||
519104fe | 6096 | const char * |
16d74a3c | 6097 | output_cbranch (rtx *operands, int negated, rtx insn) |
b1a275e1 | 6098 | { |
d2364a74 JL |
6099 | static char buf[100]; |
6100 | int useskip = 0; | |
16d74a3c JDA |
6101 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6102 | int length = get_attr_length (insn); | |
6103 | int xdelay; | |
d2364a74 | 6104 | |
112cdef5 | 6105 | /* A conditional branch to the following instruction (e.g. the delay slot) |
02a57c73 JDA |
6106 | is asking for a disaster. This can happen when not optimizing and |
6107 | when jump optimization fails. | |
b1a275e1 | 6108 | |
7772f0a9 JDA |
6109 | While it is usually safe to emit nothing, this can fail if the |
6110 | preceding instruction is a nullified branch with an empty delay | |
6111 | slot and the same branch target as this branch. We could check | |
6112 | for this but jump optimization should eliminate nop jumps. It | |
6113 | is always safe to emit a nop. */ | |
02a57c73 JDA |
6114 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6115 | return "nop"; | |
23f6f34f | 6116 | |
ae2ea719 JDA |
6117 | /* The doubleword form of the cmpib instruction doesn't have the LEU |
6118 | and GTU conditions while the cmpb instruction does. Since we accept | |
6119 | zero for cmpb, we must ensure that we use cmpb for the comparison. */ | |
6120 | if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx) | |
6121 | operands[2] = gen_rtx_REG (DImode, 0); | |
9972f30d SE |
6122 | if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx) |
6123 | operands[1] = gen_rtx_REG (DImode, 0); | |
ae2ea719 | 6124 | |
b9821af8 JL |
6125 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6126 | as it can nullify the delay slot and save a nop. */ | |
a1b36964 | 6127 | if (length == 8 && dbr_sequence_length () == 0) |
b9821af8 JL |
6128 | nullify = 1; |
6129 | ||
6130 | /* If this is a short forward conditional branch which did not get | |
6131 | its delay slot filled, the delay slot can still be nullified. */ | |
a1b36964 | 6132 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
b9821af8 JL |
6133 | nullify = forward_branch_p (insn); |
6134 | ||
23f6f34f | 6135 | /* A forward branch over a single nullified insn can be done with a |
d2364a74 JL |
6136 | comclr instruction. This avoids a single cycle penalty due to |
6137 | mis-predicted branch if we fall through (branch not taken). */ | |
a1b36964 | 6138 | if (length == 4 |
b9821af8 | 6139 | && next_real_insn (insn) != 0 |
a1b36964 | 6140 | && get_attr_length (next_real_insn (insn)) == 4 |
b9821af8 | 6141 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
d2364a74 JL |
6142 | && nullify) |
6143 | useskip = 1; | |
6144 | ||
6145 | switch (length) | |
6146 | { | |
b9821af8 JL |
6147 | /* All short conditional branches except backwards with an unfilled |
6148 | delay slot. */ | |
a1b36964 | 6149 | case 4: |
d2364a74 | 6150 | if (useskip) |
f38b27c7 | 6151 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
d2364a74 | 6152 | else |
f38b27c7 | 6153 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
520babc7 JL |
6154 | if (GET_MODE (operands[1]) == DImode) |
6155 | strcat (buf, "*"); | |
d2364a74 JL |
6156 | if (negated) |
6157 | strcat (buf, "%B3"); | |
6158 | else | |
6159 | strcat (buf, "%S3"); | |
6160 | if (useskip) | |
3b5e5fb3 | 6161 | strcat (buf, " %2,%r1,%%r0"); |
d2364a74 | 6162 | else if (nullify) |
dcaeffef | 6163 | strcat (buf, ",n %2,%r1,%0"); |
23f6f34f | 6164 | else |
dcaeffef | 6165 | strcat (buf, " %2,%r1,%0"); |
d2364a74 JL |
6166 | break; |
6167 | ||
5bdc5878 | 6168 | /* All long conditionals. Note a short backward branch with an |
b9821af8 JL |
6169 | unfilled delay slot is treated just like a long backward branch |
6170 | with an unfilled delay slot. */ | |
a1b36964 | 6171 | case 8: |
b9821af8 | 6172 | /* Handle weird backwards branch with a filled delay slot |
16d74a3c | 6173 | which is nullified. */ |
b9821af8 JL |
6174 | if (dbr_sequence_length () != 0 |
6175 | && ! forward_branch_p (insn) | |
6176 | && nullify) | |
6177 | { | |
f38b27c7 | 6178 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
520babc7 JL |
6179 | if (GET_MODE (operands[1]) == DImode) |
6180 | strcat (buf, "*"); | |
b9821af8 JL |
6181 | if (negated) |
6182 | strcat (buf, "%S3"); | |
6183 | else | |
6184 | strcat (buf, "%B3"); | |
3b5e5fb3 | 6185 | strcat (buf, ",n %2,%r1,.+12\n\tb %0"); |
b9821af8 | 6186 | } |
923f781d JL |
6187 | /* Handle short backwards branch with an unfilled delay slot. |
6188 | Using a comb;nop rather than comiclr;bl saves 1 cycle for both | |
6189 | taken and untaken branches. */ | |
6190 | else if (dbr_sequence_length () == 0 | |
6191 | && ! forward_branch_p (insn) | |
9d98a694 AO |
6192 | && INSN_ADDRESSES_SET_P () |
6193 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6194 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
923f781d | 6195 | { |
f38b27c7 | 6196 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
520babc7 JL |
6197 | if (GET_MODE (operands[1]) == DImode) |
6198 | strcat (buf, "*"); | |
923f781d | 6199 | if (negated) |
dcaeffef | 6200 | strcat (buf, "%B3 %2,%r1,%0%#"); |
923f781d | 6201 | else |
dcaeffef | 6202 | strcat (buf, "%S3 %2,%r1,%0%#"); |
923f781d | 6203 | } |
d2364a74 | 6204 | else |
b9821af8 | 6205 | { |
f38b27c7 | 6206 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
520babc7 JL |
6207 | if (GET_MODE (operands[1]) == DImode) |
6208 | strcat (buf, "*"); | |
b9821af8 JL |
6209 | if (negated) |
6210 | strcat (buf, "%S3"); | |
6211 | else | |
6212 | strcat (buf, "%B3"); | |
6213 | if (nullify) | |
3b5e5fb3 | 6214 | strcat (buf, " %2,%r1,%%r0\n\tb,n %0"); |
b9821af8 | 6215 | else |
3b5e5fb3 | 6216 | strcat (buf, " %2,%r1,%%r0\n\tb %0"); |
b9821af8 | 6217 | } |
d2364a74 JL |
6218 | break; |
6219 | ||
16d74a3c | 6220 | default: |
685d0e07 | 6221 | /* The reversed conditional branch must branch over one additional |
16d74a3c JDA |
6222 | instruction if the delay slot is filled and needs to be extracted |
6223 | by output_lbranch. If the delay slot is empty or this is a | |
6224 | nullified forward branch, the instruction after the reversed | |
6225 | condition branch must be nullified. */ | |
6226 | if (dbr_sequence_length () == 0 | |
6227 | || (nullify && forward_branch_p (insn))) | |
6228 | { | |
6229 | nullify = 1; | |
6230 | xdelay = 0; | |
6231 | operands[4] = GEN_INT (length); | |
6232 | } | |
6233 | else | |
6234 | { | |
6235 | xdelay = 1; | |
6236 | operands[4] = GEN_INT (length + 4); | |
6237 | } | |
4bcb9e3f JL |
6238 | |
6239 | /* Create a reversed conditional branch which branches around | |
6240 | the following insns. */ | |
685d0e07 JDA |
6241 | if (GET_MODE (operands[1]) != DImode) |
6242 | { | |
6243 | if (nullify) | |
6244 | { | |
6245 | if (negated) | |
6246 | strcpy (buf, | |
6247 | "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}"); | |
6248 | else | |
6249 | strcpy (buf, | |
6250 | "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}"); | |
6251 | } | |
6252 | else | |
6253 | { | |
6254 | if (negated) | |
6255 | strcpy (buf, | |
6256 | "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}"); | |
6257 | else | |
6258 | strcpy (buf, | |
6259 | "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}"); | |
6260 | } | |
6261 | } | |
4bcb9e3f | 6262 | else |
520babc7 | 6263 | { |
685d0e07 JDA |
6264 | if (nullify) |
6265 | { | |
6266 | if (negated) | |
6267 | strcpy (buf, | |
6268 | "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}"); | |
6269 | else | |
6270 | strcpy (buf, | |
6271 | "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}"); | |
6272 | } | |
520babc7 | 6273 | else |
685d0e07 JDA |
6274 | { |
6275 | if (negated) | |
6276 | strcpy (buf, | |
6277 | "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}"); | |
6278 | else | |
6279 | strcpy (buf, | |
6280 | "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}"); | |
6281 | } | |
520babc7 | 6282 | } |
4bcb9e3f | 6283 | |
16d74a3c JDA |
6284 | output_asm_insn (buf, operands); |
6285 | return output_lbranch (operands[0], insn, xdelay); | |
685d0e07 JDA |
6286 | } |
6287 | return buf; | |
6288 | } | |
4bcb9e3f | 6289 | |
16d74a3c JDA |
6290 | /* This routine handles output of long unconditional branches that |
6291 | exceed the maximum range of a simple branch instruction. Since | |
6292 | we don't have a register available for the branch, we save register | |
6293 | %r1 in the frame marker, load the branch destination DEST into %r1, | |
6294 | execute the branch, and restore %r1 in the delay slot of the branch. | |
6295 | ||
6296 | Since long branches may have an insn in the delay slot and the | |
6297 | delay slot is used to restore %r1, we in general need to extract | |
6298 | this insn and execute it before the branch. However, to facilitate | |
6299 | use of this function by conditional branches, we also provide an | |
6300 | option to not extract the delay insn so that it will be emitted | |
6301 | after the long branch. So, if there is an insn in the delay slot, | |
6302 | it is extracted if XDELAY is nonzero. | |
6303 | ||
6304 | The lengths of the various long-branch sequences are 20, 16 and 24 | |
6305 | bytes for the portable runtime, non-PIC and PIC cases, respectively. */ | |
4bcb9e3f | 6306 | |
685d0e07 | 6307 | const char * |
16d74a3c | 6308 | output_lbranch (rtx dest, rtx insn, int xdelay) |
685d0e07 JDA |
6309 | { |
6310 | rtx xoperands[2]; | |
6311 | ||
6312 | xoperands[0] = dest; | |
4bcb9e3f | 6313 | |
685d0e07 | 6314 | /* First, free up the delay slot. */ |
16d74a3c | 6315 | if (xdelay && dbr_sequence_length () != 0) |
685d0e07 JDA |
6316 | { |
6317 | /* We can't handle a jump in the delay slot. */ | |
144d51f9 | 6318 | gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN); |
4bcb9e3f | 6319 | |
685d0e07 | 6320 | final_scan_insn (NEXT_INSN (insn), asm_out_file, |
c9d691e9 | 6321 | optimize, 0, NULL); |
4bcb9e3f | 6322 | |
685d0e07 | 6323 | /* Now delete the delay insn. */ |
a38e7aa5 | 6324 | SET_INSN_DELETED (NEXT_INSN (insn)); |
685d0e07 | 6325 | } |
4bcb9e3f | 6326 | |
685d0e07 JDA |
6327 | /* Output an insn to save %r1. The runtime documentation doesn't |
6328 | specify whether the "Clean Up" slot in the callers frame can | |
6329 | be clobbered by the callee. It isn't copied by HP's builtin | |
6330 | alloca, so this suggests that it can be clobbered if necessary. | |
6331 | The "Static Link" location is copied by HP builtin alloca, so | |
6332 | we avoid using it. Using the cleanup slot might be a problem | |
6333 | if we have to interoperate with languages that pass cleanup | |
6334 | information. However, it should be possible to handle these | |
6335 | situations with GCC's asm feature. | |
6336 | ||
6337 | The "Current RP" slot is reserved for the called procedure, so | |
6338 | we try to use it when we don't have a frame of our own. It's | |
6339 | rather unlikely that we won't have a frame when we need to emit | |
6340 | a very long branch. | |
6341 | ||
6342 | Really the way to go long term is a register scavenger; goto | |
6343 | the target of the jump and find a register which we can use | |
6344 | as a scratch to hold the value in %r1. Then, we wouldn't have | |
6345 | to free up the delay slot or clobber a slot that may be needed | |
6346 | for other purposes. */ | |
6347 | if (TARGET_64BIT) | |
6348 | { | |
6fb5fa3c | 6349 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
685d0e07 JDA |
6350 | /* Use the return pointer slot in the frame marker. */ |
6351 | output_asm_insn ("std %%r1,-16(%%r30)", xoperands); | |
6352 | else | |
6353 | /* Use the slot at -40 in the frame marker since HP builtin | |
6354 | alloca doesn't copy it. */ | |
6355 | output_asm_insn ("std %%r1,-40(%%r30)", xoperands); | |
6356 | } | |
6357 | else | |
6358 | { | |
6fb5fa3c | 6359 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
685d0e07 JDA |
6360 | /* Use the return pointer slot in the frame marker. */ |
6361 | output_asm_insn ("stw %%r1,-20(%%r30)", xoperands); | |
6362 | else | |
6363 | /* Use the "Clean Up" slot in the frame marker. In GCC, | |
6364 | the only other use of this location is for copying a | |
6365 | floating point double argument from a floating-point | |
6366 | register to two general registers. The copy is done | |
aa7f1eb1 | 6367 | as an "atomic" operation when outputting a call, so it |
685d0e07 JDA |
6368 | won't interfere with our using the location here. */ |
6369 | output_asm_insn ("stw %%r1,-12(%%r30)", xoperands); | |
6370 | } | |
3d9268b6 | 6371 | |
5fad1c24 JDA |
6372 | if (TARGET_PORTABLE_RUNTIME) |
6373 | { | |
6374 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6375 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
6376 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6377 | } | |
6378 | else if (flag_pic) | |
685d0e07 JDA |
6379 | { |
6380 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
6381 | if (TARGET_SOM || !TARGET_GAS) | |
6382 | { | |
6383 | xoperands[1] = gen_label_rtx (); | |
6384 | output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands); | |
ecc418c4 JDA |
6385 | targetm.asm_out.internal_label (asm_out_file, "L", |
6386 | CODE_LABEL_NUMBER (xoperands[1])); | |
685d0e07 | 6387 | output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands); |
4bcb9e3f | 6388 | } |
685d0e07 JDA |
6389 | else |
6390 | { | |
6391 | output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6392 | output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6393 | } | |
6394 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6395 | } | |
6396 | else | |
6397 | /* Now output a very long branch to the original target. */ | |
6398 | output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands); | |
4bcb9e3f | 6399 | |
685d0e07 JDA |
6400 | /* Now restore the value of %r1 in the delay slot. */ |
6401 | if (TARGET_64BIT) | |
6402 | { | |
6fb5fa3c | 6403 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
685d0e07 JDA |
6404 | return "ldd -16(%%r30),%%r1"; |
6405 | else | |
6406 | return "ldd -40(%%r30),%%r1"; | |
6407 | } | |
6408 | else | |
6409 | { | |
6fb5fa3c | 6410 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
685d0e07 JDA |
6411 | return "ldw -20(%%r30),%%r1"; |
6412 | else | |
6413 | return "ldw -12(%%r30),%%r1"; | |
b9821af8 | 6414 | } |
d2364a74 JL |
6415 | } |
6416 | ||
23f6f34f | 6417 | /* This routine handles all the branch-on-bit conditional branch sequences we |
d2364a74 JL |
6418 | might need to generate. It handles nullification of delay slots, |
6419 | varying length branches, negated branches and all combinations of the | |
6420 | above. it returns the appropriate output template to emit the branch. */ | |
6421 | ||
519104fe | 6422 | const char * |
16d74a3c | 6423 | output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
b1a275e1 | 6424 | { |
d2364a74 JL |
6425 | static char buf[100]; |
6426 | int useskip = 0; | |
16d74a3c JDA |
6427 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6428 | int length = get_attr_length (insn); | |
6429 | int xdelay; | |
d2364a74 | 6430 | |
112cdef5 | 6431 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
b1a275e1 | 6432 | asking for a disaster. I do not think this can happen as this pattern |
23f6f34f | 6433 | is only used when optimizing; jump optimization should eliminate the |
b1a275e1 | 6434 | jump. But be prepared just in case. */ |
23f6f34f | 6435 | |
02a57c73 JDA |
6436 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6437 | return "nop"; | |
23f6f34f | 6438 | |
b9821af8 JL |
6439 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6440 | as it can nullify the delay slot and save a nop. */ | |
a1b36964 | 6441 | if (length == 8 && dbr_sequence_length () == 0) |
b9821af8 JL |
6442 | nullify = 1; |
6443 | ||
6444 | /* If this is a short forward conditional branch which did not get | |
6445 | its delay slot filled, the delay slot can still be nullified. */ | |
a1b36964 | 6446 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
b9821af8 JL |
6447 | nullify = forward_branch_p (insn); |
6448 | ||
23f6f34f | 6449 | /* A forward branch over a single nullified insn can be done with a |
d2364a74 JL |
6450 | extrs instruction. This avoids a single cycle penalty due to |
6451 | mis-predicted branch if we fall through (branch not taken). */ | |
6452 | ||
a1b36964 | 6453 | if (length == 4 |
b9821af8 | 6454 | && next_real_insn (insn) != 0 |
a1b36964 | 6455 | && get_attr_length (next_real_insn (insn)) == 4 |
b9821af8 | 6456 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
d2364a74 JL |
6457 | && nullify) |
6458 | useskip = 1; | |
6459 | ||
6460 | switch (length) | |
6461 | { | |
6462 | ||
b9821af8 JL |
6463 | /* All short conditional branches except backwards with an unfilled |
6464 | delay slot. */ | |
a1b36964 | 6465 | case 4: |
d2364a74 | 6466 | if (useskip) |
f38b27c7 | 6467 | strcpy (buf, "{extrs,|extrw,s,}"); |
23f6f34f | 6468 | else |
d2364a74 | 6469 | strcpy (buf, "bb,"); |
520babc7 JL |
6470 | if (useskip && GET_MODE (operands[0]) == DImode) |
6471 | strcpy (buf, "extrd,s,*"); | |
6472 | else if (GET_MODE (operands[0]) == DImode) | |
6473 | strcpy (buf, "bb,*"); | |
d2364a74 JL |
6474 | if ((which == 0 && negated) |
6475 | || (which == 1 && ! negated)) | |
6476 | strcat (buf, ">="); | |
6477 | else | |
6478 | strcat (buf, "<"); | |
6479 | if (useskip) | |
3b5e5fb3 | 6480 | strcat (buf, " %0,%1,1,%%r0"); |
d2364a74 JL |
6481 | else if (nullify && negated) |
6482 | strcat (buf, ",n %0,%1,%3"); | |
6483 | else if (nullify && ! negated) | |
6484 | strcat (buf, ",n %0,%1,%2"); | |
6485 | else if (! nullify && negated) | |
b9821af8 | 6486 | strcat (buf, "%0,%1,%3"); |
d2364a74 | 6487 | else if (! nullify && ! negated) |
b9821af8 | 6488 | strcat (buf, " %0,%1,%2"); |
d2364a74 JL |
6489 | break; |
6490 | ||
5bdc5878 | 6491 | /* All long conditionals. Note a short backward branch with an |
b9821af8 JL |
6492 | unfilled delay slot is treated just like a long backward branch |
6493 | with an unfilled delay slot. */ | |
a1b36964 | 6494 | case 8: |
b9821af8 | 6495 | /* Handle weird backwards branch with a filled delay slot |
16d74a3c | 6496 | which is nullified. */ |
b9821af8 JL |
6497 | if (dbr_sequence_length () != 0 |
6498 | && ! forward_branch_p (insn) | |
6499 | && nullify) | |
6500 | { | |
6501 | strcpy (buf, "bb,"); | |
520babc7 JL |
6502 | if (GET_MODE (operands[0]) == DImode) |
6503 | strcat (buf, "*"); | |
b9821af8 JL |
6504 | if ((which == 0 && negated) |
6505 | || (which == 1 && ! negated)) | |
6506 | strcat (buf, "<"); | |
6507 | else | |
6508 | strcat (buf, ">="); | |
6509 | if (negated) | |
3b5e5fb3 | 6510 | strcat (buf, ",n %0,%1,.+12\n\tb %3"); |
b9821af8 | 6511 | else |
3b5e5fb3 | 6512 | strcat (buf, ",n %0,%1,.+12\n\tb %2"); |
b9821af8 | 6513 | } |
923f781d JL |
6514 | /* Handle short backwards branch with an unfilled delay slot. |
6515 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6516 | taken and untaken branches. */ | |
6517 | else if (dbr_sequence_length () == 0 | |
6518 | && ! forward_branch_p (insn) | |
9d98a694 AO |
6519 | && INSN_ADDRESSES_SET_P () |
6520 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6521 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
923f781d JL |
6522 | { |
6523 | strcpy (buf, "bb,"); | |
520babc7 JL |
6524 | if (GET_MODE (operands[0]) == DImode) |
6525 | strcat (buf, "*"); | |
923f781d JL |
6526 | if ((which == 0 && negated) |
6527 | || (which == 1 && ! negated)) | |
6528 | strcat (buf, ">="); | |
6529 | else | |
6530 | strcat (buf, "<"); | |
6531 | if (negated) | |
6532 | strcat (buf, " %0,%1,%3%#"); | |
6533 | else | |
6534 | strcat (buf, " %0,%1,%2%#"); | |
6535 | } | |
d2364a74 | 6536 | else |
b9821af8 | 6537 | { |
520babc7 JL |
6538 | if (GET_MODE (operands[0]) == DImode) |
6539 | strcpy (buf, "extrd,s,*"); | |
16d74a3c JDA |
6540 | else |
6541 | strcpy (buf, "{extrs,|extrw,s,}"); | |
b9821af8 JL |
6542 | if ((which == 0 && negated) |
6543 | || (which == 1 && ! negated)) | |
6544 | strcat (buf, "<"); | |
6545 | else | |
6546 | strcat (buf, ">="); | |
6547 | if (nullify && negated) | |
55abf18a | 6548 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %3"); |
b9821af8 | 6549 | else if (nullify && ! negated) |
55abf18a | 6550 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %2"); |
b9821af8 | 6551 | else if (negated) |
3b5e5fb3 | 6552 | strcat (buf, " %0,%1,1,%%r0\n\tb %3"); |
23f6f34f | 6553 | else |
3b5e5fb3 | 6554 | strcat (buf, " %0,%1,1,%%r0\n\tb %2"); |
b9821af8 | 6555 | } |
d2364a74 JL |
6556 | break; |
6557 | ||
6558 | default: | |
16d74a3c JDA |
6559 | /* The reversed conditional branch must branch over one additional |
6560 | instruction if the delay slot is filled and needs to be extracted | |
6561 | by output_lbranch. If the delay slot is empty or this is a | |
6562 | nullified forward branch, the instruction after the reversed | |
6563 | condition branch must be nullified. */ | |
6564 | if (dbr_sequence_length () == 0 | |
6565 | || (nullify && forward_branch_p (insn))) | |
6566 | { | |
6567 | nullify = 1; | |
6568 | xdelay = 0; | |
8370f6fa | 6569 | operands[4] = GEN_INT (length); |
16d74a3c JDA |
6570 | } |
6571 | else | |
6572 | { | |
6573 | xdelay = 1; | |
8370f6fa | 6574 | operands[4] = GEN_INT (length + 4); |
16d74a3c JDA |
6575 | } |
6576 | ||
6577 | if (GET_MODE (operands[0]) == DImode) | |
8370f6fa | 6578 | strcpy (buf, "bb,*"); |
16d74a3c | 6579 | else |
8370f6fa | 6580 | strcpy (buf, "bb,"); |
16d74a3c JDA |
6581 | if ((which == 0 && negated) |
6582 | || (which == 1 && !negated)) | |
8370f6fa | 6583 | strcat (buf, "<"); |
16d74a3c | 6584 | else |
8370f6fa | 6585 | strcat (buf, ">="); |
16d74a3c | 6586 | if (nullify) |
8370f6fa | 6587 | strcat (buf, ",n %0,%1,.+%4"); |
16d74a3c | 6588 | else |
8370f6fa | 6589 | strcat (buf, " %0,%1,.+%4"); |
16d74a3c JDA |
6590 | output_asm_insn (buf, operands); |
6591 | return output_lbranch (negated ? operands[3] : operands[2], | |
6592 | insn, xdelay); | |
b9821af8 | 6593 | } |
d2364a74 JL |
6594 | return buf; |
6595 | } | |
6596 | ||
6a73009d JL |
6597 | /* This routine handles all the branch-on-variable-bit conditional branch |
6598 | sequences we might need to generate. It handles nullification of delay | |
6599 | slots, varying length branches, negated branches and all combinations | |
6600 | of the above. it returns the appropriate output template to emit the | |
6601 | branch. */ | |
6602 | ||
519104fe | 6603 | const char * |
16d74a3c | 6604 | output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
6a73009d JL |
6605 | { |
6606 | static char buf[100]; | |
6607 | int useskip = 0; | |
16d74a3c JDA |
6608 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6609 | int length = get_attr_length (insn); | |
6610 | int xdelay; | |
6a73009d | 6611 | |
112cdef5 | 6612 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
6a73009d JL |
6613 | asking for a disaster. I do not think this can happen as this pattern |
6614 | is only used when optimizing; jump optimization should eliminate the | |
6615 | jump. But be prepared just in case. */ | |
6616 | ||
02a57c73 JDA |
6617 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6618 | return "nop"; | |
6a73009d JL |
6619 | |
6620 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6621 | as it can nullify the delay slot and save a nop. */ | |
6622 | if (length == 8 && dbr_sequence_length () == 0) | |
6623 | nullify = 1; | |
6624 | ||
6625 | /* If this is a short forward conditional branch which did not get | |
6626 | its delay slot filled, the delay slot can still be nullified. */ | |
6627 | if (! nullify && length == 4 && dbr_sequence_length () == 0) | |
6628 | nullify = forward_branch_p (insn); | |
6629 | ||
6630 | /* A forward branch over a single nullified insn can be done with a | |
6631 | extrs instruction. This avoids a single cycle penalty due to | |
6632 | mis-predicted branch if we fall through (branch not taken). */ | |
6633 | ||
6634 | if (length == 4 | |
6635 | && next_real_insn (insn) != 0 | |
6636 | && get_attr_length (next_real_insn (insn)) == 4 | |
6637 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) | |
6638 | && nullify) | |
6639 | useskip = 1; | |
6640 | ||
6641 | switch (length) | |
6642 | { | |
6643 | ||
6644 | /* All short conditional branches except backwards with an unfilled | |
6645 | delay slot. */ | |
6646 | case 4: | |
6647 | if (useskip) | |
f38b27c7 | 6648 | strcpy (buf, "{vextrs,|extrw,s,}"); |
6a73009d | 6649 | else |
f38b27c7 | 6650 | strcpy (buf, "{bvb,|bb,}"); |
520babc7 | 6651 | if (useskip && GET_MODE (operands[0]) == DImode) |
e72ed000 | 6652 | strcpy (buf, "extrd,s,*"); |
520babc7 JL |
6653 | else if (GET_MODE (operands[0]) == DImode) |
6654 | strcpy (buf, "bb,*"); | |
6a73009d JL |
6655 | if ((which == 0 && negated) |
6656 | || (which == 1 && ! negated)) | |
6657 | strcat (buf, ">="); | |
6658 | else | |
6659 | strcat (buf, "<"); | |
6660 | if (useskip) | |
f38b27c7 | 6661 | strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}"); |
6a73009d | 6662 | else if (nullify && negated) |
f38b27c7 | 6663 | strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}"); |
6a73009d | 6664 | else if (nullify && ! negated) |
f38b27c7 | 6665 | strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}"); |
6a73009d | 6666 | else if (! nullify && negated) |
f38b27c7 | 6667 | strcat (buf, "{%0,%3|%0,%%sar,%3}"); |
6a73009d | 6668 | else if (! nullify && ! negated) |
f38b27c7 | 6669 | strcat (buf, "{ %0,%2| %0,%%sar,%2}"); |
6a73009d JL |
6670 | break; |
6671 | ||
5bdc5878 | 6672 | /* All long conditionals. Note a short backward branch with an |
6a73009d JL |
6673 | unfilled delay slot is treated just like a long backward branch |
6674 | with an unfilled delay slot. */ | |
6675 | case 8: | |
6676 | /* Handle weird backwards branch with a filled delay slot | |
16d74a3c | 6677 | which is nullified. */ |
6a73009d JL |
6678 | if (dbr_sequence_length () != 0 |
6679 | && ! forward_branch_p (insn) | |
6680 | && nullify) | |
6681 | { | |
f38b27c7 | 6682 | strcpy (buf, "{bvb,|bb,}"); |
520babc7 JL |
6683 | if (GET_MODE (operands[0]) == DImode) |
6684 | strcat (buf, "*"); | |
6a73009d JL |
6685 | if ((which == 0 && negated) |
6686 | || (which == 1 && ! negated)) | |
6687 | strcat (buf, "<"); | |
6688 | else | |
6689 | strcat (buf, ">="); | |
6690 | if (negated) | |
f38b27c7 | 6691 | strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}"); |
6a73009d | 6692 | else |
f38b27c7 | 6693 | strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}"); |
6a73009d JL |
6694 | } |
6695 | /* Handle short backwards branch with an unfilled delay slot. | |
6696 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6697 | taken and untaken branches. */ | |
6698 | else if (dbr_sequence_length () == 0 | |
6699 | && ! forward_branch_p (insn) | |
9d98a694 AO |
6700 | && INSN_ADDRESSES_SET_P () |
6701 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6702 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
6a73009d | 6703 | { |
f38b27c7 | 6704 | strcpy (buf, "{bvb,|bb,}"); |
520babc7 JL |
6705 | if (GET_MODE (operands[0]) == DImode) |
6706 | strcat (buf, "*"); | |
6a73009d JL |
6707 | if ((which == 0 && negated) |
6708 | || (which == 1 && ! negated)) | |
6709 | strcat (buf, ">="); | |
6710 | else | |
6711 | strcat (buf, "<"); | |
6712 | if (negated) | |
f38b27c7 | 6713 | strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}"); |
6a73009d | 6714 | else |
f38b27c7 | 6715 | strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}"); |
6a73009d JL |
6716 | } |
6717 | else | |
6718 | { | |
f38b27c7 | 6719 | strcpy (buf, "{vextrs,|extrw,s,}"); |
520babc7 JL |
6720 | if (GET_MODE (operands[0]) == DImode) |
6721 | strcpy (buf, "extrd,s,*"); | |
6a73009d JL |
6722 | if ((which == 0 && negated) |
6723 | || (which == 1 && ! negated)) | |
6724 | strcat (buf, "<"); | |
6725 | else | |
6726 | strcat (buf, ">="); | |
6727 | if (nullify && negated) | |
f38b27c7 | 6728 | strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}"); |
6a73009d | 6729 | else if (nullify && ! negated) |
f38b27c7 | 6730 | strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}"); |
6a73009d | 6731 | else if (negated) |
f38b27c7 | 6732 | strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}"); |
6a73009d | 6733 | else |
f38b27c7 | 6734 | strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}"); |
6a73009d JL |
6735 | } |
6736 | break; | |
6737 | ||
6738 | default: | |
16d74a3c JDA |
6739 | /* The reversed conditional branch must branch over one additional |
6740 | instruction if the delay slot is filled and needs to be extracted | |
6741 | by output_lbranch. If the delay slot is empty or this is a | |
6742 | nullified forward branch, the instruction after the reversed | |
6743 | condition branch must be nullified. */ | |
6744 | if (dbr_sequence_length () == 0 | |
6745 | || (nullify && forward_branch_p (insn))) | |
6746 | { | |
6747 | nullify = 1; | |
6748 | xdelay = 0; | |
8370f6fa | 6749 | operands[4] = GEN_INT (length); |
16d74a3c JDA |
6750 | } |
6751 | else | |
6752 | { | |
6753 | xdelay = 1; | |
8370f6fa | 6754 | operands[4] = GEN_INT (length + 4); |
16d74a3c JDA |
6755 | } |
6756 | ||
6757 | if (GET_MODE (operands[0]) == DImode) | |
8370f6fa | 6758 | strcpy (buf, "bb,*"); |
16d74a3c | 6759 | else |
8370f6fa | 6760 | strcpy (buf, "{bvb,|bb,}"); |
16d74a3c JDA |
6761 | if ((which == 0 && negated) |
6762 | || (which == 1 && !negated)) | |
8370f6fa | 6763 | strcat (buf, "<"); |
16d74a3c | 6764 | else |
8370f6fa | 6765 | strcat (buf, ">="); |
16d74a3c | 6766 | if (nullify) |
8370f6fa | 6767 | strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}"); |
16d74a3c | 6768 | else |
8370f6fa | 6769 | strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}"); |
16d74a3c JDA |
6770 | output_asm_insn (buf, operands); |
6771 | return output_lbranch (negated ? operands[3] : operands[2], | |
6772 | insn, xdelay); | |
6a73009d JL |
6773 | } |
6774 | return buf; | |
6775 | } | |
6776 | ||
b1a275e1 JL |
6777 | /* Return the output template for emitting a dbra type insn. |
6778 | ||
6779 | Note it may perform some output operations on its own before | |
6780 | returning the final output string. */ | |
519104fe | 6781 | const char * |
b7849684 | 6782 | output_dbra (rtx *operands, rtx insn, int which_alternative) |
b1a275e1 | 6783 | { |
16d74a3c | 6784 | int length = get_attr_length (insn); |
b1a275e1 | 6785 | |
112cdef5 | 6786 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
b1a275e1 JL |
6787 | asking for a disaster. Be prepared! */ |
6788 | ||
02a57c73 | 6789 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
b1a275e1 JL |
6790 | { |
6791 | if (which_alternative == 0) | |
6792 | return "ldo %1(%0),%0"; | |
6793 | else if (which_alternative == 1) | |
6794 | { | |
831c1763 AM |
6795 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands); |
6796 | output_asm_insn ("ldw -16(%%r30),%4", operands); | |
d2d28085 | 6797 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
f38b27c7 | 6798 | return "{fldws|fldw} -16(%%r30),%0"; |
b1a275e1 JL |
6799 | } |
6800 | else | |
6801 | { | |
6802 | output_asm_insn ("ldw %0,%4", operands); | |
6803 | return "ldo %1(%4),%4\n\tstw %4,%0"; | |
6804 | } | |
6805 | } | |
6806 | ||
6807 | if (which_alternative == 0) | |
6808 | { | |
6809 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
16d74a3c | 6810 | int xdelay; |
b1a275e1 JL |
6811 | |
6812 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6813 | as it can nullify the delay slot and save a nop. */ | |
a1b36964 | 6814 | if (length == 8 && dbr_sequence_length () == 0) |
b1a275e1 JL |
6815 | nullify = 1; |
6816 | ||
6817 | /* If this is a short forward conditional branch which did not get | |
6818 | its delay slot filled, the delay slot can still be nullified. */ | |
a1b36964 | 6819 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
b1a275e1 JL |
6820 | nullify = forward_branch_p (insn); |
6821 | ||
144d51f9 | 6822 | switch (length) |
b1a275e1 | 6823 | { |
144d51f9 NS |
6824 | case 4: |
6825 | if (nullify) | |
6826 | return "addib,%C2,n %1,%0,%3"; | |
6827 | else | |
6828 | return "addib,%C2 %1,%0,%3"; | |
6829 | ||
6830 | case 8: | |
23f6f34f | 6831 | /* Handle weird backwards branch with a fulled delay slot |
b1a275e1 JL |
6832 | which is nullified. */ |
6833 | if (dbr_sequence_length () != 0 | |
6834 | && ! forward_branch_p (insn) | |
6835 | && nullify) | |
3b5e5fb3 | 6836 | return "addib,%N2,n %1,%0,.+12\n\tb %3"; |
923f781d JL |
6837 | /* Handle short backwards branch with an unfilled delay slot. |
6838 | Using a addb;nop rather than addi;bl saves 1 cycle for both | |
6839 | taken and untaken branches. */ | |
6840 | else if (dbr_sequence_length () == 0 | |
6841 | && ! forward_branch_p (insn) | |
9d98a694 AO |
6842 | && INSN_ADDRESSES_SET_P () |
6843 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6844 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
923f781d | 6845 | return "addib,%C2 %1,%0,%3%#"; |
23f6f34f TG |
6846 | |
6847 | /* Handle normal cases. */ | |
b1a275e1 | 6848 | if (nullify) |
3b5e5fb3 | 6849 | return "addi,%N2 %1,%0,%0\n\tb,n %3"; |
b1a275e1 | 6850 | else |
3b5e5fb3 | 6851 | return "addi,%N2 %1,%0,%0\n\tb %3"; |
144d51f9 NS |
6852 | |
6853 | default: | |
16d74a3c JDA |
6854 | /* The reversed conditional branch must branch over one additional |
6855 | instruction if the delay slot is filled and needs to be extracted | |
6856 | by output_lbranch. If the delay slot is empty or this is a | |
6857 | nullified forward branch, the instruction after the reversed | |
6858 | condition branch must be nullified. */ | |
6859 | if (dbr_sequence_length () == 0 | |
6860 | || (nullify && forward_branch_p (insn))) | |
6861 | { | |
6862 | nullify = 1; | |
6863 | xdelay = 0; | |
6864 | operands[4] = GEN_INT (length); | |
6865 | } | |
6866 | else | |
6867 | { | |
6868 | xdelay = 1; | |
6869 | operands[4] = GEN_INT (length + 4); | |
6870 | } | |
6871 | ||
6872 | if (nullify) | |
6873 | output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands); | |
6874 | else | |
6875 | output_asm_insn ("addib,%N2 %1,%0,.+%4", operands); | |
6876 | ||
6877 | return output_lbranch (operands[3], insn, xdelay); | |
b1a275e1 | 6878 | } |
144d51f9 | 6879 | |
b1a275e1 JL |
6880 | } |
6881 | /* Deal with gross reload from FP register case. */ | |
6882 | else if (which_alternative == 1) | |
6883 | { | |
6884 | /* Move loop counter from FP register to MEM then into a GR, | |
6885 | increment the GR, store the GR into MEM, and finally reload | |
23f6f34f | 6886 | the FP register from MEM from within the branch's delay slot. */ |
831c1763 AM |
6887 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4", |
6888 | operands); | |
d2d28085 | 6889 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
16d74a3c | 6890 | if (length == 24) |
f38b27c7 | 6891 | return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
16d74a3c | 6892 | else if (length == 28) |
f38b27c7 | 6893 | return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
16d74a3c JDA |
6894 | else |
6895 | { | |
8370f6fa JDA |
6896 | operands[5] = GEN_INT (length - 16); |
6897 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands); | |
16d74a3c JDA |
6898 | output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands); |
6899 | return output_lbranch (operands[3], insn, 0); | |
6900 | } | |
b1a275e1 JL |
6901 | } |
6902 | /* Deal with gross reload from memory case. */ | |
6903 | else | |
6904 | { | |
6905 | /* Reload loop counter from memory, the store back to memory | |
71cc389b | 6906 | happens in the branch's delay slot. */ |
b1a275e1 | 6907 | output_asm_insn ("ldw %0,%4", operands); |
16d74a3c | 6908 | if (length == 12) |
b1a275e1 | 6909 | return "addib,%C2 %1,%4,%3\n\tstw %4,%0"; |
16d74a3c | 6910 | else if (length == 16) |
3b5e5fb3 | 6911 | return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0"; |
16d74a3c JDA |
6912 | else |
6913 | { | |
8370f6fa JDA |
6914 | operands[5] = GEN_INT (length - 4); |
6915 | output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands); | |
16d74a3c JDA |
6916 | return output_lbranch (operands[3], insn, 0); |
6917 | } | |
b1a275e1 JL |
6918 | } |
6919 | } | |
6920 | ||
16d74a3c | 6921 | /* Return the output template for emitting a movb type insn. |
b1a275e1 JL |
6922 | |
6923 | Note it may perform some output operations on its own before | |
6924 | returning the final output string. */ | |
519104fe | 6925 | const char * |
b7849684 JE |
6926 | output_movb (rtx *operands, rtx insn, int which_alternative, |
6927 | int reverse_comparison) | |
b1a275e1 | 6928 | { |
16d74a3c | 6929 | int length = get_attr_length (insn); |
b1a275e1 | 6930 | |
112cdef5 | 6931 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
b1a275e1 JL |
6932 | asking for a disaster. Be prepared! */ |
6933 | ||
02a57c73 | 6934 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
b1a275e1 JL |
6935 | { |
6936 | if (which_alternative == 0) | |
6937 | return "copy %1,%0"; | |
6938 | else if (which_alternative == 1) | |
6939 | { | |
831c1763 | 6940 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
f38b27c7 | 6941 | return "{fldws|fldw} -16(%%r30),%0"; |
b1a275e1 | 6942 | } |
b1092901 | 6943 | else if (which_alternative == 2) |
b1a275e1 | 6944 | return "stw %1,%0"; |
b1092901 JL |
6945 | else |
6946 | return "mtsar %r1"; | |
b1a275e1 JL |
6947 | } |
6948 | ||
6949 | /* Support the second variant. */ | |
6950 | if (reverse_comparison) | |
6951 | PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2]))); | |
6952 | ||
6953 | if (which_alternative == 0) | |
6954 | { | |
6955 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
16d74a3c | 6956 | int xdelay; |
b1a275e1 JL |
6957 | |
6958 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6959 | as it can nullify the delay slot and save a nop. */ | |
a1b36964 | 6960 | if (length == 8 && dbr_sequence_length () == 0) |
b1a275e1 JL |
6961 | nullify = 1; |
6962 | ||
6963 | /* If this is a short forward conditional branch which did not get | |
6964 | its delay slot filled, the delay slot can still be nullified. */ | |
a1b36964 | 6965 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
b1a275e1 JL |
6966 | nullify = forward_branch_p (insn); |
6967 | ||
144d51f9 | 6968 | switch (length) |
b1a275e1 | 6969 | { |
144d51f9 NS |
6970 | case 4: |
6971 | if (nullify) | |
6972 | return "movb,%C2,n %1,%0,%3"; | |
6973 | else | |
6974 | return "movb,%C2 %1,%0,%3"; | |
6975 | ||
6976 | case 8: | |
23f6f34f | 6977 | /* Handle weird backwards branch with a filled delay slot |
b1a275e1 JL |
6978 | which is nullified. */ |
6979 | if (dbr_sequence_length () != 0 | |
6980 | && ! forward_branch_p (insn) | |
6981 | && nullify) | |
3b5e5fb3 | 6982 | return "movb,%N2,n %1,%0,.+12\n\tb %3"; |
23f6f34f | 6983 | |
923f781d JL |
6984 | /* Handle short backwards branch with an unfilled delay slot. |
6985 | Using a movb;nop rather than or;bl saves 1 cycle for both | |
6986 | taken and untaken branches. */ | |
6987 | else if (dbr_sequence_length () == 0 | |
6988 | && ! forward_branch_p (insn) | |
9d98a694 AO |
6989 | && INSN_ADDRESSES_SET_P () |
6990 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6991 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
923f781d | 6992 | return "movb,%C2 %1,%0,%3%#"; |
23f6f34f | 6993 | /* Handle normal cases. */ |
b1a275e1 | 6994 | if (nullify) |
3b5e5fb3 | 6995 | return "or,%N2 %1,%%r0,%0\n\tb,n %3"; |
b1a275e1 | 6996 | else |
3b5e5fb3 | 6997 | return "or,%N2 %1,%%r0,%0\n\tb %3"; |
144d51f9 NS |
6998 | |
6999 | default: | |
16d74a3c JDA |
7000 | /* The reversed conditional branch must branch over one additional |
7001 | instruction if the delay slot is filled and needs to be extracted | |
7002 | by output_lbranch. If the delay slot is empty or this is a | |
7003 | nullified forward branch, the instruction after the reversed | |
7004 | condition branch must be nullified. */ | |
7005 | if (dbr_sequence_length () == 0 | |
7006 | || (nullify && forward_branch_p (insn))) | |
7007 | { | |
7008 | nullify = 1; | |
7009 | xdelay = 0; | |
7010 | operands[4] = GEN_INT (length); | |
7011 | } | |
7012 | else | |
7013 | { | |
7014 | xdelay = 1; | |
7015 | operands[4] = GEN_INT (length + 4); | |
7016 | } | |
7017 | ||
7018 | if (nullify) | |
7019 | output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands); | |
7020 | else | |
7021 | output_asm_insn ("movb,%N2 %1,%0,.+%4", operands); | |
7022 | ||
7023 | return output_lbranch (operands[3], insn, xdelay); | |
b1a275e1 | 7024 | } |
b1a275e1 | 7025 | } |
16d74a3c | 7026 | /* Deal with gross reload for FP destination register case. */ |
b1a275e1 JL |
7027 | else if (which_alternative == 1) |
7028 | { | |
16d74a3c JDA |
7029 | /* Move source register to MEM, perform the branch test, then |
7030 | finally load the FP register from MEM from within the branch's | |
7031 | delay slot. */ | |
831c1763 | 7032 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
16d74a3c | 7033 | if (length == 12) |
f38b27c7 | 7034 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
16d74a3c | 7035 | else if (length == 16) |
f38b27c7 | 7036 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
16d74a3c JDA |
7037 | else |
7038 | { | |
8370f6fa JDA |
7039 | operands[4] = GEN_INT (length - 4); |
7040 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands); | |
16d74a3c JDA |
7041 | output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands); |
7042 | return output_lbranch (operands[3], insn, 0); | |
7043 | } | |
b1a275e1 JL |
7044 | } |
7045 | /* Deal with gross reload from memory case. */ | |
b1092901 | 7046 | else if (which_alternative == 2) |
b1a275e1 JL |
7047 | { |
7048 | /* Reload loop counter from memory, the store back to memory | |
71cc389b | 7049 | happens in the branch's delay slot. */ |
16d74a3c | 7050 | if (length == 8) |
f38b27c7 | 7051 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0"; |
16d74a3c | 7052 | else if (length == 12) |
f38b27c7 | 7053 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0"; |
16d74a3c JDA |
7054 | else |
7055 | { | |
8370f6fa JDA |
7056 | operands[4] = GEN_INT (length); |
7057 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0", | |
7058 | operands); | |
16d74a3c JDA |
7059 | return output_lbranch (operands[3], insn, 0); |
7060 | } | |
b1a275e1 | 7061 | } |
b1092901 JL |
7062 | /* Handle SAR as a destination. */ |
7063 | else | |
7064 | { | |
16d74a3c | 7065 | if (length == 8) |
f38b27c7 | 7066 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1"; |
16d74a3c | 7067 | else if (length == 12) |
715ab8c3 | 7068 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1"; |
16d74a3c JDA |
7069 | else |
7070 | { | |
8370f6fa JDA |
7071 | operands[4] = GEN_INT (length); |
7072 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1", | |
7073 | operands); | |
16d74a3c JDA |
7074 | return output_lbranch (operands[3], insn, 0); |
7075 | } | |
b1092901 | 7076 | } |
b1a275e1 JL |
7077 | } |
7078 | ||
a02aa5b0 JDA |
7079 | /* Copy any FP arguments in INSN into integer registers. */ |
7080 | static void | |
b7849684 | 7081 | copy_fp_args (rtx insn) |
a02aa5b0 JDA |
7082 | { |
7083 | rtx link; | |
7084 | rtx xoperands[2]; | |
b1a275e1 | 7085 | |
a02aa5b0 JDA |
7086 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
7087 | { | |
7088 | int arg_mode, regno; | |
7089 | rtx use = XEXP (link, 0); | |
f726ea7d | 7090 | |
a02aa5b0 JDA |
7091 | if (! (GET_CODE (use) == USE |
7092 | && GET_CODE (XEXP (use, 0)) == REG | |
7093 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
7094 | continue; | |
2c4ff308 | 7095 | |
a02aa5b0 JDA |
7096 | arg_mode = GET_MODE (XEXP (use, 0)); |
7097 | regno = REGNO (XEXP (use, 0)); | |
520babc7 | 7098 | |
a02aa5b0 JDA |
7099 | /* Is it a floating point register? */ |
7100 | if (regno >= 32 && regno <= 39) | |
7101 | { | |
7102 | /* Copy the FP register into an integer register via memory. */ | |
7103 | if (arg_mode == SFmode) | |
7104 | { | |
7105 | xoperands[0] = XEXP (use, 0); | |
7106 | xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2); | |
7107 | output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands); | |
7108 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
7109 | } | |
7110 | else | |
7111 | { | |
7112 | xoperands[0] = XEXP (use, 0); | |
7113 | xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2); | |
7114 | output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands); | |
7115 | output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands); | |
7116 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
7117 | } | |
7118 | } | |
279c9bde | 7119 | } |
a02aa5b0 JDA |
7120 | } |
7121 | ||
7122 | /* Compute length of the FP argument copy sequence for INSN. */ | |
7123 | static int | |
b7849684 | 7124 | length_fp_args (rtx insn) |
a02aa5b0 JDA |
7125 | { |
7126 | int length = 0; | |
7127 | rtx link; | |
279c9bde | 7128 | |
a02aa5b0 | 7129 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
6a73009d | 7130 | { |
a02aa5b0 JDA |
7131 | int arg_mode, regno; |
7132 | rtx use = XEXP (link, 0); | |
7133 | ||
7134 | if (! (GET_CODE (use) == USE | |
7135 | && GET_CODE (XEXP (use, 0)) == REG | |
7136 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
7137 | continue; | |
6a73009d | 7138 | |
a02aa5b0 JDA |
7139 | arg_mode = GET_MODE (XEXP (use, 0)); |
7140 | regno = REGNO (XEXP (use, 0)); | |
7141 | ||
7142 | /* Is it a floating point register? */ | |
7143 | if (regno >= 32 && regno <= 39) | |
6a73009d | 7144 | { |
a02aa5b0 JDA |
7145 | if (arg_mode == SFmode) |
7146 | length += 8; | |
7147 | else | |
7148 | length += 12; | |
6a73009d | 7149 | } |
a02aa5b0 | 7150 | } |
6a73009d | 7151 | |
a02aa5b0 JDA |
7152 | return length; |
7153 | } | |
3d9268b6 | 7154 | |
611ad29e JDA |
7155 | /* Return the attribute length for the millicode call instruction INSN. |
7156 | The length must match the code generated by output_millicode_call. | |
7157 | We include the delay slot in the returned length as it is better to | |
a02aa5b0 | 7158 | over estimate the length than to under estimate it. */ |
a7721dc0 | 7159 | |
a02aa5b0 | 7160 | int |
b7849684 | 7161 | attr_length_millicode_call (rtx insn) |
a02aa5b0 | 7162 | { |
611ad29e | 7163 | unsigned long distance = -1; |
62910663 | 7164 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
a02aa5b0 | 7165 | |
611ad29e JDA |
7166 | if (INSN_ADDRESSES_SET_P ()) |
7167 | { | |
5fad1c24 JDA |
7168 | distance = (total + insn_current_reference_address (insn)); |
7169 | if (distance < total) | |
611ad29e JDA |
7170 | distance = -1; |
7171 | } | |
a02aa5b0 JDA |
7172 | |
7173 | if (TARGET_64BIT) | |
7174 | { | |
7175 | if (!TARGET_LONG_CALLS && distance < 7600000) | |
611ad29e | 7176 | return 8; |
a02aa5b0 | 7177 | |
611ad29e | 7178 | return 20; |
a02aa5b0 JDA |
7179 | } |
7180 | else if (TARGET_PORTABLE_RUNTIME) | |
611ad29e | 7181 | return 24; |
a02aa5b0 JDA |
7182 | else |
7183 | { | |
7184 | if (!TARGET_LONG_CALLS && distance < 240000) | |
611ad29e | 7185 | return 8; |
a02aa5b0 JDA |
7186 | |
7187 | if (TARGET_LONG_ABS_CALL && !flag_pic) | |
611ad29e | 7188 | return 12; |
a02aa5b0 | 7189 | |
611ad29e | 7190 | return 24; |
a02aa5b0 JDA |
7191 | } |
7192 | } | |
7193 | ||
7194 | /* INSN is a function call. It may have an unconditional jump | |
7195 | in its delay slot. | |
a7721dc0 | 7196 | |
a02aa5b0 | 7197 | CALL_DEST is the routine we are calling. */ |
a7721dc0 | 7198 | |
a02aa5b0 | 7199 | const char * |
b7849684 | 7200 | output_millicode_call (rtx insn, rtx call_dest) |
a02aa5b0 JDA |
7201 | { |
7202 | int attr_length = get_attr_length (insn); | |
7203 | int seq_length = dbr_sequence_length (); | |
7204 | int distance; | |
7205 | rtx seq_insn; | |
7206 | rtx xoperands[3]; | |
a7721dc0 | 7207 | |
a02aa5b0 JDA |
7208 | xoperands[0] = call_dest; |
7209 | xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31); | |
7210 | ||
7211 | /* Handle the common case where we are sure that the branch will | |
7212 | reach the beginning of the $CODE$ subspace. The within reach | |
7213 | form of the $$sh_func_adrs call has a length of 28. Because | |
272d0bee | 7214 | it has an attribute type of multi, it never has a nonzero |
a02aa5b0 JDA |
7215 | sequence length. The length of the $$sh_func_adrs is the same |
7216 | as certain out of reach PIC calls to other routines. */ | |
7217 | if (!TARGET_LONG_CALLS | |
7218 | && ((seq_length == 0 | |
7219 | && (attr_length == 12 | |
7220 | || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI))) | |
7221 | || (seq_length != 0 && attr_length == 8))) | |
7222 | { | |
7223 | output_asm_insn ("{bl|b,l} %0,%2", xoperands); | |
7224 | } | |
7225 | else | |
7226 | { | |
7227 | if (TARGET_64BIT) | |
7228 | { | |
7229 | /* It might seem that one insn could be saved by accessing | |
7230 | the millicode function using the linkage table. However, | |
7231 | this doesn't work in shared libraries and other dynamically | |
7232 | loaded objects. Using a pc-relative sequence also avoids | |
7233 | problems related to the implicit use of the gp register. */ | |
7234 | output_asm_insn ("b,l .+8,%%r1", xoperands); | |
581d9404 JDA |
7235 | |
7236 | if (TARGET_GAS) | |
7237 | { | |
7238 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); | |
7239 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
7240 | } | |
7241 | else | |
7242 | { | |
7243 | xoperands[1] = gen_label_rtx (); | |
7244 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
ecc418c4 | 7245 | targetm.asm_out.internal_label (asm_out_file, "L", |
581d9404 JDA |
7246 | CODE_LABEL_NUMBER (xoperands[1])); |
7247 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
7248 | } | |
7249 | ||
a02aa5b0 | 7250 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); |
6a73009d | 7251 | } |
6a73009d JL |
7252 | else if (TARGET_PORTABLE_RUNTIME) |
7253 | { | |
a02aa5b0 JDA |
7254 | /* Pure portable runtime doesn't allow be/ble; we also don't |
7255 | have PIC support in the assembler/linker, so this sequence | |
7256 | is needed. */ | |
6a73009d | 7257 | |
a02aa5b0 JDA |
7258 | /* Get the address of our target into %r1. */ |
7259 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
7260 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
6a73009d | 7261 | |
a02aa5b0 JDA |
7262 | /* Get our return address into %r31. */ |
7263 | output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands); | |
7264 | output_asm_insn ("addi 8,%%r31,%%r31", xoperands); | |
6a73009d | 7265 | |
a02aa5b0 JDA |
7266 | /* Jump to our target address in %r1. */ |
7267 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6a73009d | 7268 | } |
a02aa5b0 | 7269 | else if (!flag_pic) |
6a73009d | 7270 | { |
a02aa5b0 | 7271 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
6248c4dd | 7272 | if (TARGET_PA_20) |
a02aa5b0 | 7273 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands); |
6248c4dd | 7274 | else |
a02aa5b0 | 7275 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); |
6a73009d | 7276 | } |
a02aa5b0 | 7277 | else |
6a73009d | 7278 | { |
581d9404 JDA |
7279 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
7280 | output_asm_insn ("addi 16,%%r1,%%r31", xoperands); | |
7281 | ||
a02aa5b0 JDA |
7282 | if (TARGET_SOM || !TARGET_GAS) |
7283 | { | |
7284 | /* The HP assembler can generate relocations for the | |
7285 | difference of two symbols. GAS can do this for a | |
7286 | millicode symbol but not an arbitrary external | |
7287 | symbol when generating SOM output. */ | |
7288 | xoperands[1] = gen_label_rtx (); | |
ecc418c4 | 7289 | targetm.asm_out.internal_label (asm_out_file, "L", |
a02aa5b0 JDA |
7290 | CODE_LABEL_NUMBER (xoperands[1])); |
7291 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
7292 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
7293 | } | |
7294 | else | |
7295 | { | |
a02aa5b0 JDA |
7296 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands); |
7297 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1", | |
7298 | xoperands); | |
7299 | } | |
6a73009d | 7300 | |
a02aa5b0 JDA |
7301 | /* Jump to our target address in %r1. */ |
7302 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6a73009d | 7303 | } |
6a73009d JL |
7304 | } |
7305 | ||
a02aa5b0 JDA |
7306 | if (seq_length == 0) |
7307 | output_asm_insn ("nop", xoperands); | |
6a73009d | 7308 | |
a02aa5b0 JDA |
7309 | /* We are done if there isn't a jump in the delay slot. */ |
7310 | if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7311 | return ""; | |
6a73009d | 7312 | |
a02aa5b0 JDA |
7313 | /* This call has an unconditional jump in its delay slot. */ |
7314 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
6a73009d | 7315 | |
a02aa5b0 JDA |
7316 | /* See if the return address can be adjusted. Use the containing |
7317 | sequence insn's address. */ | |
611ad29e | 7318 | if (INSN_ADDRESSES_SET_P ()) |
6a73009d | 7319 | { |
611ad29e JDA |
7320 | seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); |
7321 | distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7322 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7323 | ||
7324 | if (VAL_14_BITS_P (distance)) | |
7325 | { | |
7326 | xoperands[1] = gen_label_rtx (); | |
7327 | output_asm_insn ("ldo %0-%1(%2),%2", xoperands); | |
ecc418c4 JDA |
7328 | targetm.asm_out.internal_label (asm_out_file, "L", |
7329 | CODE_LABEL_NUMBER (xoperands[1])); | |
611ad29e JDA |
7330 | } |
7331 | else | |
7332 | /* ??? This branch may not reach its target. */ | |
7333 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
6a73009d | 7334 | } |
a02aa5b0 JDA |
7335 | else |
7336 | /* ??? This branch may not reach its target. */ | |
7337 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
6a73009d JL |
7338 | |
7339 | /* Delete the jump. */ | |
a38e7aa5 | 7340 | SET_INSN_DELETED (NEXT_INSN (insn)); |
a02aa5b0 | 7341 | |
6a73009d JL |
7342 | return ""; |
7343 | } | |
7344 | ||
611ad29e JDA |
7345 | /* Return the attribute length of the call instruction INSN. The SIBCALL |
7346 | flag indicates whether INSN is a regular call or a sibling call. The | |
32562302 JDA |
7347 | length returned must be longer than the code actually generated by |
7348 | output_call. Since branch shortening is done before delay branch | |
7349 | sequencing, there is no way to determine whether or not the delay | |
7350 | slot will be filled during branch shortening. Even when the delay | |
7351 | slot is filled, we may have to add a nop if the delay slot contains | |
7352 | a branch that can't reach its target. Thus, we always have to include | |
7353 | the delay slot in the length estimate. This used to be done in | |
7354 | pa_adjust_insn_length but we do it here now as some sequences always | |
7355 | fill the delay slot and we can save four bytes in the estimate for | |
7356 | these sequences. */ | |
a02aa5b0 JDA |
7357 | |
7358 | int | |
b7849684 | 7359 | attr_length_call (rtx insn, int sibcall) |
a02aa5b0 | 7360 | { |
32562302 | 7361 | int local_call; |
e40375e0 | 7362 | rtx call, call_dest; |
32562302 JDA |
7363 | tree call_decl; |
7364 | int length = 0; | |
7365 | rtx pat = PATTERN (insn); | |
611ad29e | 7366 | unsigned long distance = -1; |
a02aa5b0 | 7367 | |
e40375e0 JDA |
7368 | gcc_assert (GET_CODE (insn) == CALL_INSN); |
7369 | ||
611ad29e JDA |
7370 | if (INSN_ADDRESSES_SET_P ()) |
7371 | { | |
32562302 JDA |
7372 | unsigned long total; |
7373 | ||
7374 | total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; | |
5fad1c24 JDA |
7375 | distance = (total + insn_current_reference_address (insn)); |
7376 | if (distance < total) | |
611ad29e JDA |
7377 | distance = -1; |
7378 | } | |
a02aa5b0 | 7379 | |
e40375e0 | 7380 | gcc_assert (GET_CODE (pat) == PARALLEL); |
a02aa5b0 | 7381 | |
e40375e0 JDA |
7382 | /* Get the call rtx. */ |
7383 | call = XVECEXP (pat, 0, 0); | |
7384 | if (GET_CODE (call) == SET) | |
7385 | call = SET_SRC (call); | |
7386 | ||
7387 | gcc_assert (GET_CODE (call) == CALL); | |
7388 | ||
7389 | /* Determine if this is a local call. */ | |
7390 | call_dest = XEXP (XEXP (call, 0), 0); | |
32562302 | 7391 | call_decl = SYMBOL_REF_DECL (call_dest); |
ecc418c4 | 7392 | local_call = call_decl && targetm.binds_local_p (call_decl); |
a02aa5b0 | 7393 | |
32562302 JDA |
7394 | /* pc-relative branch. */ |
7395 | if (!TARGET_LONG_CALLS | |
7396 | && ((TARGET_PA_20 && !sibcall && distance < 7600000) | |
7397 | || distance < 240000)) | |
7398 | length += 8; | |
a02aa5b0 | 7399 | |
32562302 JDA |
7400 | /* 64-bit plabel sequence. */ |
7401 | else if (TARGET_64BIT && !local_call) | |
7402 | length += sibcall ? 28 : 24; | |
a02aa5b0 | 7403 | |
32562302 JDA |
7404 | /* non-pic long absolute branch sequence. */ |
7405 | else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) | |
7406 | length += 12; | |
a02aa5b0 | 7407 | |
32562302 | 7408 | /* long pc-relative branch sequence. */ |
9dbd54be | 7409 | else if (TARGET_LONG_PIC_SDIFF_CALL |
751d9855 JDA |
7410 | || (TARGET_GAS && !TARGET_SOM |
7411 | && (TARGET_LONG_PIC_PCREL_CALL || local_call))) | |
32562302 JDA |
7412 | { |
7413 | length += 20; | |
a02aa5b0 | 7414 | |
9dbd54be | 7415 | if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS && flag_pic) |
32562302 JDA |
7416 | length += 8; |
7417 | } | |
62910663 | 7418 | |
32562302 JDA |
7419 | /* 32-bit plabel sequence. */ |
7420 | else | |
7421 | { | |
7422 | length += 32; | |
a02aa5b0 | 7423 | |
32562302 JDA |
7424 | if (TARGET_SOM) |
7425 | length += length_fp_args (insn); | |
7426 | ||
7427 | if (flag_pic) | |
7428 | length += 4; | |
90330d31 | 7429 | |
32562302 JDA |
7430 | if (!TARGET_PA_20) |
7431 | { | |
a02aa5b0 JDA |
7432 | if (!sibcall) |
7433 | length += 8; | |
7434 | ||
9dbd54be | 7435 | if (!TARGET_NO_SPACE_REGS && flag_pic) |
32562302 | 7436 | length += 8; |
a02aa5b0 JDA |
7437 | } |
7438 | } | |
32562302 JDA |
7439 | |
7440 | return length; | |
a02aa5b0 JDA |
7441 | } |
7442 | ||
7443 | /* INSN is a function call. It may have an unconditional jump | |
6a73009d JL |
7444 | in its delay slot. |
7445 | ||
7446 | CALL_DEST is the routine we are calling. */ | |
7447 | ||
519104fe | 7448 | const char * |
b7849684 | 7449 | output_call (rtx insn, rtx call_dest, int sibcall) |
6a73009d | 7450 | { |
a02aa5b0 JDA |
7451 | int delay_insn_deleted = 0; |
7452 | int delay_slot_filled = 0; | |
3d9268b6 | 7453 | int seq_length = dbr_sequence_length (); |
5fad1c24 | 7454 | tree call_decl = SYMBOL_REF_DECL (call_dest); |
ecc418c4 | 7455 | int local_call = call_decl && targetm.binds_local_p (call_decl); |
a02aa5b0 JDA |
7456 | rtx xoperands[2]; |
7457 | ||
7458 | xoperands[0] = call_dest; | |
6a73009d | 7459 | |
a02aa5b0 | 7460 | /* Handle the common case where we're sure that the branch will reach |
5fad1c24 JDA |
7461 | the beginning of the "$CODE$" subspace. This is the beginning of |
7462 | the current function if we are in a named section. */ | |
611ad29e | 7463 | if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8) |
2c4ff308 | 7464 | { |
520babc7 | 7465 | xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2); |
a02aa5b0 | 7466 | output_asm_insn ("{bl|b,l} %0,%1", xoperands); |
279c9bde | 7467 | } |
a02aa5b0 | 7468 | else |
279c9bde | 7469 | { |
5fad1c24 | 7470 | if (TARGET_64BIT && !local_call) |
f726ea7d | 7471 | { |
a02aa5b0 JDA |
7472 | /* ??? As far as I can tell, the HP linker doesn't support the |
7473 | long pc-relative sequence described in the 64-bit runtime | |
7474 | architecture. So, we use a slightly longer indirect call. */ | |
7aaf280e | 7475 | xoperands[0] = get_deferred_plabel (call_dest); |
a02aa5b0 JDA |
7476 | xoperands[1] = gen_label_rtx (); |
7477 | ||
7478 | /* If this isn't a sibcall, we put the load of %r27 into the | |
7479 | delay slot. We can't do this in a sibcall as we don't | |
7480 | have a second call-clobbered scratch register available. */ | |
7481 | if (seq_length != 0 | |
7482 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7483 | && !sibcall) | |
7484 | { | |
7485 | final_scan_insn (NEXT_INSN (insn), asm_out_file, | |
c9d691e9 | 7486 | optimize, 0, NULL); |
a02aa5b0 JDA |
7487 | |
7488 | /* Now delete the delay insn. */ | |
a38e7aa5 | 7489 | SET_INSN_DELETED (NEXT_INSN (insn)); |
a02aa5b0 JDA |
7490 | delay_insn_deleted = 1; |
7491 | } | |
279c9bde | 7492 | |
a02aa5b0 JDA |
7493 | output_asm_insn ("addil LT'%0,%%r27", xoperands); |
7494 | output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands); | |
7495 | output_asm_insn ("ldd 0(%%r1),%%r1", xoperands); | |
279c9bde | 7496 | |
a02aa5b0 | 7497 | if (sibcall) |
279c9bde | 7498 | { |
a02aa5b0 JDA |
7499 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); |
7500 | output_asm_insn ("ldd 16(%%r1),%%r1", xoperands); | |
7501 | output_asm_insn ("bve (%%r1)", xoperands); | |
7502 | } | |
7503 | else | |
7504 | { | |
7505 | output_asm_insn ("ldd 16(%%r1),%%r2", xoperands); | |
7506 | output_asm_insn ("bve,l (%%r2),%%r2", xoperands); | |
7507 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); | |
7508 | delay_slot_filled = 1; | |
279c9bde JL |
7509 | } |
7510 | } | |
a02aa5b0 | 7511 | else |
93ae92c1 | 7512 | { |
a02aa5b0 JDA |
7513 | int indirect_call = 0; |
7514 | ||
7515 | /* Emit a long call. There are several different sequences | |
7516 | of increasing length and complexity. In most cases, | |
7517 | they don't allow an instruction in the delay slot. */ | |
5fad1c24 | 7518 | if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
9dbd54be | 7519 | && !TARGET_LONG_PIC_SDIFF_CALL |
751d9855 JDA |
7520 | && !(TARGET_GAS && !TARGET_SOM |
7521 | && (TARGET_LONG_PIC_PCREL_CALL || local_call)) | |
5fad1c24 | 7522 | && !TARGET_64BIT) |
a02aa5b0 JDA |
7523 | indirect_call = 1; |
7524 | ||
7525 | if (seq_length != 0 | |
7526 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7527 | && !sibcall | |
44b86471 JDA |
7528 | && (!TARGET_PA_20 |
7529 | || indirect_call | |
7530 | || ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic))) | |
359255a9 | 7531 | { |
a02aa5b0 JDA |
7532 | /* A non-jump insn in the delay slot. By definition we can |
7533 | emit this insn before the call (and in fact before argument | |
7534 | relocating. */ | |
c9d691e9 | 7535 | final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, |
5cfc5f84 | 7536 | NULL); |
a02aa5b0 JDA |
7537 | |
7538 | /* Now delete the delay insn. */ | |
a38e7aa5 | 7539 | SET_INSN_DELETED (NEXT_INSN (insn)); |
a02aa5b0 | 7540 | delay_insn_deleted = 1; |
359255a9 | 7541 | } |
93ae92c1 | 7542 | |
5fad1c24 | 7543 | if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
359255a9 | 7544 | { |
a02aa5b0 JDA |
7545 | /* This is the best sequence for making long calls in |
7546 | non-pic code. Unfortunately, GNU ld doesn't provide | |
7547 | the stub needed for external calls, and GAS's support | |
5fad1c24 JDA |
7548 | for this with the SOM linker is buggy. It is safe |
7549 | to use this for local calls. */ | |
a02aa5b0 JDA |
7550 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
7551 | if (sibcall) | |
7552 | output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands); | |
7553 | else | |
7554 | { | |
7555 | if (TARGET_PA_20) | |
7556 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", | |
7557 | xoperands); | |
7558 | else | |
7559 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); | |
6a73009d | 7560 | |
a02aa5b0 JDA |
7561 | output_asm_insn ("copy %%r31,%%r2", xoperands); |
7562 | delay_slot_filled = 1; | |
7563 | } | |
7564 | } | |
7565 | else | |
7566 | { | |
9dbd54be | 7567 | if (TARGET_LONG_PIC_SDIFF_CALL) |
3d9268b6 | 7568 | { |
a02aa5b0 | 7569 | /* The HP assembler and linker can handle relocations |
9dbd54be JDA |
7570 | for the difference of two symbols. The HP assembler |
7571 | recognizes the sequence as a pc-relative call and | |
7572 | the linker provides stubs when needed. */ | |
a02aa5b0 JDA |
7573 | xoperands[1] = gen_label_rtx (); |
7574 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7575 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
ecc418c4 | 7576 | targetm.asm_out.internal_label (asm_out_file, "L", |
3d9268b6 | 7577 | CODE_LABEL_NUMBER (xoperands[1])); |
a02aa5b0 JDA |
7578 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); |
7579 | } | |
751d9855 JDA |
7580 | else if (TARGET_GAS && !TARGET_SOM |
7581 | && (TARGET_LONG_PIC_PCREL_CALL || local_call)) | |
3d9268b6 | 7582 | { |
a02aa5b0 JDA |
7583 | /* GAS currently can't generate the relocations that |
7584 | are needed for the SOM linker under HP-UX using this | |
7585 | sequence. The GNU linker doesn't generate the stubs | |
7586 | that are needed for external calls on TARGET_ELF32 | |
7587 | with this sequence. For now, we have to use a | |
7588 | longer plabel sequence when using GAS. */ | |
7589 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7590 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", | |
3d9268b6 | 7591 | xoperands); |
a02aa5b0 | 7592 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", |
3d9268b6 JDA |
7593 | xoperands); |
7594 | } | |
520babc7 JL |
7595 | else |
7596 | { | |
a02aa5b0 JDA |
7597 | /* Emit a long plabel-based call sequence. This is |
7598 | essentially an inline implementation of $$dyncall. | |
7599 | We don't actually try to call $$dyncall as this is | |
7600 | as difficult as calling the function itself. */ | |
7aaf280e | 7601 | xoperands[0] = get_deferred_plabel (call_dest); |
a02aa5b0 JDA |
7602 | xoperands[1] = gen_label_rtx (); |
7603 | ||
7604 | /* Since the call is indirect, FP arguments in registers | |
7605 | need to be copied to the general registers. Then, the | |
7606 | argument relocation stub will copy them back. */ | |
7607 | if (TARGET_SOM) | |
7608 | copy_fp_args (insn); | |
7609 | ||
7610 | if (flag_pic) | |
7611 | { | |
7612 | output_asm_insn ("addil LT'%0,%%r19", xoperands); | |
7613 | output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands); | |
7614 | output_asm_insn ("ldw 0(%%r1),%%r1", xoperands); | |
7615 | } | |
7616 | else | |
7617 | { | |
7618 | output_asm_insn ("addil LR'%0-$global$,%%r27", | |
7619 | xoperands); | |
7620 | output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1", | |
7621 | xoperands); | |
7622 | } | |
279c9bde | 7623 | |
a02aa5b0 JDA |
7624 | output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands); |
7625 | output_asm_insn ("depi 0,31,2,%%r1", xoperands); | |
7626 | output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands); | |
7627 | output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands); | |
6a73009d | 7628 | |
a02aa5b0 JDA |
7629 | if (!sibcall && !TARGET_PA_20) |
7630 | { | |
7631 | output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands); | |
90330d31 JDA |
7632 | if (TARGET_NO_SPACE_REGS) |
7633 | output_asm_insn ("addi 8,%%r2,%%r2", xoperands); | |
7634 | else | |
7635 | output_asm_insn ("addi 16,%%r2,%%r2", xoperands); | |
a02aa5b0 JDA |
7636 | } |
7637 | } | |
6a73009d | 7638 | |
a02aa5b0 | 7639 | if (TARGET_PA_20) |
520babc7 | 7640 | { |
a02aa5b0 JDA |
7641 | if (sibcall) |
7642 | output_asm_insn ("bve (%%r1)", xoperands); | |
7643 | else | |
7644 | { | |
7645 | if (indirect_call) | |
7646 | { | |
7647 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7648 | output_asm_insn ("stw %%r2,-24(%%sp)", xoperands); | |
7649 | delay_slot_filled = 1; | |
7650 | } | |
7651 | else | |
7652 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7653 | } | |
520babc7 JL |
7654 | } |
7655 | else | |
7656 | { | |
9dbd54be | 7657 | if (!TARGET_NO_SPACE_REGS && flag_pic) |
90330d31 JDA |
7658 | output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0", |
7659 | xoperands); | |
279c9bde | 7660 | |
a02aa5b0 | 7661 | if (sibcall) |
90330d31 | 7662 | { |
9dbd54be | 7663 | if (TARGET_NO_SPACE_REGS || !flag_pic) |
90330d31 JDA |
7664 | output_asm_insn ("be 0(%%sr4,%%r1)", xoperands); |
7665 | else | |
7666 | output_asm_insn ("be 0(%%sr0,%%r1)", xoperands); | |
7667 | } | |
a02aa5b0 JDA |
7668 | else |
7669 | { | |
9dbd54be | 7670 | if (TARGET_NO_SPACE_REGS || !flag_pic) |
90330d31 JDA |
7671 | output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands); |
7672 | else | |
7673 | output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands); | |
279c9bde | 7674 | |
a02aa5b0 JDA |
7675 | if (indirect_call) |
7676 | output_asm_insn ("stw %%r31,-24(%%sp)", xoperands); | |
7677 | else | |
7678 | output_asm_insn ("copy %%r31,%%r2", xoperands); | |
7679 | delay_slot_filled = 1; | |
7680 | } | |
7681 | } | |
7682 | } | |
279c9bde | 7683 | } |
2c4ff308 | 7684 | } |
23f6f34f | 7685 | |
62910663 | 7686 | if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted)) |
a02aa5b0 | 7687 | output_asm_insn ("nop", xoperands); |
2c4ff308 | 7688 | |
a02aa5b0 JDA |
7689 | /* We are done if there isn't a jump in the delay slot. */ |
7690 | if (seq_length == 0 | |
7691 | || delay_insn_deleted | |
7692 | || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7693 | return ""; | |
2c4ff308 | 7694 | |
a02aa5b0 | 7695 | /* A sibcall should never have a branch in the delay slot. */ |
144d51f9 | 7696 | gcc_assert (!sibcall); |
2c4ff308 | 7697 | |
a02aa5b0 JDA |
7698 | /* This call has an unconditional jump in its delay slot. */ |
7699 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
2c4ff308 | 7700 | |
611ad29e | 7701 | if (!delay_slot_filled && INSN_ADDRESSES_SET_P ()) |
2c4ff308 | 7702 | { |
a02aa5b0 JDA |
7703 | /* See if the return address can be adjusted. Use the containing |
7704 | sequence insn's address. */ | |
7705 | rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); | |
7706 | int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7707 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7708 | ||
7709 | if (VAL_14_BITS_P (distance)) | |
7710 | { | |
7711 | xoperands[1] = gen_label_rtx (); | |
7712 | output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands); | |
ecc418c4 JDA |
7713 | targetm.asm_out.internal_label (asm_out_file, "L", |
7714 | CODE_LABEL_NUMBER (xoperands[1])); | |
a02aa5b0 JDA |
7715 | } |
7716 | else | |
a02aa5b0 | 7717 | output_asm_insn ("nop\n\tb,n %0", xoperands); |
2c4ff308 | 7718 | } |
a02aa5b0 | 7719 | else |
a02aa5b0 | 7720 | output_asm_insn ("b,n %0", xoperands); |
2c4ff308 JL |
7721 | |
7722 | /* Delete the jump. */ | |
a38e7aa5 | 7723 | SET_INSN_DELETED (NEXT_INSN (insn)); |
a02aa5b0 | 7724 | |
2c4ff308 JL |
7725 | return ""; |
7726 | } | |
7727 | ||
611ad29e JDA |
7728 | /* Return the attribute length of the indirect call instruction INSN. |
7729 | The length must match the code generated by output_indirect call. | |
7730 | The returned length includes the delay slot. Currently, the delay | |
7731 | slot of an indirect call sequence is not exposed and it is used by | |
7732 | the sequence itself. */ | |
7733 | ||
7734 | int | |
b7849684 | 7735 | attr_length_indirect_call (rtx insn) |
611ad29e JDA |
7736 | { |
7737 | unsigned long distance = -1; | |
62910663 | 7738 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
611ad29e JDA |
7739 | |
7740 | if (INSN_ADDRESSES_SET_P ()) | |
7741 | { | |
5fad1c24 JDA |
7742 | distance = (total + insn_current_reference_address (insn)); |
7743 | if (distance < total) | |
611ad29e JDA |
7744 | distance = -1; |
7745 | } | |
7746 | ||
7747 | if (TARGET_64BIT) | |
7748 | return 12; | |
7749 | ||
7750 | if (TARGET_FAST_INDIRECT_CALLS | |
7751 | || (!TARGET_PORTABLE_RUNTIME | |
40fc2e0b JDA |
7752 | && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000) |
7753 | || distance < 240000))) | |
611ad29e JDA |
7754 | return 8; |
7755 | ||
7756 | if (flag_pic) | |
7757 | return 24; | |
7758 | ||
7759 | if (TARGET_PORTABLE_RUNTIME) | |
7760 | return 20; | |
7761 | ||
7762 | /* Out of reach, can use ble. */ | |
7763 | return 12; | |
7764 | } | |
7765 | ||
7766 | const char * | |
b7849684 | 7767 | output_indirect_call (rtx insn, rtx call_dest) |
611ad29e JDA |
7768 | { |
7769 | rtx xoperands[1]; | |
7770 | ||
7771 | if (TARGET_64BIT) | |
7772 | { | |
7773 | xoperands[0] = call_dest; | |
7774 | output_asm_insn ("ldd 16(%0),%%r2", xoperands); | |
7775 | output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands); | |
7776 | return ""; | |
7777 | } | |
7778 | ||
7779 | /* First the special case for kernels, level 0 systems, etc. */ | |
7780 | if (TARGET_FAST_INDIRECT_CALLS) | |
7781 | return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2"; | |
7782 | ||
7783 | /* Now the normal case -- we can reach $$dyncall directly or | |
7784 | we're sure that we can get there via a long-branch stub. | |
7785 | ||
7786 | No need to check target flags as the length uniquely identifies | |
7787 | the remaining cases. */ | |
7788 | if (attr_length_indirect_call (insn) == 8) | |
2c774817 | 7789 | { |
40fc2e0b JDA |
7790 | /* The HP linker sometimes substitutes a BLE for BL/B,L calls to |
7791 | $$dyncall. Since BLE uses %r31 as the link register, the 22-bit | |
7792 | variant of the B,L instruction can't be used on the SOM target. */ | |
7793 | if (TARGET_PA_20 && !TARGET_SOM) | |
2c774817 JDA |
7794 | return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31"; |
7795 | else | |
7796 | return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2"; | |
7797 | } | |
611ad29e JDA |
7798 | |
7799 | /* Long millicode call, but we are not generating PIC or portable runtime | |
7800 | code. */ | |
7801 | if (attr_length_indirect_call (insn) == 12) | |
7802 | return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2"; | |
7803 | ||
7804 | /* Long millicode call for portable runtime. */ | |
7805 | if (attr_length_indirect_call (insn) == 20) | |
7806 | return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop"; | |
7807 | ||
7808 | /* We need a long PIC call to $$dyncall. */ | |
7809 | xoperands[0] = NULL_RTX; | |
7810 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7811 | if (TARGET_SOM || !TARGET_GAS) | |
7812 | { | |
7813 | xoperands[0] = gen_label_rtx (); | |
7814 | output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands); | |
ecc418c4 JDA |
7815 | targetm.asm_out.internal_label (asm_out_file, "L", |
7816 | CODE_LABEL_NUMBER (xoperands[0])); | |
611ad29e JDA |
7817 | output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands); |
7818 | } | |
7819 | else | |
7820 | { | |
7821 | output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands); | |
7822 | output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1", | |
7823 | xoperands); | |
7824 | } | |
7825 | output_asm_insn ("blr %%r0,%%r2", xoperands); | |
7826 | output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands); | |
7827 | return ""; | |
7828 | } | |
7829 | ||
7830 | /* Return the total length of the save and restore instructions needed for | |
7831 | the data linkage table pointer (i.e., the PIC register) across the call | |
7832 | instruction INSN. No-return calls do not require a save and restore. | |
7833 | In addition, we may be able to avoid the save and restore for calls | |
7834 | within the same translation unit. */ | |
7835 | ||
7836 | int | |
b7849684 | 7837 | attr_length_save_restore_dltp (rtx insn) |
611ad29e JDA |
7838 | { |
7839 | if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
7840 | return 0; | |
7841 | ||
7842 | return 8; | |
7843 | } | |
7844 | ||
d2a94ec0 | 7845 | /* In HPUX 8.0's shared library scheme, special relocations are needed |
23f6f34f | 7846 | for function labels if they might be passed to a function |
d2a94ec0 | 7847 | in a shared library (because shared libraries don't live in code |
520a57c8 | 7848 | space), and special magic is needed to construct their address. */ |
d2a94ec0 TM |
7849 | |
7850 | void | |
b7849684 | 7851 | hppa_encode_label (rtx sym) |
d2a94ec0 | 7852 | { |
519104fe | 7853 | const char *str = XSTR (sym, 0); |
10d17cb7 AM |
7854 | int len = strlen (str) + 1; |
7855 | char *newstr, *p; | |
d2a94ec0 | 7856 | |
5ead67f6 | 7857 | p = newstr = XALLOCAVEC (char, len + 1); |
10d17cb7 AM |
7858 | *p++ = '@'; |
7859 | strcpy (p, str); | |
67d6f2fc | 7860 | |
831c1763 | 7861 | XSTR (sym, 0) = ggc_alloc_string (newstr, len); |
d2a94ec0 | 7862 | } |
23f6f34f | 7863 | |
fb49053f | 7864 | static void |
b7849684 | 7865 | pa_encode_section_info (tree decl, rtx rtl, int first) |
fb49053f | 7866 | { |
9a60b229 JJ |
7867 | int old_referenced = 0; |
7868 | ||
7869 | if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF) | |
7870 | old_referenced | |
7871 | = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED; | |
7872 | ||
51076f96 RC |
7873 | default_encode_section_info (decl, rtl, first); |
7874 | ||
fb49053f RH |
7875 | if (first && TEXT_SPACE_P (decl)) |
7876 | { | |
fb49053f RH |
7877 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
7878 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
c6a2438a | 7879 | hppa_encode_label (XEXP (rtl, 0)); |
fb49053f | 7880 | } |
9a60b229 JJ |
7881 | else if (old_referenced) |
7882 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced; | |
fb49053f RH |
7883 | } |
7884 | ||
772c5265 RH |
7885 | /* This is sort of inverse to pa_encode_section_info. */ |
7886 | ||
7887 | static const char * | |
b7849684 | 7888 | pa_strip_name_encoding (const char *str) |
772c5265 | 7889 | { |
7830ba7b JDA |
7890 | str += (*str == '@'); |
7891 | str += (*str == '*'); | |
7892 | return str; | |
772c5265 RH |
7893 | } |
7894 | ||
d2a94ec0 | 7895 | int |
b7849684 | 7896 | function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d2a94ec0 | 7897 | { |
e5d4ff05 | 7898 | return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0)); |
d2a94ec0 | 7899 | } |
9bb77117 | 7900 | |
326bc2de JL |
7901 | /* Returns 1 if OP is a function label involved in a simple addition |
7902 | with a constant. Used to keep certain patterns from matching | |
7903 | during instruction combination. */ | |
7904 | int | |
b7849684 | 7905 | is_function_label_plus_const (rtx op) |
326bc2de JL |
7906 | { |
7907 | /* Strip off any CONST. */ | |
7908 | if (GET_CODE (op) == CONST) | |
7909 | op = XEXP (op, 0); | |
7910 | ||
7911 | return (GET_CODE (op) == PLUS | |
7912 | && function_label_operand (XEXP (op, 0), Pmode) | |
7913 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
7914 | } | |
7915 | ||
54374491 JL |
7916 | /* Output assembly code for a thunk to FUNCTION. */ |
7917 | ||
c590b625 | 7918 | static void |
b7849684 JE |
7919 | pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, |
7920 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
7921 | tree function) | |
54374491 | 7922 | { |
cdcb88d7 | 7923 | static unsigned int current_thunk_number; |
5fad1c24 | 7924 | int val_14 = VAL_14_BITS_P (delta); |
67b846fa | 7925 | unsigned int old_last_address = last_address, nbytes = 0; |
54374491 | 7926 | char label[16]; |
cdcb88d7 | 7927 | rtx xoperands[4]; |
5fad1c24 | 7928 | |
cdcb88d7 JDA |
7929 | xoperands[0] = XEXP (DECL_RTL (function), 0); |
7930 | xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0); | |
7931 | xoperands[2] = GEN_INT (delta); | |
5fad1c24 | 7932 | |
cdcb88d7 JDA |
7933 | ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0)); |
7934 | fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); | |
5fad1c24 JDA |
7935 | |
7936 | /* Output the thunk. We know that the function is in the same | |
7937 | translation unit (i.e., the same space) as the thunk, and that | |
7938 | thunks are output after their method. Thus, we don't need an | |
7939 | external branch to reach the function. With SOM and GAS, | |
7940 | functions and thunks are effectively in different sections. | |
7941 | Thus, we can always use a IA-relative branch and the linker | |
7942 | will add a long branch stub if necessary. | |
7943 | ||
7944 | However, we have to be careful when generating PIC code on the | |
7945 | SOM port to ensure that the sequence does not transfer to an | |
7946 | import stub for the target function as this could clobber the | |
7947 | return value saved at SP-24. This would also apply to the | |
7948 | 32-bit linux port if the multi-space model is implemented. */ | |
7949 | if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
7950 | && !(flag_pic && TREE_PUBLIC (function)) | |
7951 | && (TARGET_GAS || last_address < 262132)) | |
7952 | || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
7953 | && ((targetm.have_named_sections | |
7954 | && DECL_SECTION_NAME (thunk_fndecl) != NULL | |
7955 | /* The GNU 64-bit linker has rather poor stub management. | |
7956 | So, we use a long branch from thunks that aren't in | |
7957 | the same section as the target function. */ | |
7958 | && ((!TARGET_64BIT | |
7959 | && (DECL_SECTION_NAME (thunk_fndecl) | |
7960 | != DECL_SECTION_NAME (function))) | |
7961 | || ((DECL_SECTION_NAME (thunk_fndecl) | |
7962 | == DECL_SECTION_NAME (function)) | |
7963 | && last_address < 262132))) | |
2842bb86 JDA |
7964 | || (targetm.have_named_sections |
7965 | && DECL_SECTION_NAME (thunk_fndecl) == NULL | |
7966 | && DECL_SECTION_NAME (function) == NULL | |
7967 | && last_address < 262132) | |
5fad1c24 JDA |
7968 | || (!targetm.have_named_sections && last_address < 262132)))) |
7969 | { | |
cdcb88d7 JDA |
7970 | if (!val_14) |
7971 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
7972 | ||
7973 | output_asm_insn ("b %0", xoperands); | |
7974 | ||
5fad1c24 JDA |
7975 | if (val_14) |
7976 | { | |
cdcb88d7 | 7977 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
5fad1c24 JDA |
7978 | nbytes += 8; |
7979 | } | |
7980 | else | |
7981 | { | |
cdcb88d7 | 7982 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
5fad1c24 JDA |
7983 | nbytes += 12; |
7984 | } | |
7985 | } | |
7986 | else if (TARGET_64BIT) | |
7987 | { | |
7988 | /* We only have one call-clobbered scratch register, so we can't | |
7989 | make use of the delay slot if delta doesn't fit in 14 bits. */ | |
7990 | if (!val_14) | |
cdcb88d7 JDA |
7991 | { |
7992 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
7993 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); | |
7994 | } | |
5fad1c24 | 7995 | |
cdcb88d7 | 7996 | output_asm_insn ("b,l .+8,%%r1", xoperands); |
5fad1c24 JDA |
7997 | |
7998 | if (TARGET_GAS) | |
7999 | { | |
cdcb88d7 JDA |
8000 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
8001 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
5fad1c24 JDA |
8002 | } |
8003 | else | |
8004 | { | |
cdcb88d7 JDA |
8005 | xoperands[3] = GEN_INT (val_14 ? 8 : 16); |
8006 | output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands); | |
5fad1c24 JDA |
8007 | } |
8008 | ||
8009 | if (val_14) | |
8010 | { | |
cdcb88d7 JDA |
8011 | output_asm_insn ("bv %%r0(%%r1)", xoperands); |
8012 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); | |
5fad1c24 JDA |
8013 | nbytes += 20; |
8014 | } | |
8015 | else | |
8016 | { | |
cdcb88d7 | 8017 | output_asm_insn ("bv,n %%r0(%%r1)", xoperands); |
5fad1c24 JDA |
8018 | nbytes += 24; |
8019 | } | |
8020 | } | |
8021 | else if (TARGET_PORTABLE_RUNTIME) | |
8022 | { | |
cdcb88d7 JDA |
8023 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
8024 | output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands); | |
8025 | ||
8026 | if (!val_14) | |
8027 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8028 | ||
8029 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
5fad1c24 JDA |
8030 | |
8031 | if (val_14) | |
8032 | { | |
cdcb88d7 | 8033 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
5fad1c24 JDA |
8034 | nbytes += 16; |
8035 | } | |
8036 | else | |
8037 | { | |
cdcb88d7 | 8038 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
5fad1c24 JDA |
8039 | nbytes += 20; |
8040 | } | |
8041 | } | |
8042 | else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
8043 | { | |
8044 | /* The function is accessible from outside this module. The only | |
8045 | way to avoid an import stub between the thunk and function is to | |
8046 | call the function directly with an indirect sequence similar to | |
8047 | that used by $$dyncall. This is possible because $$dyncall acts | |
8048 | as the import stub in an indirect call. */ | |
5fad1c24 | 8049 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number); |
cdcb88d7 JDA |
8050 | xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label); |
8051 | output_asm_insn ("addil LT'%3,%%r19", xoperands); | |
8052 | output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands); | |
8053 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
8054 | output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands); | |
8055 | output_asm_insn ("depi 0,31,2,%%r22", xoperands); | |
8056 | output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands); | |
8057 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
8058 | ||
5fad1c24 JDA |
8059 | if (!val_14) |
8060 | { | |
cdcb88d7 | 8061 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
5fad1c24 JDA |
8062 | nbytes += 4; |
8063 | } | |
cdcb88d7 | 8064 | |
5fad1c24 JDA |
8065 | if (TARGET_PA_20) |
8066 | { | |
cdcb88d7 JDA |
8067 | output_asm_insn ("bve (%%r22)", xoperands); |
8068 | nbytes += 36; | |
8069 | } | |
8070 | else if (TARGET_NO_SPACE_REGS) | |
8071 | { | |
8072 | output_asm_insn ("be 0(%%sr4,%%r22)", xoperands); | |
5fad1c24 JDA |
8073 | nbytes += 36; |
8074 | } | |
8075 | else | |
54374491 | 8076 | { |
cdcb88d7 JDA |
8077 | output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands); |
8078 | output_asm_insn ("mtsp %%r21,%%sr0", xoperands); | |
8079 | output_asm_insn ("be 0(%%sr0,%%r22)", xoperands); | |
8080 | nbytes += 44; | |
5fad1c24 JDA |
8081 | } |
8082 | ||
8083 | if (val_14) | |
cdcb88d7 | 8084 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
5fad1c24 | 8085 | else |
cdcb88d7 | 8086 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
5fad1c24 JDA |
8087 | } |
8088 | else if (flag_pic) | |
8089 | { | |
cdcb88d7 | 8090 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
5fad1c24 JDA |
8091 | |
8092 | if (TARGET_SOM || !TARGET_GAS) | |
8093 | { | |
cdcb88d7 JDA |
8094 | output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands); |
8095 | output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands); | |
5fad1c24 JDA |
8096 | } |
8097 | else | |
8098 | { | |
cdcb88d7 JDA |
8099 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
8100 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands); | |
5fad1c24 JDA |
8101 | } |
8102 | ||
cdcb88d7 JDA |
8103 | if (!val_14) |
8104 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8105 | ||
8106 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
8107 | ||
5fad1c24 JDA |
8108 | if (val_14) |
8109 | { | |
cdcb88d7 | 8110 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
5fad1c24 | 8111 | nbytes += 20; |
54374491 JL |
8112 | } |
8113 | else | |
5fad1c24 | 8114 | { |
cdcb88d7 | 8115 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
5fad1c24 JDA |
8116 | nbytes += 24; |
8117 | } | |
54374491 JL |
8118 | } |
8119 | else | |
8120 | { | |
5fad1c24 | 8121 | if (!val_14) |
cdcb88d7 | 8122 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
5fad1c24 | 8123 | |
cdcb88d7 JDA |
8124 | output_asm_insn ("ldil L'%0,%%r22", xoperands); |
8125 | output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands); | |
5fad1c24 JDA |
8126 | |
8127 | if (val_14) | |
54374491 | 8128 | { |
cdcb88d7 | 8129 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
5fad1c24 | 8130 | nbytes += 12; |
54374491 JL |
8131 | } |
8132 | else | |
5fad1c24 | 8133 | { |
cdcb88d7 | 8134 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
5fad1c24 JDA |
8135 | nbytes += 16; |
8136 | } | |
54374491 | 8137 | } |
5fad1c24 | 8138 | |
54374491 | 8139 | fprintf (file, "\t.EXIT\n\t.PROCEND\n"); |
5fad1c24 | 8140 | |
1a83bfc3 JDA |
8141 | if (TARGET_SOM && TARGET_GAS) |
8142 | { | |
8143 | /* We done with this subspace except possibly for some additional | |
8144 | debug information. Forget that we are in this subspace to ensure | |
8145 | that the next function is output in its own subspace. */ | |
8146 | in_section = NULL; | |
8147 | cfun->machine->in_nsubspa = 2; | |
8148 | } | |
8149 | ||
5fad1c24 | 8150 | if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) |
54374491 | 8151 | { |
d6b5193b | 8152 | switch_to_section (data_section); |
cdcb88d7 | 8153 | output_asm_insn (".align 4", xoperands); |
5fad1c24 | 8154 | ASM_OUTPUT_LABEL (file, label); |
cdcb88d7 | 8155 | output_asm_insn (".word P'%0", xoperands); |
54374491 | 8156 | } |
5fad1c24 | 8157 | |
54374491 | 8158 | current_thunk_number++; |
5fad1c24 JDA |
8159 | nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) |
8160 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
8161 | last_address += nbytes; | |
67b846fa JDA |
8162 | if (old_last_address > last_address) |
8163 | last_address = UINT_MAX; | |
5fad1c24 | 8164 | update_total_code_bytes (nbytes); |
54374491 JL |
8165 | } |
8166 | ||
4977bab6 ZW |
8167 | /* Only direct calls to static functions are allowed to be sibling (tail) |
8168 | call optimized. | |
8169 | ||
8170 | This restriction is necessary because some linker generated stubs will | |
8171 | store return pointers into rp' in some cases which might clobber a | |
8172 | live value already in rp'. | |
8173 | ||
8174 | In a sibcall the current function and the target function share stack | |
8175 | space. Thus if the path to the current function and the path to the | |
8176 | target function save a value in rp', they save the value into the | |
8177 | same stack slot, which has undesirable consequences. | |
8178 | ||
8179 | Because of the deferred binding nature of shared libraries any function | |
8180 | with external scope could be in a different load module and thus require | |
8181 | rp' to be saved when calling that function. So sibcall optimizations | |
8182 | can only be safe for static function. | |
8183 | ||
8184 | Note that GCC never needs return value relocations, so we don't have to | |
8185 | worry about static calls with return value relocations (which require | |
8186 | saving rp'). | |
8187 | ||
8188 | It is safe to perform a sibcall optimization when the target function | |
8189 | will never return. */ | |
8190 | static bool | |
b7849684 | 8191 | pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
4977bab6 | 8192 | { |
73096ba9 JDA |
8193 | if (TARGET_PORTABLE_RUNTIME) |
8194 | return false; | |
8195 | ||
11f43127 JDA |
8196 | /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in |
8197 | single subspace mode and the call is not indirect. As far as I know, | |
8198 | there is no operating system support for the multiple subspace mode. | |
8199 | It might be possible to support indirect calls if we didn't use | |
8200 | $$dyncall (see the indirect sequence generated in output_call). */ | |
8201 | if (TARGET_ELF32) | |
8202 | return (decl != NULL_TREE); | |
8203 | ||
8204 | /* Sibcalls are not ok because the arg pointer register is not a fixed | |
c1207243 | 8205 | register. This prevents the sibcall optimization from occurring. In |
11f43127 JDA |
8206 | addition, there are problems with stub placement using GNU ld. This |
8207 | is because a normal sibcall branch uses a 17-bit relocation while | |
8208 | a regular call branch uses a 22-bit relocation. As a result, more | |
8209 | care needs to be taken in the placement of long-branch stubs. */ | |
8210 | if (TARGET_64BIT) | |
8211 | return false; | |
8212 | ||
73096ba9 JDA |
8213 | /* Sibcalls are only ok within a translation unit. */ |
8214 | return (decl && !TREE_PUBLIC (decl)); | |
4977bab6 ZW |
8215 | } |
8216 | ||
8ddf681a R |
8217 | /* ??? Addition is not commutative on the PA due to the weird implicit |
8218 | space register selection rules for memory addresses. Therefore, we | |
8219 | don't consider a + b == b + a, as this might be inside a MEM. */ | |
8220 | static bool | |
3101faab | 8221 | pa_commutative_p (const_rtx x, int outer_code) |
8ddf681a R |
8222 | { |
8223 | return (COMMUTATIVE_P (x) | |
bd7d5043 JDA |
8224 | && (TARGET_NO_SPACE_REGS |
8225 | || (outer_code != UNKNOWN && outer_code != MEM) | |
8ddf681a R |
8226 | || GET_CODE (x) != PLUS)); |
8227 | } | |
8228 | ||
88e5c029 JL |
8229 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
8230 | use in fmpyadd instructions. */ | |
2fe24884 | 8231 | int |
b7849684 | 8232 | fmpyaddoperands (rtx *operands) |
2fe24884 | 8233 | { |
f133af4c | 8234 | enum machine_mode mode = GET_MODE (operands[0]); |
2fe24884 | 8235 | |
d85ab966 JL |
8236 | /* Must be a floating point mode. */ |
8237 | if (mode != SFmode && mode != DFmode) | |
8238 | return 0; | |
8239 | ||
2fe24884 | 8240 | /* All modes must be the same. */ |
f133af4c TG |
8241 | if (! (mode == GET_MODE (operands[1]) |
8242 | && mode == GET_MODE (operands[2]) | |
8243 | && mode == GET_MODE (operands[3]) | |
8244 | && mode == GET_MODE (operands[4]) | |
8245 | && mode == GET_MODE (operands[5]))) | |
2fe24884 JL |
8246 | return 0; |
8247 | ||
d85ab966 JL |
8248 | /* All operands must be registers. */ |
8249 | if (! (GET_CODE (operands[1]) == REG | |
8250 | && GET_CODE (operands[2]) == REG | |
8251 | && GET_CODE (operands[3]) == REG | |
8252 | && GET_CODE (operands[4]) == REG | |
8253 | && GET_CODE (operands[5]) == REG)) | |
2fe24884 JL |
8254 | return 0; |
8255 | ||
88e5c029 JL |
8256 | /* Only 2 real operands to the addition. One of the input operands must |
8257 | be the same as the output operand. */ | |
2fe24884 JL |
8258 | if (! rtx_equal_p (operands[3], operands[4]) |
8259 | && ! rtx_equal_p (operands[3], operands[5])) | |
8260 | return 0; | |
8261 | ||
1e5f1716 | 8262 | /* Inout operand of add cannot conflict with any operands from multiply. */ |
2fe24884 JL |
8263 | if (rtx_equal_p (operands[3], operands[0]) |
8264 | || rtx_equal_p (operands[3], operands[1]) | |
8265 | || rtx_equal_p (operands[3], operands[2])) | |
8266 | return 0; | |
8267 | ||
1e5f1716 | 8268 | /* multiply cannot feed into addition operands. */ |
2fe24884 JL |
8269 | if (rtx_equal_p (operands[4], operands[0]) |
8270 | || rtx_equal_p (operands[5], operands[0])) | |
8271 | return 0; | |
8272 | ||
d85ab966 JL |
8273 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8274 | if (mode == SFmode | |
88624c0e JL |
8275 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8276 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8277 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8278 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8279 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8280 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
d85ab966 JL |
8281 | return 0; |
8282 | ||
2fe24884 JL |
8283 | /* Passed. Operands are suitable for fmpyadd. */ |
8284 | return 1; | |
8285 | } | |
8286 | ||
35d434ed JDA |
8287 | #if !defined(USE_COLLECT2) |
8288 | static void | |
b7849684 | 8289 | pa_asm_out_constructor (rtx symbol, int priority) |
35d434ed JDA |
8290 | { |
8291 | if (!function_label_operand (symbol, VOIDmode)) | |
8292 | hppa_encode_label (symbol); | |
8293 | ||
8294 | #ifdef CTORS_SECTION_ASM_OP | |
8295 | default_ctor_section_asm_out_constructor (symbol, priority); | |
8296 | #else | |
8297 | # ifdef TARGET_ASM_NAMED_SECTION | |
8298 | default_named_section_asm_out_constructor (symbol, priority); | |
8299 | # else | |
8300 | default_stabs_asm_out_constructor (symbol, priority); | |
8301 | # endif | |
8302 | #endif | |
8303 | } | |
8304 | ||
8305 | static void | |
b7849684 | 8306 | pa_asm_out_destructor (rtx symbol, int priority) |
35d434ed JDA |
8307 | { |
8308 | if (!function_label_operand (symbol, VOIDmode)) | |
8309 | hppa_encode_label (symbol); | |
8310 | ||
8311 | #ifdef DTORS_SECTION_ASM_OP | |
8312 | default_dtor_section_asm_out_destructor (symbol, priority); | |
8313 | #else | |
8314 | # ifdef TARGET_ASM_NAMED_SECTION | |
8315 | default_named_section_asm_out_destructor (symbol, priority); | |
8316 | # else | |
8317 | default_stabs_asm_out_destructor (symbol, priority); | |
8318 | # endif | |
8319 | #endif | |
8320 | } | |
8321 | #endif | |
8322 | ||
d4482715 JDA |
8323 | /* This function places uninitialized global data in the bss section. |
8324 | The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this | |
8325 | function on the SOM port to prevent uninitialized global data from | |
8326 | being placed in the data section. */ | |
8327 | ||
8328 | void | |
8329 | pa_asm_output_aligned_bss (FILE *stream, | |
8330 | const char *name, | |
8331 | unsigned HOST_WIDE_INT size, | |
8332 | unsigned int align) | |
8333 | { | |
d6b5193b | 8334 | switch_to_section (bss_section); |
d4482715 JDA |
8335 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); |
8336 | ||
8337 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
8338 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); | |
8339 | #endif | |
8340 | ||
8341 | #ifdef ASM_OUTPUT_SIZE_DIRECTIVE | |
8342 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
8343 | #endif | |
8344 | ||
8345 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); | |
8346 | ASM_OUTPUT_LABEL (stream, name); | |
8347 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
8348 | } | |
8349 | ||
8350 | /* Both the HP and GNU assemblers under HP-UX provide a .comm directive | |
8351 | that doesn't allow the alignment of global common storage to be directly | |
8352 | specified. The SOM linker aligns common storage based on the rounded | |
8353 | value of the NUM_BYTES parameter in the .comm directive. It's not | |
8354 | possible to use the .align directive as it doesn't affect the alignment | |
8355 | of the label associated with a .comm directive. */ | |
8356 | ||
8357 | void | |
8358 | pa_asm_output_aligned_common (FILE *stream, | |
8359 | const char *name, | |
8360 | unsigned HOST_WIDE_INT size, | |
8361 | unsigned int align) | |
8362 | { | |
22f549fd JDA |
8363 | unsigned int max_common_align; |
8364 | ||
8365 | max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64); | |
8366 | if (align > max_common_align) | |
8367 | { | |
d4ee4d25 | 8368 | warning (0, "alignment (%u) for %s exceeds maximum alignment " |
22f549fd JDA |
8369 | "for global common data. Using %u", |
8370 | align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT); | |
8371 | align = max_common_align; | |
8372 | } | |
8373 | ||
d6b5193b | 8374 | switch_to_section (bss_section); |
d4482715 JDA |
8375 | |
8376 | assemble_name (stream, name); | |
8377 | fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n", | |
8378 | MAX (size, align / BITS_PER_UNIT)); | |
8379 | } | |
8380 | ||
8381 | /* We can't use .comm for local common storage as the SOM linker effectively | |
8382 | treats the symbol as universal and uses the same storage for local symbols | |
8383 | with the same name in different object files. The .block directive | |
8384 | reserves an uninitialized block of storage. However, it's not common | |
8385 | storage. Fortunately, GCC never requests common storage with the same | |
8386 | name in any given translation unit. */ | |
8387 | ||
8388 | void | |
8389 | pa_asm_output_aligned_local (FILE *stream, | |
8390 | const char *name, | |
8391 | unsigned HOST_WIDE_INT size, | |
8392 | unsigned int align) | |
8393 | { | |
d6b5193b | 8394 | switch_to_section (bss_section); |
d4482715 JDA |
8395 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); |
8396 | ||
8397 | #ifdef LOCAL_ASM_OP | |
8398 | fprintf (stream, "%s", LOCAL_ASM_OP); | |
8399 | assemble_name (stream, name); | |
8400 | fprintf (stream, "\n"); | |
8401 | #endif | |
8402 | ||
8403 | ASM_OUTPUT_LABEL (stream, name); | |
8404 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
8405 | } | |
8406 | ||
88e5c029 JL |
8407 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
8408 | use in fmpysub instructions. */ | |
2fe24884 | 8409 | int |
b7849684 | 8410 | fmpysuboperands (rtx *operands) |
2fe24884 | 8411 | { |
f133af4c | 8412 | enum machine_mode mode = GET_MODE (operands[0]); |
2fe24884 | 8413 | |
d85ab966 JL |
8414 | /* Must be a floating point mode. */ |
8415 | if (mode != SFmode && mode != DFmode) | |
8416 | return 0; | |
8417 | ||
2fe24884 | 8418 | /* All modes must be the same. */ |
f133af4c TG |
8419 | if (! (mode == GET_MODE (operands[1]) |
8420 | && mode == GET_MODE (operands[2]) | |
8421 | && mode == GET_MODE (operands[3]) | |
8422 | && mode == GET_MODE (operands[4]) | |
8423 | && mode == GET_MODE (operands[5]))) | |
2fe24884 JL |
8424 | return 0; |
8425 | ||
d85ab966 JL |
8426 | /* All operands must be registers. */ |
8427 | if (! (GET_CODE (operands[1]) == REG | |
8428 | && GET_CODE (operands[2]) == REG | |
8429 | && GET_CODE (operands[3]) == REG | |
8430 | && GET_CODE (operands[4]) == REG | |
8431 | && GET_CODE (operands[5]) == REG)) | |
2fe24884 JL |
8432 | return 0; |
8433 | ||
88e5c029 JL |
8434 | /* Only 2 real operands to the subtraction. Subtraction is not a commutative |
8435 | operation, so operands[4] must be the same as operand[3]. */ | |
2fe24884 JL |
8436 | if (! rtx_equal_p (operands[3], operands[4])) |
8437 | return 0; | |
8438 | ||
1e5f1716 | 8439 | /* multiply cannot feed into subtraction. */ |
88e5c029 | 8440 | if (rtx_equal_p (operands[5], operands[0])) |
2fe24884 JL |
8441 | return 0; |
8442 | ||
1e5f1716 | 8443 | /* Inout operand of sub cannot conflict with any operands from multiply. */ |
2fe24884 JL |
8444 | if (rtx_equal_p (operands[3], operands[0]) |
8445 | || rtx_equal_p (operands[3], operands[1]) | |
8446 | || rtx_equal_p (operands[3], operands[2])) | |
8447 | return 0; | |
8448 | ||
d85ab966 JL |
8449 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8450 | if (mode == SFmode | |
88624c0e JL |
8451 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8452 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8453 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8454 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8455 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8456 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
d85ab966 JL |
8457 | return 0; |
8458 | ||
2fe24884 JL |
8459 | /* Passed. Operands are suitable for fmpysub. */ |
8460 | return 1; | |
8461 | } | |
8462 | ||
c2264220 JL |
8463 | /* Return 1 if the given constant is 2, 4, or 8. These are the valid |
8464 | constants for shadd instructions. */ | |
c9a88190 | 8465 | int |
b7849684 | 8466 | shadd_constant_p (int val) |
c2264220 JL |
8467 | { |
8468 | if (val == 2 || val == 4 || val == 8) | |
8469 | return 1; | |
8470 | else | |
8471 | return 0; | |
8472 | } | |
4802a0d6 | 8473 | |
d8f95bed JDA |
8474 | /* Return 1 if OP is valid as a base or index register in a |
8475 | REG+REG address. */ | |
68944452 JL |
8476 | |
8477 | int | |
d8f95bed | 8478 | borx_reg_operand (rtx op, enum machine_mode mode) |
68944452 | 8479 | { |
d8f95bed | 8480 | if (GET_CODE (op) != REG) |
31d4f31f JL |
8481 | return 0; |
8482 | ||
d8f95bed JDA |
8483 | /* We must reject virtual registers as the only expressions that |
8484 | can be instantiated are REG and REG+CONST. */ | |
8485 | if (op == virtual_incoming_args_rtx | |
8486 | || op == virtual_stack_vars_rtx | |
8487 | || op == virtual_stack_dynamic_rtx | |
8488 | || op == virtual_outgoing_args_rtx | |
8489 | || op == virtual_cfa_rtx) | |
8490 | return 0; | |
68944452 | 8491 | |
31d4f31f | 8492 | /* While it's always safe to index off the frame pointer, it's not |
d8f95bed JDA |
8493 | profitable to do so when the frame pointer is being eliminated. */ |
8494 | if (!reload_completed | |
8495 | && flag_omit_frame_pointer | |
e3b5732b | 8496 | && !cfun->calls_alloca |
d8f95bed JDA |
8497 | && op == frame_pointer_rtx) |
8498 | return 0; | |
68944452 | 8499 | |
d8f95bed | 8500 | return register_operand (op, mode); |
68944452 JL |
8501 | } |
8502 | ||
8a149902 RK |
8503 | /* Return 1 if this operand is anything other than a hard register. */ |
8504 | ||
8505 | int | |
b7849684 | 8506 | non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
8a149902 RK |
8507 | { |
8508 | return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER); | |
8509 | } | |
8510 | ||
b9821af8 | 8511 | /* Return 1 if INSN branches forward. Should be using insn_addresses |
fe19a83d | 8512 | to avoid walking through all the insns... */ |
51723711 | 8513 | static int |
b7849684 | 8514 | forward_branch_p (rtx insn) |
b9821af8 JL |
8515 | { |
8516 | rtx label = JUMP_LABEL (insn); | |
8517 | ||
8518 | while (insn) | |
8519 | { | |
8520 | if (insn == label) | |
8521 | break; | |
8522 | else | |
8523 | insn = NEXT_INSN (insn); | |
8524 | } | |
8525 | ||
8526 | return (insn == label); | |
8527 | } | |
8528 | ||
b1a275e1 JL |
8529 | /* Return 1 if OP is an equality comparison, else return 0. */ |
8530 | int | |
b7849684 | 8531 | eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
b1a275e1 JL |
8532 | { |
8533 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
8534 | } | |
8535 | ||
2c4ff308 JL |
8536 | /* Return 1 if INSN is in the delay slot of a call instruction. */ |
8537 | int | |
b7849684 | 8538 | jump_in_call_delay (rtx insn) |
2c4ff308 JL |
8539 | { |
8540 | ||
8541 | if (GET_CODE (insn) != JUMP_INSN) | |
8542 | return 0; | |
8543 | ||
8544 | if (PREV_INSN (insn) | |
8545 | && PREV_INSN (PREV_INSN (insn)) | |
02a57c73 | 8546 | && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN) |
2c4ff308 | 8547 | { |
02a57c73 | 8548 | rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn))); |
2c4ff308 JL |
8549 | |
8550 | return (GET_CODE (PATTERN (test_insn)) == SEQUENCE | |
8551 | && XVECEXP (PATTERN (test_insn), 0, 1) == insn); | |
8552 | ||
8553 | } | |
8554 | else | |
8555 | return 0; | |
8556 | } | |
746a9efa | 8557 | |
b1092901 JL |
8558 | /* Output an unconditional move and branch insn. */ |
8559 | ||
519104fe | 8560 | const char * |
16d74a3c | 8561 | output_parallel_movb (rtx *operands, rtx insn) |
b1092901 | 8562 | { |
16d74a3c JDA |
8563 | int length = get_attr_length (insn); |
8564 | ||
b1092901 JL |
8565 | /* These are the cases in which we win. */ |
8566 | if (length == 4) | |
8567 | return "mov%I1b,tr %1,%0,%2"; | |
8568 | ||
16d74a3c JDA |
8569 | /* None of the following cases win, but they don't lose either. */ |
8570 | if (length == 8) | |
b1092901 | 8571 | { |
16d74a3c JDA |
8572 | if (dbr_sequence_length () == 0) |
8573 | { | |
8574 | /* Nothing in the delay slot, fake it by putting the combined | |
8575 | insn (the copy or add) in the delay slot of a bl. */ | |
8576 | if (GET_CODE (operands[1]) == CONST_INT) | |
8577 | return "b %2\n\tldi %1,%0"; | |
8578 | else | |
8579 | return "b %2\n\tcopy %1,%0"; | |
8580 | } | |
b1092901 | 8581 | else |
16d74a3c JDA |
8582 | { |
8583 | /* Something in the delay slot, but we've got a long branch. */ | |
8584 | if (GET_CODE (operands[1]) == CONST_INT) | |
8585 | return "ldi %1,%0\n\tb %2"; | |
8586 | else | |
8587 | return "copy %1,%0\n\tb %2"; | |
8588 | } | |
b1092901 | 8589 | } |
16d74a3c JDA |
8590 | |
8591 | if (GET_CODE (operands[1]) == CONST_INT) | |
8592 | output_asm_insn ("ldi %1,%0", operands); | |
b1092901 | 8593 | else |
16d74a3c JDA |
8594 | output_asm_insn ("copy %1,%0", operands); |
8595 | return output_lbranch (operands[2], insn, 1); | |
b1092901 JL |
8596 | } |
8597 | ||
8598 | /* Output an unconditional add and branch insn. */ | |
8599 | ||
519104fe | 8600 | const char * |
16d74a3c | 8601 | output_parallel_addb (rtx *operands, rtx insn) |
b1092901 | 8602 | { |
16d74a3c JDA |
8603 | int length = get_attr_length (insn); |
8604 | ||
b1092901 JL |
8605 | /* To make life easy we want operand0 to be the shared input/output |
8606 | operand and operand1 to be the readonly operand. */ | |
8607 | if (operands[0] == operands[1]) | |
8608 | operands[1] = operands[2]; | |
8609 | ||
8610 | /* These are the cases in which we win. */ | |
8611 | if (length == 4) | |
8612 | return "add%I1b,tr %1,%0,%3"; | |
8613 | ||
16d74a3c JDA |
8614 | /* None of the following cases win, but they don't lose either. */ |
8615 | if (length == 8) | |
b1092901 | 8616 | { |
16d74a3c JDA |
8617 | if (dbr_sequence_length () == 0) |
8618 | /* Nothing in the delay slot, fake it by putting the combined | |
8619 | insn (the copy or add) in the delay slot of a bl. */ | |
8620 | return "b %3\n\tadd%I1 %1,%0,%0"; | |
8621 | else | |
8622 | /* Something in the delay slot, but we've got a long branch. */ | |
8623 | return "add%I1 %1,%0,%0\n\tb %3"; | |
b1092901 | 8624 | } |
16d74a3c JDA |
8625 | |
8626 | output_asm_insn ("add%I1 %1,%0,%0", operands); | |
8627 | return output_lbranch (operands[3], insn, 1); | |
b1092901 JL |
8628 | } |
8629 | ||
1c31ecf6 JDA |
8630 | /* Return nonzero if INSN (a jump insn) immediately follows a call |
8631 | to a named function. This is used to avoid filling the delay slot | |
8632 | of the jump since it can usually be eliminated by modifying RP in | |
8633 | the delay slot of the call. */ | |
6619e96c | 8634 | |
51723711 | 8635 | int |
b7849684 | 8636 | following_call (rtx insn) |
b1092901 | 8637 | { |
6d8d2bbc | 8638 | if (! TARGET_JUMP_IN_DELAY) |
f9bd8d8e JL |
8639 | return 0; |
8640 | ||
b1092901 JL |
8641 | /* Find the previous real insn, skipping NOTEs. */ |
8642 | insn = PREV_INSN (insn); | |
8643 | while (insn && GET_CODE (insn) == NOTE) | |
8644 | insn = PREV_INSN (insn); | |
8645 | ||
8646 | /* Check for CALL_INSNs and millicode calls. */ | |
8647 | if (insn | |
cdc0de30 JL |
8648 | && ((GET_CODE (insn) == CALL_INSN |
8649 | && get_attr_type (insn) != TYPE_DYNCALL) | |
b1092901 JL |
8650 | || (GET_CODE (insn) == INSN |
8651 | && GET_CODE (PATTERN (insn)) != SEQUENCE | |
8652 | && GET_CODE (PATTERN (insn)) != USE | |
8653 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8654 | && get_attr_type (insn) == TYPE_MILLI))) | |
8655 | return 1; | |
8656 | ||
8657 | return 0; | |
8658 | } | |
8659 | ||
746a9efa JL |
8660 | /* We use this hook to perform a PA specific optimization which is difficult |
8661 | to do in earlier passes. | |
8662 | ||
8663 | We want the delay slots of branches within jump tables to be filled. | |
8664 | None of the compiler passes at the moment even has the notion that a | |
8665 | PA jump table doesn't contain addresses, but instead contains actual | |
8666 | instructions! | |
8667 | ||
8668 | Because we actually jump into the table, the addresses of each entry | |
ddd5a7c1 | 8669 | must stay constant in relation to the beginning of the table (which |
746a9efa JL |
8670 | itself must stay constant relative to the instruction to jump into |
8671 | it). I don't believe we can guarantee earlier passes of the compiler | |
8672 | will adhere to those rules. | |
8673 | ||
8674 | So, late in the compilation process we find all the jump tables, and | |
112cdef5 | 8675 | expand them into real code -- e.g. each entry in the jump table vector |
746a9efa JL |
8676 | will get an appropriate label followed by a jump to the final target. |
8677 | ||
8678 | Reorg and the final jump pass can then optimize these branches and | |
8679 | fill their delay slots. We end up with smaller, more efficient code. | |
8680 | ||
6619e96c | 8681 | The jump instructions within the table are special; we must be able |
746a9efa JL |
8682 | to identify them during assembly output (if the jumps don't get filled |
8683 | we need to emit a nop rather than nullifying the delay slot)). We | |
cb4d476c JDA |
8684 | identify jumps in switch tables by using insns with the attribute |
8685 | type TYPE_BTABLE_BRANCH. | |
251ffdee JL |
8686 | |
8687 | We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB | |
8688 | insns. This serves two purposes, first it prevents jump.c from | |
8689 | noticing that the last N entries in the table jump to the instruction | |
8690 | immediately after the table and deleting the jumps. Second, those | |
8691 | insns mark where we should emit .begin_brtab and .end_brtab directives | |
8692 | when using GAS (allows for better link time optimizations). */ | |
746a9efa | 8693 | |
18dbd950 | 8694 | static void |
b7849684 | 8695 | pa_reorg (void) |
746a9efa JL |
8696 | { |
8697 | rtx insn; | |
8698 | ||
18dbd950 | 8699 | remove_useless_addtr_insns (1); |
d8b79470 | 8700 | |
86001391 | 8701 | if (pa_cpu < PROCESSOR_8000) |
18dbd950 | 8702 | pa_combine_instructions (); |
86001391 | 8703 | |
c4bb6b38 | 8704 | |
d8b79470 | 8705 | /* This is fairly cheap, so always run it if optimizing. */ |
3e056efc | 8706 | if (optimize > 0 && !TARGET_BIG_SWITCH) |
746a9efa | 8707 | { |
29763968 | 8708 | /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */ |
18dbd950 | 8709 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
746a9efa | 8710 | { |
cb4d476c | 8711 | rtx pattern, tmp, location, label; |
746a9efa JL |
8712 | unsigned int length, i; |
8713 | ||
29763968 | 8714 | /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */ |
746a9efa | 8715 | if (GET_CODE (insn) != JUMP_INSN |
29763968 JL |
8716 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8717 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
746a9efa JL |
8718 | continue; |
8719 | ||
251ffdee JL |
8720 | /* Emit marker for the beginning of the branch table. */ |
8721 | emit_insn_before (gen_begin_brtab (), insn); | |
ad238e4b | 8722 | |
746a9efa JL |
8723 | pattern = PATTERN (insn); |
8724 | location = PREV_INSN (insn); | |
29763968 | 8725 | length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC); |
ad238e4b | 8726 | |
746a9efa JL |
8727 | for (i = 0; i < length; i++) |
8728 | { | |
3e056efc JL |
8729 | /* Emit a label before each jump to keep jump.c from |
8730 | removing this code. */ | |
8731 | tmp = gen_label_rtx (); | |
8732 | LABEL_NUSES (tmp) = 1; | |
8733 | emit_label_after (tmp, location); | |
8734 | location = NEXT_INSN (location); | |
8735 | ||
29763968 | 8736 | if (GET_CODE (pattern) == ADDR_VEC) |
cb4d476c | 8737 | label = XEXP (XVECEXP (pattern, 0, i), 0); |
29763968 | 8738 | else |
cb4d476c JDA |
8739 | label = XEXP (XVECEXP (pattern, 1, i), 0); |
8740 | ||
8741 | tmp = gen_short_jump (label); | |
8742 | ||
8743 | /* Emit the jump itself. */ | |
8744 | tmp = emit_jump_insn_after (tmp, location); | |
8745 | JUMP_LABEL (tmp) = label; | |
8746 | LABEL_NUSES (label)++; | |
8747 | location = NEXT_INSN (location); | |
746a9efa JL |
8748 | |
8749 | /* Emit a BARRIER after the jump. */ | |
746a9efa | 8750 | emit_barrier_after (location); |
746a9efa JL |
8751 | location = NEXT_INSN (location); |
8752 | } | |
ad238e4b | 8753 | |
251ffdee JL |
8754 | /* Emit marker for the end of the branch table. */ |
8755 | emit_insn_before (gen_end_brtab (), location); | |
8756 | location = NEXT_INSN (location); | |
8757 | emit_barrier_after (location); | |
3e056efc | 8758 | |
29763968 | 8759 | /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */ |
746a9efa JL |
8760 | delete_insn (insn); |
8761 | } | |
8762 | } | |
251ffdee | 8763 | else |
ad238e4b | 8764 | { |
cb4d476c JDA |
8765 | /* Still need brtab marker insns. FIXME: the presence of these |
8766 | markers disables output of the branch table to readonly memory, | |
8767 | and any alignment directives that might be needed. Possibly, | |
8768 | the begin_brtab insn should be output before the label for the | |
1ae58c30 | 8769 | table. This doesn't matter at the moment since the tables are |
cb4d476c | 8770 | always output in the text section. */ |
18dbd950 | 8771 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
ad238e4b JL |
8772 | { |
8773 | /* Find an ADDR_VEC insn. */ | |
8774 | if (GET_CODE (insn) != JUMP_INSN | |
29763968 JL |
8775 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8776 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
ad238e4b JL |
8777 | continue; |
8778 | ||
8779 | /* Now generate markers for the beginning and end of the | |
956d6950 | 8780 | branch table. */ |
ad238e4b JL |
8781 | emit_insn_before (gen_begin_brtab (), insn); |
8782 | emit_insn_after (gen_end_brtab (), insn); | |
8783 | } | |
8784 | } | |
aba892c4 | 8785 | } |
c4bb6b38 JL |
8786 | |
8787 | /* The PA has a number of odd instructions which can perform multiple | |
8788 | tasks at once. On first generation PA machines (PA1.0 and PA1.1) | |
8789 | it may be profitable to combine two instructions into one instruction | |
8790 | with two outputs. It's not profitable PA2.0 machines because the | |
8791 | two outputs would take two slots in the reorder buffers. | |
8792 | ||
8793 | This routine finds instructions which can be combined and combines | |
8794 | them. We only support some of the potential combinations, and we | |
8795 | only try common ways to find suitable instructions. | |
8796 | ||
8797 | * addb can add two registers or a register and a small integer | |
8798 | and jump to a nearby (+-8k) location. Normally the jump to the | |
8799 | nearby location is conditional on the result of the add, but by | |
8800 | using the "true" condition we can make the jump unconditional. | |
8801 | Thus addb can perform two independent operations in one insn. | |
8802 | ||
8803 | * movb is similar to addb in that it can perform a reg->reg | |
8804 | or small immediate->reg copy and jump to a nearby (+-8k location). | |
8805 | ||
8806 | * fmpyadd and fmpysub can perform a FP multiply and either an | |
8807 | FP add or FP sub if the operands of the multiply and add/sub are | |
8808 | independent (there are other minor restrictions). Note both | |
8809 | the fmpy and fadd/fsub can in theory move to better spots according | |
8810 | to data dependencies, but for now we require the fmpy stay at a | |
8811 | fixed location. | |
8812 | ||
8813 | * Many of the memory operations can perform pre & post updates | |
8814 | of index registers. GCC's pre/post increment/decrement addressing | |
8815 | is far too simple to take advantage of all the possibilities. This | |
8816 | pass may not be suitable since those insns may not be independent. | |
8817 | ||
8818 | * comclr can compare two ints or an int and a register, nullify | |
8819 | the following instruction and zero some other register. This | |
8820 | is more difficult to use as it's harder to find an insn which | |
8821 | will generate a comclr than finding something like an unconditional | |
8822 | branch. (conditional moves & long branches create comclr insns). | |
8823 | ||
8824 | * Most arithmetic operations can conditionally skip the next | |
8825 | instruction. They can be viewed as "perform this operation | |
8826 | and conditionally jump to this nearby location" (where nearby | |
8827 | is an insns away). These are difficult to use due to the | |
8828 | branch length restrictions. */ | |
8829 | ||
51723711 | 8830 | static void |
b7849684 | 8831 | pa_combine_instructions (void) |
c4bb6b38 | 8832 | { |
0a2aaacc | 8833 | rtx anchor, new_rtx; |
c4bb6b38 JL |
8834 | |
8835 | /* This can get expensive since the basic algorithm is on the | |
8836 | order of O(n^2) (or worse). Only do it for -O2 or higher | |
956d6950 | 8837 | levels of optimization. */ |
c4bb6b38 JL |
8838 | if (optimize < 2) |
8839 | return; | |
8840 | ||
8841 | /* Walk down the list of insns looking for "anchor" insns which | |
8842 | may be combined with "floating" insns. As the name implies, | |
8843 | "anchor" instructions don't move, while "floating" insns may | |
8844 | move around. */ | |
0a2aaacc KG |
8845 | new_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX)); |
8846 | new_rtx = make_insn_raw (new_rtx); | |
c4bb6b38 JL |
8847 | |
8848 | for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor)) | |
8849 | { | |
8850 | enum attr_pa_combine_type anchor_attr; | |
8851 | enum attr_pa_combine_type floater_attr; | |
8852 | ||
8853 | /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs. | |
8854 | Also ignore any special USE insns. */ | |
51723711 | 8855 | if ((GET_CODE (anchor) != INSN |
c4bb6b38 | 8856 | && GET_CODE (anchor) != JUMP_INSN |
51723711 | 8857 | && GET_CODE (anchor) != CALL_INSN) |
c4bb6b38 JL |
8858 | || GET_CODE (PATTERN (anchor)) == USE |
8859 | || GET_CODE (PATTERN (anchor)) == CLOBBER | |
8860 | || GET_CODE (PATTERN (anchor)) == ADDR_VEC | |
8861 | || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC) | |
8862 | continue; | |
8863 | ||
8864 | anchor_attr = get_attr_pa_combine_type (anchor); | |
8865 | /* See if anchor is an insn suitable for combination. */ | |
8866 | if (anchor_attr == PA_COMBINE_TYPE_FMPY | |
8867 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8868 | || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
8869 | && ! forward_branch_p (anchor))) | |
8870 | { | |
8871 | rtx floater; | |
8872 | ||
8873 | for (floater = PREV_INSN (anchor); | |
8874 | floater; | |
8875 | floater = PREV_INSN (floater)) | |
8876 | { | |
8877 | if (GET_CODE (floater) == NOTE | |
8878 | || (GET_CODE (floater) == INSN | |
8879 | && (GET_CODE (PATTERN (floater)) == USE | |
8880 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
8881 | continue; | |
8882 | ||
8883 | /* Anything except a regular INSN will stop our search. */ | |
8884 | if (GET_CODE (floater) != INSN | |
8885 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
8886 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
8887 | { | |
8888 | floater = NULL_RTX; | |
8889 | break; | |
8890 | } | |
8891 | ||
8892 | /* See if FLOATER is suitable for combination with the | |
8893 | anchor. */ | |
8894 | floater_attr = get_attr_pa_combine_type (floater); | |
8895 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
8896 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
8897 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8898 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
8899 | { | |
8900 | /* If ANCHOR and FLOATER can be combined, then we're | |
8901 | done with this pass. */ | |
0a2aaacc | 8902 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
c4bb6b38 JL |
8903 | SET_DEST (PATTERN (floater)), |
8904 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
8905 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
8906 | break; | |
8907 | } | |
8908 | ||
8909 | else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
8910 | && floater_attr == PA_COMBINE_TYPE_ADDMOVE) | |
8911 | { | |
8912 | if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS) | |
8913 | { | |
0a2aaacc | 8914 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
c4bb6b38 JL |
8915 | SET_DEST (PATTERN (floater)), |
8916 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
8917 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
8918 | break; | |
8919 | } | |
8920 | else | |
8921 | { | |
0a2aaacc | 8922 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
c4bb6b38 JL |
8923 | SET_DEST (PATTERN (floater)), |
8924 | SET_SRC (PATTERN (floater)), | |
8925 | SET_SRC (PATTERN (floater)))) | |
8926 | break; | |
8927 | } | |
8928 | } | |
8929 | } | |
8930 | ||
8931 | /* If we didn't find anything on the backwards scan try forwards. */ | |
8932 | if (!floater | |
8933 | && (anchor_attr == PA_COMBINE_TYPE_FMPY | |
8934 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB)) | |
8935 | { | |
8936 | for (floater = anchor; floater; floater = NEXT_INSN (floater)) | |
8937 | { | |
8938 | if (GET_CODE (floater) == NOTE | |
8939 | || (GET_CODE (floater) == INSN | |
8940 | && (GET_CODE (PATTERN (floater)) == USE | |
8941 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
6619e96c | 8942 | |
c4bb6b38 JL |
8943 | continue; |
8944 | ||
8945 | /* Anything except a regular INSN will stop our search. */ | |
8946 | if (GET_CODE (floater) != INSN | |
8947 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
8948 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
8949 | { | |
8950 | floater = NULL_RTX; | |
8951 | break; | |
8952 | } | |
8953 | ||
8954 | /* See if FLOATER is suitable for combination with the | |
8955 | anchor. */ | |
8956 | floater_attr = get_attr_pa_combine_type (floater); | |
8957 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
8958 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
8959 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8960 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
8961 | { | |
8962 | /* If ANCHOR and FLOATER can be combined, then we're | |
8963 | done with this pass. */ | |
0a2aaacc | 8964 | if (pa_can_combine_p (new_rtx, anchor, floater, 1, |
c4bb6b38 | 8965 | SET_DEST (PATTERN (floater)), |
831c1763 AM |
8966 | XEXP (SET_SRC (PATTERN (floater)), |
8967 | 0), | |
8968 | XEXP (SET_SRC (PATTERN (floater)), | |
8969 | 1))) | |
c4bb6b38 JL |
8970 | break; |
8971 | } | |
8972 | } | |
8973 | } | |
8974 | ||
8975 | /* FLOATER will be nonzero if we found a suitable floating | |
8976 | insn for combination with ANCHOR. */ | |
8977 | if (floater | |
8978 | && (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8979 | || anchor_attr == PA_COMBINE_TYPE_FMPY)) | |
8980 | { | |
8981 | /* Emit the new instruction and delete the old anchor. */ | |
c5c76735 JL |
8982 | emit_insn_before (gen_rtx_PARALLEL |
8983 | (VOIDmode, | |
8984 | gen_rtvec (2, PATTERN (anchor), | |
8985 | PATTERN (floater))), | |
8986 | anchor); | |
8987 | ||
a38e7aa5 | 8988 | SET_INSN_DELETED (anchor); |
c4bb6b38 JL |
8989 | |
8990 | /* Emit a special USE insn for FLOATER, then delete | |
8991 | the floating insn. */ | |
ad2c71b7 | 8992 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
c4bb6b38 JL |
8993 | delete_insn (floater); |
8994 | ||
8995 | continue; | |
8996 | } | |
8997 | else if (floater | |
8998 | && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH) | |
8999 | { | |
9000 | rtx temp; | |
9001 | /* Emit the new_jump instruction and delete the old anchor. */ | |
c5c76735 JL |
9002 | temp |
9003 | = emit_jump_insn_before (gen_rtx_PARALLEL | |
9004 | (VOIDmode, | |
9005 | gen_rtvec (2, PATTERN (anchor), | |
9006 | PATTERN (floater))), | |
9007 | anchor); | |
9008 | ||
c4bb6b38 | 9009 | JUMP_LABEL (temp) = JUMP_LABEL (anchor); |
a38e7aa5 | 9010 | SET_INSN_DELETED (anchor); |
c4bb6b38 JL |
9011 | |
9012 | /* Emit a special USE insn for FLOATER, then delete | |
9013 | the floating insn. */ | |
ad2c71b7 | 9014 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
c4bb6b38 JL |
9015 | delete_insn (floater); |
9016 | continue; | |
9017 | } | |
9018 | } | |
9019 | } | |
9020 | } | |
9021 | ||
0952f89b | 9022 | static int |
0a2aaacc | 9023 | pa_can_combine_p (rtx new_rtx, rtx anchor, rtx floater, int reversed, rtx dest, |
b7849684 | 9024 | rtx src1, rtx src2) |
c4bb6b38 JL |
9025 | { |
9026 | int insn_code_number; | |
9027 | rtx start, end; | |
9028 | ||
9029 | /* Create a PARALLEL with the patterns of ANCHOR and | |
9030 | FLOATER, try to recognize it, then test constraints | |
9031 | for the resulting pattern. | |
9032 | ||
9033 | If the pattern doesn't match or the constraints | |
9034 | aren't met keep searching for a suitable floater | |
9035 | insn. */ | |
0a2aaacc KG |
9036 | XVECEXP (PATTERN (new_rtx), 0, 0) = PATTERN (anchor); |
9037 | XVECEXP (PATTERN (new_rtx), 0, 1) = PATTERN (floater); | |
9038 | INSN_CODE (new_rtx) = -1; | |
9039 | insn_code_number = recog_memoized (new_rtx); | |
c4bb6b38 | 9040 | if (insn_code_number < 0 |
0a2aaacc | 9041 | || (extract_insn (new_rtx), ! constrain_operands (1))) |
c4bb6b38 JL |
9042 | return 0; |
9043 | ||
9044 | if (reversed) | |
9045 | { | |
9046 | start = anchor; | |
9047 | end = floater; | |
9048 | } | |
9049 | else | |
9050 | { | |
9051 | start = floater; | |
9052 | end = anchor; | |
9053 | } | |
9054 | ||
9055 | /* There's up to three operands to consider. One | |
9056 | output and two inputs. | |
9057 | ||
9058 | The output must not be used between FLOATER & ANCHOR | |
9059 | exclusive. The inputs must not be set between | |
9060 | FLOATER and ANCHOR exclusive. */ | |
9061 | ||
9062 | if (reg_used_between_p (dest, start, end)) | |
9063 | return 0; | |
9064 | ||
9065 | if (reg_set_between_p (src1, start, end)) | |
9066 | return 0; | |
9067 | ||
9068 | if (reg_set_between_p (src2, start, end)) | |
9069 | return 0; | |
9070 | ||
9071 | /* If we get here, then everything is good. */ | |
9072 | return 1; | |
9073 | } | |
b9cd54d2 | 9074 | |
2561a923 | 9075 | /* Return nonzero if references for INSN are delayed. |
b9cd54d2 JL |
9076 | |
9077 | Millicode insns are actually function calls with some special | |
9078 | constraints on arguments and register usage. | |
9079 | ||
9080 | Millicode calls always expect their arguments in the integer argument | |
9081 | registers, and always return their result in %r29 (ret1). They | |
7d8b1412 AM |
9082 | are expected to clobber their arguments, %r1, %r29, and the return |
9083 | pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else. | |
9084 | ||
9085 | This function tells reorg that the references to arguments and | |
9086 | millicode calls do not appear to happen until after the millicode call. | |
9087 | This allows reorg to put insns which set the argument registers into the | |
9088 | delay slot of the millicode call -- thus they act more like traditional | |
9089 | CALL_INSNs. | |
9090 | ||
1e5f1716 | 9091 | Note we cannot consider side effects of the insn to be delayed because |
7d8b1412 AM |
9092 | the branch and link insn will clobber the return pointer. If we happened |
9093 | to use the return pointer in the delay slot of the call, then we lose. | |
b9cd54d2 JL |
9094 | |
9095 | get_attr_type will try to recognize the given insn, so make sure to | |
9096 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
9097 | in particular. */ | |
9098 | int | |
b7849684 | 9099 | insn_refs_are_delayed (rtx insn) |
b9cd54d2 | 9100 | { |
6619e96c | 9101 | return ((GET_CODE (insn) == INSN |
b9cd54d2 JL |
9102 | && GET_CODE (PATTERN (insn)) != SEQUENCE |
9103 | && GET_CODE (PATTERN (insn)) != USE | |
9104 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
9105 | && get_attr_type (insn) == TYPE_MILLI)); | |
9106 | } | |
d07d525a | 9107 | |
44571d6e JDA |
9108 | /* On the HP-PA the value is found in register(s) 28(-29), unless |
9109 | the mode is SF or DF. Then the value is returned in fr4 (32). | |
9110 | ||
9111 | This must perform the same promotions as PROMOTE_MODE, else | |
3f12cd9b | 9112 | TARGET_PROMOTE_FUNCTION_RETURN will not work correctly. |
44571d6e JDA |
9113 | |
9114 | Small structures must be returned in a PARALLEL on PA64 in order | |
9115 | to match the HP Compiler ABI. */ | |
9116 | ||
9117 | rtx | |
586de218 | 9118 | function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED) |
44571d6e JDA |
9119 | { |
9120 | enum machine_mode valmode; | |
9121 | ||
4720d5ca JDA |
9122 | if (AGGREGATE_TYPE_P (valtype) |
9123 | || TREE_CODE (valtype) == COMPLEX_TYPE | |
9124 | || TREE_CODE (valtype) == VECTOR_TYPE) | |
44571d6e | 9125 | { |
2a04824b JDA |
9126 | if (TARGET_64BIT) |
9127 | { | |
9128 | /* Aggregates with a size less than or equal to 128 bits are | |
9129 | returned in GR 28(-29). They are left justified. The pad | |
9130 | bits are undefined. Larger aggregates are returned in | |
9131 | memory. */ | |
9132 | rtx loc[2]; | |
9133 | int i, offset = 0; | |
9134 | int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2; | |
9135 | ||
9136 | for (i = 0; i < ub; i++) | |
9137 | { | |
9138 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
9139 | gen_rtx_REG (DImode, 28 + i), | |
9140 | GEN_INT (offset)); | |
9141 | offset += 8; | |
9142 | } | |
44571d6e | 9143 | |
2a04824b JDA |
9144 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc)); |
9145 | } | |
9146 | else if (int_size_in_bytes (valtype) > UNITS_PER_WORD) | |
44571d6e | 9147 | { |
2a04824b JDA |
9148 | /* Aggregates 5 to 8 bytes in size are returned in general |
9149 | registers r28-r29 in the same manner as other non | |
9150 | floating-point objects. The data is right-justified and | |
9151 | zero-extended to 64 bits. This is opposite to the normal | |
9152 | justification used on big endian targets and requires | |
9153 | special treatment. */ | |
9154 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, | |
9155 | gen_rtx_REG (DImode, 28), const0_rtx); | |
9156 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc)); | |
44571d6e | 9157 | } |
44571d6e JDA |
9158 | } |
9159 | ||
9160 | if ((INTEGRAL_TYPE_P (valtype) | |
2ae88ecd | 9161 | && GET_MODE_BITSIZE (TYPE_MODE (valtype)) < BITS_PER_WORD) |
44571d6e JDA |
9162 | || POINTER_TYPE_P (valtype)) |
9163 | valmode = word_mode; | |
9164 | else | |
9165 | valmode = TYPE_MODE (valtype); | |
9166 | ||
9167 | if (TREE_CODE (valtype) == REAL_TYPE | |
2a04824b | 9168 | && !AGGREGATE_TYPE_P (valtype) |
44571d6e JDA |
9169 | && TYPE_MODE (valtype) != TFmode |
9170 | && !TARGET_SOFT_FLOAT) | |
9171 | return gen_rtx_REG (valmode, 32); | |
9172 | ||
9173 | return gen_rtx_REG (valmode, 28); | |
9174 | } | |
9175 | ||
520babc7 JL |
9176 | /* Return the location of a parameter that is passed in a register or NULL |
9177 | if the parameter has any component that is passed in memory. | |
9178 | ||
9179 | This is new code and will be pushed to into the net sources after | |
6619e96c | 9180 | further testing. |
520babc7 JL |
9181 | |
9182 | ??? We might want to restructure this so that it looks more like other | |
9183 | ports. */ | |
9184 | rtx | |
b7849684 JE |
9185 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, |
9186 | int named ATTRIBUTE_UNUSED) | |
520babc7 JL |
9187 | { |
9188 | int max_arg_words = (TARGET_64BIT ? 8 : 4); | |
015b1ad1 | 9189 | int alignment = 0; |
9dff28ab | 9190 | int arg_size; |
520babc7 JL |
9191 | int fpr_reg_base; |
9192 | int gpr_reg_base; | |
9193 | rtx retval; | |
9194 | ||
9dff28ab JDA |
9195 | if (mode == VOIDmode) |
9196 | return NULL_RTX; | |
9197 | ||
9198 | arg_size = FUNCTION_ARG_SIZE (mode, type); | |
9199 | ||
9200 | /* If this arg would be passed partially or totally on the stack, then | |
78a52f11 | 9201 | this routine should return zero. pa_arg_partial_bytes will |
9dff28ab JDA |
9202 | handle arguments which are split between regs and stack slots if |
9203 | the ABI mandates split arguments. */ | |
4720d5ca | 9204 | if (!TARGET_64BIT) |
520babc7 | 9205 | { |
9dff28ab JDA |
9206 | /* The 32-bit ABI does not split arguments. */ |
9207 | if (cum->words + arg_size > max_arg_words) | |
520babc7 JL |
9208 | return NULL_RTX; |
9209 | } | |
9210 | else | |
9211 | { | |
015b1ad1 JDA |
9212 | if (arg_size > 1) |
9213 | alignment = cum->words & 1; | |
9dff28ab | 9214 | if (cum->words + alignment >= max_arg_words) |
520babc7 JL |
9215 | return NULL_RTX; |
9216 | } | |
9217 | ||
9218 | /* The 32bit ABIs and the 64bit ABIs are rather different, | |
9219 | particularly in their handling of FP registers. We might | |
9220 | be able to cleverly share code between them, but I'm not | |
0952f89b | 9221 | going to bother in the hope that splitting them up results |
015b1ad1 | 9222 | in code that is more easily understood. */ |
520babc7 | 9223 | |
520babc7 JL |
9224 | if (TARGET_64BIT) |
9225 | { | |
9226 | /* Advance the base registers to their current locations. | |
9227 | ||
9228 | Remember, gprs grow towards smaller register numbers while | |
015b1ad1 JDA |
9229 | fprs grow to higher register numbers. Also remember that |
9230 | although FP regs are 32-bit addressable, we pretend that | |
9231 | the registers are 64-bits wide. */ | |
520babc7 JL |
9232 | gpr_reg_base = 26 - cum->words; |
9233 | fpr_reg_base = 32 + cum->words; | |
6619e96c | 9234 | |
9dff28ab JDA |
9235 | /* Arguments wider than one word and small aggregates need special |
9236 | treatment. */ | |
9237 | if (arg_size > 1 | |
9238 | || mode == BLKmode | |
4720d5ca JDA |
9239 | || (type && (AGGREGATE_TYPE_P (type) |
9240 | || TREE_CODE (type) == COMPLEX_TYPE | |
9241 | || TREE_CODE (type) == VECTOR_TYPE))) | |
520babc7 | 9242 | { |
015b1ad1 JDA |
9243 | /* Double-extended precision (80-bit), quad-precision (128-bit) |
9244 | and aggregates including complex numbers are aligned on | |
9245 | 128-bit boundaries. The first eight 64-bit argument slots | |
9246 | are associated one-to-one, with general registers r26 | |
9247 | through r19, and also with floating-point registers fr4 | |
9248 | through fr11. Arguments larger than one word are always | |
9dff28ab JDA |
9249 | passed in general registers. |
9250 | ||
9251 | Using a PARALLEL with a word mode register results in left | |
9252 | justified data on a big-endian target. */ | |
015b1ad1 JDA |
9253 | |
9254 | rtx loc[8]; | |
9255 | int i, offset = 0, ub = arg_size; | |
9256 | ||
9257 | /* Align the base register. */ | |
9258 | gpr_reg_base -= alignment; | |
9259 | ||
9260 | ub = MIN (ub, max_arg_words - cum->words - alignment); | |
9261 | for (i = 0; i < ub; i++) | |
520babc7 | 9262 | { |
015b1ad1 JDA |
9263 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, |
9264 | gen_rtx_REG (DImode, gpr_reg_base), | |
9265 | GEN_INT (offset)); | |
9266 | gpr_reg_base -= 1; | |
9267 | offset += 8; | |
520babc7 | 9268 | } |
015b1ad1 | 9269 | |
e4b95210 | 9270 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc)); |
520babc7 | 9271 | } |
9dff28ab | 9272 | } |
520babc7 JL |
9273 | else |
9274 | { | |
9275 | /* If the argument is larger than a word, then we know precisely | |
9276 | which registers we must use. */ | |
015b1ad1 | 9277 | if (arg_size > 1) |
520babc7 JL |
9278 | { |
9279 | if (cum->words) | |
9280 | { | |
9281 | gpr_reg_base = 23; | |
9282 | fpr_reg_base = 38; | |
9283 | } | |
9284 | else | |
9285 | { | |
9286 | gpr_reg_base = 25; | |
9287 | fpr_reg_base = 34; | |
9288 | } | |
9dff28ab JDA |
9289 | |
9290 | /* Structures 5 to 8 bytes in size are passed in the general | |
9291 | registers in the same manner as other non floating-point | |
9292 | objects. The data is right-justified and zero-extended | |
7ea18c08 JDA |
9293 | to 64 bits. This is opposite to the normal justification |
9294 | used on big endian targets and requires special treatment. | |
4720d5ca JDA |
9295 | We now define BLOCK_REG_PADDING to pad these objects. |
9296 | Aggregates, complex and vector types are passed in the same | |
9297 | manner as structures. */ | |
9298 | if (mode == BLKmode | |
9299 | || (type && (AGGREGATE_TYPE_P (type) | |
9300 | || TREE_CODE (type) == COMPLEX_TYPE | |
9301 | || TREE_CODE (type) == VECTOR_TYPE))) | |
9dff28ab | 9302 | { |
44571d6e JDA |
9303 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, |
9304 | gen_rtx_REG (DImode, gpr_reg_base), | |
9305 | const0_rtx); | |
2a04824b | 9306 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc)); |
9dff28ab | 9307 | } |
520babc7 JL |
9308 | } |
9309 | else | |
9310 | { | |
9311 | /* We have a single word (32 bits). A simple computation | |
9312 | will get us the register #s we need. */ | |
9313 | gpr_reg_base = 26 - cum->words; | |
9314 | fpr_reg_base = 32 + 2 * cum->words; | |
9315 | } | |
9316 | } | |
9317 | ||
b848dc65 | 9318 | /* Determine if the argument needs to be passed in both general and |
520babc7 | 9319 | floating point registers. */ |
b848dc65 JDA |
9320 | if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32) |
9321 | /* If we are doing soft-float with portable runtime, then there | |
9322 | is no need to worry about FP regs. */ | |
c328adfa | 9323 | && !TARGET_SOFT_FLOAT |
4720d5ca | 9324 | /* The parameter must be some kind of scalar float, else we just |
b848dc65 | 9325 | pass it in integer registers. */ |
4720d5ca | 9326 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
b848dc65 JDA |
9327 | /* The target function must not have a prototype. */ |
9328 | && cum->nargs_prototype <= 0 | |
9329 | /* libcalls do not need to pass items in both FP and general | |
9330 | registers. */ | |
9331 | && type != NULL_TREE | |
c328adfa JDA |
9332 | /* All this hair applies to "outgoing" args only. This includes |
9333 | sibcall arguments setup with FUNCTION_INCOMING_ARG. */ | |
9334 | && !cum->incoming) | |
b848dc65 JDA |
9335 | /* Also pass outgoing floating arguments in both registers in indirect |
9336 | calls with the 32 bit ABI and the HP assembler since there is no | |
9337 | way to the specify argument locations in static functions. */ | |
c328adfa JDA |
9338 | || (!TARGET_64BIT |
9339 | && !TARGET_GAS | |
9340 | && !cum->incoming | |
b848dc65 | 9341 | && cum->indirect |
4720d5ca | 9342 | && GET_MODE_CLASS (mode) == MODE_FLOAT)) |
520babc7 JL |
9343 | { |
9344 | retval | |
9345 | = gen_rtx_PARALLEL | |
9346 | (mode, | |
9347 | gen_rtvec (2, | |
9348 | gen_rtx_EXPR_LIST (VOIDmode, | |
9349 | gen_rtx_REG (mode, fpr_reg_base), | |
9350 | const0_rtx), | |
9351 | gen_rtx_EXPR_LIST (VOIDmode, | |
9352 | gen_rtx_REG (mode, gpr_reg_base), | |
9353 | const0_rtx))); | |
9354 | } | |
9355 | else | |
9356 | { | |
9357 | /* See if we should pass this parameter in a general register. */ | |
9358 | if (TARGET_SOFT_FLOAT | |
9359 | /* Indirect calls in the normal 32bit ABI require all arguments | |
9360 | to be passed in general registers. */ | |
9361 | || (!TARGET_PORTABLE_RUNTIME | |
9362 | && !TARGET_64BIT | |
50b424a9 | 9363 | && !TARGET_ELF32 |
520babc7 | 9364 | && cum->indirect) |
4720d5ca JDA |
9365 | /* If the parameter is not a scalar floating-point parameter, |
9366 | then it belongs in GPRs. */ | |
9367 | || GET_MODE_CLASS (mode) != MODE_FLOAT | |
2a04824b JDA |
9368 | /* Structure with single SFmode field belongs in GPR. */ |
9369 | || (type && AGGREGATE_TYPE_P (type))) | |
520babc7 JL |
9370 | retval = gen_rtx_REG (mode, gpr_reg_base); |
9371 | else | |
9372 | retval = gen_rtx_REG (mode, fpr_reg_base); | |
9373 | } | |
9374 | return retval; | |
9375 | } | |
9376 | ||
9377 | ||
9378 | /* If this arg would be passed totally in registers or totally on the stack, | |
78a52f11 RH |
9379 | then this routine should return zero. */ |
9380 | ||
9381 | static int | |
9382 | pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
9383 | tree type, bool named ATTRIBUTE_UNUSED) | |
520babc7 | 9384 | { |
e0c556d3 AM |
9385 | unsigned int max_arg_words = 8; |
9386 | unsigned int offset = 0; | |
520babc7 | 9387 | |
78a52f11 RH |
9388 | if (!TARGET_64BIT) |
9389 | return 0; | |
9390 | ||
e0c556d3 | 9391 | if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1)) |
520babc7 JL |
9392 | offset = 1; |
9393 | ||
e0c556d3 | 9394 | if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words) |
fe19a83d | 9395 | /* Arg fits fully into registers. */ |
520babc7 | 9396 | return 0; |
6619e96c | 9397 | else if (cum->words + offset >= max_arg_words) |
fe19a83d | 9398 | /* Arg fully on the stack. */ |
520babc7 JL |
9399 | return 0; |
9400 | else | |
fe19a83d | 9401 | /* Arg is split. */ |
78a52f11 | 9402 | return (max_arg_words - cum->words - offset) * UNITS_PER_WORD; |
520babc7 JL |
9403 | } |
9404 | ||
9405 | ||
d6b5193b | 9406 | /* A get_unnamed_section callback for switching to the text section. |
9a55eab3 JDA |
9407 | |
9408 | This function is only used with SOM. Because we don't support | |
9409 | named subspaces, we can only create a new subspace or switch back | |
774acadf | 9410 | to the default text subspace. */ |
774acadf | 9411 | |
d6b5193b RS |
9412 | static void |
9413 | som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
9414 | { | |
9415 | gcc_assert (TARGET_SOM); | |
774acadf | 9416 | if (TARGET_GAS) |
9a55eab3 | 9417 | { |
8c5e065b | 9418 | if (cfun && cfun->machine && !cfun->machine->in_nsubspa) |
9a55eab3 JDA |
9419 | { |
9420 | /* We only want to emit a .nsubspa directive once at the | |
9421 | start of the function. */ | |
9422 | cfun->machine->in_nsubspa = 1; | |
9423 | ||
9424 | /* Create a new subspace for the text. This provides | |
9425 | better stub placement and one-only functions. */ | |
9426 | if (cfun->decl | |
9427 | && DECL_ONE_ONLY (cfun->decl) | |
9428 | && !DECL_WEAK (cfun->decl)) | |
1a83bfc3 JDA |
9429 | { |
9430 | output_section_asm_op ("\t.SPACE $TEXT$\n" | |
9431 | "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8," | |
9432 | "ACCESS=44,SORT=24,COMDAT"); | |
9433 | return; | |
9434 | } | |
9a55eab3 JDA |
9435 | } |
9436 | else | |
9437 | { | |
9438 | /* There isn't a current function or the body of the current | |
9439 | function has been completed. So, we are changing to the | |
1a83bfc3 JDA |
9440 | text section to output debugging information. Thus, we |
9441 | need to forget that we are in the text section so that | |
9442 | varasm.c will call us when text_section is selected again. */ | |
8c5e065b JDA |
9443 | gcc_assert (!cfun || !cfun->machine |
9444 | || cfun->machine->in_nsubspa == 2); | |
d6b5193b | 9445 | in_section = NULL; |
9a55eab3 | 9446 | } |
1a83bfc3 JDA |
9447 | output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$"); |
9448 | return; | |
9a55eab3 | 9449 | } |
d6b5193b RS |
9450 | output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$"); |
9451 | } | |
9452 | ||
1a83bfc3 JDA |
9453 | /* A get_unnamed_section callback for switching to comdat data |
9454 | sections. This function is only used with SOM. */ | |
9455 | ||
9456 | static void | |
9457 | som_output_comdat_data_section_asm_op (const void *data) | |
9458 | { | |
9459 | in_section = NULL; | |
9460 | output_section_asm_op (data); | |
9461 | } | |
9462 | ||
d6b5193b | 9463 | /* Implement TARGET_ASM_INITIALIZE_SECTIONS */ |
9a55eab3 | 9464 | |
d6b5193b RS |
9465 | static void |
9466 | pa_som_asm_init_sections (void) | |
9467 | { | |
9468 | text_section | |
9469 | = get_unnamed_section (0, som_output_text_section_asm_op, NULL); | |
9470 | ||
9471 | /* SOM puts readonly data in the default $LIT$ subspace when PIC code | |
9472 | is not being generated. */ | |
9473 | som_readonly_data_section | |
9474 | = get_unnamed_section (0, output_section_asm_op, | |
9475 | "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$"); | |
9476 | ||
9477 | /* When secondary definitions are not supported, SOM makes readonly | |
9478 | data one-only by creating a new $LIT$ subspace in $TEXT$ with | |
9479 | the comdat flag. */ | |
9480 | som_one_only_readonly_data_section | |
1a83bfc3 | 9481 | = get_unnamed_section (0, som_output_comdat_data_section_asm_op, |
d6b5193b RS |
9482 | "\t.SPACE $TEXT$\n" |
9483 | "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8," | |
9484 | "ACCESS=0x2c,SORT=16,COMDAT"); | |
9485 | ||
9486 | ||
9487 | /* When secondary definitions are not supported, SOM makes data one-only | |
9488 | by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */ | |
9489 | som_one_only_data_section | |
1a83bfc3 JDA |
9490 | = get_unnamed_section (SECTION_WRITE, |
9491 | som_output_comdat_data_section_asm_op, | |
d6b5193b RS |
9492 | "\t.SPACE $PRIVATE$\n" |
9493 | "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8," | |
9494 | "ACCESS=31,SORT=24,COMDAT"); | |
9495 | ||
9496 | /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups | |
9497 | which reference data within the $TEXT$ space (for example constant | |
9498 | strings in the $LIT$ subspace). | |
9499 | ||
9500 | The assemblers (GAS and HP as) both have problems with handling | |
9501 | the difference of two symbols which is the other correct way to | |
9502 | reference constant data during PIC code generation. | |
9503 | ||
9504 | So, there's no way to reference constant data which is in the | |
9505 | $TEXT$ space during PIC generation. Instead place all constant | |
9506 | data into the $PRIVATE$ subspace (this reduces sharing, but it | |
9507 | works correctly). */ | |
9508 | readonly_data_section = flag_pic ? data_section : som_readonly_data_section; | |
9509 | ||
9510 | /* We must not have a reference to an external symbol defined in a | |
9511 | shared library in a readonly section, else the SOM linker will | |
9512 | complain. | |
9513 | ||
9514 | So, we force exception information into the data section. */ | |
9515 | exception_section = data_section; | |
9a55eab3 JDA |
9516 | } |
9517 | ||
ae46c4e0 RH |
9518 | /* On hpux10, the linker will give an error if we have a reference |
9519 | in the read-only data section to a symbol defined in a shared | |
9520 | library. Therefore, expressions that might require a reloc can | |
9521 | not be placed in the read-only data section. */ | |
9522 | ||
d6b5193b | 9523 | static section * |
24a52160 JDA |
9524 | pa_select_section (tree exp, int reloc, |
9525 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
ae46c4e0 RH |
9526 | { |
9527 | if (TREE_CODE (exp) == VAR_DECL | |
9528 | && TREE_READONLY (exp) | |
9529 | && !TREE_THIS_VOLATILE (exp) | |
9530 | && DECL_INITIAL (exp) | |
9531 | && (DECL_INITIAL (exp) == error_mark_node | |
9532 | || TREE_CONSTANT (DECL_INITIAL (exp))) | |
9533 | && !reloc) | |
9a55eab3 JDA |
9534 | { |
9535 | if (TARGET_SOM | |
9536 | && DECL_ONE_ONLY (exp) | |
9537 | && !DECL_WEAK (exp)) | |
d6b5193b | 9538 | return som_one_only_readonly_data_section; |
9a55eab3 | 9539 | else |
d6b5193b | 9540 | return readonly_data_section; |
9a55eab3 | 9541 | } |
6615c446 | 9542 | else if (CONSTANT_CLASS_P (exp) && !reloc) |
d6b5193b | 9543 | return readonly_data_section; |
9a55eab3 JDA |
9544 | else if (TARGET_SOM |
9545 | && TREE_CODE (exp) == VAR_DECL | |
9546 | && DECL_ONE_ONLY (exp) | |
e41f3691 | 9547 | && !DECL_WEAK (exp)) |
d6b5193b | 9548 | return som_one_only_data_section; |
ae46c4e0 | 9549 | else |
d6b5193b | 9550 | return data_section; |
ae46c4e0 | 9551 | } |
e2500fed | 9552 | |
5eb99654 | 9553 | static void |
b7849684 | 9554 | pa_globalize_label (FILE *stream, const char *name) |
5eb99654 KG |
9555 | { |
9556 | /* We only handle DATA objects here, functions are globalized in | |
9557 | ASM_DECLARE_FUNCTION_NAME. */ | |
9558 | if (! FUNCTION_NAME_P (name)) | |
9559 | { | |
9560 | fputs ("\t.EXPORT ", stream); | |
9561 | assemble_name (stream, name); | |
9562 | fputs (",DATA\n", stream); | |
9563 | } | |
9564 | } | |
3f12cd9b | 9565 | |
bd5bd7ac KH |
9566 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
9567 | ||
3f12cd9b KH |
9568 | static rtx |
9569 | pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
9570 | int incoming ATTRIBUTE_UNUSED) | |
9571 | { | |
9572 | return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM); | |
9573 | } | |
9574 | ||
bd5bd7ac KH |
9575 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
9576 | ||
3f12cd9b | 9577 | bool |
586de218 | 9578 | pa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
3f12cd9b KH |
9579 | { |
9580 | /* SOM ABI says that objects larger than 64 bits are returned in memory. | |
9581 | PA64 ABI says that objects larger than 128 bits are returned in memory. | |
9582 | Note, int_size_in_bytes can return -1 if the size of the object is | |
9583 | variable or larger than the maximum value that can be expressed as | |
9584 | a HOST_WIDE_INT. It can also return zero for an empty type. The | |
9585 | simplest way to handle variable and empty types is to pass them in | |
9586 | memory. This avoids problems in defining the boundaries of argument | |
9587 | slots, allocating registers, etc. */ | |
9588 | return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8) | |
9589 | || int_size_in_bytes (type) <= 0); | |
9590 | } | |
9591 | ||
744b2d61 JDA |
9592 | /* Structure to hold declaration and name of external symbols that are |
9593 | emitted by GCC. We generate a vector of these symbols and output them | |
9594 | at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true. | |
9595 | This avoids putting out names that are never really used. */ | |
9596 | ||
d1b38208 | 9597 | typedef struct GTY(()) extern_symbol |
744b2d61 JDA |
9598 | { |
9599 | tree decl; | |
9600 | const char *name; | |
d4e6fecb | 9601 | } extern_symbol; |
744b2d61 JDA |
9602 | |
9603 | /* Define gc'd vector type for extern_symbol. */ | |
d4e6fecb NS |
9604 | DEF_VEC_O(extern_symbol); |
9605 | DEF_VEC_ALLOC_O(extern_symbol,gc); | |
744b2d61 JDA |
9606 | |
9607 | /* Vector of extern_symbol pointers. */ | |
d4e6fecb | 9608 | static GTY(()) VEC(extern_symbol,gc) *extern_symbols; |
744b2d61 JDA |
9609 | |
9610 | #ifdef ASM_OUTPUT_EXTERNAL_REAL | |
9611 | /* Mark DECL (name NAME) as an external reference (assembler output | |
9612 | file FILE). This saves the names to output at the end of the file | |
9613 | if actually referenced. */ | |
9614 | ||
9615 | void | |
9616 | pa_hpux_asm_output_external (FILE *file, tree decl, const char *name) | |
9617 | { | |
d4e6fecb | 9618 | extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL); |
744b2d61 JDA |
9619 | |
9620 | gcc_assert (file == asm_out_file); | |
9621 | p->decl = decl; | |
9622 | p->name = name; | |
744b2d61 JDA |
9623 | } |
9624 | ||
9625 | /* Output text required at the end of an assembler file. | |
9626 | This includes deferred plabels and .import directives for | |
9627 | all external symbols that were actually referenced. */ | |
9628 | ||
9629 | static void | |
9630 | pa_hpux_file_end (void) | |
9631 | { | |
9632 | unsigned int i; | |
d4e6fecb | 9633 | extern_symbol *p; |
744b2d61 | 9634 | |
3674b34d JDA |
9635 | if (!NO_DEFERRED_PROFILE_COUNTERS) |
9636 | output_deferred_profile_counters (); | |
9637 | ||
744b2d61 JDA |
9638 | output_deferred_plabels (); |
9639 | ||
9640 | for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++) | |
9641 | { | |
9642 | tree decl = p->decl; | |
9643 | ||
9644 | if (!TREE_ASM_WRITTEN (decl) | |
9645 | && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0))) | |
9646 | ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name); | |
9647 | } | |
9648 | ||
d4e6fecb | 9649 | VEC_free (extern_symbol, gc, extern_symbols); |
744b2d61 JDA |
9650 | } |
9651 | #endif | |
9652 | ||
6982c5d4 | 9653 | /* Return true if a change from mode FROM to mode TO for a register |
0a2aaacc | 9654 | in register class RCLASS is invalid. */ |
6982c5d4 JDA |
9655 | |
9656 | bool | |
9657 | pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to, | |
0a2aaacc | 9658 | enum reg_class rclass) |
6982c5d4 JDA |
9659 | { |
9660 | if (from == to) | |
9661 | return false; | |
9662 | ||
9663 | /* Reject changes to/from complex and vector modes. */ | |
9664 | if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from) | |
9665 | || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to)) | |
9666 | return true; | |
9667 | ||
9668 | if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to)) | |
9669 | return false; | |
9670 | ||
9671 | /* There is no way to load QImode or HImode values directly from | |
9672 | memory. SImode loads to the FP registers are not zero extended. | |
9673 | On the 64-bit target, this conflicts with the definition of | |
9674 | LOAD_EXTEND_OP. Thus, we can't allow changing between modes | |
9675 | with different sizes in the floating-point registers. */ | |
0a2aaacc | 9676 | if (MAYBE_FP_REG_CLASS_P (rclass)) |
6982c5d4 JDA |
9677 | return true; |
9678 | ||
9679 | /* HARD_REGNO_MODE_OK places modes with sizes larger than a word | |
9680 | in specific sets of registers. Thus, we cannot allow changing | |
9681 | to a larger mode when it's larger than a word. */ | |
9682 | if (GET_MODE_SIZE (to) > UNITS_PER_WORD | |
9683 | && GET_MODE_SIZE (to) > GET_MODE_SIZE (from)) | |
9684 | return true; | |
9685 | ||
9686 | return false; | |
9687 | } | |
9688 | ||
9689 | /* Returns TRUE if it is a good idea to tie two pseudo registers | |
9690 | when one has mode MODE1 and one has mode MODE2. | |
9691 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
9692 | for any hard reg, then this must be FALSE for correct output. | |
9693 | ||
9694 | We should return FALSE for QImode and HImode because these modes | |
9695 | are not ok in the floating-point registers. However, this prevents | |
9696 | tieing these modes to SImode and DImode in the general registers. | |
9697 | So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and | |
9698 | CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used | |
9699 | in the floating-point registers. */ | |
9700 | ||
9701 | bool | |
9702 | pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) | |
9703 | { | |
9704 | /* Don't tie modes in different classes. */ | |
9705 | if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2)) | |
9706 | return false; | |
9707 | ||
9708 | return true; | |
9709 | } | |
9710 | ||
e2500fed | 9711 | #include "gt-pa.h" |