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87ad11b0 | 1 | /* Subroutines for insn-output.c for HPPA. |
a9ac13e4 | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
fba5dd52 | 3 | 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
cfaf579d | 4 | Free Software Foundation, Inc. |
87ad11b0 | 5 | Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c |
6 | ||
5c1d8983 | 7 | This file is part of GCC. |
87ad11b0 | 8 | |
5c1d8983 | 9 | GCC is free software; you can redistribute it and/or modify |
87ad11b0 | 10 | it under the terms of the GNU General Public License as published by |
038d1e19 | 11 | the Free Software Foundation; either version 3, or (at your option) |
87ad11b0 | 12 | any later version. |
13 | ||
5c1d8983 | 14 | GCC is distributed in the hope that it will be useful, |
87ad11b0 | 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
038d1e19 | 20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
87ad11b0 | 22 | |
87ad11b0 | 23 | #include "config.h" |
b1ca791d | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
87ad11b0 | 27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
87ad11b0 | 30 | #include "insn-config.h" |
31 | #include "conditions.h" | |
87ad11b0 | 32 | #include "insn-attr.h" |
33 | #include "flags.h" | |
34 | #include "tree.h" | |
9d2d8bd6 | 35 | #include "output.h" |
b5369b7d | 36 | #include "dbxout.h" |
a584fe8a | 37 | #include "except.h" |
32509e56 | 38 | #include "expr.h" |
d8fc4d0b | 39 | #include "optabs.h" |
d8fc4d0b | 40 | #include "reload.h" |
0a893c29 | 41 | #include "function.h" |
0b205f4c | 42 | #include "diagnostic-core.h" |
5cb4669a | 43 | #include "ggc.h" |
611a88e1 | 44 | #include "recog.h" |
a584fe8a | 45 | #include "predict.h" |
611a88e1 | 46 | #include "tm_p.h" |
a767736d | 47 | #include "target.h" |
218e3e4e | 48 | #include "common/common-target.h" |
a767736d | 49 | #include "target-def.h" |
0f9c87cc | 50 | #include "langhooks.h" |
a179d6b2 | 51 | #include "df.h" |
fba5dd52 | 52 | #include "opts.h" |
87ad11b0 | 53 | |
cde3e16c | 54 | /* Return nonzero if there is a bypass for the output of |
55 | OUT_INSN and the fp store IN_INSN. */ | |
56 | int | |
e202682d | 57 | pa_fpstore_bypass_p (rtx out_insn, rtx in_insn) |
cde3e16c | 58 | { |
59 | enum machine_mode store_mode; | |
60 | enum machine_mode other_mode; | |
61 | rtx set; | |
62 | ||
63 | if (recog_memoized (in_insn) < 0 | |
7d9f62cc | 64 | || (get_attr_type (in_insn) != TYPE_FPSTORE |
65 | && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD) | |
cde3e16c | 66 | || recog_memoized (out_insn) < 0) |
67 | return 0; | |
68 | ||
69 | store_mode = GET_MODE (SET_SRC (PATTERN (in_insn))); | |
70 | ||
71 | set = single_set (out_insn); | |
72 | if (!set) | |
73 | return 0; | |
74 | ||
75 | other_mode = GET_MODE (SET_SRC (set)); | |
76 | ||
77 | return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode)); | |
78 | } | |
79 | ||
80 | ||
cc858176 | 81 | #ifndef DO_FRAME_NOTES |
82 | #ifdef INCOMING_RETURN_ADDR_RTX | |
83 | #define DO_FRAME_NOTES 1 | |
84 | #else | |
85 | #define DO_FRAME_NOTES 0 | |
86 | #endif | |
87 | #endif | |
88 | ||
93d3ee56 | 89 | static void pa_option_override (void); |
dbd3d89d | 90 | static void copy_reg_pointer (rtx, rtx); |
320e1276 | 91 | static void fix_range (const char *); |
93d3ee56 | 92 | static int hppa_register_move_cost (enum machine_mode mode, reg_class_t, |
93 | reg_class_t); | |
d9c5e5f4 | 94 | static int hppa_address_cost (rtx, enum machine_mode mode, addr_space_t, bool); |
20d892d1 | 95 | static bool hppa_rtx_costs (rtx, int, int, int, int *, bool); |
5c1d8983 | 96 | static inline rtx force_mode (enum machine_mode, rtx); |
97 | static void pa_reorg (void); | |
98 | static void pa_combine_instructions (void); | |
99 | static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx); | |
372b3fe2 | 100 | static bool forward_branch_p (rtx); |
5c1d8983 | 101 | static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *); |
e202682d | 102 | static void compute_zdepdi_operands (unsigned HOST_WIDE_INT, unsigned *); |
008c057d | 103 | static int compute_movmem_length (rtx); |
104 | static int compute_clrmem_length (rtx); | |
5c1d8983 | 105 | static bool pa_assemble_integer (rtx, unsigned int, int); |
106 | static void remove_useless_addtr_insns (int); | |
6bcdc1fb | 107 | static void store_reg (int, HOST_WIDE_INT, int); |
108 | static void store_reg_modify (int, int, HOST_WIDE_INT); | |
109 | static void load_reg (int, HOST_WIDE_INT, int); | |
110 | static void set_reg_plus_d (int, int, HOST_WIDE_INT, int); | |
cb0b8817 | 111 | static rtx pa_function_value (const_tree, const_tree, bool); |
93d3ee56 | 112 | static rtx pa_libcall_value (enum machine_mode, const_rtx); |
113 | static bool pa_function_value_regno_p (const unsigned int); | |
5c1d8983 | 114 | static void pa_output_function_prologue (FILE *, HOST_WIDE_INT); |
21a47bc9 | 115 | static void update_total_code_bytes (unsigned int); |
5c1d8983 | 116 | static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT); |
117 | static int pa_adjust_cost (rtx, rtx, rtx, int); | |
118 | static int pa_adjust_priority (rtx, int); | |
119 | static int pa_issue_rate (void); | |
2f14b1f9 | 120 | static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED; |
8151bf30 | 121 | static section *pa_som_tm_clone_table_section (void) ATTRIBUTE_UNUSED; |
2f14b1f9 | 122 | static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT) |
52470889 | 123 | ATTRIBUTE_UNUSED; |
5c1d8983 | 124 | static void pa_encode_section_info (tree, rtx, int); |
125 | static const char *pa_strip_name_encoding (const char *); | |
126 | static bool pa_function_ok_for_sibcall (tree, tree); | |
127 | static void pa_globalize_label (FILE *, const char *) | |
63b8cd48 | 128 | ATTRIBUTE_UNUSED; |
5c1d8983 | 129 | static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
130 | HOST_WIDE_INT, tree); | |
de419443 | 131 | #if !defined(USE_COLLECT2) |
5c1d8983 | 132 | static void pa_asm_out_constructor (rtx, int); |
133 | static void pa_asm_out_destructor (rtx, int); | |
de419443 | 134 | #endif |
5c1d8983 | 135 | static void pa_init_builtins (void); |
0f9c87cc | 136 | static rtx pa_expand_builtin (tree, rtx, rtx, enum machine_mode mode, int); |
b8debbe8 | 137 | static rtx hppa_builtin_saveregs (void); |
8a58ed0a | 138 | static void hppa_va_start (tree, rtx); |
75a70cf9 | 139 | static tree hppa_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); |
2b1e7cc3 | 140 | static bool pa_scalar_mode_supported_p (enum machine_mode); |
a9f1838b | 141 | static bool pa_commutative_p (const_rtx x, int outer_code); |
5c1d8983 | 142 | static void copy_fp_args (rtx) ATTRIBUTE_UNUSED; |
143 | static int length_fp_args (rtx) ATTRIBUTE_UNUSED; | |
41e3a0c7 | 144 | static rtx hppa_legitimize_address (rtx, rtx, enum machine_mode); |
5c1d8983 | 145 | static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED; |
146 | static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED; | |
147 | static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED; | |
148 | static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED; | |
149 | static void pa_elf_file_start (void) ATTRIBUTE_UNUSED; | |
150 | static void pa_som_file_start (void) ATTRIBUTE_UNUSED; | |
151 | static void pa_linux_file_start (void) ATTRIBUTE_UNUSED; | |
152 | static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED; | |
153 | static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED; | |
154 | static void output_deferred_plabels (void); | |
bb1bc2ca | 155 | static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED; |
5f43b4f6 | 156 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
157 | static void pa_hpux_file_end (void); | |
158 | #endif | |
3912b4d0 | 159 | static void pa_init_libfuncs (void); |
b8debbe8 | 160 | static rtx pa_struct_value_rtx (tree, int); |
39cba157 | 161 | static bool pa_pass_by_reference (cumulative_args_t, enum machine_mode, |
fb80456a | 162 | const_tree, bool); |
39cba157 | 163 | static int pa_arg_partial_bytes (cumulative_args_t, enum machine_mode, |
f054eb3c | 164 | tree, bool); |
39cba157 | 165 | static void pa_function_arg_advance (cumulative_args_t, enum machine_mode, |
8b4bd662 | 166 | const_tree, bool); |
39cba157 | 167 | static rtx pa_function_arg (cumulative_args_t, enum machine_mode, |
8b4bd662 | 168 | const_tree, bool); |
bd99ba64 | 169 | static unsigned int pa_function_arg_boundary (enum machine_mode, const_tree); |
916c9cef | 170 | static struct machine_function * pa_init_machine_status (void); |
964229b7 | 171 | static reg_class_t pa_secondary_reload (bool, rtx, reg_class_t, |
172 | enum machine_mode, | |
173 | secondary_reload_info *); | |
df6b92e4 | 174 | static void pa_extra_live_on_entry (bitmap); |
15a27966 | 175 | static enum machine_mode pa_promote_function_mode (const_tree, |
176 | enum machine_mode, int *, | |
177 | const_tree, int); | |
9d3ddb8f | 178 | |
623a97bc | 179 | static void pa_asm_trampoline_template (FILE *); |
180 | static void pa_trampoline_init (rtx, tree, rtx); | |
181 | static rtx pa_trampoline_adjust_address (rtx); | |
c731c4f5 | 182 | static rtx pa_delegitimize_address (rtx); |
93d3ee56 | 183 | static bool pa_print_operand_punct_valid_p (unsigned char); |
68bc9ae6 | 184 | static rtx pa_internal_arg_pointer (void); |
185 | static bool pa_can_eliminate (const int, const int); | |
b2d7ede1 | 186 | static void pa_conditional_register_usage (void); |
0f9c87cc | 187 | static enum machine_mode pa_c_mode_for_suffix (char); |
c9b4a514 | 188 | static section *pa_function_section (tree, enum node_frequency, bool, bool); |
7d7d7bd2 | 189 | static bool pa_cannot_force_const_mem (enum machine_mode, rtx); |
ca316360 | 190 | static bool pa_legitimate_constant_p (enum machine_mode, rtx); |
7949e3eb | 191 | static unsigned int pa_section_type_flags (tree, const char *, int); |
623a97bc | 192 | |
2f14b1f9 | 193 | /* The following extra sections are only used for SOM. */ |
194 | static GTY(()) section *som_readonly_data_section; | |
195 | static GTY(()) section *som_one_only_readonly_data_section; | |
196 | static GTY(()) section *som_one_only_data_section; | |
8151bf30 | 197 | static GTY(()) section *som_tm_clone_table_section; |
2f14b1f9 | 198 | |
a9960cdc | 199 | /* Counts for the number of callee-saved general and floating point |
200 | registers which were saved by the current function's prologue. */ | |
201 | static int gr_saved, fr_saved; | |
202 | ||
df6b92e4 | 203 | /* Boolean indicating whether the return pointer was saved by the |
204 | current function's prologue. */ | |
205 | static bool rp_saved; | |
206 | ||
5c1d8983 | 207 | static rtx find_addr_reg (rtx); |
87ad11b0 | 208 | |
2247cc5f | 209 | /* Keep track of the number of bytes we have output in the CODE subspace |
06ddb6f8 | 210 | during this compilation so we'll know when to emit inline long-calls. */ |
ece88821 | 211 | unsigned long total_code_bytes; |
06ddb6f8 | 212 | |
2247cc5f | 213 | /* The last address of the previous function plus the number of bytes in |
214 | associated thunks that have been output. This is used to determine if | |
215 | a thunk can use an IA-relative branch to reach its target function. */ | |
21a47bc9 | 216 | static unsigned int last_address; |
2247cc5f | 217 | |
e3f53689 | 218 | /* Variables to handle plabels that we discover are necessary at assembly |
01cc3b75 | 219 | output time. They are output after the current function. */ |
fb1e4f4a | 220 | struct GTY(()) deferred_plabel |
e3f53689 | 221 | { |
222 | rtx internal_label; | |
5f43b4f6 | 223 | rtx symbol; |
1f3233d1 | 224 | }; |
225 | static GTY((length ("n_deferred_plabels"))) struct deferred_plabel * | |
226 | deferred_plabels; | |
e11bd7e5 | 227 | static size_t n_deferred_plabels = 0; |
a767736d | 228 | \f |
229 | /* Initialize the GCC target structure. */ | |
58356836 | 230 | |
93d3ee56 | 231 | #undef TARGET_OPTION_OVERRIDE |
232 | #define TARGET_OPTION_OVERRIDE pa_option_override | |
233 | ||
58356836 | 234 | #undef TARGET_ASM_ALIGNED_HI_OP |
235 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
236 | #undef TARGET_ASM_ALIGNED_SI_OP | |
237 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
238 | #undef TARGET_ASM_ALIGNED_DI_OP | |
239 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
240 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
241 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
242 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
243 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
244 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
245 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
246 | #undef TARGET_ASM_INTEGER | |
247 | #define TARGET_ASM_INTEGER pa_assemble_integer | |
248 | ||
17d9b0c3 | 249 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
250 | #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue | |
251 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
252 | #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue | |
e3f53689 | 253 | |
cb0b8817 | 254 | #undef TARGET_FUNCTION_VALUE |
255 | #define TARGET_FUNCTION_VALUE pa_function_value | |
93d3ee56 | 256 | #undef TARGET_LIBCALL_VALUE |
257 | #define TARGET_LIBCALL_VALUE pa_libcall_value | |
258 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
259 | #define TARGET_FUNCTION_VALUE_REGNO_P pa_function_value_regno_p | |
cb0b8817 | 260 | |
41e3a0c7 | 261 | #undef TARGET_LEGITIMIZE_ADDRESS |
262 | #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address | |
263 | ||
747af5e7 | 264 | #undef TARGET_SCHED_ADJUST_COST |
265 | #define TARGET_SCHED_ADJUST_COST pa_adjust_cost | |
266 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
267 | #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority | |
268 | #undef TARGET_SCHED_ISSUE_RATE | |
269 | #define TARGET_SCHED_ISSUE_RATE pa_issue_rate | |
270 | ||
7811991d | 271 | #undef TARGET_ENCODE_SECTION_INFO |
272 | #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info | |
7b4a38a6 | 273 | #undef TARGET_STRIP_NAME_ENCODING |
274 | #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding | |
7811991d | 275 | |
805e22b2 | 276 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
277 | #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall | |
278 | ||
280566a7 | 279 | #undef TARGET_COMMUTATIVE_P |
280 | #define TARGET_COMMUTATIVE_P pa_commutative_p | |
281 | ||
6988553d | 282 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
283 | #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk | |
eb344f43 | 284 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
285 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
6988553d | 286 | |
f6940372 | 287 | #undef TARGET_ASM_FILE_END |
5f43b4f6 | 288 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
289 | #define TARGET_ASM_FILE_END pa_hpux_file_end | |
290 | #else | |
f6940372 | 291 | #define TARGET_ASM_FILE_END output_deferred_plabels |
5f43b4f6 | 292 | #endif |
f6940372 | 293 | |
93d3ee56 | 294 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P |
295 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pa_print_operand_punct_valid_p | |
296 | ||
de419443 | 297 | #if !defined(USE_COLLECT2) |
298 | #undef TARGET_ASM_CONSTRUCTOR | |
299 | #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor | |
300 | #undef TARGET_ASM_DESTRUCTOR | |
301 | #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor | |
302 | #endif | |
303 | ||
ffa8918b | 304 | #undef TARGET_INIT_BUILTINS |
305 | #define TARGET_INIT_BUILTINS pa_init_builtins | |
306 | ||
0f9c87cc | 307 | #undef TARGET_EXPAND_BUILTIN |
308 | #define TARGET_EXPAND_BUILTIN pa_expand_builtin | |
309 | ||
93d3ee56 | 310 | #undef TARGET_REGISTER_MOVE_COST |
311 | #define TARGET_REGISTER_MOVE_COST hppa_register_move_cost | |
fab7adbf | 312 | #undef TARGET_RTX_COSTS |
313 | #define TARGET_RTX_COSTS hppa_rtx_costs | |
ec0457a8 | 314 | #undef TARGET_ADDRESS_COST |
315 | #define TARGET_ADDRESS_COST hppa_address_cost | |
fab7adbf | 316 | |
2efea8c0 | 317 | #undef TARGET_MACHINE_DEPENDENT_REORG |
318 | #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg | |
319 | ||
f2f543a3 | 320 | #undef TARGET_INIT_LIBFUNCS |
3912b4d0 | 321 | #define TARGET_INIT_LIBFUNCS pa_init_libfuncs |
f2f543a3 | 322 | |
3b2411a8 | 323 | #undef TARGET_PROMOTE_FUNCTION_MODE |
324 | #define TARGET_PROMOTE_FUNCTION_MODE pa_promote_function_mode | |
b8debbe8 | 325 | #undef TARGET_PROMOTE_PROTOTYPES |
fb80456a | 326 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
b8debbe8 | 327 | |
328 | #undef TARGET_STRUCT_VALUE_RTX | |
329 | #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx | |
330 | #undef TARGET_RETURN_IN_MEMORY | |
331 | #define TARGET_RETURN_IN_MEMORY pa_return_in_memory | |
0336f0f0 | 332 | #undef TARGET_MUST_PASS_IN_STACK |
333 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
b981d932 | 334 | #undef TARGET_PASS_BY_REFERENCE |
335 | #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference | |
13f08ee7 | 336 | #undef TARGET_CALLEE_COPIES |
337 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
f054eb3c | 338 | #undef TARGET_ARG_PARTIAL_BYTES |
339 | #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes | |
8b4bd662 | 340 | #undef TARGET_FUNCTION_ARG |
341 | #define TARGET_FUNCTION_ARG pa_function_arg | |
342 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
343 | #define TARGET_FUNCTION_ARG_ADVANCE pa_function_arg_advance | |
bd99ba64 | 344 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
345 | #define TARGET_FUNCTION_ARG_BOUNDARY pa_function_arg_boundary | |
b8debbe8 | 346 | |
347 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
348 | #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs | |
8a58ed0a | 349 | #undef TARGET_EXPAND_BUILTIN_VA_START |
350 | #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start | |
4c33eb68 | 351 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
352 | #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr | |
b8debbe8 | 353 | |
2b1e7cc3 | 354 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
355 | #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p | |
356 | ||
716b2c5a | 357 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
7d7d7bd2 | 358 | #define TARGET_CANNOT_FORCE_CONST_MEM pa_cannot_force_const_mem |
716b2c5a | 359 | |
5655a0e5 | 360 | #undef TARGET_SECONDARY_RELOAD |
361 | #define TARGET_SECONDARY_RELOAD pa_secondary_reload | |
362 | ||
df6b92e4 | 363 | #undef TARGET_EXTRA_LIVE_ON_ENTRY |
364 | #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry | |
365 | ||
623a97bc | 366 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
367 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE pa_asm_trampoline_template | |
368 | #undef TARGET_TRAMPOLINE_INIT | |
369 | #define TARGET_TRAMPOLINE_INIT pa_trampoline_init | |
370 | #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS | |
371 | #define TARGET_TRAMPOLINE_ADJUST_ADDRESS pa_trampoline_adjust_address | |
c731c4f5 | 372 | #undef TARGET_DELEGITIMIZE_ADDRESS |
373 | #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address | |
68bc9ae6 | 374 | #undef TARGET_INTERNAL_ARG_POINTER |
375 | #define TARGET_INTERNAL_ARG_POINTER pa_internal_arg_pointer | |
376 | #undef TARGET_CAN_ELIMINATE | |
377 | #define TARGET_CAN_ELIMINATE pa_can_eliminate | |
b2d7ede1 | 378 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
379 | #define TARGET_CONDITIONAL_REGISTER_USAGE pa_conditional_register_usage | |
0f9c87cc | 380 | #undef TARGET_C_MODE_FOR_SUFFIX |
381 | #define TARGET_C_MODE_FOR_SUFFIX pa_c_mode_for_suffix | |
c9b4a514 | 382 | #undef TARGET_ASM_FUNCTION_SECTION |
383 | #define TARGET_ASM_FUNCTION_SECTION pa_function_section | |
623a97bc | 384 | |
ca316360 | 385 | #undef TARGET_LEGITIMATE_CONSTANT_P |
386 | #define TARGET_LEGITIMATE_CONSTANT_P pa_legitimate_constant_p | |
7949e3eb | 387 | #undef TARGET_SECTION_TYPE_FLAGS |
388 | #define TARGET_SECTION_TYPE_FLAGS pa_section_type_flags | |
ca316360 | 389 | |
57e4bbfb | 390 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 391 | \f |
320e1276 | 392 | /* Parse the -mfixed-range= option string. */ |
393 | ||
394 | static void | |
395 | fix_range (const char *const_str) | |
396 | { | |
397 | int i, first, last; | |
398 | char *str, *dash, *comma; | |
399 | ||
400 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and | |
401 | REG2 are either register names or register numbers. The effect | |
402 | of this option is to mark the registers in the range from REG1 to | |
403 | REG2 as ``fixed'' so they won't be used by the compiler. This is | |
765cebfc | 404 | used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */ |
320e1276 | 405 | |
406 | i = strlen (const_str); | |
407 | str = (char *) alloca (i + 1); | |
408 | memcpy (str, const_str, i + 1); | |
409 | ||
410 | while (1) | |
411 | { | |
412 | dash = strchr (str, '-'); | |
413 | if (!dash) | |
414 | { | |
c3ceba8e | 415 | warning (0, "value of -mfixed-range must have form REG1-REG2"); |
320e1276 | 416 | return; |
417 | } | |
418 | *dash = '\0'; | |
419 | ||
420 | comma = strchr (dash + 1, ','); | |
421 | if (comma) | |
422 | *comma = '\0'; | |
423 | ||
424 | first = decode_reg_name (str); | |
425 | if (first < 0) | |
426 | { | |
c3ceba8e | 427 | warning (0, "unknown register name: %s", str); |
320e1276 | 428 | return; |
429 | } | |
430 | ||
431 | last = decode_reg_name (dash + 1); | |
432 | if (last < 0) | |
433 | { | |
c3ceba8e | 434 | warning (0, "unknown register name: %s", dash + 1); |
320e1276 | 435 | return; |
436 | } | |
437 | ||
438 | *dash = '-'; | |
439 | ||
440 | if (first > last) | |
441 | { | |
c3ceba8e | 442 | warning (0, "%s-%s is an empty range", str, dash + 1); |
320e1276 | 443 | return; |
444 | } | |
445 | ||
446 | for (i = first; i <= last; ++i) | |
447 | fixed_regs[i] = call_used_regs[i] = 1; | |
448 | ||
449 | if (!comma) | |
450 | break; | |
451 | ||
452 | *comma = ','; | |
453 | str = comma + 1; | |
454 | } | |
455 | ||
456 | /* Check if all floating point registers have been fixed. */ | |
457 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
458 | if (!fixed_regs[i]) | |
459 | break; | |
460 | ||
461 | if (i > FP_REG_LAST) | |
462 | target_flags |= MASK_DISABLE_FPREGS; | |
463 | } | |
464 | ||
93d3ee56 | 465 | /* Implement the TARGET_OPTION_OVERRIDE hook. */ |
466 | ||
467 | static void | |
468 | pa_option_override (void) | |
bd57250e | 469 | { |
d09dbe0a | 470 | unsigned int i; |
471 | cl_deferred_option *opt; | |
472 | VEC(cl_deferred_option,heap) *vec | |
473 | = (VEC(cl_deferred_option,heap) *) pa_deferred_options; | |
474 | ||
475 | FOR_EACH_VEC_ELT (cl_deferred_option, vec, i, opt) | |
476 | { | |
477 | switch (opt->opt_index) | |
478 | { | |
479 | case OPT_mfixed_range_: | |
480 | fix_range (opt->arg); | |
481 | break; | |
482 | ||
483 | default: | |
484 | gcc_unreachable (); | |
485 | } | |
486 | } | |
487 | ||
7c5101fc | 488 | /* Unconditional branches in the delay slot are not compatible with dwarf2 |
489 | call frame information. There is no benefit in using this optimization | |
490 | on PA8000 and later processors. */ | |
491 | if (pa_cpu >= PROCESSOR_8000 | |
218e3e4e | 492 | || (targetm_common.except_unwind_info (&global_options) == UI_DWARF2 |
b213bf24 | 493 | && flag_exceptions) |
7c5101fc | 494 | || flag_unwind_tables) |
495 | target_flags &= ~MASK_JUMP_IN_DELAY; | |
496 | ||
c7a4e712 | 497 | if (flag_pic && TARGET_PORTABLE_RUNTIME) |
498 | { | |
0a81f5a0 | 499 | warning (0, "PIC code generation is not supported in the portable runtime model"); |
c7a4e712 | 500 | } |
501 | ||
b29897dd | 502 | if (flag_pic && TARGET_FAST_INDIRECT_CALLS) |
c7a4e712 | 503 | { |
0a81f5a0 | 504 | warning (0, "PIC code generation is not compatible with fast indirect calls"); |
c7a4e712 | 505 | } |
751e64a1 | 506 | |
5bd7b548 | 507 | if (! TARGET_GAS && write_symbols != NO_DEBUG) |
508 | { | |
c3ceba8e | 509 | warning (0, "-g is only supported when using GAS on this processor,"); |
510 | warning (0, "-g option disabled"); | |
5bd7b548 | 511 | write_symbols = NO_DEBUG; |
512 | } | |
5cb4669a | 513 | |
fc44315f | 514 | /* We only support the "big PIC" model now. And we always generate PIC |
515 | code when in 64bit mode. */ | |
516 | if (flag_pic == 1 || TARGET_64BIT) | |
5e3c5739 | 517 | flag_pic = 2; |
518 | ||
1724df0b | 519 | /* Disable -freorder-blocks-and-partition as we don't support hot and |
520 | cold partitioning. */ | |
521 | if (flag_reorder_blocks_and_partition) | |
522 | { | |
523 | inform (input_location, | |
524 | "-freorder-blocks-and-partition does not work " | |
525 | "on this architecture"); | |
526 | flag_reorder_blocks_and_partition = 0; | |
527 | flag_reorder_blocks = 1; | |
528 | } | |
529 | ||
58356836 | 530 | /* We can't guarantee that .dword is available for 32-bit targets. */ |
531 | if (UNITS_PER_WORD == 4) | |
532 | targetm.asm_out.aligned_op.di = NULL; | |
533 | ||
534 | /* The unaligned ops are only available when using GAS. */ | |
535 | if (!TARGET_GAS) | |
536 | { | |
537 | targetm.asm_out.unaligned_op.hi = NULL; | |
538 | targetm.asm_out.unaligned_op.si = NULL; | |
539 | targetm.asm_out.unaligned_op.di = NULL; | |
540 | } | |
916c9cef | 541 | |
542 | init_machine_status = pa_init_machine_status; | |
134b4858 | 543 | } |
544 | ||
0f9c87cc | 545 | enum pa_builtins |
546 | { | |
547 | PA_BUILTIN_COPYSIGNQ, | |
548 | PA_BUILTIN_FABSQ, | |
549 | PA_BUILTIN_INFQ, | |
550 | PA_BUILTIN_HUGE_VALQ, | |
551 | PA_BUILTIN_max | |
552 | }; | |
553 | ||
554 | static GTY(()) tree pa_builtins[(int) PA_BUILTIN_max]; | |
555 | ||
066397a3 | 556 | static void |
5c1d8983 | 557 | pa_init_builtins (void) |
ffa8918b | 558 | { |
559 | #ifdef DONT_HAVE_FPUTC_UNLOCKED | |
b9a16870 | 560 | { |
561 | tree decl = builtin_decl_explicit (BUILT_IN_PUTC_UNLOCKED); | |
562 | set_builtin_decl (BUILT_IN_FPUTC_UNLOCKED, decl, | |
563 | builtin_decl_implicit_p (BUILT_IN_PUTC_UNLOCKED)); | |
564 | } | |
ffa8918b | 565 | #endif |
01cbacb9 | 566 | #if TARGET_HPUX_11 |
b9a16870 | 567 | { |
568 | tree decl; | |
569 | ||
570 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITE)) != NULL_TREE) | |
571 | set_user_assembler_name (decl, "_Isfinite"); | |
572 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITEF)) != NULL_TREE) | |
573 | set_user_assembler_name (decl, "_Isfinitef"); | |
574 | } | |
aafb162c | 575 | #endif |
0f9c87cc | 576 | |
577 | if (HPUX_LONG_DOUBLE_LIBRARY) | |
578 | { | |
579 | tree decl, ftype; | |
580 | ||
581 | /* Under HPUX, the __float128 type is a synonym for "long double". */ | |
582 | (*lang_hooks.types.register_builtin_type) (long_double_type_node, | |
583 | "__float128"); | |
584 | ||
585 | /* TFmode support builtins. */ | |
586 | ftype = build_function_type_list (long_double_type_node, | |
587 | long_double_type_node, | |
588 | NULL_TREE); | |
589 | decl = add_builtin_function ("__builtin_fabsq", ftype, | |
590 | PA_BUILTIN_FABSQ, BUILT_IN_MD, | |
591 | "_U_Qfabs", NULL_TREE); | |
592 | TREE_READONLY (decl) = 1; | |
593 | pa_builtins[PA_BUILTIN_FABSQ] = decl; | |
594 | ||
595 | ftype = build_function_type_list (long_double_type_node, | |
596 | long_double_type_node, | |
597 | long_double_type_node, | |
598 | NULL_TREE); | |
599 | decl = add_builtin_function ("__builtin_copysignq", ftype, | |
600 | PA_BUILTIN_COPYSIGNQ, BUILT_IN_MD, | |
601 | "_U_Qfcopysign", NULL_TREE); | |
602 | TREE_READONLY (decl) = 1; | |
603 | pa_builtins[PA_BUILTIN_COPYSIGNQ] = decl; | |
604 | ||
ab27801e | 605 | ftype = build_function_type_list (long_double_type_node, NULL_TREE); |
0f9c87cc | 606 | decl = add_builtin_function ("__builtin_infq", ftype, |
607 | PA_BUILTIN_INFQ, BUILT_IN_MD, | |
608 | NULL, NULL_TREE); | |
609 | pa_builtins[PA_BUILTIN_INFQ] = decl; | |
610 | ||
611 | decl = add_builtin_function ("__builtin_huge_valq", ftype, | |
612 | PA_BUILTIN_HUGE_VALQ, BUILT_IN_MD, | |
613 | NULL, NULL_TREE); | |
614 | pa_builtins[PA_BUILTIN_HUGE_VALQ] = decl; | |
615 | } | |
616 | } | |
617 | ||
618 | static rtx | |
619 | pa_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, | |
620 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
621 | int ignore ATTRIBUTE_UNUSED) | |
622 | { | |
623 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
624 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
625 | ||
626 | switch (fcode) | |
627 | { | |
628 | case PA_BUILTIN_FABSQ: | |
629 | case PA_BUILTIN_COPYSIGNQ: | |
630 | return expand_call (exp, target, ignore); | |
631 | ||
632 | case PA_BUILTIN_INFQ: | |
633 | case PA_BUILTIN_HUGE_VALQ: | |
634 | { | |
635 | enum machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp)); | |
636 | REAL_VALUE_TYPE inf; | |
637 | rtx tmp; | |
638 | ||
639 | real_inf (&inf); | |
640 | tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode); | |
641 | ||
642 | tmp = validize_mem (force_const_mem (target_mode, tmp)); | |
643 | ||
644 | if (target == 0) | |
645 | target = gen_reg_rtx (target_mode); | |
646 | ||
647 | emit_move_insn (target, tmp); | |
648 | return target; | |
649 | } | |
650 | ||
651 | default: | |
652 | gcc_unreachable (); | |
653 | } | |
654 | ||
655 | return NULL_RTX; | |
ffa8918b | 656 | } |
657 | ||
916c9cef | 658 | /* Function to init struct machine_function. |
659 | This will be called, via a pointer variable, | |
660 | from push_function_context. */ | |
661 | ||
662 | static struct machine_function * | |
663 | pa_init_machine_status (void) | |
664 | { | |
ba72912a | 665 | return ggc_alloc_cleared_machine_function (); |
916c9cef | 666 | } |
667 | ||
dbd3d89d | 668 | /* If FROM is a probable pointer register, mark TO as a probable |
669 | pointer register with the same pointer alignment as FROM. */ | |
670 | ||
671 | static void | |
672 | copy_reg_pointer (rtx to, rtx from) | |
673 | { | |
674 | if (REG_POINTER (from)) | |
675 | mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from))); | |
676 | } | |
677 | ||
6d36483b | 678 | /* Return 1 if X contains a symbolic expression. We know these |
679 | expressions will have one of a few well defined forms, so | |
347b5848 | 680 | we need only check those forms. */ |
681 | int | |
e202682d | 682 | pa_symbolic_expression_p (rtx x) |
347b5848 | 683 | { |
684 | ||
6dc3b0d9 | 685 | /* Strip off any HIGH. */ |
347b5848 | 686 | if (GET_CODE (x) == HIGH) |
687 | x = XEXP (x, 0); | |
688 | ||
689 | return (symbolic_operand (x, VOIDmode)); | |
690 | } | |
691 | ||
7c4d3047 | 692 | /* Accept any constant that can be moved in one instruction into a |
d9d7c968 | 693 | general register. */ |
6d36483b | 694 | int |
e202682d | 695 | pa_cint_ok_for_move (HOST_WIDE_INT ival) |
d9d7c968 | 696 | { |
697 | /* OK if ldo, ldil, or zdepi, can be used. */ | |
59ad2f1e | 698 | return (VAL_14_BITS_P (ival) |
e202682d | 699 | || pa_ldil_cint_p (ival) |
700 | || pa_zdepi_cint_p (ival)); | |
d9d7c968 | 701 | } |
87ad11b0 | 702 | \f |
59ad2f1e | 703 | /* True iff ldil can be used to load this CONST_INT. The least |
704 | significant 11 bits of the value must be zero and the value must | |
705 | not change sign when extended from 32 to 64 bits. */ | |
706 | int | |
e202682d | 707 | pa_ldil_cint_p (HOST_WIDE_INT ival) |
59ad2f1e | 708 | { |
709 | HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff); | |
710 | ||
711 | return x == 0 || x == ((HOST_WIDE_INT) -1 << 31); | |
712 | } | |
713 | ||
ea52c577 | 714 | /* True iff zdepi can be used to generate this CONST_INT. |
5b865faf | 715 | zdepi first sign extends a 5-bit signed number to a given field |
ea52c577 | 716 | length, then places this field anywhere in a zero. */ |
e057641f | 717 | int |
e202682d | 718 | pa_zdepi_cint_p (unsigned HOST_WIDE_INT x) |
fad0b60f | 719 | { |
3745c59b | 720 | unsigned HOST_WIDE_INT lsb_mask, t; |
fad0b60f | 721 | |
722 | /* This might not be obvious, but it's at least fast. | |
01cc3b75 | 723 | This function is critical; we don't have the time loops would take. */ |
42faba01 | 724 | lsb_mask = x & -x; |
725 | t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1); | |
726 | /* Return true iff t is a power of two. */ | |
fad0b60f | 727 | return ((t & (t - 1)) == 0); |
728 | } | |
729 | ||
6d36483b | 730 | /* True iff depi or extru can be used to compute (reg & mask). |
731 | Accept bit pattern like these: | |
732 | 0....01....1 | |
733 | 1....10....0 | |
734 | 1..10..01..1 */ | |
e057641f | 735 | int |
e202682d | 736 | pa_and_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 737 | { |
738 | mask = ~mask; | |
739 | mask += mask & -mask; | |
740 | return (mask & (mask - 1)) == 0; | |
741 | } | |
742 | ||
e057641f | 743 | /* True iff depi can be used to compute (reg | MASK). */ |
744 | int | |
e202682d | 745 | pa_ior_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 746 | { |
747 | mask += mask & -mask; | |
748 | return (mask & (mask - 1)) == 0; | |
749 | } | |
87ad11b0 | 750 | \f |
751 | /* Legitimize PIC addresses. If the address is already | |
752 | position-independent, we return ORIG. Newly generated | |
753 | position-independent addresses go to REG. If we need more | |
754 | than one register, we lose. */ | |
755 | ||
e202682d | 756 | static rtx |
5c1d8983 | 757 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
87ad11b0 | 758 | { |
759 | rtx pic_ref = orig; | |
760 | ||
f7229f19 | 761 | gcc_assert (!PA_SYMBOL_REF_TLS_P (orig)); |
716b2c5a | 762 | |
b090827b | 763 | /* Labels need special handling. */ |
611a88e1 | 764 | if (pic_label_operand (orig, mode)) |
b4a7bf10 | 765 | { |
3e478718 | 766 | rtx insn; |
767 | ||
2536cc16 | 768 | /* We do not want to go through the movXX expanders here since that |
769 | would create recursion. | |
770 | ||
771 | Nor do we really want to call a generator for a named pattern | |
772 | since that requires multiple patterns if we want to support | |
773 | multiple word sizes. | |
774 | ||
775 | So instead we just emit the raw set, which avoids the movXX | |
776 | expanders completely. */ | |
dbd3d89d | 777 | mark_reg_pointer (reg, BITS_PER_UNIT); |
3e478718 | 778 | insn = emit_insn (gen_rtx_SET (VOIDmode, reg, orig)); |
779 | ||
780 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
b9c74b4d | 781 | add_reg_note (insn, REG_EQUAL, orig); |
3e478718 | 782 | |
783 | /* During and after reload, we need to generate a REG_LABEL_OPERAND note | |
784 | and update LABEL_NUSES because this is not done automatically. */ | |
785 | if (reload_in_progress || reload_completed) | |
786 | { | |
787 | /* Extract LABEL_REF. */ | |
788 | if (GET_CODE (orig) == CONST) | |
789 | orig = XEXP (XEXP (orig, 0), 0); | |
790 | /* Extract CODE_LABEL. */ | |
791 | orig = XEXP (orig, 0); | |
a1ddb869 | 792 | add_reg_note (insn, REG_LABEL_OPERAND, orig); |
3e478718 | 793 | LABEL_NUSES (orig)++; |
794 | } | |
18d50ae6 | 795 | crtl->uses_pic_offset_table = 1; |
b4a7bf10 | 796 | return reg; |
797 | } | |
87ad11b0 | 798 | if (GET_CODE (orig) == SYMBOL_REF) |
799 | { | |
f9c1ba9d | 800 | rtx insn, tmp_reg; |
801 | ||
ecf2283d | 802 | gcc_assert (reg); |
87ad11b0 | 803 | |
f9c1ba9d | 804 | /* Before reload, allocate a temporary register for the intermediate |
805 | result. This allows the sequence to be deleted when the final | |
806 | result is unused and the insns are trivially dead. */ | |
807 | tmp_reg = ((reload_in_progress || reload_completed) | |
808 | ? reg : gen_reg_rtx (Pmode)); | |
809 | ||
39ec41d4 | 810 | if (function_label_operand (orig, VOIDmode)) |
3635d963 | 811 | { |
cefef42c | 812 | /* Force function label into memory in word mode. */ |
813 | orig = XEXP (force_const_mem (word_mode, orig), 0); | |
3635d963 | 814 | /* Load plabel address from DLT. */ |
815 | emit_move_insn (tmp_reg, | |
816 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, | |
817 | gen_rtx_HIGH (word_mode, orig))); | |
818 | pic_ref | |
819 | = gen_const_mem (Pmode, | |
820 | gen_rtx_LO_SUM (Pmode, tmp_reg, | |
821 | gen_rtx_UNSPEC (Pmode, | |
e265a6da | 822 | gen_rtvec (1, orig), |
823 | UNSPEC_DLTIND14R))); | |
3635d963 | 824 | emit_move_insn (reg, pic_ref); |
825 | /* Now load address of function descriptor. */ | |
826 | pic_ref = gen_rtx_MEM (Pmode, reg); | |
827 | } | |
828 | else | |
829 | { | |
830 | /* Load symbol reference from DLT. */ | |
831 | emit_move_insn (tmp_reg, | |
832 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, | |
833 | gen_rtx_HIGH (word_mode, orig))); | |
834 | pic_ref | |
835 | = gen_const_mem (Pmode, | |
836 | gen_rtx_LO_SUM (Pmode, tmp_reg, | |
837 | gen_rtx_UNSPEC (Pmode, | |
838 | gen_rtvec (1, orig), | |
839 | UNSPEC_DLTIND14R))); | |
840 | } | |
7014838c | 841 | |
18d50ae6 | 842 | crtl->uses_pic_offset_table = 1; |
dbd3d89d | 843 | mark_reg_pointer (reg, BITS_PER_UNIT); |
f9c1ba9d | 844 | insn = emit_move_insn (reg, pic_ref); |
845 | ||
846 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
24153880 | 847 | set_unique_reg_note (insn, REG_EQUAL, orig); |
f9c1ba9d | 848 | |
87ad11b0 | 849 | return reg; |
850 | } | |
851 | else if (GET_CODE (orig) == CONST) | |
852 | { | |
57ed30e5 | 853 | rtx base; |
87ad11b0 | 854 | |
855 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
856 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
857 | return orig; | |
858 | ||
ecf2283d | 859 | gcc_assert (reg); |
860 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); | |
861 | ||
862 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
863 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
864 | base == reg ? 0 : reg); | |
dbd3d89d | 865 | |
87ad11b0 | 866 | if (GET_CODE (orig) == CONST_INT) |
867 | { | |
42faba01 | 868 | if (INT_14_BITS (orig)) |
29c05e22 | 869 | return plus_constant (Pmode, base, INTVAL (orig)); |
87ad11b0 | 870 | orig = force_reg (Pmode, orig); |
871 | } | |
ad851752 | 872 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
87ad11b0 | 873 | /* Likewise, should we set special REG_NOTEs here? */ |
874 | } | |
dbd3d89d | 875 | |
87ad11b0 | 876 | return pic_ref; |
877 | } | |
878 | ||
716b2c5a | 879 | static GTY(()) rtx gen_tls_tga; |
880 | ||
881 | static rtx | |
882 | gen_tls_get_addr (void) | |
883 | { | |
884 | if (!gen_tls_tga) | |
885 | gen_tls_tga = init_one_libfunc ("__tls_get_addr"); | |
886 | return gen_tls_tga; | |
887 | } | |
888 | ||
889 | static rtx | |
890 | hppa_tls_call (rtx arg) | |
891 | { | |
892 | rtx ret; | |
893 | ||
894 | ret = gen_reg_rtx (Pmode); | |
895 | emit_library_call_value (gen_tls_get_addr (), ret, | |
896 | LCT_CONST, Pmode, 1, arg, Pmode); | |
897 | ||
898 | return ret; | |
899 | } | |
900 | ||
901 | static rtx | |
902 | legitimize_tls_address (rtx addr) | |
903 | { | |
904 | rtx ret, insn, tmp, t1, t2, tp; | |
905 | enum tls_model model = SYMBOL_REF_TLS_MODEL (addr); | |
906 | ||
907 | switch (model) | |
908 | { | |
909 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
910 | tmp = gen_reg_rtx (Pmode); | |
3f8d8851 | 911 | if (flag_pic) |
912 | emit_insn (gen_tgd_load_pic (tmp, addr)); | |
913 | else | |
914 | emit_insn (gen_tgd_load (tmp, addr)); | |
716b2c5a | 915 | ret = hppa_tls_call (tmp); |
916 | break; | |
917 | ||
918 | case TLS_MODEL_LOCAL_DYNAMIC: | |
919 | ret = gen_reg_rtx (Pmode); | |
920 | tmp = gen_reg_rtx (Pmode); | |
921 | start_sequence (); | |
3f8d8851 | 922 | if (flag_pic) |
923 | emit_insn (gen_tld_load_pic (tmp, addr)); | |
924 | else | |
925 | emit_insn (gen_tld_load (tmp, addr)); | |
716b2c5a | 926 | t1 = hppa_tls_call (tmp); |
927 | insn = get_insns (); | |
928 | end_sequence (); | |
929 | t2 = gen_reg_rtx (Pmode); | |
930 | emit_libcall_block (insn, t2, t1, | |
931 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
932 | UNSPEC_TLSLDBASE)); | |
933 | emit_insn (gen_tld_offset_load (ret, addr, t2)); | |
934 | break; | |
935 | ||
936 | case TLS_MODEL_INITIAL_EXEC: | |
937 | tp = gen_reg_rtx (Pmode); | |
938 | tmp = gen_reg_rtx (Pmode); | |
939 | ret = gen_reg_rtx (Pmode); | |
940 | emit_insn (gen_tp_load (tp)); | |
3f8d8851 | 941 | if (flag_pic) |
942 | emit_insn (gen_tie_load_pic (tmp, addr)); | |
943 | else | |
944 | emit_insn (gen_tie_load (tmp, addr)); | |
716b2c5a | 945 | emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp)); |
946 | break; | |
947 | ||
948 | case TLS_MODEL_LOCAL_EXEC: | |
949 | tp = gen_reg_rtx (Pmode); | |
950 | ret = gen_reg_rtx (Pmode); | |
951 | emit_insn (gen_tp_load (tp)); | |
952 | emit_insn (gen_tle_load (ret, addr, tp)); | |
953 | break; | |
954 | ||
955 | default: | |
f7229f19 | 956 | gcc_unreachable (); |
716b2c5a | 957 | } |
958 | ||
959 | return ret; | |
960 | } | |
961 | ||
347b5848 | 962 | /* Try machine-dependent ways of modifying an illegitimate address |
963 | to be legitimate. If we find one, return the new, valid address. | |
964 | This macro is used in only one place: `memory_address' in explow.c. | |
965 | ||
966 | OLDX is the address as it was before break_out_memory_refs was called. | |
967 | In some cases it is useful to look at this to decide what needs to be done. | |
968 | ||
347b5848 | 969 | It is always safe for this macro to do nothing. It exists to recognize |
6d36483b | 970 | opportunities to optimize the output. |
347b5848 | 971 | |
972 | For the PA, transform: | |
973 | ||
974 | memory(X + <large int>) | |
975 | ||
976 | into: | |
977 | ||
978 | if (<large int> & mask) >= 16 | |
979 | Y = (<large int> & ~mask) + mask + 1 Round up. | |
980 | else | |
981 | Y = (<large int> & ~mask) Round down. | |
982 | Z = X + Y | |
983 | memory (Z + (<large int> - Y)); | |
984 | ||
6d36483b | 985 | This is for CSE to find several similar references, and only use one Z. |
347b5848 | 986 | |
33f88b1c | 987 | X can either be a SYMBOL_REF or REG, but because combine cannot |
347b5848 | 988 | perform a 4->2 combination we do nothing for SYMBOL_REF + D where |
989 | D will not fit in 14 bits. | |
990 | ||
991 | MODE_FLOAT references allow displacements which fit in 5 bits, so use | |
6d36483b | 992 | 0x1f as the mask. |
347b5848 | 993 | |
994 | MODE_INT references allow displacements which fit in 14 bits, so use | |
6d36483b | 995 | 0x3fff as the mask. |
347b5848 | 996 | |
997 | This relies on the fact that most mode MODE_FLOAT references will use FP | |
998 | registers and most mode MODE_INT references will use integer registers. | |
999 | (In the rare case of an FP register used in an integer MODE, we depend | |
1000 | on secondary reloads to clean things up.) | |
1001 | ||
1002 | ||
1003 | It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special | |
1004 | manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed | |
01cc3b75 | 1005 | addressing modes to be used). |
347b5848 | 1006 | |
1007 | Put X and Z into registers. Then put the entire expression into | |
1008 | a register. */ | |
1009 | ||
1010 | rtx | |
5c1d8983 | 1011 | hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1012 | enum machine_mode mode) | |
347b5848 | 1013 | { |
347b5848 | 1014 | rtx orig = x; |
1015 | ||
dbd3d89d | 1016 | /* We need to canonicalize the order of operands in unscaled indexed |
1017 | addresses since the code that checks if an address is valid doesn't | |
1018 | always try both orders. */ | |
1019 | if (!TARGET_NO_SPACE_REGS | |
1020 | && GET_CODE (x) == PLUS | |
1021 | && GET_MODE (x) == Pmode | |
1022 | && REG_P (XEXP (x, 0)) | |
1023 | && REG_P (XEXP (x, 1)) | |
1024 | && REG_POINTER (XEXP (x, 0)) | |
1025 | && !REG_POINTER (XEXP (x, 1))) | |
1026 | return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0)); | |
1027 | ||
716b2c5a | 1028 | if (PA_SYMBOL_REF_TLS_P (x)) |
1029 | return legitimize_tls_address (x); | |
1030 | else if (flag_pic) | |
b4a7bf10 | 1031 | return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); |
1032 | ||
6dc3b0d9 | 1033 | /* Strip off CONST. */ |
347b5848 | 1034 | if (GET_CODE (x) == CONST) |
1035 | x = XEXP (x, 0); | |
1036 | ||
42819d4e | 1037 | /* Special case. Get the SYMBOL_REF into a register and use indexing. |
1038 | That should always be safe. */ | |
1039 | if (GET_CODE (x) == PLUS | |
1040 | && GET_CODE (XEXP (x, 0)) == REG | |
1041 | && GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
1042 | { | |
440c23df | 1043 | rtx reg = force_reg (Pmode, XEXP (x, 1)); |
1044 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0))); | |
42819d4e | 1045 | } |
1046 | ||
166bf021 | 1047 | /* Note we must reject symbols which represent function addresses |
1048 | since the assembler/linker can't handle arithmetic on plabels. */ | |
347b5848 | 1049 | if (GET_CODE (x) == PLUS |
1050 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
166bf021 | 1051 | && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF |
1052 | && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0))) | |
347b5848 | 1053 | || GET_CODE (XEXP (x, 0)) == REG)) |
1054 | { | |
1055 | rtx int_part, ptr_reg; | |
1056 | int newoffset; | |
1057 | int offset = INTVAL (XEXP (x, 1)); | |
1b6f11e2 | 1058 | int mask; |
1059 | ||
1060 | mask = (GET_MODE_CLASS (mode) == MODE_FLOAT | |
c78e6152 | 1061 | ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff); |
347b5848 | 1062 | |
6d36483b | 1063 | /* Choose which way to round the offset. Round up if we |
347b5848 | 1064 | are >= halfway to the next boundary. */ |
1065 | if ((offset & mask) >= ((mask + 1) / 2)) | |
1066 | newoffset = (offset & ~ mask) + mask + 1; | |
1067 | else | |
1068 | newoffset = (offset & ~ mask); | |
1069 | ||
1070 | /* If the newoffset will not fit in 14 bits (ldo), then | |
1071 | handling this would take 4 or 5 instructions (2 to load | |
1072 | the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to | |
1073 | add the new offset and the SYMBOL_REF.) Combine can | |
1074 | not handle 4->2 or 5->2 combinations, so do not create | |
1075 | them. */ | |
1076 | if (! VAL_14_BITS_P (newoffset) | |
1077 | && GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
1078 | { | |
29c05e22 | 1079 | rtx const_part = plus_constant (Pmode, XEXP (x, 0), newoffset); |
347b5848 | 1080 | rtx tmp_reg |
339613b4 | 1081 | = force_reg (Pmode, |
ad851752 | 1082 | gen_rtx_HIGH (Pmode, const_part)); |
347b5848 | 1083 | ptr_reg |
339613b4 | 1084 | = force_reg (Pmode, |
7014838c | 1085 | gen_rtx_LO_SUM (Pmode, |
1086 | tmp_reg, const_part)); | |
347b5848 | 1087 | } |
1088 | else | |
1089 | { | |
1090 | if (! VAL_14_BITS_P (newoffset)) | |
339613b4 | 1091 | int_part = force_reg (Pmode, GEN_INT (newoffset)); |
347b5848 | 1092 | else |
1093 | int_part = GEN_INT (newoffset); | |
1094 | ||
339613b4 | 1095 | ptr_reg = force_reg (Pmode, |
ad851752 | 1096 | gen_rtx_PLUS (Pmode, |
1097 | force_reg (Pmode, XEXP (x, 0)), | |
1098 | int_part)); | |
347b5848 | 1099 | } |
29c05e22 | 1100 | return plus_constant (Pmode, ptr_reg, offset - newoffset); |
347b5848 | 1101 | } |
45f1285a | 1102 | |
5115683e | 1103 | /* Handle (plus (mult (a) (shadd_constant)) (b)). */ |
45f1285a | 1104 | |
347b5848 | 1105 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT |
1106 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
e202682d | 1107 | && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))) |
6720e96c | 1108 | && (OBJECT_P (XEXP (x, 1)) |
45f1285a | 1109 | || GET_CODE (XEXP (x, 1)) == SUBREG) |
1110 | && GET_CODE (XEXP (x, 1)) != CONST) | |
347b5848 | 1111 | { |
1112 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1113 | rtx reg1, reg2; | |
5115683e | 1114 | |
1115 | reg1 = XEXP (x, 1); | |
1116 | if (GET_CODE (reg1) != REG) | |
1117 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1118 | ||
1119 | reg2 = XEXP (XEXP (x, 0), 0); | |
1120 | if (GET_CODE (reg2) != REG) | |
1121 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1122 | ||
ad851752 | 1123 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1124 | gen_rtx_MULT (Pmode, |
1125 | reg2, | |
1126 | GEN_INT (val)), | |
ad851752 | 1127 | reg1)); |
347b5848 | 1128 | } |
45f1285a | 1129 | |
00a87639 | 1130 | /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)). |
1131 | ||
1132 | Only do so for floating point modes since this is more speculative | |
1133 | and we lose if it's an integer store. */ | |
5115683e | 1134 | if (GET_CODE (x) == PLUS |
00a87639 | 1135 | && GET_CODE (XEXP (x, 0)) == PLUS |
1136 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
1137 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
e202682d | 1138 | && pa_shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) |
5115683e | 1139 | && (mode == SFmode || mode == DFmode)) |
00a87639 | 1140 | { |
5115683e | 1141 | |
1142 | /* First, try and figure out what to use as a base register. */ | |
1ce99229 | 1143 | rtx reg1, reg2, base, idx; |
5115683e | 1144 | |
1145 | reg1 = XEXP (XEXP (x, 0), 1); | |
1146 | reg2 = XEXP (x, 1); | |
1147 | base = NULL_RTX; | |
1148 | idx = NULL_RTX; | |
1149 | ||
1150 | /* Make sure they're both regs. If one was a SYMBOL_REF [+ const], | |
e202682d | 1151 | then pa_emit_move_sequence will turn on REG_POINTER so we'll know |
e61a0a7f | 1152 | it's a base register below. */ |
5115683e | 1153 | if (GET_CODE (reg1) != REG) |
1154 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1155 | ||
1156 | if (GET_CODE (reg2) != REG) | |
1157 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1158 | ||
1159 | /* Figure out what the base and index are. */ | |
9840d99d | 1160 | |
5115683e | 1161 | if (GET_CODE (reg1) == REG |
e61a0a7f | 1162 | && REG_POINTER (reg1)) |
5115683e | 1163 | { |
1164 | base = reg1; | |
ad851752 | 1165 | idx = gen_rtx_PLUS (Pmode, |
1166 | gen_rtx_MULT (Pmode, | |
1167 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
1168 | XEXP (XEXP (XEXP (x, 0), 0), 1)), | |
1169 | XEXP (x, 1)); | |
5115683e | 1170 | } |
1171 | else if (GET_CODE (reg2) == REG | |
e61a0a7f | 1172 | && REG_POINTER (reg2)) |
5115683e | 1173 | { |
1174 | base = reg2; | |
5115683e | 1175 | idx = XEXP (x, 0); |
1176 | } | |
1177 | ||
1178 | if (base == 0) | |
21f3ee9c | 1179 | return orig; |
5115683e | 1180 | |
1181 | /* If the index adds a large constant, try to scale the | |
1182 | constant so that it can be loaded with only one insn. */ | |
1183 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1184 | && VAL_14_BITS_P (INTVAL (XEXP (idx, 1)) | |
1185 | / INTVAL (XEXP (XEXP (idx, 0), 1))) | |
1186 | && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0) | |
1187 | { | |
1188 | /* Divide the CONST_INT by the scale factor, then add it to A. */ | |
1189 | int val = INTVAL (XEXP (idx, 1)); | |
1190 | ||
1191 | val /= INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1192 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1193 | if (GET_CODE (reg1) != REG) | |
1194 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1195 | ||
ad851752 | 1196 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val))); |
5115683e | 1197 | |
1198 | /* We can now generate a simple scaled indexed address. */ | |
7014838c | 1199 | return |
1200 | force_reg | |
1201 | (Pmode, gen_rtx_PLUS (Pmode, | |
1202 | gen_rtx_MULT (Pmode, reg1, | |
1203 | XEXP (XEXP (idx, 0), 1)), | |
1204 | base)); | |
5115683e | 1205 | } |
1206 | ||
1207 | /* If B + C is still a valid base register, then add them. */ | |
1208 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1209 | && INTVAL (XEXP (idx, 1)) <= 4096 | |
1210 | && INTVAL (XEXP (idx, 1)) >= -4096) | |
1211 | { | |
1212 | int val = INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1213 | rtx reg1, reg2; | |
1214 | ||
ad851752 | 1215 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1))); |
5115683e | 1216 | |
1217 | reg2 = XEXP (XEXP (idx, 0), 0); | |
1218 | if (GET_CODE (reg2) != CONST_INT) | |
1219 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1220 | ||
ad851752 | 1221 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1222 | gen_rtx_MULT (Pmode, |
1223 | reg2, | |
ad851752 | 1224 | GEN_INT (val)), |
1225 | reg1)); | |
5115683e | 1226 | } |
1227 | ||
1228 | /* Get the index into a register, then add the base + index and | |
1229 | return a register holding the result. */ | |
1230 | ||
1231 | /* First get A into a register. */ | |
1232 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1233 | if (GET_CODE (reg1) != REG) | |
1234 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1235 | ||
1236 | /* And get B into a register. */ | |
1237 | reg2 = XEXP (idx, 1); | |
1238 | if (GET_CODE (reg2) != REG) | |
1239 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1240 | ||
ad851752 | 1241 | reg1 = force_reg (Pmode, |
1242 | gen_rtx_PLUS (Pmode, | |
1243 | gen_rtx_MULT (Pmode, reg1, | |
1244 | XEXP (XEXP (idx, 0), 1)), | |
1245 | reg2)); | |
5115683e | 1246 | |
1247 | /* Add the result to our base register and return. */ | |
ad851752 | 1248 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1)); |
9840d99d | 1249 | |
00a87639 | 1250 | } |
1251 | ||
6d36483b | 1252 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
fb5390c1 | 1253 | special handling to avoid creating an indexed memory address |
1254 | with x-100000 as the base. | |
9840d99d | 1255 | |
fb5390c1 | 1256 | If the constant part is small enough, then it's still safe because |
1257 | there is a guard page at the beginning and end of the data segment. | |
1258 | ||
1259 | Scaled references are common enough that we want to try and rearrange the | |
1260 | terms so that we can use indexing for these addresses too. Only | |
00a87639 | 1261 | do the optimization for floatint point modes. */ |
45f1285a | 1262 | |
fb5390c1 | 1263 | if (GET_CODE (x) == PLUS |
e202682d | 1264 | && pa_symbolic_expression_p (XEXP (x, 1))) |
45f1285a | 1265 | { |
1266 | /* Ugly. We modify things here so that the address offset specified | |
1267 | by the index expression is computed first, then added to x to form | |
fb5390c1 | 1268 | the entire address. */ |
45f1285a | 1269 | |
00a87639 | 1270 | rtx regx1, regx2, regy1, regy2, y; |
45f1285a | 1271 | |
1272 | /* Strip off any CONST. */ | |
1273 | y = XEXP (x, 1); | |
1274 | if (GET_CODE (y) == CONST) | |
1275 | y = XEXP (y, 0); | |
1276 | ||
7ee96d6e | 1277 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1278 | { | |
00a87639 | 1279 | /* See if this looks like |
1280 | (plus (mult (reg) (shadd_const)) | |
1281 | (const (plus (symbol_ref) (const_int)))) | |
1282 | ||
5115683e | 1283 | Where const_int is small. In that case the const |
9840d99d | 1284 | expression is a valid pointer for indexing. |
5115683e | 1285 | |
1286 | If const_int is big, but can be divided evenly by shadd_const | |
1287 | and added to (reg). This allows more scaled indexed addresses. */ | |
1288 | if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1289 | && GET_CODE (XEXP (x, 0)) == MULT | |
00a87639 | 1290 | && GET_CODE (XEXP (y, 1)) == CONST_INT |
5115683e | 1291 | && INTVAL (XEXP (y, 1)) >= -4096 |
1292 | && INTVAL (XEXP (y, 1)) <= 4095 | |
1293 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
e202682d | 1294 | && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) |
5115683e | 1295 | { |
1296 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1297 | rtx reg1, reg2; | |
1298 | ||
1299 | reg1 = XEXP (x, 1); | |
1300 | if (GET_CODE (reg1) != REG) | |
1301 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1302 | ||
1303 | reg2 = XEXP (XEXP (x, 0), 0); | |
1304 | if (GET_CODE (reg2) != REG) | |
1305 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1306 | ||
ad851752 | 1307 | return force_reg (Pmode, |
1308 | gen_rtx_PLUS (Pmode, | |
7014838c | 1309 | gen_rtx_MULT (Pmode, |
1310 | reg2, | |
ad851752 | 1311 | GEN_INT (val)), |
7014838c | 1312 | reg1)); |
5115683e | 1313 | } |
1314 | else if ((mode == DFmode || mode == SFmode) | |
1315 | && GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1316 | && GET_CODE (XEXP (x, 0)) == MULT | |
1317 | && GET_CODE (XEXP (y, 1)) == CONST_INT | |
1318 | && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0 | |
1319 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
e202682d | 1320 | && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) |
00a87639 | 1321 | { |
1322 | regx1 | |
1323 | = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1)) | |
1324 | / INTVAL (XEXP (XEXP (x, 0), 1)))); | |
1325 | regx2 = XEXP (XEXP (x, 0), 0); | |
1326 | if (GET_CODE (regx2) != REG) | |
1327 | regx2 = force_reg (Pmode, force_operand (regx2, 0)); | |
ad851752 | 1328 | regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1329 | regx2, regx1)); | |
7014838c | 1330 | return |
1331 | force_reg (Pmode, | |
1332 | gen_rtx_PLUS (Pmode, | |
1333 | gen_rtx_MULT (Pmode, regx2, | |
1334 | XEXP (XEXP (x, 0), 1)), | |
1335 | force_reg (Pmode, XEXP (y, 0)))); | |
00a87639 | 1336 | } |
fb5390c1 | 1337 | else if (GET_CODE (XEXP (y, 1)) == CONST_INT |
1338 | && INTVAL (XEXP (y, 1)) >= -4096 | |
1339 | && INTVAL (XEXP (y, 1)) <= 4095) | |
1340 | { | |
1341 | /* This is safe because of the guard page at the | |
1342 | beginning and end of the data space. Just | |
1343 | return the original address. */ | |
1344 | return orig; | |
1345 | } | |
00a87639 | 1346 | else |
1347 | { | |
1348 | /* Doesn't look like one we can optimize. */ | |
1349 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1350 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1351 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1352 | regx1 = force_reg (Pmode, | |
ad851752 | 1353 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1354 | regx1, regy2)); | |
1355 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); | |
00a87639 | 1356 | } |
7ee96d6e | 1357 | } |
45f1285a | 1358 | } |
1359 | ||
347b5848 | 1360 | return orig; |
1361 | } | |
1362 | ||
93d3ee56 | 1363 | /* Implement the TARGET_REGISTER_MOVE_COST hook. |
1364 | ||
1365 | Compute extra cost of moving data between one register class | |
1366 | and another. | |
1367 | ||
1368 | Make moves from SAR so expensive they should never happen. We used to | |
1369 | have 0xffff here, but that generates overflow in rare cases. | |
1370 | ||
1371 | Copies involving a FP register and a non-FP register are relatively | |
1372 | expensive because they must go through memory. | |
1373 | ||
1374 | Other copies are reasonably cheap. */ | |
1375 | ||
1376 | static int | |
1377 | hppa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
1378 | reg_class_t from, reg_class_t to) | |
1379 | { | |
1380 | if (from == SHIFT_REGS) | |
1381 | return 0x100; | |
5ddb2975 | 1382 | else if (to == SHIFT_REGS && FP_REG_CLASS_P (from)) |
1383 | return 18; | |
93d3ee56 | 1384 | else if ((FP_REG_CLASS_P (from) && ! FP_REG_CLASS_P (to)) |
1385 | || (FP_REG_CLASS_P (to) && ! FP_REG_CLASS_P (from))) | |
1386 | return 16; | |
1387 | else | |
1388 | return 2; | |
1389 | } | |
1390 | ||
87ad11b0 | 1391 | /* For the HPPA, REG and REG+CONST is cost 0 |
1392 | and addresses involving symbolic constants are cost 2. | |
1393 | ||
1394 | PIC addresses are very expensive. | |
1395 | ||
1396 | It is no coincidence that this has the same structure | |
1397 | as GO_IF_LEGITIMATE_ADDRESS. */ | |
ec0457a8 | 1398 | |
1399 | static int | |
d9c5e5f4 | 1400 | hppa_address_cost (rtx X, enum machine_mode mode ATTRIBUTE_UNUSED, |
1401 | addr_space_t as ATTRIBUTE_UNUSED, | |
f529eb25 | 1402 | bool speed ATTRIBUTE_UNUSED) |
87ad11b0 | 1403 | { |
ec0457a8 | 1404 | switch (GET_CODE (X)) |
1405 | { | |
1406 | case REG: | |
1407 | case PLUS: | |
1408 | case LO_SUM: | |
87ad11b0 | 1409 | return 1; |
ec0457a8 | 1410 | case HIGH: |
1411 | return 2; | |
1412 | default: | |
1413 | return 4; | |
1414 | } | |
87ad11b0 | 1415 | } |
1416 | ||
fab7adbf | 1417 | /* Compute a (partial) cost for rtx X. Return true if the complete |
1418 | cost has been computed, and false if subexpressions should be | |
1419 | scanned. In either case, *TOTAL contains the cost result. */ | |
1420 | ||
1421 | static bool | |
20d892d1 | 1422 | hppa_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
1423 | int *total, bool speed ATTRIBUTE_UNUSED) | |
fab7adbf | 1424 | { |
42622d54 | 1425 | int factor; |
1426 | ||
fab7adbf | 1427 | switch (code) |
1428 | { | |
1429 | case CONST_INT: | |
1430 | if (INTVAL (x) == 0) | |
1431 | *total = 0; | |
1432 | else if (INT_14_BITS (x)) | |
1433 | *total = 1; | |
1434 | else | |
1435 | *total = 2; | |
1436 | return true; | |
1437 | ||
1438 | case HIGH: | |
1439 | *total = 2; | |
1440 | return true; | |
1441 | ||
1442 | case CONST: | |
1443 | case LABEL_REF: | |
1444 | case SYMBOL_REF: | |
1445 | *total = 4; | |
1446 | return true; | |
1447 | ||
1448 | case CONST_DOUBLE: | |
1449 | if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode)) | |
1450 | && outer_code != SET) | |
1451 | *total = 0; | |
1452 | else | |
1453 | *total = 8; | |
1454 | return true; | |
1455 | ||
1456 | case MULT: | |
1457 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
42622d54 | 1458 | { |
1459 | *total = COSTS_N_INSNS (3); | |
1460 | return true; | |
1461 | } | |
1462 | ||
1463 | /* A mode size N times larger than SImode needs O(N*N) more insns. */ | |
1464 | factor = GET_MODE_SIZE (GET_MODE (x)) / 4; | |
1465 | if (factor == 0) | |
1466 | factor = 1; | |
1467 | ||
1468 | if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT) | |
1469 | *total = factor * factor * COSTS_N_INSNS (8); | |
fab7adbf | 1470 | else |
42622d54 | 1471 | *total = factor * factor * COSTS_N_INSNS (20); |
fab7adbf | 1472 | return true; |
1473 | ||
1474 | case DIV: | |
1475 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1476 | { | |
1477 | *total = COSTS_N_INSNS (14); | |
1478 | return true; | |
1479 | } | |
8e262b5e | 1480 | /* FALLTHRU */ |
fab7adbf | 1481 | |
1482 | case UDIV: | |
1483 | case MOD: | |
1484 | case UMOD: | |
42622d54 | 1485 | /* A mode size N times larger than SImode needs O(N*N) more insns. */ |
1486 | factor = GET_MODE_SIZE (GET_MODE (x)) / 4; | |
1487 | if (factor == 0) | |
1488 | factor = 1; | |
1489 | ||
1490 | *total = factor * factor * COSTS_N_INSNS (60); | |
fab7adbf | 1491 | return true; |
1492 | ||
1493 | case PLUS: /* this includes shNadd insns */ | |
1494 | case MINUS: | |
1495 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
42622d54 | 1496 | { |
1497 | *total = COSTS_N_INSNS (3); | |
1498 | return true; | |
1499 | } | |
1500 | ||
1501 | /* A size N times larger than UNITS_PER_WORD needs N times as | |
1502 | many insns, taking N times as long. */ | |
1503 | factor = GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD; | |
1504 | if (factor == 0) | |
1505 | factor = 1; | |
1506 | *total = factor * COSTS_N_INSNS (1); | |
fab7adbf | 1507 | return true; |
1508 | ||
1509 | case ASHIFT: | |
1510 | case ASHIFTRT: | |
1511 | case LSHIFTRT: | |
1512 | *total = COSTS_N_INSNS (1); | |
1513 | return true; | |
1514 | ||
1515 | default: | |
1516 | return false; | |
1517 | } | |
1518 | } | |
1519 | ||
9840d99d | 1520 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a |
1521 | new rtx with the correct mode. */ | |
1522 | static inline rtx | |
5c1d8983 | 1523 | force_mode (enum machine_mode mode, rtx orig) |
9840d99d | 1524 | { |
1525 | if (mode == GET_MODE (orig)) | |
1526 | return orig; | |
1527 | ||
ecf2283d | 1528 | gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER); |
9840d99d | 1529 | |
1530 | return gen_rtx_REG (mode, REGNO (orig)); | |
1531 | } | |
1532 | ||
716b2c5a | 1533 | /* Return 1 if *X is a thread-local symbol. */ |
1534 | ||
1535 | static int | |
1536 | pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
1537 | { | |
1538 | return PA_SYMBOL_REF_TLS_P (*x); | |
1539 | } | |
1540 | ||
1541 | /* Return 1 if X contains a thread-local symbol. */ | |
1542 | ||
1543 | bool | |
1544 | pa_tls_referenced_p (rtx x) | |
1545 | { | |
1546 | if (!TARGET_HAVE_TLS) | |
1547 | return false; | |
1548 | ||
1549 | return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0); | |
1550 | } | |
1551 | ||
7d7d7bd2 | 1552 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ |
1553 | ||
1554 | static bool | |
1555 | pa_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
1556 | { | |
1557 | return pa_tls_referenced_p (x); | |
1558 | } | |
1559 | ||
87ad11b0 | 1560 | /* Emit insns to move operands[1] into operands[0]. |
1561 | ||
1562 | Return 1 if we have written out everything that needs to be done to | |
1563 | do the move. Otherwise, return 0 and the caller will emit the move | |
9840d99d | 1564 | normally. |
f756078b | 1565 | |
1566 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
2cecd772 | 1567 | will be used. This routine is responsible for creating a new copy |
f756078b | 1568 | of SCRATCH_REG in the proper mode. */ |
87ad11b0 | 1569 | |
1570 | int | |
e202682d | 1571 | pa_emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) |
87ad11b0 | 1572 | { |
1573 | register rtx operand0 = operands[0]; | |
1574 | register rtx operand1 = operands[1]; | |
4a155b0f | 1575 | register rtx tem; |
87ad11b0 | 1576 | |
dbd3d89d | 1577 | /* We can only handle indexed addresses in the destination operand |
1578 | of floating point stores. Thus, we need to break out indexed | |
1579 | addresses from the destination operand. */ | |
1580 | if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0))) | |
1581 | { | |
e1ba4a27 | 1582 | gcc_assert (can_create_pseudo_p ()); |
dbd3d89d | 1583 | |
1584 | tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0)); | |
1585 | operand0 = replace_equiv_address (operand0, tem); | |
1586 | } | |
1587 | ||
1588 | /* On targets with non-equivalent space registers, break out unscaled | |
1589 | indexed addresses from the source operand before the final CSE. | |
1590 | We have to do this because the REG_POINTER flag is not correctly | |
1591 | carried through various optimization passes and CSE may substitute | |
1592 | a pseudo without the pointer set for one with the pointer set. As | |
5aedf60c | 1593 | a result, we loose various opportunities to create insns with |
dbd3d89d | 1594 | unscaled indexed addresses. */ |
1595 | if (!TARGET_NO_SPACE_REGS | |
1596 | && !cse_not_expected | |
1597 | && GET_CODE (operand1) == MEM | |
1598 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1599 | && REG_P (XEXP (XEXP (operand1, 0), 0)) | |
1600 | && REG_P (XEXP (XEXP (operand1, 0), 1))) | |
1601 | operand1 | |
1602 | = replace_equiv_address (operand1, | |
1603 | copy_to_mode_reg (Pmode, XEXP (operand1, 0))); | |
1604 | ||
2d4dc8d2 | 1605 | if (scratch_reg |
1606 | && reload_in_progress && GET_CODE (operand0) == REG | |
d1e2bb73 | 1607 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) |
1c654ff1 | 1608 | operand0 = reg_equiv_mem (REGNO (operand0)); |
2d4dc8d2 | 1609 | else if (scratch_reg |
1610 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
d1e2bb73 | 1611 | && GET_CODE (SUBREG_REG (operand0)) == REG |
1612 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1613 | { |
701e46d0 | 1614 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1615 | the code which tracks sets/uses for delete_output_reload. */ |
1616 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
1c654ff1 | 1617 | reg_equiv_mem (REGNO (SUBREG_REG (operand0))), |
701e46d0 | 1618 | SUBREG_BYTE (operand0)); |
e00b80b2 | 1619 | operand0 = alter_subreg (&temp); |
a3afad75 | 1620 | } |
d1e2bb73 | 1621 | |
2d4dc8d2 | 1622 | if (scratch_reg |
1623 | && reload_in_progress && GET_CODE (operand1) == REG | |
d1e2bb73 | 1624 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) |
1c654ff1 | 1625 | operand1 = reg_equiv_mem (REGNO (operand1)); |
2d4dc8d2 | 1626 | else if (scratch_reg |
1627 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
d1e2bb73 | 1628 | && GET_CODE (SUBREG_REG (operand1)) == REG |
1629 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1630 | { |
701e46d0 | 1631 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1632 | the code which tracks sets/uses for delete_output_reload. */ |
1633 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
1c654ff1 | 1634 | reg_equiv_mem (REGNO (SUBREG_REG (operand1))), |
701e46d0 | 1635 | SUBREG_BYTE (operand1)); |
e00b80b2 | 1636 | operand1 = alter_subreg (&temp); |
a3afad75 | 1637 | } |
d1e2bb73 | 1638 | |
2d4dc8d2 | 1639 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM |
4a155b0f | 1640 | && ((tem = find_replacement (&XEXP (operand0, 0))) |
1641 | != XEXP (operand0, 0))) | |
ed498904 | 1642 | operand0 = replace_equiv_address (operand0, tem); |
dbd3d89d | 1643 | |
2d4dc8d2 | 1644 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM |
4a155b0f | 1645 | && ((tem = find_replacement (&XEXP (operand1, 0))) |
1646 | != XEXP (operand1, 0))) | |
ed498904 | 1647 | operand1 = replace_equiv_address (operand1, tem); |
4a155b0f | 1648 | |
e8fdbafa | 1649 | /* Handle secondary reloads for loads/stores of FP registers from |
047e3121 | 1650 | REG+D addresses where D does not fit in 5 or 14 bits, including |
42819d4e | 1651 | (subreg (mem (addr))) cases. */ |
6bcdc1fb | 1652 | if (scratch_reg |
1653 | && fp_reg_operand (operand0, mode) | |
6b1c36c2 | 1654 | && ((GET_CODE (operand1) == MEM |
047e3121 | 1655 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode), |
1656 | XEXP (operand1, 0))) | |
6b1c36c2 | 1657 | || ((GET_CODE (operand1) == SUBREG |
1658 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
047e3121 | 1659 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1660 | ? SFmode : DFmode), | |
1661 | XEXP (XEXP (operand1, 0), 0)))))) | |
d6f01525 | 1662 | { |
6b1c36c2 | 1663 | if (GET_CODE (operand1) == SUBREG) |
1664 | operand1 = XEXP (operand1, 0); | |
1665 | ||
f756078b | 1666 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1667 | it in WORD_MODE regardless of what mode it was originally given | |
1668 | to us. */ | |
9840d99d | 1669 | scratch_reg = force_mode (word_mode, scratch_reg); |
7ee39d73 | 1670 | |
1671 | /* D might not fit in 14 bits either; for such cases load D into | |
1672 | scratch reg. */ | |
440c23df | 1673 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) |
7ee39d73 | 1674 | { |
1675 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
dbd3d89d | 1676 | emit_move_insn (scratch_reg, |
1677 | gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
1678 | Pmode, | |
1679 | XEXP (XEXP (operand1, 0), 0), | |
1680 | scratch_reg)); | |
7ee39d73 | 1681 | } |
1682 | else | |
1683 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
7014838c | 1684 | emit_insn (gen_rtx_SET (VOIDmode, operand0, |
ed498904 | 1685 | replace_equiv_address (operand1, scratch_reg))); |
d6f01525 | 1686 | return 1; |
1687 | } | |
6bcdc1fb | 1688 | else if (scratch_reg |
1689 | && fp_reg_operand (operand1, mode) | |
6b1c36c2 | 1690 | && ((GET_CODE (operand0) == MEM |
047e3121 | 1691 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1692 | ? SFmode : DFmode), | |
1693 | XEXP (operand0, 0))) | |
6b1c36c2 | 1694 | || ((GET_CODE (operand0) == SUBREG) |
1695 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
047e3121 | 1696 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1697 | ? SFmode : DFmode), | |
6bcdc1fb | 1698 | XEXP (XEXP (operand0, 0), 0))))) |
d6f01525 | 1699 | { |
6b1c36c2 | 1700 | if (GET_CODE (operand0) == SUBREG) |
1701 | operand0 = XEXP (operand0, 0); | |
1702 | ||
f756078b | 1703 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1704 | it in WORD_MODE regardless of what mode it was originally given | |
1705 | to us. */ | |
9840d99d | 1706 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1707 | |
7ee39d73 | 1708 | /* D might not fit in 14 bits either; for such cases load D into |
1709 | scratch reg. */ | |
440c23df | 1710 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) |
7ee39d73 | 1711 | { |
1712 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
ad851752 | 1713 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, |
1714 | 0)), | |
440c23df | 1715 | Pmode, |
ad851752 | 1716 | XEXP (XEXP (operand0, 0), |
1717 | 0), | |
1718 | scratch_reg)); | |
7ee39d73 | 1719 | } |
1720 | else | |
1721 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
ed498904 | 1722 | emit_insn (gen_rtx_SET (VOIDmode, |
1723 | replace_equiv_address (operand0, scratch_reg), | |
ad851752 | 1724 | operand1)); |
d6f01525 | 1725 | return 1; |
1726 | } | |
753bd06a | 1727 | /* Handle secondary reloads for loads of FP registers from constant |
1728 | expressions by forcing the constant into memory. | |
1729 | ||
6bcdc1fb | 1730 | Use scratch_reg to hold the address of the memory location. |
753bd06a | 1731 | |
0a5dd1a5 | 1732 | The proper fix is to change TARGET_PREFERRED_RELOAD_CLASS to return |
87fcb603 | 1733 | NO_REGS when presented with a const_int and a register class |
753bd06a | 1734 | containing only FP registers. Doing so unfortunately creates |
1735 | more problems than it solves. Fix this for 2.5. */ | |
6bcdc1fb | 1736 | else if (scratch_reg |
753bd06a | 1737 | && CONSTANT_P (operand1) |
6bcdc1fb | 1738 | && fp_reg_operand (operand0, mode)) |
753bd06a | 1739 | { |
ed498904 | 1740 | rtx const_mem, xoperands[2]; |
753bd06a | 1741 | |
f756078b | 1742 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1743 | it in WORD_MODE regardless of what mode it was originally given | |
1744 | to us. */ | |
9840d99d | 1745 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1746 | |
753bd06a | 1747 | /* Force the constant into memory and put the address of the |
1748 | memory location into scratch_reg. */ | |
ed498904 | 1749 | const_mem = force_const_mem (mode, operand1); |
753bd06a | 1750 | xoperands[0] = scratch_reg; |
ed498904 | 1751 | xoperands[1] = XEXP (const_mem, 0); |
e202682d | 1752 | pa_emit_move_sequence (xoperands, Pmode, 0); |
753bd06a | 1753 | |
1754 | /* Now load the destination register. */ | |
7014838c | 1755 | emit_insn (gen_rtx_SET (mode, operand0, |
ed498904 | 1756 | replace_equiv_address (const_mem, scratch_reg))); |
753bd06a | 1757 | return 1; |
1758 | } | |
e8fdbafa | 1759 | /* Handle secondary reloads for SAR. These occur when trying to load |
5ddb2975 | 1760 | the SAR from memory or a constant. */ |
6bcdc1fb | 1761 | else if (scratch_reg |
1762 | && GET_CODE (operand0) == REG | |
2a170404 | 1763 | && REGNO (operand0) < FIRST_PSEUDO_REGISTER |
e8fdbafa | 1764 | && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS |
5ddb2975 | 1765 | && (GET_CODE (operand1) == MEM || GET_CODE (operand1) == CONST_INT)) |
e8fdbafa | 1766 | { |
7eac600c | 1767 | /* D might not fit in 14 bits either; for such cases load D into |
1768 | scratch reg. */ | |
1769 | if (GET_CODE (operand1) == MEM | |
853940d9 | 1770 | && !memory_address_p (GET_MODE (operand0), XEXP (operand1, 0))) |
7eac600c | 1771 | { |
fc4d127d | 1772 | /* We are reloading the address into the scratch register, so we |
1773 | want to make sure the scratch register is a full register. */ | |
9840d99d | 1774 | scratch_reg = force_mode (word_mode, scratch_reg); |
fc4d127d | 1775 | |
9840d99d | 1776 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); |
ad851752 | 1777 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, |
1778 | 0)), | |
440c23df | 1779 | Pmode, |
ad851752 | 1780 | XEXP (XEXP (operand1, 0), |
1781 | 0), | |
1782 | scratch_reg)); | |
fc4d127d | 1783 | |
1784 | /* Now we are going to load the scratch register from memory, | |
1785 | we want to load it in the same width as the original MEM, | |
1786 | which must be the same as the width of the ultimate destination, | |
1787 | OPERAND0. */ | |
9840d99d | 1788 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1789 | ||
ed498904 | 1790 | emit_move_insn (scratch_reg, |
1791 | replace_equiv_address (operand1, scratch_reg)); | |
7eac600c | 1792 | } |
1793 | else | |
fc4d127d | 1794 | { |
1795 | /* We want to load the scratch register using the same mode as | |
1796 | the ultimate destination. */ | |
9840d99d | 1797 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1798 | ||
fc4d127d | 1799 | emit_move_insn (scratch_reg, operand1); |
1800 | } | |
1801 | ||
1802 | /* And emit the insn to set the ultimate destination. We know that | |
1803 | the scratch register has the same mode as the destination at this | |
1804 | point. */ | |
e8fdbafa | 1805 | emit_move_insn (operand0, scratch_reg); |
1806 | return 1; | |
1807 | } | |
dbd3d89d | 1808 | /* Handle the most common case: storing into a register. */ |
d6f01525 | 1809 | else if (register_operand (operand0, mode)) |
87ad11b0 | 1810 | { |
f784d2ac | 1811 | /* Legitimize TLS symbol references. This happens for references |
1812 | that aren't a legitimate constant. */ | |
1813 | if (PA_SYMBOL_REF_TLS_P (operand1)) | |
1814 | operand1 = legitimize_tls_address (operand1); | |
1815 | ||
87ad11b0 | 1816 | if (register_operand (operand1, mode) |
93f6e1c7 | 1817 | || (GET_CODE (operand1) == CONST_INT |
e202682d | 1818 | && pa_cint_ok_for_move (INTVAL (operand1))) |
891b55b4 | 1819 | || (operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1820 | || (GET_CODE (operand1) == HIGH |
df0651dc | 1821 | && !symbolic_operand (XEXP (operand1, 0), VOIDmode)) |
87ad11b0 | 1822 | /* Only `general_operands' can come here, so MEM is ok. */ |
1823 | || GET_CODE (operand1) == MEM) | |
1824 | { | |
dbd3d89d | 1825 | /* Various sets are created during RTL generation which don't |
1826 | have the REG_POINTER flag correctly set. After the CSE pass, | |
1827 | instruction recognition can fail if we don't consistently | |
1828 | set this flag when performing register copies. This should | |
1829 | also improve the opportunities for creating insns that use | |
1830 | unscaled indexing. */ | |
1831 | if (REG_P (operand0) && REG_P (operand1)) | |
1832 | { | |
1833 | if (REG_POINTER (operand1) | |
1834 | && !REG_POINTER (operand0) | |
1835 | && !HARD_REGISTER_P (operand0)) | |
1836 | copy_reg_pointer (operand0, operand1); | |
dbd3d89d | 1837 | } |
1838 | ||
1839 | /* When MEMs are broken out, the REG_POINTER flag doesn't | |
1840 | get set. In some cases, we can set the REG_POINTER flag | |
1841 | from the declaration for the MEM. */ | |
1842 | if (REG_P (operand0) | |
1843 | && GET_CODE (operand1) == MEM | |
1844 | && !REG_POINTER (operand0)) | |
1845 | { | |
1846 | tree decl = MEM_EXPR (operand1); | |
1847 | ||
1848 | /* Set the register pointer flag and register alignment | |
1849 | if the declaration for this memory reference is a | |
4d41e927 | 1850 | pointer type. */ |
1851 | if (decl) | |
dbd3d89d | 1852 | { |
1853 | tree type; | |
1854 | ||
1855 | /* If this is a COMPONENT_REF, use the FIELD_DECL from | |
1856 | tree operand 1. */ | |
1857 | if (TREE_CODE (decl) == COMPONENT_REF) | |
1858 | decl = TREE_OPERAND (decl, 1); | |
1859 | ||
1860 | type = TREE_TYPE (decl); | |
eec9c06d | 1861 | type = strip_array_types (type); |
dbd3d89d | 1862 | |
1863 | if (POINTER_TYPE_P (type)) | |
1864 | { | |
1865 | int align; | |
1866 | ||
1867 | type = TREE_TYPE (type); | |
1868 | /* Using TYPE_ALIGN_OK is rather conservative as | |
1869 | only the ada frontend actually sets it. */ | |
1870 | align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type) | |
1871 | : BITS_PER_UNIT); | |
1872 | mark_reg_pointer (operand0, align); | |
1873 | } | |
1874 | } | |
1875 | } | |
1876 | ||
ad851752 | 1877 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1878 | return 1; |
1879 | } | |
1880 | } | |
1881 | else if (GET_CODE (operand0) == MEM) | |
1882 | { | |
85eb4c6e | 1883 | if (mode == DFmode && operand1 == CONST0_RTX (mode) |
1884 | && !(reload_in_progress || reload_completed)) | |
1885 | { | |
1886 | rtx temp = gen_reg_rtx (DFmode); | |
1887 | ||
ad851752 | 1888 | emit_insn (gen_rtx_SET (VOIDmode, temp, operand1)); |
1889 | emit_insn (gen_rtx_SET (VOIDmode, operand0, temp)); | |
85eb4c6e | 1890 | return 1; |
1891 | } | |
891b55b4 | 1892 | if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1893 | { |
1894 | /* Run this case quickly. */ | |
ad851752 | 1895 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1896 | return 1; |
1897 | } | |
2ff4bf8d | 1898 | if (! (reload_in_progress || reload_completed)) |
87ad11b0 | 1899 | { |
1900 | operands[0] = validize_mem (operand0); | |
1901 | operands[1] = operand1 = force_reg (mode, operand1); | |
1902 | } | |
1903 | } | |
1904 | ||
37a75d53 | 1905 | /* Simplify the source if we need to. |
1906 | Note we do have to handle function labels here, even though we do | |
1907 | not consider them legitimate constants. Loop optimizations can | |
bea60f66 | 1908 | call the emit_move_xxx with one as a source. */ |
57ed30e5 | 1909 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) |
39ec41d4 | 1910 | || function_label_operand (operand1, VOIDmode) |
2ee034bc | 1911 | || (GET_CODE (operand1) == HIGH |
63882853 | 1912 | && symbolic_operand (XEXP (operand1, 0), mode))) |
87ad11b0 | 1913 | { |
2ee034bc | 1914 | int ishighonly = 0; |
1915 | ||
1916 | if (GET_CODE (operand1) == HIGH) | |
1917 | { | |
1918 | ishighonly = 1; | |
1919 | operand1 = XEXP (operand1, 0); | |
1920 | } | |
87ad11b0 | 1921 | if (symbolic_operand (operand1, mode)) |
1922 | { | |
005a7dd0 | 1923 | /* Argh. The assembler and linker can't handle arithmetic |
81653f9b | 1924 | involving plabels. |
005a7dd0 | 1925 | |
81653f9b | 1926 | So we force the plabel into memory, load operand0 from |
1927 | the memory location, then add in the constant part. */ | |
37a75d53 | 1928 | if ((GET_CODE (operand1) == CONST |
1929 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
39ec41d4 | 1930 | && function_label_operand (XEXP (XEXP (operand1, 0), 0), |
1931 | VOIDmode)) | |
1932 | || function_label_operand (operand1, VOIDmode)) | |
005a7dd0 | 1933 | { |
b3d569a0 | 1934 | rtx temp, const_part; |
81653f9b | 1935 | |
1936 | /* Figure out what (if any) scratch register to use. */ | |
1937 | if (reload_in_progress || reload_completed) | |
f756078b | 1938 | { |
1939 | scratch_reg = scratch_reg ? scratch_reg : operand0; | |
1940 | /* SCRATCH_REG will hold an address and maybe the actual | |
1941 | data. We want it in WORD_MODE regardless of what mode it | |
1942 | was originally given to us. */ | |
9840d99d | 1943 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1944 | } |
81653f9b | 1945 | else if (flag_pic) |
1946 | scratch_reg = gen_reg_rtx (Pmode); | |
1947 | ||
37a75d53 | 1948 | if (GET_CODE (operand1) == CONST) |
1949 | { | |
1950 | /* Save away the constant part of the expression. */ | |
1951 | const_part = XEXP (XEXP (operand1, 0), 1); | |
ecf2283d | 1952 | gcc_assert (GET_CODE (const_part) == CONST_INT); |
37a75d53 | 1953 | |
1954 | /* Force the function label into memory. */ | |
1955 | temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0)); | |
1956 | } | |
1957 | else | |
1958 | { | |
1959 | /* No constant part. */ | |
1960 | const_part = NULL_RTX; | |
005a7dd0 | 1961 | |
37a75d53 | 1962 | /* Force the function label into memory. */ |
1963 | temp = force_const_mem (mode, operand1); | |
1964 | } | |
9840d99d | 1965 | |
81653f9b | 1966 | |
1967 | /* Get the address of the memory location. PIC-ify it if | |
1968 | necessary. */ | |
1969 | temp = XEXP (temp, 0); | |
1970 | if (flag_pic) | |
1971 | temp = legitimize_pic_address (temp, mode, scratch_reg); | |
1972 | ||
1973 | /* Put the address of the memory location into our destination | |
1974 | register. */ | |
1975 | operands[1] = temp; | |
e202682d | 1976 | pa_emit_move_sequence (operands, mode, scratch_reg); |
81653f9b | 1977 | |
1978 | /* Now load from the memory location into our destination | |
1979 | register. */ | |
ad851752 | 1980 | operands[1] = gen_rtx_MEM (Pmode, operands[0]); |
e202682d | 1981 | pa_emit_move_sequence (operands, mode, scratch_reg); |
81653f9b | 1982 | |
1983 | /* And add back in the constant part. */ | |
37a75d53 | 1984 | if (const_part != NULL_RTX) |
1985 | expand_inc (operand0, const_part); | |
81653f9b | 1986 | |
1987 | return 1; | |
005a7dd0 | 1988 | } |
1989 | ||
87ad11b0 | 1990 | if (flag_pic) |
1991 | { | |
2ff4bf8d | 1992 | rtx temp; |
1993 | ||
1994 | if (reload_in_progress || reload_completed) | |
f756078b | 1995 | { |
1996 | temp = scratch_reg ? scratch_reg : operand0; | |
1997 | /* TEMP will hold an address and maybe the actual | |
1998 | data. We want it in WORD_MODE regardless of what mode it | |
1999 | was originally given to us. */ | |
9840d99d | 2000 | temp = force_mode (word_mode, temp); |
f756078b | 2001 | } |
2ff4bf8d | 2002 | else |
2003 | temp = gen_reg_rtx (Pmode); | |
6d36483b | 2004 | |
81653f9b | 2005 | /* (const (plus (symbol) (const_int))) must be forced to |
2006 | memory during/after reload if the const_int will not fit | |
2007 | in 14 bits. */ | |
2008 | if (GET_CODE (operand1) == CONST | |
96b86ab6 | 2009 | && GET_CODE (XEXP (operand1, 0)) == PLUS |
2010 | && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT | |
2011 | && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)) | |
2012 | && (reload_completed || reload_in_progress) | |
2013 | && flag_pic) | |
2014 | { | |
ed498904 | 2015 | rtx const_mem = force_const_mem (mode, operand1); |
4109fd6d | 2016 | operands[1] = legitimize_pic_address (XEXP (const_mem, 0), |
96b86ab6 | 2017 | mode, temp); |
ed498904 | 2018 | operands[1] = replace_equiv_address (const_mem, operands[1]); |
e202682d | 2019 | pa_emit_move_sequence (operands, mode, temp); |
96b86ab6 | 2020 | } |
005a7dd0 | 2021 | else |
2022 | { | |
2023 | operands[1] = legitimize_pic_address (operand1, mode, temp); | |
dbd3d89d | 2024 | if (REG_P (operand0) && REG_P (operands[1])) |
2025 | copy_reg_pointer (operand0, operands[1]); | |
ad851752 | 2026 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1])); |
005a7dd0 | 2027 | } |
87ad11b0 | 2028 | } |
b4a7bf10 | 2029 | /* On the HPPA, references to data space are supposed to use dp, |
2030 | register 27, but showing it in the RTL inhibits various cse | |
2031 | and loop optimizations. */ | |
6d36483b | 2032 | else |
87ad11b0 | 2033 | { |
005a7dd0 | 2034 | rtx temp, set; |
2ee034bc | 2035 | |
6d36483b | 2036 | if (reload_in_progress || reload_completed) |
f756078b | 2037 | { |
2038 | temp = scratch_reg ? scratch_reg : operand0; | |
2039 | /* TEMP will hold an address and maybe the actual | |
2040 | data. We want it in WORD_MODE regardless of what mode it | |
2041 | was originally given to us. */ | |
9840d99d | 2042 | temp = force_mode (word_mode, temp); |
f756078b | 2043 | } |
2ee034bc | 2044 | else |
2045 | temp = gen_reg_rtx (mode); | |
2046 | ||
42819d4e | 2047 | /* Loading a SYMBOL_REF into a register makes that register |
9840d99d | 2048 | safe to be used as the base in an indexed address. |
42819d4e | 2049 | |
2050 | Don't mark hard registers though. That loses. */ | |
47a61b79 | 2051 | if (GET_CODE (operand0) == REG |
2052 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
dbd3d89d | 2053 | mark_reg_pointer (operand0, BITS_PER_UNIT); |
42819d4e | 2054 | if (REGNO (temp) >= FIRST_PSEUDO_REGISTER) |
dbd3d89d | 2055 | mark_reg_pointer (temp, BITS_PER_UNIT); |
2056 | ||
2ee034bc | 2057 | if (ishighonly) |
ad851752 | 2058 | set = gen_rtx_SET (mode, operand0, temp); |
2ee034bc | 2059 | else |
7014838c | 2060 | set = gen_rtx_SET (VOIDmode, |
2061 | operand0, | |
ad851752 | 2062 | gen_rtx_LO_SUM (mode, temp, operand1)); |
6d36483b | 2063 | |
ad851752 | 2064 | emit_insn (gen_rtx_SET (VOIDmode, |
2065 | temp, | |
2066 | gen_rtx_HIGH (mode, operand1))); | |
d2498717 | 2067 | emit_insn (set); |
166bf021 | 2068 | |
87ad11b0 | 2069 | } |
2ee034bc | 2070 | return 1; |
87ad11b0 | 2071 | } |
716b2c5a | 2072 | else if (pa_tls_referenced_p (operand1)) |
2073 | { | |
2074 | rtx tmp = operand1; | |
2075 | rtx addend = NULL; | |
2076 | ||
2077 | if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS) | |
2078 | { | |
2079 | addend = XEXP (XEXP (tmp, 0), 1); | |
2080 | tmp = XEXP (XEXP (tmp, 0), 0); | |
2081 | } | |
2082 | ||
2083 | gcc_assert (GET_CODE (tmp) == SYMBOL_REF); | |
2084 | tmp = legitimize_tls_address (tmp); | |
2085 | if (addend) | |
2086 | { | |
2087 | tmp = gen_rtx_PLUS (mode, tmp, addend); | |
2088 | tmp = force_operand (tmp, operands[0]); | |
2089 | } | |
2090 | operands[1] = tmp; | |
2091 | } | |
42faba01 | 2092 | else if (GET_CODE (operand1) != CONST_INT |
e202682d | 2093 | || !pa_cint_ok_for_move (INTVAL (operand1))) |
87ad11b0 | 2094 | { |
6bcdc1fb | 2095 | rtx insn, temp; |
2096 | rtx op1 = operand1; | |
6edde44b | 2097 | HOST_WIDE_INT value = 0; |
6bcdc1fb | 2098 | HOST_WIDE_INT insv = 0; |
2099 | int insert = 0; | |
2100 | ||
6edde44b | 2101 | if (GET_CODE (operand1) == CONST_INT) |
2102 | value = INTVAL (operand1); | |
2103 | ||
6bcdc1fb | 2104 | if (TARGET_64BIT |
2105 | && GET_CODE (operand1) == CONST_INT | |
b7d86581 | 2106 | && HOST_BITS_PER_WIDE_INT > 32 |
5e3c5739 | 2107 | && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32) |
2108 | { | |
b7d86581 | 2109 | HOST_WIDE_INT nval; |
5e3c5739 | 2110 | |
93f6e1c7 | 2111 | /* Extract the low order 32 bits of the value and sign extend. |
2112 | If the new value is the same as the original value, we can | |
2113 | can use the original value as-is. If the new value is | |
2114 | different, we use it and insert the most-significant 32-bits | |
2115 | of the original value into the final result. */ | |
6bcdc1fb | 2116 | nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1)) |
b7d86581 | 2117 | ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31); |
6bcdc1fb | 2118 | if (value != nval) |
5e3c5739 | 2119 | { |
93f6e1c7 | 2120 | #if HOST_BITS_PER_WIDE_INT > 32 |
6bcdc1fb | 2121 | insv = value >= 0 ? value >> 32 : ~(~value >> 32); |
93f6e1c7 | 2122 | #endif |
6bcdc1fb | 2123 | insert = 1; |
2124 | value = nval; | |
5e3c5739 | 2125 | operand1 = GEN_INT (nval); |
2126 | } | |
2127 | } | |
2ff4bf8d | 2128 | |
2129 | if (reload_in_progress || reload_completed) | |
6bcdc1fb | 2130 | temp = scratch_reg ? scratch_reg : operand0; |
2ff4bf8d | 2131 | else |
2132 | temp = gen_reg_rtx (mode); | |
2133 | ||
7c4d3047 | 2134 | /* We don't directly split DImode constants on 32-bit targets |
2135 | because PLUS uses an 11-bit immediate and the insn sequence | |
2136 | generated is not as efficient as the one using HIGH/LO_SUM. */ | |
2137 | if (GET_CODE (operand1) == CONST_INT | |
58cac6ba | 2138 | && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD |
6bcdc1fb | 2139 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
2140 | && !insert) | |
93f6e1c7 | 2141 | { |
7c4d3047 | 2142 | /* Directly break constant into high and low parts. This |
93f6e1c7 | 2143 | provides better optimization opportunities because various |
2144 | passes recognize constants split with PLUS but not LO_SUM. | |
2145 | We use a 14-bit signed low part except when the addition | |
2146 | of 0x4000 to the high part might change the sign of the | |
2147 | high part. */ | |
93f6e1c7 | 2148 | HOST_WIDE_INT low = value & 0x3fff; |
2149 | HOST_WIDE_INT high = value & ~ 0x3fff; | |
2150 | ||
2151 | if (low >= 0x2000) | |
2152 | { | |
2153 | if (high == 0x7fffc000 || (mode == HImode && high == 0x4000)) | |
2154 | high += 0x2000; | |
2155 | else | |
2156 | high += 0x4000; | |
2157 | } | |
2158 | ||
2159 | low = value - high; | |
5e3c5739 | 2160 | |
93f6e1c7 | 2161 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high))); |
2162 | operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low)); | |
2163 | } | |
2164 | else | |
5e3c5739 | 2165 | { |
93f6e1c7 | 2166 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
2167 | gen_rtx_HIGH (mode, operand1))); | |
2168 | operands[1] = gen_rtx_LO_SUM (mode, temp, operand1); | |
5e3c5739 | 2169 | } |
9840d99d | 2170 | |
6bcdc1fb | 2171 | insn = emit_move_insn (operands[0], operands[1]); |
2172 | ||
2173 | /* Now insert the most significant 32 bits of the value | |
2174 | into the register. When we don't have a second register | |
2175 | available, it could take up to nine instructions to load | |
2176 | a 64-bit integer constant. Prior to reload, we force | |
2177 | constants that would take more than three instructions | |
2178 | to load to the constant pool. During and after reload, | |
2179 | we have to handle all possible values. */ | |
2180 | if (insert) | |
2181 | { | |
2182 | /* Use a HIGH/LO_SUM/INSV sequence if we have a second | |
2183 | register and the value to be inserted is outside the | |
2184 | range that can be loaded with three depdi instructions. */ | |
2185 | if (temp != operand0 && (insv >= 16384 || insv < -16384)) | |
2186 | { | |
2187 | operand1 = GEN_INT (insv); | |
2188 | ||
2189 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
2190 | gen_rtx_HIGH (mode, operand1))); | |
2191 | emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1)); | |
2192 | emit_insn (gen_insv (operand0, GEN_INT (32), | |
2193 | const0_rtx, temp)); | |
2194 | } | |
2195 | else | |
2196 | { | |
2197 | int len = 5, pos = 27; | |
2198 | ||
2199 | /* Insert the bits using the depdi instruction. */ | |
2200 | while (pos >= 0) | |
2201 | { | |
2202 | HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16; | |
2203 | HOST_WIDE_INT sign = v5 < 0; | |
2204 | ||
2205 | /* Left extend the insertion. */ | |
2206 | insv = (insv >= 0 ? insv >> len : ~(~insv >> len)); | |
2207 | while (pos > 0 && (insv & 1) == sign) | |
2208 | { | |
2209 | insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1)); | |
2210 | len += 1; | |
2211 | pos -= 1; | |
2212 | } | |
2213 | ||
2214 | emit_insn (gen_insv (operand0, GEN_INT (len), | |
2215 | GEN_INT (pos), GEN_INT (v5))); | |
2216 | ||
2217 | len = pos > 0 && pos < 5 ? pos : 5; | |
2218 | pos -= len; | |
2219 | } | |
2220 | } | |
2221 | } | |
93f6e1c7 | 2222 | |
24153880 | 2223 | set_unique_reg_note (insn, REG_EQUAL, op1); |
93f6e1c7 | 2224 | |
5e3c5739 | 2225 | return 1; |
87ad11b0 | 2226 | } |
2227 | } | |
2228 | /* Now have insn-emit do whatever it normally does. */ | |
2229 | return 0; | |
2230 | } | |
2231 | ||
1946138e | 2232 | /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning |
bd49d362 | 2233 | it will need a link/runtime reloc). */ |
1946138e | 2234 | |
2235 | int | |
e202682d | 2236 | pa_reloc_needed (tree exp) |
1946138e | 2237 | { |
2238 | int reloc = 0; | |
2239 | ||
2240 | switch (TREE_CODE (exp)) | |
2241 | { | |
2242 | case ADDR_EXPR: | |
2243 | return 1; | |
2244 | ||
0de36bdb | 2245 | case POINTER_PLUS_EXPR: |
1946138e | 2246 | case PLUS_EXPR: |
2247 | case MINUS_EXPR: | |
e202682d | 2248 | reloc = pa_reloc_needed (TREE_OPERAND (exp, 0)); |
2249 | reloc |= pa_reloc_needed (TREE_OPERAND (exp, 1)); | |
1946138e | 2250 | break; |
2251 | ||
72dd6141 | 2252 | CASE_CONVERT: |
1946138e | 2253 | case NON_LVALUE_EXPR: |
e202682d | 2254 | reloc = pa_reloc_needed (TREE_OPERAND (exp, 0)); |
1946138e | 2255 | break; |
2256 | ||
2257 | case CONSTRUCTOR: | |
2258 | { | |
729d4a82 | 2259 | tree value; |
2260 | unsigned HOST_WIDE_INT ix; | |
2261 | ||
2262 | FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value) | |
2263 | if (value) | |
e202682d | 2264 | reloc |= pa_reloc_needed (value); |
1946138e | 2265 | } |
2266 | break; | |
2267 | ||
2268 | case ERROR_MARK: | |
2269 | break; | |
7d27e4c9 | 2270 | |
2271 | default: | |
2272 | break; | |
1946138e | 2273 | } |
2274 | return reloc; | |
2275 | } | |
2276 | ||
87ad11b0 | 2277 | \f |
2278 | /* Return the best assembler insn template | |
5aedf60c | 2279 | for moving operands[1] into operands[0] as a fullword. */ |
611a88e1 | 2280 | const char * |
e202682d | 2281 | pa_singlemove_string (rtx *operands) |
87ad11b0 | 2282 | { |
3745c59b | 2283 | HOST_WIDE_INT intval; |
2284 | ||
87ad11b0 | 2285 | if (GET_CODE (operands[0]) == MEM) |
2286 | return "stw %r1,%0"; | |
3745c59b | 2287 | if (GET_CODE (operands[1]) == MEM) |
87ad11b0 | 2288 | return "ldw %1,%0"; |
3745c59b | 2289 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
9d5108ea | 2290 | { |
3745c59b | 2291 | long i; |
2292 | REAL_VALUE_TYPE d; | |
9d5108ea | 2293 | |
ecf2283d | 2294 | gcc_assert (GET_MODE (operands[1]) == SFmode); |
9d5108ea | 2295 | |
3745c59b | 2296 | /* Translate the CONST_DOUBLE to a CONST_INT with the same target |
2297 | bit pattern. */ | |
2298 | REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]); | |
2299 | REAL_VALUE_TO_TARGET_SINGLE (d, i); | |
9d5108ea | 2300 | |
3745c59b | 2301 | operands[1] = GEN_INT (i); |
2302 | /* Fall through to CONST_INT case. */ | |
2303 | } | |
2304 | if (GET_CODE (operands[1]) == CONST_INT) | |
9d5108ea | 2305 | { |
3745c59b | 2306 | intval = INTVAL (operands[1]); |
2307 | ||
2308 | if (VAL_14_BITS_P (intval)) | |
2309 | return "ldi %1,%0"; | |
2310 | else if ((intval & 0x7ff) == 0) | |
2311 | return "ldil L'%1,%0"; | |
e202682d | 2312 | else if (pa_zdepi_cint_p (intval)) |
e4065f95 | 2313 | return "{zdepi %Z1,%0|depwi,z %Z1,%0}"; |
9d5108ea | 2314 | else |
2315 | return "ldil L'%1,%0\n\tldo R'%1(%0),%0"; | |
2316 | } | |
87ad11b0 | 2317 | return "copy %1,%0"; |
2318 | } | |
2319 | \f | |
2320 | ||
201f01e9 | 2321 | /* Compute position (in OP[1]) and width (in OP[2]) |
2322 | useful for copying IMM to a register using the zdepi | |
2323 | instructions. Store the immediate value to insert in OP[0]. */ | |
611a88e1 | 2324 | static void |
5c1d8983 | 2325 | compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
7e10ba53 | 2326 | { |
e057641f | 2327 | int lsb, len; |
7e10ba53 | 2328 | |
e057641f | 2329 | /* Find the least significant set bit in IMM. */ |
2330 | for (lsb = 0; lsb < 32; lsb++) | |
7e10ba53 | 2331 | { |
e057641f | 2332 | if ((imm & 1) != 0) |
7e10ba53 | 2333 | break; |
e057641f | 2334 | imm >>= 1; |
7e10ba53 | 2335 | } |
2336 | ||
e057641f | 2337 | /* Choose variants based on *sign* of the 5-bit field. */ |
2338 | if ((imm & 0x10) == 0) | |
2339 | len = (lsb <= 28) ? 4 : 32 - lsb; | |
7e10ba53 | 2340 | else |
2341 | { | |
e057641f | 2342 | /* Find the width of the bitstring in IMM. */ |
eab96f1c | 2343 | for (len = 5; len < 32 - lsb; len++) |
7e10ba53 | 2344 | { |
eab96f1c | 2345 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
7e10ba53 | 2346 | break; |
7e10ba53 | 2347 | } |
2348 | ||
e057641f | 2349 | /* Sign extend IMM as a 5-bit value. */ |
2350 | imm = (imm & 0xf) - 0x10; | |
7e10ba53 | 2351 | } |
2352 | ||
42faba01 | 2353 | op[0] = imm; |
2354 | op[1] = 31 - lsb; | |
2355 | op[2] = len; | |
7e10ba53 | 2356 | } |
2357 | ||
5e3c5739 | 2358 | /* Compute position (in OP[1]) and width (in OP[2]) |
2359 | useful for copying IMM to a register using the depdi,z | |
2360 | instructions. Store the immediate value to insert in OP[0]. */ | |
e202682d | 2361 | |
2362 | static void | |
5c1d8983 | 2363 | compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
5e3c5739 | 2364 | { |
eab96f1c | 2365 | int lsb, len, maxlen; |
2366 | ||
2367 | maxlen = MIN (HOST_BITS_PER_WIDE_INT, 64); | |
5e3c5739 | 2368 | |
2369 | /* Find the least significant set bit in IMM. */ | |
eab96f1c | 2370 | for (lsb = 0; lsb < maxlen; lsb++) |
5e3c5739 | 2371 | { |
2372 | if ((imm & 1) != 0) | |
2373 | break; | |
2374 | imm >>= 1; | |
2375 | } | |
2376 | ||
2377 | /* Choose variants based on *sign* of the 5-bit field. */ | |
2378 | if ((imm & 0x10) == 0) | |
eab96f1c | 2379 | len = (lsb <= maxlen - 4) ? 4 : maxlen - lsb; |
5e3c5739 | 2380 | else |
2381 | { | |
2382 | /* Find the width of the bitstring in IMM. */ | |
eab96f1c | 2383 | for (len = 5; len < maxlen - lsb; len++) |
5e3c5739 | 2384 | { |
ea52c577 | 2385 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
5e3c5739 | 2386 | break; |
2387 | } | |
2388 | ||
eab96f1c | 2389 | /* Extend length if host is narrow and IMM is negative. */ |
2390 | if (HOST_BITS_PER_WIDE_INT == 32 && len == maxlen - lsb) | |
2391 | len += 32; | |
2392 | ||
5e3c5739 | 2393 | /* Sign extend IMM as a 5-bit value. */ |
2394 | imm = (imm & 0xf) - 0x10; | |
2395 | } | |
2396 | ||
2397 | op[0] = imm; | |
2398 | op[1] = 63 - lsb; | |
2399 | op[2] = len; | |
2400 | } | |
2401 | ||
87ad11b0 | 2402 | /* Output assembler code to perform a doubleword move insn |
2403 | with operands OPERANDS. */ | |
2404 | ||
611a88e1 | 2405 | const char * |
e202682d | 2406 | pa_output_move_double (rtx *operands) |
87ad11b0 | 2407 | { |
2408 | enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1; | |
2409 | rtx latehalf[2]; | |
2410 | rtx addreg0 = 0, addreg1 = 0; | |
2411 | ||
2412 | /* First classify both operands. */ | |
2413 | ||
2414 | if (REG_P (operands[0])) | |
2415 | optype0 = REGOP; | |
2416 | else if (offsettable_memref_p (operands[0])) | |
2417 | optype0 = OFFSOP; | |
2418 | else if (GET_CODE (operands[0]) == MEM) | |
2419 | optype0 = MEMOP; | |
2420 | else | |
2421 | optype0 = RNDOP; | |
2422 | ||
2423 | if (REG_P (operands[1])) | |
2424 | optype1 = REGOP; | |
2425 | else if (CONSTANT_P (operands[1])) | |
2426 | optype1 = CNSTOP; | |
2427 | else if (offsettable_memref_p (operands[1])) | |
2428 | optype1 = OFFSOP; | |
2429 | else if (GET_CODE (operands[1]) == MEM) | |
2430 | optype1 = MEMOP; | |
2431 | else | |
2432 | optype1 = RNDOP; | |
2433 | ||
2434 | /* Check for the cases that the operand constraints are not | |
ecf2283d | 2435 | supposed to allow to happen. */ |
2436 | gcc_assert (optype0 == REGOP || optype1 == REGOP); | |
87ad11b0 | 2437 | |
e106b699 | 2438 | /* Handle copies between general and floating registers. */ |
2439 | ||
2440 | if (optype0 == REGOP && optype1 == REGOP | |
2441 | && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])) | |
2442 | { | |
2443 | if (FP_REG_P (operands[0])) | |
2444 | { | |
2445 | output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands); | |
2446 | output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands); | |
2447 | return "{fldds|fldd} -16(%%sp),%0"; | |
2448 | } | |
2449 | else | |
2450 | { | |
2451 | output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands); | |
2452 | output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands); | |
2453 | return "{ldws|ldw} -12(%%sp),%R0"; | |
2454 | } | |
2455 | } | |
2456 | ||
87ad11b0 | 2457 | /* Handle auto decrementing and incrementing loads and stores |
2458 | specifically, since the structure of the function doesn't work | |
2459 | for them without major modification. Do it better when we learn | |
2460 | this port about the general inc/dec addressing of PA. | |
2461 | (This was written by tege. Chide him if it doesn't work.) */ | |
2462 | ||
2463 | if (optype0 == MEMOP) | |
2464 | { | |
1df0058a | 2465 | /* We have to output the address syntax ourselves, since print_operand |
2466 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2467 | ||
87ad11b0 | 2468 | rtx addr = XEXP (operands[0], 0); |
1df0058a | 2469 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) |
87ad11b0 | 2470 | { |
ad851752 | 2471 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2472 | |
2473 | operands[0] = XEXP (addr, 0); | |
ecf2283d | 2474 | gcc_assert (GET_CODE (operands[1]) == REG |
2475 | && GET_CODE (operands[0]) == REG); | |
1df0058a | 2476 | |
ecf2283d | 2477 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); |
2478 | ||
2479 | /* No overlap between high target register and address | |
2480 | register. (We do this in a non-obvious way to | |
2481 | save a register file writeback) */ | |
2482 | if (GET_CODE (addr) == POST_INC) | |
2483 | return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)"; | |
2484 | return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)"; | |
a3217f65 | 2485 | } |
1df0058a | 2486 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) |
a3217f65 | 2487 | { |
ad851752 | 2488 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2489 | |
2490 | operands[0] = XEXP (addr, 0); | |
ecf2283d | 2491 | gcc_assert (GET_CODE (operands[1]) == REG |
2492 | && GET_CODE (operands[0]) == REG); | |
2493 | ||
2494 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); | |
2495 | /* No overlap between high target register and address | |
2496 | register. (We do this in a non-obvious way to save a | |
2497 | register file writeback) */ | |
2498 | if (GET_CODE (addr) == PRE_INC) | |
2499 | return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)"; | |
2500 | return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)"; | |
87ad11b0 | 2501 | } |
2502 | } | |
2503 | if (optype1 == MEMOP) | |
2504 | { | |
2505 | /* We have to output the address syntax ourselves, since print_operand | |
2506 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2507 | ||
2508 | rtx addr = XEXP (operands[1], 0); | |
2509 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) | |
2510 | { | |
ad851752 | 2511 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2512 | |
2513 | operands[1] = XEXP (addr, 0); | |
ecf2283d | 2514 | gcc_assert (GET_CODE (operands[0]) == REG |
2515 | && GET_CODE (operands[1]) == REG); | |
87ad11b0 | 2516 | |
2517 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2518 | { | |
2519 | /* No overlap between high target register and address | |
3857fa62 | 2520 | register. (We do this in a non-obvious way to |
87ad11b0 | 2521 | save a register file writeback) */ |
2522 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2523 | return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0"; |
01fd4b49 | 2524 | return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0"; |
87ad11b0 | 2525 | } |
2526 | else | |
2527 | { | |
2528 | /* This is an undefined situation. We should load into the | |
2529 | address register *and* update that register. Probably | |
2530 | we don't need to handle this at all. */ | |
2531 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2532 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0"; |
2533 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0"; | |
87ad11b0 | 2534 | } |
2535 | } | |
2536 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) | |
2537 | { | |
ad851752 | 2538 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2539 | |
2540 | operands[1] = XEXP (addr, 0); | |
ecf2283d | 2541 | gcc_assert (GET_CODE (operands[0]) == REG |
2542 | && GET_CODE (operands[1]) == REG); | |
87ad11b0 | 2543 | |
2544 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2545 | { | |
2546 | /* No overlap between high target register and address | |
3857fa62 | 2547 | register. (We do this in a non-obvious way to |
87ad11b0 | 2548 | save a register file writeback) */ |
2549 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2550 | return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0"; |
2551 | return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0"; | |
87ad11b0 | 2552 | } |
2553 | else | |
2554 | { | |
2555 | /* This is an undefined situation. We should load into the | |
2556 | address register *and* update that register. Probably | |
2557 | we don't need to handle this at all. */ | |
2558 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2559 | return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0"; |
2560 | return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0"; | |
87ad11b0 | 2561 | } |
2562 | } | |
12b02046 | 2563 | else if (GET_CODE (addr) == PLUS |
2564 | && GET_CODE (XEXP (addr, 0)) == MULT) | |
2565 | { | |
b2f8bd14 | 2566 | rtx xoperands[4]; |
ad851752 | 2567 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
12b02046 | 2568 | |
2569 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2570 | { | |
12b02046 | 2571 | xoperands[0] = high_reg; |
2572 | xoperands[1] = XEXP (addr, 1); | |
2573 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2574 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2575 | output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}", |
2576 | xoperands); | |
34940871 | 2577 | return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; |
12b02046 | 2578 | } |
2579 | else | |
2580 | { | |
12b02046 | 2581 | xoperands[0] = high_reg; |
2582 | xoperands[1] = XEXP (addr, 1); | |
2583 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2584 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2585 | output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}", |
2586 | xoperands); | |
34940871 | 2587 | return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0"; |
12b02046 | 2588 | } |
12b02046 | 2589 | } |
87ad11b0 | 2590 | } |
2591 | ||
2592 | /* If an operand is an unoffsettable memory ref, find a register | |
2593 | we can increment temporarily to make it refer to the second word. */ | |
2594 | ||
2595 | if (optype0 == MEMOP) | |
2596 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2597 | ||
2598 | if (optype1 == MEMOP) | |
2599 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2600 | ||
2601 | /* Ok, we can do one word at a time. | |
2602 | Normally we do the low-numbered word first. | |
2603 | ||
2604 | In either case, set up in LATEHALF the operands to use | |
2605 | for the high-numbered word and in some cases alter the | |
2606 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2607 | ||
2608 | if (optype0 == REGOP) | |
ad851752 | 2609 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
87ad11b0 | 2610 | else if (optype0 == OFFSOP) |
eafc6604 | 2611 | latehalf[0] = adjust_address (operands[0], SImode, 4); |
87ad11b0 | 2612 | else |
2613 | latehalf[0] = operands[0]; | |
2614 | ||
2615 | if (optype1 == REGOP) | |
ad851752 | 2616 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
87ad11b0 | 2617 | else if (optype1 == OFFSOP) |
eafc6604 | 2618 | latehalf[1] = adjust_address (operands[1], SImode, 4); |
87ad11b0 | 2619 | else if (optype1 == CNSTOP) |
2620 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2621 | else | |
2622 | latehalf[1] = operands[1]; | |
2623 | ||
2624 | /* If the first move would clobber the source of the second one, | |
2625 | do them in the other order. | |
2626 | ||
cf489d53 | 2627 | This can happen in two cases: |
87ad11b0 | 2628 | |
cf489d53 | 2629 | mem -> register where the first half of the destination register |
2630 | is the same register used in the memory's address. Reload | |
2631 | can create such insns. | |
87ad11b0 | 2632 | |
cf489d53 | 2633 | mem in this case will be either register indirect or register |
9840d99d | 2634 | indirect plus a valid offset. |
cf489d53 | 2635 | |
2636 | register -> register move where REGNO(dst) == REGNO(src + 1) | |
9840d99d | 2637 | someone (Tim/Tege?) claimed this can happen for parameter loads. |
cf489d53 | 2638 | |
2639 | Handle mem -> register case first. */ | |
2640 | if (optype0 == REGOP | |
2641 | && (optype1 == MEMOP || optype1 == OFFSOP) | |
2642 | && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2643 | operands[1], 0)) | |
87ad11b0 | 2644 | { |
87ad11b0 | 2645 | /* Do the late half first. */ |
2646 | if (addreg1) | |
6a5d085a | 2647 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
e202682d | 2648 | output_asm_insn (pa_singlemove_string (latehalf), latehalf); |
cf489d53 | 2649 | |
2650 | /* Then clobber. */ | |
87ad11b0 | 2651 | if (addreg1) |
6a5d085a | 2652 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
e202682d | 2653 | return pa_singlemove_string (operands); |
87ad11b0 | 2654 | } |
2655 | ||
cf489d53 | 2656 | /* Now handle register -> register case. */ |
c4fa5937 | 2657 | if (optype0 == REGOP && optype1 == REGOP |
2658 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
2659 | { | |
e202682d | 2660 | output_asm_insn (pa_singlemove_string (latehalf), latehalf); |
2661 | return pa_singlemove_string (operands); | |
c4fa5937 | 2662 | } |
2663 | ||
87ad11b0 | 2664 | /* Normal case: do the two words, low-numbered first. */ |
2665 | ||
e202682d | 2666 | output_asm_insn (pa_singlemove_string (operands), operands); |
87ad11b0 | 2667 | |
2668 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2669 | if (addreg0) | |
6a5d085a | 2670 | output_asm_insn ("ldo 4(%0),%0", &addreg0); |
87ad11b0 | 2671 | if (addreg1) |
6a5d085a | 2672 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2673 | |
2674 | /* Do that word. */ | |
e202682d | 2675 | output_asm_insn (pa_singlemove_string (latehalf), latehalf); |
87ad11b0 | 2676 | |
2677 | /* Undo the adds we just did. */ | |
2678 | if (addreg0) | |
6a5d085a | 2679 | output_asm_insn ("ldo -4(%0),%0", &addreg0); |
87ad11b0 | 2680 | if (addreg1) |
6a5d085a | 2681 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2682 | |
2683 | return ""; | |
2684 | } | |
2685 | \f | |
611a88e1 | 2686 | const char * |
e202682d | 2687 | pa_output_fp_move_double (rtx *operands) |
87ad11b0 | 2688 | { |
2689 | if (FP_REG_P (operands[0])) | |
2690 | { | |
6d36483b | 2691 | if (FP_REG_P (operands[1]) |
891b55b4 | 2692 | || operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
c6ae275c | 2693 | output_asm_insn ("fcpy,dbl %f1,%0", operands); |
6d36483b | 2694 | else |
27ef382d | 2695 | output_asm_insn ("fldd%F1 %1,%0", operands); |
87ad11b0 | 2696 | } |
2697 | else if (FP_REG_P (operands[1])) | |
2698 | { | |
27ef382d | 2699 | output_asm_insn ("fstd%F0 %1,%0", operands); |
87ad11b0 | 2700 | } |
ecf2283d | 2701 | else |
891b55b4 | 2702 | { |
ecf2283d | 2703 | rtx xoperands[2]; |
2704 | ||
2705 | gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0]))); | |
2706 | ||
6d36483b | 2707 | /* This is a pain. You have to be prepared to deal with an |
01cc3b75 | 2708 | arbitrary address here including pre/post increment/decrement. |
891b55b4 | 2709 | |
2710 | so avoid this in the MD. */ | |
ecf2283d | 2711 | gcc_assert (GET_CODE (operands[0]) == REG); |
2712 | ||
2713 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2714 | xoperands[0] = operands[0]; | |
2715 | output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands); | |
891b55b4 | 2716 | } |
87ad11b0 | 2717 | return ""; |
2718 | } | |
2719 | \f | |
2720 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2721 | ADDR can be effectively incremented by incrementing REG. */ | |
2722 | ||
2723 | static rtx | |
5c1d8983 | 2724 | find_addr_reg (rtx addr) |
87ad11b0 | 2725 | { |
2726 | while (GET_CODE (addr) == PLUS) | |
2727 | { | |
2728 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2729 | addr = XEXP (addr, 0); | |
2730 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2731 | addr = XEXP (addr, 1); | |
2732 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2733 | addr = XEXP (addr, 1); | |
2734 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2735 | addr = XEXP (addr, 0); | |
2736 | else | |
ecf2283d | 2737 | gcc_unreachable (); |
87ad11b0 | 2738 | } |
ecf2283d | 2739 | gcc_assert (GET_CODE (addr) == REG); |
2740 | return addr; | |
87ad11b0 | 2741 | } |
2742 | ||
87ad11b0 | 2743 | /* Emit code to perform a block move. |
2744 | ||
87ad11b0 | 2745 | OPERANDS[0] is the destination pointer as a REG, clobbered. |
2746 | OPERANDS[1] is the source pointer as a REG, clobbered. | |
42819d4e | 2747 | OPERANDS[2] is a register for temporary storage. |
87ad11b0 | 2748 | OPERANDS[3] is a register for temporary storage. |
a7e1bb24 | 2749 | OPERANDS[4] is the size as a CONST_INT |
9840d99d | 2750 | OPERANDS[5] is the alignment safe to use, as a CONST_INT. |
5aedf60c | 2751 | OPERANDS[6] is another temporary register. */ |
87ad11b0 | 2752 | |
611a88e1 | 2753 | const char * |
e202682d | 2754 | pa_output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) |
87ad11b0 | 2755 | { |
2756 | int align = INTVAL (operands[5]); | |
42819d4e | 2757 | unsigned long n_bytes = INTVAL (operands[4]); |
87ad11b0 | 2758 | |
a7e1bb24 | 2759 | /* We can't move more than a word at a time because the PA |
87ad11b0 | 2760 | has no longer integer move insns. (Could use fp mem ops?) */ |
a7e1bb24 | 2761 | if (align > (TARGET_64BIT ? 8 : 4)) |
2762 | align = (TARGET_64BIT ? 8 : 4); | |
87ad11b0 | 2763 | |
42819d4e | 2764 | /* Note that we know each loop below will execute at least twice |
2765 | (else we would have open-coded the copy). */ | |
2766 | switch (align) | |
87ad11b0 | 2767 | { |
a7e1bb24 | 2768 | case 8: |
2769 | /* Pre-adjust the loop counter. */ | |
2770 | operands[4] = GEN_INT (n_bytes - 16); | |
2771 | output_asm_insn ("ldi %4,%2", operands); | |
2772 | ||
2773 | /* Copying loop. */ | |
2774 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2775 | output_asm_insn ("ldd,ma 8(%1),%6", operands); | |
2776 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2777 | output_asm_insn ("addib,>= -16,%2,.-12", operands); | |
2778 | output_asm_insn ("std,ma %6,8(%0)", operands); | |
2779 | ||
2780 | /* Handle the residual. There could be up to 7 bytes of | |
2781 | residual to copy! */ | |
2782 | if (n_bytes % 16 != 0) | |
2783 | { | |
2784 | operands[4] = GEN_INT (n_bytes % 8); | |
2785 | if (n_bytes % 16 >= 8) | |
2786 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2787 | if (n_bytes % 8 != 0) | |
2788 | output_asm_insn ("ldd 0(%1),%6", operands); | |
2789 | if (n_bytes % 16 >= 8) | |
2790 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2791 | if (n_bytes % 8 != 0) | |
2792 | output_asm_insn ("stdby,e %6,%4(%0)", operands); | |
2793 | } | |
2794 | return ""; | |
2795 | ||
42819d4e | 2796 | case 4: |
2797 | /* Pre-adjust the loop counter. */ | |
2798 | operands[4] = GEN_INT (n_bytes - 8); | |
2799 | output_asm_insn ("ldi %4,%2", operands); | |
2800 | ||
2801 | /* Copying loop. */ | |
e4065f95 | 2802 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
2803 | output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands); | |
2804 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); | |
42819d4e | 2805 | output_asm_insn ("addib,>= -8,%2,.-12", operands); |
e4065f95 | 2806 | output_asm_insn ("{stws|stw},ma %6,4(%0)", operands); |
42819d4e | 2807 | |
2808 | /* Handle the residual. There could be up to 7 bytes of | |
2809 | residual to copy! */ | |
2810 | if (n_bytes % 8 != 0) | |
2811 | { | |
2812 | operands[4] = GEN_INT (n_bytes % 4); | |
2813 | if (n_bytes % 8 >= 4) | |
e4065f95 | 2814 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
42819d4e | 2815 | if (n_bytes % 4 != 0) |
34940871 | 2816 | output_asm_insn ("ldw 0(%1),%6", operands); |
42819d4e | 2817 | if (n_bytes % 8 >= 4) |
e4065f95 | 2818 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); |
42819d4e | 2819 | if (n_bytes % 4 != 0) |
e4065f95 | 2820 | output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands); |
42819d4e | 2821 | } |
2822 | return ""; | |
87ad11b0 | 2823 | |
42819d4e | 2824 | case 2: |
2825 | /* Pre-adjust the loop counter. */ | |
2826 | operands[4] = GEN_INT (n_bytes - 4); | |
2827 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2828 | |
42819d4e | 2829 | /* Copying loop. */ |
e4065f95 | 2830 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
2831 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands); | |
2832 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); | |
42819d4e | 2833 | output_asm_insn ("addib,>= -4,%2,.-12", operands); |
e4065f95 | 2834 | output_asm_insn ("{sths|sth},ma %6,2(%0)", operands); |
87ad11b0 | 2835 | |
42819d4e | 2836 | /* Handle the residual. */ |
2837 | if (n_bytes % 4 != 0) | |
2838 | { | |
2839 | if (n_bytes % 4 >= 2) | |
e4065f95 | 2840 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
42819d4e | 2841 | if (n_bytes % 2 != 0) |
34940871 | 2842 | output_asm_insn ("ldb 0(%1),%6", operands); |
42819d4e | 2843 | if (n_bytes % 4 >= 2) |
e4065f95 | 2844 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); |
42819d4e | 2845 | if (n_bytes % 2 != 0) |
34940871 | 2846 | output_asm_insn ("stb %6,0(%0)", operands); |
42819d4e | 2847 | } |
2848 | return ""; | |
87ad11b0 | 2849 | |
42819d4e | 2850 | case 1: |
2851 | /* Pre-adjust the loop counter. */ | |
2852 | operands[4] = GEN_INT (n_bytes - 2); | |
2853 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2854 | |
42819d4e | 2855 | /* Copying loop. */ |
e4065f95 | 2856 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands); |
2857 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands); | |
2858 | output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands); | |
42819d4e | 2859 | output_asm_insn ("addib,>= -2,%2,.-12", operands); |
e4065f95 | 2860 | output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands); |
87ad11b0 | 2861 | |
42819d4e | 2862 | /* Handle the residual. */ |
2863 | if (n_bytes % 2 != 0) | |
2864 | { | |
34940871 | 2865 | output_asm_insn ("ldb 0(%1),%3", operands); |
2866 | output_asm_insn ("stb %3,0(%0)", operands); | |
42819d4e | 2867 | } |
2868 | return ""; | |
87ad11b0 | 2869 | |
42819d4e | 2870 | default: |
ecf2283d | 2871 | gcc_unreachable (); |
87ad11b0 | 2872 | } |
87ad11b0 | 2873 | } |
58e17b0b | 2874 | |
2875 | /* Count the number of insns necessary to handle this block move. | |
2876 | ||
2877 | Basic structure is the same as emit_block_move, except that we | |
2878 | count insns rather than emit them. */ | |
2879 | ||
611a88e1 | 2880 | static int |
008c057d | 2881 | compute_movmem_length (rtx insn) |
58e17b0b | 2882 | { |
2883 | rtx pat = PATTERN (insn); | |
fc1fb057 | 2884 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0)); |
2885 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0)); | |
42819d4e | 2886 | unsigned int n_insns = 0; |
58e17b0b | 2887 | |
2888 | /* We can't move more than four bytes at a time because the PA | |
2889 | has no longer integer move insns. (Could use fp mem ops?) */ | |
a7e1bb24 | 2890 | if (align > (TARGET_64BIT ? 8 : 4)) |
2891 | align = (TARGET_64BIT ? 8 : 4); | |
58e17b0b | 2892 | |
79bfe6ae | 2893 | /* The basic copying loop. */ |
42819d4e | 2894 | n_insns = 6; |
58e17b0b | 2895 | |
42819d4e | 2896 | /* Residuals. */ |
2897 | if (n_bytes % (2 * align) != 0) | |
58e17b0b | 2898 | { |
79bfe6ae | 2899 | if ((n_bytes % (2 * align)) >= align) |
2900 | n_insns += 2; | |
2901 | ||
2902 | if ((n_bytes % align) != 0) | |
2903 | n_insns += 2; | |
58e17b0b | 2904 | } |
42819d4e | 2905 | |
2906 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2907 | return n_insns * 4; | |
58e17b0b | 2908 | } |
a7e1bb24 | 2909 | |
2910 | /* Emit code to perform a block clear. | |
2911 | ||
2912 | OPERANDS[0] is the destination pointer as a REG, clobbered. | |
2913 | OPERANDS[1] is a register for temporary storage. | |
2914 | OPERANDS[2] is the size as a CONST_INT | |
2915 | OPERANDS[3] is the alignment safe to use, as a CONST_INT. */ | |
2916 | ||
2917 | const char * | |
e202682d | 2918 | pa_output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) |
a7e1bb24 | 2919 | { |
2920 | int align = INTVAL (operands[3]); | |
2921 | unsigned long n_bytes = INTVAL (operands[2]); | |
2922 | ||
2923 | /* We can't clear more than a word at a time because the PA | |
2924 | has no longer integer move insns. */ | |
2925 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2926 | align = (TARGET_64BIT ? 8 : 4); | |
2927 | ||
2928 | /* Note that we know each loop below will execute at least twice | |
2929 | (else we would have open-coded the copy). */ | |
2930 | switch (align) | |
2931 | { | |
2932 | case 8: | |
2933 | /* Pre-adjust the loop counter. */ | |
2934 | operands[2] = GEN_INT (n_bytes - 16); | |
2935 | output_asm_insn ("ldi %2,%1", operands); | |
2936 | ||
2937 | /* Loop. */ | |
2938 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2939 | output_asm_insn ("addib,>= -16,%1,.-4", operands); | |
2940 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2941 | ||
2942 | /* Handle the residual. There could be up to 7 bytes of | |
2943 | residual to copy! */ | |
2944 | if (n_bytes % 16 != 0) | |
2945 | { | |
2946 | operands[2] = GEN_INT (n_bytes % 8); | |
2947 | if (n_bytes % 16 >= 8) | |
2948 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2949 | if (n_bytes % 8 != 0) | |
2950 | output_asm_insn ("stdby,e %%r0,%2(%0)", operands); | |
2951 | } | |
2952 | return ""; | |
2953 | ||
2954 | case 4: | |
2955 | /* Pre-adjust the loop counter. */ | |
2956 | operands[2] = GEN_INT (n_bytes - 8); | |
2957 | output_asm_insn ("ldi %2,%1", operands); | |
2958 | ||
2959 | /* Loop. */ | |
2960 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2961 | output_asm_insn ("addib,>= -8,%1,.-4", operands); | |
2962 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2963 | ||
2964 | /* Handle the residual. There could be up to 7 bytes of | |
2965 | residual to copy! */ | |
2966 | if (n_bytes % 8 != 0) | |
2967 | { | |
2968 | operands[2] = GEN_INT (n_bytes % 4); | |
2969 | if (n_bytes % 8 >= 4) | |
2970 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2971 | if (n_bytes % 4 != 0) | |
2972 | output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands); | |
2973 | } | |
2974 | return ""; | |
2975 | ||
2976 | case 2: | |
2977 | /* Pre-adjust the loop counter. */ | |
2978 | operands[2] = GEN_INT (n_bytes - 4); | |
2979 | output_asm_insn ("ldi %2,%1", operands); | |
2980 | ||
2981 | /* Loop. */ | |
2982 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2983 | output_asm_insn ("addib,>= -4,%1,.-4", operands); | |
2984 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2985 | ||
2986 | /* Handle the residual. */ | |
2987 | if (n_bytes % 4 != 0) | |
2988 | { | |
2989 | if (n_bytes % 4 >= 2) | |
2990 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2991 | if (n_bytes % 2 != 0) | |
2992 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2993 | } | |
2994 | return ""; | |
2995 | ||
2996 | case 1: | |
2997 | /* Pre-adjust the loop counter. */ | |
2998 | operands[2] = GEN_INT (n_bytes - 2); | |
2999 | output_asm_insn ("ldi %2,%1", operands); | |
3000 | ||
3001 | /* Loop. */ | |
3002 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
3003 | output_asm_insn ("addib,>= -2,%1,.-4", operands); | |
3004 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
3005 | ||
3006 | /* Handle the residual. */ | |
3007 | if (n_bytes % 2 != 0) | |
3008 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
3009 | ||
3010 | return ""; | |
3011 | ||
3012 | default: | |
ecf2283d | 3013 | gcc_unreachable (); |
a7e1bb24 | 3014 | } |
3015 | } | |
3016 | ||
3017 | /* Count the number of insns necessary to handle this block move. | |
3018 | ||
3019 | Basic structure is the same as emit_block_move, except that we | |
3020 | count insns rather than emit them. */ | |
3021 | ||
3022 | static int | |
008c057d | 3023 | compute_clrmem_length (rtx insn) |
a7e1bb24 | 3024 | { |
3025 | rtx pat = PATTERN (insn); | |
3026 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0)); | |
3027 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0)); | |
3028 | unsigned int n_insns = 0; | |
3029 | ||
3030 | /* We can't clear more than a word at a time because the PA | |
3031 | has no longer integer move insns. */ | |
3032 | if (align > (TARGET_64BIT ? 8 : 4)) | |
3033 | align = (TARGET_64BIT ? 8 : 4); | |
3034 | ||
3035 | /* The basic loop. */ | |
3036 | n_insns = 4; | |
3037 | ||
3038 | /* Residuals. */ | |
3039 | if (n_bytes % (2 * align) != 0) | |
3040 | { | |
3041 | if ((n_bytes % (2 * align)) >= align) | |
3042 | n_insns++; | |
3043 | ||
3044 | if ((n_bytes % align) != 0) | |
3045 | n_insns++; | |
3046 | } | |
3047 | ||
3048 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
3049 | return n_insns * 4; | |
3050 | } | |
87ad11b0 | 3051 | \f |
3052 | ||
611a88e1 | 3053 | const char * |
e202682d | 3054 | pa_output_and (rtx *operands) |
e057641f | 3055 | { |
d6f01525 | 3056 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) |
e057641f | 3057 | { |
3745c59b | 3058 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
e057641f | 3059 | int ls0, ls1, ms0, p, len; |
3060 | ||
3061 | for (ls0 = 0; ls0 < 32; ls0++) | |
3062 | if ((mask & (1 << ls0)) == 0) | |
3063 | break; | |
3064 | ||
3065 | for (ls1 = ls0; ls1 < 32; ls1++) | |
3066 | if ((mask & (1 << ls1)) != 0) | |
3067 | break; | |
3068 | ||
3069 | for (ms0 = ls1; ms0 < 32; ms0++) | |
3070 | if ((mask & (1 << ms0)) == 0) | |
3071 | break; | |
3072 | ||
ecf2283d | 3073 | gcc_assert (ms0 == 32); |
e057641f | 3074 | |
3075 | if (ls1 == 32) | |
3076 | { | |
3077 | len = ls0; | |
3078 | ||
ecf2283d | 3079 | gcc_assert (len); |
e057641f | 3080 | |
ef618fe4 | 3081 | operands[2] = GEN_INT (len); |
e4065f95 | 3082 | return "{extru|extrw,u} %1,31,%2,%0"; |
e057641f | 3083 | } |
3084 | else | |
3085 | { | |
3086 | /* We could use this `depi' for the case above as well, but `depi' | |
3087 | requires one more register file access than an `extru'. */ | |
3088 | ||
3089 | p = 31 - ls0; | |
3090 | len = ls1 - ls0; | |
3091 | ||
ef618fe4 | 3092 | operands[2] = GEN_INT (p); |
3093 | operands[3] = GEN_INT (len); | |
e4065f95 | 3094 | return "{depi|depwi} 0,%2,%3,%0"; |
e057641f | 3095 | } |
3096 | } | |
3097 | else | |
3098 | return "and %1,%2,%0"; | |
3099 | } | |
3100 | ||
5e3c5739 | 3101 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] |
3102 | storing the result in operands[0]. */ | |
9aadea62 | 3103 | const char * |
e202682d | 3104 | pa_output_64bit_and (rtx *operands) |
5e3c5739 | 3105 | { |
3106 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) | |
3107 | { | |
3108 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 3109 | int ls0, ls1, ms0, p, len; |
5e3c5739 | 3110 | |
3111 | for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++) | |
b7d86581 | 3112 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0) |
5e3c5739 | 3113 | break; |
3114 | ||
3115 | for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++) | |
b7d86581 | 3116 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0) |
5e3c5739 | 3117 | break; |
3118 | ||
3119 | for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++) | |
b7d86581 | 3120 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0) |
5e3c5739 | 3121 | break; |
3122 | ||
ecf2283d | 3123 | gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT); |
5e3c5739 | 3124 | |
3125 | if (ls1 == HOST_BITS_PER_WIDE_INT) | |
3126 | { | |
3127 | len = ls0; | |
3128 | ||
ecf2283d | 3129 | gcc_assert (len); |
5e3c5739 | 3130 | |
3131 | operands[2] = GEN_INT (len); | |
3132 | return "extrd,u %1,63,%2,%0"; | |
3133 | } | |
3134 | else | |
3135 | { | |
3136 | /* We could use this `depi' for the case above as well, but `depi' | |
3137 | requires one more register file access than an `extru'. */ | |
3138 | ||
3139 | p = 63 - ls0; | |
3140 | len = ls1 - ls0; | |
3141 | ||
3142 | operands[2] = GEN_INT (p); | |
3143 | operands[3] = GEN_INT (len); | |
3144 | return "depdi 0,%2,%3,%0"; | |
3145 | } | |
3146 | } | |
3147 | else | |
3148 | return "and %1,%2,%0"; | |
3149 | } | |
3150 | ||
611a88e1 | 3151 | const char * |
e202682d | 3152 | pa_output_ior (rtx *operands) |
e057641f | 3153 | { |
3745c59b | 3154 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
57ed30e5 | 3155 | int bs0, bs1, p, len; |
6d36483b | 3156 | |
c9da5f4d | 3157 | if (INTVAL (operands[2]) == 0) |
3158 | return "copy %1,%0"; | |
e057641f | 3159 | |
c9da5f4d | 3160 | for (bs0 = 0; bs0 < 32; bs0++) |
3161 | if ((mask & (1 << bs0)) != 0) | |
3162 | break; | |
e057641f | 3163 | |
c9da5f4d | 3164 | for (bs1 = bs0; bs1 < 32; bs1++) |
3165 | if ((mask & (1 << bs1)) == 0) | |
3166 | break; | |
e057641f | 3167 | |
ecf2283d | 3168 | gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); |
e057641f | 3169 | |
c9da5f4d | 3170 | p = 31 - bs0; |
3171 | len = bs1 - bs0; | |
e057641f | 3172 | |
ef618fe4 | 3173 | operands[2] = GEN_INT (p); |
3174 | operands[3] = GEN_INT (len); | |
e4065f95 | 3175 | return "{depi|depwi} -1,%2,%3,%0"; |
e057641f | 3176 | } |
5e3c5739 | 3177 | |
3178 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] | |
3179 | storing the result in operands[0]. */ | |
9aadea62 | 3180 | const char * |
e202682d | 3181 | pa_output_64bit_ior (rtx *operands) |
5e3c5739 | 3182 | { |
3183 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 3184 | int bs0, bs1, p, len; |
5e3c5739 | 3185 | |
3186 | if (INTVAL (operands[2]) == 0) | |
3187 | return "copy %1,%0"; | |
3188 | ||
3189 | for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++) | |
b7d86581 | 3190 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0) |
5e3c5739 | 3191 | break; |
3192 | ||
3193 | for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++) | |
b7d86581 | 3194 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0) |
5e3c5739 | 3195 | break; |
3196 | ||
ecf2283d | 3197 | gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT |
3198 | || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); | |
5e3c5739 | 3199 | |
3200 | p = 63 - bs0; | |
3201 | len = bs1 - bs0; | |
3202 | ||
3203 | operands[2] = GEN_INT (p); | |
3204 | operands[3] = GEN_INT (len); | |
3205 | return "depdi -1,%2,%3,%0"; | |
3206 | } | |
e057641f | 3207 | \f |
58356836 | 3208 | /* Target hook for assembling integer objects. This code handles |
e678758c | 3209 | aligned SI and DI integers specially since function references |
3210 | must be preceded by P%. */ | |
58356836 | 3211 | |
3212 | static bool | |
5c1d8983 | 3213 | pa_assemble_integer (rtx x, unsigned int size, int aligned_p) |
58356836 | 3214 | { |
e678758c | 3215 | if (size == UNITS_PER_WORD |
3216 | && aligned_p | |
58356836 | 3217 | && function_label_operand (x, VOIDmode)) |
3218 | { | |
3219 | fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file); | |
3220 | output_addr_const (asm_out_file, x); | |
3221 | fputc ('\n', asm_out_file); | |
3222 | return true; | |
3223 | } | |
3224 | return default_assemble_integer (x, size, aligned_p); | |
3225 | } | |
3226 | \f | |
87ad11b0 | 3227 | /* Output an ascii string. */ |
57ed30e5 | 3228 | void |
e202682d | 3229 | pa_output_ascii (FILE *file, const char *p, int size) |
87ad11b0 | 3230 | { |
3231 | int i; | |
3232 | int chars_output; | |
5aedf60c | 3233 | unsigned char partial_output[16]; /* Max space 4 chars can occupy. */ |
87ad11b0 | 3234 | |
3235 | /* The HP assembler can only take strings of 256 characters at one | |
3236 | time. This is a limitation on input line length, *not* the | |
3237 | length of the string. Sigh. Even worse, it seems that the | |
3238 | restriction is in number of input characters (see \xnn & | |
3239 | \whatever). So we have to do this very carefully. */ | |
3240 | ||
9c0ac0fd | 3241 | fputs ("\t.STRING \"", file); |
87ad11b0 | 3242 | |
3243 | chars_output = 0; | |
3244 | for (i = 0; i < size; i += 4) | |
3245 | { | |
3246 | int co = 0; | |
3247 | int io = 0; | |
3248 | for (io = 0, co = 0; io < MIN (4, size - i); io++) | |
3249 | { | |
bf8aac3e | 3250 | register unsigned int c = (unsigned char) p[i + io]; |
87ad11b0 | 3251 | |
3252 | if (c == '\"' || c == '\\') | |
3253 | partial_output[co++] = '\\'; | |
3254 | if (c >= ' ' && c < 0177) | |
3255 | partial_output[co++] = c; | |
3256 | else | |
3257 | { | |
3258 | unsigned int hexd; | |
3259 | partial_output[co++] = '\\'; | |
3260 | partial_output[co++] = 'x'; | |
3261 | hexd = c / 16 - 0 + '0'; | |
3262 | if (hexd > '9') | |
3263 | hexd -= '9' - 'a' + 1; | |
3264 | partial_output[co++] = hexd; | |
3265 | hexd = c % 16 - 0 + '0'; | |
3266 | if (hexd > '9') | |
3267 | hexd -= '9' - 'a' + 1; | |
3268 | partial_output[co++] = hexd; | |
3269 | } | |
3270 | } | |
3271 | if (chars_output + co > 243) | |
3272 | { | |
9c0ac0fd | 3273 | fputs ("\"\n\t.STRING \"", file); |
87ad11b0 | 3274 | chars_output = 0; |
3275 | } | |
a584fe8a | 3276 | fwrite (partial_output, 1, (size_t) co, file); |
87ad11b0 | 3277 | chars_output += co; |
3278 | co = 0; | |
3279 | } | |
9c0ac0fd | 3280 | fputs ("\"\n", file); |
87ad11b0 | 3281 | } |
c533da59 | 3282 | |
3283 | /* Try to rewrite floating point comparisons & branches to avoid | |
3284 | useless add,tr insns. | |
3285 | ||
3286 | CHECK_NOTES is nonzero if we should examine REG_DEAD notes | |
3287 | to see if FPCC is dead. CHECK_NOTES is nonzero for the | |
3288 | first attempt to remove useless add,tr insns. It is zero | |
3289 | for the second pass as reorg sometimes leaves bogus REG_DEAD | |
3290 | notes lying around. | |
3291 | ||
3292 | When CHECK_NOTES is zero we can only eliminate add,tr insns | |
3293 | when there's a 1:1 correspondence between fcmp and ftest/fbranch | |
3294 | instructions. */ | |
611a88e1 | 3295 | static void |
5c1d8983 | 3296 | remove_useless_addtr_insns (int check_notes) |
c533da59 | 3297 | { |
3298 | rtx insn; | |
c533da59 | 3299 | static int pass = 0; |
3300 | ||
3301 | /* This is fairly cheap, so always run it when optimizing. */ | |
3302 | if (optimize > 0) | |
3303 | { | |
3304 | int fcmp_count = 0; | |
3305 | int fbranch_count = 0; | |
3306 | ||
3307 | /* Walk all the insns in this function looking for fcmp & fbranch | |
3308 | instructions. Keep track of how many of each we find. */ | |
2efea8c0 | 3309 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3310 | { |
3311 | rtx tmp; | |
3312 | ||
3313 | /* Ignore anything that isn't an INSN or a JUMP_INSN. */ | |
3314 | if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
3315 | continue; | |
3316 | ||
3317 | tmp = PATTERN (insn); | |
3318 | ||
3319 | /* It must be a set. */ | |
3320 | if (GET_CODE (tmp) != SET) | |
3321 | continue; | |
3322 | ||
3323 | /* If the destination is CCFP, then we've found an fcmp insn. */ | |
3324 | tmp = SET_DEST (tmp); | |
3325 | if (GET_CODE (tmp) == REG && REGNO (tmp) == 0) | |
3326 | { | |
3327 | fcmp_count++; | |
3328 | continue; | |
3329 | } | |
9840d99d | 3330 | |
c533da59 | 3331 | tmp = PATTERN (insn); |
3332 | /* If this is an fbranch instruction, bump the fbranch counter. */ | |
3333 | if (GET_CODE (tmp) == SET | |
3334 | && SET_DEST (tmp) == pc_rtx | |
3335 | && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE | |
3336 | && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE | |
3337 | && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG | |
3338 | && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0) | |
3339 | { | |
3340 | fbranch_count++; | |
3341 | continue; | |
3342 | } | |
3343 | } | |
3344 | ||
3345 | ||
3346 | /* Find all floating point compare + branch insns. If possible, | |
3347 | reverse the comparison & the branch to avoid add,tr insns. */ | |
2efea8c0 | 3348 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3349 | { |
3350 | rtx tmp, next; | |
3351 | ||
3352 | /* Ignore anything that isn't an INSN. */ | |
3353 | if (GET_CODE (insn) != INSN) | |
3354 | continue; | |
3355 | ||
3356 | tmp = PATTERN (insn); | |
3357 | ||
3358 | /* It must be a set. */ | |
3359 | if (GET_CODE (tmp) != SET) | |
3360 | continue; | |
3361 | ||
3362 | /* The destination must be CCFP, which is register zero. */ | |
3363 | tmp = SET_DEST (tmp); | |
3364 | if (GET_CODE (tmp) != REG || REGNO (tmp) != 0) | |
3365 | continue; | |
3366 | ||
3367 | /* INSN should be a set of CCFP. | |
3368 | ||
3369 | See if the result of this insn is used in a reversed FP | |
3370 | conditional branch. If so, reverse our condition and | |
3371 | the branch. Doing so avoids useless add,tr insns. */ | |
3372 | next = next_insn (insn); | |
3373 | while (next) | |
3374 | { | |
3375 | /* Jumps, calls and labels stop our search. */ | |
3376 | if (GET_CODE (next) == JUMP_INSN | |
3377 | || GET_CODE (next) == CALL_INSN | |
3378 | || GET_CODE (next) == CODE_LABEL) | |
3379 | break; | |
3380 | ||
3381 | /* As does another fcmp insn. */ | |
3382 | if (GET_CODE (next) == INSN | |
3383 | && GET_CODE (PATTERN (next)) == SET | |
3384 | && GET_CODE (SET_DEST (PATTERN (next))) == REG | |
3385 | && REGNO (SET_DEST (PATTERN (next))) == 0) | |
3386 | break; | |
3387 | ||
3388 | next = next_insn (next); | |
3389 | } | |
3390 | ||
3391 | /* Is NEXT_INSN a branch? */ | |
3392 | if (next | |
3393 | && GET_CODE (next) == JUMP_INSN) | |
3394 | { | |
3395 | rtx pattern = PATTERN (next); | |
3396 | ||
a361b456 | 3397 | /* If it a reversed fp conditional branch (e.g. uses add,tr) |
c533da59 | 3398 | and CCFP dies, then reverse our conditional and the branch |
3399 | to avoid the add,tr. */ | |
3400 | if (GET_CODE (pattern) == SET | |
3401 | && SET_DEST (pattern) == pc_rtx | |
3402 | && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE | |
3403 | && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE | |
3404 | && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG | |
3405 | && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0 | |
3406 | && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC | |
3407 | && (fcmp_count == fbranch_count | |
3408 | || (check_notes | |
3409 | && find_regno_note (next, REG_DEAD, 0)))) | |
3410 | { | |
3411 | /* Reverse the branch. */ | |
3412 | tmp = XEXP (SET_SRC (pattern), 1); | |
3413 | XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2); | |
3414 | XEXP (SET_SRC (pattern), 2) = tmp; | |
3415 | INSN_CODE (next) = -1; | |
3416 | ||
3417 | /* Reverse our condition. */ | |
3418 | tmp = PATTERN (insn); | |
3419 | PUT_CODE (XEXP (tmp, 1), | |
ea52c577 | 3420 | (reverse_condition_maybe_unordered |
3421 | (GET_CODE (XEXP (tmp, 1))))); | |
c533da59 | 3422 | } |
3423 | } | |
3424 | } | |
3425 | } | |
3426 | ||
3427 | pass = !pass; | |
3428 | ||
3429 | } | |
87ad11b0 | 3430 | \f |
ea52c577 | 3431 | /* You may have trouble believing this, but this is the 32 bit HP-PA |
3432 | stack layout. Wow. | |
87ad11b0 | 3433 | |
3434 | Offset Contents | |
3435 | ||
3436 | Variable arguments (optional; any number may be allocated) | |
3437 | ||
3438 | SP-(4*(N+9)) arg word N | |
3439 | : : | |
3440 | SP-56 arg word 5 | |
3441 | SP-52 arg word 4 | |
3442 | ||
3443 | Fixed arguments (must be allocated; may remain unused) | |
3444 | ||
3445 | SP-48 arg word 3 | |
3446 | SP-44 arg word 2 | |
3447 | SP-40 arg word 1 | |
3448 | SP-36 arg word 0 | |
3449 | ||
3450 | Frame Marker | |
3451 | ||
3452 | SP-32 External Data Pointer (DP) | |
3453 | SP-28 External sr4 | |
3454 | SP-24 External/stub RP (RP') | |
3455 | SP-20 Current RP | |
3456 | SP-16 Static Link | |
3457 | SP-12 Clean up | |
3458 | SP-8 Calling Stub RP (RP'') | |
3459 | SP-4 Previous SP | |
3460 | ||
3461 | Top of Frame | |
3462 | ||
3463 | SP-0 Stack Pointer (points to next available address) | |
3464 | ||
3465 | */ | |
3466 | ||
3467 | /* This function saves registers as follows. Registers marked with ' are | |
3468 | this function's registers (as opposed to the previous function's). | |
3469 | If a frame_pointer isn't needed, r4 is saved as a general register; | |
3470 | the space for the frame pointer is still allocated, though, to keep | |
3471 | things simple. | |
3472 | ||
3473 | ||
3474 | Top of Frame | |
3475 | ||
3476 | SP (FP') Previous FP | |
3477 | SP + 4 Alignment filler (sigh) | |
3478 | SP + 8 Space for locals reserved here. | |
3479 | . | |
3480 | . | |
3481 | . | |
3482 | SP + n All call saved register used. | |
3483 | . | |
3484 | . | |
3485 | . | |
3486 | SP + o All call saved fp registers used. | |
3487 | . | |
3488 | . | |
3489 | . | |
3490 | SP + p (SP') points to next available address. | |
6d36483b | 3491 | |
87ad11b0 | 3492 | */ |
3493 | ||
17d9b0c3 | 3494 | /* Global variables set by output_function_prologue(). */ |
cc858176 | 3495 | /* Size of frame. Need to know this to emit return insns from |
3496 | leaf procedures. */ | |
6bcdc1fb | 3497 | static HOST_WIDE_INT actual_fsize, local_fsize; |
3498 | static int save_fregs; | |
cc858176 | 3499 | |
daee63dd | 3500 | /* Emit RTL to store REG at the memory location specified by BASE+DISP. |
359a0be8 | 3501 | Handle case where DISP > 8k by using the add_high_const patterns. |
daee63dd | 3502 | |
3503 | Note in DISP > 8k case, we will leave the high part of the address | |
3504 | in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/ | |
7014838c | 3505 | |
6a2c16d6 | 3506 | static void |
6bcdc1fb | 3507 | store_reg (int reg, HOST_WIDE_INT disp, int base) |
87ad11b0 | 3508 | { |
6a2c16d6 | 3509 | rtx insn, dest, src, basereg; |
cc858176 | 3510 | |
3511 | src = gen_rtx_REG (word_mode, reg); | |
3512 | basereg = gen_rtx_REG (Pmode, base); | |
87ad11b0 | 3513 | if (VAL_14_BITS_P (disp)) |
daee63dd | 3514 | { |
29c05e22 | 3515 | dest = gen_rtx_MEM (word_mode, plus_constant (Pmode, basereg, disp)); |
6a2c16d6 | 3516 | insn = emit_move_insn (dest, src); |
daee63dd | 3517 | } |
6bcdc1fb | 3518 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3519 | { | |
3520 | rtx delta = GEN_INT (disp); | |
3521 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3522 | ||
3523 | emit_move_insn (tmpreg, delta); | |
5ecfd087 | 3524 | insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); |
6bcdc1fb | 3525 | if (DO_FRAME_NOTES) |
3526 | { | |
b9c74b4d | 3527 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3528 | gen_rtx_SET (VOIDmode, tmpreg, | |
3529 | gen_rtx_PLUS (Pmode, basereg, delta))); | |
5ecfd087 | 3530 | RTX_FRAME_RELATED_P (insn) = 1; |
6bcdc1fb | 3531 | } |
5ecfd087 | 3532 | dest = gen_rtx_MEM (word_mode, tmpreg); |
3533 | insn = emit_move_insn (dest, src); | |
6bcdc1fb | 3534 | } |
daee63dd | 3535 | else |
3536 | { | |
cc858176 | 3537 | rtx delta = GEN_INT (disp); |
3538 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3539 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 3540 | |
cc858176 | 3541 | emit_move_insn (tmpreg, high); |
3542 | dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
6a2c16d6 | 3543 | insn = emit_move_insn (dest, src); |
3544 | if (DO_FRAME_NOTES) | |
b9c74b4d | 3545 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3546 | gen_rtx_SET (VOIDmode, | |
3547 | gen_rtx_MEM (word_mode, | |
3548 | gen_rtx_PLUS (word_mode, | |
3549 | basereg, | |
3550 | delta)), | |
3551 | src)); | |
daee63dd | 3552 | } |
6a2c16d6 | 3553 | |
3554 | if (DO_FRAME_NOTES) | |
3555 | RTX_FRAME_RELATED_P (insn) = 1; | |
daee63dd | 3556 | } |
3557 | ||
a584fe8a | 3558 | /* Emit RTL to store REG at the memory location specified by BASE and then |
3559 | add MOD to BASE. MOD must be <= 8k. */ | |
daee63dd | 3560 | |
a584fe8a | 3561 | static void |
6bcdc1fb | 3562 | store_reg_modify (int base, int reg, HOST_WIDE_INT mod) |
a584fe8a | 3563 | { |
3564 | rtx insn, basereg, srcreg, delta; | |
3565 | ||
ecf2283d | 3566 | gcc_assert (VAL_14_BITS_P (mod)); |
a584fe8a | 3567 | |
3568 | basereg = gen_rtx_REG (Pmode, base); | |
3569 | srcreg = gen_rtx_REG (word_mode, reg); | |
3570 | delta = GEN_INT (mod); | |
3571 | ||
3572 | insn = emit_insn (gen_post_store (basereg, srcreg, delta)); | |
3573 | if (DO_FRAME_NOTES) | |
3574 | { | |
3575 | RTX_FRAME_RELATED_P (insn) = 1; | |
3576 | ||
3577 | /* RTX_FRAME_RELATED_P must be set on each frame related set | |
dc873350 | 3578 | in a parallel with more than one element. */ |
3579 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1; | |
3580 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; | |
a584fe8a | 3581 | } |
3582 | } | |
3583 | ||
3584 | /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case | |
3585 | where DISP > 8k by using the add_high_const patterns. NOTE indicates | |
3586 | whether to add a frame note or not. | |
3587 | ||
3588 | In the DISP > 8k case, we leave the high part of the address in %r1. | |
3589 | There is code in expand_hppa_{prologue,epilogue} that knows about this. */ | |
7014838c | 3590 | |
6a2c16d6 | 3591 | static void |
6bcdc1fb | 3592 | set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note) |
87ad11b0 | 3593 | { |
6a2c16d6 | 3594 | rtx insn; |
cc858176 | 3595 | |
87ad11b0 | 3596 | if (VAL_14_BITS_P (disp)) |
cc858176 | 3597 | { |
6a2c16d6 | 3598 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
29c05e22 | 3599 | plus_constant (Pmode, |
3600 | gen_rtx_REG (Pmode, base), disp)); | |
cc858176 | 3601 | } |
6bcdc1fb | 3602 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3603 | { | |
3604 | rtx basereg = gen_rtx_REG (Pmode, base); | |
3605 | rtx delta = GEN_INT (disp); | |
3606 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3607 | ||
3608 | emit_move_insn (tmpreg, delta); | |
3609 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), | |
3610 | gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
5ecfd087 | 3611 | if (DO_FRAME_NOTES) |
b9c74b4d | 3612 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3613 | gen_rtx_SET (VOIDmode, tmpreg, | |
3614 | gen_rtx_PLUS (Pmode, basereg, delta))); | |
6bcdc1fb | 3615 | } |
87ad11b0 | 3616 | else |
daee63dd | 3617 | { |
6a2c16d6 | 3618 | rtx basereg = gen_rtx_REG (Pmode, base); |
cc858176 | 3619 | rtx delta = GEN_INT (disp); |
6bcdc1fb | 3620 | rtx tmpreg = gen_rtx_REG (Pmode, 1); |
6a2c16d6 | 3621 | |
6bcdc1fb | 3622 | emit_move_insn (tmpreg, |
6a2c16d6 | 3623 | gen_rtx_PLUS (Pmode, basereg, |
cc858176 | 3624 | gen_rtx_HIGH (Pmode, delta))); |
6a2c16d6 | 3625 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
6bcdc1fb | 3626 | gen_rtx_LO_SUM (Pmode, tmpreg, delta)); |
daee63dd | 3627 | } |
6a2c16d6 | 3628 | |
a584fe8a | 3629 | if (DO_FRAME_NOTES && note) |
6a2c16d6 | 3630 | RTX_FRAME_RELATED_P (insn) = 1; |
87ad11b0 | 3631 | } |
3632 | ||
6bcdc1fb | 3633 | HOST_WIDE_INT |
e202682d | 3634 | pa_compute_frame_size (HOST_WIDE_INT size, int *fregs_live) |
87ad11b0 | 3635 | { |
256f9b65 | 3636 | int freg_saved = 0; |
3637 | int i, j; | |
3638 | ||
e202682d | 3639 | /* The code in pa_expand_prologue and pa_expand_epilogue must |
256f9b65 | 3640 | be consistent with the rounding and size calculation done here. |
3641 | Change them at the same time. */ | |
3642 | ||
3643 | /* We do our own stack alignment. First, round the size of the | |
3644 | stack locals up to a word boundary. */ | |
3645 | size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3646 | ||
3647 | /* Space for previous frame pointer + filler. If any frame is | |
3648 | allocated, we need to add in the STARTING_FRAME_OFFSET. We | |
3649 | waste some space here for the sake of HP compatibility. The | |
3650 | first slot is only used when the frame pointer is needed. */ | |
3651 | if (size || frame_pointer_needed) | |
3652 | size += STARTING_FRAME_OFFSET; | |
3653 | ||
a584fe8a | 3654 | /* If the current function calls __builtin_eh_return, then we need |
3655 | to allocate stack space for registers that will hold data for | |
3656 | the exception handler. */ | |
18d50ae6 | 3657 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 3658 | { |
3659 | unsigned int i; | |
3660 | ||
3661 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
3662 | continue; | |
256f9b65 | 3663 | size += i * UNITS_PER_WORD; |
a584fe8a | 3664 | } |
3665 | ||
3a51bad9 | 3666 | /* Account for space used by the callee general register saves. */ |
256f9b65 | 3667 | for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--) |
3072d30e | 3668 | if (df_regs_ever_live_p (i)) |
256f9b65 | 3669 | size += UNITS_PER_WORD; |
df0651dc | 3670 | |
3a51bad9 | 3671 | /* Account for space used by the callee floating point register saves. */ |
bac38c40 | 3672 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
3072d30e | 3673 | if (df_regs_ever_live_p (i) |
3674 | || (!TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
df0651dc | 3675 | { |
256f9b65 | 3676 | freg_saved = 1; |
002fc5f7 | 3677 | |
3a51bad9 | 3678 | /* We always save both halves of the FP register, so always |
3679 | increment the frame size by 8 bytes. */ | |
256f9b65 | 3680 | size += 8; |
df0651dc | 3681 | } |
3682 | ||
256f9b65 | 3683 | /* If any of the floating registers are saved, account for the |
3684 | alignment needed for the floating point register save block. */ | |
3685 | if (freg_saved) | |
3686 | { | |
3687 | size = (size + 7) & ~7; | |
3688 | if (fregs_live) | |
3689 | *fregs_live = 1; | |
3690 | } | |
3691 | ||
3a51bad9 | 3692 | /* The various ABIs include space for the outgoing parameters in the |
256f9b65 | 3693 | size of the current function's stack frame. We don't need to align |
3694 | for the outgoing arguments as their alignment is set by the final | |
3695 | rounding for the frame as a whole. */ | |
abe32cce | 3696 | size += crtl->outgoing_args_size; |
3a51bad9 | 3697 | |
3698 | /* Allocate space for the fixed frame marker. This space must be | |
e9ec370e | 3699 | allocated for any function that makes calls or allocates |
3a51bad9 | 3700 | stack space. */ |
d5bf7b64 | 3701 | if (!crtl->is_leaf || size) |
e9ec370e | 3702 | size += TARGET_64BIT ? 48 : 32; |
5e3c5739 | 3703 | |
256f9b65 | 3704 | /* Finally, round to the preferred stack boundary. */ |
2247cc5f | 3705 | return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1) |
3706 | & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
87ad11b0 | 3707 | } |
6d36483b | 3708 | |
17d9b0c3 | 3709 | /* Generate the assembly code for function entry. FILE is a stdio |
3710 | stream to output the code to. SIZE is an int: how many units of | |
3711 | temporary storage to allocate. | |
3712 | ||
3713 | Refer to the array `regs_ever_live' to determine which registers to | |
3714 | save; `regs_ever_live[I]' is nonzero if register number I is ever | |
3715 | used in the function. This function is responsible for knowing | |
3716 | which registers should not be saved even if used. */ | |
3717 | ||
3718 | /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block | |
3719 | of memory. If any fpu reg is used in the function, we allocate | |
3720 | such a block here, at the bottom of the frame, just in case it's needed. | |
3721 | ||
3722 | If this function is a leaf procedure, then we may choose not | |
3723 | to do a "save" insn. The decision about whether or not | |
3724 | to do this is made in regclass.c. */ | |
3725 | ||
6988553d | 3726 | static void |
5c1d8983 | 3727 | pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 3728 | { |
d151162a | 3729 | /* The function's label and associated .PROC must never be |
3730 | separated and must be output *after* any profiling declarations | |
3731 | to avoid changing spaces/subspaces within a procedure. */ | |
3732 | ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3733 | fputs ("\t.PROC\n", file); | |
3734 | ||
e202682d | 3735 | /* pa_expand_prologue does the dirty work now. We just need |
daee63dd | 3736 | to output the assembler directives which denote the start |
3737 | of a function. */ | |
6bcdc1fb | 3738 | fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize); |
d5bf7b64 | 3739 | if (crtl->is_leaf) |
9c0ac0fd | 3740 | fputs (",NO_CALLS", file); |
df6b92e4 | 3741 | else |
3742 | fputs (",CALLS", file); | |
3743 | if (rp_saved) | |
3744 | fputs (",SAVE_RP", file); | |
f3ba7709 | 3745 | |
e9ec370e | 3746 | /* The SAVE_SP flag is used to indicate that register %r3 is stored |
3747 | at the beginning of the frame and that it is used as the frame | |
3748 | pointer for the frame. We do this because our current frame | |
3ce7ff97 | 3749 | layout doesn't conform to that specified in the HP runtime |
e9ec370e | 3750 | documentation and we need a way to indicate to programs such as |
3751 | GDB where %r3 is saved. The SAVE_SP flag was chosen because it | |
3752 | isn't used by HP compilers but is supported by the assembler. | |
3753 | However, SAVE_SP is supposed to indicate that the previous stack | |
3754 | pointer has been saved in the frame marker. */ | |
f3ba7709 | 3755 | if (frame_pointer_needed) |
9c0ac0fd | 3756 | fputs (",SAVE_SP", file); |
f3ba7709 | 3757 | |
a9960cdc | 3758 | /* Pass on information about the number of callee register saves |
9b0c95be | 3759 | performed in the prologue. |
3760 | ||
3761 | The compiler is supposed to pass the highest register number | |
6d36483b | 3762 | saved, the assembler then has to adjust that number before |
9b0c95be | 3763 | entering it into the unwind descriptor (to account for any |
6d36483b | 3764 | caller saved registers with lower register numbers than the |
9b0c95be | 3765 | first callee saved register). */ |
3766 | if (gr_saved) | |
3767 | fprintf (file, ",ENTRY_GR=%d", gr_saved + 2); | |
3768 | ||
3769 | if (fr_saved) | |
3770 | fprintf (file, ",ENTRY_FR=%d", fr_saved + 11); | |
a9960cdc | 3771 | |
9c0ac0fd | 3772 | fputs ("\n\t.ENTRY\n", file); |
daee63dd | 3773 | |
2efea8c0 | 3774 | remove_useless_addtr_insns (0); |
daee63dd | 3775 | } |
3776 | ||
57ed30e5 | 3777 | void |
e202682d | 3778 | pa_expand_prologue (void) |
daee63dd | 3779 | { |
afd7b680 | 3780 | int merge_sp_adjust_with_store = 0; |
6bcdc1fb | 3781 | HOST_WIDE_INT size = get_frame_size (); |
3782 | HOST_WIDE_INT offset; | |
3783 | int i; | |
a584fe8a | 3784 | rtx insn, tmpreg; |
daee63dd | 3785 | |
a9960cdc | 3786 | gr_saved = 0; |
3787 | fr_saved = 0; | |
3ddcbb9d | 3788 | save_fregs = 0; |
3a51bad9 | 3789 | |
256f9b65 | 3790 | /* Compute total size for frame pointer, filler, locals and rounding to |
e202682d | 3791 | the next word boundary. Similar code appears in pa_compute_frame_size |
256f9b65 | 3792 | and must be changed in tandem with this code. */ |
3793 | local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3794 | if (local_fsize || frame_pointer_needed) | |
3795 | local_fsize += STARTING_FRAME_OFFSET; | |
3a51bad9 | 3796 | |
e202682d | 3797 | actual_fsize = pa_compute_frame_size (size, &save_fregs); |
8c0dd614 | 3798 | if (flag_stack_usage_info) |
990495a7 | 3799 | current_function_static_stack_size = actual_fsize; |
87ad11b0 | 3800 | |
daee63dd | 3801 | /* Compute a few things we will use often. */ |
440c23df | 3802 | tmpreg = gen_rtx_REG (word_mode, 1); |
87ad11b0 | 3803 | |
6d36483b | 3804 | /* Save RP first. The calling conventions manual states RP will |
cc858176 | 3805 | always be stored into the caller's frame at sp - 20 or sp - 16 |
5e3c5739 | 3806 | depending on which ABI is in use. */ |
18d50ae6 | 3807 | if (df_regs_ever_live_p (2) || crtl->calls_eh_return) |
df6b92e4 | 3808 | { |
3809 | store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM); | |
3810 | rp_saved = true; | |
3811 | } | |
3812 | else | |
3813 | rp_saved = false; | |
6d36483b | 3814 | |
daee63dd | 3815 | /* Allocate the local frame and set up the frame pointer if needed. */ |
58361f39 | 3816 | if (actual_fsize != 0) |
3817 | { | |
3818 | if (frame_pointer_needed) | |
3819 | { | |
3820 | /* Copy the old frame pointer temporarily into %r1. Set up the | |
3821 | new stack pointer, then store away the saved old frame pointer | |
a584fe8a | 3822 | into the stack at sp and at the same time update the stack |
3823 | pointer by actual_fsize bytes. Two versions, first | |
58361f39 | 3824 | handles small (<8k) frames. The second handles large (>=8k) |
3825 | frames. */ | |
68bc9ae6 | 3826 | insn = emit_move_insn (tmpreg, hard_frame_pointer_rtx); |
a584fe8a | 3827 | if (DO_FRAME_NOTES) |
dc873350 | 3828 | RTX_FRAME_RELATED_P (insn) = 1; |
a584fe8a | 3829 | |
68bc9ae6 | 3830 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); |
a584fe8a | 3831 | if (DO_FRAME_NOTES) |
3832 | RTX_FRAME_RELATED_P (insn) = 1; | |
3833 | ||
3834 | if (VAL_14_BITS_P (actual_fsize)) | |
3835 | store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize); | |
58361f39 | 3836 | else |
3837 | { | |
3838 | /* It is incorrect to store the saved frame pointer at *sp, | |
3839 | then increment sp (writes beyond the current stack boundary). | |
3840 | ||
3841 | So instead use stwm to store at *sp and post-increment the | |
3842 | stack pointer as an atomic operation. Then increment sp to | |
3843 | finish allocating the new frame. */ | |
6bcdc1fb | 3844 | HOST_WIDE_INT adjust1 = 8192 - 64; |
3845 | HOST_WIDE_INT adjust2 = actual_fsize - adjust1; | |
cc858176 | 3846 | |
a584fe8a | 3847 | store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1); |
6a2c16d6 | 3848 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3849 | adjust2, 1); |
58361f39 | 3850 | } |
a584fe8a | 3851 | |
e9ec370e | 3852 | /* We set SAVE_SP in frames that need a frame pointer. Thus, |
3853 | we need to store the previous stack pointer (frame pointer) | |
3854 | into the frame marker on targets that use the HP unwind | |
3855 | library. This allows the HP unwind library to be used to | |
3856 | unwind GCC frames. However, we are not fully compatible | |
3857 | with the HP library because our frame layout differs from | |
3858 | that specified in the HP runtime specification. | |
3859 | ||
3860 | We don't want a frame note on this instruction as the frame | |
3861 | marker moves during dynamic stack allocation. | |
3862 | ||
3863 | This instruction also serves as a blockage to prevent | |
3864 | register spills from being scheduled before the stack | |
3865 | pointer is raised. This is necessary as we store | |
3866 | registers using the frame pointer as a base register, | |
3867 | and the frame pointer is set before sp is raised. */ | |
3868 | if (TARGET_HPUX_UNWIND_LIBRARY) | |
3869 | { | |
3870 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, | |
3871 | GEN_INT (TARGET_64BIT ? -8 : -4)); | |
3872 | ||
3873 | emit_move_insn (gen_rtx_MEM (word_mode, addr), | |
68bc9ae6 | 3874 | hard_frame_pointer_rtx); |
e9ec370e | 3875 | } |
3876 | else | |
3877 | emit_insn (gen_blockage ()); | |
58361f39 | 3878 | } |
3879 | /* no frame pointer needed. */ | |
3880 | else | |
3881 | { | |
3882 | /* In some cases we can perform the first callee register save | |
3883 | and allocating the stack frame at the same time. If so, just | |
3884 | make a note of it and defer allocating the frame until saving | |
3885 | the callee registers. */ | |
df6edefa | 3886 | if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0) |
58361f39 | 3887 | merge_sp_adjust_with_store = 1; |
3888 | /* Can not optimize. Adjust the stack frame by actual_fsize | |
3889 | bytes. */ | |
3890 | else | |
6a2c16d6 | 3891 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3892 | actual_fsize, 1); |
58361f39 | 3893 | } |
372ef038 | 3894 | } |
3895 | ||
6d36483b | 3896 | /* Normal register save. |
daee63dd | 3897 | |
3898 | Do not save the frame pointer in the frame_pointer_needed case. It | |
3899 | was done earlier. */ | |
87ad11b0 | 3900 | if (frame_pointer_needed) |
3901 | { | |
a584fe8a | 3902 | offset = local_fsize; |
3903 | ||
3904 | /* Saving the EH return data registers in the frame is the simplest | |
3905 | way to get the frame unwind information emitted. We put them | |
3906 | just before the general registers. */ | |
18d50ae6 | 3907 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 3908 | { |
3909 | unsigned int i, regno; | |
3910 | ||
3911 | for (i = 0; ; ++i) | |
3912 | { | |
3913 | regno = EH_RETURN_DATA_REGNO (i); | |
3914 | if (regno == INVALID_REGNUM) | |
3915 | break; | |
3916 | ||
68bc9ae6 | 3917 | store_reg (regno, offset, HARD_FRAME_POINTER_REGNUM); |
a584fe8a | 3918 | offset += UNITS_PER_WORD; |
3919 | } | |
3920 | } | |
3921 | ||
3922 | for (i = 18; i >= 4; i--) | |
3072d30e | 3923 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
87ad11b0 | 3924 | { |
68bc9ae6 | 3925 | store_reg (i, offset, HARD_FRAME_POINTER_REGNUM); |
6ec4380b | 3926 | offset += UNITS_PER_WORD; |
a9960cdc | 3927 | gr_saved++; |
87ad11b0 | 3928 | } |
7f7c4869 | 3929 | /* Account for %r3 which is saved in a special place. */ |
9b0c95be | 3930 | gr_saved++; |
87ad11b0 | 3931 | } |
daee63dd | 3932 | /* No frame pointer needed. */ |
87ad11b0 | 3933 | else |
3934 | { | |
a584fe8a | 3935 | offset = local_fsize - actual_fsize; |
3936 | ||
3937 | /* Saving the EH return data registers in the frame is the simplest | |
3938 | way to get the frame unwind information emitted. */ | |
18d50ae6 | 3939 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 3940 | { |
3941 | unsigned int i, regno; | |
3942 | ||
3943 | for (i = 0; ; ++i) | |
3944 | { | |
3945 | regno = EH_RETURN_DATA_REGNO (i); | |
3946 | if (regno == INVALID_REGNUM) | |
3947 | break; | |
3948 | ||
3949 | /* If merge_sp_adjust_with_store is nonzero, then we can | |
3950 | optimize the first save. */ | |
3951 | if (merge_sp_adjust_with_store) | |
3952 | { | |
3953 | store_reg_modify (STACK_POINTER_REGNUM, regno, -offset); | |
3954 | merge_sp_adjust_with_store = 0; | |
3955 | } | |
3956 | else | |
3957 | store_reg (regno, offset, STACK_POINTER_REGNUM); | |
3958 | offset += UNITS_PER_WORD; | |
3959 | } | |
3960 | } | |
3961 | ||
3962 | for (i = 18; i >= 3; i--) | |
3072d30e | 3963 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
87ad11b0 | 3964 | { |
6d36483b | 3965 | /* If merge_sp_adjust_with_store is nonzero, then we can |
afd7b680 | 3966 | optimize the first GR save. */ |
201f01e9 | 3967 | if (merge_sp_adjust_with_store) |
afd7b680 | 3968 | { |
a584fe8a | 3969 | store_reg_modify (STACK_POINTER_REGNUM, i, -offset); |
afd7b680 | 3970 | merge_sp_adjust_with_store = 0; |
afd7b680 | 3971 | } |
3972 | else | |
6a2c16d6 | 3973 | store_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 3974 | offset += UNITS_PER_WORD; |
a9960cdc | 3975 | gr_saved++; |
87ad11b0 | 3976 | } |
daee63dd | 3977 | |
afd7b680 | 3978 | /* If we wanted to merge the SP adjustment with a GR save, but we never |
daee63dd | 3979 | did any GR saves, then just emit the adjustment here. */ |
201f01e9 | 3980 | if (merge_sp_adjust_with_store) |
6a2c16d6 | 3981 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3982 | actual_fsize, 1); |
87ad11b0 | 3983 | } |
6d36483b | 3984 | |
df6edefa | 3985 | /* The hppa calling conventions say that %r19, the pic offset |
3986 | register, is saved at sp - 32 (in this function's frame) | |
3987 | when generating PIC code. FIXME: What is the correct thing | |
3988 | to do for functions which make no calls and allocate no | |
3989 | frame? Do we need to allocate a frame, or can we just omit | |
8f177faf | 3990 | the save? For now we'll just omit the save. |
3991 | ||
3992 | We don't want a note on this insn as the frame marker can | |
3993 | move if there is a dynamic stack allocation. */ | |
df6edefa | 3994 | if (flag_pic && actual_fsize != 0 && !TARGET_64BIT) |
8f177faf | 3995 | { |
3996 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32)); | |
3997 | ||
3998 | emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx); | |
3999 | ||
4000 | } | |
df6edefa | 4001 | |
87ad11b0 | 4002 | /* Align pointer properly (doubleword boundary). */ |
4003 | offset = (offset + 7) & ~7; | |
4004 | ||
4005 | /* Floating point register store. */ | |
4006 | if (save_fregs) | |
87ad11b0 | 4007 | { |
a584fe8a | 4008 | rtx base; |
4009 | ||
daee63dd | 4010 | /* First get the frame or stack pointer to the start of the FP register |
4011 | save area. */ | |
a1ab4fa3 | 4012 | if (frame_pointer_needed) |
a584fe8a | 4013 | { |
68bc9ae6 | 4014 | set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0); |
4015 | base = hard_frame_pointer_rtx; | |
a584fe8a | 4016 | } |
a1ab4fa3 | 4017 | else |
a584fe8a | 4018 | { |
4019 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); | |
4020 | base = stack_pointer_rtx; | |
4021 | } | |
daee63dd | 4022 | |
4023 | /* Now actually save the FP registers. */ | |
bac38c40 | 4024 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
7f7c4869 | 4025 | { |
3072d30e | 4026 | if (df_regs_ever_live_p (i) |
4027 | || (! TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
7f7c4869 | 4028 | { |
6a2c16d6 | 4029 | rtx addr, insn, reg; |
cc858176 | 4030 | addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); |
4031 | reg = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 4032 | insn = emit_move_insn (addr, reg); |
4033 | if (DO_FRAME_NOTES) | |
4034 | { | |
4035 | RTX_FRAME_RELATED_P (insn) = 1; | |
a584fe8a | 4036 | if (TARGET_64BIT) |
4037 | { | |
4038 | rtx mem = gen_rtx_MEM (DFmode, | |
29c05e22 | 4039 | plus_constant (Pmode, base, |
4040 | offset)); | |
b9c74b4d | 4041 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
4042 | gen_rtx_SET (VOIDmode, mem, reg)); | |
a584fe8a | 4043 | } |
4044 | else | |
4045 | { | |
4046 | rtx meml = gen_rtx_MEM (SFmode, | |
29c05e22 | 4047 | plus_constant (Pmode, base, |
4048 | offset)); | |
a584fe8a | 4049 | rtx memr = gen_rtx_MEM (SFmode, |
29c05e22 | 4050 | plus_constant (Pmode, base, |
4051 | offset + 4)); | |
a584fe8a | 4052 | rtx regl = gen_rtx_REG (SFmode, i); |
4053 | rtx regr = gen_rtx_REG (SFmode, i + 1); | |
4054 | rtx setl = gen_rtx_SET (VOIDmode, meml, regl); | |
4055 | rtx setr = gen_rtx_SET (VOIDmode, memr, regr); | |
4056 | rtvec vec; | |
4057 | ||
4058 | RTX_FRAME_RELATED_P (setl) = 1; | |
4059 | RTX_FRAME_RELATED_P (setr) = 1; | |
4060 | vec = gen_rtvec (2, setl, setr); | |
b9c74b4d | 4061 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
4062 | gen_rtx_SEQUENCE (VOIDmode, vec)); | |
a584fe8a | 4063 | } |
6a2c16d6 | 4064 | } |
4065 | offset += GET_MODE_SIZE (DFmode); | |
7f7c4869 | 4066 | fr_saved++; |
4067 | } | |
4068 | } | |
87ad11b0 | 4069 | } |
4070 | } | |
4071 | ||
cc858176 | 4072 | /* Emit RTL to load REG from the memory location specified by BASE+DISP. |
4073 | Handle case where DISP > 8k by using the add_high_const patterns. */ | |
4074 | ||
6a2c16d6 | 4075 | static void |
6bcdc1fb | 4076 | load_reg (int reg, HOST_WIDE_INT disp, int base) |
cc858176 | 4077 | { |
6bcdc1fb | 4078 | rtx dest = gen_rtx_REG (word_mode, reg); |
4079 | rtx basereg = gen_rtx_REG (Pmode, base); | |
4080 | rtx src; | |
cc858176 | 4081 | |
cc858176 | 4082 | if (VAL_14_BITS_P (disp)) |
29c05e22 | 4083 | src = gen_rtx_MEM (word_mode, plus_constant (Pmode, basereg, disp)); |
6bcdc1fb | 4084 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
cc858176 | 4085 | { |
6bcdc1fb | 4086 | rtx delta = GEN_INT (disp); |
4087 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
4088 | ||
4089 | emit_move_insn (tmpreg, delta); | |
4090 | if (TARGET_DISABLE_INDEXING) | |
4091 | { | |
4092 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
4093 | src = gen_rtx_MEM (word_mode, tmpreg); | |
4094 | } | |
4095 | else | |
4096 | src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
cc858176 | 4097 | } |
4098 | else | |
4099 | { | |
4100 | rtx delta = GEN_INT (disp); | |
4101 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
4102 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 4103 | |
cc858176 | 4104 | emit_move_insn (tmpreg, high); |
4105 | src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
cc858176 | 4106 | } |
6bcdc1fb | 4107 | |
4108 | emit_move_insn (dest, src); | |
cc858176 | 4109 | } |
daee63dd | 4110 | |
2247cc5f | 4111 | /* Update the total code bytes output to the text section. */ |
4112 | ||
4113 | static void | |
21a47bc9 | 4114 | update_total_code_bytes (unsigned int nbytes) |
2247cc5f | 4115 | { |
4116 | if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM) | |
8a05c3c2 | 4117 | && !IN_NAMED_SECTION_P (cfun->decl)) |
2247cc5f | 4118 | { |
21a47bc9 | 4119 | unsigned int old_total = total_code_bytes; |
2247cc5f | 4120 | |
21a47bc9 | 4121 | total_code_bytes += nbytes; |
2247cc5f | 4122 | |
21a47bc9 | 4123 | /* Be prepared to handle overflows. */ |
4124 | if (old_total > total_code_bytes) | |
4125 | total_code_bytes = UINT_MAX; | |
2247cc5f | 4126 | } |
4127 | } | |
4128 | ||
17d9b0c3 | 4129 | /* This function generates the assembly code for function exit. |
4130 | Args are as for output_function_prologue (). | |
4131 | ||
4132 | The function epilogue should not depend on the current stack | |
4133 | pointer! It should use the frame pointer only. This is mandatory | |
4134 | because of alloca; we also take advantage of it to omit stack | |
6dc3b0d9 | 4135 | adjustments before returning. */ |
17d9b0c3 | 4136 | |
4137 | static void | |
5c1d8983 | 4138 | pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 4139 | { |
3695c664 | 4140 | rtx insn = get_last_insn (); |
4141 | ||
2247cc5f | 4142 | last_address = 0; |
4143 | ||
e202682d | 4144 | /* pa_expand_epilogue does the dirty work now. We just need |
daee63dd | 4145 | to output the assembler directives which denote the end |
3695c664 | 4146 | of a function. |
4147 | ||
4148 | To make debuggers happy, emit a nop if the epilogue was completely | |
4149 | eliminated due to a volatile call as the last insn in the | |
6d36483b | 4150 | current function. That way the return address (in %r2) will |
3695c664 | 4151 | always point to a valid instruction in the current function. */ |
4152 | ||
4153 | /* Get the last real insn. */ | |
4154 | if (GET_CODE (insn) == NOTE) | |
4155 | insn = prev_real_insn (insn); | |
4156 | ||
4157 | /* If it is a sequence, then look inside. */ | |
4158 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
4159 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
4160 | ||
6d36483b | 4161 | /* If insn is a CALL_INSN, then it must be a call to a volatile |
3695c664 | 4162 | function (otherwise there would be epilogue insns). */ |
4163 | if (insn && GET_CODE (insn) == CALL_INSN) | |
90c41894 | 4164 | { |
4165 | fputs ("\tnop\n", file); | |
4166 | last_address += 4; | |
4167 | } | |
6d36483b | 4168 | |
9c0ac0fd | 4169 | fputs ("\t.EXIT\n\t.PROCEND\n", file); |
90c41894 | 4170 | |
916c9cef | 4171 | if (TARGET_SOM && TARGET_GAS) |
4172 | { | |
4173 | /* We done with this subspace except possibly for some additional | |
4174 | debug information. Forget that we are in this subspace to ensure | |
4175 | that the next function is output in its own subspace. */ | |
2f14b1f9 | 4176 | in_section = NULL; |
78962d38 | 4177 | cfun->machine->in_nsubspa = 2; |
916c9cef | 4178 | } |
4179 | ||
2247cc5f | 4180 | if (INSN_ADDRESSES_SET_P ()) |
90c41894 | 4181 | { |
2247cc5f | 4182 | insn = get_last_nonnote_insn (); |
4183 | last_address += INSN_ADDRESSES (INSN_UID (insn)); | |
4184 | if (INSN_P (insn)) | |
4185 | last_address += insn_default_length (insn); | |
4186 | last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) | |
4187 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
90c41894 | 4188 | } |
21a47bc9 | 4189 | else |
4190 | last_address = UINT_MAX; | |
2247cc5f | 4191 | |
4192 | /* Finally, update the total number of code bytes output so far. */ | |
4193 | update_total_code_bytes (last_address); | |
daee63dd | 4194 | } |
afd7b680 | 4195 | |
daee63dd | 4196 | void |
e202682d | 4197 | pa_expand_epilogue (void) |
daee63dd | 4198 | { |
6d36483b | 4199 | rtx tmpreg; |
6bcdc1fb | 4200 | HOST_WIDE_INT offset; |
4201 | HOST_WIDE_INT ret_off = 0; | |
4202 | int i; | |
58361f39 | 4203 | int merge_sp_adjust_with_load = 0; |
daee63dd | 4204 | |
4205 | /* We will use this often. */ | |
440c23df | 4206 | tmpreg = gen_rtx_REG (word_mode, 1); |
daee63dd | 4207 | |
4208 | /* Try to restore RP early to avoid load/use interlocks when | |
4209 | RP gets used in the return (bv) instruction. This appears to still | |
6dc3b0d9 | 4210 | be necessary even when we schedule the prologue and epilogue. */ |
df6b92e4 | 4211 | if (rp_saved) |
58361f39 | 4212 | { |
4213 | ret_off = TARGET_64BIT ? -16 : -20; | |
4214 | if (frame_pointer_needed) | |
4215 | { | |
68bc9ae6 | 4216 | load_reg (2, ret_off, HARD_FRAME_POINTER_REGNUM); |
58361f39 | 4217 | ret_off = 0; |
4218 | } | |
4219 | else | |
4220 | { | |
4221 | /* No frame pointer, and stack is smaller than 8k. */ | |
4222 | if (VAL_14_BITS_P (ret_off - actual_fsize)) | |
4223 | { | |
6a2c16d6 | 4224 | load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM); |
58361f39 | 4225 | ret_off = 0; |
4226 | } | |
4227 | } | |
4228 | } | |
daee63dd | 4229 | |
4230 | /* General register restores. */ | |
87ad11b0 | 4231 | if (frame_pointer_needed) |
4232 | { | |
a584fe8a | 4233 | offset = local_fsize; |
4234 | ||
4235 | /* If the current function calls __builtin_eh_return, then we need | |
4236 | to restore the saved EH data registers. */ | |
18d50ae6 | 4237 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 4238 | { |
4239 | unsigned int i, regno; | |
4240 | ||
4241 | for (i = 0; ; ++i) | |
4242 | { | |
4243 | regno = EH_RETURN_DATA_REGNO (i); | |
4244 | if (regno == INVALID_REGNUM) | |
4245 | break; | |
4246 | ||
68bc9ae6 | 4247 | load_reg (regno, offset, HARD_FRAME_POINTER_REGNUM); |
a584fe8a | 4248 | offset += UNITS_PER_WORD; |
4249 | } | |
4250 | } | |
4251 | ||
4252 | for (i = 18; i >= 4; i--) | |
3072d30e | 4253 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
87ad11b0 | 4254 | { |
68bc9ae6 | 4255 | load_reg (i, offset, HARD_FRAME_POINTER_REGNUM); |
6ec4380b | 4256 | offset += UNITS_PER_WORD; |
87ad11b0 | 4257 | } |
87ad11b0 | 4258 | } |
4259 | else | |
4260 | { | |
a584fe8a | 4261 | offset = local_fsize - actual_fsize; |
4262 | ||
4263 | /* If the current function calls __builtin_eh_return, then we need | |
4264 | to restore the saved EH data registers. */ | |
18d50ae6 | 4265 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 4266 | { |
4267 | unsigned int i, regno; | |
4268 | ||
4269 | for (i = 0; ; ++i) | |
4270 | { | |
4271 | regno = EH_RETURN_DATA_REGNO (i); | |
4272 | if (regno == INVALID_REGNUM) | |
4273 | break; | |
4274 | ||
4275 | /* Only for the first load. | |
4276 | merge_sp_adjust_with_load holds the register load | |
4277 | with which we will merge the sp adjustment. */ | |
4278 | if (merge_sp_adjust_with_load == 0 | |
4279 | && local_fsize == 0 | |
4280 | && VAL_14_BITS_P (-actual_fsize)) | |
4281 | merge_sp_adjust_with_load = regno; | |
4282 | else | |
4283 | load_reg (regno, offset, STACK_POINTER_REGNUM); | |
4284 | offset += UNITS_PER_WORD; | |
4285 | } | |
4286 | } | |
4287 | ||
4288 | for (i = 18; i >= 3; i--) | |
7f7c4869 | 4289 | { |
3072d30e | 4290 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
7f7c4869 | 4291 | { |
7f7c4869 | 4292 | /* Only for the first load. |
4293 | merge_sp_adjust_with_load holds the register load | |
4294 | with which we will merge the sp adjustment. */ | |
58361f39 | 4295 | if (merge_sp_adjust_with_load == 0 |
7f7c4869 | 4296 | && local_fsize == 0 |
58361f39 | 4297 | && VAL_14_BITS_P (-actual_fsize)) |
7f7c4869 | 4298 | merge_sp_adjust_with_load = i; |
4299 | else | |
6a2c16d6 | 4300 | load_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 4301 | offset += UNITS_PER_WORD; |
7f7c4869 | 4302 | } |
4303 | } | |
87ad11b0 | 4304 | } |
daee63dd | 4305 | |
87ad11b0 | 4306 | /* Align pointer properly (doubleword boundary). */ |
4307 | offset = (offset + 7) & ~7; | |
4308 | ||
daee63dd | 4309 | /* FP register restores. */ |
87ad11b0 | 4310 | if (save_fregs) |
87ad11b0 | 4311 | { |
daee63dd | 4312 | /* Adjust the register to index off of. */ |
a1ab4fa3 | 4313 | if (frame_pointer_needed) |
68bc9ae6 | 4314 | set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0); |
a1ab4fa3 | 4315 | else |
a584fe8a | 4316 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); |
daee63dd | 4317 | |
4318 | /* Actually do the restores now. */ | |
bac38c40 | 4319 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
3072d30e | 4320 | if (df_regs_ever_live_p (i) |
4321 | || (! TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
cc858176 | 4322 | { |
4323 | rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); | |
4324 | rtx dest = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 4325 | emit_move_insn (dest, src); |
cc858176 | 4326 | } |
87ad11b0 | 4327 | } |
daee63dd | 4328 | |
14660146 | 4329 | /* Emit a blockage insn here to keep these insns from being moved to |
4330 | an earlier spot in the epilogue, or into the main instruction stream. | |
4331 | ||
4332 | This is necessary as we must not cut the stack back before all the | |
4333 | restores are finished. */ | |
4334 | emit_insn (gen_blockage ()); | |
daee63dd | 4335 | |
9840d99d | 4336 | /* Reset stack pointer (and possibly frame pointer). The stack |
42819d4e | 4337 | pointer is initially set to fp + 64 to avoid a race condition. */ |
58361f39 | 4338 | if (frame_pointer_needed) |
87ad11b0 | 4339 | { |
cc858176 | 4340 | rtx delta = GEN_INT (-64); |
a584fe8a | 4341 | |
68bc9ae6 | 4342 | set_reg_plus_d (STACK_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM, 64, 0); |
4343 | emit_insn (gen_pre_load (hard_frame_pointer_rtx, | |
4344 | stack_pointer_rtx, delta)); | |
87ad11b0 | 4345 | } |
daee63dd | 4346 | /* If we were deferring a callee register restore, do it now. */ |
58361f39 | 4347 | else if (merge_sp_adjust_with_load) |
4348 | { | |
4349 | rtx delta = GEN_INT (-actual_fsize); | |
cc858176 | 4350 | rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load); |
a584fe8a | 4351 | |
4352 | emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)); | |
58361f39 | 4353 | } |
daee63dd | 4354 | else if (actual_fsize != 0) |
a584fe8a | 4355 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
4356 | - actual_fsize, 0); | |
58361f39 | 4357 | |
4358 | /* If we haven't restored %r2 yet (no frame pointer, and a stack | |
4359 | frame greater than 8k), do so now. */ | |
4360 | if (ret_off != 0) | |
6a2c16d6 | 4361 | load_reg (2, ret_off, STACK_POINTER_REGNUM); |
a584fe8a | 4362 | |
18d50ae6 | 4363 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 4364 | { |
4365 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
4366 | ||
4367 | emit_insn (gen_blockage ()); | |
4368 | emit_insn (TARGET_64BIT | |
4369 | ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa) | |
4370 | : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa)); | |
4371 | } | |
fed903e9 | 4372 | } |
4373 | ||
4374 | bool | |
4375 | pa_can_use_return_insn (void) | |
4376 | { | |
4377 | if (!reload_completed) | |
4378 | return false; | |
4379 | ||
4380 | if (frame_pointer_needed) | |
4381 | return false; | |
4382 | ||
4383 | if (df_regs_ever_live_p (2)) | |
4384 | return false; | |
4385 | ||
4386 | if (crtl->profile) | |
4387 | return false; | |
4388 | ||
e202682d | 4389 | return pa_compute_frame_size (get_frame_size (), 0) == 0; |
87ad11b0 | 4390 | } |
4391 | ||
d7e2f694 | 4392 | rtx |
5c1d8983 | 4393 | hppa_pic_save_rtx (void) |
cf3de5bb | 4394 | { |
d7e2f694 | 4395 | return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM); |
df6edefa | 4396 | } |
4397 | ||
bb1bc2ca | 4398 | #ifndef NO_DEFERRED_PROFILE_COUNTERS |
4399 | #define NO_DEFERRED_PROFILE_COUNTERS 0 | |
4400 | #endif | |
4401 | ||
bb1bc2ca | 4402 | |
4403 | /* Vector of funcdef numbers. */ | |
4404 | static VEC(int,heap) *funcdef_nos; | |
4405 | ||
4406 | /* Output deferred profile counters. */ | |
4407 | static void | |
4408 | output_deferred_profile_counters (void) | |
4409 | { | |
4410 | unsigned int i; | |
4411 | int align, n; | |
4412 | ||
4413 | if (VEC_empty (int, funcdef_nos)) | |
4414 | return; | |
4415 | ||
2f14b1f9 | 4416 | switch_to_section (data_section); |
bb1bc2ca | 4417 | align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE); |
4418 | ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT)); | |
4419 | ||
4420 | for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++) | |
4421 | { | |
4422 | targetm.asm_out.internal_label (asm_out_file, "LP", n); | |
4423 | assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1); | |
4424 | } | |
4425 | ||
4426 | VEC_free (int, heap, funcdef_nos); | |
4427 | } | |
4428 | ||
df6edefa | 4429 | void |
5c1d8983 | 4430 | hppa_profile_hook (int label_no) |
df6edefa | 4431 | { |
4da37e2f | 4432 | /* We use SImode for the address of the function in both 32 and |
4433 | 64-bit code to avoid having to provide DImode versions of the | |
4434 | lcla2 and load_offset_label_address insn patterns. */ | |
4435 | rtx reg = gen_reg_rtx (SImode); | |
4436 | rtx label_rtx = gen_label_rtx (); | |
a9ac13e4 | 4437 | rtx begin_label_rtx, call_insn; |
4438 | char begin_label_name[16]; | |
df6edefa | 4439 | |
a9ac13e4 | 4440 | ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL, |
b8a21949 | 4441 | label_no); |
4da37e2f | 4442 | begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name)); |
df6edefa | 4443 | |
4444 | if (TARGET_64BIT) | |
4445 | emit_move_insn (arg_pointer_rtx, | |
4446 | gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, | |
4447 | GEN_INT (64))); | |
4448 | ||
df6edefa | 4449 | emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2)); |
4450 | ||
80777cd8 | 4451 | /* The address of the function is loaded into %r25 with an instruction- |
4da37e2f | 4452 | relative sequence that avoids the use of relocations. The sequence |
4453 | is split so that the load_offset_label_address instruction can | |
4454 | occupy the delay slot of the call to _mcount. */ | |
4455 | if (TARGET_PA_20) | |
4456 | emit_insn (gen_lcla2 (reg, label_rtx)); | |
4457 | else | |
4458 | emit_insn (gen_lcla1 (reg, label_rtx)); | |
4459 | ||
4460 | emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25), | |
4461 | reg, begin_label_rtx, label_rtx)); | |
4462 | ||
bb1bc2ca | 4463 | #if !NO_DEFERRED_PROFILE_COUNTERS |
df6edefa | 4464 | { |
4465 | rtx count_label_rtx, addr, r24; | |
a9ac13e4 | 4466 | char count_label_name[16]; |
df6edefa | 4467 | |
bb1bc2ca | 4468 | VEC_safe_push (int, heap, funcdef_nos, label_no); |
a9ac13e4 | 4469 | ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no); |
4470 | count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name)); | |
df6edefa | 4471 | |
831a12d9 | 4472 | addr = force_reg (Pmode, count_label_rtx); |
df6edefa | 4473 | r24 = gen_rtx_REG (Pmode, 24); |
4474 | emit_move_insn (r24, addr); | |
4475 | ||
df6edefa | 4476 | call_insn = |
4da37e2f | 4477 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4478 | gen_rtx_SYMBOL_REF (Pmode, | |
4479 | "_mcount")), | |
4480 | GEN_INT (TARGET_64BIT ? 24 : 12))); | |
df6edefa | 4481 | |
4482 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24); | |
4483 | } | |
4484 | #else | |
4da37e2f | 4485 | |
df6edefa | 4486 | call_insn = |
4da37e2f | 4487 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4488 | gen_rtx_SYMBOL_REF (Pmode, | |
4489 | "_mcount")), | |
4490 | GEN_INT (TARGET_64BIT ? 16 : 8))); | |
4491 | ||
df6edefa | 4492 | #endif |
4493 | ||
4da37e2f | 4494 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25)); |
4495 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26)); | |
4496 | ||
df6edefa | 4497 | /* Indicate the _mcount call cannot throw, nor will it execute a |
4498 | non-local goto. */ | |
450040e5 | 4499 | make_reg_eh_region_note_nothrow_nononlocal (call_insn); |
cf3de5bb | 4500 | } |
4501 | ||
e07ff380 | 4502 | /* Fetch the return address for the frame COUNT steps up from |
4503 | the current frame, after the prologue. FRAMEADDR is the | |
4504 | frame pointer of the COUNT frame. | |
4505 | ||
f49b2e77 | 4506 | We want to ignore any export stub remnants here. To handle this, |
4507 | we examine the code at the return address, and if it is an export | |
4508 | stub, we return a memory rtx for the stub return address stored | |
4509 | at frame-24. | |
a6c6fd6c | 4510 | |
4511 | The value returned is used in two different ways: | |
4512 | ||
4513 | 1. To find a function's caller. | |
4514 | ||
4515 | 2. To change the return address for a function. | |
4516 | ||
4517 | This function handles most instances of case 1; however, it will | |
4518 | fail if there are two levels of stubs to execute on the return | |
4519 | path. The only way I believe that can happen is if the return value | |
4520 | needs a parameter relocation, which never happens for C code. | |
4521 | ||
4522 | This function handles most instances of case 2; however, it will | |
4523 | fail if we did not originally have stub code on the return path | |
f49b2e77 | 4524 | but will need stub code on the new return path. This can happen if |
a6c6fd6c | 4525 | the caller & callee are both in the main program, but the new |
f49b2e77 | 4526 | return location is in a shared library. */ |
e07ff380 | 4527 | |
4528 | rtx | |
e202682d | 4529 | pa_return_addr_rtx (int count, rtx frameaddr) |
e07ff380 | 4530 | { |
4531 | rtx label; | |
f49b2e77 | 4532 | rtx rp; |
e07ff380 | 4533 | rtx saved_rp; |
4534 | rtx ins; | |
4535 | ||
16309fef | 4536 | /* The instruction stream at the return address of a PA1.X export stub is: |
74f4459c | 4537 | |
4538 | 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp | |
4539 | 0x004010a1 | stub+12: ldsid (sr0,rp),r1 | |
4540 | 0x00011820 | stub+16: mtsp r1,sr0 | |
4541 | 0xe0400002 | stub+20: be,n 0(sr0,rp) | |
4542 | ||
4543 | 0xe0400002 must be specified as -532676606 so that it won't be | |
16309fef | 4544 | rejected as an invalid immediate operand on 64-bit hosts. |
74f4459c | 4545 | |
16309fef | 4546 | The instruction stream at the return address of a PA2.0 export stub is: |
4547 | ||
4548 | 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp | |
4549 | 0xe840d002 | stub+12: bve,n (rp) | |
4550 | */ | |
4551 | ||
4552 | HOST_WIDE_INT insns[4]; | |
4553 | int i, len; | |
74f4459c | 4554 | |
f49b2e77 | 4555 | if (count != 0) |
4556 | return NULL_RTX; | |
b29897dd | 4557 | |
f49b2e77 | 4558 | rp = get_hard_reg_initial_val (Pmode, 2); |
e07ff380 | 4559 | |
f49b2e77 | 4560 | if (TARGET_64BIT || TARGET_NO_SPACE_REGS) |
4561 | return rp; | |
e07ff380 | 4562 | |
74f4459c | 4563 | /* If there is no export stub then just use the value saved from |
4564 | the return pointer register. */ | |
4565 | ||
b29897dd | 4566 | saved_rp = gen_reg_rtx (Pmode); |
f49b2e77 | 4567 | emit_move_insn (saved_rp, rp); |
e07ff380 | 4568 | |
4569 | /* Get pointer to the instruction stream. We have to mask out the | |
4570 | privilege level from the two low order bits of the return address | |
4571 | pointer here so that ins will point to the start of the first | |
4572 | instruction that would have been executed if we returned. */ | |
f49b2e77 | 4573 | ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR)); |
e07ff380 | 4574 | label = gen_label_rtx (); |
4575 | ||
16309fef | 4576 | if (TARGET_PA_20) |
4577 | { | |
4578 | insns[0] = 0x4bc23fd1; | |
4579 | insns[1] = -398405630; | |
4580 | len = 2; | |
4581 | } | |
4582 | else | |
4583 | { | |
4584 | insns[0] = 0x4bc23fd1; | |
4585 | insns[1] = 0x004010a1; | |
4586 | insns[2] = 0x00011820; | |
4587 | insns[3] = -532676606; | |
4588 | len = 4; | |
4589 | } | |
4590 | ||
e07ff380 | 4591 | /* Check the instruction stream at the normal return address for the |
74f4459c | 4592 | export stub. If it is an export stub, than our return address is |
4593 | really in -24[frameaddr]. */ | |
e07ff380 | 4594 | |
16309fef | 4595 | for (i = 0; i < len; i++) |
74f4459c | 4596 | { |
29c05e22 | 4597 | rtx op0 = gen_rtx_MEM (SImode, plus_constant (Pmode, ins, i * 4)); |
74f4459c | 4598 | rtx op1 = GEN_INT (insns[i]); |
4599 | emit_cmp_and_jump_insns (op0, op1, NE, NULL, SImode, 0, label); | |
4600 | } | |
e07ff380 | 4601 | |
f49b2e77 | 4602 | /* Here we know that our return address points to an export |
e07ff380 | 4603 | stub. We don't want to return the address of the export stub, |
f49b2e77 | 4604 | but rather the return address of the export stub. That return |
4605 | address is stored at -24[frameaddr]. */ | |
e07ff380 | 4606 | |
f49b2e77 | 4607 | emit_move_insn (saved_rp, |
4608 | gen_rtx_MEM (Pmode, | |
4609 | memory_address (Pmode, | |
29c05e22 | 4610 | plus_constant (Pmode, frameaddr, |
f49b2e77 | 4611 | -24)))); |
e07ff380 | 4612 | |
4613 | emit_label (label); | |
74f4459c | 4614 | |
f49b2e77 | 4615 | return saved_rp; |
e07ff380 | 4616 | } |
4617 | ||
87ad11b0 | 4618 | void |
e202682d | 4619 | pa_emit_bcond_fp (rtx operands[]) |
87ad11b0 | 4620 | { |
74f4459c | 4621 | enum rtx_code code = GET_CODE (operands[0]); |
4622 | rtx operand0 = operands[1]; | |
4623 | rtx operand1 = operands[2]; | |
4624 | rtx label = operands[3]; | |
4625 | ||
4626 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0), | |
4627 | gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1))); | |
4628 | ||
ad851752 | 4629 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, |
4630 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
74f4459c | 4631 | gen_rtx_fmt_ee (NE, |
ad851752 | 4632 | VOIDmode, |
4633 | gen_rtx_REG (CCFPmode, 0), | |
4634 | const0_rtx), | |
74f4459c | 4635 | gen_rtx_LABEL_REF (VOIDmode, label), |
ad851752 | 4636 | pc_rtx))); |
87ad11b0 | 4637 | |
4638 | } | |
4639 | ||
8b49b3c7 | 4640 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
4641 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4642 | ||
747af5e7 | 4643 | static int |
5c1d8983 | 4644 | pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
8b49b3c7 | 4645 | { |
43048d2c | 4646 | enum attr_type attr_type; |
4647 | ||
cde3e16c | 4648 | /* Don't adjust costs for a pa8000 chip, also do not adjust any |
4649 | true dependencies as they are described with bypasses now. */ | |
4650 | if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0) | |
342aabd9 | 4651 | return cost; |
4652 | ||
d402da4b | 4653 | if (! recog_memoized (insn)) |
4654 | return 0; | |
8b49b3c7 | 4655 | |
43048d2c | 4656 | attr_type = get_attr_type (insn); |
4657 | ||
ecf2283d | 4658 | switch (REG_NOTE_KIND (link)) |
8b49b3c7 | 4659 | { |
ecf2283d | 4660 | case REG_DEP_ANTI: |
8b49b3c7 | 4661 | /* Anti dependency; DEP_INSN reads a register that INSN writes some |
4662 | cycles later. */ | |
4663 | ||
43048d2c | 4664 | if (attr_type == TYPE_FPLOAD) |
8b49b3c7 | 4665 | { |
d402da4b | 4666 | rtx pat = PATTERN (insn); |
4667 | rtx dep_pat = PATTERN (dep_insn); | |
4668 | if (GET_CODE (pat) == PARALLEL) | |
4669 | { | |
4670 | /* This happens for the fldXs,mb patterns. */ | |
4671 | pat = XVECEXP (pat, 0, 0); | |
4672 | } | |
4673 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
8b49b3c7 | 4674 | /* If this happens, we have to extend this to schedule |
d402da4b | 4675 | optimally. Return 0 for now. */ |
4676 | return 0; | |
8b49b3c7 | 4677 | |
d402da4b | 4678 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) |
8b49b3c7 | 4679 | { |
d402da4b | 4680 | if (! recog_memoized (dep_insn)) |
4681 | return 0; | |
8b49b3c7 | 4682 | switch (get_attr_type (dep_insn)) |
4683 | { | |
4684 | case TYPE_FPALU: | |
134b4858 | 4685 | case TYPE_FPMULSGL: |
4686 | case TYPE_FPMULDBL: | |
8b49b3c7 | 4687 | case TYPE_FPDIVSGL: |
4688 | case TYPE_FPDIVDBL: | |
4689 | case TYPE_FPSQRTSGL: | |
4690 | case TYPE_FPSQRTDBL: | |
d402da4b | 4691 | /* A fpload can't be issued until one cycle before a |
01cc3b75 | 4692 | preceding arithmetic operation has finished if |
d402da4b | 4693 | the target of the fpload is any of the sources |
4694 | (or destination) of the arithmetic operation. */ | |
cde3e16c | 4695 | return insn_default_latency (dep_insn) - 1; |
134b4858 | 4696 | |
4697 | default: | |
4698 | return 0; | |
4699 | } | |
4700 | } | |
4701 | } | |
43048d2c | 4702 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4703 | { |
4704 | rtx pat = PATTERN (insn); | |
4705 | rtx dep_pat = PATTERN (dep_insn); | |
4706 | if (GET_CODE (pat) == PARALLEL) | |
4707 | { | |
4708 | /* This happens for the fldXs,mb patterns. */ | |
4709 | pat = XVECEXP (pat, 0, 0); | |
4710 | } | |
4711 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4712 | /* If this happens, we have to extend this to schedule | |
4713 | optimally. Return 0 for now. */ | |
4714 | return 0; | |
4715 | ||
4716 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) | |
4717 | { | |
4718 | if (! recog_memoized (dep_insn)) | |
4719 | return 0; | |
4720 | switch (get_attr_type (dep_insn)) | |
4721 | { | |
4722 | case TYPE_FPDIVSGL: | |
4723 | case TYPE_FPDIVDBL: | |
4724 | case TYPE_FPSQRTSGL: | |
4725 | case TYPE_FPSQRTDBL: | |
4726 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4727 | preceding divide or sqrt operation has finished if |
134b4858 | 4728 | the target of the ALU flop is any of the sources |
4729 | (or destination) of the divide or sqrt operation. */ | |
cde3e16c | 4730 | return insn_default_latency (dep_insn) - 2; |
8b49b3c7 | 4731 | |
4732 | default: | |
4733 | return 0; | |
4734 | } | |
4735 | } | |
4736 | } | |
4737 | ||
4738 | /* For other anti dependencies, the cost is 0. */ | |
4739 | return 0; | |
ecf2283d | 4740 | |
4741 | case REG_DEP_OUTPUT: | |
134b4858 | 4742 | /* Output dependency; DEP_INSN writes a register that INSN writes some |
4743 | cycles later. */ | |
43048d2c | 4744 | if (attr_type == TYPE_FPLOAD) |
134b4858 | 4745 | { |
4746 | rtx pat = PATTERN (insn); | |
4747 | rtx dep_pat = PATTERN (dep_insn); | |
4748 | if (GET_CODE (pat) == PARALLEL) | |
4749 | { | |
4750 | /* This happens for the fldXs,mb patterns. */ | |
4751 | pat = XVECEXP (pat, 0, 0); | |
4752 | } | |
4753 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4754 | /* If this happens, we have to extend this to schedule | |
4755 | optimally. Return 0 for now. */ | |
4756 | return 0; | |
4757 | ||
4758 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4759 | { | |
4760 | if (! recog_memoized (dep_insn)) | |
4761 | return 0; | |
4762 | switch (get_attr_type (dep_insn)) | |
4763 | { | |
4764 | case TYPE_FPALU: | |
4765 | case TYPE_FPMULSGL: | |
4766 | case TYPE_FPMULDBL: | |
4767 | case TYPE_FPDIVSGL: | |
4768 | case TYPE_FPDIVDBL: | |
4769 | case TYPE_FPSQRTSGL: | |
4770 | case TYPE_FPSQRTDBL: | |
4771 | /* A fpload can't be issued until one cycle before a | |
01cc3b75 | 4772 | preceding arithmetic operation has finished if |
134b4858 | 4773 | the target of the fpload is the destination of the |
bea4bad2 | 4774 | arithmetic operation. |
4775 | ||
4776 | Exception: For PA7100LC, PA7200 and PA7300, the cost | |
4777 | is 3 cycles, unless they bundle together. We also | |
4778 | pay the penalty if the second insn is a fpload. */ | |
cde3e16c | 4779 | return insn_default_latency (dep_insn) - 1; |
8b49b3c7 | 4780 | |
134b4858 | 4781 | default: |
4782 | return 0; | |
4783 | } | |
4784 | } | |
4785 | } | |
43048d2c | 4786 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4787 | { |
4788 | rtx pat = PATTERN (insn); | |
4789 | rtx dep_pat = PATTERN (dep_insn); | |
4790 | if (GET_CODE (pat) == PARALLEL) | |
4791 | { | |
4792 | /* This happens for the fldXs,mb patterns. */ | |
4793 | pat = XVECEXP (pat, 0, 0); | |
4794 | } | |
4795 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4796 | /* If this happens, we have to extend this to schedule | |
4797 | optimally. Return 0 for now. */ | |
4798 | return 0; | |
4799 | ||
4800 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4801 | { | |
4802 | if (! recog_memoized (dep_insn)) | |
4803 | return 0; | |
4804 | switch (get_attr_type (dep_insn)) | |
4805 | { | |
4806 | case TYPE_FPDIVSGL: | |
4807 | case TYPE_FPDIVDBL: | |
4808 | case TYPE_FPSQRTSGL: | |
4809 | case TYPE_FPSQRTDBL: | |
4810 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4811 | preceding divide or sqrt operation has finished if |
134b4858 | 4812 | the target of the ALU flop is also the target of |
3398e91d | 4813 | the divide or sqrt operation. */ |
cde3e16c | 4814 | return insn_default_latency (dep_insn) - 2; |
134b4858 | 4815 | |
4816 | default: | |
4817 | return 0; | |
4818 | } | |
4819 | } | |
4820 | } | |
4821 | ||
4822 | /* For other output dependencies, the cost is 0. */ | |
4823 | return 0; | |
ecf2283d | 4824 | |
4825 | default: | |
4826 | gcc_unreachable (); | |
134b4858 | 4827 | } |
8b49b3c7 | 4828 | } |
87ad11b0 | 4829 | |
747af5e7 | 4830 | /* Adjust scheduling priorities. We use this to try and keep addil |
4831 | and the next use of %r1 close together. */ | |
4832 | static int | |
5c1d8983 | 4833 | pa_adjust_priority (rtx insn, int priority) |
747af5e7 | 4834 | { |
4835 | rtx set = single_set (insn); | |
4836 | rtx src, dest; | |
4837 | if (set) | |
4838 | { | |
4839 | src = SET_SRC (set); | |
4840 | dest = SET_DEST (set); | |
4841 | if (GET_CODE (src) == LO_SUM | |
4842 | && symbolic_operand (XEXP (src, 1), VOIDmode) | |
4843 | && ! read_only_operand (XEXP (src, 1), VOIDmode)) | |
4844 | priority >>= 3; | |
4845 | ||
4846 | else if (GET_CODE (src) == MEM | |
4847 | && GET_CODE (XEXP (src, 0)) == LO_SUM | |
4848 | && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode) | |
4849 | && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode)) | |
4850 | priority >>= 1; | |
4851 | ||
4852 | else if (GET_CODE (dest) == MEM | |
4853 | && GET_CODE (XEXP (dest, 0)) == LO_SUM | |
4854 | && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode) | |
4855 | && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)) | |
4856 | priority >>= 3; | |
4857 | } | |
4858 | return priority; | |
4859 | } | |
4860 | ||
4861 | /* The 700 can only issue a single insn at a time. | |
4862 | The 7XXX processors can issue two insns at a time. | |
4863 | The 8000 can issue 4 insns at a time. */ | |
4864 | static int | |
5c1d8983 | 4865 | pa_issue_rate (void) |
747af5e7 | 4866 | { |
4867 | switch (pa_cpu) | |
4868 | { | |
4869 | case PROCESSOR_700: return 1; | |
4870 | case PROCESSOR_7100: return 2; | |
4871 | case PROCESSOR_7100LC: return 2; | |
4872 | case PROCESSOR_7200: return 2; | |
bea4bad2 | 4873 | case PROCESSOR_7300: return 2; |
747af5e7 | 4874 | case PROCESSOR_8000: return 4; |
4875 | ||
4876 | default: | |
ecf2283d | 4877 | gcc_unreachable (); |
747af5e7 | 4878 | } |
4879 | } | |
4880 | ||
4881 | ||
4882 | ||
58e17b0b | 4883 | /* Return any length adjustment needed by INSN which already has its length |
6d36483b | 4884 | computed as LENGTH. Return zero if no adjustment is necessary. |
58e17b0b | 4885 | |
5fbd5940 | 4886 | For the PA: function calls, millicode calls, and backwards short |
6d36483b | 4887 | conditional branches with unfilled delay slots need an adjustment by +1 |
5fbd5940 | 4888 | (to account for the NOP which will be inserted into the instruction stream). |
58e17b0b | 4889 | |
4890 | Also compute the length of an inline block move here as it is too | |
5fbd5940 | 4891 | complicated to express as a length attribute in pa.md. */ |
58e17b0b | 4892 | int |
5c1d8983 | 4893 | pa_adjust_insn_length (rtx insn, int length) |
58e17b0b | 4894 | { |
4895 | rtx pat = PATTERN (insn); | |
4896 | ||
faf3f8c1 | 4897 | /* Jumps inside switch tables which have unfilled delay slots need |
4898 | adjustment. */ | |
4899 | if (GET_CODE (insn) == JUMP_INSN | |
b932f66c | 4900 | && GET_CODE (pat) == PARALLEL |
4901 | && get_attr_type (insn) == TYPE_BTABLE_BRANCH) | |
3b1e673e | 4902 | return 4; |
58e17b0b | 4903 | /* Millicode insn with an unfilled delay slot. */ |
4904 | else if (GET_CODE (insn) == INSN | |
4905 | && GET_CODE (pat) != SEQUENCE | |
4906 | && GET_CODE (pat) != USE | |
4907 | && GET_CODE (pat) != CLOBBER | |
4908 | && get_attr_type (insn) == TYPE_MILLI) | |
5a1231ef | 4909 | return 4; |
58e17b0b | 4910 | /* Block move pattern. */ |
4911 | else if (GET_CODE (insn) == INSN | |
4912 | && GET_CODE (pat) == PARALLEL | |
f2ebcf32 | 4913 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET |
58e17b0b | 4914 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM |
4915 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM | |
4916 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode | |
4917 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode) | |
008c057d | 4918 | return compute_movmem_length (insn) - 4; |
a7e1bb24 | 4919 | /* Block clear pattern. */ |
4920 | else if (GET_CODE (insn) == INSN | |
4921 | && GET_CODE (pat) == PARALLEL | |
4922 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET | |
4923 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM | |
4924 | && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx | |
4925 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode) | |
008c057d | 4926 | return compute_clrmem_length (insn) - 4; |
58e17b0b | 4927 | /* Conditional branch with an unfilled delay slot. */ |
5fbd5940 | 4928 | else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn)) |
4929 | { | |
4930 | /* Adjust a short backwards conditional with an unfilled delay slot. */ | |
4931 | if (GET_CODE (pat) == SET | |
5a1231ef | 4932 | && length == 4 |
372b3fe2 | 4933 | && JUMP_LABEL (insn) != NULL_RTX |
5fbd5940 | 4934 | && ! forward_branch_p (insn)) |
5a1231ef | 4935 | return 4; |
546a40bd | 4936 | else if (GET_CODE (pat) == PARALLEL |
4937 | && get_attr_type (insn) == TYPE_PARALLEL_BRANCH | |
4938 | && length == 4) | |
4939 | return 4; | |
5fbd5940 | 4940 | /* Adjust dbra insn with short backwards conditional branch with |
6d36483b | 4941 | unfilled delay slot -- only for case where counter is in a |
6dc3b0d9 | 4942 | general register register. */ |
5fbd5940 | 4943 | else if (GET_CODE (pat) == PARALLEL |
4944 | && GET_CODE (XVECEXP (pat, 0, 1)) == SET | |
4945 | && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG | |
6d36483b | 4946 | && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0)) |
5a1231ef | 4947 | && length == 4 |
5fbd5940 | 4948 | && ! forward_branch_p (insn)) |
5a1231ef | 4949 | return 4; |
5fbd5940 | 4950 | else |
4951 | return 0; | |
4952 | } | |
546a40bd | 4953 | return 0; |
58e17b0b | 4954 | } |
4955 | ||
93d3ee56 | 4956 | /* Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook. */ |
4957 | ||
4958 | static bool | |
4959 | pa_print_operand_punct_valid_p (unsigned char code) | |
4960 | { | |
4961 | if (code == '@' | |
4962 | || code == '#' | |
4963 | || code == '*' | |
4964 | || code == '^') | |
4965 | return true; | |
4966 | ||
4967 | return false; | |
4968 | } | |
4969 | ||
87ad11b0 | 4970 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
4971 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
4972 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
4973 | ||
4974 | void | |
e202682d | 4975 | pa_print_operand (FILE *file, rtx x, int code) |
87ad11b0 | 4976 | { |
4977 | switch (code) | |
4978 | { | |
4979 | case '#': | |
4980 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
4981 | if (dbr_sequence_length () == 0) | |
4982 | fputs ("\n\tnop", file); | |
4983 | return; | |
4984 | case '*': | |
87fcb603 | 4985 | /* Output a nullification completer if there's nothing for the */ |
6d36483b | 4986 | /* delay slot or nullification is requested. */ |
87ad11b0 | 4987 | if (dbr_sequence_length () == 0 || |
4988 | (final_sequence && | |
4989 | INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))) | |
4990 | fputs (",n", file); | |
4991 | return; | |
4992 | case 'R': | |
4993 | /* Print out the second register name of a register pair. | |
4994 | I.e., R (6) => 7. */ | |
ea52c577 | 4995 | fputs (reg_names[REGNO (x) + 1], file); |
87ad11b0 | 4996 | return; |
4997 | case 'r': | |
6dc3b0d9 | 4998 | /* A register or zero. */ |
891b55b4 | 4999 | if (x == const0_rtx |
5000 | || (x == CONST0_RTX (DFmode)) | |
5001 | || (x == CONST0_RTX (SFmode))) | |
87ad11b0 | 5002 | { |
c6ae275c | 5003 | fputs ("%r0", file); |
5004 | return; | |
5005 | } | |
5006 | else | |
5007 | break; | |
5008 | case 'f': | |
6dc3b0d9 | 5009 | /* A register or zero (floating point). */ |
c6ae275c | 5010 | if (x == const0_rtx |
5011 | || (x == CONST0_RTX (DFmode)) | |
5012 | || (x == CONST0_RTX (SFmode))) | |
5013 | { | |
5014 | fputs ("%fr0", file); | |
87ad11b0 | 5015 | return; |
5016 | } | |
5017 | else | |
5018 | break; | |
2d14b1f0 | 5019 | case 'A': |
5020 | { | |
5021 | rtx xoperands[2]; | |
5022 | ||
5023 | xoperands[0] = XEXP (XEXP (x, 0), 0); | |
5024 | xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0); | |
e202682d | 5025 | pa_output_global_address (file, xoperands[1], 0); |
2d14b1f0 | 5026 | fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]); |
5027 | return; | |
5028 | } | |
5029 | ||
c8975385 | 5030 | case 'C': /* Plain (C)ondition */ |
87ad11b0 | 5031 | case 'X': |
5032 | switch (GET_CODE (x)) | |
6d36483b | 5033 | { |
87ad11b0 | 5034 | case EQ: |
9c0ac0fd | 5035 | fputs ("=", file); break; |
87ad11b0 | 5036 | case NE: |
9c0ac0fd | 5037 | fputs ("<>", file); break; |
87ad11b0 | 5038 | case GT: |
9c0ac0fd | 5039 | fputs (">", file); break; |
87ad11b0 | 5040 | case GE: |
9c0ac0fd | 5041 | fputs (">=", file); break; |
87ad11b0 | 5042 | case GEU: |
9c0ac0fd | 5043 | fputs (">>=", file); break; |
87ad11b0 | 5044 | case GTU: |
9c0ac0fd | 5045 | fputs (">>", file); break; |
87ad11b0 | 5046 | case LT: |
9c0ac0fd | 5047 | fputs ("<", file); break; |
87ad11b0 | 5048 | case LE: |
9c0ac0fd | 5049 | fputs ("<=", file); break; |
87ad11b0 | 5050 | case LEU: |
9c0ac0fd | 5051 | fputs ("<<=", file); break; |
87ad11b0 | 5052 | case LTU: |
9c0ac0fd | 5053 | fputs ("<<", file); break; |
87ad11b0 | 5054 | default: |
ecf2283d | 5055 | gcc_unreachable (); |
87ad11b0 | 5056 | } |
5057 | return; | |
c8975385 | 5058 | case 'N': /* Condition, (N)egated */ |
87ad11b0 | 5059 | switch (GET_CODE (x)) |
5060 | { | |
5061 | case EQ: | |
9c0ac0fd | 5062 | fputs ("<>", file); break; |
87ad11b0 | 5063 | case NE: |
9c0ac0fd | 5064 | fputs ("=", file); break; |
87ad11b0 | 5065 | case GT: |
9c0ac0fd | 5066 | fputs ("<=", file); break; |
87ad11b0 | 5067 | case GE: |
9c0ac0fd | 5068 | fputs ("<", file); break; |
87ad11b0 | 5069 | case GEU: |
9c0ac0fd | 5070 | fputs ("<<", file); break; |
87ad11b0 | 5071 | case GTU: |
9c0ac0fd | 5072 | fputs ("<<=", file); break; |
87ad11b0 | 5073 | case LT: |
9c0ac0fd | 5074 | fputs (">=", file); break; |
87ad11b0 | 5075 | case LE: |
9c0ac0fd | 5076 | fputs (">", file); break; |
87ad11b0 | 5077 | case LEU: |
9c0ac0fd | 5078 | fputs (">>", file); break; |
87ad11b0 | 5079 | case LTU: |
9c0ac0fd | 5080 | fputs (">>=", file); break; |
87ad11b0 | 5081 | default: |
ecf2283d | 5082 | gcc_unreachable (); |
87ad11b0 | 5083 | } |
5084 | return; | |
ea52c577 | 5085 | /* For floating point comparisons. Note that the output |
321c1598 | 5086 | predicates are the complement of the desired mode. The |
5087 | conditions for GT, GE, LT, LE and LTGT cause an invalid | |
5088 | operation exception if the result is unordered and this | |
5089 | exception is enabled in the floating-point status register. */ | |
61230bc9 | 5090 | case 'Y': |
5091 | switch (GET_CODE (x)) | |
5092 | { | |
5093 | case EQ: | |
9c0ac0fd | 5094 | fputs ("!=", file); break; |
61230bc9 | 5095 | case NE: |
9c0ac0fd | 5096 | fputs ("=", file); break; |
61230bc9 | 5097 | case GT: |
32509e56 | 5098 | fputs ("!>", file); break; |
61230bc9 | 5099 | case GE: |
32509e56 | 5100 | fputs ("!>=", file); break; |
61230bc9 | 5101 | case LT: |
32509e56 | 5102 | fputs ("!<", file); break; |
61230bc9 | 5103 | case LE: |
32509e56 | 5104 | fputs ("!<=", file); break; |
5105 | case LTGT: | |
5106 | fputs ("!<>", file); break; | |
5107 | case UNLE: | |
321c1598 | 5108 | fputs ("!?<=", file); break; |
32509e56 | 5109 | case UNLT: |
321c1598 | 5110 | fputs ("!?<", file); break; |
32509e56 | 5111 | case UNGE: |
321c1598 | 5112 | fputs ("!?>=", file); break; |
32509e56 | 5113 | case UNGT: |
321c1598 | 5114 | fputs ("!?>", file); break; |
32509e56 | 5115 | case UNEQ: |
321c1598 | 5116 | fputs ("!?=", file); break; |
32509e56 | 5117 | case UNORDERED: |
321c1598 | 5118 | fputs ("!?", file); break; |
32509e56 | 5119 | case ORDERED: |
321c1598 | 5120 | fputs ("?", file); break; |
61230bc9 | 5121 | default: |
ecf2283d | 5122 | gcc_unreachable (); |
61230bc9 | 5123 | } |
5124 | return; | |
c8975385 | 5125 | case 'S': /* Condition, operands are (S)wapped. */ |
5126 | switch (GET_CODE (x)) | |
5127 | { | |
5128 | case EQ: | |
9c0ac0fd | 5129 | fputs ("=", file); break; |
c8975385 | 5130 | case NE: |
9c0ac0fd | 5131 | fputs ("<>", file); break; |
c8975385 | 5132 | case GT: |
9c0ac0fd | 5133 | fputs ("<", file); break; |
c8975385 | 5134 | case GE: |
9c0ac0fd | 5135 | fputs ("<=", file); break; |
c8975385 | 5136 | case GEU: |
9c0ac0fd | 5137 | fputs ("<<=", file); break; |
c8975385 | 5138 | case GTU: |
9c0ac0fd | 5139 | fputs ("<<", file); break; |
c8975385 | 5140 | case LT: |
9c0ac0fd | 5141 | fputs (">", file); break; |
c8975385 | 5142 | case LE: |
9c0ac0fd | 5143 | fputs (">=", file); break; |
c8975385 | 5144 | case LEU: |
9c0ac0fd | 5145 | fputs (">>=", file); break; |
c8975385 | 5146 | case LTU: |
9c0ac0fd | 5147 | fputs (">>", file); break; |
c8975385 | 5148 | default: |
ecf2283d | 5149 | gcc_unreachable (); |
6d36483b | 5150 | } |
c8975385 | 5151 | return; |
5152 | case 'B': /* Condition, (B)oth swapped and negate. */ | |
5153 | switch (GET_CODE (x)) | |
5154 | { | |
5155 | case EQ: | |
9c0ac0fd | 5156 | fputs ("<>", file); break; |
c8975385 | 5157 | case NE: |
9c0ac0fd | 5158 | fputs ("=", file); break; |
c8975385 | 5159 | case GT: |
9c0ac0fd | 5160 | fputs (">=", file); break; |
c8975385 | 5161 | case GE: |
9c0ac0fd | 5162 | fputs (">", file); break; |
c8975385 | 5163 | case GEU: |
9c0ac0fd | 5164 | fputs (">>", file); break; |
c8975385 | 5165 | case GTU: |
9c0ac0fd | 5166 | fputs (">>=", file); break; |
c8975385 | 5167 | case LT: |
9c0ac0fd | 5168 | fputs ("<=", file); break; |
c8975385 | 5169 | case LE: |
9c0ac0fd | 5170 | fputs ("<", file); break; |
c8975385 | 5171 | case LEU: |
9c0ac0fd | 5172 | fputs ("<<", file); break; |
c8975385 | 5173 | case LTU: |
9c0ac0fd | 5174 | fputs ("<<=", file); break; |
c8975385 | 5175 | default: |
ecf2283d | 5176 | gcc_unreachable (); |
6d36483b | 5177 | } |
c8975385 | 5178 | return; |
5179 | case 'k': | |
ecf2283d | 5180 | gcc_assert (GET_CODE (x) == CONST_INT); |
5181 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x)); | |
5182 | return; | |
5e3c5739 | 5183 | case 'Q': |
ecf2283d | 5184 | gcc_assert (GET_CODE (x) == CONST_INT); |
5185 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63)); | |
5186 | return; | |
e5965947 | 5187 | case 'L': |
ecf2283d | 5188 | gcc_assert (GET_CODE (x) == CONST_INT); |
5189 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31)); | |
5190 | return; | |
3a16146d | 5191 | case 'O': |
ecf2283d | 5192 | gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0); |
5193 | fprintf (file, "%d", exact_log2 (INTVAL (x))); | |
5194 | return; | |
5e3c5739 | 5195 | case 'p': |
ecf2283d | 5196 | gcc_assert (GET_CODE (x) == CONST_INT); |
5197 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63)); | |
5198 | return; | |
e5965947 | 5199 | case 'P': |
ecf2283d | 5200 | gcc_assert (GET_CODE (x) == CONST_INT); |
5201 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31)); | |
5202 | return; | |
c8975385 | 5203 | case 'I': |
5204 | if (GET_CODE (x) == CONST_INT) | |
5205 | fputs ("i", file); | |
5206 | return; | |
87ad11b0 | 5207 | case 'M': |
27ef382d | 5208 | case 'F': |
87ad11b0 | 5209 | switch (GET_CODE (XEXP (x, 0))) |
5210 | { | |
5211 | case PRE_DEC: | |
5212 | case PRE_INC: | |
e4065f95 | 5213 | if (ASSEMBLER_DIALECT == 0) |
5214 | fputs ("s,mb", file); | |
5215 | else | |
5216 | fputs (",mb", file); | |
87ad11b0 | 5217 | break; |
5218 | case POST_DEC: | |
5219 | case POST_INC: | |
e4065f95 | 5220 | if (ASSEMBLER_DIALECT == 0) |
5221 | fputs ("s,ma", file); | |
5222 | else | |
5223 | fputs (",ma", file); | |
87ad11b0 | 5224 | break; |
27ef382d | 5225 | case PLUS: |
dbd3d89d | 5226 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5227 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5228 | { | |
5229 | if (ASSEMBLER_DIALECT == 0) | |
5230 | fputs ("x", file); | |
5231 | } | |
5232 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
5233 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) | |
e4065f95 | 5234 | { |
5235 | if (ASSEMBLER_DIALECT == 0) | |
5236 | fputs ("x,s", file); | |
5237 | else | |
5238 | fputs (",s", file); | |
5239 | } | |
5240 | else if (code == 'F' && ASSEMBLER_DIALECT == 0) | |
27ef382d | 5241 | fputs ("s", file); |
87ad11b0 | 5242 | break; |
5243 | default: | |
e4065f95 | 5244 | if (code == 'F' && ASSEMBLER_DIALECT == 0) |
27ef382d | 5245 | fputs ("s", file); |
87ad11b0 | 5246 | break; |
5247 | } | |
5248 | return; | |
5249 | case 'G': | |
e202682d | 5250 | pa_output_global_address (file, x, 0); |
f9333726 | 5251 | return; |
5252 | case 'H': | |
e202682d | 5253 | pa_output_global_address (file, x, 1); |
87ad11b0 | 5254 | return; |
5255 | case 0: /* Don't do anything special */ | |
5256 | break; | |
42faba01 | 5257 | case 'Z': |
5258 | { | |
5259 | unsigned op[3]; | |
fb22aedc | 5260 | compute_zdepwi_operands (INTVAL (x), op); |
42faba01 | 5261 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); |
5262 | return; | |
5263 | } | |
5e3c5739 | 5264 | case 'z': |
5265 | { | |
5266 | unsigned op[3]; | |
5267 | compute_zdepdi_operands (INTVAL (x), op); | |
5268 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); | |
5269 | return; | |
5270 | } | |
c9cc98e1 | 5271 | case 'c': |
5272 | /* We can get here from a .vtable_inherit due to our | |
5273 | CONSTANT_ADDRESS_P rejecting perfectly good constant | |
5274 | addresses. */ | |
5275 | break; | |
87ad11b0 | 5276 | default: |
ecf2283d | 5277 | gcc_unreachable (); |
87ad11b0 | 5278 | } |
5279 | if (GET_CODE (x) == REG) | |
df0651dc | 5280 | { |
35661368 | 5281 | fputs (reg_names [REGNO (x)], file); |
5e3c5739 | 5282 | if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4) |
5283 | { | |
5284 | fputs ("R", file); | |
5285 | return; | |
5286 | } | |
5287 | if (FP_REG_P (x) | |
5288 | && GET_MODE_SIZE (GET_MODE (x)) <= 4 | |
5289 | && (REGNO (x) & 1) == 0) | |
35661368 | 5290 | fputs ("L", file); |
df0651dc | 5291 | } |
87ad11b0 | 5292 | else if (GET_CODE (x) == MEM) |
5293 | { | |
5294 | int size = GET_MODE_SIZE (GET_MODE (x)); | |
f7dff90d | 5295 | rtx base = NULL_RTX; |
87ad11b0 | 5296 | switch (GET_CODE (XEXP (x, 0))) |
5297 | { | |
5298 | case PRE_DEC: | |
5299 | case POST_DEC: | |
5e3c5739 | 5300 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 5301 | fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5302 | break; |
5303 | case PRE_INC: | |
5304 | case POST_INC: | |
5e3c5739 | 5305 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 5306 | fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5307 | break; |
dbd3d89d | 5308 | case PLUS: |
5309 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT) | |
34940871 | 5310 | fprintf (file, "%s(%s)", |
27ef382d | 5311 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))], |
5312 | reg_names [REGNO (XEXP (XEXP (x, 0), 1))]); | |
dbd3d89d | 5313 | else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) |
34940871 | 5314 | fprintf (file, "%s(%s)", |
27ef382d | 5315 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))], |
5316 | reg_names [REGNO (XEXP (XEXP (x, 0), 0))]); | |
dbd3d89d | 5317 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5318 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5319 | { | |
5320 | /* Because the REG_POINTER flag can get lost during reload, | |
5321 | GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the | |
5322 | index and base registers in the combined move patterns. */ | |
5323 | rtx base = XEXP (XEXP (x, 0), 1); | |
5324 | rtx index = XEXP (XEXP (x, 0), 0); | |
5325 | ||
5326 | fprintf (file, "%s(%s)", | |
5327 | reg_names [REGNO (index)], reg_names [REGNO (base)]); | |
5328 | } | |
27ef382d | 5329 | else |
5330 | output_address (XEXP (x, 0)); | |
87ad11b0 | 5331 | break; |
dbd3d89d | 5332 | default: |
5333 | output_address (XEXP (x, 0)); | |
5334 | break; | |
87ad11b0 | 5335 | } |
5336 | } | |
87ad11b0 | 5337 | else |
5338 | output_addr_const (file, x); | |
5339 | } | |
5340 | ||
6dc3b0d9 | 5341 | /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */ |
87ad11b0 | 5342 | |
5343 | void | |
e202682d | 5344 | pa_output_global_address (FILE *file, rtx x, int round_constant) |
87ad11b0 | 5345 | { |
2ee034bc | 5346 | |
5347 | /* Imagine (high (const (plus ...))). */ | |
5348 | if (GET_CODE (x) == HIGH) | |
5349 | x = XEXP (x, 0); | |
5350 | ||
611a88e1 | 5351 | if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode)) |
5f43b4f6 | 5352 | output_addr_const (file, x); |
b4a7bf10 | 5353 | else if (GET_CODE (x) == SYMBOL_REF && !flag_pic) |
87ad11b0 | 5354 | { |
5f43b4f6 | 5355 | output_addr_const (file, x); |
9c0ac0fd | 5356 | fputs ("-$global$", file); |
87ad11b0 | 5357 | } |
5358 | else if (GET_CODE (x) == CONST) | |
5359 | { | |
611a88e1 | 5360 | const char *sep = ""; |
87ad11b0 | 5361 | int offset = 0; /* assembler wants -$global$ at end */ |
33ae0dba | 5362 | rtx base = NULL_RTX; |
6d36483b | 5363 | |
ecf2283d | 5364 | switch (GET_CODE (XEXP (XEXP (x, 0), 0))) |
87ad11b0 | 5365 | { |
ecf2283d | 5366 | case SYMBOL_REF: |
87ad11b0 | 5367 | base = XEXP (XEXP (x, 0), 0); |
5368 | output_addr_const (file, base); | |
ecf2283d | 5369 | break; |
5370 | case CONST_INT: | |
5371 | offset = INTVAL (XEXP (XEXP (x, 0), 0)); | |
5372 | break; | |
5373 | default: | |
5374 | gcc_unreachable (); | |
87ad11b0 | 5375 | } |
87ad11b0 | 5376 | |
ecf2283d | 5377 | switch (GET_CODE (XEXP (XEXP (x, 0), 1))) |
87ad11b0 | 5378 | { |
ecf2283d | 5379 | case SYMBOL_REF: |
87ad11b0 | 5380 | base = XEXP (XEXP (x, 0), 1); |
5381 | output_addr_const (file, base); | |
ecf2283d | 5382 | break; |
5383 | case CONST_INT: | |
5384 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
5385 | break; | |
5386 | default: | |
5387 | gcc_unreachable (); | |
87ad11b0 | 5388 | } |
87ad11b0 | 5389 | |
f9333726 | 5390 | /* How bogus. The compiler is apparently responsible for |
5391 | rounding the constant if it uses an LR field selector. | |
5392 | ||
5393 | The linker and/or assembler seem a better place since | |
5394 | they have to do this kind of thing already. | |
5395 | ||
5396 | If we fail to do this, HP's optimizing linker may eliminate | |
5397 | an addil, but not update the ldw/stw/ldo instruction that | |
5398 | uses the result of the addil. */ | |
5399 | if (round_constant) | |
5400 | offset = ((offset + 0x1000) & ~0x1fff); | |
5401 | ||
ecf2283d | 5402 | switch (GET_CODE (XEXP (x, 0))) |
87ad11b0 | 5403 | { |
ecf2283d | 5404 | case PLUS: |
87ad11b0 | 5405 | if (offset < 0) |
5406 | { | |
5407 | offset = -offset; | |
5408 | sep = "-"; | |
5409 | } | |
5410 | else | |
5411 | sep = "+"; | |
ecf2283d | 5412 | break; |
5413 | ||
5414 | case MINUS: | |
5415 | gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF); | |
5416 | sep = "-"; | |
5417 | break; | |
87ad11b0 | 5418 | |
ecf2283d | 5419 | default: |
5420 | gcc_unreachable (); | |
5421 | } | |
5422 | ||
611a88e1 | 5423 | if (!read_only_operand (base, VOIDmode) && !flag_pic) |
9c0ac0fd | 5424 | fputs ("-$global$", file); |
f9333726 | 5425 | if (offset) |
ea52c577 | 5426 | fprintf (file, "%s%d", sep, offset); |
87ad11b0 | 5427 | } |
5428 | else | |
5429 | output_addr_const (file, x); | |
5430 | } | |
5431 | ||
92c473b8 | 5432 | /* Output boilerplate text to appear at the beginning of the file. |
5433 | There are several possible versions. */ | |
5434 | #define aputs(x) fputs(x, asm_out_file) | |
5435 | static inline void | |
5c1d8983 | 5436 | pa_file_start_level (void) |
92c473b8 | 5437 | { |
5438 | if (TARGET_64BIT) | |
5439 | aputs ("\t.LEVEL 2.0w\n"); | |
5440 | else if (TARGET_PA_20) | |
5441 | aputs ("\t.LEVEL 2.0\n"); | |
5442 | else if (TARGET_PA_11) | |
5443 | aputs ("\t.LEVEL 1.1\n"); | |
5444 | else | |
5445 | aputs ("\t.LEVEL 1.0\n"); | |
5446 | } | |
5447 | ||
5448 | static inline void | |
5c1d8983 | 5449 | pa_file_start_space (int sortspace) |
92c473b8 | 5450 | { |
5451 | aputs ("\t.SPACE $PRIVATE$"); | |
5452 | if (sortspace) | |
5453 | aputs (",SORT=16"); | |
8151bf30 | 5454 | aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"); |
5455 | if (flag_tm) | |
5456 | aputs ("\n\t.SUBSPA $TM_CLONE_TABLE$,QUAD=1,ALIGN=8,ACCESS=31"); | |
5457 | aputs ("\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82" | |
5458 | "\n\t.SPACE $TEXT$"); | |
92c473b8 | 5459 | if (sortspace) |
5460 | aputs (",SORT=8"); | |
5461 | aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44" | |
8151bf30 | 5462 | "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n"); |
92c473b8 | 5463 | } |
5464 | ||
5465 | static inline void | |
5c1d8983 | 5466 | pa_file_start_file (int want_version) |
92c473b8 | 5467 | { |
5468 | if (write_symbols != NO_DEBUG) | |
5469 | { | |
5470 | output_file_directive (asm_out_file, main_input_filename); | |
5471 | if (want_version) | |
5472 | aputs ("\t.version\t\"01.01\"\n"); | |
5473 | } | |
5474 | } | |
5475 | ||
5476 | static inline void | |
5c1d8983 | 5477 | pa_file_start_mcount (const char *aswhat) |
92c473b8 | 5478 | { |
5479 | if (profile_flag) | |
5480 | fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat); | |
5481 | } | |
5482 | ||
5483 | static void | |
5c1d8983 | 5484 | pa_elf_file_start (void) |
92c473b8 | 5485 | { |
5486 | pa_file_start_level (); | |
5487 | pa_file_start_mcount ("ENTRY"); | |
5488 | pa_file_start_file (0); | |
5489 | } | |
5490 | ||
5491 | static void | |
5c1d8983 | 5492 | pa_som_file_start (void) |
92c473b8 | 5493 | { |
5494 | pa_file_start_level (); | |
5495 | pa_file_start_space (0); | |
5496 | aputs ("\t.IMPORT $global$,DATA\n" | |
5497 | "\t.IMPORT $$dyncall,MILLICODE\n"); | |
5498 | pa_file_start_mcount ("CODE"); | |
5499 | pa_file_start_file (0); | |
5500 | } | |
5501 | ||
5502 | static void | |
5c1d8983 | 5503 | pa_linux_file_start (void) |
92c473b8 | 5504 | { |
5505 | pa_file_start_file (1); | |
5506 | pa_file_start_level (); | |
5507 | pa_file_start_mcount ("CODE"); | |
5508 | } | |
5509 | ||
5510 | static void | |
5c1d8983 | 5511 | pa_hpux64_gas_file_start (void) |
92c473b8 | 5512 | { |
5513 | pa_file_start_level (); | |
5514 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
5515 | if (profile_flag) | |
5516 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function"); | |
5517 | #endif | |
5518 | pa_file_start_file (1); | |
5519 | } | |
5520 | ||
5521 | static void | |
5c1d8983 | 5522 | pa_hpux64_hpas_file_start (void) |
92c473b8 | 5523 | { |
5524 | pa_file_start_level (); | |
5525 | pa_file_start_space (1); | |
5526 | pa_file_start_mcount ("CODE"); | |
5527 | pa_file_start_file (0); | |
5528 | } | |
5529 | #undef aputs | |
5530 | ||
4e75439e | 5531 | /* Search the deferred plabel list for SYMBOL and return its internal |
5532 | label. If an entry for SYMBOL is not found, a new entry is created. */ | |
5533 | ||
5534 | rtx | |
e202682d | 5535 | pa_get_deferred_plabel (rtx symbol) |
ece88821 | 5536 | { |
5f43b4f6 | 5537 | const char *fname = XSTR (symbol, 0); |
ece88821 | 5538 | size_t i; |
5539 | ||
5540 | /* See if we have already put this function on the list of deferred | |
5541 | plabels. This list is generally small, so a liner search is not | |
5542 | too ugly. If it proves too slow replace it with something faster. */ | |
5543 | for (i = 0; i < n_deferred_plabels; i++) | |
5f43b4f6 | 5544 | if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0) |
ece88821 | 5545 | break; |
5546 | ||
5547 | /* If the deferred plabel list is empty, or this entry was not found | |
5548 | on the list, create a new entry on the list. */ | |
5549 | if (deferred_plabels == NULL || i == n_deferred_plabels) | |
5550 | { | |
5f43b4f6 | 5551 | tree id; |
5552 | ||
ece88821 | 5553 | if (deferred_plabels == 0) |
ba72912a | 5554 | deferred_plabels = ggc_alloc_deferred_plabel (); |
ece88821 | 5555 | else |
ba72912a | 5556 | deferred_plabels = GGC_RESIZEVEC (struct deferred_plabel, |
5557 | deferred_plabels, | |
5558 | n_deferred_plabels + 1); | |
ece88821 | 5559 | |
5560 | i = n_deferred_plabels++; | |
5561 | deferred_plabels[i].internal_label = gen_label_rtx (); | |
5f43b4f6 | 5562 | deferred_plabels[i].symbol = symbol; |
ece88821 | 5563 | |
5f43b4f6 | 5564 | /* Gross. We have just implicitly taken the address of this |
5565 | function. Mark it in the same manner as assemble_name. */ | |
5566 | id = maybe_get_identifier (targetm.strip_name_encoding (fname)); | |
5567 | if (id) | |
5568 | mark_referenced (id); | |
ece88821 | 5569 | } |
5570 | ||
4e75439e | 5571 | return deferred_plabels[i].internal_label; |
ece88821 | 5572 | } |
5573 | ||
f6940372 | 5574 | static void |
5c1d8983 | 5575 | output_deferred_plabels (void) |
5cc6b2bc | 5576 | { |
e11bd7e5 | 5577 | size_t i; |
78962d38 | 5578 | |
5579 | /* If we have some deferred plabels, then we need to switch into the | |
5580 | data or readonly data section, and align it to a 4 byte boundary | |
191ec5a2 | 5581 | before outputting the deferred plabels. */ |
5cc6b2bc | 5582 | if (n_deferred_plabels) |
5583 | { | |
78962d38 | 5584 | switch_to_section (flag_pic ? data_section : readonly_data_section); |
f6940372 | 5585 | ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2); |
5cc6b2bc | 5586 | } |
5587 | ||
5588 | /* Now output the deferred plabels. */ | |
5589 | for (i = 0; i < n_deferred_plabels; i++) | |
5590 | { | |
c5559ed4 | 5591 | targetm.asm_out.internal_label (asm_out_file, "L", |
f6940372 | 5592 | CODE_LABEL_NUMBER (deferred_plabels[i].internal_label)); |
5f43b4f6 | 5593 | assemble_integer (deferred_plabels[i].symbol, |
b70ea764 | 5594 | TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1); |
5cc6b2bc | 5595 | } |
5596 | } | |
5597 | ||
3912b4d0 | 5598 | /* Initialize optabs to point to emulation routines. */ |
5599 | ||
f2f543a3 | 5600 | static void |
3912b4d0 | 5601 | pa_init_libfuncs (void) |
f2f543a3 | 5602 | { |
3912b4d0 | 5603 | if (HPUX_LONG_DOUBLE_LIBRARY) |
5604 | { | |
5605 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
5606 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
5607 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
5608 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
5609 | set_optab_libfunc (smin_optab, TFmode, "_U_Qmin"); | |
5610 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
5611 | set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt"); | |
5612 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
5613 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
5614 | ||
5615 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); | |
5616 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
5617 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
5618 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
5619 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
5620 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
5621 | set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord"); | |
5622 | ||
5623 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); | |
5624 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
5625 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
5626 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
5627 | ||
5628 | set_conv_libfunc (sfix_optab, SImode, TFmode, | |
5629 | TARGET_64BIT ? "__U_Qfcnvfxt_quad_to_sgl" | |
5630 | : "_U_Qfcnvfxt_quad_to_sgl"); | |
5631 | set_conv_libfunc (sfix_optab, DImode, TFmode, | |
5632 | "_U_Qfcnvfxt_quad_to_dbl"); | |
5633 | set_conv_libfunc (ufix_optab, SImode, TFmode, | |
5634 | "_U_Qfcnvfxt_quad_to_usgl"); | |
5635 | set_conv_libfunc (ufix_optab, DImode, TFmode, | |
5636 | "_U_Qfcnvfxt_quad_to_udbl"); | |
5637 | ||
5638 | set_conv_libfunc (sfloat_optab, TFmode, SImode, | |
5639 | "_U_Qfcnvxf_sgl_to_quad"); | |
5640 | set_conv_libfunc (sfloat_optab, TFmode, DImode, | |
5641 | "_U_Qfcnvxf_dbl_to_quad"); | |
5642 | set_conv_libfunc (ufloat_optab, TFmode, SImode, | |
5643 | "_U_Qfcnvxf_usgl_to_quad"); | |
5644 | set_conv_libfunc (ufloat_optab, TFmode, DImode, | |
5645 | "_U_Qfcnvxf_udbl_to_quad"); | |
5646 | } | |
d094e1b2 | 5647 | |
5648 | if (TARGET_SYNC_LIBCALL) | |
5649 | init_sync_libfuncs (UNITS_PER_WORD); | |
f2f543a3 | 5650 | } |
f2f543a3 | 5651 | |
87ad11b0 | 5652 | /* HP's millicode routines mean something special to the assembler. |
5653 | Keep track of which ones we have used. */ | |
5654 | ||
c2271c34 | 5655 | enum millicodes { remI, remU, divI, divU, mulI, end1000 }; |
5c1d8983 | 5656 | static void import_milli (enum millicodes); |
ea52c577 | 5657 | static char imported[(int) end1000]; |
c2271c34 | 5658 | static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"}; |
e99c3a1d | 5659 | static const char import_string[] = ".IMPORT $$....,MILLICODE"; |
87ad11b0 | 5660 | #define MILLI_START 10 |
5661 | ||
57ed30e5 | 5662 | static void |
5c1d8983 | 5663 | import_milli (enum millicodes code) |
87ad11b0 | 5664 | { |
5665 | char str[sizeof (import_string)]; | |
6d36483b | 5666 | |
ea52c577 | 5667 | if (!imported[(int) code]) |
87ad11b0 | 5668 | { |
ea52c577 | 5669 | imported[(int) code] = 1; |
87ad11b0 | 5670 | strcpy (str, import_string); |
ea52c577 | 5671 | strncpy (str + MILLI_START, milli_names[(int) code], 4); |
87ad11b0 | 5672 | output_asm_insn (str, 0); |
5673 | } | |
5674 | } | |
5675 | ||
6d36483b | 5676 | /* The register constraints have put the operands and return value in |
6dc3b0d9 | 5677 | the proper registers. */ |
87ad11b0 | 5678 | |
611a88e1 | 5679 | const char * |
e202682d | 5680 | pa_output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn) |
87ad11b0 | 5681 | { |
d178f670 | 5682 | import_milli (mulI); |
e202682d | 5683 | return pa_output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI")); |
87ad11b0 | 5684 | } |
5685 | ||
6dc3b0d9 | 5686 | /* Emit the rtl for doing a division by a constant. */ |
87ad11b0 | 5687 | |
d178f670 | 5688 | /* Do magic division millicodes exist for this value? */ |
e202682d | 5689 | const int pa_magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1}; |
87ad11b0 | 5690 | |
6d36483b | 5691 | /* We'll use an array to keep track of the magic millicodes and |
87ad11b0 | 5692 | whether or not we've used them already. [n][0] is signed, [n][1] is |
6dc3b0d9 | 5693 | unsigned. */ |
87ad11b0 | 5694 | |
87ad11b0 | 5695 | static int div_milli[16][2]; |
5696 | ||
87ad11b0 | 5697 | int |
e202682d | 5698 | pa_emit_hpdiv_const (rtx *operands, int unsignedp) |
87ad11b0 | 5699 | { |
5700 | if (GET_CODE (operands[2]) == CONST_INT | |
5701 | && INTVAL (operands[2]) > 0 | |
5702 | && INTVAL (operands[2]) < 16 | |
e202682d | 5703 | && pa_magic_milli[INTVAL (operands[2])]) |
87ad11b0 | 5704 | { |
2013ddf6 | 5705 | rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31); |
5706 | ||
ad851752 | 5707 | emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]); |
87ad11b0 | 5708 | emit |
75b1a41a | 5709 | (gen_rtx_PARALLEL |
5710 | (VOIDmode, | |
c2078db8 | 5711 | gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29), |
ad851752 | 5712 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, |
5713 | SImode, | |
5714 | gen_rtx_REG (SImode, 26), | |
5715 | operands[2])), | |
c2078db8 | 5716 | gen_rtx_CLOBBER (VOIDmode, operands[4]), |
ad851752 | 5717 | gen_rtx_CLOBBER (VOIDmode, operands[3]), |
5718 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)), | |
5719 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)), | |
2013ddf6 | 5720 | gen_rtx_CLOBBER (VOIDmode, ret)))); |
ad851752 | 5721 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 29)); |
87ad11b0 | 5722 | return 1; |
5723 | } | |
5724 | return 0; | |
5725 | } | |
5726 | ||
611a88e1 | 5727 | const char * |
e202682d | 5728 | pa_output_div_insn (rtx *operands, int unsignedp, rtx insn) |
87ad11b0 | 5729 | { |
5730 | int divisor; | |
6d36483b | 5731 | |
5732 | /* If the divisor is a constant, try to use one of the special | |
87ad11b0 | 5733 | opcodes .*/ |
5734 | if (GET_CODE (operands[0]) == CONST_INT) | |
5735 | { | |
d6686e21 | 5736 | static char buf[100]; |
87ad11b0 | 5737 | divisor = INTVAL (operands[0]); |
5738 | if (!div_milli[divisor][unsignedp]) | |
5739 | { | |
d6686e21 | 5740 | div_milli[divisor][unsignedp] = 1; |
87ad11b0 | 5741 | if (unsignedp) |
5742 | output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands); | |
5743 | else | |
5744 | output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands); | |
87ad11b0 | 5745 | } |
5746 | if (unsignedp) | |
d6686e21 | 5747 | { |
4840a03a | 5748 | sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC, |
5749 | INTVAL (operands[0])); | |
e202682d | 5750 | return pa_output_millicode_call (insn, |
5751 | gen_rtx_SYMBOL_REF (SImode, buf)); | |
d6686e21 | 5752 | } |
5753 | else | |
5754 | { | |
4840a03a | 5755 | sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC, |
5756 | INTVAL (operands[0])); | |
e202682d | 5757 | return pa_output_millicode_call (insn, |
5758 | gen_rtx_SYMBOL_REF (SImode, buf)); | |
d6686e21 | 5759 | } |
87ad11b0 | 5760 | } |
6dc3b0d9 | 5761 | /* Divisor isn't a special constant. */ |
87ad11b0 | 5762 | else |
5763 | { | |
5764 | if (unsignedp) | |
5765 | { | |
5766 | import_milli (divU); | |
e202682d | 5767 | return pa_output_millicode_call (insn, |
ad851752 | 5768 | gen_rtx_SYMBOL_REF (SImode, "$$divU")); |
87ad11b0 | 5769 | } |
5770 | else | |
5771 | { | |
5772 | import_milli (divI); | |
e202682d | 5773 | return pa_output_millicode_call (insn, |
ad851752 | 5774 | gen_rtx_SYMBOL_REF (SImode, "$$divI")); |
87ad11b0 | 5775 | } |
5776 | } | |
5777 | } | |
5778 | ||
6dc3b0d9 | 5779 | /* Output a $$rem millicode to do mod. */ |
87ad11b0 | 5780 | |
611a88e1 | 5781 | const char * |
e202682d | 5782 | pa_output_mod_insn (int unsignedp, rtx insn) |
87ad11b0 | 5783 | { |
5784 | if (unsignedp) | |
5785 | { | |
5786 | import_milli (remU); | |
e202682d | 5787 | return pa_output_millicode_call (insn, |
5788 | gen_rtx_SYMBOL_REF (SImode, "$$remU")); | |
87ad11b0 | 5789 | } |
5790 | else | |
5791 | { | |
5792 | import_milli (remI); | |
e202682d | 5793 | return pa_output_millicode_call (insn, |
5794 | gen_rtx_SYMBOL_REF (SImode, "$$remI")); | |
87ad11b0 | 5795 | } |
5796 | } | |
5797 | ||
5798 | void | |
e202682d | 5799 | pa_output_arg_descriptor (rtx call_insn) |
87ad11b0 | 5800 | { |
611a88e1 | 5801 | const char *arg_regs[4]; |
87ad11b0 | 5802 | enum machine_mode arg_mode; |
df0651dc | 5803 | rtx link; |
87ad11b0 | 5804 | int i, output_flag = 0; |
5805 | int regno; | |
6d36483b | 5806 | |
5e3c5739 | 5807 | /* We neither need nor want argument location descriptors for the |
5d0619cc | 5808 | 64bit runtime environment or the ELF32 environment. */ |
5809 | if (TARGET_64BIT || TARGET_ELF32) | |
5e3c5739 | 5810 | return; |
5811 | ||
87ad11b0 | 5812 | for (i = 0; i < 4; i++) |
5813 | arg_regs[i] = 0; | |
5814 | ||
738176ab | 5815 | /* Specify explicitly that no argument relocations should take place |
5816 | if using the portable runtime calling conventions. */ | |
5817 | if (TARGET_PORTABLE_RUNTIME) | |
5818 | { | |
9c0ac0fd | 5819 | fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n", |
5820 | asm_out_file); | |
738176ab | 5821 | return; |
5822 | } | |
5823 | ||
ecf2283d | 5824 | gcc_assert (GET_CODE (call_insn) == CALL_INSN); |
5825 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); | |
5826 | link; link = XEXP (link, 1)) | |
87ad11b0 | 5827 | { |
df0651dc | 5828 | rtx use = XEXP (link, 0); |
c12afafd | 5829 | |
df0651dc | 5830 | if (! (GET_CODE (use) == USE |
5831 | && GET_CODE (XEXP (use, 0)) == REG | |
5832 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
c12afafd | 5833 | continue; |
5834 | ||
df0651dc | 5835 | arg_mode = GET_MODE (XEXP (use, 0)); |
5836 | regno = REGNO (XEXP (use, 0)); | |
87ad11b0 | 5837 | if (regno >= 23 && regno <= 26) |
372ef038 | 5838 | { |
5839 | arg_regs[26 - regno] = "GR"; | |
5840 | if (arg_mode == DImode) | |
5841 | arg_regs[25 - regno] = "GR"; | |
5842 | } | |
df0651dc | 5843 | else if (regno >= 32 && regno <= 39) |
87ad11b0 | 5844 | { |
5845 | if (arg_mode == SFmode) | |
df0651dc | 5846 | arg_regs[(regno - 32) / 2] = "FR"; |
e6ba640e | 5847 | else |
87ad11b0 | 5848 | { |
eeec72c0 | 5849 | #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED |
df0651dc | 5850 | arg_regs[(regno - 34) / 2] = "FR"; |
5851 | arg_regs[(regno - 34) / 2 + 1] = "FU"; | |
87ad11b0 | 5852 | #else |
df0651dc | 5853 | arg_regs[(regno - 34) / 2] = "FU"; |
5854 | arg_regs[(regno - 34) / 2 + 1] = "FR"; | |
87ad11b0 | 5855 | #endif |
5856 | } | |
87ad11b0 | 5857 | } |
5858 | } | |
5859 | fputs ("\t.CALL ", asm_out_file); | |
5860 | for (i = 0; i < 4; i++) | |
5861 | { | |
5862 | if (arg_regs[i]) | |
5863 | { | |
5864 | if (output_flag++) | |
5865 | fputc (',', asm_out_file); | |
5866 | fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]); | |
5867 | } | |
5868 | } | |
5869 | fputc ('\n', asm_out_file); | |
5870 | } | |
5871 | \f | |
5ddb2975 | 5872 | /* Inform reload about cases where moving X with a mode MODE to a register in |
5873 | RCLASS requires an extra scratch or immediate register. Return the class | |
5874 | needed for the immediate register. */ | |
5875 | ||
964229b7 | 5876 | static reg_class_t |
5877 | pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, | |
5655a0e5 | 5878 | enum machine_mode mode, secondary_reload_info *sri) |
5879 | { | |
c9b20949 | 5880 | int regno; |
964229b7 | 5881 | enum reg_class rclass = (enum reg_class) rclass_i; |
9c0ac0fd | 5882 | |
5655a0e5 | 5883 | /* Handle the easy stuff first. */ |
8deb3959 | 5884 | if (rclass == R1_REGS) |
5655a0e5 | 5885 | return NO_REGS; |
9c0ac0fd | 5886 | |
5655a0e5 | 5887 | if (REG_P (x)) |
5888 | { | |
5889 | regno = REGNO (x); | |
8deb3959 | 5890 | if (rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER) |
5655a0e5 | 5891 | return NO_REGS; |
5892 | } | |
cca0fae1 | 5893 | else |
5894 | regno = -1; | |
87ad11b0 | 5895 | |
5655a0e5 | 5896 | /* If we have something like (mem (mem (...)), we can safely assume the |
5897 | inner MEM will end up in a general register after reloading, so there's | |
5898 | no need for a secondary reload. */ | |
5899 | if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM) | |
5900 | return NO_REGS; | |
87ad11b0 | 5901 | |
b4a7bf10 | 5902 | /* Trying to load a constant into a FP register during PIC code |
5655a0e5 | 5903 | generation requires %r1 as a scratch register. */ |
fc44315f | 5904 | if (flag_pic |
9c0b6987 | 5905 | && (mode == SImode || mode == DImode) |
8deb3959 | 5906 | && FP_REG_CLASS_P (rclass) |
5655a0e5 | 5907 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
9c0ac0fd | 5908 | { |
5655a0e5 | 5909 | sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1 |
5910 | : CODE_FOR_reload_indi_r1); | |
5911 | return NO_REGS; | |
9c0ac0fd | 5912 | } |
9c0ac0fd | 5913 | |
c9b20949 | 5914 | /* Secondary reloads of symbolic operands require %r1 as a scratch |
5915 | register when we're generating PIC code and when the operand isn't | |
5916 | readonly. */ | |
e202682d | 5917 | if (pa_symbolic_expression_p (x)) |
c9b20949 | 5918 | { |
5919 | if (GET_CODE (x) == HIGH) | |
5920 | x = XEXP (x, 0); | |
5921 | ||
5922 | if (flag_pic || !read_only_operand (x, VOIDmode)) | |
5923 | { | |
5924 | gcc_assert (mode == SImode || mode == DImode); | |
5925 | sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1 | |
5926 | : CODE_FOR_reload_indi_r1); | |
5927 | return NO_REGS; | |
5928 | } | |
5929 | } | |
5930 | ||
5655a0e5 | 5931 | /* Profiling showed the PA port spends about 1.3% of its compilation |
5932 | time in true_regnum from calls inside pa_secondary_reload_class. */ | |
5933 | if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG) | |
5934 | regno = true_regnum (x); | |
76a0ced5 | 5935 | |
7050ff73 | 5936 | /* In order to allow 14-bit displacements in integer loads and stores, |
5937 | we need to prevent reload from generating out of range integer mode | |
5938 | loads and stores to the floating point registers. Previously, we | |
e202682d | 5939 | used to call for a secondary reload and have pa_emit_move_sequence() |
7050ff73 | 5940 | fix the instruction sequence. However, reload occasionally wouldn't |
5941 | generate the reload and we would end up with an invalid REG+D memory | |
5942 | address. So, now we use an intermediate general register for most | |
5943 | memory loads and stores. */ | |
5944 | if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1) | |
5945 | && GET_MODE_CLASS (mode) == MODE_INT | |
8deb3959 | 5946 | && FP_REG_CLASS_P (rclass)) |
7050ff73 | 5947 | { |
5948 | /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check | |
5949 | the secondary reload needed for a pseudo. It never passes a | |
5950 | REG+D address. */ | |
5951 | if (GET_CODE (x) == MEM) | |
5952 | { | |
5953 | x = XEXP (x, 0); | |
5954 | ||
5955 | /* We don't need an intermediate for indexed and LO_SUM DLT | |
5956 | memory addresses. When INT14_OK_STRICT is true, it might | |
5957 | appear that we could directly allow register indirect | |
5958 | memory addresses. However, this doesn't work because we | |
5959 | don't support SUBREGs in floating-point register copies | |
5960 | and reload doesn't tell us when it's going to use a SUBREG. */ | |
5961 | if (IS_INDEX_ADDR_P (x) | |
5962 | || IS_LO_SUM_DLT_ADDR_P (x)) | |
5963 | return NO_REGS; | |
5964 | ||
5965 | /* Otherwise, we need an intermediate general register. */ | |
5966 | return GENERAL_REGS; | |
5967 | } | |
5968 | ||
5969 | /* Request a secondary reload with a general scratch register | |
9d75589a | 5970 | for everything else. ??? Could symbolic operands be handled |
7050ff73 | 5971 | directly when generating non-pic PA 2.0 code? */ |
6b531606 | 5972 | sri->icode = (in_p |
5973 | ? direct_optab_handler (reload_in_optab, mode) | |
5974 | : direct_optab_handler (reload_out_optab, mode)); | |
7050ff73 | 5975 | return NO_REGS; |
5976 | } | |
5977 | ||
5ddb2975 | 5978 | /* A SAR<->FP register copy requires an intermediate general register |
5979 | and secondary memory. We need a secondary reload with a general | |
5980 | scratch register for spills. */ | |
5981 | if (rclass == SHIFT_REGS) | |
5655a0e5 | 5982 | { |
5ddb2975 | 5983 | /* Handle spill. */ |
5984 | if (regno >= FIRST_PSEUDO_REGISTER || regno < 0) | |
5985 | { | |
5986 | sri->icode = (in_p | |
5987 | ? direct_optab_handler (reload_in_optab, mode) | |
5988 | : direct_optab_handler (reload_out_optab, mode)); | |
5989 | return NO_REGS; | |
5990 | } | |
5991 | ||
5992 | /* Handle FP copy. */ | |
5993 | if (FP_REG_CLASS_P (REGNO_REG_CLASS (regno))) | |
5994 | return GENERAL_REGS; | |
5655a0e5 | 5995 | } |
d2c1d63d | 5996 | |
7c4b32f3 | 5997 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER |
5ddb2975 | 5998 | && REGNO_REG_CLASS (regno) == SHIFT_REGS |
5999 | && FP_REG_CLASS_P (rclass)) | |
6000 | return GENERAL_REGS; | |
2ee034bc | 6001 | |
d2c1d63d | 6002 | return NO_REGS; |
87ad11b0 | 6003 | } |
6004 | ||
df6b92e4 | 6005 | /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer |
6006 | is only marked as live on entry by df-scan when it is a fixed | |
6007 | register. It isn't a fixed register in the 64-bit runtime, | |
6008 | so we need to mark it here. */ | |
6009 | ||
6010 | static void | |
6011 | pa_extra_live_on_entry (bitmap regs) | |
6012 | { | |
6013 | if (TARGET_64BIT) | |
6014 | bitmap_set_bit (regs, ARG_POINTER_REGNUM); | |
6015 | } | |
6016 | ||
6017 | /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile | |
6018 | to prevent it from being deleted. */ | |
6019 | ||
6020 | rtx | |
6021 | pa_eh_return_handler_rtx (void) | |
6022 | { | |
6023 | rtx tmp; | |
6024 | ||
68bc9ae6 | 6025 | tmp = gen_rtx_PLUS (word_mode, hard_frame_pointer_rtx, |
df6b92e4 | 6026 | TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)); |
6027 | tmp = gen_rtx_MEM (word_mode, tmp); | |
6028 | tmp->volatil = 1; | |
6029 | return tmp; | |
6030 | } | |
6031 | ||
b981d932 | 6032 | /* In the 32-bit runtime, arguments larger than eight bytes are passed |
6033 | by invisible reference. As a GCC extension, we also pass anything | |
6034 | with a zero or variable size by reference. | |
6035 | ||
6036 | The 64-bit runtime does not describe passing any types by invisible | |
6037 | reference. The internals of GCC can't currently handle passing | |
6038 | empty structures, and zero or variable length arrays when they are | |
6039 | not passed entirely on the stack or by reference. Thus, as a GCC | |
6040 | extension, we pass these types by reference. The HP compiler doesn't | |
6041 | support these types, so hopefully there shouldn't be any compatibility | |
6042 | issues. This may have to be revisited when HP releases a C99 compiler | |
6043 | or updates the ABI. */ | |
6044 | ||
6045 | static bool | |
39cba157 | 6046 | pa_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED, |
fb80456a | 6047 | enum machine_mode mode, const_tree type, |
b981d932 | 6048 | bool named ATTRIBUTE_UNUSED) |
6049 | { | |
6050 | HOST_WIDE_INT size; | |
6051 | ||
6052 | if (type) | |
6053 | size = int_size_in_bytes (type); | |
6054 | else | |
6055 | size = GET_MODE_SIZE (mode); | |
6056 | ||
6057 | if (TARGET_64BIT) | |
6058 | return size <= 0; | |
6059 | else | |
6060 | return size <= 0 || size > 8; | |
6061 | } | |
6062 | ||
87ad11b0 | 6063 | enum direction |
e202682d | 6064 | pa_function_arg_padding (enum machine_mode mode, const_tree type) |
87ad11b0 | 6065 | { |
ac965869 | 6066 | if (mode == BLKmode |
ef669d1a | 6067 | || (TARGET_64BIT |
6068 | && type | |
6069 | && (AGGREGATE_TYPE_P (type) | |
6070 | || TREE_CODE (type) == COMPLEX_TYPE | |
6071 | || TREE_CODE (type) == VECTOR_TYPE))) | |
ac965869 | 6072 | { |
6073 | /* Return none if justification is not required. */ | |
6074 | if (type | |
6075 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
6076 | && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0) | |
6077 | return none; | |
6078 | ||
6079 | /* The directions set here are ignored when a BLKmode argument larger | |
6080 | than a word is placed in a register. Different code is used for | |
6081 | the stack and registers. This makes it difficult to have a | |
6082 | consistent data representation for both the stack and registers. | |
6083 | For both runtimes, the justification and padding for arguments on | |
6084 | the stack and in registers should be identical. */ | |
6085 | if (TARGET_64BIT) | |
6086 | /* The 64-bit runtime specifies left justification for aggregates. */ | |
6087 | return upward; | |
87ad11b0 | 6088 | else |
ac965869 | 6089 | /* The 32-bit runtime architecture specifies right justification. |
6090 | When the argument is passed on the stack, the argument is padded | |
6091 | with garbage on the left. The HP compiler pads with zeros. */ | |
6092 | return downward; | |
87ad11b0 | 6093 | } |
ac965869 | 6094 | |
6095 | if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
87ad11b0 | 6096 | return downward; |
87ad11b0 | 6097 | else |
6098 | return none; | |
6099 | } | |
6100 | ||
87ad11b0 | 6101 | \f |
55f54832 | 6102 | /* Do what is necessary for `va_start'. We look at the current function |
6103 | to determine if stdargs or varargs is used and fill in an initial | |
6104 | va_list. A pointer to this constructor is returned. */ | |
87ad11b0 | 6105 | |
b8debbe8 | 6106 | static rtx |
5c1d8983 | 6107 | hppa_builtin_saveregs (void) |
87ad11b0 | 6108 | { |
01251cbc | 6109 | rtx offset, dest; |
87ad11b0 | 6110 | tree fntype = TREE_TYPE (current_function_decl); |
257d99c3 | 6111 | int argadj = ((!stdarg_p (fntype)) |
87ad11b0 | 6112 | ? UNITS_PER_WORD : 0); |
6113 | ||
6114 | if (argadj) | |
29c05e22 | 6115 | offset = plus_constant (Pmode, crtl->args.arg_offset_rtx, argadj); |
87ad11b0 | 6116 | else |
abe32cce | 6117 | offset = crtl->args.arg_offset_rtx; |
9c6d4825 | 6118 | |
5e3c5739 | 6119 | if (TARGET_64BIT) |
6120 | { | |
6121 | int i, off; | |
9840d99d | 6122 | |
5e3c5739 | 6123 | /* Adjust for varargs/stdarg differences. */ |
6124 | if (argadj) | |
29c05e22 | 6125 | offset = plus_constant (Pmode, crtl->args.arg_offset_rtx, -argadj); |
5e3c5739 | 6126 | else |
abe32cce | 6127 | offset = crtl->args.arg_offset_rtx; |
5e3c5739 | 6128 | |
6129 | /* We need to save %r26 .. %r19 inclusive starting at offset -64 | |
6130 | from the incoming arg pointer and growing to larger addresses. */ | |
6131 | for (i = 26, off = -64; i >= 19; i--, off += 8) | |
6132 | emit_move_insn (gen_rtx_MEM (word_mode, | |
29c05e22 | 6133 | plus_constant (Pmode, |
6134 | arg_pointer_rtx, off)), | |
5e3c5739 | 6135 | gen_rtx_REG (word_mode, i)); |
6136 | ||
6137 | /* The incoming args pointer points just beyond the flushback area; | |
8ef587dc | 6138 | normally this is not a serious concern. However, when we are doing |
5e3c5739 | 6139 | varargs/stdargs we want to make the arg pointer point to the start |
6140 | of the incoming argument area. */ | |
6141 | emit_move_insn (virtual_incoming_args_rtx, | |
29c05e22 | 6142 | plus_constant (Pmode, arg_pointer_rtx, -64)); |
5e3c5739 | 6143 | |
6144 | /* Now return a pointer to the first anonymous argument. */ | |
6145 | return copy_to_reg (expand_binop (Pmode, add_optab, | |
6146 | virtual_incoming_args_rtx, | |
6147 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
6148 | } | |
6149 | ||
6dc3b0d9 | 6150 | /* Store general registers on the stack. */ |
ad851752 | 6151 | dest = gen_rtx_MEM (BLKmode, |
29c05e22 | 6152 | plus_constant (Pmode, crtl->args.internal_arg_pointer, |
ad851752 | 6153 | -16)); |
ab6ab77e | 6154 | set_mem_alias_set (dest, get_varargs_alias_set ()); |
2a631e19 | 6155 | set_mem_align (dest, BITS_PER_WORD); |
530178a9 | 6156 | move_block_from_reg (23, dest, 4); |
01251cbc | 6157 | |
76a0ced5 | 6158 | /* move_block_from_reg will emit code to store the argument registers |
6159 | individually as scalar stores. | |
6160 | ||
6161 | However, other insns may later load from the same addresses for | |
ad87de1e | 6162 | a structure load (passing a struct to a varargs routine). |
76a0ced5 | 6163 | |
6164 | The alias code assumes that such aliasing can never happen, so we | |
6165 | have to keep memory referencing insns from moving up beyond the | |
6166 | last argument register store. So we emit a blockage insn here. */ | |
6167 | emit_insn (gen_blockage ()); | |
6168 | ||
9c6d4825 | 6169 | return copy_to_reg (expand_binop (Pmode, add_optab, |
abe32cce | 6170 | crtl->args.internal_arg_pointer, |
9c6d4825 | 6171 | offset, 0, 0, OPTAB_LIB_WIDEN)); |
87ad11b0 | 6172 | } |
d6f01525 | 6173 | |
8a58ed0a | 6174 | static void |
5c1d8983 | 6175 | hppa_va_start (tree valist, rtx nextarg) |
72899a61 | 6176 | { |
6177 | nextarg = expand_builtin_saveregs (); | |
7df226a2 | 6178 | std_expand_builtin_va_start (valist, nextarg); |
72899a61 | 6179 | } |
6180 | ||
4c33eb68 | 6181 | static tree |
75a70cf9 | 6182 | hppa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
6183 | gimple_seq *post_p) | |
72899a61 | 6184 | { |
5e3c5739 | 6185 | if (TARGET_64BIT) |
6186 | { | |
4c33eb68 | 6187 | /* Args grow upward. We can use the generic routines. */ |
bef380a4 | 6188 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
72899a61 | 6189 | } |
ac965869 | 6190 | else /* !TARGET_64BIT */ |
72899a61 | 6191 | { |
4c33eb68 | 6192 | tree ptr = build_pointer_type (type); |
6193 | tree valist_type; | |
6194 | tree t, u; | |
6195 | unsigned int size, ofs; | |
bef380a4 | 6196 | bool indirect; |
72899a61 | 6197 | |
bef380a4 | 6198 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0); |
4c33eb68 | 6199 | if (indirect) |
ac965869 | 6200 | { |
4c33eb68 | 6201 | type = ptr; |
6202 | ptr = build_pointer_type (type); | |
72899a61 | 6203 | } |
4c33eb68 | 6204 | size = int_size_in_bytes (type); |
6205 | valist_type = TREE_TYPE (valist); | |
ac965869 | 6206 | |
4c33eb68 | 6207 | /* Args grow down. Not handled by generic routines. */ |
ac965869 | 6208 | |
0de36bdb | 6209 | u = fold_convert (sizetype, size_in_bytes (type)); |
6210 | u = fold_build1 (NEGATE_EXPR, sizetype, u); | |
2cc66f2a | 6211 | t = fold_build_pointer_plus (valist, u); |
ac965869 | 6212 | |
175fd0a9 | 6213 | /* Align to 4 or 8 byte boundary depending on argument size. */ |
6214 | ||
6215 | u = build_int_cst (TREE_TYPE (t), (HOST_WIDE_INT)(size > 4 ? -8 : -4)); | |
6216 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u); | |
0de36bdb | 6217 | t = fold_convert (valist_type, t); |
4c33eb68 | 6218 | |
33b1284b | 6219 | t = build2 (MODIFY_EXPR, valist_type, valist, t); |
72899a61 | 6220 | |
4c33eb68 | 6221 | ofs = (8 - size) % 4; |
6222 | if (ofs != 0) | |
2cc66f2a | 6223 | t = fold_build_pointer_plus_hwi (t, ofs); |
72899a61 | 6224 | |
4c33eb68 | 6225 | t = fold_convert (ptr, t); |
063f5fdd | 6226 | t = build_va_arg_indirect_ref (t); |
72899a61 | 6227 | |
4c33eb68 | 6228 | if (indirect) |
063f5fdd | 6229 | t = build_va_arg_indirect_ref (t); |
72899a61 | 6230 | |
4c33eb68 | 6231 | return t; |
6232 | } | |
6233 | } | |
72899a61 | 6234 | |
2b1e7cc3 | 6235 | /* True if MODE is valid for the target. By "valid", we mean able to |
6236 | be manipulated in non-trivial ways. In particular, this means all | |
6237 | the arithmetic is supported. | |
6238 | ||
6239 | Currently, TImode is not valid as the HP 64-bit runtime documentation | |
6240 | doesn't document the alignment and calling conventions for this type. | |
6241 | Thus, we return false when PRECISION is 2 * BITS_PER_WORD and | |
6242 | 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */ | |
6243 | ||
6244 | static bool | |
6245 | pa_scalar_mode_supported_p (enum machine_mode mode) | |
6246 | { | |
6247 | int precision = GET_MODE_PRECISION (mode); | |
6248 | ||
6249 | switch (GET_MODE_CLASS (mode)) | |
6250 | { | |
6251 | case MODE_PARTIAL_INT: | |
6252 | case MODE_INT: | |
6253 | if (precision == CHAR_TYPE_SIZE) | |
6254 | return true; | |
6255 | if (precision == SHORT_TYPE_SIZE) | |
6256 | return true; | |
6257 | if (precision == INT_TYPE_SIZE) | |
6258 | return true; | |
6259 | if (precision == LONG_TYPE_SIZE) | |
6260 | return true; | |
6261 | if (precision == LONG_LONG_TYPE_SIZE) | |
6262 | return true; | |
6263 | return false; | |
6264 | ||
6265 | case MODE_FLOAT: | |
6266 | if (precision == FLOAT_TYPE_SIZE) | |
6267 | return true; | |
6268 | if (precision == DOUBLE_TYPE_SIZE) | |
6269 | return true; | |
6270 | if (precision == LONG_DOUBLE_TYPE_SIZE) | |
6271 | return true; | |
6272 | return false; | |
6273 | ||
2af936a9 | 6274 | case MODE_DECIMAL_FLOAT: |
6275 | return false; | |
6276 | ||
2b1e7cc3 | 6277 | default: |
6278 | gcc_unreachable (); | |
6279 | } | |
6280 | } | |
6281 | ||
317754f4 | 6282 | /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and |
ebeae299 | 6283 | it branches into the delay slot. Otherwise, return FALSE. */ |
317754f4 | 6284 | |
6285 | static bool | |
6286 | branch_to_delay_slot_p (rtx insn) | |
6287 | { | |
ebeae299 | 6288 | rtx jump_insn; |
6289 | ||
317754f4 | 6290 | if (dbr_sequence_length ()) |
6291 | return FALSE; | |
6292 | ||
ebeae299 | 6293 | jump_insn = next_active_insn (JUMP_LABEL (insn)); |
6294 | while (insn) | |
6295 | { | |
6296 | insn = next_active_insn (insn); | |
6297 | if (jump_insn == insn) | |
6298 | return TRUE; | |
6299 | ||
6300 | /* We can't rely on the length of asms. So, we return FALSE when | |
6301 | the branch is followed by an asm. */ | |
6302 | if (!insn | |
6303 | || GET_CODE (PATTERN (insn)) == ASM_INPUT | |
6304 | || extract_asm_operands (PATTERN (insn)) != NULL_RTX | |
6305 | || get_attr_length (insn) > 0) | |
6306 | break; | |
6307 | } | |
6308 | ||
6309 | return FALSE; | |
317754f4 | 6310 | } |
6311 | ||
ebeae299 | 6312 | /* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot. |
317754f4 | 6313 | |
6314 | This occurs when INSN has an unfilled delay slot and is followed | |
ebeae299 | 6315 | by an asm. Disaster can occur if the asm is empty and the jump |
6316 | branches into the delay slot. So, we add a nop in the delay slot | |
6317 | when this occurs. */ | |
317754f4 | 6318 | |
6319 | static bool | |
6320 | branch_needs_nop_p (rtx insn) | |
6321 | { | |
ebeae299 | 6322 | rtx jump_insn; |
317754f4 | 6323 | |
6324 | if (dbr_sequence_length ()) | |
6325 | return FALSE; | |
6326 | ||
ebeae299 | 6327 | jump_insn = next_active_insn (JUMP_LABEL (insn)); |
6328 | while (insn) | |
6329 | { | |
6330 | insn = next_active_insn (insn); | |
6331 | if (!insn || jump_insn == insn) | |
6332 | return TRUE; | |
6333 | ||
6334 | if (!(GET_CODE (PATTERN (insn)) == ASM_INPUT | |
6335 | || extract_asm_operands (PATTERN (insn)) != NULL_RTX) | |
6336 | && get_attr_length (insn) > 0) | |
6337 | break; | |
6338 | } | |
6339 | ||
6340 | return FALSE; | |
6341 | } | |
6342 | ||
6343 | /* Return TRUE if INSN, a forward jump insn, can use nullification | |
6344 | to skip the following instruction. This avoids an extra cycle due | |
6345 | to a mis-predicted branch when we fall through. */ | |
6346 | ||
6347 | static bool | |
6348 | use_skip_p (rtx insn) | |
6349 | { | |
6350 | rtx jump_insn = next_active_insn (JUMP_LABEL (insn)); | |
6351 | ||
6352 | while (insn) | |
6353 | { | |
6354 | insn = next_active_insn (insn); | |
6355 | ||
6356 | /* We can't rely on the length of asms, so we can't skip asms. */ | |
6357 | if (!insn | |
6358 | || GET_CODE (PATTERN (insn)) == ASM_INPUT | |
6359 | || extract_asm_operands (PATTERN (insn)) != NULL_RTX) | |
6360 | break; | |
6361 | if (get_attr_length (insn) == 4 | |
6362 | && jump_insn == next_active_insn (insn)) | |
6363 | return TRUE; | |
6364 | if (get_attr_length (insn) > 0) | |
6365 | break; | |
6366 | } | |
6367 | ||
6368 | return FALSE; | |
317754f4 | 6369 | } |
6370 | ||
6d36483b | 6371 | /* This routine handles all the normal conditional branch sequences we |
6372 | might need to generate. It handles compare immediate vs compare | |
6373 | register, nullification of delay slots, varying length branches, | |
0d986529 | 6374 | negated branches, and all combinations of the above. It returns the |
6d36483b | 6375 | output appropriate to emit the branch corresponding to all given |
0d986529 | 6376 | parameters. */ |
6377 | ||
611a88e1 | 6378 | const char * |
e202682d | 6379 | pa_output_cbranch (rtx *operands, int negated, rtx insn) |
29a4502c | 6380 | { |
0d986529 | 6381 | static char buf[100]; |
ebeae299 | 6382 | bool useskip; |
f26036bb | 6383 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6384 | int length = get_attr_length (insn); | |
6385 | int xdelay; | |
0d986529 | 6386 | |
a361b456 | 6387 | /* A conditional branch to the following instruction (e.g. the delay slot) |
ece0fa59 | 6388 | is asking for a disaster. This can happen when not optimizing and |
6389 | when jump optimization fails. | |
29a4502c | 6390 | |
38efba6c | 6391 | While it is usually safe to emit nothing, this can fail if the |
6392 | preceding instruction is a nullified branch with an empty delay | |
6393 | slot and the same branch target as this branch. We could check | |
6394 | for this but jump optimization should eliminate nop jumps. It | |
6395 | is always safe to emit a nop. */ | |
317754f4 | 6396 | if (branch_to_delay_slot_p (insn)) |
ece0fa59 | 6397 | return "nop"; |
6d36483b | 6398 | |
22699a7e | 6399 | /* The doubleword form of the cmpib instruction doesn't have the LEU |
6400 | and GTU conditions while the cmpb instruction does. Since we accept | |
6401 | zero for cmpb, we must ensure that we use cmpb for the comparison. */ | |
6402 | if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx) | |
6403 | operands[2] = gen_rtx_REG (DImode, 0); | |
d65b8df8 | 6404 | if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx) |
6405 | operands[1] = gen_rtx_REG (DImode, 0); | |
22699a7e | 6406 | |
5fbd5940 | 6407 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6408 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6409 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6410 | nullify = 1; |
6411 | ||
6412 | /* If this is a short forward conditional branch which did not get | |
6413 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6414 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6415 | nullify = forward_branch_p (insn); |
6416 | ||
6d36483b | 6417 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6418 | comclr instruction. This avoids a single cycle penalty due to |
6419 | mis-predicted branch if we fall through (branch not taken). */ | |
ebeae299 | 6420 | useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; |
0d986529 | 6421 | |
6422 | switch (length) | |
6423 | { | |
5fbd5940 | 6424 | /* All short conditional branches except backwards with an unfilled |
6425 | delay slot. */ | |
5a1231ef | 6426 | case 4: |
0d986529 | 6427 | if (useskip) |
e4065f95 | 6428 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
0d986529 | 6429 | else |
e4065f95 | 6430 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6431 | if (GET_MODE (operands[1]) == DImode) |
6432 | strcat (buf, "*"); | |
0d986529 | 6433 | if (negated) |
6434 | strcat (buf, "%B3"); | |
6435 | else | |
6436 | strcat (buf, "%S3"); | |
6437 | if (useskip) | |
5a811d43 | 6438 | strcat (buf, " %2,%r1,%%r0"); |
0d986529 | 6439 | else if (nullify) |
317754f4 | 6440 | { |
6441 | if (branch_needs_nop_p (insn)) | |
6442 | strcat (buf, ",n %2,%r1,%0%#"); | |
6443 | else | |
6444 | strcat (buf, ",n %2,%r1,%0"); | |
6445 | } | |
6d36483b | 6446 | else |
9e49be0e | 6447 | strcat (buf, " %2,%r1,%0"); |
0d986529 | 6448 | break; |
6449 | ||
87fcb603 | 6450 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6451 | unfilled delay slot is treated just like a long backward branch |
6452 | with an unfilled delay slot. */ | |
5a1231ef | 6453 | case 8: |
5fbd5940 | 6454 | /* Handle weird backwards branch with a filled delay slot |
f26036bb | 6455 | which is nullified. */ |
5fbd5940 | 6456 | if (dbr_sequence_length () != 0 |
6457 | && ! forward_branch_p (insn) | |
6458 | && nullify) | |
6459 | { | |
e4065f95 | 6460 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6461 | if (GET_MODE (operands[1]) == DImode) |
6462 | strcat (buf, "*"); | |
5fbd5940 | 6463 | if (negated) |
6464 | strcat (buf, "%S3"); | |
6465 | else | |
6466 | strcat (buf, "%B3"); | |
5a811d43 | 6467 | strcat (buf, ",n %2,%r1,.+12\n\tb %0"); |
5fbd5940 | 6468 | } |
43f0c1f2 | 6469 | /* Handle short backwards branch with an unfilled delay slot. |
6470 | Using a comb;nop rather than comiclr;bl saves 1 cycle for both | |
6471 | taken and untaken branches. */ | |
6472 | else if (dbr_sequence_length () == 0 | |
6473 | && ! forward_branch_p (insn) | |
47fc0706 | 6474 | && INSN_ADDRESSES_SET_P () |
6475 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6476 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6477 | { |
e4065f95 | 6478 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6479 | if (GET_MODE (operands[1]) == DImode) |
6480 | strcat (buf, "*"); | |
43f0c1f2 | 6481 | if (negated) |
9e49be0e | 6482 | strcat (buf, "%B3 %2,%r1,%0%#"); |
43f0c1f2 | 6483 | else |
9e49be0e | 6484 | strcat (buf, "%S3 %2,%r1,%0%#"); |
43f0c1f2 | 6485 | } |
0d986529 | 6486 | else |
5fbd5940 | 6487 | { |
e4065f95 | 6488 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
5e3c5739 | 6489 | if (GET_MODE (operands[1]) == DImode) |
6490 | strcat (buf, "*"); | |
5fbd5940 | 6491 | if (negated) |
6492 | strcat (buf, "%S3"); | |
6493 | else | |
6494 | strcat (buf, "%B3"); | |
6495 | if (nullify) | |
5a811d43 | 6496 | strcat (buf, " %2,%r1,%%r0\n\tb,n %0"); |
5fbd5940 | 6497 | else |
5a811d43 | 6498 | strcat (buf, " %2,%r1,%%r0\n\tb %0"); |
5fbd5940 | 6499 | } |
0d986529 | 6500 | break; |
6501 | ||
f26036bb | 6502 | default: |
e9ec370e | 6503 | /* The reversed conditional branch must branch over one additional |
f26036bb | 6504 | instruction if the delay slot is filled and needs to be extracted |
e202682d | 6505 | by pa_output_lbranch. If the delay slot is empty or this is a |
f26036bb | 6506 | nullified forward branch, the instruction after the reversed |
6507 | condition branch must be nullified. */ | |
6508 | if (dbr_sequence_length () == 0 | |
6509 | || (nullify && forward_branch_p (insn))) | |
6510 | { | |
6511 | nullify = 1; | |
6512 | xdelay = 0; | |
6513 | operands[4] = GEN_INT (length); | |
6514 | } | |
6515 | else | |
6516 | { | |
6517 | xdelay = 1; | |
6518 | operands[4] = GEN_INT (length + 4); | |
6519 | } | |
c8a0e52b | 6520 | |
6521 | /* Create a reversed conditional branch which branches around | |
6522 | the following insns. */ | |
e9ec370e | 6523 | if (GET_MODE (operands[1]) != DImode) |
6524 | { | |
6525 | if (nullify) | |
6526 | { | |
6527 | if (negated) | |
6528 | strcpy (buf, | |
6529 | "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}"); | |
6530 | else | |
6531 | strcpy (buf, | |
6532 | "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}"); | |
6533 | } | |
6534 | else | |
6535 | { | |
6536 | if (negated) | |
6537 | strcpy (buf, | |
6538 | "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}"); | |
6539 | else | |
6540 | strcpy (buf, | |
6541 | "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}"); | |
6542 | } | |
6543 | } | |
c8a0e52b | 6544 | else |
5e3c5739 | 6545 | { |
e9ec370e | 6546 | if (nullify) |
6547 | { | |
6548 | if (negated) | |
6549 | strcpy (buf, | |
6550 | "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}"); | |
6551 | else | |
6552 | strcpy (buf, | |
6553 | "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}"); | |
6554 | } | |
5e3c5739 | 6555 | else |
e9ec370e | 6556 | { |
6557 | if (negated) | |
6558 | strcpy (buf, | |
6559 | "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}"); | |
6560 | else | |
6561 | strcpy (buf, | |
6562 | "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}"); | |
6563 | } | |
5e3c5739 | 6564 | } |
c8a0e52b | 6565 | |
f26036bb | 6566 | output_asm_insn (buf, operands); |
e202682d | 6567 | return pa_output_lbranch (operands[0], insn, xdelay); |
e9ec370e | 6568 | } |
6569 | return buf; | |
6570 | } | |
c8a0e52b | 6571 | |
f26036bb | 6572 | /* This routine handles output of long unconditional branches that |
6573 | exceed the maximum range of a simple branch instruction. Since | |
6574 | we don't have a register available for the branch, we save register | |
6575 | %r1 in the frame marker, load the branch destination DEST into %r1, | |
6576 | execute the branch, and restore %r1 in the delay slot of the branch. | |
6577 | ||
6578 | Since long branches may have an insn in the delay slot and the | |
6579 | delay slot is used to restore %r1, we in general need to extract | |
6580 | this insn and execute it before the branch. However, to facilitate | |
6581 | use of this function by conditional branches, we also provide an | |
6582 | option to not extract the delay insn so that it will be emitted | |
6583 | after the long branch. So, if there is an insn in the delay slot, | |
6584 | it is extracted if XDELAY is nonzero. | |
6585 | ||
6586 | The lengths of the various long-branch sequences are 20, 16 and 24 | |
6587 | bytes for the portable runtime, non-PIC and PIC cases, respectively. */ | |
c8a0e52b | 6588 | |
e9ec370e | 6589 | const char * |
e202682d | 6590 | pa_output_lbranch (rtx dest, rtx insn, int xdelay) |
e9ec370e | 6591 | { |
6592 | rtx xoperands[2]; | |
6593 | ||
6594 | xoperands[0] = dest; | |
c8a0e52b | 6595 | |
e9ec370e | 6596 | /* First, free up the delay slot. */ |
f26036bb | 6597 | if (xdelay && dbr_sequence_length () != 0) |
e9ec370e | 6598 | { |
6599 | /* We can't handle a jump in the delay slot. */ | |
ecf2283d | 6600 | gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN); |
c8a0e52b | 6601 | |
e9ec370e | 6602 | final_scan_insn (NEXT_INSN (insn), asm_out_file, |
4bf029b0 | 6603 | optimize, 0, NULL); |
c8a0e52b | 6604 | |
e9ec370e | 6605 | /* Now delete the delay insn. */ |
ad4583d9 | 6606 | SET_INSN_DELETED (NEXT_INSN (insn)); |
e9ec370e | 6607 | } |
c8a0e52b | 6608 | |
e9ec370e | 6609 | /* Output an insn to save %r1. The runtime documentation doesn't |
6610 | specify whether the "Clean Up" slot in the callers frame can | |
6611 | be clobbered by the callee. It isn't copied by HP's builtin | |
6612 | alloca, so this suggests that it can be clobbered if necessary. | |
6613 | The "Static Link" location is copied by HP builtin alloca, so | |
6614 | we avoid using it. Using the cleanup slot might be a problem | |
6615 | if we have to interoperate with languages that pass cleanup | |
6616 | information. However, it should be possible to handle these | |
6617 | situations with GCC's asm feature. | |
6618 | ||
6619 | The "Current RP" slot is reserved for the called procedure, so | |
6620 | we try to use it when we don't have a frame of our own. It's | |
6621 | rather unlikely that we won't have a frame when we need to emit | |
6622 | a very long branch. | |
6623 | ||
6624 | Really the way to go long term is a register scavenger; goto | |
6625 | the target of the jump and find a register which we can use | |
6626 | as a scratch to hold the value in %r1. Then, we wouldn't have | |
6627 | to free up the delay slot or clobber a slot that may be needed | |
6628 | for other purposes. */ | |
6629 | if (TARGET_64BIT) | |
6630 | { | |
3072d30e | 6631 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6632 | /* Use the return pointer slot in the frame marker. */ |
6633 | output_asm_insn ("std %%r1,-16(%%r30)", xoperands); | |
6634 | else | |
6635 | /* Use the slot at -40 in the frame marker since HP builtin | |
6636 | alloca doesn't copy it. */ | |
6637 | output_asm_insn ("std %%r1,-40(%%r30)", xoperands); | |
6638 | } | |
6639 | else | |
6640 | { | |
3072d30e | 6641 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6642 | /* Use the return pointer slot in the frame marker. */ |
6643 | output_asm_insn ("stw %%r1,-20(%%r30)", xoperands); | |
6644 | else | |
6645 | /* Use the "Clean Up" slot in the frame marker. In GCC, | |
6646 | the only other use of this location is for copying a | |
6647 | floating point double argument from a floating-point | |
6648 | register to two general registers. The copy is done | |
19ee40ed | 6649 | as an "atomic" operation when outputting a call, so it |
e9ec370e | 6650 | won't interfere with our using the location here. */ |
6651 | output_asm_insn ("stw %%r1,-12(%%r30)", xoperands); | |
6652 | } | |
b70ea764 | 6653 | |
2247cc5f | 6654 | if (TARGET_PORTABLE_RUNTIME) |
6655 | { | |
6656 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6657 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
6658 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6659 | } | |
6660 | else if (flag_pic) | |
e9ec370e | 6661 | { |
6662 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
6663 | if (TARGET_SOM || !TARGET_GAS) | |
6664 | { | |
6665 | xoperands[1] = gen_label_rtx (); | |
6666 | output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands); | |
c5559ed4 | 6667 | targetm.asm_out.internal_label (asm_out_file, "L", |
6668 | CODE_LABEL_NUMBER (xoperands[1])); | |
e9ec370e | 6669 | output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands); |
c8a0e52b | 6670 | } |
e9ec370e | 6671 | else |
6672 | { | |
6673 | output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6674 | output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6675 | } | |
6676 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6677 | } | |
6678 | else | |
6679 | /* Now output a very long branch to the original target. */ | |
6680 | output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands); | |
c8a0e52b | 6681 | |
e9ec370e | 6682 | /* Now restore the value of %r1 in the delay slot. */ |
6683 | if (TARGET_64BIT) | |
6684 | { | |
3072d30e | 6685 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6686 | return "ldd -16(%%r30),%%r1"; |
6687 | else | |
6688 | return "ldd -40(%%r30),%%r1"; | |
6689 | } | |
6690 | else | |
6691 | { | |
3072d30e | 6692 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6693 | return "ldw -20(%%r30),%%r1"; |
6694 | else | |
6695 | return "ldw -12(%%r30),%%r1"; | |
5fbd5940 | 6696 | } |
0d986529 | 6697 | } |
6698 | ||
6d36483b | 6699 | /* This routine handles all the branch-on-bit conditional branch sequences we |
0d986529 | 6700 | might need to generate. It handles nullification of delay slots, |
6701 | varying length branches, negated branches and all combinations of the | |
6702 | above. it returns the appropriate output template to emit the branch. */ | |
6703 | ||
611a88e1 | 6704 | const char * |
e202682d | 6705 | pa_output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
29a4502c | 6706 | { |
0d986529 | 6707 | static char buf[100]; |
ebeae299 | 6708 | bool useskip; |
f26036bb | 6709 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6710 | int length = get_attr_length (insn); | |
6711 | int xdelay; | |
0d986529 | 6712 | |
a361b456 | 6713 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 6714 | asking for a disaster. I do not think this can happen as this pattern |
6d36483b | 6715 | is only used when optimizing; jump optimization should eliminate the |
29a4502c | 6716 | jump. But be prepared just in case. */ |
6d36483b | 6717 | |
317754f4 | 6718 | if (branch_to_delay_slot_p (insn)) |
ece0fa59 | 6719 | return "nop"; |
6d36483b | 6720 | |
5fbd5940 | 6721 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6722 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6723 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6724 | nullify = 1; |
6725 | ||
6726 | /* If this is a short forward conditional branch which did not get | |
6727 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6728 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6729 | nullify = forward_branch_p (insn); |
6730 | ||
6d36483b | 6731 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6732 | extrs instruction. This avoids a single cycle penalty due to |
6733 | mis-predicted branch if we fall through (branch not taken). */ | |
ebeae299 | 6734 | useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; |
0d986529 | 6735 | |
6736 | switch (length) | |
6737 | { | |
6738 | ||
5fbd5940 | 6739 | /* All short conditional branches except backwards with an unfilled |
6740 | delay slot. */ | |
5a1231ef | 6741 | case 4: |
0d986529 | 6742 | if (useskip) |
e4065f95 | 6743 | strcpy (buf, "{extrs,|extrw,s,}"); |
6d36483b | 6744 | else |
0d986529 | 6745 | strcpy (buf, "bb,"); |
5e3c5739 | 6746 | if (useskip && GET_MODE (operands[0]) == DImode) |
6747 | strcpy (buf, "extrd,s,*"); | |
6748 | else if (GET_MODE (operands[0]) == DImode) | |
6749 | strcpy (buf, "bb,*"); | |
0d986529 | 6750 | if ((which == 0 && negated) |
6751 | || (which == 1 && ! negated)) | |
6752 | strcat (buf, ">="); | |
6753 | else | |
6754 | strcat (buf, "<"); | |
6755 | if (useskip) | |
5a811d43 | 6756 | strcat (buf, " %0,%1,1,%%r0"); |
0d986529 | 6757 | else if (nullify && negated) |
317754f4 | 6758 | { |
6759 | if (branch_needs_nop_p (insn)) | |
6760 | strcat (buf, ",n %0,%1,%3%#"); | |
6761 | else | |
6762 | strcat (buf, ",n %0,%1,%3"); | |
6763 | } | |
0d986529 | 6764 | else if (nullify && ! negated) |
317754f4 | 6765 | { |
6766 | if (branch_needs_nop_p (insn)) | |
6767 | strcat (buf, ",n %0,%1,%2%#"); | |
6768 | else | |
6769 | strcat (buf, ",n %0,%1,%2"); | |
6770 | } | |
0d986529 | 6771 | else if (! nullify && negated) |
317754f4 | 6772 | strcat (buf, " %0,%1,%3"); |
0d986529 | 6773 | else if (! nullify && ! negated) |
5fbd5940 | 6774 | strcat (buf, " %0,%1,%2"); |
0d986529 | 6775 | break; |
6776 | ||
87fcb603 | 6777 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6778 | unfilled delay slot is treated just like a long backward branch |
6779 | with an unfilled delay slot. */ | |
5a1231ef | 6780 | case 8: |
5fbd5940 | 6781 | /* Handle weird backwards branch with a filled delay slot |
f26036bb | 6782 | which is nullified. */ |
5fbd5940 | 6783 | if (dbr_sequence_length () != 0 |
6784 | && ! forward_branch_p (insn) | |
6785 | && nullify) | |
6786 | { | |
6787 | strcpy (buf, "bb,"); | |
5e3c5739 | 6788 | if (GET_MODE (operands[0]) == DImode) |
6789 | strcat (buf, "*"); | |
5fbd5940 | 6790 | if ((which == 0 && negated) |
6791 | || (which == 1 && ! negated)) | |
6792 | strcat (buf, "<"); | |
6793 | else | |
6794 | strcat (buf, ">="); | |
6795 | if (negated) | |
5a811d43 | 6796 | strcat (buf, ",n %0,%1,.+12\n\tb %3"); |
5fbd5940 | 6797 | else |
5a811d43 | 6798 | strcat (buf, ",n %0,%1,.+12\n\tb %2"); |
5fbd5940 | 6799 | } |
43f0c1f2 | 6800 | /* Handle short backwards branch with an unfilled delay slot. |
6801 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6802 | taken and untaken branches. */ | |
6803 | else if (dbr_sequence_length () == 0 | |
6804 | && ! forward_branch_p (insn) | |
47fc0706 | 6805 | && INSN_ADDRESSES_SET_P () |
6806 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6807 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6808 | { |
6809 | strcpy (buf, "bb,"); | |
5e3c5739 | 6810 | if (GET_MODE (operands[0]) == DImode) |
6811 | strcat (buf, "*"); | |
43f0c1f2 | 6812 | if ((which == 0 && negated) |
6813 | || (which == 1 && ! negated)) | |
6814 | strcat (buf, ">="); | |
6815 | else | |
6816 | strcat (buf, "<"); | |
6817 | if (negated) | |
6818 | strcat (buf, " %0,%1,%3%#"); | |
6819 | else | |
6820 | strcat (buf, " %0,%1,%2%#"); | |
6821 | } | |
0d986529 | 6822 | else |
5fbd5940 | 6823 | { |
5e3c5739 | 6824 | if (GET_MODE (operands[0]) == DImode) |
6825 | strcpy (buf, "extrd,s,*"); | |
f26036bb | 6826 | else |
6827 | strcpy (buf, "{extrs,|extrw,s,}"); | |
5fbd5940 | 6828 | if ((which == 0 && negated) |
6829 | || (which == 1 && ! negated)) | |
6830 | strcat (buf, "<"); | |
6831 | else | |
6832 | strcat (buf, ">="); | |
6833 | if (nullify && negated) | |
c6ae275c | 6834 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %3"); |
5fbd5940 | 6835 | else if (nullify && ! negated) |
c6ae275c | 6836 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %2"); |
5fbd5940 | 6837 | else if (negated) |
5a811d43 | 6838 | strcat (buf, " %0,%1,1,%%r0\n\tb %3"); |
6d36483b | 6839 | else |
5a811d43 | 6840 | strcat (buf, " %0,%1,1,%%r0\n\tb %2"); |
5fbd5940 | 6841 | } |
0d986529 | 6842 | break; |
6843 | ||
6844 | default: | |
f26036bb | 6845 | /* The reversed conditional branch must branch over one additional |
6846 | instruction if the delay slot is filled and needs to be extracted | |
e202682d | 6847 | by pa_output_lbranch. If the delay slot is empty or this is a |
f26036bb | 6848 | nullified forward branch, the instruction after the reversed |
6849 | condition branch must be nullified. */ | |
6850 | if (dbr_sequence_length () == 0 | |
6851 | || (nullify && forward_branch_p (insn))) | |
6852 | { | |
6853 | nullify = 1; | |
6854 | xdelay = 0; | |
d9e3874e | 6855 | operands[4] = GEN_INT (length); |
f26036bb | 6856 | } |
6857 | else | |
6858 | { | |
6859 | xdelay = 1; | |
d9e3874e | 6860 | operands[4] = GEN_INT (length + 4); |
f26036bb | 6861 | } |
6862 | ||
6863 | if (GET_MODE (operands[0]) == DImode) | |
d9e3874e | 6864 | strcpy (buf, "bb,*"); |
f26036bb | 6865 | else |
d9e3874e | 6866 | strcpy (buf, "bb,"); |
f26036bb | 6867 | if ((which == 0 && negated) |
6868 | || (which == 1 && !negated)) | |
d9e3874e | 6869 | strcat (buf, "<"); |
f26036bb | 6870 | else |
d9e3874e | 6871 | strcat (buf, ">="); |
f26036bb | 6872 | if (nullify) |
d9e3874e | 6873 | strcat (buf, ",n %0,%1,.+%4"); |
f26036bb | 6874 | else |
d9e3874e | 6875 | strcat (buf, " %0,%1,.+%4"); |
f26036bb | 6876 | output_asm_insn (buf, operands); |
e202682d | 6877 | return pa_output_lbranch (negated ? operands[3] : operands[2], |
6878 | insn, xdelay); | |
5fbd5940 | 6879 | } |
0d986529 | 6880 | return buf; |
6881 | } | |
6882 | ||
c7a4e712 | 6883 | /* This routine handles all the branch-on-variable-bit conditional branch |
6884 | sequences we might need to generate. It handles nullification of delay | |
6885 | slots, varying length branches, negated branches and all combinations | |
6886 | of the above. it returns the appropriate output template to emit the | |
6887 | branch. */ | |
6888 | ||
611a88e1 | 6889 | const char * |
e202682d | 6890 | pa_output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, |
6891 | int which) | |
c7a4e712 | 6892 | { |
6893 | static char buf[100]; | |
ebeae299 | 6894 | bool useskip; |
f26036bb | 6895 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6896 | int length = get_attr_length (insn); | |
6897 | int xdelay; | |
c7a4e712 | 6898 | |
a361b456 | 6899 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
c7a4e712 | 6900 | asking for a disaster. I do not think this can happen as this pattern |
6901 | is only used when optimizing; jump optimization should eliminate the | |
6902 | jump. But be prepared just in case. */ | |
6903 | ||
317754f4 | 6904 | if (branch_to_delay_slot_p (insn)) |
ece0fa59 | 6905 | return "nop"; |
c7a4e712 | 6906 | |
6907 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6908 | as it can nullify the delay slot and save a nop. */ | |
6909 | if (length == 8 && dbr_sequence_length () == 0) | |
6910 | nullify = 1; | |
6911 | ||
6912 | /* If this is a short forward conditional branch which did not get | |
6913 | its delay slot filled, the delay slot can still be nullified. */ | |
6914 | if (! nullify && length == 4 && dbr_sequence_length () == 0) | |
6915 | nullify = forward_branch_p (insn); | |
6916 | ||
6917 | /* A forward branch over a single nullified insn can be done with a | |
6918 | extrs instruction. This avoids a single cycle penalty due to | |
6919 | mis-predicted branch if we fall through (branch not taken). */ | |
ebeae299 | 6920 | useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; |
c7a4e712 | 6921 | |
6922 | switch (length) | |
6923 | { | |
6924 | ||
6925 | /* All short conditional branches except backwards with an unfilled | |
6926 | delay slot. */ | |
6927 | case 4: | |
6928 | if (useskip) | |
e4065f95 | 6929 | strcpy (buf, "{vextrs,|extrw,s,}"); |
c7a4e712 | 6930 | else |
e4065f95 | 6931 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6932 | if (useskip && GET_MODE (operands[0]) == DImode) |
e75269fd | 6933 | strcpy (buf, "extrd,s,*"); |
5e3c5739 | 6934 | else if (GET_MODE (operands[0]) == DImode) |
6935 | strcpy (buf, "bb,*"); | |
c7a4e712 | 6936 | if ((which == 0 && negated) |
6937 | || (which == 1 && ! negated)) | |
6938 | strcat (buf, ">="); | |
6939 | else | |
6940 | strcat (buf, "<"); | |
6941 | if (useskip) | |
e4065f95 | 6942 | strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}"); |
c7a4e712 | 6943 | else if (nullify && negated) |
317754f4 | 6944 | { |
6945 | if (branch_needs_nop_p (insn)) | |
6946 | strcat (buf, "{,n %0,%3%#|,n %0,%%sar,%3%#}"); | |
6947 | else | |
6948 | strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}"); | |
6949 | } | |
c7a4e712 | 6950 | else if (nullify && ! negated) |
317754f4 | 6951 | { |
6952 | if (branch_needs_nop_p (insn)) | |
6953 | strcat (buf, "{,n %0,%2%#|,n %0,%%sar,%2%#}"); | |
6954 | else | |
6955 | strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}"); | |
6956 | } | |
c7a4e712 | 6957 | else if (! nullify && negated) |
317754f4 | 6958 | strcat (buf, "{ %0,%3| %0,%%sar,%3}"); |
c7a4e712 | 6959 | else if (! nullify && ! negated) |
e4065f95 | 6960 | strcat (buf, "{ %0,%2| %0,%%sar,%2}"); |
c7a4e712 | 6961 | break; |
6962 | ||
87fcb603 | 6963 | /* All long conditionals. Note a short backward branch with an |
c7a4e712 | 6964 | unfilled delay slot is treated just like a long backward branch |
6965 | with an unfilled delay slot. */ | |
6966 | case 8: | |
6967 | /* Handle weird backwards branch with a filled delay slot | |
f26036bb | 6968 | which is nullified. */ |
c7a4e712 | 6969 | if (dbr_sequence_length () != 0 |
6970 | && ! forward_branch_p (insn) | |
6971 | && nullify) | |
6972 | { | |
e4065f95 | 6973 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6974 | if (GET_MODE (operands[0]) == DImode) |
6975 | strcat (buf, "*"); | |
c7a4e712 | 6976 | if ((which == 0 && negated) |
6977 | || (which == 1 && ! negated)) | |
6978 | strcat (buf, "<"); | |
6979 | else | |
6980 | strcat (buf, ">="); | |
6981 | if (negated) | |
e4065f95 | 6982 | strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}"); |
c7a4e712 | 6983 | else |
e4065f95 | 6984 | strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}"); |
c7a4e712 | 6985 | } |
6986 | /* Handle short backwards branch with an unfilled delay slot. | |
6987 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6988 | taken and untaken branches. */ | |
6989 | else if (dbr_sequence_length () == 0 | |
6990 | && ! forward_branch_p (insn) | |
47fc0706 | 6991 | && INSN_ADDRESSES_SET_P () |
6992 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6993 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
c7a4e712 | 6994 | { |
e4065f95 | 6995 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6996 | if (GET_MODE (operands[0]) == DImode) |
6997 | strcat (buf, "*"); | |
c7a4e712 | 6998 | if ((which == 0 && negated) |
6999 | || (which == 1 && ! negated)) | |
7000 | strcat (buf, ">="); | |
7001 | else | |
7002 | strcat (buf, "<"); | |
7003 | if (negated) | |
e4065f95 | 7004 | strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}"); |
c7a4e712 | 7005 | else |
e4065f95 | 7006 | strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}"); |
c7a4e712 | 7007 | } |
7008 | else | |
7009 | { | |
e4065f95 | 7010 | strcpy (buf, "{vextrs,|extrw,s,}"); |
5e3c5739 | 7011 | if (GET_MODE (operands[0]) == DImode) |
7012 | strcpy (buf, "extrd,s,*"); | |
c7a4e712 | 7013 | if ((which == 0 && negated) |
7014 | || (which == 1 && ! negated)) | |
7015 | strcat (buf, "<"); | |
7016 | else | |
7017 | strcat (buf, ">="); | |
7018 | if (nullify && negated) | |
e4065f95 | 7019 | strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}"); |
c7a4e712 | 7020 | else if (nullify && ! negated) |
e4065f95 | 7021 | strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}"); |
c7a4e712 | 7022 | else if (negated) |
e4065f95 | 7023 | strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}"); |
c7a4e712 | 7024 | else |
e4065f95 | 7025 | strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}"); |
c7a4e712 | 7026 | } |
7027 | break; | |
7028 | ||
7029 | default: | |
f26036bb | 7030 | /* The reversed conditional branch must branch over one additional |
7031 | instruction if the delay slot is filled and needs to be extracted | |
e202682d | 7032 | by pa_output_lbranch. If the delay slot is empty or this is a |
f26036bb | 7033 | nullified forward branch, the instruction after the reversed |
7034 | condition branch must be nullified. */ | |
7035 | if (dbr_sequence_length () == 0 | |
7036 | || (nullify && forward_branch_p (insn))) | |
7037 | { | |
7038 | nullify = 1; | |
7039 | xdelay = 0; | |
d9e3874e | 7040 | operands[4] = GEN_INT (length); |
f26036bb | 7041 | } |
7042 | else | |
7043 | { | |
7044 | xdelay = 1; | |
d9e3874e | 7045 | operands[4] = GEN_INT (length + 4); |
f26036bb | 7046 | } |
7047 | ||
7048 | if (GET_MODE (operands[0]) == DImode) | |
d9e3874e | 7049 | strcpy (buf, "bb,*"); |
f26036bb | 7050 | else |
d9e3874e | 7051 | strcpy (buf, "{bvb,|bb,}"); |
f26036bb | 7052 | if ((which == 0 && negated) |
7053 | || (which == 1 && !negated)) | |
d9e3874e | 7054 | strcat (buf, "<"); |
f26036bb | 7055 | else |
d9e3874e | 7056 | strcat (buf, ">="); |
f26036bb | 7057 | if (nullify) |
d9e3874e | 7058 | strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}"); |
f26036bb | 7059 | else |
d9e3874e | 7060 | strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}"); |
f26036bb | 7061 | output_asm_insn (buf, operands); |
e202682d | 7062 | return pa_output_lbranch (negated ? operands[3] : operands[2], |
7063 | insn, xdelay); | |
c7a4e712 | 7064 | } |
7065 | return buf; | |
7066 | } | |
7067 | ||
29a4502c | 7068 | /* Return the output template for emitting a dbra type insn. |
7069 | ||
7070 | Note it may perform some output operations on its own before | |
7071 | returning the final output string. */ | |
611a88e1 | 7072 | const char * |
e202682d | 7073 | pa_output_dbra (rtx *operands, rtx insn, int which_alternative) |
29a4502c | 7074 | { |
f26036bb | 7075 | int length = get_attr_length (insn); |
29a4502c | 7076 | |
a361b456 | 7077 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 7078 | asking for a disaster. Be prepared! */ |
7079 | ||
317754f4 | 7080 | if (branch_to_delay_slot_p (insn)) |
29a4502c | 7081 | { |
7082 | if (which_alternative == 0) | |
7083 | return "ldo %1(%0),%0"; | |
7084 | else if (which_alternative == 1) | |
7085 | { | |
ea52c577 | 7086 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands); |
7087 | output_asm_insn ("ldw -16(%%r30),%4", operands); | |
34940871 | 7088 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
e4065f95 | 7089 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 7090 | } |
7091 | else | |
7092 | { | |
7093 | output_asm_insn ("ldw %0,%4", operands); | |
7094 | return "ldo %1(%4),%4\n\tstw %4,%0"; | |
7095 | } | |
7096 | } | |
7097 | ||
7098 | if (which_alternative == 0) | |
7099 | { | |
7100 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
f26036bb | 7101 | int xdelay; |
29a4502c | 7102 | |
7103 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
7104 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 7105 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 7106 | nullify = 1; |
7107 | ||
7108 | /* If this is a short forward conditional branch which did not get | |
7109 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 7110 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 7111 | nullify = forward_branch_p (insn); |
7112 | ||
ecf2283d | 7113 | switch (length) |
29a4502c | 7114 | { |
ecf2283d | 7115 | case 4: |
7116 | if (nullify) | |
317754f4 | 7117 | { |
7118 | if (branch_needs_nop_p (insn)) | |
7119 | return "addib,%C2,n %1,%0,%3%#"; | |
7120 | else | |
7121 | return "addib,%C2,n %1,%0,%3"; | |
7122 | } | |
ecf2283d | 7123 | else |
7124 | return "addib,%C2 %1,%0,%3"; | |
7125 | ||
7126 | case 8: | |
6d36483b | 7127 | /* Handle weird backwards branch with a fulled delay slot |
29a4502c | 7128 | which is nullified. */ |
7129 | if (dbr_sequence_length () != 0 | |
7130 | && ! forward_branch_p (insn) | |
7131 | && nullify) | |
5a811d43 | 7132 | return "addib,%N2,n %1,%0,.+12\n\tb %3"; |
43f0c1f2 | 7133 | /* Handle short backwards branch with an unfilled delay slot. |
7134 | Using a addb;nop rather than addi;bl saves 1 cycle for both | |
7135 | taken and untaken branches. */ | |
7136 | else if (dbr_sequence_length () == 0 | |
7137 | && ! forward_branch_p (insn) | |
47fc0706 | 7138 | && INSN_ADDRESSES_SET_P () |
7139 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
7140 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 7141 | return "addib,%C2 %1,%0,%3%#"; |
6d36483b | 7142 | |
7143 | /* Handle normal cases. */ | |
29a4502c | 7144 | if (nullify) |
5a811d43 | 7145 | return "addi,%N2 %1,%0,%0\n\tb,n %3"; |
29a4502c | 7146 | else |
5a811d43 | 7147 | return "addi,%N2 %1,%0,%0\n\tb %3"; |
ecf2283d | 7148 | |
7149 | default: | |
f26036bb | 7150 | /* The reversed conditional branch must branch over one additional |
7151 | instruction if the delay slot is filled and needs to be extracted | |
e202682d | 7152 | by pa_output_lbranch. If the delay slot is empty or this is a |
f26036bb | 7153 | nullified forward branch, the instruction after the reversed |
7154 | condition branch must be nullified. */ | |
7155 | if (dbr_sequence_length () == 0 | |
7156 | || (nullify && forward_branch_p (insn))) | |
7157 | { | |
7158 | nullify = 1; | |
7159 | xdelay = 0; | |
7160 | operands[4] = GEN_INT (length); | |
7161 | } | |
7162 | else | |
7163 | { | |
7164 | xdelay = 1; | |
7165 | operands[4] = GEN_INT (length + 4); | |
7166 | } | |
7167 | ||
7168 | if (nullify) | |
7169 | output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands); | |
7170 | else | |
7171 | output_asm_insn ("addib,%N2 %1,%0,.+%4", operands); | |
7172 | ||
e202682d | 7173 | return pa_output_lbranch (operands[3], insn, xdelay); |
29a4502c | 7174 | } |
ecf2283d | 7175 | |
29a4502c | 7176 | } |
7177 | /* Deal with gross reload from FP register case. */ | |
7178 | else if (which_alternative == 1) | |
7179 | { | |
7180 | /* Move loop counter from FP register to MEM then into a GR, | |
7181 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 7182 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 7183 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4", |
7184 | operands); | |
34940871 | 7185 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
f26036bb | 7186 | if (length == 24) |
e4065f95 | 7187 | return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7188 | else if (length == 28) |
e4065f95 | 7189 | return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7190 | else |
7191 | { | |
d9e3874e | 7192 | operands[5] = GEN_INT (length - 16); |
7193 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands); | |
f26036bb | 7194 | output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands); |
e202682d | 7195 | return pa_output_lbranch (operands[3], insn, 0); |
f26036bb | 7196 | } |
29a4502c | 7197 | } |
7198 | /* Deal with gross reload from memory case. */ | |
7199 | else | |
7200 | { | |
7201 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 7202 | happens in the branch's delay slot. */ |
29a4502c | 7203 | output_asm_insn ("ldw %0,%4", operands); |
f26036bb | 7204 | if (length == 12) |
29a4502c | 7205 | return "addib,%C2 %1,%4,%3\n\tstw %4,%0"; |
f26036bb | 7206 | else if (length == 16) |
5a811d43 | 7207 | return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0"; |
f26036bb | 7208 | else |
7209 | { | |
d9e3874e | 7210 | operands[5] = GEN_INT (length - 4); |
7211 | output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands); | |
e202682d | 7212 | return pa_output_lbranch (operands[3], insn, 0); |
f26036bb | 7213 | } |
29a4502c | 7214 | } |
7215 | } | |
7216 | ||
f26036bb | 7217 | /* Return the output template for emitting a movb type insn. |
29a4502c | 7218 | |
7219 | Note it may perform some output operations on its own before | |
7220 | returning the final output string. */ | |
611a88e1 | 7221 | const char * |
e202682d | 7222 | pa_output_movb (rtx *operands, rtx insn, int which_alternative, |
5c1d8983 | 7223 | int reverse_comparison) |
29a4502c | 7224 | { |
f26036bb | 7225 | int length = get_attr_length (insn); |
29a4502c | 7226 | |
a361b456 | 7227 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 7228 | asking for a disaster. Be prepared! */ |
7229 | ||
317754f4 | 7230 | if (branch_to_delay_slot_p (insn)) |
29a4502c | 7231 | { |
7232 | if (which_alternative == 0) | |
7233 | return "copy %1,%0"; | |
7234 | else if (which_alternative == 1) | |
7235 | { | |
ea52c577 | 7236 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
e4065f95 | 7237 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 7238 | } |
546a40bd | 7239 | else if (which_alternative == 2) |
29a4502c | 7240 | return "stw %1,%0"; |
546a40bd | 7241 | else |
7242 | return "mtsar %r1"; | |
29a4502c | 7243 | } |
7244 | ||
7245 | /* Support the second variant. */ | |
7246 | if (reverse_comparison) | |
7247 | PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2]))); | |
7248 | ||
7249 | if (which_alternative == 0) | |
7250 | { | |
7251 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
f26036bb | 7252 | int xdelay; |
29a4502c | 7253 | |
7254 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
7255 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 7256 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 7257 | nullify = 1; |
7258 | ||
7259 | /* If this is a short forward conditional branch which did not get | |
7260 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 7261 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 7262 | nullify = forward_branch_p (insn); |
7263 | ||
ecf2283d | 7264 | switch (length) |
29a4502c | 7265 | { |
ecf2283d | 7266 | case 4: |
7267 | if (nullify) | |
317754f4 | 7268 | { |
7269 | if (branch_needs_nop_p (insn)) | |
7270 | return "movb,%C2,n %1,%0,%3%#"; | |
7271 | else | |
7272 | return "movb,%C2,n %1,%0,%3"; | |
7273 | } | |
ecf2283d | 7274 | else |
7275 | return "movb,%C2 %1,%0,%3"; | |
7276 | ||
7277 | case 8: | |
6d36483b | 7278 | /* Handle weird backwards branch with a filled delay slot |
29a4502c | 7279 | which is nullified. */ |
7280 | if (dbr_sequence_length () != 0 | |
7281 | && ! forward_branch_p (insn) | |
7282 | && nullify) | |
5a811d43 | 7283 | return "movb,%N2,n %1,%0,.+12\n\tb %3"; |
6d36483b | 7284 | |
43f0c1f2 | 7285 | /* Handle short backwards branch with an unfilled delay slot. |
7286 | Using a movb;nop rather than or;bl saves 1 cycle for both | |
7287 | taken and untaken branches. */ | |
7288 | else if (dbr_sequence_length () == 0 | |
7289 | && ! forward_branch_p (insn) | |
47fc0706 | 7290 | && INSN_ADDRESSES_SET_P () |
7291 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
7292 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 7293 | return "movb,%C2 %1,%0,%3%#"; |
6d36483b | 7294 | /* Handle normal cases. */ |
29a4502c | 7295 | if (nullify) |
5a811d43 | 7296 | return "or,%N2 %1,%%r0,%0\n\tb,n %3"; |
29a4502c | 7297 | else |
5a811d43 | 7298 | return "or,%N2 %1,%%r0,%0\n\tb %3"; |
ecf2283d | 7299 | |
7300 | default: | |
f26036bb | 7301 | /* The reversed conditional branch must branch over one additional |
7302 | instruction if the delay slot is filled and needs to be extracted | |
e202682d | 7303 | by pa_output_lbranch. If the delay slot is empty or this is a |
f26036bb | 7304 | nullified forward branch, the instruction after the reversed |
7305 | condition branch must be nullified. */ | |
7306 | if (dbr_sequence_length () == 0 | |
7307 | || (nullify && forward_branch_p (insn))) | |
7308 | { | |
7309 | nullify = 1; | |
7310 | xdelay = 0; | |
7311 | operands[4] = GEN_INT (length); | |
7312 | } | |
7313 | else | |
7314 | { | |
7315 | xdelay = 1; | |
7316 | operands[4] = GEN_INT (length + 4); | |
7317 | } | |
7318 | ||
7319 | if (nullify) | |
7320 | output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands); | |
7321 | else | |
7322 | output_asm_insn ("movb,%N2 %1,%0,.+%4", operands); | |
7323 | ||
e202682d | 7324 | return pa_output_lbranch (operands[3], insn, xdelay); |
29a4502c | 7325 | } |
29a4502c | 7326 | } |
f26036bb | 7327 | /* Deal with gross reload for FP destination register case. */ |
29a4502c | 7328 | else if (which_alternative == 1) |
7329 | { | |
f26036bb | 7330 | /* Move source register to MEM, perform the branch test, then |
7331 | finally load the FP register from MEM from within the branch's | |
7332 | delay slot. */ | |
ea52c577 | 7333 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
f26036bb | 7334 | if (length == 12) |
e4065f95 | 7335 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7336 | else if (length == 16) |
e4065f95 | 7337 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7338 | else |
7339 | { | |
d9e3874e | 7340 | operands[4] = GEN_INT (length - 4); |
7341 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands); | |
f26036bb | 7342 | output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands); |
e202682d | 7343 | return pa_output_lbranch (operands[3], insn, 0); |
f26036bb | 7344 | } |
29a4502c | 7345 | } |
7346 | /* Deal with gross reload from memory case. */ | |
546a40bd | 7347 | else if (which_alternative == 2) |
29a4502c | 7348 | { |
7349 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 7350 | happens in the branch's delay slot. */ |
f26036bb | 7351 | if (length == 8) |
e4065f95 | 7352 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0"; |
f26036bb | 7353 | else if (length == 12) |
e4065f95 | 7354 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0"; |
f26036bb | 7355 | else |
7356 | { | |
d9e3874e | 7357 | operands[4] = GEN_INT (length); |
7358 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0", | |
7359 | operands); | |
e202682d | 7360 | return pa_output_lbranch (operands[3], insn, 0); |
f26036bb | 7361 | } |
29a4502c | 7362 | } |
546a40bd | 7363 | /* Handle SAR as a destination. */ |
7364 | else | |
7365 | { | |
f26036bb | 7366 | if (length == 8) |
e4065f95 | 7367 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1"; |
f26036bb | 7368 | else if (length == 12) |
be7770ad | 7369 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1"; |
f26036bb | 7370 | else |
7371 | { | |
d9e3874e | 7372 | operands[4] = GEN_INT (length); |
7373 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1", | |
7374 | operands); | |
e202682d | 7375 | return pa_output_lbranch (operands[3], insn, 0); |
f26036bb | 7376 | } |
546a40bd | 7377 | } |
29a4502c | 7378 | } |
7379 | ||
ece88821 | 7380 | /* Copy any FP arguments in INSN into integer registers. */ |
7381 | static void | |
5c1d8983 | 7382 | copy_fp_args (rtx insn) |
ece88821 | 7383 | { |
7384 | rtx link; | |
7385 | rtx xoperands[2]; | |
29a4502c | 7386 | |
ece88821 | 7387 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
7388 | { | |
7389 | int arg_mode, regno; | |
7390 | rtx use = XEXP (link, 0); | |
3683f840 | 7391 | |
ece88821 | 7392 | if (! (GET_CODE (use) == USE |
7393 | && GET_CODE (XEXP (use, 0)) == REG | |
7394 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
7395 | continue; | |
d6686e21 | 7396 | |
ece88821 | 7397 | arg_mode = GET_MODE (XEXP (use, 0)); |
7398 | regno = REGNO (XEXP (use, 0)); | |
5e3c5739 | 7399 | |
ece88821 | 7400 | /* Is it a floating point register? */ |
7401 | if (regno >= 32 && regno <= 39) | |
7402 | { | |
7403 | /* Copy the FP register into an integer register via memory. */ | |
7404 | if (arg_mode == SFmode) | |
7405 | { | |
7406 | xoperands[0] = XEXP (use, 0); | |
7407 | xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2); | |
7408 | output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands); | |
7409 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
7410 | } | |
7411 | else | |
7412 | { | |
7413 | xoperands[0] = XEXP (use, 0); | |
7414 | xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2); | |
7415 | output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands); | |
7416 | output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands); | |
7417 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
7418 | } | |
7419 | } | |
06ddb6f8 | 7420 | } |
ece88821 | 7421 | } |
7422 | ||
7423 | /* Compute length of the FP argument copy sequence for INSN. */ | |
7424 | static int | |
5c1d8983 | 7425 | length_fp_args (rtx insn) |
ece88821 | 7426 | { |
7427 | int length = 0; | |
7428 | rtx link; | |
06ddb6f8 | 7429 | |
ece88821 | 7430 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
c7a4e712 | 7431 | { |
ece88821 | 7432 | int arg_mode, regno; |
7433 | rtx use = XEXP (link, 0); | |
7434 | ||
7435 | if (! (GET_CODE (use) == USE | |
7436 | && GET_CODE (XEXP (use, 0)) == REG | |
7437 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
7438 | continue; | |
c7a4e712 | 7439 | |
ece88821 | 7440 | arg_mode = GET_MODE (XEXP (use, 0)); |
7441 | regno = REGNO (XEXP (use, 0)); | |
7442 | ||
7443 | /* Is it a floating point register? */ | |
7444 | if (regno >= 32 && regno <= 39) | |
c7a4e712 | 7445 | { |
ece88821 | 7446 | if (arg_mode == SFmode) |
7447 | length += 8; | |
7448 | else | |
7449 | length += 12; | |
c7a4e712 | 7450 | } |
ece88821 | 7451 | } |
c7a4e712 | 7452 | |
ece88821 | 7453 | return length; |
7454 | } | |
b70ea764 | 7455 | |
cd0dfcc5 | 7456 | /* Return the attribute length for the millicode call instruction INSN. |
e202682d | 7457 | The length must match the code generated by pa_output_millicode_call. |
cd0dfcc5 | 7458 | We include the delay slot in the returned length as it is better to |
ece88821 | 7459 | over estimate the length than to under estimate it. */ |
b29897dd | 7460 | |
ece88821 | 7461 | int |
e202682d | 7462 | pa_attr_length_millicode_call (rtx insn) |
ece88821 | 7463 | { |
cd0dfcc5 | 7464 | unsigned long distance = -1; |
8a05c3c2 | 7465 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
ece88821 | 7466 | |
cd0dfcc5 | 7467 | if (INSN_ADDRESSES_SET_P ()) |
7468 | { | |
2247cc5f | 7469 | distance = (total + insn_current_reference_address (insn)); |
7470 | if (distance < total) | |
cd0dfcc5 | 7471 | distance = -1; |
7472 | } | |
ece88821 | 7473 | |
7474 | if (TARGET_64BIT) | |
7475 | { | |
7476 | if (!TARGET_LONG_CALLS && distance < 7600000) | |
cd0dfcc5 | 7477 | return 8; |
ece88821 | 7478 | |
cd0dfcc5 | 7479 | return 20; |
ece88821 | 7480 | } |
7481 | else if (TARGET_PORTABLE_RUNTIME) | |
cd0dfcc5 | 7482 | return 24; |
ece88821 | 7483 | else |
7484 | { | |
4f12c67a | 7485 | if (!TARGET_LONG_CALLS && distance < MAX_PCREL17F_OFFSET) |
cd0dfcc5 | 7486 | return 8; |
ece88821 | 7487 | |
7488 | if (TARGET_LONG_ABS_CALL && !flag_pic) | |
cd0dfcc5 | 7489 | return 12; |
ece88821 | 7490 | |
cd0dfcc5 | 7491 | return 24; |
ece88821 | 7492 | } |
7493 | } | |
7494 | ||
7495 | /* INSN is a function call. It may have an unconditional jump | |
7496 | in its delay slot. | |
b29897dd | 7497 | |
ece88821 | 7498 | CALL_DEST is the routine we are calling. */ |
b29897dd | 7499 | |
ece88821 | 7500 | const char * |
e202682d | 7501 | pa_output_millicode_call (rtx insn, rtx call_dest) |
ece88821 | 7502 | { |
7503 | int attr_length = get_attr_length (insn); | |
7504 | int seq_length = dbr_sequence_length (); | |
7505 | int distance; | |
7506 | rtx seq_insn; | |
7507 | rtx xoperands[3]; | |
b29897dd | 7508 | |
ece88821 | 7509 | xoperands[0] = call_dest; |
7510 | xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31); | |
7511 | ||
7512 | /* Handle the common case where we are sure that the branch will | |
7513 | reach the beginning of the $CODE$ subspace. The within reach | |
7514 | form of the $$sh_func_adrs call has a length of 28. Because | |
a8b24921 | 7515 | it has an attribute type of multi, it never has a nonzero |
ece88821 | 7516 | sequence length. The length of the $$sh_func_adrs is the same |
7517 | as certain out of reach PIC calls to other routines. */ | |
7518 | if (!TARGET_LONG_CALLS | |
7519 | && ((seq_length == 0 | |
7520 | && (attr_length == 12 | |
7521 | || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI))) | |
7522 | || (seq_length != 0 && attr_length == 8))) | |
7523 | { | |
7524 | output_asm_insn ("{bl|b,l} %0,%2", xoperands); | |
7525 | } | |
7526 | else | |
7527 | { | |
7528 | if (TARGET_64BIT) | |
7529 | { | |
7530 | /* It might seem that one insn could be saved by accessing | |
7531 | the millicode function using the linkage table. However, | |
7532 | this doesn't work in shared libraries and other dynamically | |
7533 | loaded objects. Using a pc-relative sequence also avoids | |
7534 | problems related to the implicit use of the gp register. */ | |
7535 | output_asm_insn ("b,l .+8,%%r1", xoperands); | |
9bd9af5d | 7536 | |
7537 | if (TARGET_GAS) | |
7538 | { | |
7539 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); | |
7540 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
7541 | } | |
7542 | else | |
7543 | { | |
7544 | xoperands[1] = gen_label_rtx (); | |
7545 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
c5559ed4 | 7546 | targetm.asm_out.internal_label (asm_out_file, "L", |
9bd9af5d | 7547 | CODE_LABEL_NUMBER (xoperands[1])); |
7548 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
7549 | } | |
7550 | ||
ece88821 | 7551 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); |
c7a4e712 | 7552 | } |
c7a4e712 | 7553 | else if (TARGET_PORTABLE_RUNTIME) |
7554 | { | |
ece88821 | 7555 | /* Pure portable runtime doesn't allow be/ble; we also don't |
7556 | have PIC support in the assembler/linker, so this sequence | |
7557 | is needed. */ | |
c7a4e712 | 7558 | |
ece88821 | 7559 | /* Get the address of our target into %r1. */ |
7560 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
7561 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
c7a4e712 | 7562 | |
ece88821 | 7563 | /* Get our return address into %r31. */ |
7564 | output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands); | |
7565 | output_asm_insn ("addi 8,%%r31,%%r31", xoperands); | |
c7a4e712 | 7566 | |
ece88821 | 7567 | /* Jump to our target address in %r1. */ |
7568 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 7569 | } |
ece88821 | 7570 | else if (!flag_pic) |
c7a4e712 | 7571 | { |
ece88821 | 7572 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
356267e0 | 7573 | if (TARGET_PA_20) |
ece88821 | 7574 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands); |
356267e0 | 7575 | else |
ece88821 | 7576 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); |
c7a4e712 | 7577 | } |
ece88821 | 7578 | else |
c7a4e712 | 7579 | { |
9bd9af5d | 7580 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
7581 | output_asm_insn ("addi 16,%%r1,%%r31", xoperands); | |
7582 | ||
ece88821 | 7583 | if (TARGET_SOM || !TARGET_GAS) |
7584 | { | |
7585 | /* The HP assembler can generate relocations for the | |
7586 | difference of two symbols. GAS can do this for a | |
7587 | millicode symbol but not an arbitrary external | |
7588 | symbol when generating SOM output. */ | |
7589 | xoperands[1] = gen_label_rtx (); | |
c5559ed4 | 7590 | targetm.asm_out.internal_label (asm_out_file, "L", |
ece88821 | 7591 | CODE_LABEL_NUMBER (xoperands[1])); |
7592 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
7593 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
7594 | } | |
7595 | else | |
7596 | { | |
ece88821 | 7597 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands); |
7598 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1", | |
7599 | xoperands); | |
7600 | } | |
c7a4e712 | 7601 | |
ece88821 | 7602 | /* Jump to our target address in %r1. */ |
7603 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 7604 | } |
c7a4e712 | 7605 | } |
7606 | ||
ece88821 | 7607 | if (seq_length == 0) |
7608 | output_asm_insn ("nop", xoperands); | |
c7a4e712 | 7609 | |
ece88821 | 7610 | /* We are done if there isn't a jump in the delay slot. */ |
7611 | if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7612 | return ""; | |
c7a4e712 | 7613 | |
ece88821 | 7614 | /* This call has an unconditional jump in its delay slot. */ |
7615 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
c7a4e712 | 7616 | |
ece88821 | 7617 | /* See if the return address can be adjusted. Use the containing |
7618 | sequence insn's address. */ | |
cd0dfcc5 | 7619 | if (INSN_ADDRESSES_SET_P ()) |
c7a4e712 | 7620 | { |
cd0dfcc5 | 7621 | seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); |
7622 | distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7623 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7624 | ||
7625 | if (VAL_14_BITS_P (distance)) | |
7626 | { | |
7627 | xoperands[1] = gen_label_rtx (); | |
7628 | output_asm_insn ("ldo %0-%1(%2),%2", xoperands); | |
c5559ed4 | 7629 | targetm.asm_out.internal_label (asm_out_file, "L", |
7630 | CODE_LABEL_NUMBER (xoperands[1])); | |
cd0dfcc5 | 7631 | } |
7632 | else | |
7633 | /* ??? This branch may not reach its target. */ | |
7634 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 7635 | } |
ece88821 | 7636 | else |
7637 | /* ??? This branch may not reach its target. */ | |
7638 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 7639 | |
7640 | /* Delete the jump. */ | |
ad4583d9 | 7641 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 7642 | |
c7a4e712 | 7643 | return ""; |
7644 | } | |
7645 | ||
cd0dfcc5 | 7646 | /* Return the attribute length of the call instruction INSN. The SIBCALL |
7647 | flag indicates whether INSN is a regular call or a sibling call. The | |
faf3f8c1 | 7648 | length returned must be longer than the code actually generated by |
e202682d | 7649 | pa_output_call. Since branch shortening is done before delay branch |
faf3f8c1 | 7650 | sequencing, there is no way to determine whether or not the delay |
7651 | slot will be filled during branch shortening. Even when the delay | |
7652 | slot is filled, we may have to add a nop if the delay slot contains | |
7653 | a branch that can't reach its target. Thus, we always have to include | |
7654 | the delay slot in the length estimate. This used to be done in | |
7655 | pa_adjust_insn_length but we do it here now as some sequences always | |
7656 | fill the delay slot and we can save four bytes in the estimate for | |
7657 | these sequences. */ | |
ece88821 | 7658 | |
7659 | int | |
e202682d | 7660 | pa_attr_length_call (rtx insn, int sibcall) |
ece88821 | 7661 | { |
faf3f8c1 | 7662 | int local_call; |
f7bb6501 | 7663 | rtx call, call_dest; |
faf3f8c1 | 7664 | tree call_decl; |
7665 | int length = 0; | |
7666 | rtx pat = PATTERN (insn); | |
cd0dfcc5 | 7667 | unsigned long distance = -1; |
ece88821 | 7668 | |
f7bb6501 | 7669 | gcc_assert (GET_CODE (insn) == CALL_INSN); |
7670 | ||
cd0dfcc5 | 7671 | if (INSN_ADDRESSES_SET_P ()) |
7672 | { | |
faf3f8c1 | 7673 | unsigned long total; |
7674 | ||
7675 | total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; | |
2247cc5f | 7676 | distance = (total + insn_current_reference_address (insn)); |
7677 | if (distance < total) | |
cd0dfcc5 | 7678 | distance = -1; |
7679 | } | |
ece88821 | 7680 | |
f7bb6501 | 7681 | gcc_assert (GET_CODE (pat) == PARALLEL); |
ece88821 | 7682 | |
f7bb6501 | 7683 | /* Get the call rtx. */ |
7684 | call = XVECEXP (pat, 0, 0); | |
7685 | if (GET_CODE (call) == SET) | |
7686 | call = SET_SRC (call); | |
7687 | ||
7688 | gcc_assert (GET_CODE (call) == CALL); | |
7689 | ||
7690 | /* Determine if this is a local call. */ | |
7691 | call_dest = XEXP (XEXP (call, 0), 0); | |
faf3f8c1 | 7692 | call_decl = SYMBOL_REF_DECL (call_dest); |
c5559ed4 | 7693 | local_call = call_decl && targetm.binds_local_p (call_decl); |
ece88821 | 7694 | |
faf3f8c1 | 7695 | /* pc-relative branch. */ |
7696 | if (!TARGET_LONG_CALLS | |
7697 | && ((TARGET_PA_20 && !sibcall && distance < 7600000) | |
4f12c67a | 7698 | || distance < MAX_PCREL17F_OFFSET)) |
faf3f8c1 | 7699 | length += 8; |
ece88821 | 7700 | |
faf3f8c1 | 7701 | /* 64-bit plabel sequence. */ |
7702 | else if (TARGET_64BIT && !local_call) | |
7703 | length += sibcall ? 28 : 24; | |
ece88821 | 7704 | |
faf3f8c1 | 7705 | /* non-pic long absolute branch sequence. */ |
7706 | else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) | |
7707 | length += 12; | |
ece88821 | 7708 | |
faf3f8c1 | 7709 | /* long pc-relative branch sequence. */ |
feb01ed5 | 7710 | else if (TARGET_LONG_PIC_SDIFF_CALL |
ea24f9f4 | 7711 | || (TARGET_GAS && !TARGET_SOM |
7712 | && (TARGET_LONG_PIC_PCREL_CALL || local_call))) | |
faf3f8c1 | 7713 | { |
7714 | length += 20; | |
ece88821 | 7715 | |
226f6453 | 7716 | if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS && (!local_call || flag_pic)) |
faf3f8c1 | 7717 | length += 8; |
7718 | } | |
8a05c3c2 | 7719 | |
faf3f8c1 | 7720 | /* 32-bit plabel sequence. */ |
7721 | else | |
7722 | { | |
7723 | length += 32; | |
ece88821 | 7724 | |
faf3f8c1 | 7725 | if (TARGET_SOM) |
7726 | length += length_fp_args (insn); | |
7727 | ||
7728 | if (flag_pic) | |
7729 | length += 4; | |
ee376abe | 7730 | |
faf3f8c1 | 7731 | if (!TARGET_PA_20) |
7732 | { | |
ece88821 | 7733 | if (!sibcall) |
7734 | length += 8; | |
7735 | ||
226f6453 | 7736 | if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic)) |
faf3f8c1 | 7737 | length += 8; |
ece88821 | 7738 | } |
7739 | } | |
faf3f8c1 | 7740 | |
7741 | return length; | |
ece88821 | 7742 | } |
7743 | ||
7744 | /* INSN is a function call. It may have an unconditional jump | |
c7a4e712 | 7745 | in its delay slot. |
7746 | ||
7747 | CALL_DEST is the routine we are calling. */ | |
7748 | ||
611a88e1 | 7749 | const char * |
e202682d | 7750 | pa_output_call (rtx insn, rtx call_dest, int sibcall) |
c7a4e712 | 7751 | { |
ece88821 | 7752 | int delay_insn_deleted = 0; |
7753 | int delay_slot_filled = 0; | |
b70ea764 | 7754 | int seq_length = dbr_sequence_length (); |
2247cc5f | 7755 | tree call_decl = SYMBOL_REF_DECL (call_dest); |
c5559ed4 | 7756 | int local_call = call_decl && targetm.binds_local_p (call_decl); |
ece88821 | 7757 | rtx xoperands[2]; |
7758 | ||
7759 | xoperands[0] = call_dest; | |
c7a4e712 | 7760 | |
ece88821 | 7761 | /* Handle the common case where we're sure that the branch will reach |
2247cc5f | 7762 | the beginning of the "$CODE$" subspace. This is the beginning of |
7763 | the current function if we are in a named section. */ | |
e202682d | 7764 | if (!TARGET_LONG_CALLS && pa_attr_length_call (insn, sibcall) == 8) |
d6686e21 | 7765 | { |
5e3c5739 | 7766 | xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2); |
ece88821 | 7767 | output_asm_insn ("{bl|b,l} %0,%1", xoperands); |
06ddb6f8 | 7768 | } |
ece88821 | 7769 | else |
06ddb6f8 | 7770 | { |
2247cc5f | 7771 | if (TARGET_64BIT && !local_call) |
3683f840 | 7772 | { |
ece88821 | 7773 | /* ??? As far as I can tell, the HP linker doesn't support the |
7774 | long pc-relative sequence described in the 64-bit runtime | |
7775 | architecture. So, we use a slightly longer indirect call. */ | |
e202682d | 7776 | xoperands[0] = pa_get_deferred_plabel (call_dest); |
ece88821 | 7777 | xoperands[1] = gen_label_rtx (); |
7778 | ||
7779 | /* If this isn't a sibcall, we put the load of %r27 into the | |
7780 | delay slot. We can't do this in a sibcall as we don't | |
7781 | have a second call-clobbered scratch register available. */ | |
7782 | if (seq_length != 0 | |
7783 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7784 | && !sibcall) | |
7785 | { | |
7786 | final_scan_insn (NEXT_INSN (insn), asm_out_file, | |
4bf029b0 | 7787 | optimize, 0, NULL); |
ece88821 | 7788 | |
7789 | /* Now delete the delay insn. */ | |
ad4583d9 | 7790 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 7791 | delay_insn_deleted = 1; |
7792 | } | |
06ddb6f8 | 7793 | |
ece88821 | 7794 | output_asm_insn ("addil LT'%0,%%r27", xoperands); |
7795 | output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands); | |
7796 | output_asm_insn ("ldd 0(%%r1),%%r1", xoperands); | |
06ddb6f8 | 7797 | |
ece88821 | 7798 | if (sibcall) |
06ddb6f8 | 7799 | { |
ece88821 | 7800 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); |
7801 | output_asm_insn ("ldd 16(%%r1),%%r1", xoperands); | |
7802 | output_asm_insn ("bve (%%r1)", xoperands); | |
7803 | } | |
7804 | else | |
7805 | { | |
7806 | output_asm_insn ("ldd 16(%%r1),%%r2", xoperands); | |
7807 | output_asm_insn ("bve,l (%%r2),%%r2", xoperands); | |
7808 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); | |
7809 | delay_slot_filled = 1; | |
06ddb6f8 | 7810 | } |
7811 | } | |
ece88821 | 7812 | else |
e3f53689 | 7813 | { |
ece88821 | 7814 | int indirect_call = 0; |
7815 | ||
7816 | /* Emit a long call. There are several different sequences | |
7817 | of increasing length and complexity. In most cases, | |
7818 | they don't allow an instruction in the delay slot. */ | |
2247cc5f | 7819 | if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
feb01ed5 | 7820 | && !TARGET_LONG_PIC_SDIFF_CALL |
ea24f9f4 | 7821 | && !(TARGET_GAS && !TARGET_SOM |
7822 | && (TARGET_LONG_PIC_PCREL_CALL || local_call)) | |
2247cc5f | 7823 | && !TARGET_64BIT) |
ece88821 | 7824 | indirect_call = 1; |
7825 | ||
7826 | if (seq_length != 0 | |
7827 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7828 | && !sibcall | |
c4b36071 | 7829 | && (!TARGET_PA_20 |
7830 | || indirect_call | |
7831 | || ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic))) | |
5cc6b2bc | 7832 | { |
ece88821 | 7833 | /* A non-jump insn in the delay slot. By definition we can |
7834 | emit this insn before the call (and in fact before argument | |
7835 | relocating. */ | |
4bf029b0 | 7836 | final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, |
fbf5169c | 7837 | NULL); |
ece88821 | 7838 | |
7839 | /* Now delete the delay insn. */ | |
ad4583d9 | 7840 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 7841 | delay_insn_deleted = 1; |
5cc6b2bc | 7842 | } |
e3f53689 | 7843 | |
2247cc5f | 7844 | if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
5cc6b2bc | 7845 | { |
ece88821 | 7846 | /* This is the best sequence for making long calls in |
7847 | non-pic code. Unfortunately, GNU ld doesn't provide | |
7848 | the stub needed for external calls, and GAS's support | |
2247cc5f | 7849 | for this with the SOM linker is buggy. It is safe |
7850 | to use this for local calls. */ | |
ece88821 | 7851 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
7852 | if (sibcall) | |
7853 | output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands); | |
7854 | else | |
7855 | { | |
7856 | if (TARGET_PA_20) | |
7857 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", | |
7858 | xoperands); | |
7859 | else | |
7860 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); | |
c7a4e712 | 7861 | |
ece88821 | 7862 | output_asm_insn ("copy %%r31,%%r2", xoperands); |
7863 | delay_slot_filled = 1; | |
7864 | } | |
7865 | } | |
7866 | else | |
7867 | { | |
feb01ed5 | 7868 | if (TARGET_LONG_PIC_SDIFF_CALL) |
b70ea764 | 7869 | { |
ece88821 | 7870 | /* The HP assembler and linker can handle relocations |
feb01ed5 | 7871 | for the difference of two symbols. The HP assembler |
7872 | recognizes the sequence as a pc-relative call and | |
7873 | the linker provides stubs when needed. */ | |
ece88821 | 7874 | xoperands[1] = gen_label_rtx (); |
7875 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7876 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
c5559ed4 | 7877 | targetm.asm_out.internal_label (asm_out_file, "L", |
b70ea764 | 7878 | CODE_LABEL_NUMBER (xoperands[1])); |
ece88821 | 7879 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); |
7880 | } | |
ea24f9f4 | 7881 | else if (TARGET_GAS && !TARGET_SOM |
7882 | && (TARGET_LONG_PIC_PCREL_CALL || local_call)) | |
b70ea764 | 7883 | { |
ece88821 | 7884 | /* GAS currently can't generate the relocations that |
7885 | are needed for the SOM linker under HP-UX using this | |
7886 | sequence. The GNU linker doesn't generate the stubs | |
7887 | that are needed for external calls on TARGET_ELF32 | |
7888 | with this sequence. For now, we have to use a | |
7889 | longer plabel sequence when using GAS. */ | |
7890 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7891 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", | |
b70ea764 | 7892 | xoperands); |
ece88821 | 7893 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", |
b70ea764 | 7894 | xoperands); |
7895 | } | |
5e3c5739 | 7896 | else |
7897 | { | |
ece88821 | 7898 | /* Emit a long plabel-based call sequence. This is |
7899 | essentially an inline implementation of $$dyncall. | |
7900 | We don't actually try to call $$dyncall as this is | |
7901 | as difficult as calling the function itself. */ | |
e202682d | 7902 | xoperands[0] = pa_get_deferred_plabel (call_dest); |
ece88821 | 7903 | xoperands[1] = gen_label_rtx (); |
7904 | ||
7905 | /* Since the call is indirect, FP arguments in registers | |
7906 | need to be copied to the general registers. Then, the | |
7907 | argument relocation stub will copy them back. */ | |
7908 | if (TARGET_SOM) | |
7909 | copy_fp_args (insn); | |
7910 | ||
7911 | if (flag_pic) | |
7912 | { | |
7913 | output_asm_insn ("addil LT'%0,%%r19", xoperands); | |
7914 | output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands); | |
7915 | output_asm_insn ("ldw 0(%%r1),%%r1", xoperands); | |
7916 | } | |
7917 | else | |
7918 | { | |
7919 | output_asm_insn ("addil LR'%0-$global$,%%r27", | |
7920 | xoperands); | |
7921 | output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1", | |
7922 | xoperands); | |
7923 | } | |
06ddb6f8 | 7924 | |
ece88821 | 7925 | output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands); |
7926 | output_asm_insn ("depi 0,31,2,%%r1", xoperands); | |
7927 | output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands); | |
7928 | output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands); | |
c7a4e712 | 7929 | |
ece88821 | 7930 | if (!sibcall && !TARGET_PA_20) |
7931 | { | |
7932 | output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands); | |
226f6453 | 7933 | if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic)) |
ee376abe | 7934 | output_asm_insn ("addi 8,%%r2,%%r2", xoperands); |
7935 | else | |
7936 | output_asm_insn ("addi 16,%%r2,%%r2", xoperands); | |
ece88821 | 7937 | } |
7938 | } | |
c7a4e712 | 7939 | |
ece88821 | 7940 | if (TARGET_PA_20) |
5e3c5739 | 7941 | { |
ece88821 | 7942 | if (sibcall) |
7943 | output_asm_insn ("bve (%%r1)", xoperands); | |
7944 | else | |
7945 | { | |
7946 | if (indirect_call) | |
7947 | { | |
7948 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7949 | output_asm_insn ("stw %%r2,-24(%%sp)", xoperands); | |
7950 | delay_slot_filled = 1; | |
7951 | } | |
7952 | else | |
7953 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7954 | } | |
5e3c5739 | 7955 | } |
7956 | else | |
7957 | { | |
226f6453 | 7958 | if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic)) |
ee376abe | 7959 | output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0", |
7960 | xoperands); | |
06ddb6f8 | 7961 | |
ece88821 | 7962 | if (sibcall) |
ee376abe | 7963 | { |
226f6453 | 7964 | if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic)) |
ee376abe | 7965 | output_asm_insn ("be 0(%%sr4,%%r1)", xoperands); |
7966 | else | |
7967 | output_asm_insn ("be 0(%%sr0,%%r1)", xoperands); | |
7968 | } | |
ece88821 | 7969 | else |
7970 | { | |
226f6453 | 7971 | if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic)) |
ee376abe | 7972 | output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands); |
7973 | else | |
7974 | output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands); | |
06ddb6f8 | 7975 | |
ece88821 | 7976 | if (indirect_call) |
7977 | output_asm_insn ("stw %%r31,-24(%%sp)", xoperands); | |
7978 | else | |
7979 | output_asm_insn ("copy %%r31,%%r2", xoperands); | |
7980 | delay_slot_filled = 1; | |
7981 | } | |
7982 | } | |
7983 | } | |
06ddb6f8 | 7984 | } |
d6686e21 | 7985 | } |
6d36483b | 7986 | |
8a05c3c2 | 7987 | if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted)) |
ece88821 | 7988 | output_asm_insn ("nop", xoperands); |
d6686e21 | 7989 | |
ece88821 | 7990 | /* We are done if there isn't a jump in the delay slot. */ |
7991 | if (seq_length == 0 | |
7992 | || delay_insn_deleted | |
7993 | || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7994 | return ""; | |
d6686e21 | 7995 | |
ece88821 | 7996 | /* A sibcall should never have a branch in the delay slot. */ |
ecf2283d | 7997 | gcc_assert (!sibcall); |
d6686e21 | 7998 | |
ece88821 | 7999 | /* This call has an unconditional jump in its delay slot. */ |
8000 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
d6686e21 | 8001 | |
cd0dfcc5 | 8002 | if (!delay_slot_filled && INSN_ADDRESSES_SET_P ()) |
d6686e21 | 8003 | { |
ece88821 | 8004 | /* See if the return address can be adjusted. Use the containing |
1b448af3 | 8005 | sequence insn's address. This would break the regular call/return@ |
8006 | relationship assumed by the table based eh unwinder, so only do that | |
8007 | if the call is not possibly throwing. */ | |
ece88821 | 8008 | rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); |
8009 | int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
8010 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
8011 | ||
1b448af3 | 8012 | if (VAL_14_BITS_P (distance) |
8013 | && !(can_throw_internal (insn) || can_throw_external (insn))) | |
ece88821 | 8014 | { |
8015 | xoperands[1] = gen_label_rtx (); | |
8016 | output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands); | |
c5559ed4 | 8017 | targetm.asm_out.internal_label (asm_out_file, "L", |
8018 | CODE_LABEL_NUMBER (xoperands[1])); | |
ece88821 | 8019 | } |
8020 | else | |
ece88821 | 8021 | output_asm_insn ("nop\n\tb,n %0", xoperands); |
d6686e21 | 8022 | } |
ece88821 | 8023 | else |
ece88821 | 8024 | output_asm_insn ("b,n %0", xoperands); |
d6686e21 | 8025 | |
8026 | /* Delete the jump. */ | |
ad4583d9 | 8027 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 8028 | |
d6686e21 | 8029 | return ""; |
8030 | } | |
8031 | ||
cd0dfcc5 | 8032 | /* Return the attribute length of the indirect call instruction INSN. |
8033 | The length must match the code generated by output_indirect call. | |
8034 | The returned length includes the delay slot. Currently, the delay | |
8035 | slot of an indirect call sequence is not exposed and it is used by | |
8036 | the sequence itself. */ | |
8037 | ||
8038 | int | |
e202682d | 8039 | pa_attr_length_indirect_call (rtx insn) |
cd0dfcc5 | 8040 | { |
8041 | unsigned long distance = -1; | |
8a05c3c2 | 8042 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
cd0dfcc5 | 8043 | |
8044 | if (INSN_ADDRESSES_SET_P ()) | |
8045 | { | |
2247cc5f | 8046 | distance = (total + insn_current_reference_address (insn)); |
8047 | if (distance < total) | |
cd0dfcc5 | 8048 | distance = -1; |
8049 | } | |
8050 | ||
8051 | if (TARGET_64BIT) | |
8052 | return 12; | |
8053 | ||
8054 | if (TARGET_FAST_INDIRECT_CALLS | |
8055 | || (!TARGET_PORTABLE_RUNTIME | |
5925d47a | 8056 | && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000) |
4f12c67a | 8057 | || distance < MAX_PCREL17F_OFFSET))) |
cd0dfcc5 | 8058 | return 8; |
8059 | ||
8060 | if (flag_pic) | |
8061 | return 24; | |
8062 | ||
8063 | if (TARGET_PORTABLE_RUNTIME) | |
8064 | return 20; | |
8065 | ||
8066 | /* Out of reach, can use ble. */ | |
8067 | return 12; | |
8068 | } | |
8069 | ||
8070 | const char * | |
e202682d | 8071 | pa_output_indirect_call (rtx insn, rtx call_dest) |
cd0dfcc5 | 8072 | { |
8073 | rtx xoperands[1]; | |
8074 | ||
8075 | if (TARGET_64BIT) | |
8076 | { | |
8077 | xoperands[0] = call_dest; | |
8078 | output_asm_insn ("ldd 16(%0),%%r2", xoperands); | |
8079 | output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands); | |
8080 | return ""; | |
8081 | } | |
8082 | ||
8083 | /* First the special case for kernels, level 0 systems, etc. */ | |
8084 | if (TARGET_FAST_INDIRECT_CALLS) | |
8085 | return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2"; | |
8086 | ||
8087 | /* Now the normal case -- we can reach $$dyncall directly or | |
8088 | we're sure that we can get there via a long-branch stub. | |
8089 | ||
8090 | No need to check target flags as the length uniquely identifies | |
8091 | the remaining cases. */ | |
e202682d | 8092 | if (pa_attr_length_indirect_call (insn) == 8) |
f707acb9 | 8093 | { |
5925d47a | 8094 | /* The HP linker sometimes substitutes a BLE for BL/B,L calls to |
8095 | $$dyncall. Since BLE uses %r31 as the link register, the 22-bit | |
8096 | variant of the B,L instruction can't be used on the SOM target. */ | |
8097 | if (TARGET_PA_20 && !TARGET_SOM) | |
f707acb9 | 8098 | return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31"; |
8099 | else | |
8100 | return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2"; | |
8101 | } | |
cd0dfcc5 | 8102 | |
8103 | /* Long millicode call, but we are not generating PIC or portable runtime | |
8104 | code. */ | |
e202682d | 8105 | if (pa_attr_length_indirect_call (insn) == 12) |
cd0dfcc5 | 8106 | return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2"; |
8107 | ||
8108 | /* Long millicode call for portable runtime. */ | |
e202682d | 8109 | if (pa_attr_length_indirect_call (insn) == 20) |
cd0dfcc5 | 8110 | return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop"; |
8111 | ||
8112 | /* We need a long PIC call to $$dyncall. */ | |
8113 | xoperands[0] = NULL_RTX; | |
8114 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
8115 | if (TARGET_SOM || !TARGET_GAS) | |
8116 | { | |
8117 | xoperands[0] = gen_label_rtx (); | |
8118 | output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands); | |
c5559ed4 | 8119 | targetm.asm_out.internal_label (asm_out_file, "L", |
8120 | CODE_LABEL_NUMBER (xoperands[0])); | |
cd0dfcc5 | 8121 | output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands); |
8122 | } | |
8123 | else | |
8124 | { | |
8125 | output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands); | |
8126 | output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1", | |
8127 | xoperands); | |
8128 | } | |
8129 | output_asm_insn ("blr %%r0,%%r2", xoperands); | |
8130 | output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands); | |
8131 | return ""; | |
8132 | } | |
8133 | ||
d6f01525 | 8134 | /* In HPUX 8.0's shared library scheme, special relocations are needed |
6d36483b | 8135 | for function labels if they might be passed to a function |
d6f01525 | 8136 | in a shared library (because shared libraries don't live in code |
44acf429 | 8137 | space), and special magic is needed to construct their address. */ |
d6f01525 | 8138 | |
8139 | void | |
e202682d | 8140 | pa_encode_label (rtx sym) |
d6f01525 | 8141 | { |
611a88e1 | 8142 | const char *str = XSTR (sym, 0); |
cccfb31e | 8143 | int len = strlen (str) + 1; |
8144 | char *newstr, *p; | |
d6f01525 | 8145 | |
225ab426 | 8146 | p = newstr = XALLOCAVEC (char, len + 1); |
cccfb31e | 8147 | *p++ = '@'; |
8148 | strcpy (p, str); | |
74d80a9a | 8149 | |
ea52c577 | 8150 | XSTR (sym, 0) = ggc_alloc_string (newstr, len); |
d6f01525 | 8151 | } |
6d36483b | 8152 | |
7811991d | 8153 | static void |
5c1d8983 | 8154 | pa_encode_section_info (tree decl, rtx rtl, int first) |
7811991d | 8155 | { |
54d7a10c | 8156 | int old_referenced = 0; |
8157 | ||
8158 | if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF) | |
8159 | old_referenced | |
8160 | = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED; | |
8161 | ||
716b2c5a | 8162 | default_encode_section_info (decl, rtl, first); |
8163 | ||
7811991d | 8164 | if (first && TEXT_SPACE_P (decl)) |
8165 | { | |
7811991d | 8166 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
8167 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
e202682d | 8168 | pa_encode_label (XEXP (rtl, 0)); |
7811991d | 8169 | } |
54d7a10c | 8170 | else if (old_referenced) |
8171 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced; | |
7811991d | 8172 | } |
8173 | ||
7b4a38a6 | 8174 | /* This is sort of inverse to pa_encode_section_info. */ |
8175 | ||
8176 | static const char * | |
5c1d8983 | 8177 | pa_strip_name_encoding (const char *str) |
7b4a38a6 | 8178 | { |
c0264367 | 8179 | str += (*str == '@'); |
8180 | str += (*str == '*'); | |
8181 | return str; | |
7b4a38a6 | 8182 | } |
8183 | ||
166bf021 | 8184 | /* Returns 1 if OP is a function label involved in a simple addition |
8185 | with a constant. Used to keep certain patterns from matching | |
8186 | during instruction combination. */ | |
8187 | int | |
e202682d | 8188 | pa_is_function_label_plus_const (rtx op) |
166bf021 | 8189 | { |
8190 | /* Strip off any CONST. */ | |
8191 | if (GET_CODE (op) == CONST) | |
8192 | op = XEXP (op, 0); | |
8193 | ||
8194 | return (GET_CODE (op) == PLUS | |
39ec41d4 | 8195 | && function_label_operand (XEXP (op, 0), VOIDmode) |
166bf021 | 8196 | && GET_CODE (XEXP (op, 1)) == CONST_INT); |
8197 | } | |
8198 | ||
f1752b7e | 8199 | /* Output assembly code for a thunk to FUNCTION. */ |
8200 | ||
6988553d | 8201 | static void |
5c1d8983 | 8202 | pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, |
8203 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
8204 | tree function) | |
f1752b7e | 8205 | { |
e678758c | 8206 | static unsigned int current_thunk_number; |
2247cc5f | 8207 | int val_14 = VAL_14_BITS_P (delta); |
21a47bc9 | 8208 | unsigned int old_last_address = last_address, nbytes = 0; |
f1752b7e | 8209 | char label[16]; |
e678758c | 8210 | rtx xoperands[4]; |
2247cc5f | 8211 | |
e678758c | 8212 | xoperands[0] = XEXP (DECL_RTL (function), 0); |
8213 | xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0); | |
8214 | xoperands[2] = GEN_INT (delta); | |
2247cc5f | 8215 | |
e678758c | 8216 | ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0)); |
8217 | fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); | |
2247cc5f | 8218 | |
8219 | /* Output the thunk. We know that the function is in the same | |
8220 | translation unit (i.e., the same space) as the thunk, and that | |
8221 | thunks are output after their method. Thus, we don't need an | |
8222 | external branch to reach the function. With SOM and GAS, | |
8223 | functions and thunks are effectively in different sections. | |
8224 | Thus, we can always use a IA-relative branch and the linker | |
8225 | will add a long branch stub if necessary. | |
8226 | ||
8227 | However, we have to be careful when generating PIC code on the | |
8228 | SOM port to ensure that the sequence does not transfer to an | |
8229 | import stub for the target function as this could clobber the | |
8230 | return value saved at SP-24. This would also apply to the | |
8231 | 32-bit linux port if the multi-space model is implemented. */ | |
8232 | if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
8233 | && !(flag_pic && TREE_PUBLIC (function)) | |
8234 | && (TARGET_GAS || last_address < 262132)) | |
8235 | || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
218e3e4e | 8236 | && ((targetm_common.have_named_sections |
2247cc5f | 8237 | && DECL_SECTION_NAME (thunk_fndecl) != NULL |
8238 | /* The GNU 64-bit linker has rather poor stub management. | |
8239 | So, we use a long branch from thunks that aren't in | |
8240 | the same section as the target function. */ | |
8241 | && ((!TARGET_64BIT | |
8242 | && (DECL_SECTION_NAME (thunk_fndecl) | |
8243 | != DECL_SECTION_NAME (function))) | |
8244 | || ((DECL_SECTION_NAME (thunk_fndecl) | |
8245 | == DECL_SECTION_NAME (function)) | |
8246 | && last_address < 262132))) | |
218e3e4e | 8247 | || (targetm_common.have_named_sections |
55e0e460 | 8248 | && DECL_SECTION_NAME (thunk_fndecl) == NULL |
8249 | && DECL_SECTION_NAME (function) == NULL | |
8250 | && last_address < 262132) | |
218e3e4e | 8251 | || (!targetm_common.have_named_sections |
8252 | && last_address < 262132)))) | |
2247cc5f | 8253 | { |
e678758c | 8254 | if (!val_14) |
8255 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8256 | ||
8257 | output_asm_insn ("b %0", xoperands); | |
8258 | ||
2247cc5f | 8259 | if (val_14) |
8260 | { | |
e678758c | 8261 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8262 | nbytes += 8; |
8263 | } | |
8264 | else | |
8265 | { | |
e678758c | 8266 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8267 | nbytes += 12; |
8268 | } | |
8269 | } | |
8270 | else if (TARGET_64BIT) | |
8271 | { | |
8272 | /* We only have one call-clobbered scratch register, so we can't | |
8273 | make use of the delay slot if delta doesn't fit in 14 bits. */ | |
8274 | if (!val_14) | |
e678758c | 8275 | { |
8276 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8277 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); | |
8278 | } | |
2247cc5f | 8279 | |
e678758c | 8280 | output_asm_insn ("b,l .+8,%%r1", xoperands); |
2247cc5f | 8281 | |
8282 | if (TARGET_GAS) | |
8283 | { | |
e678758c | 8284 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
8285 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
2247cc5f | 8286 | } |
8287 | else | |
8288 | { | |
e678758c | 8289 | xoperands[3] = GEN_INT (val_14 ? 8 : 16); |
8290 | output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands); | |
2247cc5f | 8291 | } |
8292 | ||
8293 | if (val_14) | |
8294 | { | |
e678758c | 8295 | output_asm_insn ("bv %%r0(%%r1)", xoperands); |
8296 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); | |
2247cc5f | 8297 | nbytes += 20; |
8298 | } | |
8299 | else | |
8300 | { | |
e678758c | 8301 | output_asm_insn ("bv,n %%r0(%%r1)", xoperands); |
2247cc5f | 8302 | nbytes += 24; |
8303 | } | |
8304 | } | |
8305 | else if (TARGET_PORTABLE_RUNTIME) | |
8306 | { | |
e678758c | 8307 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
8308 | output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands); | |
8309 | ||
8310 | if (!val_14) | |
8311 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8312 | ||
8313 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
2247cc5f | 8314 | |
8315 | if (val_14) | |
8316 | { | |
e678758c | 8317 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8318 | nbytes += 16; |
8319 | } | |
8320 | else | |
8321 | { | |
e678758c | 8322 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8323 | nbytes += 20; |
8324 | } | |
8325 | } | |
8326 | else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
8327 | { | |
8328 | /* The function is accessible from outside this module. The only | |
8329 | way to avoid an import stub between the thunk and function is to | |
8330 | call the function directly with an indirect sequence similar to | |
8331 | that used by $$dyncall. This is possible because $$dyncall acts | |
8332 | as the import stub in an indirect call. */ | |
2247cc5f | 8333 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number); |
e678758c | 8334 | xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label); |
8335 | output_asm_insn ("addil LT'%3,%%r19", xoperands); | |
8336 | output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands); | |
8337 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
8338 | output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands); | |
8339 | output_asm_insn ("depi 0,31,2,%%r22", xoperands); | |
8340 | output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands); | |
8341 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
8342 | ||
2247cc5f | 8343 | if (!val_14) |
8344 | { | |
e678758c | 8345 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
2247cc5f | 8346 | nbytes += 4; |
8347 | } | |
e678758c | 8348 | |
2247cc5f | 8349 | if (TARGET_PA_20) |
8350 | { | |
e678758c | 8351 | output_asm_insn ("bve (%%r22)", xoperands); |
8352 | nbytes += 36; | |
8353 | } | |
8354 | else if (TARGET_NO_SPACE_REGS) | |
8355 | { | |
8356 | output_asm_insn ("be 0(%%sr4,%%r22)", xoperands); | |
2247cc5f | 8357 | nbytes += 36; |
8358 | } | |
8359 | else | |
f1752b7e | 8360 | { |
e678758c | 8361 | output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands); |
8362 | output_asm_insn ("mtsp %%r21,%%sr0", xoperands); | |
8363 | output_asm_insn ("be 0(%%sr0,%%r22)", xoperands); | |
8364 | nbytes += 44; | |
2247cc5f | 8365 | } |
8366 | ||
8367 | if (val_14) | |
e678758c | 8368 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8369 | else |
e678758c | 8370 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8371 | } |
8372 | else if (flag_pic) | |
8373 | { | |
e678758c | 8374 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
2247cc5f | 8375 | |
8376 | if (TARGET_SOM || !TARGET_GAS) | |
8377 | { | |
e678758c | 8378 | output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands); |
8379 | output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands); | |
2247cc5f | 8380 | } |
8381 | else | |
8382 | { | |
e678758c | 8383 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
8384 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands); | |
2247cc5f | 8385 | } |
8386 | ||
e678758c | 8387 | if (!val_14) |
8388 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8389 | ||
8390 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
8391 | ||
2247cc5f | 8392 | if (val_14) |
8393 | { | |
e678758c | 8394 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8395 | nbytes += 20; |
f1752b7e | 8396 | } |
8397 | else | |
2247cc5f | 8398 | { |
e678758c | 8399 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8400 | nbytes += 24; |
8401 | } | |
f1752b7e | 8402 | } |
8403 | else | |
8404 | { | |
2247cc5f | 8405 | if (!val_14) |
e678758c | 8406 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
2247cc5f | 8407 | |
e678758c | 8408 | output_asm_insn ("ldil L'%0,%%r22", xoperands); |
8409 | output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands); | |
2247cc5f | 8410 | |
8411 | if (val_14) | |
f1752b7e | 8412 | { |
e678758c | 8413 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8414 | nbytes += 12; |
f1752b7e | 8415 | } |
8416 | else | |
2247cc5f | 8417 | { |
e678758c | 8418 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8419 | nbytes += 16; |
8420 | } | |
f1752b7e | 8421 | } |
2247cc5f | 8422 | |
f1752b7e | 8423 | fprintf (file, "\t.EXIT\n\t.PROCEND\n"); |
2247cc5f | 8424 | |
78962d38 | 8425 | if (TARGET_SOM && TARGET_GAS) |
8426 | { | |
8427 | /* We done with this subspace except possibly for some additional | |
8428 | debug information. Forget that we are in this subspace to ensure | |
8429 | that the next function is output in its own subspace. */ | |
8430 | in_section = NULL; | |
8431 | cfun->machine->in_nsubspa = 2; | |
8432 | } | |
8433 | ||
2247cc5f | 8434 | if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) |
f1752b7e | 8435 | { |
2f14b1f9 | 8436 | switch_to_section (data_section); |
e678758c | 8437 | output_asm_insn (".align 4", xoperands); |
2247cc5f | 8438 | ASM_OUTPUT_LABEL (file, label); |
e678758c | 8439 | output_asm_insn (".word P'%0", xoperands); |
f1752b7e | 8440 | } |
2247cc5f | 8441 | |
f1752b7e | 8442 | current_thunk_number++; |
2247cc5f | 8443 | nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) |
8444 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
8445 | last_address += nbytes; | |
21a47bc9 | 8446 | if (old_last_address > last_address) |
8447 | last_address = UINT_MAX; | |
2247cc5f | 8448 | update_total_code_bytes (nbytes); |
f1752b7e | 8449 | } |
8450 | ||
805e22b2 | 8451 | /* Only direct calls to static functions are allowed to be sibling (tail) |
8452 | call optimized. | |
8453 | ||
8454 | This restriction is necessary because some linker generated stubs will | |
8455 | store return pointers into rp' in some cases which might clobber a | |
8456 | live value already in rp'. | |
8457 | ||
8458 | In a sibcall the current function and the target function share stack | |
8459 | space. Thus if the path to the current function and the path to the | |
8460 | target function save a value in rp', they save the value into the | |
8461 | same stack slot, which has undesirable consequences. | |
8462 | ||
8463 | Because of the deferred binding nature of shared libraries any function | |
8464 | with external scope could be in a different load module and thus require | |
8465 | rp' to be saved when calling that function. So sibcall optimizations | |
8466 | can only be safe for static function. | |
8467 | ||
8468 | Note that GCC never needs return value relocations, so we don't have to | |
8469 | worry about static calls with return value relocations (which require | |
8470 | saving rp'). | |
8471 | ||
8472 | It is safe to perform a sibcall optimization when the target function | |
8473 | will never return. */ | |
8474 | static bool | |
5c1d8983 | 8475 | pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
805e22b2 | 8476 | { |
e11e9ae3 | 8477 | if (TARGET_PORTABLE_RUNTIME) |
8478 | return false; | |
8479 | ||
f62b73b6 | 8480 | /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in |
8481 | single subspace mode and the call is not indirect. As far as I know, | |
8482 | there is no operating system support for the multiple subspace mode. | |
8483 | It might be possible to support indirect calls if we didn't use | |
e202682d | 8484 | $$dyncall (see the indirect sequence generated in pa_output_call). */ |
f62b73b6 | 8485 | if (TARGET_ELF32) |
8486 | return (decl != NULL_TREE); | |
8487 | ||
8488 | /* Sibcalls are not ok because the arg pointer register is not a fixed | |
2cecd772 | 8489 | register. This prevents the sibcall optimization from occurring. In |
f62b73b6 | 8490 | addition, there are problems with stub placement using GNU ld. This |
8491 | is because a normal sibcall branch uses a 17-bit relocation while | |
8492 | a regular call branch uses a 22-bit relocation. As a result, more | |
8493 | care needs to be taken in the placement of long-branch stubs. */ | |
8494 | if (TARGET_64BIT) | |
8495 | return false; | |
8496 | ||
e11e9ae3 | 8497 | /* Sibcalls are only ok within a translation unit. */ |
8498 | return (decl && !TREE_PUBLIC (decl)); | |
805e22b2 | 8499 | } |
8500 | ||
280566a7 | 8501 | /* ??? Addition is not commutative on the PA due to the weird implicit |
8502 | space register selection rules for memory addresses. Therefore, we | |
8503 | don't consider a + b == b + a, as this might be inside a MEM. */ | |
8504 | static bool | |
a9f1838b | 8505 | pa_commutative_p (const_rtx x, int outer_code) |
280566a7 | 8506 | { |
8507 | return (COMMUTATIVE_P (x) | |
55e3fa6d | 8508 | && (TARGET_NO_SPACE_REGS |
8509 | || (outer_code != UNKNOWN && outer_code != MEM) | |
280566a7 | 8510 | || GET_CODE (x) != PLUS)); |
8511 | } | |
8512 | ||
37580c80 | 8513 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
8514 | use in fmpyadd instructions. */ | |
4ed6ee50 | 8515 | int |
e202682d | 8516 | pa_fmpyaddoperands (rtx *operands) |
4ed6ee50 | 8517 | { |
201f01e9 | 8518 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 8519 | |
ab449421 | 8520 | /* Must be a floating point mode. */ |
8521 | if (mode != SFmode && mode != DFmode) | |
8522 | return 0; | |
8523 | ||
4ed6ee50 | 8524 | /* All modes must be the same. */ |
201f01e9 | 8525 | if (! (mode == GET_MODE (operands[1]) |
8526 | && mode == GET_MODE (operands[2]) | |
8527 | && mode == GET_MODE (operands[3]) | |
8528 | && mode == GET_MODE (operands[4]) | |
8529 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 8530 | return 0; |
8531 | ||
ab449421 | 8532 | /* All operands must be registers. */ |
8533 | if (! (GET_CODE (operands[1]) == REG | |
8534 | && GET_CODE (operands[2]) == REG | |
8535 | && GET_CODE (operands[3]) == REG | |
8536 | && GET_CODE (operands[4]) == REG | |
8537 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 8538 | return 0; |
8539 | ||
37580c80 | 8540 | /* Only 2 real operands to the addition. One of the input operands must |
8541 | be the same as the output operand. */ | |
4ed6ee50 | 8542 | if (! rtx_equal_p (operands[3], operands[4]) |
8543 | && ! rtx_equal_p (operands[3], operands[5])) | |
8544 | return 0; | |
8545 | ||
33f88b1c | 8546 | /* Inout operand of add cannot conflict with any operands from multiply. */ |
4ed6ee50 | 8547 | if (rtx_equal_p (operands[3], operands[0]) |
8548 | || rtx_equal_p (operands[3], operands[1]) | |
8549 | || rtx_equal_p (operands[3], operands[2])) | |
8550 | return 0; | |
8551 | ||
33f88b1c | 8552 | /* multiply cannot feed into addition operands. */ |
4ed6ee50 | 8553 | if (rtx_equal_p (operands[4], operands[0]) |
8554 | || rtx_equal_p (operands[5], operands[0])) | |
8555 | return 0; | |
8556 | ||
ab449421 | 8557 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8558 | if (mode == SFmode | |
bac38c40 | 8559 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8560 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8561 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8562 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8563 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8564 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 8565 | return 0; |
8566 | ||
4ed6ee50 | 8567 | /* Passed. Operands are suitable for fmpyadd. */ |
8568 | return 1; | |
8569 | } | |
8570 | ||
de419443 | 8571 | #if !defined(USE_COLLECT2) |
8572 | static void | |
5c1d8983 | 8573 | pa_asm_out_constructor (rtx symbol, int priority) |
de419443 | 8574 | { |
8575 | if (!function_label_operand (symbol, VOIDmode)) | |
e202682d | 8576 | pa_encode_label (symbol); |
de419443 | 8577 | |
8578 | #ifdef CTORS_SECTION_ASM_OP | |
8579 | default_ctor_section_asm_out_constructor (symbol, priority); | |
8580 | #else | |
8581 | # ifdef TARGET_ASM_NAMED_SECTION | |
8582 | default_named_section_asm_out_constructor (symbol, priority); | |
8583 | # else | |
8584 | default_stabs_asm_out_constructor (symbol, priority); | |
8585 | # endif | |
8586 | #endif | |
8587 | } | |
8588 | ||
8589 | static void | |
5c1d8983 | 8590 | pa_asm_out_destructor (rtx symbol, int priority) |
de419443 | 8591 | { |
8592 | if (!function_label_operand (symbol, VOIDmode)) | |
e202682d | 8593 | pa_encode_label (symbol); |
de419443 | 8594 | |
8595 | #ifdef DTORS_SECTION_ASM_OP | |
8596 | default_dtor_section_asm_out_destructor (symbol, priority); | |
8597 | #else | |
8598 | # ifdef TARGET_ASM_NAMED_SECTION | |
8599 | default_named_section_asm_out_destructor (symbol, priority); | |
8600 | # else | |
8601 | default_stabs_asm_out_destructor (symbol, priority); | |
8602 | # endif | |
8603 | #endif | |
8604 | } | |
8605 | #endif | |
8606 | ||
ff59d376 | 8607 | /* This function places uninitialized global data in the bss section. |
8608 | The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this | |
8609 | function on the SOM port to prevent uninitialized global data from | |
8610 | being placed in the data section. */ | |
8611 | ||
8612 | void | |
8613 | pa_asm_output_aligned_bss (FILE *stream, | |
8614 | const char *name, | |
8615 | unsigned HOST_WIDE_INT size, | |
8616 | unsigned int align) | |
8617 | { | |
2f14b1f9 | 8618 | switch_to_section (bss_section); |
ff59d376 | 8619 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); |
8620 | ||
8621 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
8622 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); | |
8623 | #endif | |
8624 | ||
8625 | #ifdef ASM_OUTPUT_SIZE_DIRECTIVE | |
8626 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
8627 | #endif | |
8628 | ||
8629 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); | |
8630 | ASM_OUTPUT_LABEL (stream, name); | |
8631 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
8632 | } | |
8633 | ||
8634 | /* Both the HP and GNU assemblers under HP-UX provide a .comm directive | |
8635 | that doesn't allow the alignment of global common storage to be directly | |
8636 | specified. The SOM linker aligns common storage based on the rounded | |
8637 | value of the NUM_BYTES parameter in the .comm directive. It's not | |
8638 | possible to use the .align directive as it doesn't affect the alignment | |
8639 | of the label associated with a .comm directive. */ | |
8640 | ||
8641 | void | |
8642 | pa_asm_output_aligned_common (FILE *stream, | |
8643 | const char *name, | |
8644 | unsigned HOST_WIDE_INT size, | |
8645 | unsigned int align) | |
8646 | { | |
33cd7888 | 8647 | unsigned int max_common_align; |
8648 | ||
8649 | max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64); | |
8650 | if (align > max_common_align) | |
8651 | { | |
c3ceba8e | 8652 | warning (0, "alignment (%u) for %s exceeds maximum alignment " |
33cd7888 | 8653 | "for global common data. Using %u", |
8654 | align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT); | |
8655 | align = max_common_align; | |
8656 | } | |
8657 | ||
2f14b1f9 | 8658 | switch_to_section (bss_section); |
ff59d376 | 8659 | |
8660 | assemble_name (stream, name); | |
8661 | fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n", | |
8662 | MAX (size, align / BITS_PER_UNIT)); | |
8663 | } | |
8664 | ||
8665 | /* We can't use .comm for local common storage as the SOM linker effectively | |
8666 | treats the symbol as universal and uses the same storage for local symbols | |
8667 | with the same name in different object files. The .block directive | |
8668 | reserves an uninitialized block of storage. However, it's not common | |
8669 | storage. Fortunately, GCC never requests common storage with the same | |
8670 | name in any given translation unit. */ | |
8671 | ||
8672 | void | |
8673 | pa_asm_output_aligned_local (FILE *stream, | |
8674 | const char *name, | |
8675 | unsigned HOST_WIDE_INT size, | |
8676 | unsigned int align) | |
8677 | { | |
2f14b1f9 | 8678 | switch_to_section (bss_section); |
ff59d376 | 8679 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); |
8680 | ||
8681 | #ifdef LOCAL_ASM_OP | |
8682 | fprintf (stream, "%s", LOCAL_ASM_OP); | |
8683 | assemble_name (stream, name); | |
8684 | fprintf (stream, "\n"); | |
8685 | #endif | |
8686 | ||
8687 | ASM_OUTPUT_LABEL (stream, name); | |
8688 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
8689 | } | |
8690 | ||
37580c80 | 8691 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
8692 | use in fmpysub instructions. */ | |
4ed6ee50 | 8693 | int |
e202682d | 8694 | pa_fmpysuboperands (rtx *operands) |
4ed6ee50 | 8695 | { |
201f01e9 | 8696 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 8697 | |
ab449421 | 8698 | /* Must be a floating point mode. */ |
8699 | if (mode != SFmode && mode != DFmode) | |
8700 | return 0; | |
8701 | ||
4ed6ee50 | 8702 | /* All modes must be the same. */ |
201f01e9 | 8703 | if (! (mode == GET_MODE (operands[1]) |
8704 | && mode == GET_MODE (operands[2]) | |
8705 | && mode == GET_MODE (operands[3]) | |
8706 | && mode == GET_MODE (operands[4]) | |
8707 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 8708 | return 0; |
8709 | ||
ab449421 | 8710 | /* All operands must be registers. */ |
8711 | if (! (GET_CODE (operands[1]) == REG | |
8712 | && GET_CODE (operands[2]) == REG | |
8713 | && GET_CODE (operands[3]) == REG | |
8714 | && GET_CODE (operands[4]) == REG | |
8715 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 8716 | return 0; |
8717 | ||
37580c80 | 8718 | /* Only 2 real operands to the subtraction. Subtraction is not a commutative |
8719 | operation, so operands[4] must be the same as operand[3]. */ | |
4ed6ee50 | 8720 | if (! rtx_equal_p (operands[3], operands[4])) |
8721 | return 0; | |
8722 | ||
33f88b1c | 8723 | /* multiply cannot feed into subtraction. */ |
37580c80 | 8724 | if (rtx_equal_p (operands[5], operands[0])) |
4ed6ee50 | 8725 | return 0; |
8726 | ||
33f88b1c | 8727 | /* Inout operand of sub cannot conflict with any operands from multiply. */ |
4ed6ee50 | 8728 | if (rtx_equal_p (operands[3], operands[0]) |
8729 | || rtx_equal_p (operands[3], operands[1]) | |
8730 | || rtx_equal_p (operands[3], operands[2])) | |
8731 | return 0; | |
8732 | ||
ab449421 | 8733 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8734 | if (mode == SFmode | |
bac38c40 | 8735 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8736 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8737 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8738 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8739 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8740 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 8741 | return 0; |
8742 | ||
4ed6ee50 | 8743 | /* Passed. Operands are suitable for fmpysub. */ |
8744 | return 1; | |
8745 | } | |
8746 | ||
6720f95e | 8747 | /* Return 1 if the given constant is 2, 4, or 8. These are the valid |
8748 | constants for shadd instructions. */ | |
913de4b4 | 8749 | int |
e202682d | 8750 | pa_shadd_constant_p (int val) |
6720f95e | 8751 | { |
8752 | if (val == 2 || val == 4 || val == 8) | |
8753 | return 1; | |
8754 | else | |
8755 | return 0; | |
8756 | } | |
3a16146d | 8757 | |
372b3fe2 | 8758 | /* Return TRUE if INSN branches forward. */ |
8759 | ||
8760 | static bool | |
5c1d8983 | 8761 | forward_branch_p (rtx insn) |
5fbd5940 | 8762 | { |
372b3fe2 | 8763 | rtx lab = JUMP_LABEL (insn); |
8764 | ||
8765 | /* The INSN must have a jump label. */ | |
8766 | gcc_assert (lab != NULL_RTX); | |
8767 | ||
8768 | if (INSN_ADDRESSES_SET_P ()) | |
8769 | return INSN_ADDRESSES (INSN_UID (lab)) > INSN_ADDRESSES (INSN_UID (insn)); | |
5fbd5940 | 8770 | |
8771 | while (insn) | |
8772 | { | |
372b3fe2 | 8773 | if (insn == lab) |
8774 | return true; | |
5fbd5940 | 8775 | else |
8776 | insn = NEXT_INSN (insn); | |
8777 | } | |
8778 | ||
372b3fe2 | 8779 | return false; |
5fbd5940 | 8780 | } |
8781 | ||
d6686e21 | 8782 | /* Return 1 if INSN is in the delay slot of a call instruction. */ |
8783 | int | |
e202682d | 8784 | pa_jump_in_call_delay (rtx insn) |
d6686e21 | 8785 | { |
8786 | ||
8787 | if (GET_CODE (insn) != JUMP_INSN) | |
8788 | return 0; | |
8789 | ||
8790 | if (PREV_INSN (insn) | |
8791 | && PREV_INSN (PREV_INSN (insn)) | |
ece0fa59 | 8792 | && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN) |
d6686e21 | 8793 | { |
ece0fa59 | 8794 | rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn))); |
d6686e21 | 8795 | |
8796 | return (GET_CODE (PATTERN (test_insn)) == SEQUENCE | |
8797 | && XVECEXP (PATTERN (test_insn), 0, 1) == insn); | |
8798 | ||
8799 | } | |
8800 | else | |
8801 | return 0; | |
8802 | } | |
3b1e673e | 8803 | |
546a40bd | 8804 | /* Output an unconditional move and branch insn. */ |
8805 | ||
611a88e1 | 8806 | const char * |
e202682d | 8807 | pa_output_parallel_movb (rtx *operands, rtx insn) |
546a40bd | 8808 | { |
f26036bb | 8809 | int length = get_attr_length (insn); |
8810 | ||
546a40bd | 8811 | /* These are the cases in which we win. */ |
8812 | if (length == 4) | |
8813 | return "mov%I1b,tr %1,%0,%2"; | |
8814 | ||
f26036bb | 8815 | /* None of the following cases win, but they don't lose either. */ |
8816 | if (length == 8) | |
546a40bd | 8817 | { |
f26036bb | 8818 | if (dbr_sequence_length () == 0) |
8819 | { | |
8820 | /* Nothing in the delay slot, fake it by putting the combined | |
8821 | insn (the copy or add) in the delay slot of a bl. */ | |
8822 | if (GET_CODE (operands[1]) == CONST_INT) | |
8823 | return "b %2\n\tldi %1,%0"; | |
8824 | else | |
8825 | return "b %2\n\tcopy %1,%0"; | |
8826 | } | |
546a40bd | 8827 | else |
f26036bb | 8828 | { |
8829 | /* Something in the delay slot, but we've got a long branch. */ | |
8830 | if (GET_CODE (operands[1]) == CONST_INT) | |
8831 | return "ldi %1,%0\n\tb %2"; | |
8832 | else | |
8833 | return "copy %1,%0\n\tb %2"; | |
8834 | } | |
546a40bd | 8835 | } |
f26036bb | 8836 | |
8837 | if (GET_CODE (operands[1]) == CONST_INT) | |
8838 | output_asm_insn ("ldi %1,%0", operands); | |
546a40bd | 8839 | else |
f26036bb | 8840 | output_asm_insn ("copy %1,%0", operands); |
e202682d | 8841 | return pa_output_lbranch (operands[2], insn, 1); |
546a40bd | 8842 | } |
8843 | ||
8844 | /* Output an unconditional add and branch insn. */ | |
8845 | ||
611a88e1 | 8846 | const char * |
e202682d | 8847 | pa_output_parallel_addb (rtx *operands, rtx insn) |
546a40bd | 8848 | { |
f26036bb | 8849 | int length = get_attr_length (insn); |
8850 | ||
546a40bd | 8851 | /* To make life easy we want operand0 to be the shared input/output |
8852 | operand and operand1 to be the readonly operand. */ | |
8853 | if (operands[0] == operands[1]) | |
8854 | operands[1] = operands[2]; | |
8855 | ||
8856 | /* These are the cases in which we win. */ | |
8857 | if (length == 4) | |
8858 | return "add%I1b,tr %1,%0,%3"; | |
8859 | ||
f26036bb | 8860 | /* None of the following cases win, but they don't lose either. */ |
8861 | if (length == 8) | |
546a40bd | 8862 | { |
f26036bb | 8863 | if (dbr_sequence_length () == 0) |
8864 | /* Nothing in the delay slot, fake it by putting the combined | |
8865 | insn (the copy or add) in the delay slot of a bl. */ | |
8866 | return "b %3\n\tadd%I1 %1,%0,%0"; | |
8867 | else | |
8868 | /* Something in the delay slot, but we've got a long branch. */ | |
8869 | return "add%I1 %1,%0,%0\n\tb %3"; | |
546a40bd | 8870 | } |
f26036bb | 8871 | |
8872 | output_asm_insn ("add%I1 %1,%0,%0", operands); | |
e202682d | 8873 | return pa_output_lbranch (operands[3], insn, 1); |
546a40bd | 8874 | } |
8875 | ||
7c5101fc | 8876 | /* Return nonzero if INSN (a jump insn) immediately follows a call |
8877 | to a named function. This is used to avoid filling the delay slot | |
8878 | of the jump since it can usually be eliminated by modifying RP in | |
8879 | the delay slot of the call. */ | |
9840d99d | 8880 | |
7d27e4c9 | 8881 | int |
e202682d | 8882 | pa_following_call (rtx insn) |
546a40bd | 8883 | { |
ed1b0769 | 8884 | if (! TARGET_JUMP_IN_DELAY) |
1b6f11e2 | 8885 | return 0; |
8886 | ||
546a40bd | 8887 | /* Find the previous real insn, skipping NOTEs. */ |
8888 | insn = PREV_INSN (insn); | |
8889 | while (insn && GET_CODE (insn) == NOTE) | |
8890 | insn = PREV_INSN (insn); | |
8891 | ||
8892 | /* Check for CALL_INSNs and millicode calls. */ | |
8893 | if (insn | |
1d2e016c | 8894 | && ((GET_CODE (insn) == CALL_INSN |
8895 | && get_attr_type (insn) != TYPE_DYNCALL) | |
546a40bd | 8896 | || (GET_CODE (insn) == INSN |
8897 | && GET_CODE (PATTERN (insn)) != SEQUENCE | |
8898 | && GET_CODE (PATTERN (insn)) != USE | |
8899 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8900 | && get_attr_type (insn) == TYPE_MILLI))) | |
8901 | return 1; | |
8902 | ||
8903 | return 0; | |
8904 | } | |
8905 | ||
3b1e673e | 8906 | /* We use this hook to perform a PA specific optimization which is difficult |
8907 | to do in earlier passes. | |
8908 | ||
8909 | We want the delay slots of branches within jump tables to be filled. | |
8910 | None of the compiler passes at the moment even has the notion that a | |
8911 | PA jump table doesn't contain addresses, but instead contains actual | |
8912 | instructions! | |
8913 | ||
8914 | Because we actually jump into the table, the addresses of each entry | |
01cc3b75 | 8915 | must stay constant in relation to the beginning of the table (which |
3b1e673e | 8916 | itself must stay constant relative to the instruction to jump into |
8917 | it). I don't believe we can guarantee earlier passes of the compiler | |
8918 | will adhere to those rules. | |
8919 | ||
8920 | So, late in the compilation process we find all the jump tables, and | |
a361b456 | 8921 | expand them into real code -- e.g. each entry in the jump table vector |
3b1e673e | 8922 | will get an appropriate label followed by a jump to the final target. |
8923 | ||
8924 | Reorg and the final jump pass can then optimize these branches and | |
8925 | fill their delay slots. We end up with smaller, more efficient code. | |
8926 | ||
9840d99d | 8927 | The jump instructions within the table are special; we must be able |
3b1e673e | 8928 | to identify them during assembly output (if the jumps don't get filled |
8929 | we need to emit a nop rather than nullifying the delay slot)). We | |
b932f66c | 8930 | identify jumps in switch tables by using insns with the attribute |
8931 | type TYPE_BTABLE_BRANCH. | |
9239127b | 8932 | |
8933 | We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB | |
8934 | insns. This serves two purposes, first it prevents jump.c from | |
8935 | noticing that the last N entries in the table jump to the instruction | |
8936 | immediately after the table and deleting the jumps. Second, those | |
8937 | insns mark where we should emit .begin_brtab and .end_brtab directives | |
8938 | when using GAS (allows for better link time optimizations). */ | |
3b1e673e | 8939 | |
2efea8c0 | 8940 | static void |
5c1d8983 | 8941 | pa_reorg (void) |
3b1e673e | 8942 | { |
8943 | rtx insn; | |
8944 | ||
2efea8c0 | 8945 | remove_useless_addtr_insns (1); |
3d457930 | 8946 | |
342aabd9 | 8947 | if (pa_cpu < PROCESSOR_8000) |
2efea8c0 | 8948 | pa_combine_instructions (); |
342aabd9 | 8949 | |
bd49d362 | 8950 | |
3d457930 | 8951 | /* This is fairly cheap, so always run it if optimizing. */ |
a66555b2 | 8952 | if (optimize > 0 && !TARGET_BIG_SWITCH) |
3b1e673e | 8953 | { |
b41266d4 | 8954 | /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */ |
2efea8c0 | 8955 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
3b1e673e | 8956 | { |
b932f66c | 8957 | rtx pattern, tmp, location, label; |
3b1e673e | 8958 | unsigned int length, i; |
8959 | ||
b41266d4 | 8960 | /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */ |
3b1e673e | 8961 | if (GET_CODE (insn) != JUMP_INSN |
b41266d4 | 8962 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8963 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
3b1e673e | 8964 | continue; |
8965 | ||
9239127b | 8966 | /* Emit marker for the beginning of the branch table. */ |
8967 | emit_insn_before (gen_begin_brtab (), insn); | |
f9333726 | 8968 | |
3b1e673e | 8969 | pattern = PATTERN (insn); |
8970 | location = PREV_INSN (insn); | |
b41266d4 | 8971 | length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC); |
f9333726 | 8972 | |
3b1e673e | 8973 | for (i = 0; i < length; i++) |
8974 | { | |
a66555b2 | 8975 | /* Emit a label before each jump to keep jump.c from |
8976 | removing this code. */ | |
8977 | tmp = gen_label_rtx (); | |
8978 | LABEL_NUSES (tmp) = 1; | |
8979 | emit_label_after (tmp, location); | |
8980 | location = NEXT_INSN (location); | |
8981 | ||
b41266d4 | 8982 | if (GET_CODE (pattern) == ADDR_VEC) |
b932f66c | 8983 | label = XEXP (XVECEXP (pattern, 0, i), 0); |
b41266d4 | 8984 | else |
b932f66c | 8985 | label = XEXP (XVECEXP (pattern, 1, i), 0); |
8986 | ||
8987 | tmp = gen_short_jump (label); | |
8988 | ||
8989 | /* Emit the jump itself. */ | |
8990 | tmp = emit_jump_insn_after (tmp, location); | |
8991 | JUMP_LABEL (tmp) = label; | |
8992 | LABEL_NUSES (label)++; | |
8993 | location = NEXT_INSN (location); | |
3b1e673e | 8994 | |
8995 | /* Emit a BARRIER after the jump. */ | |
3b1e673e | 8996 | emit_barrier_after (location); |
3b1e673e | 8997 | location = NEXT_INSN (location); |
8998 | } | |
f9333726 | 8999 | |
9239127b | 9000 | /* Emit marker for the end of the branch table. */ |
9001 | emit_insn_before (gen_end_brtab (), location); | |
9002 | location = NEXT_INSN (location); | |
9003 | emit_barrier_after (location); | |
a66555b2 | 9004 | |
b41266d4 | 9005 | /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */ |
3b1e673e | 9006 | delete_insn (insn); |
9007 | } | |
9008 | } | |
9239127b | 9009 | else |
f9333726 | 9010 | { |
b932f66c | 9011 | /* Still need brtab marker insns. FIXME: the presence of these |
9012 | markers disables output of the branch table to readonly memory, | |
9013 | and any alignment directives that might be needed. Possibly, | |
9014 | the begin_brtab insn should be output before the label for the | |
7bd28bba | 9015 | table. This doesn't matter at the moment since the tables are |
b932f66c | 9016 | always output in the text section. */ |
2efea8c0 | 9017 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
f9333726 | 9018 | { |
9019 | /* Find an ADDR_VEC insn. */ | |
9020 | if (GET_CODE (insn) != JUMP_INSN | |
b41266d4 | 9021 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
9022 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
f9333726 | 9023 | continue; |
9024 | ||
9025 | /* Now generate markers for the beginning and end of the | |
ad87de1e | 9026 | branch table. */ |
f9333726 | 9027 | emit_insn_before (gen_begin_brtab (), insn); |
9028 | emit_insn_after (gen_end_brtab (), insn); | |
9029 | } | |
9030 | } | |
d3287673 | 9031 | } |
bd49d362 | 9032 | |
9033 | /* The PA has a number of odd instructions which can perform multiple | |
9034 | tasks at once. On first generation PA machines (PA1.0 and PA1.1) | |
9035 | it may be profitable to combine two instructions into one instruction | |
9036 | with two outputs. It's not profitable PA2.0 machines because the | |
9037 | two outputs would take two slots in the reorder buffers. | |
9038 | ||
9039 | This routine finds instructions which can be combined and combines | |
9040 | them. We only support some of the potential combinations, and we | |
9041 | only try common ways to find suitable instructions. | |
9042 | ||
9043 | * addb can add two registers or a register and a small integer | |
9044 | and jump to a nearby (+-8k) location. Normally the jump to the | |
9045 | nearby location is conditional on the result of the add, but by | |
9046 | using the "true" condition we can make the jump unconditional. | |
9047 | Thus addb can perform two independent operations in one insn. | |
9048 | ||
9049 | * movb is similar to addb in that it can perform a reg->reg | |
9050 | or small immediate->reg copy and jump to a nearby (+-8k location). | |
9051 | ||
9052 | * fmpyadd and fmpysub can perform a FP multiply and either an | |
9053 | FP add or FP sub if the operands of the multiply and add/sub are | |
9054 | independent (there are other minor restrictions). Note both | |
9055 | the fmpy and fadd/fsub can in theory move to better spots according | |
9056 | to data dependencies, but for now we require the fmpy stay at a | |
9057 | fixed location. | |
9058 | ||
9059 | * Many of the memory operations can perform pre & post updates | |
9060 | of index registers. GCC's pre/post increment/decrement addressing | |
9061 | is far too simple to take advantage of all the possibilities. This | |
9062 | pass may not be suitable since those insns may not be independent. | |
9063 | ||
9064 | * comclr can compare two ints or an int and a register, nullify | |
9065 | the following instruction and zero some other register. This | |
9066 | is more difficult to use as it's harder to find an insn which | |
9067 | will generate a comclr than finding something like an unconditional | |
9068 | branch. (conditional moves & long branches create comclr insns). | |
9069 | ||
9070 | * Most arithmetic operations can conditionally skip the next | |
9071 | instruction. They can be viewed as "perform this operation | |
9072 | and conditionally jump to this nearby location" (where nearby | |
9073 | is an insns away). These are difficult to use due to the | |
9074 | branch length restrictions. */ | |
9075 | ||
7d27e4c9 | 9076 | static void |
5c1d8983 | 9077 | pa_combine_instructions (void) |
bd49d362 | 9078 | { |
8deb3959 | 9079 | rtx anchor, new_rtx; |
bd49d362 | 9080 | |
9081 | /* This can get expensive since the basic algorithm is on the | |
9082 | order of O(n^2) (or worse). Only do it for -O2 or higher | |
ad87de1e | 9083 | levels of optimization. */ |
bd49d362 | 9084 | if (optimize < 2) |
9085 | return; | |
9086 | ||
9087 | /* Walk down the list of insns looking for "anchor" insns which | |
9088 | may be combined with "floating" insns. As the name implies, | |
9089 | "anchor" instructions don't move, while "floating" insns may | |
9090 | move around. */ | |
8deb3959 | 9091 | new_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX)); |
9092 | new_rtx = make_insn_raw (new_rtx); | |
bd49d362 | 9093 | |
9094 | for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor)) | |
9095 | { | |
9096 | enum attr_pa_combine_type anchor_attr; | |
9097 | enum attr_pa_combine_type floater_attr; | |
9098 | ||
9099 | /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs. | |
9100 | Also ignore any special USE insns. */ | |
7d27e4c9 | 9101 | if ((GET_CODE (anchor) != INSN |
bd49d362 | 9102 | && GET_CODE (anchor) != JUMP_INSN |
7d27e4c9 | 9103 | && GET_CODE (anchor) != CALL_INSN) |
bd49d362 | 9104 | || GET_CODE (PATTERN (anchor)) == USE |
9105 | || GET_CODE (PATTERN (anchor)) == CLOBBER | |
9106 | || GET_CODE (PATTERN (anchor)) == ADDR_VEC | |
9107 | || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC) | |
9108 | continue; | |
9109 | ||
9110 | anchor_attr = get_attr_pa_combine_type (anchor); | |
9111 | /* See if anchor is an insn suitable for combination. */ | |
9112 | if (anchor_attr == PA_COMBINE_TYPE_FMPY | |
9113 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9114 | || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
9115 | && ! forward_branch_p (anchor))) | |
9116 | { | |
9117 | rtx floater; | |
9118 | ||
9119 | for (floater = PREV_INSN (anchor); | |
9120 | floater; | |
9121 | floater = PREV_INSN (floater)) | |
9122 | { | |
9123 | if (GET_CODE (floater) == NOTE | |
9124 | || (GET_CODE (floater) == INSN | |
9125 | && (GET_CODE (PATTERN (floater)) == USE | |
9126 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
9127 | continue; | |
9128 | ||
9129 | /* Anything except a regular INSN will stop our search. */ | |
9130 | if (GET_CODE (floater) != INSN | |
9131 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
9132 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
9133 | { | |
9134 | floater = NULL_RTX; | |
9135 | break; | |
9136 | } | |
9137 | ||
9138 | /* See if FLOATER is suitable for combination with the | |
9139 | anchor. */ | |
9140 | floater_attr = get_attr_pa_combine_type (floater); | |
9141 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
9142 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
9143 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9144 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
9145 | { | |
9146 | /* If ANCHOR and FLOATER can be combined, then we're | |
9147 | done with this pass. */ | |
8deb3959 | 9148 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
bd49d362 | 9149 | SET_DEST (PATTERN (floater)), |
9150 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
9151 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
9152 | break; | |
9153 | } | |
9154 | ||
9155 | else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
9156 | && floater_attr == PA_COMBINE_TYPE_ADDMOVE) | |
9157 | { | |
9158 | if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS) | |
9159 | { | |
8deb3959 | 9160 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
bd49d362 | 9161 | SET_DEST (PATTERN (floater)), |
9162 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
9163 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
9164 | break; | |
9165 | } | |
9166 | else | |
9167 | { | |
8deb3959 | 9168 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
bd49d362 | 9169 | SET_DEST (PATTERN (floater)), |
9170 | SET_SRC (PATTERN (floater)), | |
9171 | SET_SRC (PATTERN (floater)))) | |
9172 | break; | |
9173 | } | |
9174 | } | |
9175 | } | |
9176 | ||
9177 | /* If we didn't find anything on the backwards scan try forwards. */ | |
9178 | if (!floater | |
9179 | && (anchor_attr == PA_COMBINE_TYPE_FMPY | |
9180 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB)) | |
9181 | { | |
9182 | for (floater = anchor; floater; floater = NEXT_INSN (floater)) | |
9183 | { | |
9184 | if (GET_CODE (floater) == NOTE | |
9185 | || (GET_CODE (floater) == INSN | |
9186 | && (GET_CODE (PATTERN (floater)) == USE | |
9187 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
9840d99d | 9188 | |
bd49d362 | 9189 | continue; |
9190 | ||
9191 | /* Anything except a regular INSN will stop our search. */ | |
9192 | if (GET_CODE (floater) != INSN | |
9193 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
9194 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
9195 | { | |
9196 | floater = NULL_RTX; | |
9197 | break; | |
9198 | } | |
9199 | ||
9200 | /* See if FLOATER is suitable for combination with the | |
9201 | anchor. */ | |
9202 | floater_attr = get_attr_pa_combine_type (floater); | |
9203 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
9204 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
9205 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9206 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
9207 | { | |
9208 | /* If ANCHOR and FLOATER can be combined, then we're | |
9209 | done with this pass. */ | |
8deb3959 | 9210 | if (pa_can_combine_p (new_rtx, anchor, floater, 1, |
bd49d362 | 9211 | SET_DEST (PATTERN (floater)), |
ea52c577 | 9212 | XEXP (SET_SRC (PATTERN (floater)), |
9213 | 0), | |
9214 | XEXP (SET_SRC (PATTERN (floater)), | |
9215 | 1))) | |
bd49d362 | 9216 | break; |
9217 | } | |
9218 | } | |
9219 | } | |
9220 | ||
9221 | /* FLOATER will be nonzero if we found a suitable floating | |
9222 | insn for combination with ANCHOR. */ | |
9223 | if (floater | |
9224 | && (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9225 | || anchor_attr == PA_COMBINE_TYPE_FMPY)) | |
9226 | { | |
9227 | /* Emit the new instruction and delete the old anchor. */ | |
7014838c | 9228 | emit_insn_before (gen_rtx_PARALLEL |
9229 | (VOIDmode, | |
9230 | gen_rtvec (2, PATTERN (anchor), | |
9231 | PATTERN (floater))), | |
9232 | anchor); | |
9233 | ||
ad4583d9 | 9234 | SET_INSN_DELETED (anchor); |
bd49d362 | 9235 | |
9236 | /* Emit a special USE insn for FLOATER, then delete | |
9237 | the floating insn. */ | |
ad851752 | 9238 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 9239 | delete_insn (floater); |
9240 | ||
9241 | continue; | |
9242 | } | |
9243 | else if (floater | |
9244 | && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH) | |
9245 | { | |
9246 | rtx temp; | |
9247 | /* Emit the new_jump instruction and delete the old anchor. */ | |
7014838c | 9248 | temp |
9249 | = emit_jump_insn_before (gen_rtx_PARALLEL | |
9250 | (VOIDmode, | |
9251 | gen_rtvec (2, PATTERN (anchor), | |
9252 | PATTERN (floater))), | |
9253 | anchor); | |
9254 | ||
bd49d362 | 9255 | JUMP_LABEL (temp) = JUMP_LABEL (anchor); |
ad4583d9 | 9256 | SET_INSN_DELETED (anchor); |
bd49d362 | 9257 | |
9258 | /* Emit a special USE insn for FLOATER, then delete | |
9259 | the floating insn. */ | |
ad851752 | 9260 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 9261 | delete_insn (floater); |
9262 | continue; | |
9263 | } | |
9264 | } | |
9265 | } | |
9266 | } | |
9267 | ||
9aadea62 | 9268 | static int |
8deb3959 | 9269 | pa_can_combine_p (rtx new_rtx, rtx anchor, rtx floater, int reversed, rtx dest, |
5c1d8983 | 9270 | rtx src1, rtx src2) |
bd49d362 | 9271 | { |
9272 | int insn_code_number; | |
9273 | rtx start, end; | |
9274 | ||
9275 | /* Create a PARALLEL with the patterns of ANCHOR and | |
9276 | FLOATER, try to recognize it, then test constraints | |
9277 | for the resulting pattern. | |
9278 | ||
9279 | If the pattern doesn't match or the constraints | |
9280 | aren't met keep searching for a suitable floater | |
9281 | insn. */ | |
8deb3959 | 9282 | XVECEXP (PATTERN (new_rtx), 0, 0) = PATTERN (anchor); |
9283 | XVECEXP (PATTERN (new_rtx), 0, 1) = PATTERN (floater); | |
9284 | INSN_CODE (new_rtx) = -1; | |
9285 | insn_code_number = recog_memoized (new_rtx); | |
bd49d362 | 9286 | if (insn_code_number < 0 |
8deb3959 | 9287 | || (extract_insn (new_rtx), ! constrain_operands (1))) |
bd49d362 | 9288 | return 0; |
9289 | ||
9290 | if (reversed) | |
9291 | { | |
9292 | start = anchor; | |
9293 | end = floater; | |
9294 | } | |
9295 | else | |
9296 | { | |
9297 | start = floater; | |
9298 | end = anchor; | |
9299 | } | |
9300 | ||
9301 | /* There's up to three operands to consider. One | |
9302 | output and two inputs. | |
9303 | ||
9304 | The output must not be used between FLOATER & ANCHOR | |
9305 | exclusive. The inputs must not be set between | |
9306 | FLOATER and ANCHOR exclusive. */ | |
9307 | ||
9308 | if (reg_used_between_p (dest, start, end)) | |
9309 | return 0; | |
9310 | ||
9311 | if (reg_set_between_p (src1, start, end)) | |
9312 | return 0; | |
9313 | ||
9314 | if (reg_set_between_p (src2, start, end)) | |
9315 | return 0; | |
9316 | ||
9317 | /* If we get here, then everything is good. */ | |
9318 | return 1; | |
9319 | } | |
14d18de3 | 9320 | |
a6582a53 | 9321 | /* Return nonzero if references for INSN are delayed. |
14d18de3 | 9322 | |
9323 | Millicode insns are actually function calls with some special | |
9324 | constraints on arguments and register usage. | |
9325 | ||
9326 | Millicode calls always expect their arguments in the integer argument | |
9327 | registers, and always return their result in %r29 (ret1). They | |
2013ddf6 | 9328 | are expected to clobber their arguments, %r1, %r29, and the return |
9329 | pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else. | |
9330 | ||
9331 | This function tells reorg that the references to arguments and | |
9332 | millicode calls do not appear to happen until after the millicode call. | |
9333 | This allows reorg to put insns which set the argument registers into the | |
9334 | delay slot of the millicode call -- thus they act more like traditional | |
9335 | CALL_INSNs. | |
9336 | ||
33f88b1c | 9337 | Note we cannot consider side effects of the insn to be delayed because |
2013ddf6 | 9338 | the branch and link insn will clobber the return pointer. If we happened |
9339 | to use the return pointer in the delay slot of the call, then we lose. | |
14d18de3 | 9340 | |
9341 | get_attr_type will try to recognize the given insn, so make sure to | |
9342 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
9343 | in particular. */ | |
9344 | int | |
e202682d | 9345 | pa_insn_refs_are_delayed (rtx insn) |
14d18de3 | 9346 | { |
9840d99d | 9347 | return ((GET_CODE (insn) == INSN |
14d18de3 | 9348 | && GET_CODE (PATTERN (insn)) != SEQUENCE |
9349 | && GET_CODE (PATTERN (insn)) != USE | |
9350 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
9351 | && get_attr_type (insn) == TYPE_MILLI)); | |
9352 | } | |
5cb4669a | 9353 | |
3b2411a8 | 9354 | /* Promote the return value, but not the arguments. */ |
9355 | ||
a6b21a58 | 9356 | static enum machine_mode |
3b2411a8 | 9357 | pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, |
9358 | enum machine_mode mode, | |
9359 | int *punsignedp ATTRIBUTE_UNUSED, | |
9360 | const_tree fntype ATTRIBUTE_UNUSED, | |
9361 | int for_return) | |
9362 | { | |
c879dbcf | 9363 | if (for_return == 0) |
3b2411a8 | 9364 | return mode; |
a6b21a58 | 9365 | return promote_mode (type, mode, punsignedp); |
3b2411a8 | 9366 | } |
9367 | ||
58a72cce | 9368 | /* On the HP-PA the value is found in register(s) 28(-29), unless |
9369 | the mode is SF or DF. Then the value is returned in fr4 (32). | |
9370 | ||
3b2411a8 | 9371 | This must perform the same promotions as PROMOTE_MODE, else promoting |
9372 | return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly. | |
58a72cce | 9373 | |
9374 | Small structures must be returned in a PARALLEL on PA64 in order | |
9375 | to match the HP Compiler ABI. */ | |
9376 | ||
93d3ee56 | 9377 | static rtx |
cb0b8817 | 9378 | pa_function_value (const_tree valtype, |
9379 | const_tree func ATTRIBUTE_UNUSED, | |
9380 | bool outgoing ATTRIBUTE_UNUSED) | |
58a72cce | 9381 | { |
9382 | enum machine_mode valmode; | |
9383 | ||
4779159e | 9384 | if (AGGREGATE_TYPE_P (valtype) |
9385 | || TREE_CODE (valtype) == COMPLEX_TYPE | |
9386 | || TREE_CODE (valtype) == VECTOR_TYPE) | |
58a72cce | 9387 | { |
b105ef41 | 9388 | if (TARGET_64BIT) |
9389 | { | |
9390 | /* Aggregates with a size less than or equal to 128 bits are | |
9391 | returned in GR 28(-29). They are left justified. The pad | |
9392 | bits are undefined. Larger aggregates are returned in | |
9393 | memory. */ | |
9394 | rtx loc[2]; | |
9395 | int i, offset = 0; | |
9396 | int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2; | |
9397 | ||
9398 | for (i = 0; i < ub; i++) | |
9399 | { | |
9400 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
9401 | gen_rtx_REG (DImode, 28 + i), | |
9402 | GEN_INT (offset)); | |
9403 | offset += 8; | |
9404 | } | |
58a72cce | 9405 | |
b105ef41 | 9406 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc)); |
9407 | } | |
9408 | else if (int_size_in_bytes (valtype) > UNITS_PER_WORD) | |
58a72cce | 9409 | { |
b105ef41 | 9410 | /* Aggregates 5 to 8 bytes in size are returned in general |
9411 | registers r28-r29 in the same manner as other non | |
9412 | floating-point objects. The data is right-justified and | |
9413 | zero-extended to 64 bits. This is opposite to the normal | |
9414 | justification used on big endian targets and requires | |
9415 | special treatment. */ | |
9416 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, | |
9417 | gen_rtx_REG (DImode, 28), const0_rtx); | |
9418 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc)); | |
58a72cce | 9419 | } |
58a72cce | 9420 | } |
9421 | ||
9422 | if ((INTEGRAL_TYPE_P (valtype) | |
eb46b0b6 | 9423 | && GET_MODE_BITSIZE (TYPE_MODE (valtype)) < BITS_PER_WORD) |
58a72cce | 9424 | || POINTER_TYPE_P (valtype)) |
9425 | valmode = word_mode; | |
9426 | else | |
9427 | valmode = TYPE_MODE (valtype); | |
9428 | ||
9429 | if (TREE_CODE (valtype) == REAL_TYPE | |
b105ef41 | 9430 | && !AGGREGATE_TYPE_P (valtype) |
58a72cce | 9431 | && TYPE_MODE (valtype) != TFmode |
9432 | && !TARGET_SOFT_FLOAT) | |
9433 | return gen_rtx_REG (valmode, 32); | |
9434 | ||
9435 | return gen_rtx_REG (valmode, 28); | |
9436 | } | |
9437 | ||
93d3ee56 | 9438 | /* Implement the TARGET_LIBCALL_VALUE hook. */ |
9439 | ||
9440 | static rtx | |
9441 | pa_libcall_value (enum machine_mode mode, | |
9442 | const_rtx fun ATTRIBUTE_UNUSED) | |
9443 | { | |
9444 | if (! TARGET_SOFT_FLOAT | |
9445 | && (mode == SFmode || mode == DFmode)) | |
9446 | return gen_rtx_REG (mode, 32); | |
9447 | else | |
9448 | return gen_rtx_REG (mode, 28); | |
9449 | } | |
9450 | ||
9451 | /* Implement the TARGET_FUNCTION_VALUE_REGNO_P hook. */ | |
9452 | ||
9453 | static bool | |
9454 | pa_function_value_regno_p (const unsigned int regno) | |
9455 | { | |
9456 | if (regno == 28 | |
9457 | || (! TARGET_SOFT_FLOAT && regno == 32)) | |
9458 | return true; | |
9459 | ||
9460 | return false; | |
9461 | } | |
9462 | ||
8b4bd662 | 9463 | /* Update the data in CUM to advance over an argument |
9464 | of mode MODE and data type TYPE. | |
9465 | (TYPE is null for libcalls where that information may not be available.) */ | |
9466 | ||
9467 | static void | |
39cba157 | 9468 | pa_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, |
8b4bd662 | 9469 | const_tree type, bool named ATTRIBUTE_UNUSED) |
9470 | { | |
39cba157 | 9471 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
8b4bd662 | 9472 | int arg_size = FUNCTION_ARG_SIZE (mode, type); |
9473 | ||
9474 | cum->nargs_prototype--; | |
9475 | cum->words += (arg_size | |
9476 | + ((cum->words & 01) | |
9477 | && type != NULL_TREE | |
9478 | && arg_size > 1)); | |
9479 | } | |
9480 | ||
5e3c5739 | 9481 | /* Return the location of a parameter that is passed in a register or NULL |
9482 | if the parameter has any component that is passed in memory. | |
9483 | ||
9484 | This is new code and will be pushed to into the net sources after | |
9840d99d | 9485 | further testing. |
5e3c5739 | 9486 | |
9487 | ??? We might want to restructure this so that it looks more like other | |
9488 | ports. */ | |
8b4bd662 | 9489 | static rtx |
39cba157 | 9490 | pa_function_arg (cumulative_args_t cum_v, enum machine_mode mode, |
8b4bd662 | 9491 | const_tree type, bool named ATTRIBUTE_UNUSED) |
5e3c5739 | 9492 | { |
39cba157 | 9493 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
5e3c5739 | 9494 | int max_arg_words = (TARGET_64BIT ? 8 : 4); |
2a075f91 | 9495 | int alignment = 0; |
ac965869 | 9496 | int arg_size; |
5e3c5739 | 9497 | int fpr_reg_base; |
9498 | int gpr_reg_base; | |
9499 | rtx retval; | |
9500 | ||
ac965869 | 9501 | if (mode == VOIDmode) |
9502 | return NULL_RTX; | |
9503 | ||
9504 | arg_size = FUNCTION_ARG_SIZE (mode, type); | |
9505 | ||
9506 | /* If this arg would be passed partially or totally on the stack, then | |
f054eb3c | 9507 | this routine should return zero. pa_arg_partial_bytes will |
ac965869 | 9508 | handle arguments which are split between regs and stack slots if |
9509 | the ABI mandates split arguments. */ | |
4779159e | 9510 | if (!TARGET_64BIT) |
5e3c5739 | 9511 | { |
ac965869 | 9512 | /* The 32-bit ABI does not split arguments. */ |
9513 | if (cum->words + arg_size > max_arg_words) | |
5e3c5739 | 9514 | return NULL_RTX; |
9515 | } | |
9516 | else | |
9517 | { | |
2a075f91 | 9518 | if (arg_size > 1) |
9519 | alignment = cum->words & 1; | |
ac965869 | 9520 | if (cum->words + alignment >= max_arg_words) |
5e3c5739 | 9521 | return NULL_RTX; |
9522 | } | |
9523 | ||
9524 | /* The 32bit ABIs and the 64bit ABIs are rather different, | |
9525 | particularly in their handling of FP registers. We might | |
9526 | be able to cleverly share code between them, but I'm not | |
9aadea62 | 9527 | going to bother in the hope that splitting them up results |
2a075f91 | 9528 | in code that is more easily understood. */ |
5e3c5739 | 9529 | |
5e3c5739 | 9530 | if (TARGET_64BIT) |
9531 | { | |
9532 | /* Advance the base registers to their current locations. | |
9533 | ||
9534 | Remember, gprs grow towards smaller register numbers while | |
2a075f91 | 9535 | fprs grow to higher register numbers. Also remember that |
9536 | although FP regs are 32-bit addressable, we pretend that | |
9537 | the registers are 64-bits wide. */ | |
5e3c5739 | 9538 | gpr_reg_base = 26 - cum->words; |
9539 | fpr_reg_base = 32 + cum->words; | |
9840d99d | 9540 | |
ac965869 | 9541 | /* Arguments wider than one word and small aggregates need special |
9542 | treatment. */ | |
9543 | if (arg_size > 1 | |
9544 | || mode == BLKmode | |
4779159e | 9545 | || (type && (AGGREGATE_TYPE_P (type) |
9546 | || TREE_CODE (type) == COMPLEX_TYPE | |
9547 | || TREE_CODE (type) == VECTOR_TYPE))) | |
5e3c5739 | 9548 | { |
2a075f91 | 9549 | /* Double-extended precision (80-bit), quad-precision (128-bit) |
9550 | and aggregates including complex numbers are aligned on | |
9551 | 128-bit boundaries. The first eight 64-bit argument slots | |
9552 | are associated one-to-one, with general registers r26 | |
9553 | through r19, and also with floating-point registers fr4 | |
9554 | through fr11. Arguments larger than one word are always | |
ac965869 | 9555 | passed in general registers. |
9556 | ||
9557 | Using a PARALLEL with a word mode register results in left | |
9558 | justified data on a big-endian target. */ | |
2a075f91 | 9559 | |
9560 | rtx loc[8]; | |
9561 | int i, offset = 0, ub = arg_size; | |
9562 | ||
9563 | /* Align the base register. */ | |
9564 | gpr_reg_base -= alignment; | |
9565 | ||
9566 | ub = MIN (ub, max_arg_words - cum->words - alignment); | |
9567 | for (i = 0; i < ub; i++) | |
5e3c5739 | 9568 | { |
2a075f91 | 9569 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, |
9570 | gen_rtx_REG (DImode, gpr_reg_base), | |
9571 | GEN_INT (offset)); | |
9572 | gpr_reg_base -= 1; | |
9573 | offset += 8; | |
5e3c5739 | 9574 | } |
2a075f91 | 9575 | |
e2810de9 | 9576 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc)); |
5e3c5739 | 9577 | } |
ac965869 | 9578 | } |
5e3c5739 | 9579 | else |
9580 | { | |
9581 | /* If the argument is larger than a word, then we know precisely | |
9582 | which registers we must use. */ | |
2a075f91 | 9583 | if (arg_size > 1) |
5e3c5739 | 9584 | { |
9585 | if (cum->words) | |
9586 | { | |
9587 | gpr_reg_base = 23; | |
9588 | fpr_reg_base = 38; | |
9589 | } | |
9590 | else | |
9591 | { | |
9592 | gpr_reg_base = 25; | |
9593 | fpr_reg_base = 34; | |
9594 | } | |
ac965869 | 9595 | |
9596 | /* Structures 5 to 8 bytes in size are passed in the general | |
9597 | registers in the same manner as other non floating-point | |
9598 | objects. The data is right-justified and zero-extended | |
9f0b40a7 | 9599 | to 64 bits. This is opposite to the normal justification |
9600 | used on big endian targets and requires special treatment. | |
4779159e | 9601 | We now define BLOCK_REG_PADDING to pad these objects. |
9602 | Aggregates, complex and vector types are passed in the same | |
9603 | manner as structures. */ | |
9604 | if (mode == BLKmode | |
9605 | || (type && (AGGREGATE_TYPE_P (type) | |
9606 | || TREE_CODE (type) == COMPLEX_TYPE | |
9607 | || TREE_CODE (type) == VECTOR_TYPE))) | |
ac965869 | 9608 | { |
58a72cce | 9609 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, |
9610 | gen_rtx_REG (DImode, gpr_reg_base), | |
9611 | const0_rtx); | |
b105ef41 | 9612 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc)); |
ac965869 | 9613 | } |
5e3c5739 | 9614 | } |
9615 | else | |
9616 | { | |
9617 | /* We have a single word (32 bits). A simple computation | |
9618 | will get us the register #s we need. */ | |
9619 | gpr_reg_base = 26 - cum->words; | |
9620 | fpr_reg_base = 32 + 2 * cum->words; | |
9621 | } | |
9622 | } | |
9623 | ||
9503b0f7 | 9624 | /* Determine if the argument needs to be passed in both general and |
5e3c5739 | 9625 | floating point registers. */ |
9503b0f7 | 9626 | if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32) |
9627 | /* If we are doing soft-float with portable runtime, then there | |
9628 | is no need to worry about FP regs. */ | |
f336e0bc | 9629 | && !TARGET_SOFT_FLOAT |
4779159e | 9630 | /* The parameter must be some kind of scalar float, else we just |
9503b0f7 | 9631 | pass it in integer registers. */ |
4779159e | 9632 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
9503b0f7 | 9633 | /* The target function must not have a prototype. */ |
9634 | && cum->nargs_prototype <= 0 | |
9635 | /* libcalls do not need to pass items in both FP and general | |
9636 | registers. */ | |
9637 | && type != NULL_TREE | |
f336e0bc | 9638 | /* All this hair applies to "outgoing" args only. This includes |
9639 | sibcall arguments setup with FUNCTION_INCOMING_ARG. */ | |
9640 | && !cum->incoming) | |
9503b0f7 | 9641 | /* Also pass outgoing floating arguments in both registers in indirect |
9642 | calls with the 32 bit ABI and the HP assembler since there is no | |
9643 | way to the specify argument locations in static functions. */ | |
f336e0bc | 9644 | || (!TARGET_64BIT |
9645 | && !TARGET_GAS | |
9646 | && !cum->incoming | |
9503b0f7 | 9647 | && cum->indirect |
4779159e | 9648 | && GET_MODE_CLASS (mode) == MODE_FLOAT)) |
5e3c5739 | 9649 | { |
9650 | retval | |
9651 | = gen_rtx_PARALLEL | |
9652 | (mode, | |
9653 | gen_rtvec (2, | |
9654 | gen_rtx_EXPR_LIST (VOIDmode, | |
9655 | gen_rtx_REG (mode, fpr_reg_base), | |
9656 | const0_rtx), | |
9657 | gen_rtx_EXPR_LIST (VOIDmode, | |
9658 | gen_rtx_REG (mode, gpr_reg_base), | |
9659 | const0_rtx))); | |
9660 | } | |
9661 | else | |
9662 | { | |
9663 | /* See if we should pass this parameter in a general register. */ | |
9664 | if (TARGET_SOFT_FLOAT | |
9665 | /* Indirect calls in the normal 32bit ABI require all arguments | |
9666 | to be passed in general registers. */ | |
9667 | || (!TARGET_PORTABLE_RUNTIME | |
9668 | && !TARGET_64BIT | |
a052da6f | 9669 | && !TARGET_ELF32 |
5e3c5739 | 9670 | && cum->indirect) |
4779159e | 9671 | /* If the parameter is not a scalar floating-point parameter, |
9672 | then it belongs in GPRs. */ | |
9673 | || GET_MODE_CLASS (mode) != MODE_FLOAT | |
b105ef41 | 9674 | /* Structure with single SFmode field belongs in GPR. */ |
9675 | || (type && AGGREGATE_TYPE_P (type))) | |
5e3c5739 | 9676 | retval = gen_rtx_REG (mode, gpr_reg_base); |
9677 | else | |
9678 | retval = gen_rtx_REG (mode, fpr_reg_base); | |
9679 | } | |
9680 | return retval; | |
9681 | } | |
9682 | ||
bd99ba64 | 9683 | /* Arguments larger than one word are double word aligned. */ |
9684 | ||
9685 | static unsigned int | |
9686 | pa_function_arg_boundary (enum machine_mode mode, const_tree type) | |
9687 | { | |
bd99ba64 | 9688 | bool singleword = (type |
57a9c540 | 9689 | ? (integer_zerop (TYPE_SIZE (type)) |
9690 | || !TREE_CONSTANT (TYPE_SIZE (type)) | |
bd99ba64 | 9691 | || int_size_in_bytes (type) <= UNITS_PER_WORD) |
23e85af8 | 9692 | : GET_MODE_SIZE (mode) <= UNITS_PER_WORD); |
bd99ba64 | 9693 | |
9694 | return singleword ? PARM_BOUNDARY : MAX_PARM_BOUNDARY; | |
9695 | } | |
5e3c5739 | 9696 | |
9697 | /* If this arg would be passed totally in registers or totally on the stack, | |
f054eb3c | 9698 | then this routine should return zero. */ |
9699 | ||
9700 | static int | |
39cba157 | 9701 | pa_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode, |
f054eb3c | 9702 | tree type, bool named ATTRIBUTE_UNUSED) |
5e3c5739 | 9703 | { |
39cba157 | 9704 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
b7d86581 | 9705 | unsigned int max_arg_words = 8; |
9706 | unsigned int offset = 0; | |
5e3c5739 | 9707 | |
f054eb3c | 9708 | if (!TARGET_64BIT) |
9709 | return 0; | |
9710 | ||
b7d86581 | 9711 | if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1)) |
5e3c5739 | 9712 | offset = 1; |
9713 | ||
b7d86581 | 9714 | if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words) |
6dc3b0d9 | 9715 | /* Arg fits fully into registers. */ |
5e3c5739 | 9716 | return 0; |
9840d99d | 9717 | else if (cum->words + offset >= max_arg_words) |
6dc3b0d9 | 9718 | /* Arg fully on the stack. */ |
5e3c5739 | 9719 | return 0; |
9720 | else | |
6dc3b0d9 | 9721 | /* Arg is split. */ |
f054eb3c | 9722 | return (max_arg_words - cum->words - offset) * UNITS_PER_WORD; |
5e3c5739 | 9723 | } |
9724 | ||
9725 | ||
2f14b1f9 | 9726 | /* A get_unnamed_section callback for switching to the text section. |
916c9cef | 9727 | |
9728 | This function is only used with SOM. Because we don't support | |
9729 | named subspaces, we can only create a new subspace or switch back | |
99c11254 | 9730 | to the default text subspace. */ |
99c11254 | 9731 | |
2f14b1f9 | 9732 | static void |
9733 | som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
9734 | { | |
9735 | gcc_assert (TARGET_SOM); | |
99c11254 | 9736 | if (TARGET_GAS) |
916c9cef | 9737 | { |
9f4a0384 | 9738 | if (cfun && cfun->machine && !cfun->machine->in_nsubspa) |
916c9cef | 9739 | { |
9740 | /* We only want to emit a .nsubspa directive once at the | |
9741 | start of the function. */ | |
9742 | cfun->machine->in_nsubspa = 1; | |
9743 | ||
9744 | /* Create a new subspace for the text. This provides | |
9745 | better stub placement and one-only functions. */ | |
9746 | if (cfun->decl | |
9747 | && DECL_ONE_ONLY (cfun->decl) | |
9748 | && !DECL_WEAK (cfun->decl)) | |
78962d38 | 9749 | { |
9750 | output_section_asm_op ("\t.SPACE $TEXT$\n" | |
9751 | "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8," | |
9752 | "ACCESS=44,SORT=24,COMDAT"); | |
9753 | return; | |
9754 | } | |
916c9cef | 9755 | } |
9756 | else | |
9757 | { | |
9758 | /* There isn't a current function or the body of the current | |
9759 | function has been completed. So, we are changing to the | |
78962d38 | 9760 | text section to output debugging information. Thus, we |
9761 | need to forget that we are in the text section so that | |
9762 | varasm.c will call us when text_section is selected again. */ | |
9f4a0384 | 9763 | gcc_assert (!cfun || !cfun->machine |
9764 | || cfun->machine->in_nsubspa == 2); | |
2f14b1f9 | 9765 | in_section = NULL; |
916c9cef | 9766 | } |
78962d38 | 9767 | output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$"); |
9768 | return; | |
916c9cef | 9769 | } |
2f14b1f9 | 9770 | output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$"); |
9771 | } | |
9772 | ||
78962d38 | 9773 | /* A get_unnamed_section callback for switching to comdat data |
9774 | sections. This function is only used with SOM. */ | |
9775 | ||
9776 | static void | |
9777 | som_output_comdat_data_section_asm_op (const void *data) | |
9778 | { | |
9779 | in_section = NULL; | |
9780 | output_section_asm_op (data); | |
9781 | } | |
9782 | ||
2f14b1f9 | 9783 | /* Implement TARGET_ASM_INITIALIZE_SECTIONS */ |
916c9cef | 9784 | |
2f14b1f9 | 9785 | static void |
9786 | pa_som_asm_init_sections (void) | |
9787 | { | |
9788 | text_section | |
9789 | = get_unnamed_section (0, som_output_text_section_asm_op, NULL); | |
9790 | ||
9791 | /* SOM puts readonly data in the default $LIT$ subspace when PIC code | |
9792 | is not being generated. */ | |
9793 | som_readonly_data_section | |
9794 | = get_unnamed_section (0, output_section_asm_op, | |
9795 | "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$"); | |
9796 | ||
9797 | /* When secondary definitions are not supported, SOM makes readonly | |
9798 | data one-only by creating a new $LIT$ subspace in $TEXT$ with | |
9799 | the comdat flag. */ | |
9800 | som_one_only_readonly_data_section | |
78962d38 | 9801 | = get_unnamed_section (0, som_output_comdat_data_section_asm_op, |
2f14b1f9 | 9802 | "\t.SPACE $TEXT$\n" |
9803 | "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8," | |
9804 | "ACCESS=0x2c,SORT=16,COMDAT"); | |
9805 | ||
9806 | ||
9807 | /* When secondary definitions are not supported, SOM makes data one-only | |
9808 | by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */ | |
9809 | som_one_only_data_section | |
78962d38 | 9810 | = get_unnamed_section (SECTION_WRITE, |
9811 | som_output_comdat_data_section_asm_op, | |
2f14b1f9 | 9812 | "\t.SPACE $PRIVATE$\n" |
9813 | "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8," | |
9814 | "ACCESS=31,SORT=24,COMDAT"); | |
9815 | ||
8151bf30 | 9816 | if (flag_tm) |
9817 | som_tm_clone_table_section | |
9818 | = get_unnamed_section (0, output_section_asm_op, | |
9819 | "\t.SPACE $PRIVATE$\n\t.SUBSPA $TM_CLONE_TABLE$"); | |
9820 | ||
2f14b1f9 | 9821 | /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups |
9822 | which reference data within the $TEXT$ space (for example constant | |
9823 | strings in the $LIT$ subspace). | |
9824 | ||
9825 | The assemblers (GAS and HP as) both have problems with handling | |
9826 | the difference of two symbols which is the other correct way to | |
9827 | reference constant data during PIC code generation. | |
9828 | ||
9829 | So, there's no way to reference constant data which is in the | |
9830 | $TEXT$ space during PIC generation. Instead place all constant | |
9831 | data into the $PRIVATE$ subspace (this reduces sharing, but it | |
9832 | works correctly). */ | |
9833 | readonly_data_section = flag_pic ? data_section : som_readonly_data_section; | |
9834 | ||
9835 | /* We must not have a reference to an external symbol defined in a | |
9836 | shared library in a readonly section, else the SOM linker will | |
9837 | complain. | |
9838 | ||
9839 | So, we force exception information into the data section. */ | |
9840 | exception_section = data_section; | |
916c9cef | 9841 | } |
9842 | ||
8151bf30 | 9843 | /* Implement TARGET_ASM_TM_CLONE_TABLE_SECTION. */ |
9844 | ||
9845 | static section * | |
9846 | pa_som_tm_clone_table_section (void) | |
9847 | { | |
9848 | return som_tm_clone_table_section; | |
9849 | } | |
9850 | ||
52470889 | 9851 | /* On hpux10, the linker will give an error if we have a reference |
9852 | in the read-only data section to a symbol defined in a shared | |
9853 | library. Therefore, expressions that might require a reloc can | |
9854 | not be placed in the read-only data section. */ | |
9855 | ||
2f14b1f9 | 9856 | static section * |
b572d1a5 | 9857 | pa_select_section (tree exp, int reloc, |
9858 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
52470889 | 9859 | { |
9860 | if (TREE_CODE (exp) == VAR_DECL | |
9861 | && TREE_READONLY (exp) | |
9862 | && !TREE_THIS_VOLATILE (exp) | |
9863 | && DECL_INITIAL (exp) | |
9864 | && (DECL_INITIAL (exp) == error_mark_node | |
9865 | || TREE_CONSTANT (DECL_INITIAL (exp))) | |
9866 | && !reloc) | |
916c9cef | 9867 | { |
9868 | if (TARGET_SOM | |
9869 | && DECL_ONE_ONLY (exp) | |
9870 | && !DECL_WEAK (exp)) | |
2f14b1f9 | 9871 | return som_one_only_readonly_data_section; |
916c9cef | 9872 | else |
2f14b1f9 | 9873 | return readonly_data_section; |
916c9cef | 9874 | } |
ce45a448 | 9875 | else if (CONSTANT_CLASS_P (exp) && !reloc) |
2f14b1f9 | 9876 | return readonly_data_section; |
916c9cef | 9877 | else if (TARGET_SOM |
9878 | && TREE_CODE (exp) == VAR_DECL | |
9879 | && DECL_ONE_ONLY (exp) | |
2455c36b | 9880 | && !DECL_WEAK (exp)) |
2f14b1f9 | 9881 | return som_one_only_data_section; |
52470889 | 9882 | else |
2f14b1f9 | 9883 | return data_section; |
52470889 | 9884 | } |
1f3233d1 | 9885 | |
67c1e638 | 9886 | static void |
5c1d8983 | 9887 | pa_globalize_label (FILE *stream, const char *name) |
67c1e638 | 9888 | { |
9889 | /* We only handle DATA objects here, functions are globalized in | |
9890 | ASM_DECLARE_FUNCTION_NAME. */ | |
9891 | if (! FUNCTION_NAME_P (name)) | |
9892 | { | |
9893 | fputs ("\t.EXPORT ", stream); | |
9894 | assemble_name (stream, name); | |
9895 | fputs (",DATA\n", stream); | |
9896 | } | |
9897 | } | |
b8debbe8 | 9898 | |
6644435d | 9899 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
9900 | ||
b8debbe8 | 9901 | static rtx |
9902 | pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
9903 | int incoming ATTRIBUTE_UNUSED) | |
9904 | { | |
9905 | return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM); | |
9906 | } | |
9907 | ||
6644435d | 9908 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
9909 | ||
b8debbe8 | 9910 | bool |
fb80456a | 9911 | pa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
b8debbe8 | 9912 | { |
9913 | /* SOM ABI says that objects larger than 64 bits are returned in memory. | |
9914 | PA64 ABI says that objects larger than 128 bits are returned in memory. | |
9915 | Note, int_size_in_bytes can return -1 if the size of the object is | |
9916 | variable or larger than the maximum value that can be expressed as | |
9917 | a HOST_WIDE_INT. It can also return zero for an empty type. The | |
9918 | simplest way to handle variable and empty types is to pass them in | |
9919 | memory. This avoids problems in defining the boundaries of argument | |
9920 | slots, allocating registers, etc. */ | |
9921 | return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8) | |
9922 | || int_size_in_bytes (type) <= 0); | |
9923 | } | |
9924 | ||
5f43b4f6 | 9925 | /* Structure to hold declaration and name of external symbols that are |
9926 | emitted by GCC. We generate a vector of these symbols and output them | |
9927 | at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true. | |
9928 | This avoids putting out names that are never really used. */ | |
9929 | ||
fb1e4f4a | 9930 | typedef struct GTY(()) extern_symbol |
5f43b4f6 | 9931 | { |
9932 | tree decl; | |
9933 | const char *name; | |
046bfc77 | 9934 | } extern_symbol; |
5f43b4f6 | 9935 | |
9936 | /* Define gc'd vector type for extern_symbol. */ | |
046bfc77 | 9937 | DEF_VEC_O(extern_symbol); |
9938 | DEF_VEC_ALLOC_O(extern_symbol,gc); | |
5f43b4f6 | 9939 | |
9940 | /* Vector of extern_symbol pointers. */ | |
046bfc77 | 9941 | static GTY(()) VEC(extern_symbol,gc) *extern_symbols; |
5f43b4f6 | 9942 | |
9943 | #ifdef ASM_OUTPUT_EXTERNAL_REAL | |
9944 | /* Mark DECL (name NAME) as an external reference (assembler output | |
9945 | file FILE). This saves the names to output at the end of the file | |
9946 | if actually referenced. */ | |
9947 | ||
9948 | void | |
9949 | pa_hpux_asm_output_external (FILE *file, tree decl, const char *name) | |
9950 | { | |
046bfc77 | 9951 | extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL); |
5f43b4f6 | 9952 | |
9953 | gcc_assert (file == asm_out_file); | |
9954 | p->decl = decl; | |
9955 | p->name = name; | |
5f43b4f6 | 9956 | } |
9957 | ||
9958 | /* Output text required at the end of an assembler file. | |
9959 | This includes deferred plabels and .import directives for | |
9960 | all external symbols that were actually referenced. */ | |
9961 | ||
9962 | static void | |
9963 | pa_hpux_file_end (void) | |
9964 | { | |
9965 | unsigned int i; | |
046bfc77 | 9966 | extern_symbol *p; |
5f43b4f6 | 9967 | |
bb1bc2ca | 9968 | if (!NO_DEFERRED_PROFILE_COUNTERS) |
9969 | output_deferred_profile_counters (); | |
9970 | ||
5f43b4f6 | 9971 | output_deferred_plabels (); |
9972 | ||
9973 | for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++) | |
9974 | { | |
9975 | tree decl = p->decl; | |
9976 | ||
9977 | if (!TREE_ASM_WRITTEN (decl) | |
9978 | && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0))) | |
9979 | ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name); | |
9980 | } | |
9981 | ||
046bfc77 | 9982 | VEC_free (extern_symbol, gc, extern_symbols); |
5f43b4f6 | 9983 | } |
9984 | #endif | |
9985 | ||
7050ff73 | 9986 | /* Return true if a change from mode FROM to mode TO for a register |
8deb3959 | 9987 | in register class RCLASS is invalid. */ |
7050ff73 | 9988 | |
9989 | bool | |
9990 | pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to, | |
8deb3959 | 9991 | enum reg_class rclass) |
7050ff73 | 9992 | { |
9993 | if (from == to) | |
9994 | return false; | |
9995 | ||
9996 | /* Reject changes to/from complex and vector modes. */ | |
9997 | if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from) | |
9998 | || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to)) | |
9999 | return true; | |
10000 | ||
10001 | if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to)) | |
10002 | return false; | |
10003 | ||
10004 | /* There is no way to load QImode or HImode values directly from | |
10005 | memory. SImode loads to the FP registers are not zero extended. | |
10006 | On the 64-bit target, this conflicts with the definition of | |
10007 | LOAD_EXTEND_OP. Thus, we can't allow changing between modes | |
10008 | with different sizes in the floating-point registers. */ | |
8deb3959 | 10009 | if (MAYBE_FP_REG_CLASS_P (rclass)) |
7050ff73 | 10010 | return true; |
10011 | ||
10012 | /* HARD_REGNO_MODE_OK places modes with sizes larger than a word | |
10013 | in specific sets of registers. Thus, we cannot allow changing | |
10014 | to a larger mode when it's larger than a word. */ | |
10015 | if (GET_MODE_SIZE (to) > UNITS_PER_WORD | |
10016 | && GET_MODE_SIZE (to) > GET_MODE_SIZE (from)) | |
10017 | return true; | |
10018 | ||
10019 | return false; | |
10020 | } | |
10021 | ||
10022 | /* Returns TRUE if it is a good idea to tie two pseudo registers | |
10023 | when one has mode MODE1 and one has mode MODE2. | |
10024 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
10025 | for any hard reg, then this must be FALSE for correct output. | |
10026 | ||
10027 | We should return FALSE for QImode and HImode because these modes | |
10028 | are not ok in the floating-point registers. However, this prevents | |
10029 | tieing these modes to SImode and DImode in the general registers. | |
10030 | So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and | |
10031 | CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used | |
10032 | in the floating-point registers. */ | |
10033 | ||
10034 | bool | |
10035 | pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) | |
10036 | { | |
10037 | /* Don't tie modes in different classes. */ | |
10038 | if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2)) | |
10039 | return false; | |
10040 | ||
10041 | return true; | |
10042 | } | |
10043 | ||
623a97bc | 10044 | \f |
10045 | /* Length in units of the trampoline instruction code. */ | |
10046 | ||
10047 | #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40)) | |
10048 | ||
10049 | ||
10050 | /* Output assembler code for a block containing the constant parts | |
10051 | of a trampoline, leaving space for the variable parts.\ | |
10052 | ||
10053 | The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM | |
10054 | and then branches to the specified routine. | |
10055 | ||
10056 | This code template is copied from text segment to stack location | |
10057 | and then patched with pa_trampoline_init to contain valid values, | |
10058 | and then entered as a subroutine. | |
10059 | ||
10060 | It is best to keep this as small as possible to avoid having to | |
10061 | flush multiple lines in the cache. */ | |
10062 | ||
10063 | static void | |
10064 | pa_asm_trampoline_template (FILE *f) | |
10065 | { | |
10066 | if (!TARGET_64BIT) | |
10067 | { | |
10068 | fputs ("\tldw 36(%r22),%r21\n", f); | |
10069 | fputs ("\tbb,>=,n %r21,30,.+16\n", f); | |
10070 | if (ASSEMBLER_DIALECT == 0) | |
10071 | fputs ("\tdepi 0,31,2,%r21\n", f); | |
10072 | else | |
10073 | fputs ("\tdepwi 0,31,2,%r21\n", f); | |
10074 | fputs ("\tldw 4(%r21),%r19\n", f); | |
10075 | fputs ("\tldw 0(%r21),%r21\n", f); | |
10076 | if (TARGET_PA_20) | |
10077 | { | |
10078 | fputs ("\tbve (%r21)\n", f); | |
10079 | fputs ("\tldw 40(%r22),%r29\n", f); | |
10080 | fputs ("\t.word 0\n", f); | |
10081 | fputs ("\t.word 0\n", f); | |
10082 | } | |
10083 | else | |
10084 | { | |
10085 | fputs ("\tldsid (%r21),%r1\n", f); | |
10086 | fputs ("\tmtsp %r1,%sr0\n", f); | |
10087 | fputs ("\tbe 0(%sr0,%r21)\n", f); | |
10088 | fputs ("\tldw 40(%r22),%r29\n", f); | |
10089 | } | |
10090 | fputs ("\t.word 0\n", f); | |
10091 | fputs ("\t.word 0\n", f); | |
10092 | fputs ("\t.word 0\n", f); | |
10093 | fputs ("\t.word 0\n", f); | |
10094 | } | |
10095 | else | |
10096 | { | |
10097 | fputs ("\t.dword 0\n", f); | |
10098 | fputs ("\t.dword 0\n", f); | |
10099 | fputs ("\t.dword 0\n", f); | |
10100 | fputs ("\t.dword 0\n", f); | |
10101 | fputs ("\tmfia %r31\n", f); | |
10102 | fputs ("\tldd 24(%r31),%r1\n", f); | |
10103 | fputs ("\tldd 24(%r1),%r27\n", f); | |
10104 | fputs ("\tldd 16(%r1),%r1\n", f); | |
10105 | fputs ("\tbve (%r1)\n", f); | |
10106 | fputs ("\tldd 32(%r31),%r31\n", f); | |
10107 | fputs ("\t.dword 0 ; fptr\n", f); | |
10108 | fputs ("\t.dword 0 ; static link\n", f); | |
10109 | } | |
10110 | } | |
10111 | ||
10112 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
10113 | FNADDR is an RTX for the address of the function's pure code. | |
10114 | CXT is an RTX for the static chain value for the function. | |
10115 | ||
10116 | Move the function address to the trampoline template at offset 36. | |
10117 | Move the static chain value to trampoline template at offset 40. | |
10118 | Move the trampoline address to trampoline template at offset 44. | |
10119 | Move r19 to trampoline template at offset 48. The latter two | |
10120 | words create a plabel for the indirect call to the trampoline. | |
10121 | ||
10122 | A similar sequence is used for the 64-bit port but the plabel is | |
10123 | at the beginning of the trampoline. | |
10124 | ||
10125 | Finally, the cache entries for the trampoline code are flushed. | |
10126 | This is necessary to ensure that the trampoline instruction sequence | |
10127 | is written to memory prior to any attempts at prefetching the code | |
10128 | sequence. */ | |
10129 | ||
10130 | static void | |
10131 | pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
10132 | { | |
10133 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
10134 | rtx start_addr = gen_reg_rtx (Pmode); | |
10135 | rtx end_addr = gen_reg_rtx (Pmode); | |
10136 | rtx line_length = gen_reg_rtx (Pmode); | |
10137 | rtx r_tramp, tmp; | |
10138 | ||
10139 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
10140 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
10141 | r_tramp = force_reg (Pmode, XEXP (m_tramp, 0)); | |
10142 | ||
10143 | if (!TARGET_64BIT) | |
10144 | { | |
10145 | tmp = adjust_address (m_tramp, Pmode, 36); | |
10146 | emit_move_insn (tmp, fnaddr); | |
10147 | tmp = adjust_address (m_tramp, Pmode, 40); | |
10148 | emit_move_insn (tmp, chain_value); | |
10149 | ||
10150 | /* Create a fat pointer for the trampoline. */ | |
10151 | tmp = adjust_address (m_tramp, Pmode, 44); | |
10152 | emit_move_insn (tmp, r_tramp); | |
10153 | tmp = adjust_address (m_tramp, Pmode, 48); | |
10154 | emit_move_insn (tmp, gen_rtx_REG (Pmode, 19)); | |
10155 | ||
10156 | /* fdc and fic only use registers for the address to flush, | |
10157 | they do not accept integer displacements. We align the | |
10158 | start and end addresses to the beginning of their respective | |
10159 | cache lines to minimize the number of lines flushed. */ | |
10160 | emit_insn (gen_andsi3 (start_addr, r_tramp, | |
10161 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
29c05e22 | 10162 | tmp = force_reg (Pmode, plus_constant (Pmode, r_tramp, |
10163 | TRAMPOLINE_CODE_SIZE-1)); | |
623a97bc | 10164 | emit_insn (gen_andsi3 (end_addr, tmp, |
10165 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
10166 | emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); | |
10167 | emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length)); | |
10168 | emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length, | |
10169 | gen_reg_rtx (Pmode), | |
10170 | gen_reg_rtx (Pmode))); | |
10171 | } | |
10172 | else | |
10173 | { | |
10174 | tmp = adjust_address (m_tramp, Pmode, 56); | |
10175 | emit_move_insn (tmp, fnaddr); | |
10176 | tmp = adjust_address (m_tramp, Pmode, 64); | |
10177 | emit_move_insn (tmp, chain_value); | |
10178 | ||
10179 | /* Create a fat pointer for the trampoline. */ | |
10180 | tmp = adjust_address (m_tramp, Pmode, 16); | |
29c05e22 | 10181 | emit_move_insn (tmp, force_reg (Pmode, plus_constant (Pmode, |
10182 | r_tramp, 32))); | |
623a97bc | 10183 | tmp = adjust_address (m_tramp, Pmode, 24); |
10184 | emit_move_insn (tmp, gen_rtx_REG (Pmode, 27)); | |
10185 | ||
10186 | /* fdc and fic only use registers for the address to flush, | |
10187 | they do not accept integer displacements. We align the | |
10188 | start and end addresses to the beginning of their respective | |
10189 | cache lines to minimize the number of lines flushed. */ | |
29c05e22 | 10190 | tmp = force_reg (Pmode, plus_constant (Pmode, r_tramp, 32)); |
623a97bc | 10191 | emit_insn (gen_anddi3 (start_addr, tmp, |
10192 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
29c05e22 | 10193 | tmp = force_reg (Pmode, plus_constant (Pmode, tmp, |
10194 | TRAMPOLINE_CODE_SIZE - 1)); | |
623a97bc | 10195 | emit_insn (gen_anddi3 (end_addr, tmp, |
10196 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
10197 | emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); | |
10198 | emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length)); | |
10199 | emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length, | |
10200 | gen_reg_rtx (Pmode), | |
10201 | gen_reg_rtx (Pmode))); | |
10202 | } | |
10203 | } | |
10204 | ||
10205 | /* Perform any machine-specific adjustment in the address of the trampoline. | |
10206 | ADDR contains the address that was passed to pa_trampoline_init. | |
10207 | Adjust the trampoline address to point to the plabel at offset 44. */ | |
10208 | ||
10209 | static rtx | |
10210 | pa_trampoline_adjust_address (rtx addr) | |
10211 | { | |
10212 | if (!TARGET_64BIT) | |
29c05e22 | 10213 | addr = memory_address (Pmode, plus_constant (Pmode, addr, 46)); |
623a97bc | 10214 | return addr; |
10215 | } | |
c731c4f5 | 10216 | |
10217 | static rtx | |
10218 | pa_delegitimize_address (rtx orig_x) | |
10219 | { | |
10220 | rtx x = delegitimize_mem_from_attrs (orig_x); | |
10221 | ||
10222 | if (GET_CODE (x) == LO_SUM | |
10223 | && GET_CODE (XEXP (x, 1)) == UNSPEC | |
10224 | && XINT (XEXP (x, 1), 1) == UNSPEC_DLTIND14R) | |
10225 | return gen_const_mem (Pmode, XVECEXP (XEXP (x, 1), 0, 0)); | |
10226 | return x; | |
10227 | } | |
623a97bc | 10228 | \f |
68bc9ae6 | 10229 | static rtx |
10230 | pa_internal_arg_pointer (void) | |
10231 | { | |
10232 | /* The argument pointer and the hard frame pointer are the same in | |
10233 | the 32-bit runtime, so we don't need a copy. */ | |
10234 | if (TARGET_64BIT) | |
10235 | return copy_to_reg (virtual_incoming_args_rtx); | |
10236 | else | |
10237 | return virtual_incoming_args_rtx; | |
10238 | } | |
10239 | ||
10240 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
10241 | Frame pointer elimination is automatically handled. */ | |
10242 | ||
10243 | static bool | |
10244 | pa_can_eliminate (const int from, const int to) | |
10245 | { | |
10246 | /* The argument cannot be eliminated in the 64-bit runtime. */ | |
10247 | if (TARGET_64BIT && from == ARG_POINTER_REGNUM) | |
10248 | return false; | |
10249 | ||
10250 | return (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM | |
10251 | ? ! frame_pointer_needed | |
10252 | : true); | |
10253 | } | |
10254 | ||
10255 | /* Define the offset between two registers, FROM to be eliminated and its | |
10256 | replacement TO, at the start of a routine. */ | |
10257 | HOST_WIDE_INT | |
10258 | pa_initial_elimination_offset (int from, int to) | |
10259 | { | |
10260 | HOST_WIDE_INT offset; | |
10261 | ||
10262 | if ((from == HARD_FRAME_POINTER_REGNUM || from == FRAME_POINTER_REGNUM) | |
10263 | && to == STACK_POINTER_REGNUM) | |
e202682d | 10264 | offset = -pa_compute_frame_size (get_frame_size (), 0); |
68bc9ae6 | 10265 | else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) |
10266 | offset = 0; | |
10267 | else | |
10268 | gcc_unreachable (); | |
10269 | ||
10270 | return offset; | |
10271 | } | |
10272 | ||
b2d7ede1 | 10273 | static void |
10274 | pa_conditional_register_usage (void) | |
10275 | { | |
10276 | int i; | |
10277 | ||
10278 | if (!TARGET_64BIT && !TARGET_PA_11) | |
10279 | { | |
10280 | for (i = 56; i <= FP_REG_LAST; i++) | |
10281 | fixed_regs[i] = call_used_regs[i] = 1; | |
10282 | for (i = 33; i < 56; i += 2) | |
10283 | fixed_regs[i] = call_used_regs[i] = 1; | |
10284 | } | |
10285 | if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT) | |
10286 | { | |
10287 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
10288 | fixed_regs[i] = call_used_regs[i] = 1; | |
10289 | } | |
10290 | if (flag_pic) | |
10291 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
10292 | } | |
10293 | ||
0f9c87cc | 10294 | /* Target hook for c_mode_for_suffix. */ |
10295 | ||
10296 | static enum machine_mode | |
10297 | pa_c_mode_for_suffix (char suffix) | |
10298 | { | |
10299 | if (HPUX_LONG_DOUBLE_LIBRARY) | |
10300 | { | |
10301 | if (suffix == 'q') | |
10302 | return TFmode; | |
10303 | } | |
10304 | ||
10305 | return VOIDmode; | |
10306 | } | |
10307 | ||
c9b4a514 | 10308 | /* Target hook for function_section. */ |
10309 | ||
10310 | static section * | |
10311 | pa_function_section (tree decl, enum node_frequency freq, | |
10312 | bool startup, bool exit) | |
10313 | { | |
10314 | /* Put functions in text section if target doesn't have named sections. */ | |
218e3e4e | 10315 | if (!targetm_common.have_named_sections) |
c9b4a514 | 10316 | return text_section; |
10317 | ||
10318 | /* Force nested functions into the same section as the containing | |
10319 | function. */ | |
10320 | if (decl | |
10321 | && DECL_SECTION_NAME (decl) == NULL_TREE | |
10322 | && DECL_CONTEXT (decl) != NULL_TREE | |
10323 | && TREE_CODE (DECL_CONTEXT (decl)) == FUNCTION_DECL | |
10324 | && DECL_SECTION_NAME (DECL_CONTEXT (decl)) == NULL_TREE) | |
10325 | return function_section (DECL_CONTEXT (decl)); | |
10326 | ||
10327 | /* Otherwise, use the default function section. */ | |
10328 | return default_function_section (decl, freq, startup, exit); | |
10329 | } | |
10330 | ||
ca316360 | 10331 | /* Implement TARGET_LEGITIMATE_CONSTANT_P. |
10332 | ||
10333 | In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS | |
10334 | that need more than three instructions to load prior to reload. This | |
10335 | limit is somewhat arbitrary. It takes three instructions to load a | |
10336 | CONST_INT from memory but two are memory accesses. It may be better | |
10337 | to increase the allowed range for CONST_INTS. We may also be able | |
10338 | to handle CONST_DOUBLES. */ | |
10339 | ||
10340 | static bool | |
10341 | pa_legitimate_constant_p (enum machine_mode mode, rtx x) | |
10342 | { | |
10343 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && x != CONST0_RTX (mode)) | |
10344 | return false; | |
10345 | ||
10346 | if (!NEW_HP_ASSEMBLER && !TARGET_GAS && GET_CODE (x) == LABEL_REF) | |
10347 | return false; | |
10348 | ||
f784d2ac | 10349 | /* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not |
10350 | legitimate constants. */ | |
10351 | if (PA_SYMBOL_REF_TLS_P (x)) | |
10352 | { | |
10353 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
10354 | ||
10355 | if (model == TLS_MODEL_GLOBAL_DYNAMIC || model == TLS_MODEL_LOCAL_DYNAMIC) | |
10356 | return false; | |
10357 | } | |
10358 | ||
ca316360 | 10359 | if (TARGET_64BIT && GET_CODE (x) == CONST_DOUBLE) |
10360 | return false; | |
10361 | ||
10362 | if (TARGET_64BIT | |
10363 | && HOST_BITS_PER_WIDE_INT > 32 | |
10364 | && GET_CODE (x) == CONST_INT | |
10365 | && !reload_in_progress | |
10366 | && !reload_completed | |
10367 | && !LEGITIMATE_64BIT_CONST_INT_P (INTVAL (x)) | |
e202682d | 10368 | && !pa_cint_ok_for_move (INTVAL (x))) |
ca316360 | 10369 | return false; |
10370 | ||
7949e3eb | 10371 | if (function_label_operand (x, mode)) |
10372 | return false; | |
10373 | ||
ca316360 | 10374 | return true; |
10375 | } | |
10376 | ||
7949e3eb | 10377 | /* Implement TARGET_SECTION_TYPE_FLAGS. */ |
10378 | ||
10379 | static unsigned int | |
10380 | pa_section_type_flags (tree decl, const char *name, int reloc) | |
10381 | { | |
10382 | unsigned int flags; | |
10383 | ||
10384 | flags = default_section_type_flags (decl, name, reloc); | |
10385 | ||
10386 | /* Function labels are placed in the constant pool. This can | |
10387 | cause a section conflict if decls are put in ".data.rel.ro" | |
10388 | or ".data.rel.ro.local" using the __attribute__ construct. */ | |
10389 | if (strcmp (name, ".data.rel.ro") == 0 | |
10390 | || strcmp (name, ".data.rel.ro.local") == 0) | |
10391 | flags |= SECTION_WRITE | SECTION_RELRO; | |
10392 | ||
10393 | return flags; | |
10394 | } | |
10395 | ||
1f3233d1 | 10396 | #include "gt-pa.h" |