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87ad11b0 | 1 | /* Subroutines for insn-output.c for HPPA. |
a9ac13e4 | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
fba5dd52 | 3 | 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
cfaf579d | 4 | Free Software Foundation, Inc. |
87ad11b0 | 5 | Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c |
6 | ||
5c1d8983 | 7 | This file is part of GCC. |
87ad11b0 | 8 | |
5c1d8983 | 9 | GCC is free software; you can redistribute it and/or modify |
87ad11b0 | 10 | it under the terms of the GNU General Public License as published by |
038d1e19 | 11 | the Free Software Foundation; either version 3, or (at your option) |
87ad11b0 | 12 | any later version. |
13 | ||
5c1d8983 | 14 | GCC is distributed in the hope that it will be useful, |
87ad11b0 | 15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
038d1e19 | 20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
87ad11b0 | 22 | |
87ad11b0 | 23 | #include "config.h" |
b1ca791d | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
87ad11b0 | 27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
87ad11b0 | 30 | #include "insn-config.h" |
31 | #include "conditions.h" | |
87ad11b0 | 32 | #include "insn-attr.h" |
33 | #include "flags.h" | |
34 | #include "tree.h" | |
9d2d8bd6 | 35 | #include "output.h" |
a584fe8a | 36 | #include "except.h" |
32509e56 | 37 | #include "expr.h" |
d8fc4d0b | 38 | #include "optabs.h" |
d8fc4d0b | 39 | #include "reload.h" |
d7e2f694 | 40 | #include "integrate.h" |
0a893c29 | 41 | #include "function.h" |
0b205f4c | 42 | #include "diagnostic-core.h" |
5cb4669a | 43 | #include "ggc.h" |
611a88e1 | 44 | #include "recog.h" |
a584fe8a | 45 | #include "predict.h" |
611a88e1 | 46 | #include "tm_p.h" |
a767736d | 47 | #include "target.h" |
218e3e4e | 48 | #include "common/common-target.h" |
a767736d | 49 | #include "target-def.h" |
0f9c87cc | 50 | #include "langhooks.h" |
a179d6b2 | 51 | #include "df.h" |
fba5dd52 | 52 | #include "opts.h" |
87ad11b0 | 53 | |
cde3e16c | 54 | /* Return nonzero if there is a bypass for the output of |
55 | OUT_INSN and the fp store IN_INSN. */ | |
56 | int | |
5c1d8983 | 57 | hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn) |
cde3e16c | 58 | { |
59 | enum machine_mode store_mode; | |
60 | enum machine_mode other_mode; | |
61 | rtx set; | |
62 | ||
63 | if (recog_memoized (in_insn) < 0 | |
7d9f62cc | 64 | || (get_attr_type (in_insn) != TYPE_FPSTORE |
65 | && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD) | |
cde3e16c | 66 | || recog_memoized (out_insn) < 0) |
67 | return 0; | |
68 | ||
69 | store_mode = GET_MODE (SET_SRC (PATTERN (in_insn))); | |
70 | ||
71 | set = single_set (out_insn); | |
72 | if (!set) | |
73 | return 0; | |
74 | ||
75 | other_mode = GET_MODE (SET_SRC (set)); | |
76 | ||
77 | return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode)); | |
78 | } | |
79 | ||
80 | ||
cc858176 | 81 | #ifndef DO_FRAME_NOTES |
82 | #ifdef INCOMING_RETURN_ADDR_RTX | |
83 | #define DO_FRAME_NOTES 1 | |
84 | #else | |
85 | #define DO_FRAME_NOTES 0 | |
86 | #endif | |
87 | #endif | |
88 | ||
93d3ee56 | 89 | static void pa_option_override (void); |
dbd3d89d | 90 | static void copy_reg_pointer (rtx, rtx); |
320e1276 | 91 | static void fix_range (const char *); |
93d3ee56 | 92 | static int hppa_register_move_cost (enum machine_mode mode, reg_class_t, |
93 | reg_class_t); | |
f529eb25 | 94 | static int hppa_address_cost (rtx, bool); |
20d892d1 | 95 | static bool hppa_rtx_costs (rtx, int, int, int, int *, bool); |
5c1d8983 | 96 | static inline rtx force_mode (enum machine_mode, rtx); |
97 | static void pa_reorg (void); | |
98 | static void pa_combine_instructions (void); | |
99 | static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx); | |
372b3fe2 | 100 | static bool forward_branch_p (rtx); |
5c1d8983 | 101 | static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *); |
008c057d | 102 | static int compute_movmem_length (rtx); |
103 | static int compute_clrmem_length (rtx); | |
5c1d8983 | 104 | static bool pa_assemble_integer (rtx, unsigned int, int); |
105 | static void remove_useless_addtr_insns (int); | |
6bcdc1fb | 106 | static void store_reg (int, HOST_WIDE_INT, int); |
107 | static void store_reg_modify (int, int, HOST_WIDE_INT); | |
108 | static void load_reg (int, HOST_WIDE_INT, int); | |
109 | static void set_reg_plus_d (int, int, HOST_WIDE_INT, int); | |
cb0b8817 | 110 | static rtx pa_function_value (const_tree, const_tree, bool); |
93d3ee56 | 111 | static rtx pa_libcall_value (enum machine_mode, const_rtx); |
112 | static bool pa_function_value_regno_p (const unsigned int); | |
5c1d8983 | 113 | static void pa_output_function_prologue (FILE *, HOST_WIDE_INT); |
21a47bc9 | 114 | static void update_total_code_bytes (unsigned int); |
5c1d8983 | 115 | static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT); |
116 | static int pa_adjust_cost (rtx, rtx, rtx, int); | |
117 | static int pa_adjust_priority (rtx, int); | |
118 | static int pa_issue_rate (void); | |
2f14b1f9 | 119 | static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED; |
120 | static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT) | |
52470889 | 121 | ATTRIBUTE_UNUSED; |
5c1d8983 | 122 | static void pa_encode_section_info (tree, rtx, int); |
123 | static const char *pa_strip_name_encoding (const char *); | |
124 | static bool pa_function_ok_for_sibcall (tree, tree); | |
125 | static void pa_globalize_label (FILE *, const char *) | |
63b8cd48 | 126 | ATTRIBUTE_UNUSED; |
5c1d8983 | 127 | static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
128 | HOST_WIDE_INT, tree); | |
de419443 | 129 | #if !defined(USE_COLLECT2) |
5c1d8983 | 130 | static void pa_asm_out_constructor (rtx, int); |
131 | static void pa_asm_out_destructor (rtx, int); | |
de419443 | 132 | #endif |
5c1d8983 | 133 | static void pa_init_builtins (void); |
0f9c87cc | 134 | static rtx pa_expand_builtin (tree, rtx, rtx, enum machine_mode mode, int); |
b8debbe8 | 135 | static rtx hppa_builtin_saveregs (void); |
8a58ed0a | 136 | static void hppa_va_start (tree, rtx); |
75a70cf9 | 137 | static tree hppa_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *); |
2b1e7cc3 | 138 | static bool pa_scalar_mode_supported_p (enum machine_mode); |
a9f1838b | 139 | static bool pa_commutative_p (const_rtx x, int outer_code); |
5c1d8983 | 140 | static void copy_fp_args (rtx) ATTRIBUTE_UNUSED; |
141 | static int length_fp_args (rtx) ATTRIBUTE_UNUSED; | |
41e3a0c7 | 142 | static rtx hppa_legitimize_address (rtx, rtx, enum machine_mode); |
5c1d8983 | 143 | static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED; |
144 | static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED; | |
145 | static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED; | |
146 | static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED; | |
147 | static void pa_elf_file_start (void) ATTRIBUTE_UNUSED; | |
148 | static void pa_som_file_start (void) ATTRIBUTE_UNUSED; | |
149 | static void pa_linux_file_start (void) ATTRIBUTE_UNUSED; | |
150 | static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED; | |
151 | static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED; | |
152 | static void output_deferred_plabels (void); | |
bb1bc2ca | 153 | static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED; |
5f43b4f6 | 154 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
155 | static void pa_hpux_file_end (void); | |
156 | #endif | |
0f9c87cc | 157 | #if HPUX_LONG_DOUBLE_LIBRARY |
f2f543a3 | 158 | static void pa_hpux_init_libfuncs (void); |
159 | #endif | |
b8debbe8 | 160 | static rtx pa_struct_value_rtx (tree, int); |
39cba157 | 161 | static bool pa_pass_by_reference (cumulative_args_t, enum machine_mode, |
fb80456a | 162 | const_tree, bool); |
39cba157 | 163 | static int pa_arg_partial_bytes (cumulative_args_t, enum machine_mode, |
f054eb3c | 164 | tree, bool); |
39cba157 | 165 | static void pa_function_arg_advance (cumulative_args_t, enum machine_mode, |
8b4bd662 | 166 | const_tree, bool); |
39cba157 | 167 | static rtx pa_function_arg (cumulative_args_t, enum machine_mode, |
8b4bd662 | 168 | const_tree, bool); |
bd99ba64 | 169 | static unsigned int pa_function_arg_boundary (enum machine_mode, const_tree); |
916c9cef | 170 | static struct machine_function * pa_init_machine_status (void); |
964229b7 | 171 | static reg_class_t pa_secondary_reload (bool, rtx, reg_class_t, |
172 | enum machine_mode, | |
173 | secondary_reload_info *); | |
df6b92e4 | 174 | static void pa_extra_live_on_entry (bitmap); |
15a27966 | 175 | static enum machine_mode pa_promote_function_mode (const_tree, |
176 | enum machine_mode, int *, | |
177 | const_tree, int); | |
9d3ddb8f | 178 | |
623a97bc | 179 | static void pa_asm_trampoline_template (FILE *); |
180 | static void pa_trampoline_init (rtx, tree, rtx); | |
181 | static rtx pa_trampoline_adjust_address (rtx); | |
c731c4f5 | 182 | static rtx pa_delegitimize_address (rtx); |
93d3ee56 | 183 | static bool pa_print_operand_punct_valid_p (unsigned char); |
68bc9ae6 | 184 | static rtx pa_internal_arg_pointer (void); |
185 | static bool pa_can_eliminate (const int, const int); | |
b2d7ede1 | 186 | static void pa_conditional_register_usage (void); |
0f9c87cc | 187 | static enum machine_mode pa_c_mode_for_suffix (char); |
c9b4a514 | 188 | static section *pa_function_section (tree, enum node_frequency, bool, bool); |
7d7d7bd2 | 189 | static bool pa_cannot_force_const_mem (enum machine_mode, rtx); |
ca316360 | 190 | static bool pa_legitimate_constant_p (enum machine_mode, rtx); |
623a97bc | 191 | |
2f14b1f9 | 192 | /* The following extra sections are only used for SOM. */ |
193 | static GTY(()) section *som_readonly_data_section; | |
194 | static GTY(()) section *som_one_only_readonly_data_section; | |
195 | static GTY(()) section *som_one_only_data_section; | |
196 | ||
a9960cdc | 197 | /* Counts for the number of callee-saved general and floating point |
198 | registers which were saved by the current function's prologue. */ | |
199 | static int gr_saved, fr_saved; | |
200 | ||
df6b92e4 | 201 | /* Boolean indicating whether the return pointer was saved by the |
202 | current function's prologue. */ | |
203 | static bool rp_saved; | |
204 | ||
5c1d8983 | 205 | static rtx find_addr_reg (rtx); |
87ad11b0 | 206 | |
2247cc5f | 207 | /* Keep track of the number of bytes we have output in the CODE subspace |
06ddb6f8 | 208 | during this compilation so we'll know when to emit inline long-calls. */ |
ece88821 | 209 | unsigned long total_code_bytes; |
06ddb6f8 | 210 | |
2247cc5f | 211 | /* The last address of the previous function plus the number of bytes in |
212 | associated thunks that have been output. This is used to determine if | |
213 | a thunk can use an IA-relative branch to reach its target function. */ | |
21a47bc9 | 214 | static unsigned int last_address; |
2247cc5f | 215 | |
e3f53689 | 216 | /* Variables to handle plabels that we discover are necessary at assembly |
01cc3b75 | 217 | output time. They are output after the current function. */ |
fb1e4f4a | 218 | struct GTY(()) deferred_plabel |
e3f53689 | 219 | { |
220 | rtx internal_label; | |
5f43b4f6 | 221 | rtx symbol; |
1f3233d1 | 222 | }; |
223 | static GTY((length ("n_deferred_plabels"))) struct deferred_plabel * | |
224 | deferred_plabels; | |
e11bd7e5 | 225 | static size_t n_deferred_plabels = 0; |
a767736d | 226 | \f |
227 | /* Initialize the GCC target structure. */ | |
58356836 | 228 | |
93d3ee56 | 229 | #undef TARGET_OPTION_OVERRIDE |
230 | #define TARGET_OPTION_OVERRIDE pa_option_override | |
231 | ||
58356836 | 232 | #undef TARGET_ASM_ALIGNED_HI_OP |
233 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
234 | #undef TARGET_ASM_ALIGNED_SI_OP | |
235 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
236 | #undef TARGET_ASM_ALIGNED_DI_OP | |
237 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
238 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
239 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
240 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
241 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
242 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
243 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
244 | #undef TARGET_ASM_INTEGER | |
245 | #define TARGET_ASM_INTEGER pa_assemble_integer | |
246 | ||
17d9b0c3 | 247 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
248 | #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue | |
249 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
250 | #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue | |
e3f53689 | 251 | |
cb0b8817 | 252 | #undef TARGET_FUNCTION_VALUE |
253 | #define TARGET_FUNCTION_VALUE pa_function_value | |
93d3ee56 | 254 | #undef TARGET_LIBCALL_VALUE |
255 | #define TARGET_LIBCALL_VALUE pa_libcall_value | |
256 | #undef TARGET_FUNCTION_VALUE_REGNO_P | |
257 | #define TARGET_FUNCTION_VALUE_REGNO_P pa_function_value_regno_p | |
cb0b8817 | 258 | |
41e3a0c7 | 259 | #undef TARGET_LEGITIMIZE_ADDRESS |
260 | #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address | |
261 | ||
747af5e7 | 262 | #undef TARGET_SCHED_ADJUST_COST |
263 | #define TARGET_SCHED_ADJUST_COST pa_adjust_cost | |
264 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
265 | #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority | |
266 | #undef TARGET_SCHED_ISSUE_RATE | |
267 | #define TARGET_SCHED_ISSUE_RATE pa_issue_rate | |
268 | ||
7811991d | 269 | #undef TARGET_ENCODE_SECTION_INFO |
270 | #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info | |
7b4a38a6 | 271 | #undef TARGET_STRIP_NAME_ENCODING |
272 | #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding | |
7811991d | 273 | |
805e22b2 | 274 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
275 | #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall | |
276 | ||
280566a7 | 277 | #undef TARGET_COMMUTATIVE_P |
278 | #define TARGET_COMMUTATIVE_P pa_commutative_p | |
279 | ||
6988553d | 280 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
281 | #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk | |
eb344f43 | 282 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
283 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
6988553d | 284 | |
f6940372 | 285 | #undef TARGET_ASM_FILE_END |
5f43b4f6 | 286 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
287 | #define TARGET_ASM_FILE_END pa_hpux_file_end | |
288 | #else | |
f6940372 | 289 | #define TARGET_ASM_FILE_END output_deferred_plabels |
5f43b4f6 | 290 | #endif |
f6940372 | 291 | |
93d3ee56 | 292 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P |
293 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pa_print_operand_punct_valid_p | |
294 | ||
de419443 | 295 | #if !defined(USE_COLLECT2) |
296 | #undef TARGET_ASM_CONSTRUCTOR | |
297 | #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor | |
298 | #undef TARGET_ASM_DESTRUCTOR | |
299 | #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor | |
300 | #endif | |
301 | ||
ffa8918b | 302 | #undef TARGET_INIT_BUILTINS |
303 | #define TARGET_INIT_BUILTINS pa_init_builtins | |
304 | ||
0f9c87cc | 305 | #undef TARGET_EXPAND_BUILTIN |
306 | #define TARGET_EXPAND_BUILTIN pa_expand_builtin | |
307 | ||
93d3ee56 | 308 | #undef TARGET_REGISTER_MOVE_COST |
309 | #define TARGET_REGISTER_MOVE_COST hppa_register_move_cost | |
fab7adbf | 310 | #undef TARGET_RTX_COSTS |
311 | #define TARGET_RTX_COSTS hppa_rtx_costs | |
ec0457a8 | 312 | #undef TARGET_ADDRESS_COST |
313 | #define TARGET_ADDRESS_COST hppa_address_cost | |
fab7adbf | 314 | |
2efea8c0 | 315 | #undef TARGET_MACHINE_DEPENDENT_REORG |
316 | #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg | |
317 | ||
0f9c87cc | 318 | #if HPUX_LONG_DOUBLE_LIBRARY |
f2f543a3 | 319 | #undef TARGET_INIT_LIBFUNCS |
320 | #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs | |
321 | #endif | |
322 | ||
3b2411a8 | 323 | #undef TARGET_PROMOTE_FUNCTION_MODE |
324 | #define TARGET_PROMOTE_FUNCTION_MODE pa_promote_function_mode | |
b8debbe8 | 325 | #undef TARGET_PROMOTE_PROTOTYPES |
fb80456a | 326 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true |
b8debbe8 | 327 | |
328 | #undef TARGET_STRUCT_VALUE_RTX | |
329 | #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx | |
330 | #undef TARGET_RETURN_IN_MEMORY | |
331 | #define TARGET_RETURN_IN_MEMORY pa_return_in_memory | |
0336f0f0 | 332 | #undef TARGET_MUST_PASS_IN_STACK |
333 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
b981d932 | 334 | #undef TARGET_PASS_BY_REFERENCE |
335 | #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference | |
13f08ee7 | 336 | #undef TARGET_CALLEE_COPIES |
337 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
f054eb3c | 338 | #undef TARGET_ARG_PARTIAL_BYTES |
339 | #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes | |
8b4bd662 | 340 | #undef TARGET_FUNCTION_ARG |
341 | #define TARGET_FUNCTION_ARG pa_function_arg | |
342 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
343 | #define TARGET_FUNCTION_ARG_ADVANCE pa_function_arg_advance | |
bd99ba64 | 344 | #undef TARGET_FUNCTION_ARG_BOUNDARY |
345 | #define TARGET_FUNCTION_ARG_BOUNDARY pa_function_arg_boundary | |
b8debbe8 | 346 | |
347 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
348 | #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs | |
8a58ed0a | 349 | #undef TARGET_EXPAND_BUILTIN_VA_START |
350 | #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start | |
4c33eb68 | 351 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
352 | #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr | |
b8debbe8 | 353 | |
2b1e7cc3 | 354 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
355 | #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p | |
356 | ||
716b2c5a | 357 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
7d7d7bd2 | 358 | #define TARGET_CANNOT_FORCE_CONST_MEM pa_cannot_force_const_mem |
716b2c5a | 359 | |
5655a0e5 | 360 | #undef TARGET_SECONDARY_RELOAD |
361 | #define TARGET_SECONDARY_RELOAD pa_secondary_reload | |
362 | ||
df6b92e4 | 363 | #undef TARGET_EXTRA_LIVE_ON_ENTRY |
364 | #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry | |
365 | ||
623a97bc | 366 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
367 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE pa_asm_trampoline_template | |
368 | #undef TARGET_TRAMPOLINE_INIT | |
369 | #define TARGET_TRAMPOLINE_INIT pa_trampoline_init | |
370 | #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS | |
371 | #define TARGET_TRAMPOLINE_ADJUST_ADDRESS pa_trampoline_adjust_address | |
c731c4f5 | 372 | #undef TARGET_DELEGITIMIZE_ADDRESS |
373 | #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address | |
68bc9ae6 | 374 | #undef TARGET_INTERNAL_ARG_POINTER |
375 | #define TARGET_INTERNAL_ARG_POINTER pa_internal_arg_pointer | |
376 | #undef TARGET_CAN_ELIMINATE | |
377 | #define TARGET_CAN_ELIMINATE pa_can_eliminate | |
b2d7ede1 | 378 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
379 | #define TARGET_CONDITIONAL_REGISTER_USAGE pa_conditional_register_usage | |
0f9c87cc | 380 | #undef TARGET_C_MODE_FOR_SUFFIX |
381 | #define TARGET_C_MODE_FOR_SUFFIX pa_c_mode_for_suffix | |
c9b4a514 | 382 | #undef TARGET_ASM_FUNCTION_SECTION |
383 | #define TARGET_ASM_FUNCTION_SECTION pa_function_section | |
623a97bc | 384 | |
ca316360 | 385 | #undef TARGET_LEGITIMATE_CONSTANT_P |
386 | #define TARGET_LEGITIMATE_CONSTANT_P pa_legitimate_constant_p | |
387 | ||
57e4bbfb | 388 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 389 | \f |
320e1276 | 390 | /* Parse the -mfixed-range= option string. */ |
391 | ||
392 | static void | |
393 | fix_range (const char *const_str) | |
394 | { | |
395 | int i, first, last; | |
396 | char *str, *dash, *comma; | |
397 | ||
398 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and | |
399 | REG2 are either register names or register numbers. The effect | |
400 | of this option is to mark the registers in the range from REG1 to | |
401 | REG2 as ``fixed'' so they won't be used by the compiler. This is | |
765cebfc | 402 | used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */ |
320e1276 | 403 | |
404 | i = strlen (const_str); | |
405 | str = (char *) alloca (i + 1); | |
406 | memcpy (str, const_str, i + 1); | |
407 | ||
408 | while (1) | |
409 | { | |
410 | dash = strchr (str, '-'); | |
411 | if (!dash) | |
412 | { | |
c3ceba8e | 413 | warning (0, "value of -mfixed-range must have form REG1-REG2"); |
320e1276 | 414 | return; |
415 | } | |
416 | *dash = '\0'; | |
417 | ||
418 | comma = strchr (dash + 1, ','); | |
419 | if (comma) | |
420 | *comma = '\0'; | |
421 | ||
422 | first = decode_reg_name (str); | |
423 | if (first < 0) | |
424 | { | |
c3ceba8e | 425 | warning (0, "unknown register name: %s", str); |
320e1276 | 426 | return; |
427 | } | |
428 | ||
429 | last = decode_reg_name (dash + 1); | |
430 | if (last < 0) | |
431 | { | |
c3ceba8e | 432 | warning (0, "unknown register name: %s", dash + 1); |
320e1276 | 433 | return; |
434 | } | |
435 | ||
436 | *dash = '-'; | |
437 | ||
438 | if (first > last) | |
439 | { | |
c3ceba8e | 440 | warning (0, "%s-%s is an empty range", str, dash + 1); |
320e1276 | 441 | return; |
442 | } | |
443 | ||
444 | for (i = first; i <= last; ++i) | |
445 | fixed_regs[i] = call_used_regs[i] = 1; | |
446 | ||
447 | if (!comma) | |
448 | break; | |
449 | ||
450 | *comma = ','; | |
451 | str = comma + 1; | |
452 | } | |
453 | ||
454 | /* Check if all floating point registers have been fixed. */ | |
455 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
456 | if (!fixed_regs[i]) | |
457 | break; | |
458 | ||
459 | if (i > FP_REG_LAST) | |
460 | target_flags |= MASK_DISABLE_FPREGS; | |
461 | } | |
462 | ||
93d3ee56 | 463 | /* Implement the TARGET_OPTION_OVERRIDE hook. */ |
464 | ||
465 | static void | |
466 | pa_option_override (void) | |
bd57250e | 467 | { |
d09dbe0a | 468 | unsigned int i; |
469 | cl_deferred_option *opt; | |
470 | VEC(cl_deferred_option,heap) *vec | |
471 | = (VEC(cl_deferred_option,heap) *) pa_deferred_options; | |
472 | ||
473 | FOR_EACH_VEC_ELT (cl_deferred_option, vec, i, opt) | |
474 | { | |
475 | switch (opt->opt_index) | |
476 | { | |
477 | case OPT_mfixed_range_: | |
478 | fix_range (opt->arg); | |
479 | break; | |
480 | ||
481 | default: | |
482 | gcc_unreachable (); | |
483 | } | |
484 | } | |
485 | ||
7c5101fc | 486 | /* Unconditional branches in the delay slot are not compatible with dwarf2 |
487 | call frame information. There is no benefit in using this optimization | |
488 | on PA8000 and later processors. */ | |
489 | if (pa_cpu >= PROCESSOR_8000 | |
218e3e4e | 490 | || (targetm_common.except_unwind_info (&global_options) == UI_DWARF2 |
b213bf24 | 491 | && flag_exceptions) |
7c5101fc | 492 | || flag_unwind_tables) |
493 | target_flags &= ~MASK_JUMP_IN_DELAY; | |
494 | ||
c7a4e712 | 495 | if (flag_pic && TARGET_PORTABLE_RUNTIME) |
496 | { | |
0a81f5a0 | 497 | warning (0, "PIC code generation is not supported in the portable runtime model"); |
c7a4e712 | 498 | } |
499 | ||
b29897dd | 500 | if (flag_pic && TARGET_FAST_INDIRECT_CALLS) |
c7a4e712 | 501 | { |
0a81f5a0 | 502 | warning (0, "PIC code generation is not compatible with fast indirect calls"); |
c7a4e712 | 503 | } |
751e64a1 | 504 | |
5bd7b548 | 505 | if (! TARGET_GAS && write_symbols != NO_DEBUG) |
506 | { | |
c3ceba8e | 507 | warning (0, "-g is only supported when using GAS on this processor,"); |
508 | warning (0, "-g option disabled"); | |
5bd7b548 | 509 | write_symbols = NO_DEBUG; |
510 | } | |
5cb4669a | 511 | |
fc44315f | 512 | /* We only support the "big PIC" model now. And we always generate PIC |
513 | code when in 64bit mode. */ | |
514 | if (flag_pic == 1 || TARGET_64BIT) | |
5e3c5739 | 515 | flag_pic = 2; |
516 | ||
1724df0b | 517 | /* Disable -freorder-blocks-and-partition as we don't support hot and |
518 | cold partitioning. */ | |
519 | if (flag_reorder_blocks_and_partition) | |
520 | { | |
521 | inform (input_location, | |
522 | "-freorder-blocks-and-partition does not work " | |
523 | "on this architecture"); | |
524 | flag_reorder_blocks_and_partition = 0; | |
525 | flag_reorder_blocks = 1; | |
526 | } | |
527 | ||
58356836 | 528 | /* We can't guarantee that .dword is available for 32-bit targets. */ |
529 | if (UNITS_PER_WORD == 4) | |
530 | targetm.asm_out.aligned_op.di = NULL; | |
531 | ||
532 | /* The unaligned ops are only available when using GAS. */ | |
533 | if (!TARGET_GAS) | |
534 | { | |
535 | targetm.asm_out.unaligned_op.hi = NULL; | |
536 | targetm.asm_out.unaligned_op.si = NULL; | |
537 | targetm.asm_out.unaligned_op.di = NULL; | |
538 | } | |
916c9cef | 539 | |
540 | init_machine_status = pa_init_machine_status; | |
134b4858 | 541 | } |
542 | ||
0f9c87cc | 543 | enum pa_builtins |
544 | { | |
545 | PA_BUILTIN_COPYSIGNQ, | |
546 | PA_BUILTIN_FABSQ, | |
547 | PA_BUILTIN_INFQ, | |
548 | PA_BUILTIN_HUGE_VALQ, | |
549 | PA_BUILTIN_max | |
550 | }; | |
551 | ||
552 | static GTY(()) tree pa_builtins[(int) PA_BUILTIN_max]; | |
553 | ||
066397a3 | 554 | static void |
5c1d8983 | 555 | pa_init_builtins (void) |
ffa8918b | 556 | { |
557 | #ifdef DONT_HAVE_FPUTC_UNLOCKED | |
b9a16870 | 558 | { |
559 | tree decl = builtin_decl_explicit (BUILT_IN_PUTC_UNLOCKED); | |
560 | set_builtin_decl (BUILT_IN_FPUTC_UNLOCKED, decl, | |
561 | builtin_decl_implicit_p (BUILT_IN_PUTC_UNLOCKED)); | |
562 | } | |
ffa8918b | 563 | #endif |
01cbacb9 | 564 | #if TARGET_HPUX_11 |
b9a16870 | 565 | { |
566 | tree decl; | |
567 | ||
568 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITE)) != NULL_TREE) | |
569 | set_user_assembler_name (decl, "_Isfinite"); | |
570 | if ((decl = builtin_decl_explicit (BUILT_IN_FINITEF)) != NULL_TREE) | |
571 | set_user_assembler_name (decl, "_Isfinitef"); | |
572 | } | |
aafb162c | 573 | #endif |
0f9c87cc | 574 | |
575 | if (HPUX_LONG_DOUBLE_LIBRARY) | |
576 | { | |
577 | tree decl, ftype; | |
578 | ||
579 | /* Under HPUX, the __float128 type is a synonym for "long double". */ | |
580 | (*lang_hooks.types.register_builtin_type) (long_double_type_node, | |
581 | "__float128"); | |
582 | ||
583 | /* TFmode support builtins. */ | |
584 | ftype = build_function_type_list (long_double_type_node, | |
585 | long_double_type_node, | |
586 | NULL_TREE); | |
587 | decl = add_builtin_function ("__builtin_fabsq", ftype, | |
588 | PA_BUILTIN_FABSQ, BUILT_IN_MD, | |
589 | "_U_Qfabs", NULL_TREE); | |
590 | TREE_READONLY (decl) = 1; | |
591 | pa_builtins[PA_BUILTIN_FABSQ] = decl; | |
592 | ||
593 | ftype = build_function_type_list (long_double_type_node, | |
594 | long_double_type_node, | |
595 | long_double_type_node, | |
596 | NULL_TREE); | |
597 | decl = add_builtin_function ("__builtin_copysignq", ftype, | |
598 | PA_BUILTIN_COPYSIGNQ, BUILT_IN_MD, | |
599 | "_U_Qfcopysign", NULL_TREE); | |
600 | TREE_READONLY (decl) = 1; | |
601 | pa_builtins[PA_BUILTIN_COPYSIGNQ] = decl; | |
602 | ||
ab27801e | 603 | ftype = build_function_type_list (long_double_type_node, NULL_TREE); |
0f9c87cc | 604 | decl = add_builtin_function ("__builtin_infq", ftype, |
605 | PA_BUILTIN_INFQ, BUILT_IN_MD, | |
606 | NULL, NULL_TREE); | |
607 | pa_builtins[PA_BUILTIN_INFQ] = decl; | |
608 | ||
609 | decl = add_builtin_function ("__builtin_huge_valq", ftype, | |
610 | PA_BUILTIN_HUGE_VALQ, BUILT_IN_MD, | |
611 | NULL, NULL_TREE); | |
612 | pa_builtins[PA_BUILTIN_HUGE_VALQ] = decl; | |
613 | } | |
614 | } | |
615 | ||
616 | static rtx | |
617 | pa_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, | |
618 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
619 | int ignore ATTRIBUTE_UNUSED) | |
620 | { | |
621 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
622 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
623 | ||
624 | switch (fcode) | |
625 | { | |
626 | case PA_BUILTIN_FABSQ: | |
627 | case PA_BUILTIN_COPYSIGNQ: | |
628 | return expand_call (exp, target, ignore); | |
629 | ||
630 | case PA_BUILTIN_INFQ: | |
631 | case PA_BUILTIN_HUGE_VALQ: | |
632 | { | |
633 | enum machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp)); | |
634 | REAL_VALUE_TYPE inf; | |
635 | rtx tmp; | |
636 | ||
637 | real_inf (&inf); | |
638 | tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode); | |
639 | ||
640 | tmp = validize_mem (force_const_mem (target_mode, tmp)); | |
641 | ||
642 | if (target == 0) | |
643 | target = gen_reg_rtx (target_mode); | |
644 | ||
645 | emit_move_insn (target, tmp); | |
646 | return target; | |
647 | } | |
648 | ||
649 | default: | |
650 | gcc_unreachable (); | |
651 | } | |
652 | ||
653 | return NULL_RTX; | |
ffa8918b | 654 | } |
655 | ||
916c9cef | 656 | /* Function to init struct machine_function. |
657 | This will be called, via a pointer variable, | |
658 | from push_function_context. */ | |
659 | ||
660 | static struct machine_function * | |
661 | pa_init_machine_status (void) | |
662 | { | |
ba72912a | 663 | return ggc_alloc_cleared_machine_function (); |
916c9cef | 664 | } |
665 | ||
dbd3d89d | 666 | /* If FROM is a probable pointer register, mark TO as a probable |
667 | pointer register with the same pointer alignment as FROM. */ | |
668 | ||
669 | static void | |
670 | copy_reg_pointer (rtx to, rtx from) | |
671 | { | |
672 | if (REG_POINTER (from)) | |
673 | mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from))); | |
674 | } | |
675 | ||
6d36483b | 676 | /* Return 1 if X contains a symbolic expression. We know these |
677 | expressions will have one of a few well defined forms, so | |
347b5848 | 678 | we need only check those forms. */ |
679 | int | |
5c1d8983 | 680 | symbolic_expression_p (rtx x) |
347b5848 | 681 | { |
682 | ||
6dc3b0d9 | 683 | /* Strip off any HIGH. */ |
347b5848 | 684 | if (GET_CODE (x) == HIGH) |
685 | x = XEXP (x, 0); | |
686 | ||
687 | return (symbolic_operand (x, VOIDmode)); | |
688 | } | |
689 | ||
7c4d3047 | 690 | /* Accept any constant that can be moved in one instruction into a |
d9d7c968 | 691 | general register. */ |
6d36483b | 692 | int |
59ad2f1e | 693 | cint_ok_for_move (HOST_WIDE_INT ival) |
d9d7c968 | 694 | { |
695 | /* OK if ldo, ldil, or zdepi, can be used. */ | |
59ad2f1e | 696 | return (VAL_14_BITS_P (ival) |
697 | || ldil_cint_p (ival) | |
698 | || zdepi_cint_p (ival)); | |
d9d7c968 | 699 | } |
87ad11b0 | 700 | \f |
59ad2f1e | 701 | /* True iff ldil can be used to load this CONST_INT. The least |
702 | significant 11 bits of the value must be zero and the value must | |
703 | not change sign when extended from 32 to 64 bits. */ | |
704 | int | |
705 | ldil_cint_p (HOST_WIDE_INT ival) | |
706 | { | |
707 | HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff); | |
708 | ||
709 | return x == 0 || x == ((HOST_WIDE_INT) -1 << 31); | |
710 | } | |
711 | ||
ea52c577 | 712 | /* True iff zdepi can be used to generate this CONST_INT. |
5b865faf | 713 | zdepi first sign extends a 5-bit signed number to a given field |
ea52c577 | 714 | length, then places this field anywhere in a zero. */ |
e057641f | 715 | int |
5c1d8983 | 716 | zdepi_cint_p (unsigned HOST_WIDE_INT x) |
fad0b60f | 717 | { |
3745c59b | 718 | unsigned HOST_WIDE_INT lsb_mask, t; |
fad0b60f | 719 | |
720 | /* This might not be obvious, but it's at least fast. | |
01cc3b75 | 721 | This function is critical; we don't have the time loops would take. */ |
42faba01 | 722 | lsb_mask = x & -x; |
723 | t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1); | |
724 | /* Return true iff t is a power of two. */ | |
fad0b60f | 725 | return ((t & (t - 1)) == 0); |
726 | } | |
727 | ||
6d36483b | 728 | /* True iff depi or extru can be used to compute (reg & mask). |
729 | Accept bit pattern like these: | |
730 | 0....01....1 | |
731 | 1....10....0 | |
732 | 1..10..01..1 */ | |
e057641f | 733 | int |
5c1d8983 | 734 | and_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 735 | { |
736 | mask = ~mask; | |
737 | mask += mask & -mask; | |
738 | return (mask & (mask - 1)) == 0; | |
739 | } | |
740 | ||
e057641f | 741 | /* True iff depi can be used to compute (reg | MASK). */ |
742 | int | |
5c1d8983 | 743 | ior_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 744 | { |
745 | mask += mask & -mask; | |
746 | return (mask & (mask - 1)) == 0; | |
747 | } | |
87ad11b0 | 748 | \f |
749 | /* Legitimize PIC addresses. If the address is already | |
750 | position-independent, we return ORIG. Newly generated | |
751 | position-independent addresses go to REG. If we need more | |
752 | than one register, we lose. */ | |
753 | ||
754 | rtx | |
5c1d8983 | 755 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
87ad11b0 | 756 | { |
757 | rtx pic_ref = orig; | |
758 | ||
f7229f19 | 759 | gcc_assert (!PA_SYMBOL_REF_TLS_P (orig)); |
716b2c5a | 760 | |
b090827b | 761 | /* Labels need special handling. */ |
611a88e1 | 762 | if (pic_label_operand (orig, mode)) |
b4a7bf10 | 763 | { |
3e478718 | 764 | rtx insn; |
765 | ||
2536cc16 | 766 | /* We do not want to go through the movXX expanders here since that |
767 | would create recursion. | |
768 | ||
769 | Nor do we really want to call a generator for a named pattern | |
770 | since that requires multiple patterns if we want to support | |
771 | multiple word sizes. | |
772 | ||
773 | So instead we just emit the raw set, which avoids the movXX | |
774 | expanders completely. */ | |
dbd3d89d | 775 | mark_reg_pointer (reg, BITS_PER_UNIT); |
3e478718 | 776 | insn = emit_insn (gen_rtx_SET (VOIDmode, reg, orig)); |
777 | ||
778 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
b9c74b4d | 779 | add_reg_note (insn, REG_EQUAL, orig); |
3e478718 | 780 | |
781 | /* During and after reload, we need to generate a REG_LABEL_OPERAND note | |
782 | and update LABEL_NUSES because this is not done automatically. */ | |
783 | if (reload_in_progress || reload_completed) | |
784 | { | |
785 | /* Extract LABEL_REF. */ | |
786 | if (GET_CODE (orig) == CONST) | |
787 | orig = XEXP (XEXP (orig, 0), 0); | |
788 | /* Extract CODE_LABEL. */ | |
789 | orig = XEXP (orig, 0); | |
a1ddb869 | 790 | add_reg_note (insn, REG_LABEL_OPERAND, orig); |
3e478718 | 791 | LABEL_NUSES (orig)++; |
792 | } | |
18d50ae6 | 793 | crtl->uses_pic_offset_table = 1; |
b4a7bf10 | 794 | return reg; |
795 | } | |
87ad11b0 | 796 | if (GET_CODE (orig) == SYMBOL_REF) |
797 | { | |
f9c1ba9d | 798 | rtx insn, tmp_reg; |
799 | ||
ecf2283d | 800 | gcc_assert (reg); |
87ad11b0 | 801 | |
f9c1ba9d | 802 | /* Before reload, allocate a temporary register for the intermediate |
803 | result. This allows the sequence to be deleted when the final | |
804 | result is unused and the insns are trivially dead. */ | |
805 | tmp_reg = ((reload_in_progress || reload_completed) | |
806 | ? reg : gen_reg_rtx (Pmode)); | |
807 | ||
39ec41d4 | 808 | if (function_label_operand (orig, VOIDmode)) |
3635d963 | 809 | { |
cefef42c | 810 | /* Force function label into memory in word mode. */ |
811 | orig = XEXP (force_const_mem (word_mode, orig), 0); | |
3635d963 | 812 | /* Load plabel address from DLT. */ |
813 | emit_move_insn (tmp_reg, | |
814 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, | |
815 | gen_rtx_HIGH (word_mode, orig))); | |
816 | pic_ref | |
817 | = gen_const_mem (Pmode, | |
818 | gen_rtx_LO_SUM (Pmode, tmp_reg, | |
819 | gen_rtx_UNSPEC (Pmode, | |
e265a6da | 820 | gen_rtvec (1, orig), |
821 | UNSPEC_DLTIND14R))); | |
3635d963 | 822 | emit_move_insn (reg, pic_ref); |
823 | /* Now load address of function descriptor. */ | |
824 | pic_ref = gen_rtx_MEM (Pmode, reg); | |
825 | } | |
826 | else | |
827 | { | |
828 | /* Load symbol reference from DLT. */ | |
829 | emit_move_insn (tmp_reg, | |
830 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, | |
831 | gen_rtx_HIGH (word_mode, orig))); | |
832 | pic_ref | |
833 | = gen_const_mem (Pmode, | |
834 | gen_rtx_LO_SUM (Pmode, tmp_reg, | |
835 | gen_rtx_UNSPEC (Pmode, | |
836 | gen_rtvec (1, orig), | |
837 | UNSPEC_DLTIND14R))); | |
838 | } | |
7014838c | 839 | |
18d50ae6 | 840 | crtl->uses_pic_offset_table = 1; |
dbd3d89d | 841 | mark_reg_pointer (reg, BITS_PER_UNIT); |
f9c1ba9d | 842 | insn = emit_move_insn (reg, pic_ref); |
843 | ||
844 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
24153880 | 845 | set_unique_reg_note (insn, REG_EQUAL, orig); |
f9c1ba9d | 846 | |
87ad11b0 | 847 | return reg; |
848 | } | |
849 | else if (GET_CODE (orig) == CONST) | |
850 | { | |
57ed30e5 | 851 | rtx base; |
87ad11b0 | 852 | |
853 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
854 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
855 | return orig; | |
856 | ||
ecf2283d | 857 | gcc_assert (reg); |
858 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); | |
859 | ||
860 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
861 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
862 | base == reg ? 0 : reg); | |
dbd3d89d | 863 | |
87ad11b0 | 864 | if (GET_CODE (orig) == CONST_INT) |
865 | { | |
42faba01 | 866 | if (INT_14_BITS (orig)) |
b244d4c7 | 867 | return plus_constant (base, INTVAL (orig)); |
87ad11b0 | 868 | orig = force_reg (Pmode, orig); |
869 | } | |
ad851752 | 870 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
87ad11b0 | 871 | /* Likewise, should we set special REG_NOTEs here? */ |
872 | } | |
dbd3d89d | 873 | |
87ad11b0 | 874 | return pic_ref; |
875 | } | |
876 | ||
716b2c5a | 877 | static GTY(()) rtx gen_tls_tga; |
878 | ||
879 | static rtx | |
880 | gen_tls_get_addr (void) | |
881 | { | |
882 | if (!gen_tls_tga) | |
883 | gen_tls_tga = init_one_libfunc ("__tls_get_addr"); | |
884 | return gen_tls_tga; | |
885 | } | |
886 | ||
887 | static rtx | |
888 | hppa_tls_call (rtx arg) | |
889 | { | |
890 | rtx ret; | |
891 | ||
892 | ret = gen_reg_rtx (Pmode); | |
893 | emit_library_call_value (gen_tls_get_addr (), ret, | |
894 | LCT_CONST, Pmode, 1, arg, Pmode); | |
895 | ||
896 | return ret; | |
897 | } | |
898 | ||
899 | static rtx | |
900 | legitimize_tls_address (rtx addr) | |
901 | { | |
902 | rtx ret, insn, tmp, t1, t2, tp; | |
903 | enum tls_model model = SYMBOL_REF_TLS_MODEL (addr); | |
904 | ||
905 | switch (model) | |
906 | { | |
907 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
908 | tmp = gen_reg_rtx (Pmode); | |
3f8d8851 | 909 | if (flag_pic) |
910 | emit_insn (gen_tgd_load_pic (tmp, addr)); | |
911 | else | |
912 | emit_insn (gen_tgd_load (tmp, addr)); | |
716b2c5a | 913 | ret = hppa_tls_call (tmp); |
914 | break; | |
915 | ||
916 | case TLS_MODEL_LOCAL_DYNAMIC: | |
917 | ret = gen_reg_rtx (Pmode); | |
918 | tmp = gen_reg_rtx (Pmode); | |
919 | start_sequence (); | |
3f8d8851 | 920 | if (flag_pic) |
921 | emit_insn (gen_tld_load_pic (tmp, addr)); | |
922 | else | |
923 | emit_insn (gen_tld_load (tmp, addr)); | |
716b2c5a | 924 | t1 = hppa_tls_call (tmp); |
925 | insn = get_insns (); | |
926 | end_sequence (); | |
927 | t2 = gen_reg_rtx (Pmode); | |
928 | emit_libcall_block (insn, t2, t1, | |
929 | gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
930 | UNSPEC_TLSLDBASE)); | |
931 | emit_insn (gen_tld_offset_load (ret, addr, t2)); | |
932 | break; | |
933 | ||
934 | case TLS_MODEL_INITIAL_EXEC: | |
935 | tp = gen_reg_rtx (Pmode); | |
936 | tmp = gen_reg_rtx (Pmode); | |
937 | ret = gen_reg_rtx (Pmode); | |
938 | emit_insn (gen_tp_load (tp)); | |
3f8d8851 | 939 | if (flag_pic) |
940 | emit_insn (gen_tie_load_pic (tmp, addr)); | |
941 | else | |
942 | emit_insn (gen_tie_load (tmp, addr)); | |
716b2c5a | 943 | emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp)); |
944 | break; | |
945 | ||
946 | case TLS_MODEL_LOCAL_EXEC: | |
947 | tp = gen_reg_rtx (Pmode); | |
948 | ret = gen_reg_rtx (Pmode); | |
949 | emit_insn (gen_tp_load (tp)); | |
950 | emit_insn (gen_tle_load (ret, addr, tp)); | |
951 | break; | |
952 | ||
953 | default: | |
f7229f19 | 954 | gcc_unreachable (); |
716b2c5a | 955 | } |
956 | ||
957 | return ret; | |
958 | } | |
959 | ||
347b5848 | 960 | /* Try machine-dependent ways of modifying an illegitimate address |
961 | to be legitimate. If we find one, return the new, valid address. | |
962 | This macro is used in only one place: `memory_address' in explow.c. | |
963 | ||
964 | OLDX is the address as it was before break_out_memory_refs was called. | |
965 | In some cases it is useful to look at this to decide what needs to be done. | |
966 | ||
347b5848 | 967 | It is always safe for this macro to do nothing. It exists to recognize |
6d36483b | 968 | opportunities to optimize the output. |
347b5848 | 969 | |
970 | For the PA, transform: | |
971 | ||
972 | memory(X + <large int>) | |
973 | ||
974 | into: | |
975 | ||
976 | if (<large int> & mask) >= 16 | |
977 | Y = (<large int> & ~mask) + mask + 1 Round up. | |
978 | else | |
979 | Y = (<large int> & ~mask) Round down. | |
980 | Z = X + Y | |
981 | memory (Z + (<large int> - Y)); | |
982 | ||
6d36483b | 983 | This is for CSE to find several similar references, and only use one Z. |
347b5848 | 984 | |
33f88b1c | 985 | X can either be a SYMBOL_REF or REG, but because combine cannot |
347b5848 | 986 | perform a 4->2 combination we do nothing for SYMBOL_REF + D where |
987 | D will not fit in 14 bits. | |
988 | ||
989 | MODE_FLOAT references allow displacements which fit in 5 bits, so use | |
6d36483b | 990 | 0x1f as the mask. |
347b5848 | 991 | |
992 | MODE_INT references allow displacements which fit in 14 bits, so use | |
6d36483b | 993 | 0x3fff as the mask. |
347b5848 | 994 | |
995 | This relies on the fact that most mode MODE_FLOAT references will use FP | |
996 | registers and most mode MODE_INT references will use integer registers. | |
997 | (In the rare case of an FP register used in an integer MODE, we depend | |
998 | on secondary reloads to clean things up.) | |
999 | ||
1000 | ||
1001 | It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special | |
1002 | manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed | |
01cc3b75 | 1003 | addressing modes to be used). |
347b5848 | 1004 | |
1005 | Put X and Z into registers. Then put the entire expression into | |
1006 | a register. */ | |
1007 | ||
1008 | rtx | |
5c1d8983 | 1009 | hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
1010 | enum machine_mode mode) | |
347b5848 | 1011 | { |
347b5848 | 1012 | rtx orig = x; |
1013 | ||
dbd3d89d | 1014 | /* We need to canonicalize the order of operands in unscaled indexed |
1015 | addresses since the code that checks if an address is valid doesn't | |
1016 | always try both orders. */ | |
1017 | if (!TARGET_NO_SPACE_REGS | |
1018 | && GET_CODE (x) == PLUS | |
1019 | && GET_MODE (x) == Pmode | |
1020 | && REG_P (XEXP (x, 0)) | |
1021 | && REG_P (XEXP (x, 1)) | |
1022 | && REG_POINTER (XEXP (x, 0)) | |
1023 | && !REG_POINTER (XEXP (x, 1))) | |
1024 | return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0)); | |
1025 | ||
716b2c5a | 1026 | if (PA_SYMBOL_REF_TLS_P (x)) |
1027 | return legitimize_tls_address (x); | |
1028 | else if (flag_pic) | |
b4a7bf10 | 1029 | return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); |
1030 | ||
6dc3b0d9 | 1031 | /* Strip off CONST. */ |
347b5848 | 1032 | if (GET_CODE (x) == CONST) |
1033 | x = XEXP (x, 0); | |
1034 | ||
42819d4e | 1035 | /* Special case. Get the SYMBOL_REF into a register and use indexing. |
1036 | That should always be safe. */ | |
1037 | if (GET_CODE (x) == PLUS | |
1038 | && GET_CODE (XEXP (x, 0)) == REG | |
1039 | && GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
1040 | { | |
440c23df | 1041 | rtx reg = force_reg (Pmode, XEXP (x, 1)); |
1042 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0))); | |
42819d4e | 1043 | } |
1044 | ||
166bf021 | 1045 | /* Note we must reject symbols which represent function addresses |
1046 | since the assembler/linker can't handle arithmetic on plabels. */ | |
347b5848 | 1047 | if (GET_CODE (x) == PLUS |
1048 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
166bf021 | 1049 | && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF |
1050 | && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0))) | |
347b5848 | 1051 | || GET_CODE (XEXP (x, 0)) == REG)) |
1052 | { | |
1053 | rtx int_part, ptr_reg; | |
1054 | int newoffset; | |
1055 | int offset = INTVAL (XEXP (x, 1)); | |
1b6f11e2 | 1056 | int mask; |
1057 | ||
1058 | mask = (GET_MODE_CLASS (mode) == MODE_FLOAT | |
c78e6152 | 1059 | ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff); |
347b5848 | 1060 | |
6d36483b | 1061 | /* Choose which way to round the offset. Round up if we |
347b5848 | 1062 | are >= halfway to the next boundary. */ |
1063 | if ((offset & mask) >= ((mask + 1) / 2)) | |
1064 | newoffset = (offset & ~ mask) + mask + 1; | |
1065 | else | |
1066 | newoffset = (offset & ~ mask); | |
1067 | ||
1068 | /* If the newoffset will not fit in 14 bits (ldo), then | |
1069 | handling this would take 4 or 5 instructions (2 to load | |
1070 | the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to | |
1071 | add the new offset and the SYMBOL_REF.) Combine can | |
1072 | not handle 4->2 or 5->2 combinations, so do not create | |
1073 | them. */ | |
1074 | if (! VAL_14_BITS_P (newoffset) | |
1075 | && GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
1076 | { | |
7014838c | 1077 | rtx const_part = plus_constant (XEXP (x, 0), newoffset); |
347b5848 | 1078 | rtx tmp_reg |
339613b4 | 1079 | = force_reg (Pmode, |
ad851752 | 1080 | gen_rtx_HIGH (Pmode, const_part)); |
347b5848 | 1081 | ptr_reg |
339613b4 | 1082 | = force_reg (Pmode, |
7014838c | 1083 | gen_rtx_LO_SUM (Pmode, |
1084 | tmp_reg, const_part)); | |
347b5848 | 1085 | } |
1086 | else | |
1087 | { | |
1088 | if (! VAL_14_BITS_P (newoffset)) | |
339613b4 | 1089 | int_part = force_reg (Pmode, GEN_INT (newoffset)); |
347b5848 | 1090 | else |
1091 | int_part = GEN_INT (newoffset); | |
1092 | ||
339613b4 | 1093 | ptr_reg = force_reg (Pmode, |
ad851752 | 1094 | gen_rtx_PLUS (Pmode, |
1095 | force_reg (Pmode, XEXP (x, 0)), | |
1096 | int_part)); | |
347b5848 | 1097 | } |
1098 | return plus_constant (ptr_reg, offset - newoffset); | |
1099 | } | |
45f1285a | 1100 | |
5115683e | 1101 | /* Handle (plus (mult (a) (shadd_constant)) (b)). */ |
45f1285a | 1102 | |
347b5848 | 1103 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT |
1104 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
45f1285a | 1105 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))) |
6720e96c | 1106 | && (OBJECT_P (XEXP (x, 1)) |
45f1285a | 1107 | || GET_CODE (XEXP (x, 1)) == SUBREG) |
1108 | && GET_CODE (XEXP (x, 1)) != CONST) | |
347b5848 | 1109 | { |
1110 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1111 | rtx reg1, reg2; | |
5115683e | 1112 | |
1113 | reg1 = XEXP (x, 1); | |
1114 | if (GET_CODE (reg1) != REG) | |
1115 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1116 | ||
1117 | reg2 = XEXP (XEXP (x, 0), 0); | |
1118 | if (GET_CODE (reg2) != REG) | |
1119 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1120 | ||
ad851752 | 1121 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1122 | gen_rtx_MULT (Pmode, |
1123 | reg2, | |
1124 | GEN_INT (val)), | |
ad851752 | 1125 | reg1)); |
347b5848 | 1126 | } |
45f1285a | 1127 | |
00a87639 | 1128 | /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)). |
1129 | ||
1130 | Only do so for floating point modes since this is more speculative | |
1131 | and we lose if it's an integer store. */ | |
5115683e | 1132 | if (GET_CODE (x) == PLUS |
00a87639 | 1133 | && GET_CODE (XEXP (x, 0)) == PLUS |
1134 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
1135 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
5115683e | 1136 | && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) |
1137 | && (mode == SFmode || mode == DFmode)) | |
00a87639 | 1138 | { |
5115683e | 1139 | |
1140 | /* First, try and figure out what to use as a base register. */ | |
1ce99229 | 1141 | rtx reg1, reg2, base, idx; |
5115683e | 1142 | |
1143 | reg1 = XEXP (XEXP (x, 0), 1); | |
1144 | reg2 = XEXP (x, 1); | |
1145 | base = NULL_RTX; | |
1146 | idx = NULL_RTX; | |
1147 | ||
1148 | /* Make sure they're both regs. If one was a SYMBOL_REF [+ const], | |
e61a0a7f | 1149 | then emit_move_sequence will turn on REG_POINTER so we'll know |
1150 | it's a base register below. */ | |
5115683e | 1151 | if (GET_CODE (reg1) != REG) |
1152 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1153 | ||
1154 | if (GET_CODE (reg2) != REG) | |
1155 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1156 | ||
1157 | /* Figure out what the base and index are. */ | |
9840d99d | 1158 | |
5115683e | 1159 | if (GET_CODE (reg1) == REG |
e61a0a7f | 1160 | && REG_POINTER (reg1)) |
5115683e | 1161 | { |
1162 | base = reg1; | |
ad851752 | 1163 | idx = gen_rtx_PLUS (Pmode, |
1164 | gen_rtx_MULT (Pmode, | |
1165 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
1166 | XEXP (XEXP (XEXP (x, 0), 0), 1)), | |
1167 | XEXP (x, 1)); | |
5115683e | 1168 | } |
1169 | else if (GET_CODE (reg2) == REG | |
e61a0a7f | 1170 | && REG_POINTER (reg2)) |
5115683e | 1171 | { |
1172 | base = reg2; | |
5115683e | 1173 | idx = XEXP (x, 0); |
1174 | } | |
1175 | ||
1176 | if (base == 0) | |
21f3ee9c | 1177 | return orig; |
5115683e | 1178 | |
1179 | /* If the index adds a large constant, try to scale the | |
1180 | constant so that it can be loaded with only one insn. */ | |
1181 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1182 | && VAL_14_BITS_P (INTVAL (XEXP (idx, 1)) | |
1183 | / INTVAL (XEXP (XEXP (idx, 0), 1))) | |
1184 | && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0) | |
1185 | { | |
1186 | /* Divide the CONST_INT by the scale factor, then add it to A. */ | |
1187 | int val = INTVAL (XEXP (idx, 1)); | |
1188 | ||
1189 | val /= INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1190 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1191 | if (GET_CODE (reg1) != REG) | |
1192 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1193 | ||
ad851752 | 1194 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val))); |
5115683e | 1195 | |
1196 | /* We can now generate a simple scaled indexed address. */ | |
7014838c | 1197 | return |
1198 | force_reg | |
1199 | (Pmode, gen_rtx_PLUS (Pmode, | |
1200 | gen_rtx_MULT (Pmode, reg1, | |
1201 | XEXP (XEXP (idx, 0), 1)), | |
1202 | base)); | |
5115683e | 1203 | } |
1204 | ||
1205 | /* If B + C is still a valid base register, then add them. */ | |
1206 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
1207 | && INTVAL (XEXP (idx, 1)) <= 4096 | |
1208 | && INTVAL (XEXP (idx, 1)) >= -4096) | |
1209 | { | |
1210 | int val = INTVAL (XEXP (XEXP (idx, 0), 1)); | |
1211 | rtx reg1, reg2; | |
1212 | ||
ad851752 | 1213 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1))); |
5115683e | 1214 | |
1215 | reg2 = XEXP (XEXP (idx, 0), 0); | |
1216 | if (GET_CODE (reg2) != CONST_INT) | |
1217 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1218 | ||
ad851752 | 1219 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 1220 | gen_rtx_MULT (Pmode, |
1221 | reg2, | |
ad851752 | 1222 | GEN_INT (val)), |
1223 | reg1)); | |
5115683e | 1224 | } |
1225 | ||
1226 | /* Get the index into a register, then add the base + index and | |
1227 | return a register holding the result. */ | |
1228 | ||
1229 | /* First get A into a register. */ | |
1230 | reg1 = XEXP (XEXP (idx, 0), 0); | |
1231 | if (GET_CODE (reg1) != REG) | |
1232 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1233 | ||
1234 | /* And get B into a register. */ | |
1235 | reg2 = XEXP (idx, 1); | |
1236 | if (GET_CODE (reg2) != REG) | |
1237 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1238 | ||
ad851752 | 1239 | reg1 = force_reg (Pmode, |
1240 | gen_rtx_PLUS (Pmode, | |
1241 | gen_rtx_MULT (Pmode, reg1, | |
1242 | XEXP (XEXP (idx, 0), 1)), | |
1243 | reg2)); | |
5115683e | 1244 | |
1245 | /* Add the result to our base register and return. */ | |
ad851752 | 1246 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1)); |
9840d99d | 1247 | |
00a87639 | 1248 | } |
1249 | ||
6d36483b | 1250 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
fb5390c1 | 1251 | special handling to avoid creating an indexed memory address |
1252 | with x-100000 as the base. | |
9840d99d | 1253 | |
fb5390c1 | 1254 | If the constant part is small enough, then it's still safe because |
1255 | there is a guard page at the beginning and end of the data segment. | |
1256 | ||
1257 | Scaled references are common enough that we want to try and rearrange the | |
1258 | terms so that we can use indexing for these addresses too. Only | |
00a87639 | 1259 | do the optimization for floatint point modes. */ |
45f1285a | 1260 | |
fb5390c1 | 1261 | if (GET_CODE (x) == PLUS |
1262 | && symbolic_expression_p (XEXP (x, 1))) | |
45f1285a | 1263 | { |
1264 | /* Ugly. We modify things here so that the address offset specified | |
1265 | by the index expression is computed first, then added to x to form | |
fb5390c1 | 1266 | the entire address. */ |
45f1285a | 1267 | |
00a87639 | 1268 | rtx regx1, regx2, regy1, regy2, y; |
45f1285a | 1269 | |
1270 | /* Strip off any CONST. */ | |
1271 | y = XEXP (x, 1); | |
1272 | if (GET_CODE (y) == CONST) | |
1273 | y = XEXP (y, 0); | |
1274 | ||
7ee96d6e | 1275 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
1276 | { | |
00a87639 | 1277 | /* See if this looks like |
1278 | (plus (mult (reg) (shadd_const)) | |
1279 | (const (plus (symbol_ref) (const_int)))) | |
1280 | ||
5115683e | 1281 | Where const_int is small. In that case the const |
9840d99d | 1282 | expression is a valid pointer for indexing. |
5115683e | 1283 | |
1284 | If const_int is big, but can be divided evenly by shadd_const | |
1285 | and added to (reg). This allows more scaled indexed addresses. */ | |
1286 | if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1287 | && GET_CODE (XEXP (x, 0)) == MULT | |
00a87639 | 1288 | && GET_CODE (XEXP (y, 1)) == CONST_INT |
5115683e | 1289 | && INTVAL (XEXP (y, 1)) >= -4096 |
1290 | && INTVAL (XEXP (y, 1)) <= 4095 | |
1291 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1292 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
1293 | { | |
1294 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1295 | rtx reg1, reg2; | |
1296 | ||
1297 | reg1 = XEXP (x, 1); | |
1298 | if (GET_CODE (reg1) != REG) | |
1299 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1300 | ||
1301 | reg2 = XEXP (XEXP (x, 0), 0); | |
1302 | if (GET_CODE (reg2) != REG) | |
1303 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1304 | ||
ad851752 | 1305 | return force_reg (Pmode, |
1306 | gen_rtx_PLUS (Pmode, | |
7014838c | 1307 | gen_rtx_MULT (Pmode, |
1308 | reg2, | |
ad851752 | 1309 | GEN_INT (val)), |
7014838c | 1310 | reg1)); |
5115683e | 1311 | } |
1312 | else if ((mode == DFmode || mode == SFmode) | |
1313 | && GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1314 | && GET_CODE (XEXP (x, 0)) == MULT | |
1315 | && GET_CODE (XEXP (y, 1)) == CONST_INT | |
1316 | && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0 | |
1317 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1318 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
00a87639 | 1319 | { |
1320 | regx1 | |
1321 | = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1)) | |
1322 | / INTVAL (XEXP (XEXP (x, 0), 1)))); | |
1323 | regx2 = XEXP (XEXP (x, 0), 0); | |
1324 | if (GET_CODE (regx2) != REG) | |
1325 | regx2 = force_reg (Pmode, force_operand (regx2, 0)); | |
ad851752 | 1326 | regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1327 | regx2, regx1)); | |
7014838c | 1328 | return |
1329 | force_reg (Pmode, | |
1330 | gen_rtx_PLUS (Pmode, | |
1331 | gen_rtx_MULT (Pmode, regx2, | |
1332 | XEXP (XEXP (x, 0), 1)), | |
1333 | force_reg (Pmode, XEXP (y, 0)))); | |
00a87639 | 1334 | } |
fb5390c1 | 1335 | else if (GET_CODE (XEXP (y, 1)) == CONST_INT |
1336 | && INTVAL (XEXP (y, 1)) >= -4096 | |
1337 | && INTVAL (XEXP (y, 1)) <= 4095) | |
1338 | { | |
1339 | /* This is safe because of the guard page at the | |
1340 | beginning and end of the data space. Just | |
1341 | return the original address. */ | |
1342 | return orig; | |
1343 | } | |
00a87639 | 1344 | else |
1345 | { | |
1346 | /* Doesn't look like one we can optimize. */ | |
1347 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1348 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1349 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1350 | regx1 = force_reg (Pmode, | |
ad851752 | 1351 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1352 | regx1, regy2)); | |
1353 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); | |
00a87639 | 1354 | } |
7ee96d6e | 1355 | } |
45f1285a | 1356 | } |
1357 | ||
347b5848 | 1358 | return orig; |
1359 | } | |
1360 | ||
93d3ee56 | 1361 | /* Implement the TARGET_REGISTER_MOVE_COST hook. |
1362 | ||
1363 | Compute extra cost of moving data between one register class | |
1364 | and another. | |
1365 | ||
1366 | Make moves from SAR so expensive they should never happen. We used to | |
1367 | have 0xffff here, but that generates overflow in rare cases. | |
1368 | ||
1369 | Copies involving a FP register and a non-FP register are relatively | |
1370 | expensive because they must go through memory. | |
1371 | ||
1372 | Other copies are reasonably cheap. */ | |
1373 | ||
1374 | static int | |
1375 | hppa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
1376 | reg_class_t from, reg_class_t to) | |
1377 | { | |
1378 | if (from == SHIFT_REGS) | |
1379 | return 0x100; | |
5ddb2975 | 1380 | else if (to == SHIFT_REGS && FP_REG_CLASS_P (from)) |
1381 | return 18; | |
93d3ee56 | 1382 | else if ((FP_REG_CLASS_P (from) && ! FP_REG_CLASS_P (to)) |
1383 | || (FP_REG_CLASS_P (to) && ! FP_REG_CLASS_P (from))) | |
1384 | return 16; | |
1385 | else | |
1386 | return 2; | |
1387 | } | |
1388 | ||
87ad11b0 | 1389 | /* For the HPPA, REG and REG+CONST is cost 0 |
1390 | and addresses involving symbolic constants are cost 2. | |
1391 | ||
1392 | PIC addresses are very expensive. | |
1393 | ||
1394 | It is no coincidence that this has the same structure | |
1395 | as GO_IF_LEGITIMATE_ADDRESS. */ | |
ec0457a8 | 1396 | |
1397 | static int | |
f529eb25 | 1398 | hppa_address_cost (rtx X, |
1399 | bool speed ATTRIBUTE_UNUSED) | |
87ad11b0 | 1400 | { |
ec0457a8 | 1401 | switch (GET_CODE (X)) |
1402 | { | |
1403 | case REG: | |
1404 | case PLUS: | |
1405 | case LO_SUM: | |
87ad11b0 | 1406 | return 1; |
ec0457a8 | 1407 | case HIGH: |
1408 | return 2; | |
1409 | default: | |
1410 | return 4; | |
1411 | } | |
87ad11b0 | 1412 | } |
1413 | ||
fab7adbf | 1414 | /* Compute a (partial) cost for rtx X. Return true if the complete |
1415 | cost has been computed, and false if subexpressions should be | |
1416 | scanned. In either case, *TOTAL contains the cost result. */ | |
1417 | ||
1418 | static bool | |
20d892d1 | 1419 | hppa_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, |
1420 | int *total, bool speed ATTRIBUTE_UNUSED) | |
fab7adbf | 1421 | { |
1422 | switch (code) | |
1423 | { | |
1424 | case CONST_INT: | |
1425 | if (INTVAL (x) == 0) | |
1426 | *total = 0; | |
1427 | else if (INT_14_BITS (x)) | |
1428 | *total = 1; | |
1429 | else | |
1430 | *total = 2; | |
1431 | return true; | |
1432 | ||
1433 | case HIGH: | |
1434 | *total = 2; | |
1435 | return true; | |
1436 | ||
1437 | case CONST: | |
1438 | case LABEL_REF: | |
1439 | case SYMBOL_REF: | |
1440 | *total = 4; | |
1441 | return true; | |
1442 | ||
1443 | case CONST_DOUBLE: | |
1444 | if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode)) | |
1445 | && outer_code != SET) | |
1446 | *total = 0; | |
1447 | else | |
1448 | *total = 8; | |
1449 | return true; | |
1450 | ||
1451 | case MULT: | |
1452 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1453 | *total = COSTS_N_INSNS (3); | |
1454 | else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT) | |
1455 | *total = COSTS_N_INSNS (8); | |
1456 | else | |
1457 | *total = COSTS_N_INSNS (20); | |
1458 | return true; | |
1459 | ||
1460 | case DIV: | |
1461 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1462 | { | |
1463 | *total = COSTS_N_INSNS (14); | |
1464 | return true; | |
1465 | } | |
8e262b5e | 1466 | /* FALLTHRU */ |
fab7adbf | 1467 | |
1468 | case UDIV: | |
1469 | case MOD: | |
1470 | case UMOD: | |
1471 | *total = COSTS_N_INSNS (60); | |
1472 | return true; | |
1473 | ||
1474 | case PLUS: /* this includes shNadd insns */ | |
1475 | case MINUS: | |
1476 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1477 | *total = COSTS_N_INSNS (3); | |
1478 | else | |
1479 | *total = COSTS_N_INSNS (1); | |
1480 | return true; | |
1481 | ||
1482 | case ASHIFT: | |
1483 | case ASHIFTRT: | |
1484 | case LSHIFTRT: | |
1485 | *total = COSTS_N_INSNS (1); | |
1486 | return true; | |
1487 | ||
1488 | default: | |
1489 | return false; | |
1490 | } | |
1491 | } | |
1492 | ||
9840d99d | 1493 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a |
1494 | new rtx with the correct mode. */ | |
1495 | static inline rtx | |
5c1d8983 | 1496 | force_mode (enum machine_mode mode, rtx orig) |
9840d99d | 1497 | { |
1498 | if (mode == GET_MODE (orig)) | |
1499 | return orig; | |
1500 | ||
ecf2283d | 1501 | gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER); |
9840d99d | 1502 | |
1503 | return gen_rtx_REG (mode, REGNO (orig)); | |
1504 | } | |
1505 | ||
716b2c5a | 1506 | /* Return 1 if *X is a thread-local symbol. */ |
1507 | ||
1508 | static int | |
1509 | pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
1510 | { | |
1511 | return PA_SYMBOL_REF_TLS_P (*x); | |
1512 | } | |
1513 | ||
1514 | /* Return 1 if X contains a thread-local symbol. */ | |
1515 | ||
1516 | bool | |
1517 | pa_tls_referenced_p (rtx x) | |
1518 | { | |
1519 | if (!TARGET_HAVE_TLS) | |
1520 | return false; | |
1521 | ||
1522 | return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0); | |
1523 | } | |
1524 | ||
7d7d7bd2 | 1525 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ |
1526 | ||
1527 | static bool | |
1528 | pa_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) | |
1529 | { | |
1530 | return pa_tls_referenced_p (x); | |
1531 | } | |
1532 | ||
87ad11b0 | 1533 | /* Emit insns to move operands[1] into operands[0]. |
1534 | ||
1535 | Return 1 if we have written out everything that needs to be done to | |
1536 | do the move. Otherwise, return 0 and the caller will emit the move | |
9840d99d | 1537 | normally. |
f756078b | 1538 | |
1539 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
2cecd772 | 1540 | will be used. This routine is responsible for creating a new copy |
f756078b | 1541 | of SCRATCH_REG in the proper mode. */ |
87ad11b0 | 1542 | |
1543 | int | |
5c1d8983 | 1544 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) |
87ad11b0 | 1545 | { |
1546 | register rtx operand0 = operands[0]; | |
1547 | register rtx operand1 = operands[1]; | |
4a155b0f | 1548 | register rtx tem; |
87ad11b0 | 1549 | |
dbd3d89d | 1550 | /* We can only handle indexed addresses in the destination operand |
1551 | of floating point stores. Thus, we need to break out indexed | |
1552 | addresses from the destination operand. */ | |
1553 | if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0))) | |
1554 | { | |
e1ba4a27 | 1555 | gcc_assert (can_create_pseudo_p ()); |
dbd3d89d | 1556 | |
1557 | tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0)); | |
1558 | operand0 = replace_equiv_address (operand0, tem); | |
1559 | } | |
1560 | ||
1561 | /* On targets with non-equivalent space registers, break out unscaled | |
1562 | indexed addresses from the source operand before the final CSE. | |
1563 | We have to do this because the REG_POINTER flag is not correctly | |
1564 | carried through various optimization passes and CSE may substitute | |
1565 | a pseudo without the pointer set for one with the pointer set. As | |
5aedf60c | 1566 | a result, we loose various opportunities to create insns with |
dbd3d89d | 1567 | unscaled indexed addresses. */ |
1568 | if (!TARGET_NO_SPACE_REGS | |
1569 | && !cse_not_expected | |
1570 | && GET_CODE (operand1) == MEM | |
1571 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1572 | && REG_P (XEXP (XEXP (operand1, 0), 0)) | |
1573 | && REG_P (XEXP (XEXP (operand1, 0), 1))) | |
1574 | operand1 | |
1575 | = replace_equiv_address (operand1, | |
1576 | copy_to_mode_reg (Pmode, XEXP (operand1, 0))); | |
1577 | ||
2d4dc8d2 | 1578 | if (scratch_reg |
1579 | && reload_in_progress && GET_CODE (operand0) == REG | |
d1e2bb73 | 1580 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) |
1c654ff1 | 1581 | operand0 = reg_equiv_mem (REGNO (operand0)); |
2d4dc8d2 | 1582 | else if (scratch_reg |
1583 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
d1e2bb73 | 1584 | && GET_CODE (SUBREG_REG (operand0)) == REG |
1585 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1586 | { |
701e46d0 | 1587 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1588 | the code which tracks sets/uses for delete_output_reload. */ |
1589 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
1c654ff1 | 1590 | reg_equiv_mem (REGNO (SUBREG_REG (operand0))), |
701e46d0 | 1591 | SUBREG_BYTE (operand0)); |
e00b80b2 | 1592 | operand0 = alter_subreg (&temp); |
a3afad75 | 1593 | } |
d1e2bb73 | 1594 | |
2d4dc8d2 | 1595 | if (scratch_reg |
1596 | && reload_in_progress && GET_CODE (operand1) == REG | |
d1e2bb73 | 1597 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) |
1c654ff1 | 1598 | operand1 = reg_equiv_mem (REGNO (operand1)); |
2d4dc8d2 | 1599 | else if (scratch_reg |
1600 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
d1e2bb73 | 1601 | && GET_CODE (SUBREG_REG (operand1)) == REG |
1602 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1603 | { |
701e46d0 | 1604 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1605 | the code which tracks sets/uses for delete_output_reload. */ |
1606 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
1c654ff1 | 1607 | reg_equiv_mem (REGNO (SUBREG_REG (operand1))), |
701e46d0 | 1608 | SUBREG_BYTE (operand1)); |
e00b80b2 | 1609 | operand1 = alter_subreg (&temp); |
a3afad75 | 1610 | } |
d1e2bb73 | 1611 | |
2d4dc8d2 | 1612 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM |
4a155b0f | 1613 | && ((tem = find_replacement (&XEXP (operand0, 0))) |
1614 | != XEXP (operand0, 0))) | |
ed498904 | 1615 | operand0 = replace_equiv_address (operand0, tem); |
dbd3d89d | 1616 | |
2d4dc8d2 | 1617 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM |
4a155b0f | 1618 | && ((tem = find_replacement (&XEXP (operand1, 0))) |
1619 | != XEXP (operand1, 0))) | |
ed498904 | 1620 | operand1 = replace_equiv_address (operand1, tem); |
4a155b0f | 1621 | |
e8fdbafa | 1622 | /* Handle secondary reloads for loads/stores of FP registers from |
047e3121 | 1623 | REG+D addresses where D does not fit in 5 or 14 bits, including |
42819d4e | 1624 | (subreg (mem (addr))) cases. */ |
6bcdc1fb | 1625 | if (scratch_reg |
1626 | && fp_reg_operand (operand0, mode) | |
6b1c36c2 | 1627 | && ((GET_CODE (operand1) == MEM |
047e3121 | 1628 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode), |
1629 | XEXP (operand1, 0))) | |
6b1c36c2 | 1630 | || ((GET_CODE (operand1) == SUBREG |
1631 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
047e3121 | 1632 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1633 | ? SFmode : DFmode), | |
1634 | XEXP (XEXP (operand1, 0), 0)))))) | |
d6f01525 | 1635 | { |
6b1c36c2 | 1636 | if (GET_CODE (operand1) == SUBREG) |
1637 | operand1 = XEXP (operand1, 0); | |
1638 | ||
f756078b | 1639 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1640 | it in WORD_MODE regardless of what mode it was originally given | |
1641 | to us. */ | |
9840d99d | 1642 | scratch_reg = force_mode (word_mode, scratch_reg); |
7ee39d73 | 1643 | |
1644 | /* D might not fit in 14 bits either; for such cases load D into | |
1645 | scratch reg. */ | |
440c23df | 1646 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) |
7ee39d73 | 1647 | { |
1648 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
dbd3d89d | 1649 | emit_move_insn (scratch_reg, |
1650 | gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
1651 | Pmode, | |
1652 | XEXP (XEXP (operand1, 0), 0), | |
1653 | scratch_reg)); | |
7ee39d73 | 1654 | } |
1655 | else | |
1656 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
7014838c | 1657 | emit_insn (gen_rtx_SET (VOIDmode, operand0, |
ed498904 | 1658 | replace_equiv_address (operand1, scratch_reg))); |
d6f01525 | 1659 | return 1; |
1660 | } | |
6bcdc1fb | 1661 | else if (scratch_reg |
1662 | && fp_reg_operand (operand1, mode) | |
6b1c36c2 | 1663 | && ((GET_CODE (operand0) == MEM |
047e3121 | 1664 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1665 | ? SFmode : DFmode), | |
1666 | XEXP (operand0, 0))) | |
6b1c36c2 | 1667 | || ((GET_CODE (operand0) == SUBREG) |
1668 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
047e3121 | 1669 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1670 | ? SFmode : DFmode), | |
6bcdc1fb | 1671 | XEXP (XEXP (operand0, 0), 0))))) |
d6f01525 | 1672 | { |
6b1c36c2 | 1673 | if (GET_CODE (operand0) == SUBREG) |
1674 | operand0 = XEXP (operand0, 0); | |
1675 | ||
f756078b | 1676 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1677 | it in WORD_MODE regardless of what mode it was originally given | |
1678 | to us. */ | |
9840d99d | 1679 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1680 | |
7ee39d73 | 1681 | /* D might not fit in 14 bits either; for such cases load D into |
1682 | scratch reg. */ | |
440c23df | 1683 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) |
7ee39d73 | 1684 | { |
1685 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
ad851752 | 1686 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, |
1687 | 0)), | |
440c23df | 1688 | Pmode, |
ad851752 | 1689 | XEXP (XEXP (operand0, 0), |
1690 | 0), | |
1691 | scratch_reg)); | |
7ee39d73 | 1692 | } |
1693 | else | |
1694 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
ed498904 | 1695 | emit_insn (gen_rtx_SET (VOIDmode, |
1696 | replace_equiv_address (operand0, scratch_reg), | |
ad851752 | 1697 | operand1)); |
d6f01525 | 1698 | return 1; |
1699 | } | |
753bd06a | 1700 | /* Handle secondary reloads for loads of FP registers from constant |
1701 | expressions by forcing the constant into memory. | |
1702 | ||
6bcdc1fb | 1703 | Use scratch_reg to hold the address of the memory location. |
753bd06a | 1704 | |
0a5dd1a5 | 1705 | The proper fix is to change TARGET_PREFERRED_RELOAD_CLASS to return |
87fcb603 | 1706 | NO_REGS when presented with a const_int and a register class |
753bd06a | 1707 | containing only FP registers. Doing so unfortunately creates |
1708 | more problems than it solves. Fix this for 2.5. */ | |
6bcdc1fb | 1709 | else if (scratch_reg |
753bd06a | 1710 | && CONSTANT_P (operand1) |
6bcdc1fb | 1711 | && fp_reg_operand (operand0, mode)) |
753bd06a | 1712 | { |
ed498904 | 1713 | rtx const_mem, xoperands[2]; |
753bd06a | 1714 | |
f756078b | 1715 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1716 | it in WORD_MODE regardless of what mode it was originally given | |
1717 | to us. */ | |
9840d99d | 1718 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1719 | |
753bd06a | 1720 | /* Force the constant into memory and put the address of the |
1721 | memory location into scratch_reg. */ | |
ed498904 | 1722 | const_mem = force_const_mem (mode, operand1); |
753bd06a | 1723 | xoperands[0] = scratch_reg; |
ed498904 | 1724 | xoperands[1] = XEXP (const_mem, 0); |
8f258b49 | 1725 | emit_move_sequence (xoperands, Pmode, 0); |
753bd06a | 1726 | |
1727 | /* Now load the destination register. */ | |
7014838c | 1728 | emit_insn (gen_rtx_SET (mode, operand0, |
ed498904 | 1729 | replace_equiv_address (const_mem, scratch_reg))); |
753bd06a | 1730 | return 1; |
1731 | } | |
e8fdbafa | 1732 | /* Handle secondary reloads for SAR. These occur when trying to load |
5ddb2975 | 1733 | the SAR from memory or a constant. */ |
6bcdc1fb | 1734 | else if (scratch_reg |
1735 | && GET_CODE (operand0) == REG | |
2a170404 | 1736 | && REGNO (operand0) < FIRST_PSEUDO_REGISTER |
e8fdbafa | 1737 | && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS |
5ddb2975 | 1738 | && (GET_CODE (operand1) == MEM || GET_CODE (operand1) == CONST_INT)) |
e8fdbafa | 1739 | { |
7eac600c | 1740 | /* D might not fit in 14 bits either; for such cases load D into |
1741 | scratch reg. */ | |
1742 | if (GET_CODE (operand1) == MEM | |
853940d9 | 1743 | && !memory_address_p (GET_MODE (operand0), XEXP (operand1, 0))) |
7eac600c | 1744 | { |
fc4d127d | 1745 | /* We are reloading the address into the scratch register, so we |
1746 | want to make sure the scratch register is a full register. */ | |
9840d99d | 1747 | scratch_reg = force_mode (word_mode, scratch_reg); |
fc4d127d | 1748 | |
9840d99d | 1749 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); |
ad851752 | 1750 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, |
1751 | 0)), | |
440c23df | 1752 | Pmode, |
ad851752 | 1753 | XEXP (XEXP (operand1, 0), |
1754 | 0), | |
1755 | scratch_reg)); | |
fc4d127d | 1756 | |
1757 | /* Now we are going to load the scratch register from memory, | |
1758 | we want to load it in the same width as the original MEM, | |
1759 | which must be the same as the width of the ultimate destination, | |
1760 | OPERAND0. */ | |
9840d99d | 1761 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1762 | ||
ed498904 | 1763 | emit_move_insn (scratch_reg, |
1764 | replace_equiv_address (operand1, scratch_reg)); | |
7eac600c | 1765 | } |
1766 | else | |
fc4d127d | 1767 | { |
1768 | /* We want to load the scratch register using the same mode as | |
1769 | the ultimate destination. */ | |
9840d99d | 1770 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1771 | ||
fc4d127d | 1772 | emit_move_insn (scratch_reg, operand1); |
1773 | } | |
1774 | ||
1775 | /* And emit the insn to set the ultimate destination. We know that | |
1776 | the scratch register has the same mode as the destination at this | |
1777 | point. */ | |
e8fdbafa | 1778 | emit_move_insn (operand0, scratch_reg); |
1779 | return 1; | |
1780 | } | |
dbd3d89d | 1781 | /* Handle the most common case: storing into a register. */ |
d6f01525 | 1782 | else if (register_operand (operand0, mode)) |
87ad11b0 | 1783 | { |
f784d2ac | 1784 | /* Legitimize TLS symbol references. This happens for references |
1785 | that aren't a legitimate constant. */ | |
1786 | if (PA_SYMBOL_REF_TLS_P (operand1)) | |
1787 | operand1 = legitimize_tls_address (operand1); | |
1788 | ||
87ad11b0 | 1789 | if (register_operand (operand1, mode) |
93f6e1c7 | 1790 | || (GET_CODE (operand1) == CONST_INT |
1791 | && cint_ok_for_move (INTVAL (operand1))) | |
891b55b4 | 1792 | || (operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1793 | || (GET_CODE (operand1) == HIGH |
df0651dc | 1794 | && !symbolic_operand (XEXP (operand1, 0), VOIDmode)) |
87ad11b0 | 1795 | /* Only `general_operands' can come here, so MEM is ok. */ |
1796 | || GET_CODE (operand1) == MEM) | |
1797 | { | |
dbd3d89d | 1798 | /* Various sets are created during RTL generation which don't |
1799 | have the REG_POINTER flag correctly set. After the CSE pass, | |
1800 | instruction recognition can fail if we don't consistently | |
1801 | set this flag when performing register copies. This should | |
1802 | also improve the opportunities for creating insns that use | |
1803 | unscaled indexing. */ | |
1804 | if (REG_P (operand0) && REG_P (operand1)) | |
1805 | { | |
1806 | if (REG_POINTER (operand1) | |
1807 | && !REG_POINTER (operand0) | |
1808 | && !HARD_REGISTER_P (operand0)) | |
1809 | copy_reg_pointer (operand0, operand1); | |
dbd3d89d | 1810 | } |
1811 | ||
1812 | /* When MEMs are broken out, the REG_POINTER flag doesn't | |
1813 | get set. In some cases, we can set the REG_POINTER flag | |
1814 | from the declaration for the MEM. */ | |
1815 | if (REG_P (operand0) | |
1816 | && GET_CODE (operand1) == MEM | |
1817 | && !REG_POINTER (operand0)) | |
1818 | { | |
1819 | tree decl = MEM_EXPR (operand1); | |
1820 | ||
1821 | /* Set the register pointer flag and register alignment | |
1822 | if the declaration for this memory reference is a | |
4d41e927 | 1823 | pointer type. */ |
1824 | if (decl) | |
dbd3d89d | 1825 | { |
1826 | tree type; | |
1827 | ||
1828 | /* If this is a COMPONENT_REF, use the FIELD_DECL from | |
1829 | tree operand 1. */ | |
1830 | if (TREE_CODE (decl) == COMPONENT_REF) | |
1831 | decl = TREE_OPERAND (decl, 1); | |
1832 | ||
1833 | type = TREE_TYPE (decl); | |
eec9c06d | 1834 | type = strip_array_types (type); |
dbd3d89d | 1835 | |
1836 | if (POINTER_TYPE_P (type)) | |
1837 | { | |
1838 | int align; | |
1839 | ||
1840 | type = TREE_TYPE (type); | |
1841 | /* Using TYPE_ALIGN_OK is rather conservative as | |
1842 | only the ada frontend actually sets it. */ | |
1843 | align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type) | |
1844 | : BITS_PER_UNIT); | |
1845 | mark_reg_pointer (operand0, align); | |
1846 | } | |
1847 | } | |
1848 | } | |
1849 | ||
ad851752 | 1850 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1851 | return 1; |
1852 | } | |
1853 | } | |
1854 | else if (GET_CODE (operand0) == MEM) | |
1855 | { | |
85eb4c6e | 1856 | if (mode == DFmode && operand1 == CONST0_RTX (mode) |
1857 | && !(reload_in_progress || reload_completed)) | |
1858 | { | |
1859 | rtx temp = gen_reg_rtx (DFmode); | |
1860 | ||
ad851752 | 1861 | emit_insn (gen_rtx_SET (VOIDmode, temp, operand1)); |
1862 | emit_insn (gen_rtx_SET (VOIDmode, operand0, temp)); | |
85eb4c6e | 1863 | return 1; |
1864 | } | |
891b55b4 | 1865 | if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1866 | { |
1867 | /* Run this case quickly. */ | |
ad851752 | 1868 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1869 | return 1; |
1870 | } | |
2ff4bf8d | 1871 | if (! (reload_in_progress || reload_completed)) |
87ad11b0 | 1872 | { |
1873 | operands[0] = validize_mem (operand0); | |
1874 | operands[1] = operand1 = force_reg (mode, operand1); | |
1875 | } | |
1876 | } | |
1877 | ||
37a75d53 | 1878 | /* Simplify the source if we need to. |
1879 | Note we do have to handle function labels here, even though we do | |
1880 | not consider them legitimate constants. Loop optimizations can | |
bea60f66 | 1881 | call the emit_move_xxx with one as a source. */ |
57ed30e5 | 1882 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) |
39ec41d4 | 1883 | || function_label_operand (operand1, VOIDmode) |
2ee034bc | 1884 | || (GET_CODE (operand1) == HIGH |
63882853 | 1885 | && symbolic_operand (XEXP (operand1, 0), mode))) |
87ad11b0 | 1886 | { |
2ee034bc | 1887 | int ishighonly = 0; |
1888 | ||
1889 | if (GET_CODE (operand1) == HIGH) | |
1890 | { | |
1891 | ishighonly = 1; | |
1892 | operand1 = XEXP (operand1, 0); | |
1893 | } | |
87ad11b0 | 1894 | if (symbolic_operand (operand1, mode)) |
1895 | { | |
005a7dd0 | 1896 | /* Argh. The assembler and linker can't handle arithmetic |
81653f9b | 1897 | involving plabels. |
005a7dd0 | 1898 | |
81653f9b | 1899 | So we force the plabel into memory, load operand0 from |
1900 | the memory location, then add in the constant part. */ | |
37a75d53 | 1901 | if ((GET_CODE (operand1) == CONST |
1902 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
39ec41d4 | 1903 | && function_label_operand (XEXP (XEXP (operand1, 0), 0), |
1904 | VOIDmode)) | |
1905 | || function_label_operand (operand1, VOIDmode)) | |
005a7dd0 | 1906 | { |
b3d569a0 | 1907 | rtx temp, const_part; |
81653f9b | 1908 | |
1909 | /* Figure out what (if any) scratch register to use. */ | |
1910 | if (reload_in_progress || reload_completed) | |
f756078b | 1911 | { |
1912 | scratch_reg = scratch_reg ? scratch_reg : operand0; | |
1913 | /* SCRATCH_REG will hold an address and maybe the actual | |
1914 | data. We want it in WORD_MODE regardless of what mode it | |
1915 | was originally given to us. */ | |
9840d99d | 1916 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1917 | } |
81653f9b | 1918 | else if (flag_pic) |
1919 | scratch_reg = gen_reg_rtx (Pmode); | |
1920 | ||
37a75d53 | 1921 | if (GET_CODE (operand1) == CONST) |
1922 | { | |
1923 | /* Save away the constant part of the expression. */ | |
1924 | const_part = XEXP (XEXP (operand1, 0), 1); | |
ecf2283d | 1925 | gcc_assert (GET_CODE (const_part) == CONST_INT); |
37a75d53 | 1926 | |
1927 | /* Force the function label into memory. */ | |
1928 | temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0)); | |
1929 | } | |
1930 | else | |
1931 | { | |
1932 | /* No constant part. */ | |
1933 | const_part = NULL_RTX; | |
005a7dd0 | 1934 | |
37a75d53 | 1935 | /* Force the function label into memory. */ |
1936 | temp = force_const_mem (mode, operand1); | |
1937 | } | |
9840d99d | 1938 | |
81653f9b | 1939 | |
1940 | /* Get the address of the memory location. PIC-ify it if | |
1941 | necessary. */ | |
1942 | temp = XEXP (temp, 0); | |
1943 | if (flag_pic) | |
1944 | temp = legitimize_pic_address (temp, mode, scratch_reg); | |
1945 | ||
1946 | /* Put the address of the memory location into our destination | |
1947 | register. */ | |
1948 | operands[1] = temp; | |
1949 | emit_move_sequence (operands, mode, scratch_reg); | |
1950 | ||
1951 | /* Now load from the memory location into our destination | |
1952 | register. */ | |
ad851752 | 1953 | operands[1] = gen_rtx_MEM (Pmode, operands[0]); |
81653f9b | 1954 | emit_move_sequence (operands, mode, scratch_reg); |
1955 | ||
1956 | /* And add back in the constant part. */ | |
37a75d53 | 1957 | if (const_part != NULL_RTX) |
1958 | expand_inc (operand0, const_part); | |
81653f9b | 1959 | |
1960 | return 1; | |
005a7dd0 | 1961 | } |
1962 | ||
87ad11b0 | 1963 | if (flag_pic) |
1964 | { | |
2ff4bf8d | 1965 | rtx temp; |
1966 | ||
1967 | if (reload_in_progress || reload_completed) | |
f756078b | 1968 | { |
1969 | temp = scratch_reg ? scratch_reg : operand0; | |
1970 | /* TEMP will hold an address and maybe the actual | |
1971 | data. We want it in WORD_MODE regardless of what mode it | |
1972 | was originally given to us. */ | |
9840d99d | 1973 | temp = force_mode (word_mode, temp); |
f756078b | 1974 | } |
2ff4bf8d | 1975 | else |
1976 | temp = gen_reg_rtx (Pmode); | |
6d36483b | 1977 | |
81653f9b | 1978 | /* (const (plus (symbol) (const_int))) must be forced to |
1979 | memory during/after reload if the const_int will not fit | |
1980 | in 14 bits. */ | |
1981 | if (GET_CODE (operand1) == CONST | |
96b86ab6 | 1982 | && GET_CODE (XEXP (operand1, 0)) == PLUS |
1983 | && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT | |
1984 | && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)) | |
1985 | && (reload_completed || reload_in_progress) | |
1986 | && flag_pic) | |
1987 | { | |
ed498904 | 1988 | rtx const_mem = force_const_mem (mode, operand1); |
4109fd6d | 1989 | operands[1] = legitimize_pic_address (XEXP (const_mem, 0), |
96b86ab6 | 1990 | mode, temp); |
ed498904 | 1991 | operands[1] = replace_equiv_address (const_mem, operands[1]); |
96b86ab6 | 1992 | emit_move_sequence (operands, mode, temp); |
1993 | } | |
005a7dd0 | 1994 | else |
1995 | { | |
1996 | operands[1] = legitimize_pic_address (operand1, mode, temp); | |
dbd3d89d | 1997 | if (REG_P (operand0) && REG_P (operands[1])) |
1998 | copy_reg_pointer (operand0, operands[1]); | |
ad851752 | 1999 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1])); |
005a7dd0 | 2000 | } |
87ad11b0 | 2001 | } |
b4a7bf10 | 2002 | /* On the HPPA, references to data space are supposed to use dp, |
2003 | register 27, but showing it in the RTL inhibits various cse | |
2004 | and loop optimizations. */ | |
6d36483b | 2005 | else |
87ad11b0 | 2006 | { |
005a7dd0 | 2007 | rtx temp, set; |
2ee034bc | 2008 | |
6d36483b | 2009 | if (reload_in_progress || reload_completed) |
f756078b | 2010 | { |
2011 | temp = scratch_reg ? scratch_reg : operand0; | |
2012 | /* TEMP will hold an address and maybe the actual | |
2013 | data. We want it in WORD_MODE regardless of what mode it | |
2014 | was originally given to us. */ | |
9840d99d | 2015 | temp = force_mode (word_mode, temp); |
f756078b | 2016 | } |
2ee034bc | 2017 | else |
2018 | temp = gen_reg_rtx (mode); | |
2019 | ||
42819d4e | 2020 | /* Loading a SYMBOL_REF into a register makes that register |
9840d99d | 2021 | safe to be used as the base in an indexed address. |
42819d4e | 2022 | |
2023 | Don't mark hard registers though. That loses. */ | |
47a61b79 | 2024 | if (GET_CODE (operand0) == REG |
2025 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
dbd3d89d | 2026 | mark_reg_pointer (operand0, BITS_PER_UNIT); |
42819d4e | 2027 | if (REGNO (temp) >= FIRST_PSEUDO_REGISTER) |
dbd3d89d | 2028 | mark_reg_pointer (temp, BITS_PER_UNIT); |
2029 | ||
2ee034bc | 2030 | if (ishighonly) |
ad851752 | 2031 | set = gen_rtx_SET (mode, operand0, temp); |
2ee034bc | 2032 | else |
7014838c | 2033 | set = gen_rtx_SET (VOIDmode, |
2034 | operand0, | |
ad851752 | 2035 | gen_rtx_LO_SUM (mode, temp, operand1)); |
6d36483b | 2036 | |
ad851752 | 2037 | emit_insn (gen_rtx_SET (VOIDmode, |
2038 | temp, | |
2039 | gen_rtx_HIGH (mode, operand1))); | |
d2498717 | 2040 | emit_insn (set); |
166bf021 | 2041 | |
87ad11b0 | 2042 | } |
2ee034bc | 2043 | return 1; |
87ad11b0 | 2044 | } |
716b2c5a | 2045 | else if (pa_tls_referenced_p (operand1)) |
2046 | { | |
2047 | rtx tmp = operand1; | |
2048 | rtx addend = NULL; | |
2049 | ||
2050 | if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS) | |
2051 | { | |
2052 | addend = XEXP (XEXP (tmp, 0), 1); | |
2053 | tmp = XEXP (XEXP (tmp, 0), 0); | |
2054 | } | |
2055 | ||
2056 | gcc_assert (GET_CODE (tmp) == SYMBOL_REF); | |
2057 | tmp = legitimize_tls_address (tmp); | |
2058 | if (addend) | |
2059 | { | |
2060 | tmp = gen_rtx_PLUS (mode, tmp, addend); | |
2061 | tmp = force_operand (tmp, operands[0]); | |
2062 | } | |
2063 | operands[1] = tmp; | |
2064 | } | |
42faba01 | 2065 | else if (GET_CODE (operand1) != CONST_INT |
6bcdc1fb | 2066 | || !cint_ok_for_move (INTVAL (operand1))) |
87ad11b0 | 2067 | { |
6bcdc1fb | 2068 | rtx insn, temp; |
2069 | rtx op1 = operand1; | |
6edde44b | 2070 | HOST_WIDE_INT value = 0; |
6bcdc1fb | 2071 | HOST_WIDE_INT insv = 0; |
2072 | int insert = 0; | |
2073 | ||
6edde44b | 2074 | if (GET_CODE (operand1) == CONST_INT) |
2075 | value = INTVAL (operand1); | |
2076 | ||
6bcdc1fb | 2077 | if (TARGET_64BIT |
2078 | && GET_CODE (operand1) == CONST_INT | |
b7d86581 | 2079 | && HOST_BITS_PER_WIDE_INT > 32 |
5e3c5739 | 2080 | && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32) |
2081 | { | |
b7d86581 | 2082 | HOST_WIDE_INT nval; |
5e3c5739 | 2083 | |
93f6e1c7 | 2084 | /* Extract the low order 32 bits of the value and sign extend. |
2085 | If the new value is the same as the original value, we can | |
2086 | can use the original value as-is. If the new value is | |
2087 | different, we use it and insert the most-significant 32-bits | |
2088 | of the original value into the final result. */ | |
6bcdc1fb | 2089 | nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1)) |
b7d86581 | 2090 | ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31); |
6bcdc1fb | 2091 | if (value != nval) |
5e3c5739 | 2092 | { |
93f6e1c7 | 2093 | #if HOST_BITS_PER_WIDE_INT > 32 |
6bcdc1fb | 2094 | insv = value >= 0 ? value >> 32 : ~(~value >> 32); |
93f6e1c7 | 2095 | #endif |
6bcdc1fb | 2096 | insert = 1; |
2097 | value = nval; | |
5e3c5739 | 2098 | operand1 = GEN_INT (nval); |
2099 | } | |
2100 | } | |
2ff4bf8d | 2101 | |
2102 | if (reload_in_progress || reload_completed) | |
6bcdc1fb | 2103 | temp = scratch_reg ? scratch_reg : operand0; |
2ff4bf8d | 2104 | else |
2105 | temp = gen_reg_rtx (mode); | |
2106 | ||
7c4d3047 | 2107 | /* We don't directly split DImode constants on 32-bit targets |
2108 | because PLUS uses an 11-bit immediate and the insn sequence | |
2109 | generated is not as efficient as the one using HIGH/LO_SUM. */ | |
2110 | if (GET_CODE (operand1) == CONST_INT | |
58cac6ba | 2111 | && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD |
6bcdc1fb | 2112 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
2113 | && !insert) | |
93f6e1c7 | 2114 | { |
7c4d3047 | 2115 | /* Directly break constant into high and low parts. This |
93f6e1c7 | 2116 | provides better optimization opportunities because various |
2117 | passes recognize constants split with PLUS but not LO_SUM. | |
2118 | We use a 14-bit signed low part except when the addition | |
2119 | of 0x4000 to the high part might change the sign of the | |
2120 | high part. */ | |
93f6e1c7 | 2121 | HOST_WIDE_INT low = value & 0x3fff; |
2122 | HOST_WIDE_INT high = value & ~ 0x3fff; | |
2123 | ||
2124 | if (low >= 0x2000) | |
2125 | { | |
2126 | if (high == 0x7fffc000 || (mode == HImode && high == 0x4000)) | |
2127 | high += 0x2000; | |
2128 | else | |
2129 | high += 0x4000; | |
2130 | } | |
2131 | ||
2132 | low = value - high; | |
5e3c5739 | 2133 | |
93f6e1c7 | 2134 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high))); |
2135 | operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low)); | |
2136 | } | |
2137 | else | |
5e3c5739 | 2138 | { |
93f6e1c7 | 2139 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
2140 | gen_rtx_HIGH (mode, operand1))); | |
2141 | operands[1] = gen_rtx_LO_SUM (mode, temp, operand1); | |
5e3c5739 | 2142 | } |
9840d99d | 2143 | |
6bcdc1fb | 2144 | insn = emit_move_insn (operands[0], operands[1]); |
2145 | ||
2146 | /* Now insert the most significant 32 bits of the value | |
2147 | into the register. When we don't have a second register | |
2148 | available, it could take up to nine instructions to load | |
2149 | a 64-bit integer constant. Prior to reload, we force | |
2150 | constants that would take more than three instructions | |
2151 | to load to the constant pool. During and after reload, | |
2152 | we have to handle all possible values. */ | |
2153 | if (insert) | |
2154 | { | |
2155 | /* Use a HIGH/LO_SUM/INSV sequence if we have a second | |
2156 | register and the value to be inserted is outside the | |
2157 | range that can be loaded with three depdi instructions. */ | |
2158 | if (temp != operand0 && (insv >= 16384 || insv < -16384)) | |
2159 | { | |
2160 | operand1 = GEN_INT (insv); | |
2161 | ||
2162 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
2163 | gen_rtx_HIGH (mode, operand1))); | |
2164 | emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1)); | |
2165 | emit_insn (gen_insv (operand0, GEN_INT (32), | |
2166 | const0_rtx, temp)); | |
2167 | } | |
2168 | else | |
2169 | { | |
2170 | int len = 5, pos = 27; | |
2171 | ||
2172 | /* Insert the bits using the depdi instruction. */ | |
2173 | while (pos >= 0) | |
2174 | { | |
2175 | HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16; | |
2176 | HOST_WIDE_INT sign = v5 < 0; | |
2177 | ||
2178 | /* Left extend the insertion. */ | |
2179 | insv = (insv >= 0 ? insv >> len : ~(~insv >> len)); | |
2180 | while (pos > 0 && (insv & 1) == sign) | |
2181 | { | |
2182 | insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1)); | |
2183 | len += 1; | |
2184 | pos -= 1; | |
2185 | } | |
2186 | ||
2187 | emit_insn (gen_insv (operand0, GEN_INT (len), | |
2188 | GEN_INT (pos), GEN_INT (v5))); | |
2189 | ||
2190 | len = pos > 0 && pos < 5 ? pos : 5; | |
2191 | pos -= len; | |
2192 | } | |
2193 | } | |
2194 | } | |
93f6e1c7 | 2195 | |
24153880 | 2196 | set_unique_reg_note (insn, REG_EQUAL, op1); |
93f6e1c7 | 2197 | |
5e3c5739 | 2198 | return 1; |
87ad11b0 | 2199 | } |
2200 | } | |
2201 | /* Now have insn-emit do whatever it normally does. */ | |
2202 | return 0; | |
2203 | } | |
2204 | ||
1946138e | 2205 | /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning |
bd49d362 | 2206 | it will need a link/runtime reloc). */ |
1946138e | 2207 | |
2208 | int | |
5c1d8983 | 2209 | reloc_needed (tree exp) |
1946138e | 2210 | { |
2211 | int reloc = 0; | |
2212 | ||
2213 | switch (TREE_CODE (exp)) | |
2214 | { | |
2215 | case ADDR_EXPR: | |
2216 | return 1; | |
2217 | ||
0de36bdb | 2218 | case POINTER_PLUS_EXPR: |
1946138e | 2219 | case PLUS_EXPR: |
2220 | case MINUS_EXPR: | |
2221 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
2222 | reloc |= reloc_needed (TREE_OPERAND (exp, 1)); | |
2223 | break; | |
2224 | ||
72dd6141 | 2225 | CASE_CONVERT: |
1946138e | 2226 | case NON_LVALUE_EXPR: |
2227 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
2228 | break; | |
2229 | ||
2230 | case CONSTRUCTOR: | |
2231 | { | |
729d4a82 | 2232 | tree value; |
2233 | unsigned HOST_WIDE_INT ix; | |
2234 | ||
2235 | FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value) | |
2236 | if (value) | |
2237 | reloc |= reloc_needed (value); | |
1946138e | 2238 | } |
2239 | break; | |
2240 | ||
2241 | case ERROR_MARK: | |
2242 | break; | |
7d27e4c9 | 2243 | |
2244 | default: | |
2245 | break; | |
1946138e | 2246 | } |
2247 | return reloc; | |
2248 | } | |
2249 | ||
87ad11b0 | 2250 | \f |
2251 | /* Return the best assembler insn template | |
5aedf60c | 2252 | for moving operands[1] into operands[0] as a fullword. */ |
611a88e1 | 2253 | const char * |
5c1d8983 | 2254 | singlemove_string (rtx *operands) |
87ad11b0 | 2255 | { |
3745c59b | 2256 | HOST_WIDE_INT intval; |
2257 | ||
87ad11b0 | 2258 | if (GET_CODE (operands[0]) == MEM) |
2259 | return "stw %r1,%0"; | |
3745c59b | 2260 | if (GET_CODE (operands[1]) == MEM) |
87ad11b0 | 2261 | return "ldw %1,%0"; |
3745c59b | 2262 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
9d5108ea | 2263 | { |
3745c59b | 2264 | long i; |
2265 | REAL_VALUE_TYPE d; | |
9d5108ea | 2266 | |
ecf2283d | 2267 | gcc_assert (GET_MODE (operands[1]) == SFmode); |
9d5108ea | 2268 | |
3745c59b | 2269 | /* Translate the CONST_DOUBLE to a CONST_INT with the same target |
2270 | bit pattern. */ | |
2271 | REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]); | |
2272 | REAL_VALUE_TO_TARGET_SINGLE (d, i); | |
9d5108ea | 2273 | |
3745c59b | 2274 | operands[1] = GEN_INT (i); |
2275 | /* Fall through to CONST_INT case. */ | |
2276 | } | |
2277 | if (GET_CODE (operands[1]) == CONST_INT) | |
9d5108ea | 2278 | { |
3745c59b | 2279 | intval = INTVAL (operands[1]); |
2280 | ||
2281 | if (VAL_14_BITS_P (intval)) | |
2282 | return "ldi %1,%0"; | |
2283 | else if ((intval & 0x7ff) == 0) | |
2284 | return "ldil L'%1,%0"; | |
2285 | else if (zdepi_cint_p (intval)) | |
e4065f95 | 2286 | return "{zdepi %Z1,%0|depwi,z %Z1,%0}"; |
9d5108ea | 2287 | else |
2288 | return "ldil L'%1,%0\n\tldo R'%1(%0),%0"; | |
2289 | } | |
87ad11b0 | 2290 | return "copy %1,%0"; |
2291 | } | |
2292 | \f | |
2293 | ||
201f01e9 | 2294 | /* Compute position (in OP[1]) and width (in OP[2]) |
2295 | useful for copying IMM to a register using the zdepi | |
2296 | instructions. Store the immediate value to insert in OP[0]. */ | |
611a88e1 | 2297 | static void |
5c1d8983 | 2298 | compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
7e10ba53 | 2299 | { |
e057641f | 2300 | int lsb, len; |
7e10ba53 | 2301 | |
e057641f | 2302 | /* Find the least significant set bit in IMM. */ |
2303 | for (lsb = 0; lsb < 32; lsb++) | |
7e10ba53 | 2304 | { |
e057641f | 2305 | if ((imm & 1) != 0) |
7e10ba53 | 2306 | break; |
e057641f | 2307 | imm >>= 1; |
7e10ba53 | 2308 | } |
2309 | ||
e057641f | 2310 | /* Choose variants based on *sign* of the 5-bit field. */ |
2311 | if ((imm & 0x10) == 0) | |
2312 | len = (lsb <= 28) ? 4 : 32 - lsb; | |
7e10ba53 | 2313 | else |
2314 | { | |
e057641f | 2315 | /* Find the width of the bitstring in IMM. */ |
eab96f1c | 2316 | for (len = 5; len < 32 - lsb; len++) |
7e10ba53 | 2317 | { |
eab96f1c | 2318 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
7e10ba53 | 2319 | break; |
7e10ba53 | 2320 | } |
2321 | ||
e057641f | 2322 | /* Sign extend IMM as a 5-bit value. */ |
2323 | imm = (imm & 0xf) - 0x10; | |
7e10ba53 | 2324 | } |
2325 | ||
42faba01 | 2326 | op[0] = imm; |
2327 | op[1] = 31 - lsb; | |
2328 | op[2] = len; | |
7e10ba53 | 2329 | } |
2330 | ||
5e3c5739 | 2331 | /* Compute position (in OP[1]) and width (in OP[2]) |
2332 | useful for copying IMM to a register using the depdi,z | |
2333 | instructions. Store the immediate value to insert in OP[0]. */ | |
2334 | void | |
5c1d8983 | 2335 | compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
5e3c5739 | 2336 | { |
eab96f1c | 2337 | int lsb, len, maxlen; |
2338 | ||
2339 | maxlen = MIN (HOST_BITS_PER_WIDE_INT, 64); | |
5e3c5739 | 2340 | |
2341 | /* Find the least significant set bit in IMM. */ | |
eab96f1c | 2342 | for (lsb = 0; lsb < maxlen; lsb++) |
5e3c5739 | 2343 | { |
2344 | if ((imm & 1) != 0) | |
2345 | break; | |
2346 | imm >>= 1; | |
2347 | } | |
2348 | ||
2349 | /* Choose variants based on *sign* of the 5-bit field. */ | |
2350 | if ((imm & 0x10) == 0) | |
eab96f1c | 2351 | len = (lsb <= maxlen - 4) ? 4 : maxlen - lsb; |
5e3c5739 | 2352 | else |
2353 | { | |
2354 | /* Find the width of the bitstring in IMM. */ | |
eab96f1c | 2355 | for (len = 5; len < maxlen - lsb; len++) |
5e3c5739 | 2356 | { |
ea52c577 | 2357 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
5e3c5739 | 2358 | break; |
2359 | } | |
2360 | ||
eab96f1c | 2361 | /* Extend length if host is narrow and IMM is negative. */ |
2362 | if (HOST_BITS_PER_WIDE_INT == 32 && len == maxlen - lsb) | |
2363 | len += 32; | |
2364 | ||
5e3c5739 | 2365 | /* Sign extend IMM as a 5-bit value. */ |
2366 | imm = (imm & 0xf) - 0x10; | |
2367 | } | |
2368 | ||
2369 | op[0] = imm; | |
2370 | op[1] = 63 - lsb; | |
2371 | op[2] = len; | |
2372 | } | |
2373 | ||
87ad11b0 | 2374 | /* Output assembler code to perform a doubleword move insn |
2375 | with operands OPERANDS. */ | |
2376 | ||
611a88e1 | 2377 | const char * |
5c1d8983 | 2378 | output_move_double (rtx *operands) |
87ad11b0 | 2379 | { |
2380 | enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1; | |
2381 | rtx latehalf[2]; | |
2382 | rtx addreg0 = 0, addreg1 = 0; | |
2383 | ||
2384 | /* First classify both operands. */ | |
2385 | ||
2386 | if (REG_P (operands[0])) | |
2387 | optype0 = REGOP; | |
2388 | else if (offsettable_memref_p (operands[0])) | |
2389 | optype0 = OFFSOP; | |
2390 | else if (GET_CODE (operands[0]) == MEM) | |
2391 | optype0 = MEMOP; | |
2392 | else | |
2393 | optype0 = RNDOP; | |
2394 | ||
2395 | if (REG_P (operands[1])) | |
2396 | optype1 = REGOP; | |
2397 | else if (CONSTANT_P (operands[1])) | |
2398 | optype1 = CNSTOP; | |
2399 | else if (offsettable_memref_p (operands[1])) | |
2400 | optype1 = OFFSOP; | |
2401 | else if (GET_CODE (operands[1]) == MEM) | |
2402 | optype1 = MEMOP; | |
2403 | else | |
2404 | optype1 = RNDOP; | |
2405 | ||
2406 | /* Check for the cases that the operand constraints are not | |
ecf2283d | 2407 | supposed to allow to happen. */ |
2408 | gcc_assert (optype0 == REGOP || optype1 == REGOP); | |
87ad11b0 | 2409 | |
e106b699 | 2410 | /* Handle copies between general and floating registers. */ |
2411 | ||
2412 | if (optype0 == REGOP && optype1 == REGOP | |
2413 | && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])) | |
2414 | { | |
2415 | if (FP_REG_P (operands[0])) | |
2416 | { | |
2417 | output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands); | |
2418 | output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands); | |
2419 | return "{fldds|fldd} -16(%%sp),%0"; | |
2420 | } | |
2421 | else | |
2422 | { | |
2423 | output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands); | |
2424 | output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands); | |
2425 | return "{ldws|ldw} -12(%%sp),%R0"; | |
2426 | } | |
2427 | } | |
2428 | ||
87ad11b0 | 2429 | /* Handle auto decrementing and incrementing loads and stores |
2430 | specifically, since the structure of the function doesn't work | |
2431 | for them without major modification. Do it better when we learn | |
2432 | this port about the general inc/dec addressing of PA. | |
2433 | (This was written by tege. Chide him if it doesn't work.) */ | |
2434 | ||
2435 | if (optype0 == MEMOP) | |
2436 | { | |
1df0058a | 2437 | /* We have to output the address syntax ourselves, since print_operand |
2438 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2439 | ||
87ad11b0 | 2440 | rtx addr = XEXP (operands[0], 0); |
1df0058a | 2441 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) |
87ad11b0 | 2442 | { |
ad851752 | 2443 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2444 | |
2445 | operands[0] = XEXP (addr, 0); | |
ecf2283d | 2446 | gcc_assert (GET_CODE (operands[1]) == REG |
2447 | && GET_CODE (operands[0]) == REG); | |
1df0058a | 2448 | |
ecf2283d | 2449 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); |
2450 | ||
2451 | /* No overlap between high target register and address | |
2452 | register. (We do this in a non-obvious way to | |
2453 | save a register file writeback) */ | |
2454 | if (GET_CODE (addr) == POST_INC) | |
2455 | return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)"; | |
2456 | return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)"; | |
a3217f65 | 2457 | } |
1df0058a | 2458 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) |
a3217f65 | 2459 | { |
ad851752 | 2460 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2461 | |
2462 | operands[0] = XEXP (addr, 0); | |
ecf2283d | 2463 | gcc_assert (GET_CODE (operands[1]) == REG |
2464 | && GET_CODE (operands[0]) == REG); | |
2465 | ||
2466 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); | |
2467 | /* No overlap between high target register and address | |
2468 | register. (We do this in a non-obvious way to save a | |
2469 | register file writeback) */ | |
2470 | if (GET_CODE (addr) == PRE_INC) | |
2471 | return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)"; | |
2472 | return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)"; | |
87ad11b0 | 2473 | } |
2474 | } | |
2475 | if (optype1 == MEMOP) | |
2476 | { | |
2477 | /* We have to output the address syntax ourselves, since print_operand | |
2478 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2479 | ||
2480 | rtx addr = XEXP (operands[1], 0); | |
2481 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) | |
2482 | { | |
ad851752 | 2483 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2484 | |
2485 | operands[1] = XEXP (addr, 0); | |
ecf2283d | 2486 | gcc_assert (GET_CODE (operands[0]) == REG |
2487 | && GET_CODE (operands[1]) == REG); | |
87ad11b0 | 2488 | |
2489 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2490 | { | |
2491 | /* No overlap between high target register and address | |
3857fa62 | 2492 | register. (We do this in a non-obvious way to |
87ad11b0 | 2493 | save a register file writeback) */ |
2494 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2495 | return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0"; |
01fd4b49 | 2496 | return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0"; |
87ad11b0 | 2497 | } |
2498 | else | |
2499 | { | |
2500 | /* This is an undefined situation. We should load into the | |
2501 | address register *and* update that register. Probably | |
2502 | we don't need to handle this at all. */ | |
2503 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2504 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0"; |
2505 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0"; | |
87ad11b0 | 2506 | } |
2507 | } | |
2508 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) | |
2509 | { | |
ad851752 | 2510 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2511 | |
2512 | operands[1] = XEXP (addr, 0); | |
ecf2283d | 2513 | gcc_assert (GET_CODE (operands[0]) == REG |
2514 | && GET_CODE (operands[1]) == REG); | |
87ad11b0 | 2515 | |
2516 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2517 | { | |
2518 | /* No overlap between high target register and address | |
3857fa62 | 2519 | register. (We do this in a non-obvious way to |
87ad11b0 | 2520 | save a register file writeback) */ |
2521 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2522 | return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0"; |
2523 | return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0"; | |
87ad11b0 | 2524 | } |
2525 | else | |
2526 | { | |
2527 | /* This is an undefined situation. We should load into the | |
2528 | address register *and* update that register. Probably | |
2529 | we don't need to handle this at all. */ | |
2530 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2531 | return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0"; |
2532 | return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0"; | |
87ad11b0 | 2533 | } |
2534 | } | |
12b02046 | 2535 | else if (GET_CODE (addr) == PLUS |
2536 | && GET_CODE (XEXP (addr, 0)) == MULT) | |
2537 | { | |
b2f8bd14 | 2538 | rtx xoperands[4]; |
ad851752 | 2539 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
12b02046 | 2540 | |
2541 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2542 | { | |
12b02046 | 2543 | xoperands[0] = high_reg; |
2544 | xoperands[1] = XEXP (addr, 1); | |
2545 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2546 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2547 | output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}", |
2548 | xoperands); | |
34940871 | 2549 | return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; |
12b02046 | 2550 | } |
2551 | else | |
2552 | { | |
12b02046 | 2553 | xoperands[0] = high_reg; |
2554 | xoperands[1] = XEXP (addr, 1); | |
2555 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2556 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2557 | output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}", |
2558 | xoperands); | |
34940871 | 2559 | return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0"; |
12b02046 | 2560 | } |
12b02046 | 2561 | } |
87ad11b0 | 2562 | } |
2563 | ||
2564 | /* If an operand is an unoffsettable memory ref, find a register | |
2565 | we can increment temporarily to make it refer to the second word. */ | |
2566 | ||
2567 | if (optype0 == MEMOP) | |
2568 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2569 | ||
2570 | if (optype1 == MEMOP) | |
2571 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2572 | ||
2573 | /* Ok, we can do one word at a time. | |
2574 | Normally we do the low-numbered word first. | |
2575 | ||
2576 | In either case, set up in LATEHALF the operands to use | |
2577 | for the high-numbered word and in some cases alter the | |
2578 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2579 | ||
2580 | if (optype0 == REGOP) | |
ad851752 | 2581 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
87ad11b0 | 2582 | else if (optype0 == OFFSOP) |
eafc6604 | 2583 | latehalf[0] = adjust_address (operands[0], SImode, 4); |
87ad11b0 | 2584 | else |
2585 | latehalf[0] = operands[0]; | |
2586 | ||
2587 | if (optype1 == REGOP) | |
ad851752 | 2588 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
87ad11b0 | 2589 | else if (optype1 == OFFSOP) |
eafc6604 | 2590 | latehalf[1] = adjust_address (operands[1], SImode, 4); |
87ad11b0 | 2591 | else if (optype1 == CNSTOP) |
2592 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2593 | else | |
2594 | latehalf[1] = operands[1]; | |
2595 | ||
2596 | /* If the first move would clobber the source of the second one, | |
2597 | do them in the other order. | |
2598 | ||
cf489d53 | 2599 | This can happen in two cases: |
87ad11b0 | 2600 | |
cf489d53 | 2601 | mem -> register where the first half of the destination register |
2602 | is the same register used in the memory's address. Reload | |
2603 | can create such insns. | |
87ad11b0 | 2604 | |
cf489d53 | 2605 | mem in this case will be either register indirect or register |
9840d99d | 2606 | indirect plus a valid offset. |
cf489d53 | 2607 | |
2608 | register -> register move where REGNO(dst) == REGNO(src + 1) | |
9840d99d | 2609 | someone (Tim/Tege?) claimed this can happen for parameter loads. |
cf489d53 | 2610 | |
2611 | Handle mem -> register case first. */ | |
2612 | if (optype0 == REGOP | |
2613 | && (optype1 == MEMOP || optype1 == OFFSOP) | |
2614 | && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2615 | operands[1], 0)) | |
87ad11b0 | 2616 | { |
87ad11b0 | 2617 | /* Do the late half first. */ |
2618 | if (addreg1) | |
6a5d085a | 2619 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2620 | output_asm_insn (singlemove_string (latehalf), latehalf); |
cf489d53 | 2621 | |
2622 | /* Then clobber. */ | |
87ad11b0 | 2623 | if (addreg1) |
6a5d085a | 2624 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2625 | return singlemove_string (operands); |
2626 | } | |
2627 | ||
cf489d53 | 2628 | /* Now handle register -> register case. */ |
c4fa5937 | 2629 | if (optype0 == REGOP && optype1 == REGOP |
2630 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
2631 | { | |
2632 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2633 | return singlemove_string (operands); | |
2634 | } | |
2635 | ||
87ad11b0 | 2636 | /* Normal case: do the two words, low-numbered first. */ |
2637 | ||
2638 | output_asm_insn (singlemove_string (operands), operands); | |
2639 | ||
2640 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2641 | if (addreg0) | |
6a5d085a | 2642 | output_asm_insn ("ldo 4(%0),%0", &addreg0); |
87ad11b0 | 2643 | if (addreg1) |
6a5d085a | 2644 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2645 | |
2646 | /* Do that word. */ | |
2647 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2648 | ||
2649 | /* Undo the adds we just did. */ | |
2650 | if (addreg0) | |
6a5d085a | 2651 | output_asm_insn ("ldo -4(%0),%0", &addreg0); |
87ad11b0 | 2652 | if (addreg1) |
6a5d085a | 2653 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2654 | |
2655 | return ""; | |
2656 | } | |
2657 | \f | |
611a88e1 | 2658 | const char * |
5c1d8983 | 2659 | output_fp_move_double (rtx *operands) |
87ad11b0 | 2660 | { |
2661 | if (FP_REG_P (operands[0])) | |
2662 | { | |
6d36483b | 2663 | if (FP_REG_P (operands[1]) |
891b55b4 | 2664 | || operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
c6ae275c | 2665 | output_asm_insn ("fcpy,dbl %f1,%0", operands); |
6d36483b | 2666 | else |
27ef382d | 2667 | output_asm_insn ("fldd%F1 %1,%0", operands); |
87ad11b0 | 2668 | } |
2669 | else if (FP_REG_P (operands[1])) | |
2670 | { | |
27ef382d | 2671 | output_asm_insn ("fstd%F0 %1,%0", operands); |
87ad11b0 | 2672 | } |
ecf2283d | 2673 | else |
891b55b4 | 2674 | { |
ecf2283d | 2675 | rtx xoperands[2]; |
2676 | ||
2677 | gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0]))); | |
2678 | ||
6d36483b | 2679 | /* This is a pain. You have to be prepared to deal with an |
01cc3b75 | 2680 | arbitrary address here including pre/post increment/decrement. |
891b55b4 | 2681 | |
2682 | so avoid this in the MD. */ | |
ecf2283d | 2683 | gcc_assert (GET_CODE (operands[0]) == REG); |
2684 | ||
2685 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2686 | xoperands[0] = operands[0]; | |
2687 | output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands); | |
891b55b4 | 2688 | } |
87ad11b0 | 2689 | return ""; |
2690 | } | |
2691 | \f | |
2692 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2693 | ADDR can be effectively incremented by incrementing REG. */ | |
2694 | ||
2695 | static rtx | |
5c1d8983 | 2696 | find_addr_reg (rtx addr) |
87ad11b0 | 2697 | { |
2698 | while (GET_CODE (addr) == PLUS) | |
2699 | { | |
2700 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2701 | addr = XEXP (addr, 0); | |
2702 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2703 | addr = XEXP (addr, 1); | |
2704 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2705 | addr = XEXP (addr, 1); | |
2706 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2707 | addr = XEXP (addr, 0); | |
2708 | else | |
ecf2283d | 2709 | gcc_unreachable (); |
87ad11b0 | 2710 | } |
ecf2283d | 2711 | gcc_assert (GET_CODE (addr) == REG); |
2712 | return addr; | |
87ad11b0 | 2713 | } |
2714 | ||
87ad11b0 | 2715 | /* Emit code to perform a block move. |
2716 | ||
87ad11b0 | 2717 | OPERANDS[0] is the destination pointer as a REG, clobbered. |
2718 | OPERANDS[1] is the source pointer as a REG, clobbered. | |
42819d4e | 2719 | OPERANDS[2] is a register for temporary storage. |
87ad11b0 | 2720 | OPERANDS[3] is a register for temporary storage. |
a7e1bb24 | 2721 | OPERANDS[4] is the size as a CONST_INT |
9840d99d | 2722 | OPERANDS[5] is the alignment safe to use, as a CONST_INT. |
5aedf60c | 2723 | OPERANDS[6] is another temporary register. */ |
87ad11b0 | 2724 | |
611a88e1 | 2725 | const char * |
5c1d8983 | 2726 | output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) |
87ad11b0 | 2727 | { |
2728 | int align = INTVAL (operands[5]); | |
42819d4e | 2729 | unsigned long n_bytes = INTVAL (operands[4]); |
87ad11b0 | 2730 | |
a7e1bb24 | 2731 | /* We can't move more than a word at a time because the PA |
87ad11b0 | 2732 | has no longer integer move insns. (Could use fp mem ops?) */ |
a7e1bb24 | 2733 | if (align > (TARGET_64BIT ? 8 : 4)) |
2734 | align = (TARGET_64BIT ? 8 : 4); | |
87ad11b0 | 2735 | |
42819d4e | 2736 | /* Note that we know each loop below will execute at least twice |
2737 | (else we would have open-coded the copy). */ | |
2738 | switch (align) | |
87ad11b0 | 2739 | { |
a7e1bb24 | 2740 | case 8: |
2741 | /* Pre-adjust the loop counter. */ | |
2742 | operands[4] = GEN_INT (n_bytes - 16); | |
2743 | output_asm_insn ("ldi %4,%2", operands); | |
2744 | ||
2745 | /* Copying loop. */ | |
2746 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2747 | output_asm_insn ("ldd,ma 8(%1),%6", operands); | |
2748 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2749 | output_asm_insn ("addib,>= -16,%2,.-12", operands); | |
2750 | output_asm_insn ("std,ma %6,8(%0)", operands); | |
2751 | ||
2752 | /* Handle the residual. There could be up to 7 bytes of | |
2753 | residual to copy! */ | |
2754 | if (n_bytes % 16 != 0) | |
2755 | { | |
2756 | operands[4] = GEN_INT (n_bytes % 8); | |
2757 | if (n_bytes % 16 >= 8) | |
2758 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2759 | if (n_bytes % 8 != 0) | |
2760 | output_asm_insn ("ldd 0(%1),%6", operands); | |
2761 | if (n_bytes % 16 >= 8) | |
2762 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2763 | if (n_bytes % 8 != 0) | |
2764 | output_asm_insn ("stdby,e %6,%4(%0)", operands); | |
2765 | } | |
2766 | return ""; | |
2767 | ||
42819d4e | 2768 | case 4: |
2769 | /* Pre-adjust the loop counter. */ | |
2770 | operands[4] = GEN_INT (n_bytes - 8); | |
2771 | output_asm_insn ("ldi %4,%2", operands); | |
2772 | ||
2773 | /* Copying loop. */ | |
e4065f95 | 2774 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
2775 | output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands); | |
2776 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); | |
42819d4e | 2777 | output_asm_insn ("addib,>= -8,%2,.-12", operands); |
e4065f95 | 2778 | output_asm_insn ("{stws|stw},ma %6,4(%0)", operands); |
42819d4e | 2779 | |
2780 | /* Handle the residual. There could be up to 7 bytes of | |
2781 | residual to copy! */ | |
2782 | if (n_bytes % 8 != 0) | |
2783 | { | |
2784 | operands[4] = GEN_INT (n_bytes % 4); | |
2785 | if (n_bytes % 8 >= 4) | |
e4065f95 | 2786 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
42819d4e | 2787 | if (n_bytes % 4 != 0) |
34940871 | 2788 | output_asm_insn ("ldw 0(%1),%6", operands); |
42819d4e | 2789 | if (n_bytes % 8 >= 4) |
e4065f95 | 2790 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); |
42819d4e | 2791 | if (n_bytes % 4 != 0) |
e4065f95 | 2792 | output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands); |
42819d4e | 2793 | } |
2794 | return ""; | |
87ad11b0 | 2795 | |
42819d4e | 2796 | case 2: |
2797 | /* Pre-adjust the loop counter. */ | |
2798 | operands[4] = GEN_INT (n_bytes - 4); | |
2799 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2800 | |
42819d4e | 2801 | /* Copying loop. */ |
e4065f95 | 2802 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
2803 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands); | |
2804 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); | |
42819d4e | 2805 | output_asm_insn ("addib,>= -4,%2,.-12", operands); |
e4065f95 | 2806 | output_asm_insn ("{sths|sth},ma %6,2(%0)", operands); |
87ad11b0 | 2807 | |
42819d4e | 2808 | /* Handle the residual. */ |
2809 | if (n_bytes % 4 != 0) | |
2810 | { | |
2811 | if (n_bytes % 4 >= 2) | |
e4065f95 | 2812 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
42819d4e | 2813 | if (n_bytes % 2 != 0) |
34940871 | 2814 | output_asm_insn ("ldb 0(%1),%6", operands); |
42819d4e | 2815 | if (n_bytes % 4 >= 2) |
e4065f95 | 2816 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); |
42819d4e | 2817 | if (n_bytes % 2 != 0) |
34940871 | 2818 | output_asm_insn ("stb %6,0(%0)", operands); |
42819d4e | 2819 | } |
2820 | return ""; | |
87ad11b0 | 2821 | |
42819d4e | 2822 | case 1: |
2823 | /* Pre-adjust the loop counter. */ | |
2824 | operands[4] = GEN_INT (n_bytes - 2); | |
2825 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2826 | |
42819d4e | 2827 | /* Copying loop. */ |
e4065f95 | 2828 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands); |
2829 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands); | |
2830 | output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands); | |
42819d4e | 2831 | output_asm_insn ("addib,>= -2,%2,.-12", operands); |
e4065f95 | 2832 | output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands); |
87ad11b0 | 2833 | |
42819d4e | 2834 | /* Handle the residual. */ |
2835 | if (n_bytes % 2 != 0) | |
2836 | { | |
34940871 | 2837 | output_asm_insn ("ldb 0(%1),%3", operands); |
2838 | output_asm_insn ("stb %3,0(%0)", operands); | |
42819d4e | 2839 | } |
2840 | return ""; | |
87ad11b0 | 2841 | |
42819d4e | 2842 | default: |
ecf2283d | 2843 | gcc_unreachable (); |
87ad11b0 | 2844 | } |
87ad11b0 | 2845 | } |
58e17b0b | 2846 | |
2847 | /* Count the number of insns necessary to handle this block move. | |
2848 | ||
2849 | Basic structure is the same as emit_block_move, except that we | |
2850 | count insns rather than emit them. */ | |
2851 | ||
611a88e1 | 2852 | static int |
008c057d | 2853 | compute_movmem_length (rtx insn) |
58e17b0b | 2854 | { |
2855 | rtx pat = PATTERN (insn); | |
fc1fb057 | 2856 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0)); |
2857 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0)); | |
42819d4e | 2858 | unsigned int n_insns = 0; |
58e17b0b | 2859 | |
2860 | /* We can't move more than four bytes at a time because the PA | |
2861 | has no longer integer move insns. (Could use fp mem ops?) */ | |
a7e1bb24 | 2862 | if (align > (TARGET_64BIT ? 8 : 4)) |
2863 | align = (TARGET_64BIT ? 8 : 4); | |
58e17b0b | 2864 | |
79bfe6ae | 2865 | /* The basic copying loop. */ |
42819d4e | 2866 | n_insns = 6; |
58e17b0b | 2867 | |
42819d4e | 2868 | /* Residuals. */ |
2869 | if (n_bytes % (2 * align) != 0) | |
58e17b0b | 2870 | { |
79bfe6ae | 2871 | if ((n_bytes % (2 * align)) >= align) |
2872 | n_insns += 2; | |
2873 | ||
2874 | if ((n_bytes % align) != 0) | |
2875 | n_insns += 2; | |
58e17b0b | 2876 | } |
42819d4e | 2877 | |
2878 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2879 | return n_insns * 4; | |
58e17b0b | 2880 | } |
a7e1bb24 | 2881 | |
2882 | /* Emit code to perform a block clear. | |
2883 | ||
2884 | OPERANDS[0] is the destination pointer as a REG, clobbered. | |
2885 | OPERANDS[1] is a register for temporary storage. | |
2886 | OPERANDS[2] is the size as a CONST_INT | |
2887 | OPERANDS[3] is the alignment safe to use, as a CONST_INT. */ | |
2888 | ||
2889 | const char * | |
2890 | output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) | |
2891 | { | |
2892 | int align = INTVAL (operands[3]); | |
2893 | unsigned long n_bytes = INTVAL (operands[2]); | |
2894 | ||
2895 | /* We can't clear more than a word at a time because the PA | |
2896 | has no longer integer move insns. */ | |
2897 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2898 | align = (TARGET_64BIT ? 8 : 4); | |
2899 | ||
2900 | /* Note that we know each loop below will execute at least twice | |
2901 | (else we would have open-coded the copy). */ | |
2902 | switch (align) | |
2903 | { | |
2904 | case 8: | |
2905 | /* Pre-adjust the loop counter. */ | |
2906 | operands[2] = GEN_INT (n_bytes - 16); | |
2907 | output_asm_insn ("ldi %2,%1", operands); | |
2908 | ||
2909 | /* Loop. */ | |
2910 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2911 | output_asm_insn ("addib,>= -16,%1,.-4", operands); | |
2912 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2913 | ||
2914 | /* Handle the residual. There could be up to 7 bytes of | |
2915 | residual to copy! */ | |
2916 | if (n_bytes % 16 != 0) | |
2917 | { | |
2918 | operands[2] = GEN_INT (n_bytes % 8); | |
2919 | if (n_bytes % 16 >= 8) | |
2920 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2921 | if (n_bytes % 8 != 0) | |
2922 | output_asm_insn ("stdby,e %%r0,%2(%0)", operands); | |
2923 | } | |
2924 | return ""; | |
2925 | ||
2926 | case 4: | |
2927 | /* Pre-adjust the loop counter. */ | |
2928 | operands[2] = GEN_INT (n_bytes - 8); | |
2929 | output_asm_insn ("ldi %2,%1", operands); | |
2930 | ||
2931 | /* Loop. */ | |
2932 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2933 | output_asm_insn ("addib,>= -8,%1,.-4", operands); | |
2934 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2935 | ||
2936 | /* Handle the residual. There could be up to 7 bytes of | |
2937 | residual to copy! */ | |
2938 | if (n_bytes % 8 != 0) | |
2939 | { | |
2940 | operands[2] = GEN_INT (n_bytes % 4); | |
2941 | if (n_bytes % 8 >= 4) | |
2942 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2943 | if (n_bytes % 4 != 0) | |
2944 | output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands); | |
2945 | } | |
2946 | return ""; | |
2947 | ||
2948 | case 2: | |
2949 | /* Pre-adjust the loop counter. */ | |
2950 | operands[2] = GEN_INT (n_bytes - 4); | |
2951 | output_asm_insn ("ldi %2,%1", operands); | |
2952 | ||
2953 | /* Loop. */ | |
2954 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2955 | output_asm_insn ("addib,>= -4,%1,.-4", operands); | |
2956 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2957 | ||
2958 | /* Handle the residual. */ | |
2959 | if (n_bytes % 4 != 0) | |
2960 | { | |
2961 | if (n_bytes % 4 >= 2) | |
2962 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2963 | if (n_bytes % 2 != 0) | |
2964 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2965 | } | |
2966 | return ""; | |
2967 | ||
2968 | case 1: | |
2969 | /* Pre-adjust the loop counter. */ | |
2970 | operands[2] = GEN_INT (n_bytes - 2); | |
2971 | output_asm_insn ("ldi %2,%1", operands); | |
2972 | ||
2973 | /* Loop. */ | |
2974 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2975 | output_asm_insn ("addib,>= -2,%1,.-4", operands); | |
2976 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2977 | ||
2978 | /* Handle the residual. */ | |
2979 | if (n_bytes % 2 != 0) | |
2980 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2981 | ||
2982 | return ""; | |
2983 | ||
2984 | default: | |
ecf2283d | 2985 | gcc_unreachable (); |
a7e1bb24 | 2986 | } |
2987 | } | |
2988 | ||
2989 | /* Count the number of insns necessary to handle this block move. | |
2990 | ||
2991 | Basic structure is the same as emit_block_move, except that we | |
2992 | count insns rather than emit them. */ | |
2993 | ||
2994 | static int | |
008c057d | 2995 | compute_clrmem_length (rtx insn) |
a7e1bb24 | 2996 | { |
2997 | rtx pat = PATTERN (insn); | |
2998 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0)); | |
2999 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0)); | |
3000 | unsigned int n_insns = 0; | |
3001 | ||
3002 | /* We can't clear more than a word at a time because the PA | |
3003 | has no longer integer move insns. */ | |
3004 | if (align > (TARGET_64BIT ? 8 : 4)) | |
3005 | align = (TARGET_64BIT ? 8 : 4); | |
3006 | ||
3007 | /* The basic loop. */ | |
3008 | n_insns = 4; | |
3009 | ||
3010 | /* Residuals. */ | |
3011 | if (n_bytes % (2 * align) != 0) | |
3012 | { | |
3013 | if ((n_bytes % (2 * align)) >= align) | |
3014 | n_insns++; | |
3015 | ||
3016 | if ((n_bytes % align) != 0) | |
3017 | n_insns++; | |
3018 | } | |
3019 | ||
3020 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
3021 | return n_insns * 4; | |
3022 | } | |
87ad11b0 | 3023 | \f |
3024 | ||
611a88e1 | 3025 | const char * |
5c1d8983 | 3026 | output_and (rtx *operands) |
e057641f | 3027 | { |
d6f01525 | 3028 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) |
e057641f | 3029 | { |
3745c59b | 3030 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
e057641f | 3031 | int ls0, ls1, ms0, p, len; |
3032 | ||
3033 | for (ls0 = 0; ls0 < 32; ls0++) | |
3034 | if ((mask & (1 << ls0)) == 0) | |
3035 | break; | |
3036 | ||
3037 | for (ls1 = ls0; ls1 < 32; ls1++) | |
3038 | if ((mask & (1 << ls1)) != 0) | |
3039 | break; | |
3040 | ||
3041 | for (ms0 = ls1; ms0 < 32; ms0++) | |
3042 | if ((mask & (1 << ms0)) == 0) | |
3043 | break; | |
3044 | ||
ecf2283d | 3045 | gcc_assert (ms0 == 32); |
e057641f | 3046 | |
3047 | if (ls1 == 32) | |
3048 | { | |
3049 | len = ls0; | |
3050 | ||
ecf2283d | 3051 | gcc_assert (len); |
e057641f | 3052 | |
ef618fe4 | 3053 | operands[2] = GEN_INT (len); |
e4065f95 | 3054 | return "{extru|extrw,u} %1,31,%2,%0"; |
e057641f | 3055 | } |
3056 | else | |
3057 | { | |
3058 | /* We could use this `depi' for the case above as well, but `depi' | |
3059 | requires one more register file access than an `extru'. */ | |
3060 | ||
3061 | p = 31 - ls0; | |
3062 | len = ls1 - ls0; | |
3063 | ||
ef618fe4 | 3064 | operands[2] = GEN_INT (p); |
3065 | operands[3] = GEN_INT (len); | |
e4065f95 | 3066 | return "{depi|depwi} 0,%2,%3,%0"; |
e057641f | 3067 | } |
3068 | } | |
3069 | else | |
3070 | return "and %1,%2,%0"; | |
3071 | } | |
3072 | ||
5e3c5739 | 3073 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] |
3074 | storing the result in operands[0]. */ | |
9aadea62 | 3075 | const char * |
5c1d8983 | 3076 | output_64bit_and (rtx *operands) |
5e3c5739 | 3077 | { |
3078 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) | |
3079 | { | |
3080 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 3081 | int ls0, ls1, ms0, p, len; |
5e3c5739 | 3082 | |
3083 | for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++) | |
b7d86581 | 3084 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0) |
5e3c5739 | 3085 | break; |
3086 | ||
3087 | for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++) | |
b7d86581 | 3088 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0) |
5e3c5739 | 3089 | break; |
3090 | ||
3091 | for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++) | |
b7d86581 | 3092 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0) |
5e3c5739 | 3093 | break; |
3094 | ||
ecf2283d | 3095 | gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT); |
5e3c5739 | 3096 | |
3097 | if (ls1 == HOST_BITS_PER_WIDE_INT) | |
3098 | { | |
3099 | len = ls0; | |
3100 | ||
ecf2283d | 3101 | gcc_assert (len); |
5e3c5739 | 3102 | |
3103 | operands[2] = GEN_INT (len); | |
3104 | return "extrd,u %1,63,%2,%0"; | |
3105 | } | |
3106 | else | |
3107 | { | |
3108 | /* We could use this `depi' for the case above as well, but `depi' | |
3109 | requires one more register file access than an `extru'. */ | |
3110 | ||
3111 | p = 63 - ls0; | |
3112 | len = ls1 - ls0; | |
3113 | ||
3114 | operands[2] = GEN_INT (p); | |
3115 | operands[3] = GEN_INT (len); | |
3116 | return "depdi 0,%2,%3,%0"; | |
3117 | } | |
3118 | } | |
3119 | else | |
3120 | return "and %1,%2,%0"; | |
3121 | } | |
3122 | ||
611a88e1 | 3123 | const char * |
5c1d8983 | 3124 | output_ior (rtx *operands) |
e057641f | 3125 | { |
3745c59b | 3126 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
57ed30e5 | 3127 | int bs0, bs1, p, len; |
6d36483b | 3128 | |
c9da5f4d | 3129 | if (INTVAL (operands[2]) == 0) |
3130 | return "copy %1,%0"; | |
e057641f | 3131 | |
c9da5f4d | 3132 | for (bs0 = 0; bs0 < 32; bs0++) |
3133 | if ((mask & (1 << bs0)) != 0) | |
3134 | break; | |
e057641f | 3135 | |
c9da5f4d | 3136 | for (bs1 = bs0; bs1 < 32; bs1++) |
3137 | if ((mask & (1 << bs1)) == 0) | |
3138 | break; | |
e057641f | 3139 | |
ecf2283d | 3140 | gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); |
e057641f | 3141 | |
c9da5f4d | 3142 | p = 31 - bs0; |
3143 | len = bs1 - bs0; | |
e057641f | 3144 | |
ef618fe4 | 3145 | operands[2] = GEN_INT (p); |
3146 | operands[3] = GEN_INT (len); | |
e4065f95 | 3147 | return "{depi|depwi} -1,%2,%3,%0"; |
e057641f | 3148 | } |
5e3c5739 | 3149 | |
3150 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] | |
3151 | storing the result in operands[0]. */ | |
9aadea62 | 3152 | const char * |
5c1d8983 | 3153 | output_64bit_ior (rtx *operands) |
5e3c5739 | 3154 | { |
3155 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 3156 | int bs0, bs1, p, len; |
5e3c5739 | 3157 | |
3158 | if (INTVAL (operands[2]) == 0) | |
3159 | return "copy %1,%0"; | |
3160 | ||
3161 | for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++) | |
b7d86581 | 3162 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0) |
5e3c5739 | 3163 | break; |
3164 | ||
3165 | for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++) | |
b7d86581 | 3166 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0) |
5e3c5739 | 3167 | break; |
3168 | ||
ecf2283d | 3169 | gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT |
3170 | || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); | |
5e3c5739 | 3171 | |
3172 | p = 63 - bs0; | |
3173 | len = bs1 - bs0; | |
3174 | ||
3175 | operands[2] = GEN_INT (p); | |
3176 | operands[3] = GEN_INT (len); | |
3177 | return "depdi -1,%2,%3,%0"; | |
3178 | } | |
e057641f | 3179 | \f |
58356836 | 3180 | /* Target hook for assembling integer objects. This code handles |
e678758c | 3181 | aligned SI and DI integers specially since function references |
3182 | must be preceded by P%. */ | |
58356836 | 3183 | |
3184 | static bool | |
5c1d8983 | 3185 | pa_assemble_integer (rtx x, unsigned int size, int aligned_p) |
58356836 | 3186 | { |
e678758c | 3187 | if (size == UNITS_PER_WORD |
3188 | && aligned_p | |
58356836 | 3189 | && function_label_operand (x, VOIDmode)) |
3190 | { | |
3191 | fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file); | |
3192 | output_addr_const (asm_out_file, x); | |
3193 | fputc ('\n', asm_out_file); | |
3194 | return true; | |
3195 | } | |
3196 | return default_assemble_integer (x, size, aligned_p); | |
3197 | } | |
3198 | \f | |
87ad11b0 | 3199 | /* Output an ascii string. */ |
57ed30e5 | 3200 | void |
5c1d8983 | 3201 | output_ascii (FILE *file, const char *p, int size) |
87ad11b0 | 3202 | { |
3203 | int i; | |
3204 | int chars_output; | |
5aedf60c | 3205 | unsigned char partial_output[16]; /* Max space 4 chars can occupy. */ |
87ad11b0 | 3206 | |
3207 | /* The HP assembler can only take strings of 256 characters at one | |
3208 | time. This is a limitation on input line length, *not* the | |
3209 | length of the string. Sigh. Even worse, it seems that the | |
3210 | restriction is in number of input characters (see \xnn & | |
3211 | \whatever). So we have to do this very carefully. */ | |
3212 | ||
9c0ac0fd | 3213 | fputs ("\t.STRING \"", file); |
87ad11b0 | 3214 | |
3215 | chars_output = 0; | |
3216 | for (i = 0; i < size; i += 4) | |
3217 | { | |
3218 | int co = 0; | |
3219 | int io = 0; | |
3220 | for (io = 0, co = 0; io < MIN (4, size - i); io++) | |
3221 | { | |
bf8aac3e | 3222 | register unsigned int c = (unsigned char) p[i + io]; |
87ad11b0 | 3223 | |
3224 | if (c == '\"' || c == '\\') | |
3225 | partial_output[co++] = '\\'; | |
3226 | if (c >= ' ' && c < 0177) | |
3227 | partial_output[co++] = c; | |
3228 | else | |
3229 | { | |
3230 | unsigned int hexd; | |
3231 | partial_output[co++] = '\\'; | |
3232 | partial_output[co++] = 'x'; | |
3233 | hexd = c / 16 - 0 + '0'; | |
3234 | if (hexd > '9') | |
3235 | hexd -= '9' - 'a' + 1; | |
3236 | partial_output[co++] = hexd; | |
3237 | hexd = c % 16 - 0 + '0'; | |
3238 | if (hexd > '9') | |
3239 | hexd -= '9' - 'a' + 1; | |
3240 | partial_output[co++] = hexd; | |
3241 | } | |
3242 | } | |
3243 | if (chars_output + co > 243) | |
3244 | { | |
9c0ac0fd | 3245 | fputs ("\"\n\t.STRING \"", file); |
87ad11b0 | 3246 | chars_output = 0; |
3247 | } | |
a584fe8a | 3248 | fwrite (partial_output, 1, (size_t) co, file); |
87ad11b0 | 3249 | chars_output += co; |
3250 | co = 0; | |
3251 | } | |
9c0ac0fd | 3252 | fputs ("\"\n", file); |
87ad11b0 | 3253 | } |
c533da59 | 3254 | |
3255 | /* Try to rewrite floating point comparisons & branches to avoid | |
3256 | useless add,tr insns. | |
3257 | ||
3258 | CHECK_NOTES is nonzero if we should examine REG_DEAD notes | |
3259 | to see if FPCC is dead. CHECK_NOTES is nonzero for the | |
3260 | first attempt to remove useless add,tr insns. It is zero | |
3261 | for the second pass as reorg sometimes leaves bogus REG_DEAD | |
3262 | notes lying around. | |
3263 | ||
3264 | When CHECK_NOTES is zero we can only eliminate add,tr insns | |
3265 | when there's a 1:1 correspondence between fcmp and ftest/fbranch | |
3266 | instructions. */ | |
611a88e1 | 3267 | static void |
5c1d8983 | 3268 | remove_useless_addtr_insns (int check_notes) |
c533da59 | 3269 | { |
3270 | rtx insn; | |
c533da59 | 3271 | static int pass = 0; |
3272 | ||
3273 | /* This is fairly cheap, so always run it when optimizing. */ | |
3274 | if (optimize > 0) | |
3275 | { | |
3276 | int fcmp_count = 0; | |
3277 | int fbranch_count = 0; | |
3278 | ||
3279 | /* Walk all the insns in this function looking for fcmp & fbranch | |
3280 | instructions. Keep track of how many of each we find. */ | |
2efea8c0 | 3281 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3282 | { |
3283 | rtx tmp; | |
3284 | ||
3285 | /* Ignore anything that isn't an INSN or a JUMP_INSN. */ | |
3286 | if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
3287 | continue; | |
3288 | ||
3289 | tmp = PATTERN (insn); | |
3290 | ||
3291 | /* It must be a set. */ | |
3292 | if (GET_CODE (tmp) != SET) | |
3293 | continue; | |
3294 | ||
3295 | /* If the destination is CCFP, then we've found an fcmp insn. */ | |
3296 | tmp = SET_DEST (tmp); | |
3297 | if (GET_CODE (tmp) == REG && REGNO (tmp) == 0) | |
3298 | { | |
3299 | fcmp_count++; | |
3300 | continue; | |
3301 | } | |
9840d99d | 3302 | |
c533da59 | 3303 | tmp = PATTERN (insn); |
3304 | /* If this is an fbranch instruction, bump the fbranch counter. */ | |
3305 | if (GET_CODE (tmp) == SET | |
3306 | && SET_DEST (tmp) == pc_rtx | |
3307 | && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE | |
3308 | && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE | |
3309 | && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG | |
3310 | && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0) | |
3311 | { | |
3312 | fbranch_count++; | |
3313 | continue; | |
3314 | } | |
3315 | } | |
3316 | ||
3317 | ||
3318 | /* Find all floating point compare + branch insns. If possible, | |
3319 | reverse the comparison & the branch to avoid add,tr insns. */ | |
2efea8c0 | 3320 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 3321 | { |
3322 | rtx tmp, next; | |
3323 | ||
3324 | /* Ignore anything that isn't an INSN. */ | |
3325 | if (GET_CODE (insn) != INSN) | |
3326 | continue; | |
3327 | ||
3328 | tmp = PATTERN (insn); | |
3329 | ||
3330 | /* It must be a set. */ | |
3331 | if (GET_CODE (tmp) != SET) | |
3332 | continue; | |
3333 | ||
3334 | /* The destination must be CCFP, which is register zero. */ | |
3335 | tmp = SET_DEST (tmp); | |
3336 | if (GET_CODE (tmp) != REG || REGNO (tmp) != 0) | |
3337 | continue; | |
3338 | ||
3339 | /* INSN should be a set of CCFP. | |
3340 | ||
3341 | See if the result of this insn is used in a reversed FP | |
3342 | conditional branch. If so, reverse our condition and | |
3343 | the branch. Doing so avoids useless add,tr insns. */ | |
3344 | next = next_insn (insn); | |
3345 | while (next) | |
3346 | { | |
3347 | /* Jumps, calls and labels stop our search. */ | |
3348 | if (GET_CODE (next) == JUMP_INSN | |
3349 | || GET_CODE (next) == CALL_INSN | |
3350 | || GET_CODE (next) == CODE_LABEL) | |
3351 | break; | |
3352 | ||
3353 | /* As does another fcmp insn. */ | |
3354 | if (GET_CODE (next) == INSN | |
3355 | && GET_CODE (PATTERN (next)) == SET | |
3356 | && GET_CODE (SET_DEST (PATTERN (next))) == REG | |
3357 | && REGNO (SET_DEST (PATTERN (next))) == 0) | |
3358 | break; | |
3359 | ||
3360 | next = next_insn (next); | |
3361 | } | |
3362 | ||
3363 | /* Is NEXT_INSN a branch? */ | |
3364 | if (next | |
3365 | && GET_CODE (next) == JUMP_INSN) | |
3366 | { | |
3367 | rtx pattern = PATTERN (next); | |
3368 | ||
a361b456 | 3369 | /* If it a reversed fp conditional branch (e.g. uses add,tr) |
c533da59 | 3370 | and CCFP dies, then reverse our conditional and the branch |
3371 | to avoid the add,tr. */ | |
3372 | if (GET_CODE (pattern) == SET | |
3373 | && SET_DEST (pattern) == pc_rtx | |
3374 | && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE | |
3375 | && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE | |
3376 | && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG | |
3377 | && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0 | |
3378 | && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC | |
3379 | && (fcmp_count == fbranch_count | |
3380 | || (check_notes | |
3381 | && find_regno_note (next, REG_DEAD, 0)))) | |
3382 | { | |
3383 | /* Reverse the branch. */ | |
3384 | tmp = XEXP (SET_SRC (pattern), 1); | |
3385 | XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2); | |
3386 | XEXP (SET_SRC (pattern), 2) = tmp; | |
3387 | INSN_CODE (next) = -1; | |
3388 | ||
3389 | /* Reverse our condition. */ | |
3390 | tmp = PATTERN (insn); | |
3391 | PUT_CODE (XEXP (tmp, 1), | |
ea52c577 | 3392 | (reverse_condition_maybe_unordered |
3393 | (GET_CODE (XEXP (tmp, 1))))); | |
c533da59 | 3394 | } |
3395 | } | |
3396 | } | |
3397 | } | |
3398 | ||
3399 | pass = !pass; | |
3400 | ||
3401 | } | |
87ad11b0 | 3402 | \f |
ea52c577 | 3403 | /* You may have trouble believing this, but this is the 32 bit HP-PA |
3404 | stack layout. Wow. | |
87ad11b0 | 3405 | |
3406 | Offset Contents | |
3407 | ||
3408 | Variable arguments (optional; any number may be allocated) | |
3409 | ||
3410 | SP-(4*(N+9)) arg word N | |
3411 | : : | |
3412 | SP-56 arg word 5 | |
3413 | SP-52 arg word 4 | |
3414 | ||
3415 | Fixed arguments (must be allocated; may remain unused) | |
3416 | ||
3417 | SP-48 arg word 3 | |
3418 | SP-44 arg word 2 | |
3419 | SP-40 arg word 1 | |
3420 | SP-36 arg word 0 | |
3421 | ||
3422 | Frame Marker | |
3423 | ||
3424 | SP-32 External Data Pointer (DP) | |
3425 | SP-28 External sr4 | |
3426 | SP-24 External/stub RP (RP') | |
3427 | SP-20 Current RP | |
3428 | SP-16 Static Link | |
3429 | SP-12 Clean up | |
3430 | SP-8 Calling Stub RP (RP'') | |
3431 | SP-4 Previous SP | |
3432 | ||
3433 | Top of Frame | |
3434 | ||
3435 | SP-0 Stack Pointer (points to next available address) | |
3436 | ||
3437 | */ | |
3438 | ||
3439 | /* This function saves registers as follows. Registers marked with ' are | |
3440 | this function's registers (as opposed to the previous function's). | |
3441 | If a frame_pointer isn't needed, r4 is saved as a general register; | |
3442 | the space for the frame pointer is still allocated, though, to keep | |
3443 | things simple. | |
3444 | ||
3445 | ||
3446 | Top of Frame | |
3447 | ||
3448 | SP (FP') Previous FP | |
3449 | SP + 4 Alignment filler (sigh) | |
3450 | SP + 8 Space for locals reserved here. | |
3451 | . | |
3452 | . | |
3453 | . | |
3454 | SP + n All call saved register used. | |
3455 | . | |
3456 | . | |
3457 | . | |
3458 | SP + o All call saved fp registers used. | |
3459 | . | |
3460 | . | |
3461 | . | |
3462 | SP + p (SP') points to next available address. | |
6d36483b | 3463 | |
87ad11b0 | 3464 | */ |
3465 | ||
17d9b0c3 | 3466 | /* Global variables set by output_function_prologue(). */ |
cc858176 | 3467 | /* Size of frame. Need to know this to emit return insns from |
3468 | leaf procedures. */ | |
6bcdc1fb | 3469 | static HOST_WIDE_INT actual_fsize, local_fsize; |
3470 | static int save_fregs; | |
cc858176 | 3471 | |
daee63dd | 3472 | /* Emit RTL to store REG at the memory location specified by BASE+DISP. |
359a0be8 | 3473 | Handle case where DISP > 8k by using the add_high_const patterns. |
daee63dd | 3474 | |
3475 | Note in DISP > 8k case, we will leave the high part of the address | |
3476 | in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/ | |
7014838c | 3477 | |
6a2c16d6 | 3478 | static void |
6bcdc1fb | 3479 | store_reg (int reg, HOST_WIDE_INT disp, int base) |
87ad11b0 | 3480 | { |
6a2c16d6 | 3481 | rtx insn, dest, src, basereg; |
cc858176 | 3482 | |
3483 | src = gen_rtx_REG (word_mode, reg); | |
3484 | basereg = gen_rtx_REG (Pmode, base); | |
87ad11b0 | 3485 | if (VAL_14_BITS_P (disp)) |
daee63dd | 3486 | { |
cc858176 | 3487 | dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
6a2c16d6 | 3488 | insn = emit_move_insn (dest, src); |
daee63dd | 3489 | } |
6bcdc1fb | 3490 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3491 | { | |
3492 | rtx delta = GEN_INT (disp); | |
3493 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3494 | ||
3495 | emit_move_insn (tmpreg, delta); | |
5ecfd087 | 3496 | insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); |
6bcdc1fb | 3497 | if (DO_FRAME_NOTES) |
3498 | { | |
b9c74b4d | 3499 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3500 | gen_rtx_SET (VOIDmode, tmpreg, | |
3501 | gen_rtx_PLUS (Pmode, basereg, delta))); | |
5ecfd087 | 3502 | RTX_FRAME_RELATED_P (insn) = 1; |
6bcdc1fb | 3503 | } |
5ecfd087 | 3504 | dest = gen_rtx_MEM (word_mode, tmpreg); |
3505 | insn = emit_move_insn (dest, src); | |
6bcdc1fb | 3506 | } |
daee63dd | 3507 | else |
3508 | { | |
cc858176 | 3509 | rtx delta = GEN_INT (disp); |
3510 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3511 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 3512 | |
cc858176 | 3513 | emit_move_insn (tmpreg, high); |
3514 | dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
6a2c16d6 | 3515 | insn = emit_move_insn (dest, src); |
3516 | if (DO_FRAME_NOTES) | |
b9c74b4d | 3517 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3518 | gen_rtx_SET (VOIDmode, | |
3519 | gen_rtx_MEM (word_mode, | |
3520 | gen_rtx_PLUS (word_mode, | |
3521 | basereg, | |
3522 | delta)), | |
3523 | src)); | |
daee63dd | 3524 | } |
6a2c16d6 | 3525 | |
3526 | if (DO_FRAME_NOTES) | |
3527 | RTX_FRAME_RELATED_P (insn) = 1; | |
daee63dd | 3528 | } |
3529 | ||
a584fe8a | 3530 | /* Emit RTL to store REG at the memory location specified by BASE and then |
3531 | add MOD to BASE. MOD must be <= 8k. */ | |
daee63dd | 3532 | |
a584fe8a | 3533 | static void |
6bcdc1fb | 3534 | store_reg_modify (int base, int reg, HOST_WIDE_INT mod) |
a584fe8a | 3535 | { |
3536 | rtx insn, basereg, srcreg, delta; | |
3537 | ||
ecf2283d | 3538 | gcc_assert (VAL_14_BITS_P (mod)); |
a584fe8a | 3539 | |
3540 | basereg = gen_rtx_REG (Pmode, base); | |
3541 | srcreg = gen_rtx_REG (word_mode, reg); | |
3542 | delta = GEN_INT (mod); | |
3543 | ||
3544 | insn = emit_insn (gen_post_store (basereg, srcreg, delta)); | |
3545 | if (DO_FRAME_NOTES) | |
3546 | { | |
3547 | RTX_FRAME_RELATED_P (insn) = 1; | |
3548 | ||
3549 | /* RTX_FRAME_RELATED_P must be set on each frame related set | |
dc873350 | 3550 | in a parallel with more than one element. */ |
3551 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1; | |
3552 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; | |
a584fe8a | 3553 | } |
3554 | } | |
3555 | ||
3556 | /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case | |
3557 | where DISP > 8k by using the add_high_const patterns. NOTE indicates | |
3558 | whether to add a frame note or not. | |
3559 | ||
3560 | In the DISP > 8k case, we leave the high part of the address in %r1. | |
3561 | There is code in expand_hppa_{prologue,epilogue} that knows about this. */ | |
7014838c | 3562 | |
6a2c16d6 | 3563 | static void |
6bcdc1fb | 3564 | set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note) |
87ad11b0 | 3565 | { |
6a2c16d6 | 3566 | rtx insn; |
cc858176 | 3567 | |
87ad11b0 | 3568 | if (VAL_14_BITS_P (disp)) |
cc858176 | 3569 | { |
6a2c16d6 | 3570 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
3571 | plus_constant (gen_rtx_REG (Pmode, base), disp)); | |
cc858176 | 3572 | } |
6bcdc1fb | 3573 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3574 | { | |
3575 | rtx basereg = gen_rtx_REG (Pmode, base); | |
3576 | rtx delta = GEN_INT (disp); | |
3577 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3578 | ||
3579 | emit_move_insn (tmpreg, delta); | |
3580 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), | |
3581 | gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
5ecfd087 | 3582 | if (DO_FRAME_NOTES) |
b9c74b4d | 3583 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
3584 | gen_rtx_SET (VOIDmode, tmpreg, | |
3585 | gen_rtx_PLUS (Pmode, basereg, delta))); | |
6bcdc1fb | 3586 | } |
87ad11b0 | 3587 | else |
daee63dd | 3588 | { |
6a2c16d6 | 3589 | rtx basereg = gen_rtx_REG (Pmode, base); |
cc858176 | 3590 | rtx delta = GEN_INT (disp); |
6bcdc1fb | 3591 | rtx tmpreg = gen_rtx_REG (Pmode, 1); |
6a2c16d6 | 3592 | |
6bcdc1fb | 3593 | emit_move_insn (tmpreg, |
6a2c16d6 | 3594 | gen_rtx_PLUS (Pmode, basereg, |
cc858176 | 3595 | gen_rtx_HIGH (Pmode, delta))); |
6a2c16d6 | 3596 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
6bcdc1fb | 3597 | gen_rtx_LO_SUM (Pmode, tmpreg, delta)); |
daee63dd | 3598 | } |
6a2c16d6 | 3599 | |
a584fe8a | 3600 | if (DO_FRAME_NOTES && note) |
6a2c16d6 | 3601 | RTX_FRAME_RELATED_P (insn) = 1; |
87ad11b0 | 3602 | } |
3603 | ||
6bcdc1fb | 3604 | HOST_WIDE_INT |
3605 | compute_frame_size (HOST_WIDE_INT size, int *fregs_live) | |
87ad11b0 | 3606 | { |
256f9b65 | 3607 | int freg_saved = 0; |
3608 | int i, j; | |
3609 | ||
3610 | /* The code in hppa_expand_prologue and hppa_expand_epilogue must | |
3611 | be consistent with the rounding and size calculation done here. | |
3612 | Change them at the same time. */ | |
3613 | ||
3614 | /* We do our own stack alignment. First, round the size of the | |
3615 | stack locals up to a word boundary. */ | |
3616 | size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3617 | ||
3618 | /* Space for previous frame pointer + filler. If any frame is | |
3619 | allocated, we need to add in the STARTING_FRAME_OFFSET. We | |
3620 | waste some space here for the sake of HP compatibility. The | |
3621 | first slot is only used when the frame pointer is needed. */ | |
3622 | if (size || frame_pointer_needed) | |
3623 | size += STARTING_FRAME_OFFSET; | |
3624 | ||
a584fe8a | 3625 | /* If the current function calls __builtin_eh_return, then we need |
3626 | to allocate stack space for registers that will hold data for | |
3627 | the exception handler. */ | |
18d50ae6 | 3628 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 3629 | { |
3630 | unsigned int i; | |
3631 | ||
3632 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
3633 | continue; | |
256f9b65 | 3634 | size += i * UNITS_PER_WORD; |
a584fe8a | 3635 | } |
3636 | ||
3a51bad9 | 3637 | /* Account for space used by the callee general register saves. */ |
256f9b65 | 3638 | for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--) |
3072d30e | 3639 | if (df_regs_ever_live_p (i)) |
256f9b65 | 3640 | size += UNITS_PER_WORD; |
df0651dc | 3641 | |
3a51bad9 | 3642 | /* Account for space used by the callee floating point register saves. */ |
bac38c40 | 3643 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
3072d30e | 3644 | if (df_regs_ever_live_p (i) |
3645 | || (!TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
df0651dc | 3646 | { |
256f9b65 | 3647 | freg_saved = 1; |
002fc5f7 | 3648 | |
3a51bad9 | 3649 | /* We always save both halves of the FP register, so always |
3650 | increment the frame size by 8 bytes. */ | |
256f9b65 | 3651 | size += 8; |
df0651dc | 3652 | } |
3653 | ||
256f9b65 | 3654 | /* If any of the floating registers are saved, account for the |
3655 | alignment needed for the floating point register save block. */ | |
3656 | if (freg_saved) | |
3657 | { | |
3658 | size = (size + 7) & ~7; | |
3659 | if (fregs_live) | |
3660 | *fregs_live = 1; | |
3661 | } | |
3662 | ||
3a51bad9 | 3663 | /* The various ABIs include space for the outgoing parameters in the |
256f9b65 | 3664 | size of the current function's stack frame. We don't need to align |
3665 | for the outgoing arguments as their alignment is set by the final | |
3666 | rounding for the frame as a whole. */ | |
abe32cce | 3667 | size += crtl->outgoing_args_size; |
3a51bad9 | 3668 | |
3669 | /* Allocate space for the fixed frame marker. This space must be | |
e9ec370e | 3670 | allocated for any function that makes calls or allocates |
3a51bad9 | 3671 | stack space. */ |
256f9b65 | 3672 | if (!current_function_is_leaf || size) |
e9ec370e | 3673 | size += TARGET_64BIT ? 48 : 32; |
5e3c5739 | 3674 | |
256f9b65 | 3675 | /* Finally, round to the preferred stack boundary. */ |
2247cc5f | 3676 | return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1) |
3677 | & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
87ad11b0 | 3678 | } |
6d36483b | 3679 | |
17d9b0c3 | 3680 | /* Generate the assembly code for function entry. FILE is a stdio |
3681 | stream to output the code to. SIZE is an int: how many units of | |
3682 | temporary storage to allocate. | |
3683 | ||
3684 | Refer to the array `regs_ever_live' to determine which registers to | |
3685 | save; `regs_ever_live[I]' is nonzero if register number I is ever | |
3686 | used in the function. This function is responsible for knowing | |
3687 | which registers should not be saved even if used. */ | |
3688 | ||
3689 | /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block | |
3690 | of memory. If any fpu reg is used in the function, we allocate | |
3691 | such a block here, at the bottom of the frame, just in case it's needed. | |
3692 | ||
3693 | If this function is a leaf procedure, then we may choose not | |
3694 | to do a "save" insn. The decision about whether or not | |
3695 | to do this is made in regclass.c. */ | |
3696 | ||
6988553d | 3697 | static void |
5c1d8983 | 3698 | pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 3699 | { |
d151162a | 3700 | /* The function's label and associated .PROC must never be |
3701 | separated and must be output *after* any profiling declarations | |
3702 | to avoid changing spaces/subspaces within a procedure. */ | |
3703 | ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3704 | fputs ("\t.PROC\n", file); | |
3705 | ||
daee63dd | 3706 | /* hppa_expand_prologue does the dirty work now. We just need |
3707 | to output the assembler directives which denote the start | |
3708 | of a function. */ | |
6bcdc1fb | 3709 | fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize); |
df6b92e4 | 3710 | if (current_function_is_leaf) |
9c0ac0fd | 3711 | fputs (",NO_CALLS", file); |
df6b92e4 | 3712 | else |
3713 | fputs (",CALLS", file); | |
3714 | if (rp_saved) | |
3715 | fputs (",SAVE_RP", file); | |
f3ba7709 | 3716 | |
e9ec370e | 3717 | /* The SAVE_SP flag is used to indicate that register %r3 is stored |
3718 | at the beginning of the frame and that it is used as the frame | |
3719 | pointer for the frame. We do this because our current frame | |
3ce7ff97 | 3720 | layout doesn't conform to that specified in the HP runtime |
e9ec370e | 3721 | documentation and we need a way to indicate to programs such as |
3722 | GDB where %r3 is saved. The SAVE_SP flag was chosen because it | |
3723 | isn't used by HP compilers but is supported by the assembler. | |
3724 | However, SAVE_SP is supposed to indicate that the previous stack | |
3725 | pointer has been saved in the frame marker. */ | |
f3ba7709 | 3726 | if (frame_pointer_needed) |
9c0ac0fd | 3727 | fputs (",SAVE_SP", file); |
f3ba7709 | 3728 | |
a9960cdc | 3729 | /* Pass on information about the number of callee register saves |
9b0c95be | 3730 | performed in the prologue. |
3731 | ||
3732 | The compiler is supposed to pass the highest register number | |
6d36483b | 3733 | saved, the assembler then has to adjust that number before |
9b0c95be | 3734 | entering it into the unwind descriptor (to account for any |
6d36483b | 3735 | caller saved registers with lower register numbers than the |
9b0c95be | 3736 | first callee saved register). */ |
3737 | if (gr_saved) | |
3738 | fprintf (file, ",ENTRY_GR=%d", gr_saved + 2); | |
3739 | ||
3740 | if (fr_saved) | |
3741 | fprintf (file, ",ENTRY_FR=%d", fr_saved + 11); | |
a9960cdc | 3742 | |
9c0ac0fd | 3743 | fputs ("\n\t.ENTRY\n", file); |
daee63dd | 3744 | |
2efea8c0 | 3745 | remove_useless_addtr_insns (0); |
daee63dd | 3746 | } |
3747 | ||
57ed30e5 | 3748 | void |
5c1d8983 | 3749 | hppa_expand_prologue (void) |
daee63dd | 3750 | { |
afd7b680 | 3751 | int merge_sp_adjust_with_store = 0; |
6bcdc1fb | 3752 | HOST_WIDE_INT size = get_frame_size (); |
3753 | HOST_WIDE_INT offset; | |
3754 | int i; | |
a584fe8a | 3755 | rtx insn, tmpreg; |
daee63dd | 3756 | |
a9960cdc | 3757 | gr_saved = 0; |
3758 | fr_saved = 0; | |
3ddcbb9d | 3759 | save_fregs = 0; |
3a51bad9 | 3760 | |
256f9b65 | 3761 | /* Compute total size for frame pointer, filler, locals and rounding to |
3762 | the next word boundary. Similar code appears in compute_frame_size | |
3763 | and must be changed in tandem with this code. */ | |
3764 | local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3765 | if (local_fsize || frame_pointer_needed) | |
3766 | local_fsize += STARTING_FRAME_OFFSET; | |
3a51bad9 | 3767 | |
a1ab4fa3 | 3768 | actual_fsize = compute_frame_size (size, &save_fregs); |
8c0dd614 | 3769 | if (flag_stack_usage_info) |
990495a7 | 3770 | current_function_static_stack_size = actual_fsize; |
87ad11b0 | 3771 | |
daee63dd | 3772 | /* Compute a few things we will use often. */ |
440c23df | 3773 | tmpreg = gen_rtx_REG (word_mode, 1); |
87ad11b0 | 3774 | |
6d36483b | 3775 | /* Save RP first. The calling conventions manual states RP will |
cc858176 | 3776 | always be stored into the caller's frame at sp - 20 or sp - 16 |
5e3c5739 | 3777 | depending on which ABI is in use. */ |
18d50ae6 | 3778 | if (df_regs_ever_live_p (2) || crtl->calls_eh_return) |
df6b92e4 | 3779 | { |
3780 | store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM); | |
3781 | rp_saved = true; | |
3782 | } | |
3783 | else | |
3784 | rp_saved = false; | |
6d36483b | 3785 | |
daee63dd | 3786 | /* Allocate the local frame and set up the frame pointer if needed. */ |
58361f39 | 3787 | if (actual_fsize != 0) |
3788 | { | |
3789 | if (frame_pointer_needed) | |
3790 | { | |
3791 | /* Copy the old frame pointer temporarily into %r1. Set up the | |
3792 | new stack pointer, then store away the saved old frame pointer | |
a584fe8a | 3793 | into the stack at sp and at the same time update the stack |
3794 | pointer by actual_fsize bytes. Two versions, first | |
58361f39 | 3795 | handles small (<8k) frames. The second handles large (>=8k) |
3796 | frames. */ | |
68bc9ae6 | 3797 | insn = emit_move_insn (tmpreg, hard_frame_pointer_rtx); |
a584fe8a | 3798 | if (DO_FRAME_NOTES) |
dc873350 | 3799 | RTX_FRAME_RELATED_P (insn) = 1; |
a584fe8a | 3800 | |
68bc9ae6 | 3801 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); |
a584fe8a | 3802 | if (DO_FRAME_NOTES) |
3803 | RTX_FRAME_RELATED_P (insn) = 1; | |
3804 | ||
3805 | if (VAL_14_BITS_P (actual_fsize)) | |
3806 | store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize); | |
58361f39 | 3807 | else |
3808 | { | |
3809 | /* It is incorrect to store the saved frame pointer at *sp, | |
3810 | then increment sp (writes beyond the current stack boundary). | |
3811 | ||
3812 | So instead use stwm to store at *sp and post-increment the | |
3813 | stack pointer as an atomic operation. Then increment sp to | |
3814 | finish allocating the new frame. */ | |
6bcdc1fb | 3815 | HOST_WIDE_INT adjust1 = 8192 - 64; |
3816 | HOST_WIDE_INT adjust2 = actual_fsize - adjust1; | |
cc858176 | 3817 | |
a584fe8a | 3818 | store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1); |
6a2c16d6 | 3819 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3820 | adjust2, 1); |
58361f39 | 3821 | } |
a584fe8a | 3822 | |
e9ec370e | 3823 | /* We set SAVE_SP in frames that need a frame pointer. Thus, |
3824 | we need to store the previous stack pointer (frame pointer) | |
3825 | into the frame marker on targets that use the HP unwind | |
3826 | library. This allows the HP unwind library to be used to | |
3827 | unwind GCC frames. However, we are not fully compatible | |
3828 | with the HP library because our frame layout differs from | |
3829 | that specified in the HP runtime specification. | |
3830 | ||
3831 | We don't want a frame note on this instruction as the frame | |
3832 | marker moves during dynamic stack allocation. | |
3833 | ||
3834 | This instruction also serves as a blockage to prevent | |
3835 | register spills from being scheduled before the stack | |
3836 | pointer is raised. This is necessary as we store | |
3837 | registers using the frame pointer as a base register, | |
3838 | and the frame pointer is set before sp is raised. */ | |
3839 | if (TARGET_HPUX_UNWIND_LIBRARY) | |
3840 | { | |
3841 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, | |
3842 | GEN_INT (TARGET_64BIT ? -8 : -4)); | |
3843 | ||
3844 | emit_move_insn (gen_rtx_MEM (word_mode, addr), | |
68bc9ae6 | 3845 | hard_frame_pointer_rtx); |
e9ec370e | 3846 | } |
3847 | else | |
3848 | emit_insn (gen_blockage ()); | |
58361f39 | 3849 | } |
3850 | /* no frame pointer needed. */ | |
3851 | else | |
3852 | { | |
3853 | /* In some cases we can perform the first callee register save | |
3854 | and allocating the stack frame at the same time. If so, just | |
3855 | make a note of it and defer allocating the frame until saving | |
3856 | the callee registers. */ | |
df6edefa | 3857 | if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0) |
58361f39 | 3858 | merge_sp_adjust_with_store = 1; |
3859 | /* Can not optimize. Adjust the stack frame by actual_fsize | |
3860 | bytes. */ | |
3861 | else | |
6a2c16d6 | 3862 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3863 | actual_fsize, 1); |
58361f39 | 3864 | } |
372ef038 | 3865 | } |
3866 | ||
6d36483b | 3867 | /* Normal register save. |
daee63dd | 3868 | |
3869 | Do not save the frame pointer in the frame_pointer_needed case. It | |
3870 | was done earlier. */ | |
87ad11b0 | 3871 | if (frame_pointer_needed) |
3872 | { | |
a584fe8a | 3873 | offset = local_fsize; |
3874 | ||
3875 | /* Saving the EH return data registers in the frame is the simplest | |
3876 | way to get the frame unwind information emitted. We put them | |
3877 | just before the general registers. */ | |
18d50ae6 | 3878 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 3879 | { |
3880 | unsigned int i, regno; | |
3881 | ||
3882 | for (i = 0; ; ++i) | |
3883 | { | |
3884 | regno = EH_RETURN_DATA_REGNO (i); | |
3885 | if (regno == INVALID_REGNUM) | |
3886 | break; | |
3887 | ||
68bc9ae6 | 3888 | store_reg (regno, offset, HARD_FRAME_POINTER_REGNUM); |
a584fe8a | 3889 | offset += UNITS_PER_WORD; |
3890 | } | |
3891 | } | |
3892 | ||
3893 | for (i = 18; i >= 4; i--) | |
3072d30e | 3894 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
87ad11b0 | 3895 | { |
68bc9ae6 | 3896 | store_reg (i, offset, HARD_FRAME_POINTER_REGNUM); |
6ec4380b | 3897 | offset += UNITS_PER_WORD; |
a9960cdc | 3898 | gr_saved++; |
87ad11b0 | 3899 | } |
7f7c4869 | 3900 | /* Account for %r3 which is saved in a special place. */ |
9b0c95be | 3901 | gr_saved++; |
87ad11b0 | 3902 | } |
daee63dd | 3903 | /* No frame pointer needed. */ |
87ad11b0 | 3904 | else |
3905 | { | |
a584fe8a | 3906 | offset = local_fsize - actual_fsize; |
3907 | ||
3908 | /* Saving the EH return data registers in the frame is the simplest | |
3909 | way to get the frame unwind information emitted. */ | |
18d50ae6 | 3910 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 3911 | { |
3912 | unsigned int i, regno; | |
3913 | ||
3914 | for (i = 0; ; ++i) | |
3915 | { | |
3916 | regno = EH_RETURN_DATA_REGNO (i); | |
3917 | if (regno == INVALID_REGNUM) | |
3918 | break; | |
3919 | ||
3920 | /* If merge_sp_adjust_with_store is nonzero, then we can | |
3921 | optimize the first save. */ | |
3922 | if (merge_sp_adjust_with_store) | |
3923 | { | |
3924 | store_reg_modify (STACK_POINTER_REGNUM, regno, -offset); | |
3925 | merge_sp_adjust_with_store = 0; | |
3926 | } | |
3927 | else | |
3928 | store_reg (regno, offset, STACK_POINTER_REGNUM); | |
3929 | offset += UNITS_PER_WORD; | |
3930 | } | |
3931 | } | |
3932 | ||
3933 | for (i = 18; i >= 3; i--) | |
3072d30e | 3934 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
87ad11b0 | 3935 | { |
6d36483b | 3936 | /* If merge_sp_adjust_with_store is nonzero, then we can |
afd7b680 | 3937 | optimize the first GR save. */ |
201f01e9 | 3938 | if (merge_sp_adjust_with_store) |
afd7b680 | 3939 | { |
a584fe8a | 3940 | store_reg_modify (STACK_POINTER_REGNUM, i, -offset); |
afd7b680 | 3941 | merge_sp_adjust_with_store = 0; |
afd7b680 | 3942 | } |
3943 | else | |
6a2c16d6 | 3944 | store_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 3945 | offset += UNITS_PER_WORD; |
a9960cdc | 3946 | gr_saved++; |
87ad11b0 | 3947 | } |
daee63dd | 3948 | |
afd7b680 | 3949 | /* If we wanted to merge the SP adjustment with a GR save, but we never |
daee63dd | 3950 | did any GR saves, then just emit the adjustment here. */ |
201f01e9 | 3951 | if (merge_sp_adjust_with_store) |
6a2c16d6 | 3952 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3953 | actual_fsize, 1); |
87ad11b0 | 3954 | } |
6d36483b | 3955 | |
df6edefa | 3956 | /* The hppa calling conventions say that %r19, the pic offset |
3957 | register, is saved at sp - 32 (in this function's frame) | |
3958 | when generating PIC code. FIXME: What is the correct thing | |
3959 | to do for functions which make no calls and allocate no | |
3960 | frame? Do we need to allocate a frame, or can we just omit | |
8f177faf | 3961 | the save? For now we'll just omit the save. |
3962 | ||
3963 | We don't want a note on this insn as the frame marker can | |
3964 | move if there is a dynamic stack allocation. */ | |
df6edefa | 3965 | if (flag_pic && actual_fsize != 0 && !TARGET_64BIT) |
8f177faf | 3966 | { |
3967 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32)); | |
3968 | ||
3969 | emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx); | |
3970 | ||
3971 | } | |
df6edefa | 3972 | |
87ad11b0 | 3973 | /* Align pointer properly (doubleword boundary). */ |
3974 | offset = (offset + 7) & ~7; | |
3975 | ||
3976 | /* Floating point register store. */ | |
3977 | if (save_fregs) | |
87ad11b0 | 3978 | { |
a584fe8a | 3979 | rtx base; |
3980 | ||
daee63dd | 3981 | /* First get the frame or stack pointer to the start of the FP register |
3982 | save area. */ | |
a1ab4fa3 | 3983 | if (frame_pointer_needed) |
a584fe8a | 3984 | { |
68bc9ae6 | 3985 | set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0); |
3986 | base = hard_frame_pointer_rtx; | |
a584fe8a | 3987 | } |
a1ab4fa3 | 3988 | else |
a584fe8a | 3989 | { |
3990 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); | |
3991 | base = stack_pointer_rtx; | |
3992 | } | |
daee63dd | 3993 | |
3994 | /* Now actually save the FP registers. */ | |
bac38c40 | 3995 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
7f7c4869 | 3996 | { |
3072d30e | 3997 | if (df_regs_ever_live_p (i) |
3998 | || (! TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
7f7c4869 | 3999 | { |
6a2c16d6 | 4000 | rtx addr, insn, reg; |
cc858176 | 4001 | addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); |
4002 | reg = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 4003 | insn = emit_move_insn (addr, reg); |
4004 | if (DO_FRAME_NOTES) | |
4005 | { | |
4006 | RTX_FRAME_RELATED_P (insn) = 1; | |
a584fe8a | 4007 | if (TARGET_64BIT) |
4008 | { | |
4009 | rtx mem = gen_rtx_MEM (DFmode, | |
4010 | plus_constant (base, offset)); | |
b9c74b4d | 4011 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
4012 | gen_rtx_SET (VOIDmode, mem, reg)); | |
a584fe8a | 4013 | } |
4014 | else | |
4015 | { | |
4016 | rtx meml = gen_rtx_MEM (SFmode, | |
4017 | plus_constant (base, offset)); | |
4018 | rtx memr = gen_rtx_MEM (SFmode, | |
4019 | plus_constant (base, offset + 4)); | |
4020 | rtx regl = gen_rtx_REG (SFmode, i); | |
4021 | rtx regr = gen_rtx_REG (SFmode, i + 1); | |
4022 | rtx setl = gen_rtx_SET (VOIDmode, meml, regl); | |
4023 | rtx setr = gen_rtx_SET (VOIDmode, memr, regr); | |
4024 | rtvec vec; | |
4025 | ||
4026 | RTX_FRAME_RELATED_P (setl) = 1; | |
4027 | RTX_FRAME_RELATED_P (setr) = 1; | |
4028 | vec = gen_rtvec (2, setl, setr); | |
b9c74b4d | 4029 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
4030 | gen_rtx_SEQUENCE (VOIDmode, vec)); | |
a584fe8a | 4031 | } |
6a2c16d6 | 4032 | } |
4033 | offset += GET_MODE_SIZE (DFmode); | |
7f7c4869 | 4034 | fr_saved++; |
4035 | } | |
4036 | } | |
87ad11b0 | 4037 | } |
4038 | } | |
4039 | ||
cc858176 | 4040 | /* Emit RTL to load REG from the memory location specified by BASE+DISP. |
4041 | Handle case where DISP > 8k by using the add_high_const patterns. */ | |
4042 | ||
6a2c16d6 | 4043 | static void |
6bcdc1fb | 4044 | load_reg (int reg, HOST_WIDE_INT disp, int base) |
cc858176 | 4045 | { |
6bcdc1fb | 4046 | rtx dest = gen_rtx_REG (word_mode, reg); |
4047 | rtx basereg = gen_rtx_REG (Pmode, base); | |
4048 | rtx src; | |
cc858176 | 4049 | |
cc858176 | 4050 | if (VAL_14_BITS_P (disp)) |
6bcdc1fb | 4051 | src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
4052 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) | |
cc858176 | 4053 | { |
6bcdc1fb | 4054 | rtx delta = GEN_INT (disp); |
4055 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
4056 | ||
4057 | emit_move_insn (tmpreg, delta); | |
4058 | if (TARGET_DISABLE_INDEXING) | |
4059 | { | |
4060 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
4061 | src = gen_rtx_MEM (word_mode, tmpreg); | |
4062 | } | |
4063 | else | |
4064 | src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
cc858176 | 4065 | } |
4066 | else | |
4067 | { | |
4068 | rtx delta = GEN_INT (disp); | |
4069 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
4070 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 4071 | |
cc858176 | 4072 | emit_move_insn (tmpreg, high); |
4073 | src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
cc858176 | 4074 | } |
6bcdc1fb | 4075 | |
4076 | emit_move_insn (dest, src); | |
cc858176 | 4077 | } |
daee63dd | 4078 | |
2247cc5f | 4079 | /* Update the total code bytes output to the text section. */ |
4080 | ||
4081 | static void | |
21a47bc9 | 4082 | update_total_code_bytes (unsigned int nbytes) |
2247cc5f | 4083 | { |
4084 | if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM) | |
8a05c3c2 | 4085 | && !IN_NAMED_SECTION_P (cfun->decl)) |
2247cc5f | 4086 | { |
21a47bc9 | 4087 | unsigned int old_total = total_code_bytes; |
2247cc5f | 4088 | |
21a47bc9 | 4089 | total_code_bytes += nbytes; |
2247cc5f | 4090 | |
21a47bc9 | 4091 | /* Be prepared to handle overflows. */ |
4092 | if (old_total > total_code_bytes) | |
4093 | total_code_bytes = UINT_MAX; | |
2247cc5f | 4094 | } |
4095 | } | |
4096 | ||
17d9b0c3 | 4097 | /* This function generates the assembly code for function exit. |
4098 | Args are as for output_function_prologue (). | |
4099 | ||
4100 | The function epilogue should not depend on the current stack | |
4101 | pointer! It should use the frame pointer only. This is mandatory | |
4102 | because of alloca; we also take advantage of it to omit stack | |
6dc3b0d9 | 4103 | adjustments before returning. */ |
17d9b0c3 | 4104 | |
4105 | static void | |
5c1d8983 | 4106 | pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 4107 | { |
3695c664 | 4108 | rtx insn = get_last_insn (); |
4109 | ||
2247cc5f | 4110 | last_address = 0; |
4111 | ||
daee63dd | 4112 | /* hppa_expand_epilogue does the dirty work now. We just need |
4113 | to output the assembler directives which denote the end | |
3695c664 | 4114 | of a function. |
4115 | ||
4116 | To make debuggers happy, emit a nop if the epilogue was completely | |
4117 | eliminated due to a volatile call as the last insn in the | |
6d36483b | 4118 | current function. That way the return address (in %r2) will |
3695c664 | 4119 | always point to a valid instruction in the current function. */ |
4120 | ||
4121 | /* Get the last real insn. */ | |
4122 | if (GET_CODE (insn) == NOTE) | |
4123 | insn = prev_real_insn (insn); | |
4124 | ||
4125 | /* If it is a sequence, then look inside. */ | |
4126 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
4127 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
4128 | ||
6d36483b | 4129 | /* If insn is a CALL_INSN, then it must be a call to a volatile |
3695c664 | 4130 | function (otherwise there would be epilogue insns). */ |
4131 | if (insn && GET_CODE (insn) == CALL_INSN) | |
90c41894 | 4132 | { |
4133 | fputs ("\tnop\n", file); | |
4134 | last_address += 4; | |
4135 | } | |
6d36483b | 4136 | |
9c0ac0fd | 4137 | fputs ("\t.EXIT\n\t.PROCEND\n", file); |
90c41894 | 4138 | |
916c9cef | 4139 | if (TARGET_SOM && TARGET_GAS) |
4140 | { | |
4141 | /* We done with this subspace except possibly for some additional | |
4142 | debug information. Forget that we are in this subspace to ensure | |
4143 | that the next function is output in its own subspace. */ | |
2f14b1f9 | 4144 | in_section = NULL; |
78962d38 | 4145 | cfun->machine->in_nsubspa = 2; |
916c9cef | 4146 | } |
4147 | ||
2247cc5f | 4148 | if (INSN_ADDRESSES_SET_P ()) |
90c41894 | 4149 | { |
2247cc5f | 4150 | insn = get_last_nonnote_insn (); |
4151 | last_address += INSN_ADDRESSES (INSN_UID (insn)); | |
4152 | if (INSN_P (insn)) | |
4153 | last_address += insn_default_length (insn); | |
4154 | last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) | |
4155 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
90c41894 | 4156 | } |
21a47bc9 | 4157 | else |
4158 | last_address = UINT_MAX; | |
2247cc5f | 4159 | |
4160 | /* Finally, update the total number of code bytes output so far. */ | |
4161 | update_total_code_bytes (last_address); | |
daee63dd | 4162 | } |
afd7b680 | 4163 | |
daee63dd | 4164 | void |
5c1d8983 | 4165 | hppa_expand_epilogue (void) |
daee63dd | 4166 | { |
6d36483b | 4167 | rtx tmpreg; |
6bcdc1fb | 4168 | HOST_WIDE_INT offset; |
4169 | HOST_WIDE_INT ret_off = 0; | |
4170 | int i; | |
58361f39 | 4171 | int merge_sp_adjust_with_load = 0; |
daee63dd | 4172 | |
4173 | /* We will use this often. */ | |
440c23df | 4174 | tmpreg = gen_rtx_REG (word_mode, 1); |
daee63dd | 4175 | |
4176 | /* Try to restore RP early to avoid load/use interlocks when | |
4177 | RP gets used in the return (bv) instruction. This appears to still | |
6dc3b0d9 | 4178 | be necessary even when we schedule the prologue and epilogue. */ |
df6b92e4 | 4179 | if (rp_saved) |
58361f39 | 4180 | { |
4181 | ret_off = TARGET_64BIT ? -16 : -20; | |
4182 | if (frame_pointer_needed) | |
4183 | { | |
68bc9ae6 | 4184 | load_reg (2, ret_off, HARD_FRAME_POINTER_REGNUM); |
58361f39 | 4185 | ret_off = 0; |
4186 | } | |
4187 | else | |
4188 | { | |
4189 | /* No frame pointer, and stack is smaller than 8k. */ | |
4190 | if (VAL_14_BITS_P (ret_off - actual_fsize)) | |
4191 | { | |
6a2c16d6 | 4192 | load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM); |
58361f39 | 4193 | ret_off = 0; |
4194 | } | |
4195 | } | |
4196 | } | |
daee63dd | 4197 | |
4198 | /* General register restores. */ | |
87ad11b0 | 4199 | if (frame_pointer_needed) |
4200 | { | |
a584fe8a | 4201 | offset = local_fsize; |
4202 | ||
4203 | /* If the current function calls __builtin_eh_return, then we need | |
4204 | to restore the saved EH data registers. */ | |
18d50ae6 | 4205 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 4206 | { |
4207 | unsigned int i, regno; | |
4208 | ||
4209 | for (i = 0; ; ++i) | |
4210 | { | |
4211 | regno = EH_RETURN_DATA_REGNO (i); | |
4212 | if (regno == INVALID_REGNUM) | |
4213 | break; | |
4214 | ||
68bc9ae6 | 4215 | load_reg (regno, offset, HARD_FRAME_POINTER_REGNUM); |
a584fe8a | 4216 | offset += UNITS_PER_WORD; |
4217 | } | |
4218 | } | |
4219 | ||
4220 | for (i = 18; i >= 4; i--) | |
3072d30e | 4221 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
87ad11b0 | 4222 | { |
68bc9ae6 | 4223 | load_reg (i, offset, HARD_FRAME_POINTER_REGNUM); |
6ec4380b | 4224 | offset += UNITS_PER_WORD; |
87ad11b0 | 4225 | } |
87ad11b0 | 4226 | } |
4227 | else | |
4228 | { | |
a584fe8a | 4229 | offset = local_fsize - actual_fsize; |
4230 | ||
4231 | /* If the current function calls __builtin_eh_return, then we need | |
4232 | to restore the saved EH data registers. */ | |
18d50ae6 | 4233 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 4234 | { |
4235 | unsigned int i, regno; | |
4236 | ||
4237 | for (i = 0; ; ++i) | |
4238 | { | |
4239 | regno = EH_RETURN_DATA_REGNO (i); | |
4240 | if (regno == INVALID_REGNUM) | |
4241 | break; | |
4242 | ||
4243 | /* Only for the first load. | |
4244 | merge_sp_adjust_with_load holds the register load | |
4245 | with which we will merge the sp adjustment. */ | |
4246 | if (merge_sp_adjust_with_load == 0 | |
4247 | && local_fsize == 0 | |
4248 | && VAL_14_BITS_P (-actual_fsize)) | |
4249 | merge_sp_adjust_with_load = regno; | |
4250 | else | |
4251 | load_reg (regno, offset, STACK_POINTER_REGNUM); | |
4252 | offset += UNITS_PER_WORD; | |
4253 | } | |
4254 | } | |
4255 | ||
4256 | for (i = 18; i >= 3; i--) | |
7f7c4869 | 4257 | { |
3072d30e | 4258 | if (df_regs_ever_live_p (i) && ! call_used_regs[i]) |
7f7c4869 | 4259 | { |
7f7c4869 | 4260 | /* Only for the first load. |
4261 | merge_sp_adjust_with_load holds the register load | |
4262 | with which we will merge the sp adjustment. */ | |
58361f39 | 4263 | if (merge_sp_adjust_with_load == 0 |
7f7c4869 | 4264 | && local_fsize == 0 |
58361f39 | 4265 | && VAL_14_BITS_P (-actual_fsize)) |
7f7c4869 | 4266 | merge_sp_adjust_with_load = i; |
4267 | else | |
6a2c16d6 | 4268 | load_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 4269 | offset += UNITS_PER_WORD; |
7f7c4869 | 4270 | } |
4271 | } | |
87ad11b0 | 4272 | } |
daee63dd | 4273 | |
87ad11b0 | 4274 | /* Align pointer properly (doubleword boundary). */ |
4275 | offset = (offset + 7) & ~7; | |
4276 | ||
daee63dd | 4277 | /* FP register restores. */ |
87ad11b0 | 4278 | if (save_fregs) |
87ad11b0 | 4279 | { |
daee63dd | 4280 | /* Adjust the register to index off of. */ |
a1ab4fa3 | 4281 | if (frame_pointer_needed) |
68bc9ae6 | 4282 | set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0); |
a1ab4fa3 | 4283 | else |
a584fe8a | 4284 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); |
daee63dd | 4285 | |
4286 | /* Actually do the restores now. */ | |
bac38c40 | 4287 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
3072d30e | 4288 | if (df_regs_ever_live_p (i) |
4289 | || (! TARGET_64BIT && df_regs_ever_live_p (i + 1))) | |
cc858176 | 4290 | { |
4291 | rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); | |
4292 | rtx dest = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 4293 | emit_move_insn (dest, src); |
cc858176 | 4294 | } |
87ad11b0 | 4295 | } |
daee63dd | 4296 | |
14660146 | 4297 | /* Emit a blockage insn here to keep these insns from being moved to |
4298 | an earlier spot in the epilogue, or into the main instruction stream. | |
4299 | ||
4300 | This is necessary as we must not cut the stack back before all the | |
4301 | restores are finished. */ | |
4302 | emit_insn (gen_blockage ()); | |
daee63dd | 4303 | |
9840d99d | 4304 | /* Reset stack pointer (and possibly frame pointer). The stack |
42819d4e | 4305 | pointer is initially set to fp + 64 to avoid a race condition. */ |
58361f39 | 4306 | if (frame_pointer_needed) |
87ad11b0 | 4307 | { |
cc858176 | 4308 | rtx delta = GEN_INT (-64); |
a584fe8a | 4309 | |
68bc9ae6 | 4310 | set_reg_plus_d (STACK_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM, 64, 0); |
4311 | emit_insn (gen_pre_load (hard_frame_pointer_rtx, | |
4312 | stack_pointer_rtx, delta)); | |
87ad11b0 | 4313 | } |
daee63dd | 4314 | /* If we were deferring a callee register restore, do it now. */ |
58361f39 | 4315 | else if (merge_sp_adjust_with_load) |
4316 | { | |
4317 | rtx delta = GEN_INT (-actual_fsize); | |
cc858176 | 4318 | rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load); |
a584fe8a | 4319 | |
4320 | emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)); | |
58361f39 | 4321 | } |
daee63dd | 4322 | else if (actual_fsize != 0) |
a584fe8a | 4323 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
4324 | - actual_fsize, 0); | |
58361f39 | 4325 | |
4326 | /* If we haven't restored %r2 yet (no frame pointer, and a stack | |
4327 | frame greater than 8k), do so now. */ | |
4328 | if (ret_off != 0) | |
6a2c16d6 | 4329 | load_reg (2, ret_off, STACK_POINTER_REGNUM); |
a584fe8a | 4330 | |
18d50ae6 | 4331 | if (DO_FRAME_NOTES && crtl->calls_eh_return) |
a584fe8a | 4332 | { |
4333 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
4334 | ||
4335 | emit_insn (gen_blockage ()); | |
4336 | emit_insn (TARGET_64BIT | |
4337 | ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa) | |
4338 | : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa)); | |
4339 | } | |
fed903e9 | 4340 | } |
4341 | ||
4342 | bool | |
4343 | pa_can_use_return_insn (void) | |
4344 | { | |
4345 | if (!reload_completed) | |
4346 | return false; | |
4347 | ||
4348 | if (frame_pointer_needed) | |
4349 | return false; | |
4350 | ||
4351 | if (df_regs_ever_live_p (2)) | |
4352 | return false; | |
4353 | ||
4354 | if (crtl->profile) | |
4355 | return false; | |
4356 | ||
4357 | return compute_frame_size (get_frame_size (), 0) == 0; | |
87ad11b0 | 4358 | } |
4359 | ||
d7e2f694 | 4360 | rtx |
5c1d8983 | 4361 | hppa_pic_save_rtx (void) |
cf3de5bb | 4362 | { |
d7e2f694 | 4363 | return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM); |
df6edefa | 4364 | } |
4365 | ||
bb1bc2ca | 4366 | #ifndef NO_DEFERRED_PROFILE_COUNTERS |
4367 | #define NO_DEFERRED_PROFILE_COUNTERS 0 | |
4368 | #endif | |
4369 | ||
bb1bc2ca | 4370 | |
4371 | /* Vector of funcdef numbers. */ | |
4372 | static VEC(int,heap) *funcdef_nos; | |
4373 | ||
4374 | /* Output deferred profile counters. */ | |
4375 | static void | |
4376 | output_deferred_profile_counters (void) | |
4377 | { | |
4378 | unsigned int i; | |
4379 | int align, n; | |
4380 | ||
4381 | if (VEC_empty (int, funcdef_nos)) | |
4382 | return; | |
4383 | ||
2f14b1f9 | 4384 | switch_to_section (data_section); |
bb1bc2ca | 4385 | align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE); |
4386 | ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT)); | |
4387 | ||
4388 | for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++) | |
4389 | { | |
4390 | targetm.asm_out.internal_label (asm_out_file, "LP", n); | |
4391 | assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1); | |
4392 | } | |
4393 | ||
4394 | VEC_free (int, heap, funcdef_nos); | |
4395 | } | |
4396 | ||
df6edefa | 4397 | void |
5c1d8983 | 4398 | hppa_profile_hook (int label_no) |
df6edefa | 4399 | { |
4da37e2f | 4400 | /* We use SImode for the address of the function in both 32 and |
4401 | 64-bit code to avoid having to provide DImode versions of the | |
4402 | lcla2 and load_offset_label_address insn patterns. */ | |
4403 | rtx reg = gen_reg_rtx (SImode); | |
4404 | rtx label_rtx = gen_label_rtx (); | |
a9ac13e4 | 4405 | rtx begin_label_rtx, call_insn; |
4406 | char begin_label_name[16]; | |
df6edefa | 4407 | |
a9ac13e4 | 4408 | ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL, |
b8a21949 | 4409 | label_no); |
4da37e2f | 4410 | begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name)); |
df6edefa | 4411 | |
4412 | if (TARGET_64BIT) | |
4413 | emit_move_insn (arg_pointer_rtx, | |
4414 | gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, | |
4415 | GEN_INT (64))); | |
4416 | ||
df6edefa | 4417 | emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2)); |
4418 | ||
80777cd8 | 4419 | /* The address of the function is loaded into %r25 with an instruction- |
4da37e2f | 4420 | relative sequence that avoids the use of relocations. The sequence |
4421 | is split so that the load_offset_label_address instruction can | |
4422 | occupy the delay slot of the call to _mcount. */ | |
4423 | if (TARGET_PA_20) | |
4424 | emit_insn (gen_lcla2 (reg, label_rtx)); | |
4425 | else | |
4426 | emit_insn (gen_lcla1 (reg, label_rtx)); | |
4427 | ||
4428 | emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25), | |
4429 | reg, begin_label_rtx, label_rtx)); | |
4430 | ||
bb1bc2ca | 4431 | #if !NO_DEFERRED_PROFILE_COUNTERS |
df6edefa | 4432 | { |
4433 | rtx count_label_rtx, addr, r24; | |
a9ac13e4 | 4434 | char count_label_name[16]; |
df6edefa | 4435 | |
bb1bc2ca | 4436 | VEC_safe_push (int, heap, funcdef_nos, label_no); |
a9ac13e4 | 4437 | ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no); |
4438 | count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name)); | |
df6edefa | 4439 | |
831a12d9 | 4440 | addr = force_reg (Pmode, count_label_rtx); |
df6edefa | 4441 | r24 = gen_rtx_REG (Pmode, 24); |
4442 | emit_move_insn (r24, addr); | |
4443 | ||
df6edefa | 4444 | call_insn = |
4da37e2f | 4445 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4446 | gen_rtx_SYMBOL_REF (Pmode, | |
4447 | "_mcount")), | |
4448 | GEN_INT (TARGET_64BIT ? 24 : 12))); | |
df6edefa | 4449 | |
4450 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24); | |
4451 | } | |
4452 | #else | |
4da37e2f | 4453 | |
df6edefa | 4454 | call_insn = |
4da37e2f | 4455 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4456 | gen_rtx_SYMBOL_REF (Pmode, | |
4457 | "_mcount")), | |
4458 | GEN_INT (TARGET_64BIT ? 16 : 8))); | |
4459 | ||
df6edefa | 4460 | #endif |
4461 | ||
4da37e2f | 4462 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25)); |
4463 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26)); | |
4464 | ||
df6edefa | 4465 | /* Indicate the _mcount call cannot throw, nor will it execute a |
4466 | non-local goto. */ | |
450040e5 | 4467 | make_reg_eh_region_note_nothrow_nononlocal (call_insn); |
cf3de5bb | 4468 | } |
4469 | ||
e07ff380 | 4470 | /* Fetch the return address for the frame COUNT steps up from |
4471 | the current frame, after the prologue. FRAMEADDR is the | |
4472 | frame pointer of the COUNT frame. | |
4473 | ||
f49b2e77 | 4474 | We want to ignore any export stub remnants here. To handle this, |
4475 | we examine the code at the return address, and if it is an export | |
4476 | stub, we return a memory rtx for the stub return address stored | |
4477 | at frame-24. | |
a6c6fd6c | 4478 | |
4479 | The value returned is used in two different ways: | |
4480 | ||
4481 | 1. To find a function's caller. | |
4482 | ||
4483 | 2. To change the return address for a function. | |
4484 | ||
4485 | This function handles most instances of case 1; however, it will | |
4486 | fail if there are two levels of stubs to execute on the return | |
4487 | path. The only way I believe that can happen is if the return value | |
4488 | needs a parameter relocation, which never happens for C code. | |
4489 | ||
4490 | This function handles most instances of case 2; however, it will | |
4491 | fail if we did not originally have stub code on the return path | |
f49b2e77 | 4492 | but will need stub code on the new return path. This can happen if |
a6c6fd6c | 4493 | the caller & callee are both in the main program, but the new |
f49b2e77 | 4494 | return location is in a shared library. */ |
e07ff380 | 4495 | |
4496 | rtx | |
5c1d8983 | 4497 | return_addr_rtx (int count, rtx frameaddr) |
e07ff380 | 4498 | { |
4499 | rtx label; | |
f49b2e77 | 4500 | rtx rp; |
e07ff380 | 4501 | rtx saved_rp; |
4502 | rtx ins; | |
4503 | ||
74f4459c | 4504 | /* Instruction stream at the normal return address for the export stub: |
4505 | ||
4506 | 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp | |
4507 | 0x004010a1 | stub+12: ldsid (sr0,rp),r1 | |
4508 | 0x00011820 | stub+16: mtsp r1,sr0 | |
4509 | 0xe0400002 | stub+20: be,n 0(sr0,rp) | |
4510 | ||
4511 | 0xe0400002 must be specified as -532676606 so that it won't be | |
4512 | rejected as an invalid immediate operand on 64-bit hosts. */ | |
4513 | ||
4514 | HOST_WIDE_INT insns[4] = {0x4bc23fd1, 0x004010a1, 0x00011820, -532676606}; | |
4515 | int i; | |
4516 | ||
f49b2e77 | 4517 | if (count != 0) |
4518 | return NULL_RTX; | |
b29897dd | 4519 | |
f49b2e77 | 4520 | rp = get_hard_reg_initial_val (Pmode, 2); |
e07ff380 | 4521 | |
f49b2e77 | 4522 | if (TARGET_64BIT || TARGET_NO_SPACE_REGS) |
4523 | return rp; | |
e07ff380 | 4524 | |
74f4459c | 4525 | /* If there is no export stub then just use the value saved from |
4526 | the return pointer register. */ | |
4527 | ||
b29897dd | 4528 | saved_rp = gen_reg_rtx (Pmode); |
f49b2e77 | 4529 | emit_move_insn (saved_rp, rp); |
e07ff380 | 4530 | |
4531 | /* Get pointer to the instruction stream. We have to mask out the | |
4532 | privilege level from the two low order bits of the return address | |
4533 | pointer here so that ins will point to the start of the first | |
4534 | instruction that would have been executed if we returned. */ | |
f49b2e77 | 4535 | ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR)); |
e07ff380 | 4536 | label = gen_label_rtx (); |
4537 | ||
4538 | /* Check the instruction stream at the normal return address for the | |
74f4459c | 4539 | export stub. If it is an export stub, than our return address is |
4540 | really in -24[frameaddr]. */ | |
e07ff380 | 4541 | |
74f4459c | 4542 | for (i = 0; i < 3; i++) |
4543 | { | |
4544 | rtx op0 = gen_rtx_MEM (SImode, plus_constant (ins, i * 4)); | |
4545 | rtx op1 = GEN_INT (insns[i]); | |
4546 | emit_cmp_and_jump_insns (op0, op1, NE, NULL, SImode, 0, label); | |
4547 | } | |
e07ff380 | 4548 | |
f49b2e77 | 4549 | /* Here we know that our return address points to an export |
e07ff380 | 4550 | stub. We don't want to return the address of the export stub, |
f49b2e77 | 4551 | but rather the return address of the export stub. That return |
4552 | address is stored at -24[frameaddr]. */ | |
e07ff380 | 4553 | |
f49b2e77 | 4554 | emit_move_insn (saved_rp, |
4555 | gen_rtx_MEM (Pmode, | |
4556 | memory_address (Pmode, | |
4557 | plus_constant (frameaddr, | |
4558 | -24)))); | |
e07ff380 | 4559 | |
4560 | emit_label (label); | |
74f4459c | 4561 | |
f49b2e77 | 4562 | return saved_rp; |
e07ff380 | 4563 | } |
4564 | ||
87ad11b0 | 4565 | void |
74f4459c | 4566 | emit_bcond_fp (rtx operands[]) |
87ad11b0 | 4567 | { |
74f4459c | 4568 | enum rtx_code code = GET_CODE (operands[0]); |
4569 | rtx operand0 = operands[1]; | |
4570 | rtx operand1 = operands[2]; | |
4571 | rtx label = operands[3]; | |
4572 | ||
4573 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0), | |
4574 | gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1))); | |
4575 | ||
ad851752 | 4576 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, |
4577 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
74f4459c | 4578 | gen_rtx_fmt_ee (NE, |
ad851752 | 4579 | VOIDmode, |
4580 | gen_rtx_REG (CCFPmode, 0), | |
4581 | const0_rtx), | |
74f4459c | 4582 | gen_rtx_LABEL_REF (VOIDmode, label), |
ad851752 | 4583 | pc_rtx))); |
87ad11b0 | 4584 | |
4585 | } | |
4586 | ||
8b49b3c7 | 4587 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
4588 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4589 | ||
747af5e7 | 4590 | static int |
5c1d8983 | 4591 | pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
8b49b3c7 | 4592 | { |
43048d2c | 4593 | enum attr_type attr_type; |
4594 | ||
cde3e16c | 4595 | /* Don't adjust costs for a pa8000 chip, also do not adjust any |
4596 | true dependencies as they are described with bypasses now. */ | |
4597 | if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0) | |
342aabd9 | 4598 | return cost; |
4599 | ||
d402da4b | 4600 | if (! recog_memoized (insn)) |
4601 | return 0; | |
8b49b3c7 | 4602 | |
43048d2c | 4603 | attr_type = get_attr_type (insn); |
4604 | ||
ecf2283d | 4605 | switch (REG_NOTE_KIND (link)) |
8b49b3c7 | 4606 | { |
ecf2283d | 4607 | case REG_DEP_ANTI: |
8b49b3c7 | 4608 | /* Anti dependency; DEP_INSN reads a register that INSN writes some |
4609 | cycles later. */ | |
4610 | ||
43048d2c | 4611 | if (attr_type == TYPE_FPLOAD) |
8b49b3c7 | 4612 | { |
d402da4b | 4613 | rtx pat = PATTERN (insn); |
4614 | rtx dep_pat = PATTERN (dep_insn); | |
4615 | if (GET_CODE (pat) == PARALLEL) | |
4616 | { | |
4617 | /* This happens for the fldXs,mb patterns. */ | |
4618 | pat = XVECEXP (pat, 0, 0); | |
4619 | } | |
4620 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
8b49b3c7 | 4621 | /* If this happens, we have to extend this to schedule |
d402da4b | 4622 | optimally. Return 0 for now. */ |
4623 | return 0; | |
8b49b3c7 | 4624 | |
d402da4b | 4625 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) |
8b49b3c7 | 4626 | { |
d402da4b | 4627 | if (! recog_memoized (dep_insn)) |
4628 | return 0; | |
8b49b3c7 | 4629 | switch (get_attr_type (dep_insn)) |
4630 | { | |
4631 | case TYPE_FPALU: | |
134b4858 | 4632 | case TYPE_FPMULSGL: |
4633 | case TYPE_FPMULDBL: | |
8b49b3c7 | 4634 | case TYPE_FPDIVSGL: |
4635 | case TYPE_FPDIVDBL: | |
4636 | case TYPE_FPSQRTSGL: | |
4637 | case TYPE_FPSQRTDBL: | |
d402da4b | 4638 | /* A fpload can't be issued until one cycle before a |
01cc3b75 | 4639 | preceding arithmetic operation has finished if |
d402da4b | 4640 | the target of the fpload is any of the sources |
4641 | (or destination) of the arithmetic operation. */ | |
cde3e16c | 4642 | return insn_default_latency (dep_insn) - 1; |
134b4858 | 4643 | |
4644 | default: | |
4645 | return 0; | |
4646 | } | |
4647 | } | |
4648 | } | |
43048d2c | 4649 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4650 | { |
4651 | rtx pat = PATTERN (insn); | |
4652 | rtx dep_pat = PATTERN (dep_insn); | |
4653 | if (GET_CODE (pat) == PARALLEL) | |
4654 | { | |
4655 | /* This happens for the fldXs,mb patterns. */ | |
4656 | pat = XVECEXP (pat, 0, 0); | |
4657 | } | |
4658 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4659 | /* If this happens, we have to extend this to schedule | |
4660 | optimally. Return 0 for now. */ | |
4661 | return 0; | |
4662 | ||
4663 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) | |
4664 | { | |
4665 | if (! recog_memoized (dep_insn)) | |
4666 | return 0; | |
4667 | switch (get_attr_type (dep_insn)) | |
4668 | { | |
4669 | case TYPE_FPDIVSGL: | |
4670 | case TYPE_FPDIVDBL: | |
4671 | case TYPE_FPSQRTSGL: | |
4672 | case TYPE_FPSQRTDBL: | |
4673 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4674 | preceding divide or sqrt operation has finished if |
134b4858 | 4675 | the target of the ALU flop is any of the sources |
4676 | (or destination) of the divide or sqrt operation. */ | |
cde3e16c | 4677 | return insn_default_latency (dep_insn) - 2; |
8b49b3c7 | 4678 | |
4679 | default: | |
4680 | return 0; | |
4681 | } | |
4682 | } | |
4683 | } | |
4684 | ||
4685 | /* For other anti dependencies, the cost is 0. */ | |
4686 | return 0; | |
ecf2283d | 4687 | |
4688 | case REG_DEP_OUTPUT: | |
134b4858 | 4689 | /* Output dependency; DEP_INSN writes a register that INSN writes some |
4690 | cycles later. */ | |
43048d2c | 4691 | if (attr_type == TYPE_FPLOAD) |
134b4858 | 4692 | { |
4693 | rtx pat = PATTERN (insn); | |
4694 | rtx dep_pat = PATTERN (dep_insn); | |
4695 | if (GET_CODE (pat) == PARALLEL) | |
4696 | { | |
4697 | /* This happens for the fldXs,mb patterns. */ | |
4698 | pat = XVECEXP (pat, 0, 0); | |
4699 | } | |
4700 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4701 | /* If this happens, we have to extend this to schedule | |
4702 | optimally. Return 0 for now. */ | |
4703 | return 0; | |
4704 | ||
4705 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4706 | { | |
4707 | if (! recog_memoized (dep_insn)) | |
4708 | return 0; | |
4709 | switch (get_attr_type (dep_insn)) | |
4710 | { | |
4711 | case TYPE_FPALU: | |
4712 | case TYPE_FPMULSGL: | |
4713 | case TYPE_FPMULDBL: | |
4714 | case TYPE_FPDIVSGL: | |
4715 | case TYPE_FPDIVDBL: | |
4716 | case TYPE_FPSQRTSGL: | |
4717 | case TYPE_FPSQRTDBL: | |
4718 | /* A fpload can't be issued until one cycle before a | |
01cc3b75 | 4719 | preceding arithmetic operation has finished if |
134b4858 | 4720 | the target of the fpload is the destination of the |
bea4bad2 | 4721 | arithmetic operation. |
4722 | ||
4723 | Exception: For PA7100LC, PA7200 and PA7300, the cost | |
4724 | is 3 cycles, unless they bundle together. We also | |
4725 | pay the penalty if the second insn is a fpload. */ | |
cde3e16c | 4726 | return insn_default_latency (dep_insn) - 1; |
8b49b3c7 | 4727 | |
134b4858 | 4728 | default: |
4729 | return 0; | |
4730 | } | |
4731 | } | |
4732 | } | |
43048d2c | 4733 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4734 | { |
4735 | rtx pat = PATTERN (insn); | |
4736 | rtx dep_pat = PATTERN (dep_insn); | |
4737 | if (GET_CODE (pat) == PARALLEL) | |
4738 | { | |
4739 | /* This happens for the fldXs,mb patterns. */ | |
4740 | pat = XVECEXP (pat, 0, 0); | |
4741 | } | |
4742 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4743 | /* If this happens, we have to extend this to schedule | |
4744 | optimally. Return 0 for now. */ | |
4745 | return 0; | |
4746 | ||
4747 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4748 | { | |
4749 | if (! recog_memoized (dep_insn)) | |
4750 | return 0; | |
4751 | switch (get_attr_type (dep_insn)) | |
4752 | { | |
4753 | case TYPE_FPDIVSGL: | |
4754 | case TYPE_FPDIVDBL: | |
4755 | case TYPE_FPSQRTSGL: | |
4756 | case TYPE_FPSQRTDBL: | |
4757 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4758 | preceding divide or sqrt operation has finished if |
134b4858 | 4759 | the target of the ALU flop is also the target of |
3398e91d | 4760 | the divide or sqrt operation. */ |
cde3e16c | 4761 | return insn_default_latency (dep_insn) - 2; |
134b4858 | 4762 | |
4763 | default: | |
4764 | return 0; | |
4765 | } | |
4766 | } | |
4767 | } | |
4768 | ||
4769 | /* For other output dependencies, the cost is 0. */ | |
4770 | return 0; | |
ecf2283d | 4771 | |
4772 | default: | |
4773 | gcc_unreachable (); | |
134b4858 | 4774 | } |
8b49b3c7 | 4775 | } |
87ad11b0 | 4776 | |
747af5e7 | 4777 | /* Adjust scheduling priorities. We use this to try and keep addil |
4778 | and the next use of %r1 close together. */ | |
4779 | static int | |
5c1d8983 | 4780 | pa_adjust_priority (rtx insn, int priority) |
747af5e7 | 4781 | { |
4782 | rtx set = single_set (insn); | |
4783 | rtx src, dest; | |
4784 | if (set) | |
4785 | { | |
4786 | src = SET_SRC (set); | |
4787 | dest = SET_DEST (set); | |
4788 | if (GET_CODE (src) == LO_SUM | |
4789 | && symbolic_operand (XEXP (src, 1), VOIDmode) | |
4790 | && ! read_only_operand (XEXP (src, 1), VOIDmode)) | |
4791 | priority >>= 3; | |
4792 | ||
4793 | else if (GET_CODE (src) == MEM | |
4794 | && GET_CODE (XEXP (src, 0)) == LO_SUM | |
4795 | && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode) | |
4796 | && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode)) | |
4797 | priority >>= 1; | |
4798 | ||
4799 | else if (GET_CODE (dest) == MEM | |
4800 | && GET_CODE (XEXP (dest, 0)) == LO_SUM | |
4801 | && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode) | |
4802 | && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)) | |
4803 | priority >>= 3; | |
4804 | } | |
4805 | return priority; | |
4806 | } | |
4807 | ||
4808 | /* The 700 can only issue a single insn at a time. | |
4809 | The 7XXX processors can issue two insns at a time. | |
4810 | The 8000 can issue 4 insns at a time. */ | |
4811 | static int | |
5c1d8983 | 4812 | pa_issue_rate (void) |
747af5e7 | 4813 | { |
4814 | switch (pa_cpu) | |
4815 | { | |
4816 | case PROCESSOR_700: return 1; | |
4817 | case PROCESSOR_7100: return 2; | |
4818 | case PROCESSOR_7100LC: return 2; | |
4819 | case PROCESSOR_7200: return 2; | |
bea4bad2 | 4820 | case PROCESSOR_7300: return 2; |
747af5e7 | 4821 | case PROCESSOR_8000: return 4; |
4822 | ||
4823 | default: | |
ecf2283d | 4824 | gcc_unreachable (); |
747af5e7 | 4825 | } |
4826 | } | |
4827 | ||
4828 | ||
4829 | ||
58e17b0b | 4830 | /* Return any length adjustment needed by INSN which already has its length |
6d36483b | 4831 | computed as LENGTH. Return zero if no adjustment is necessary. |
58e17b0b | 4832 | |
5fbd5940 | 4833 | For the PA: function calls, millicode calls, and backwards short |
6d36483b | 4834 | conditional branches with unfilled delay slots need an adjustment by +1 |
5fbd5940 | 4835 | (to account for the NOP which will be inserted into the instruction stream). |
58e17b0b | 4836 | |
4837 | Also compute the length of an inline block move here as it is too | |
5fbd5940 | 4838 | complicated to express as a length attribute in pa.md. */ |
58e17b0b | 4839 | int |
5c1d8983 | 4840 | pa_adjust_insn_length (rtx insn, int length) |
58e17b0b | 4841 | { |
4842 | rtx pat = PATTERN (insn); | |
4843 | ||
faf3f8c1 | 4844 | /* Jumps inside switch tables which have unfilled delay slots need |
4845 | adjustment. */ | |
4846 | if (GET_CODE (insn) == JUMP_INSN | |
b932f66c | 4847 | && GET_CODE (pat) == PARALLEL |
4848 | && get_attr_type (insn) == TYPE_BTABLE_BRANCH) | |
3b1e673e | 4849 | return 4; |
58e17b0b | 4850 | /* Millicode insn with an unfilled delay slot. */ |
4851 | else if (GET_CODE (insn) == INSN | |
4852 | && GET_CODE (pat) != SEQUENCE | |
4853 | && GET_CODE (pat) != USE | |
4854 | && GET_CODE (pat) != CLOBBER | |
4855 | && get_attr_type (insn) == TYPE_MILLI) | |
5a1231ef | 4856 | return 4; |
58e17b0b | 4857 | /* Block move pattern. */ |
4858 | else if (GET_CODE (insn) == INSN | |
4859 | && GET_CODE (pat) == PARALLEL | |
f2ebcf32 | 4860 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET |
58e17b0b | 4861 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM |
4862 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM | |
4863 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode | |
4864 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode) | |
008c057d | 4865 | return compute_movmem_length (insn) - 4; |
a7e1bb24 | 4866 | /* Block clear pattern. */ |
4867 | else if (GET_CODE (insn) == INSN | |
4868 | && GET_CODE (pat) == PARALLEL | |
4869 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET | |
4870 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM | |
4871 | && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx | |
4872 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode) | |
008c057d | 4873 | return compute_clrmem_length (insn) - 4; |
58e17b0b | 4874 | /* Conditional branch with an unfilled delay slot. */ |
5fbd5940 | 4875 | else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn)) |
4876 | { | |
4877 | /* Adjust a short backwards conditional with an unfilled delay slot. */ | |
4878 | if (GET_CODE (pat) == SET | |
5a1231ef | 4879 | && length == 4 |
372b3fe2 | 4880 | && JUMP_LABEL (insn) != NULL_RTX |
5fbd5940 | 4881 | && ! forward_branch_p (insn)) |
5a1231ef | 4882 | return 4; |
546a40bd | 4883 | else if (GET_CODE (pat) == PARALLEL |
4884 | && get_attr_type (insn) == TYPE_PARALLEL_BRANCH | |
4885 | && length == 4) | |
4886 | return 4; | |
5fbd5940 | 4887 | /* Adjust dbra insn with short backwards conditional branch with |
6d36483b | 4888 | unfilled delay slot -- only for case where counter is in a |
6dc3b0d9 | 4889 | general register register. */ |
5fbd5940 | 4890 | else if (GET_CODE (pat) == PARALLEL |
4891 | && GET_CODE (XVECEXP (pat, 0, 1)) == SET | |
4892 | && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG | |
6d36483b | 4893 | && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0)) |
5a1231ef | 4894 | && length == 4 |
5fbd5940 | 4895 | && ! forward_branch_p (insn)) |
5a1231ef | 4896 | return 4; |
5fbd5940 | 4897 | else |
4898 | return 0; | |
4899 | } | |
546a40bd | 4900 | return 0; |
58e17b0b | 4901 | } |
4902 | ||
93d3ee56 | 4903 | /* Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook. */ |
4904 | ||
4905 | static bool | |
4906 | pa_print_operand_punct_valid_p (unsigned char code) | |
4907 | { | |
4908 | if (code == '@' | |
4909 | || code == '#' | |
4910 | || code == '*' | |
4911 | || code == '^') | |
4912 | return true; | |
4913 | ||
4914 | return false; | |
4915 | } | |
4916 | ||
87ad11b0 | 4917 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
4918 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
4919 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
4920 | ||
4921 | void | |
5c1d8983 | 4922 | print_operand (FILE *file, rtx x, int code) |
87ad11b0 | 4923 | { |
4924 | switch (code) | |
4925 | { | |
4926 | case '#': | |
4927 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
4928 | if (dbr_sequence_length () == 0) | |
4929 | fputs ("\n\tnop", file); | |
4930 | return; | |
4931 | case '*': | |
87fcb603 | 4932 | /* Output a nullification completer if there's nothing for the */ |
6d36483b | 4933 | /* delay slot or nullification is requested. */ |
87ad11b0 | 4934 | if (dbr_sequence_length () == 0 || |
4935 | (final_sequence && | |
4936 | INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))) | |
4937 | fputs (",n", file); | |
4938 | return; | |
4939 | case 'R': | |
4940 | /* Print out the second register name of a register pair. | |
4941 | I.e., R (6) => 7. */ | |
ea52c577 | 4942 | fputs (reg_names[REGNO (x) + 1], file); |
87ad11b0 | 4943 | return; |
4944 | case 'r': | |
6dc3b0d9 | 4945 | /* A register or zero. */ |
891b55b4 | 4946 | if (x == const0_rtx |
4947 | || (x == CONST0_RTX (DFmode)) | |
4948 | || (x == CONST0_RTX (SFmode))) | |
87ad11b0 | 4949 | { |
c6ae275c | 4950 | fputs ("%r0", file); |
4951 | return; | |
4952 | } | |
4953 | else | |
4954 | break; | |
4955 | case 'f': | |
6dc3b0d9 | 4956 | /* A register or zero (floating point). */ |
c6ae275c | 4957 | if (x == const0_rtx |
4958 | || (x == CONST0_RTX (DFmode)) | |
4959 | || (x == CONST0_RTX (SFmode))) | |
4960 | { | |
4961 | fputs ("%fr0", file); | |
87ad11b0 | 4962 | return; |
4963 | } | |
4964 | else | |
4965 | break; | |
2d14b1f0 | 4966 | case 'A': |
4967 | { | |
4968 | rtx xoperands[2]; | |
4969 | ||
4970 | xoperands[0] = XEXP (XEXP (x, 0), 0); | |
4971 | xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0); | |
4972 | output_global_address (file, xoperands[1], 0); | |
4973 | fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]); | |
4974 | return; | |
4975 | } | |
4976 | ||
c8975385 | 4977 | case 'C': /* Plain (C)ondition */ |
87ad11b0 | 4978 | case 'X': |
4979 | switch (GET_CODE (x)) | |
6d36483b | 4980 | { |
87ad11b0 | 4981 | case EQ: |
9c0ac0fd | 4982 | fputs ("=", file); break; |
87ad11b0 | 4983 | case NE: |
9c0ac0fd | 4984 | fputs ("<>", file); break; |
87ad11b0 | 4985 | case GT: |
9c0ac0fd | 4986 | fputs (">", file); break; |
87ad11b0 | 4987 | case GE: |
9c0ac0fd | 4988 | fputs (">=", file); break; |
87ad11b0 | 4989 | case GEU: |
9c0ac0fd | 4990 | fputs (">>=", file); break; |
87ad11b0 | 4991 | case GTU: |
9c0ac0fd | 4992 | fputs (">>", file); break; |
87ad11b0 | 4993 | case LT: |
9c0ac0fd | 4994 | fputs ("<", file); break; |
87ad11b0 | 4995 | case LE: |
9c0ac0fd | 4996 | fputs ("<=", file); break; |
87ad11b0 | 4997 | case LEU: |
9c0ac0fd | 4998 | fputs ("<<=", file); break; |
87ad11b0 | 4999 | case LTU: |
9c0ac0fd | 5000 | fputs ("<<", file); break; |
87ad11b0 | 5001 | default: |
ecf2283d | 5002 | gcc_unreachable (); |
87ad11b0 | 5003 | } |
5004 | return; | |
c8975385 | 5005 | case 'N': /* Condition, (N)egated */ |
87ad11b0 | 5006 | switch (GET_CODE (x)) |
5007 | { | |
5008 | case EQ: | |
9c0ac0fd | 5009 | fputs ("<>", file); break; |
87ad11b0 | 5010 | case NE: |
9c0ac0fd | 5011 | fputs ("=", file); break; |
87ad11b0 | 5012 | case GT: |
9c0ac0fd | 5013 | fputs ("<=", file); break; |
87ad11b0 | 5014 | case GE: |
9c0ac0fd | 5015 | fputs ("<", file); break; |
87ad11b0 | 5016 | case GEU: |
9c0ac0fd | 5017 | fputs ("<<", file); break; |
87ad11b0 | 5018 | case GTU: |
9c0ac0fd | 5019 | fputs ("<<=", file); break; |
87ad11b0 | 5020 | case LT: |
9c0ac0fd | 5021 | fputs (">=", file); break; |
87ad11b0 | 5022 | case LE: |
9c0ac0fd | 5023 | fputs (">", file); break; |
87ad11b0 | 5024 | case LEU: |
9c0ac0fd | 5025 | fputs (">>", file); break; |
87ad11b0 | 5026 | case LTU: |
9c0ac0fd | 5027 | fputs (">>=", file); break; |
87ad11b0 | 5028 | default: |
ecf2283d | 5029 | gcc_unreachable (); |
87ad11b0 | 5030 | } |
5031 | return; | |
ea52c577 | 5032 | /* For floating point comparisons. Note that the output |
321c1598 | 5033 | predicates are the complement of the desired mode. The |
5034 | conditions for GT, GE, LT, LE and LTGT cause an invalid | |
5035 | operation exception if the result is unordered and this | |
5036 | exception is enabled in the floating-point status register. */ | |
61230bc9 | 5037 | case 'Y': |
5038 | switch (GET_CODE (x)) | |
5039 | { | |
5040 | case EQ: | |
9c0ac0fd | 5041 | fputs ("!=", file); break; |
61230bc9 | 5042 | case NE: |
9c0ac0fd | 5043 | fputs ("=", file); break; |
61230bc9 | 5044 | case GT: |
32509e56 | 5045 | fputs ("!>", file); break; |
61230bc9 | 5046 | case GE: |
32509e56 | 5047 | fputs ("!>=", file); break; |
61230bc9 | 5048 | case LT: |
32509e56 | 5049 | fputs ("!<", file); break; |
61230bc9 | 5050 | case LE: |
32509e56 | 5051 | fputs ("!<=", file); break; |
5052 | case LTGT: | |
5053 | fputs ("!<>", file); break; | |
5054 | case UNLE: | |
321c1598 | 5055 | fputs ("!?<=", file); break; |
32509e56 | 5056 | case UNLT: |
321c1598 | 5057 | fputs ("!?<", file); break; |
32509e56 | 5058 | case UNGE: |
321c1598 | 5059 | fputs ("!?>=", file); break; |
32509e56 | 5060 | case UNGT: |
321c1598 | 5061 | fputs ("!?>", file); break; |
32509e56 | 5062 | case UNEQ: |
321c1598 | 5063 | fputs ("!?=", file); break; |
32509e56 | 5064 | case UNORDERED: |
321c1598 | 5065 | fputs ("!?", file); break; |
32509e56 | 5066 | case ORDERED: |
321c1598 | 5067 | fputs ("?", file); break; |
61230bc9 | 5068 | default: |
ecf2283d | 5069 | gcc_unreachable (); |
61230bc9 | 5070 | } |
5071 | return; | |
c8975385 | 5072 | case 'S': /* Condition, operands are (S)wapped. */ |
5073 | switch (GET_CODE (x)) | |
5074 | { | |
5075 | case EQ: | |
9c0ac0fd | 5076 | fputs ("=", file); break; |
c8975385 | 5077 | case NE: |
9c0ac0fd | 5078 | fputs ("<>", file); break; |
c8975385 | 5079 | case GT: |
9c0ac0fd | 5080 | fputs ("<", file); break; |
c8975385 | 5081 | case GE: |
9c0ac0fd | 5082 | fputs ("<=", file); break; |
c8975385 | 5083 | case GEU: |
9c0ac0fd | 5084 | fputs ("<<=", file); break; |
c8975385 | 5085 | case GTU: |
9c0ac0fd | 5086 | fputs ("<<", file); break; |
c8975385 | 5087 | case LT: |
9c0ac0fd | 5088 | fputs (">", file); break; |
c8975385 | 5089 | case LE: |
9c0ac0fd | 5090 | fputs (">=", file); break; |
c8975385 | 5091 | case LEU: |
9c0ac0fd | 5092 | fputs (">>=", file); break; |
c8975385 | 5093 | case LTU: |
9c0ac0fd | 5094 | fputs (">>", file); break; |
c8975385 | 5095 | default: |
ecf2283d | 5096 | gcc_unreachable (); |
6d36483b | 5097 | } |
c8975385 | 5098 | return; |
5099 | case 'B': /* Condition, (B)oth swapped and negate. */ | |
5100 | switch (GET_CODE (x)) | |
5101 | { | |
5102 | case EQ: | |
9c0ac0fd | 5103 | fputs ("<>", file); break; |
c8975385 | 5104 | case NE: |
9c0ac0fd | 5105 | fputs ("=", file); break; |
c8975385 | 5106 | case GT: |
9c0ac0fd | 5107 | fputs (">=", file); break; |
c8975385 | 5108 | case GE: |
9c0ac0fd | 5109 | fputs (">", file); break; |
c8975385 | 5110 | case GEU: |
9c0ac0fd | 5111 | fputs (">>", file); break; |
c8975385 | 5112 | case GTU: |
9c0ac0fd | 5113 | fputs (">>=", file); break; |
c8975385 | 5114 | case LT: |
9c0ac0fd | 5115 | fputs ("<=", file); break; |
c8975385 | 5116 | case LE: |
9c0ac0fd | 5117 | fputs ("<", file); break; |
c8975385 | 5118 | case LEU: |
9c0ac0fd | 5119 | fputs ("<<", file); break; |
c8975385 | 5120 | case LTU: |
9c0ac0fd | 5121 | fputs ("<<=", file); break; |
c8975385 | 5122 | default: |
ecf2283d | 5123 | gcc_unreachable (); |
6d36483b | 5124 | } |
c8975385 | 5125 | return; |
5126 | case 'k': | |
ecf2283d | 5127 | gcc_assert (GET_CODE (x) == CONST_INT); |
5128 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x)); | |
5129 | return; | |
5e3c5739 | 5130 | case 'Q': |
ecf2283d | 5131 | gcc_assert (GET_CODE (x) == CONST_INT); |
5132 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63)); | |
5133 | return; | |
e5965947 | 5134 | case 'L': |
ecf2283d | 5135 | gcc_assert (GET_CODE (x) == CONST_INT); |
5136 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31)); | |
5137 | return; | |
3a16146d | 5138 | case 'O': |
ecf2283d | 5139 | gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0); |
5140 | fprintf (file, "%d", exact_log2 (INTVAL (x))); | |
5141 | return; | |
5e3c5739 | 5142 | case 'p': |
ecf2283d | 5143 | gcc_assert (GET_CODE (x) == CONST_INT); |
5144 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63)); | |
5145 | return; | |
e5965947 | 5146 | case 'P': |
ecf2283d | 5147 | gcc_assert (GET_CODE (x) == CONST_INT); |
5148 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31)); | |
5149 | return; | |
c8975385 | 5150 | case 'I': |
5151 | if (GET_CODE (x) == CONST_INT) | |
5152 | fputs ("i", file); | |
5153 | return; | |
87ad11b0 | 5154 | case 'M': |
27ef382d | 5155 | case 'F': |
87ad11b0 | 5156 | switch (GET_CODE (XEXP (x, 0))) |
5157 | { | |
5158 | case PRE_DEC: | |
5159 | case PRE_INC: | |
e4065f95 | 5160 | if (ASSEMBLER_DIALECT == 0) |
5161 | fputs ("s,mb", file); | |
5162 | else | |
5163 | fputs (",mb", file); | |
87ad11b0 | 5164 | break; |
5165 | case POST_DEC: | |
5166 | case POST_INC: | |
e4065f95 | 5167 | if (ASSEMBLER_DIALECT == 0) |
5168 | fputs ("s,ma", file); | |
5169 | else | |
5170 | fputs (",ma", file); | |
87ad11b0 | 5171 | break; |
27ef382d | 5172 | case PLUS: |
dbd3d89d | 5173 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5174 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5175 | { | |
5176 | if (ASSEMBLER_DIALECT == 0) | |
5177 | fputs ("x", file); | |
5178 | } | |
5179 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
5180 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) | |
e4065f95 | 5181 | { |
5182 | if (ASSEMBLER_DIALECT == 0) | |
5183 | fputs ("x,s", file); | |
5184 | else | |
5185 | fputs (",s", file); | |
5186 | } | |
5187 | else if (code == 'F' && ASSEMBLER_DIALECT == 0) | |
27ef382d | 5188 | fputs ("s", file); |
87ad11b0 | 5189 | break; |
5190 | default: | |
e4065f95 | 5191 | if (code == 'F' && ASSEMBLER_DIALECT == 0) |
27ef382d | 5192 | fputs ("s", file); |
87ad11b0 | 5193 | break; |
5194 | } | |
5195 | return; | |
5196 | case 'G': | |
f9333726 | 5197 | output_global_address (file, x, 0); |
5198 | return; | |
5199 | case 'H': | |
5200 | output_global_address (file, x, 1); | |
87ad11b0 | 5201 | return; |
5202 | case 0: /* Don't do anything special */ | |
5203 | break; | |
42faba01 | 5204 | case 'Z': |
5205 | { | |
5206 | unsigned op[3]; | |
fb22aedc | 5207 | compute_zdepwi_operands (INTVAL (x), op); |
42faba01 | 5208 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); |
5209 | return; | |
5210 | } | |
5e3c5739 | 5211 | case 'z': |
5212 | { | |
5213 | unsigned op[3]; | |
5214 | compute_zdepdi_operands (INTVAL (x), op); | |
5215 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); | |
5216 | return; | |
5217 | } | |
c9cc98e1 | 5218 | case 'c': |
5219 | /* We can get here from a .vtable_inherit due to our | |
5220 | CONSTANT_ADDRESS_P rejecting perfectly good constant | |
5221 | addresses. */ | |
5222 | break; | |
87ad11b0 | 5223 | default: |
ecf2283d | 5224 | gcc_unreachable (); |
87ad11b0 | 5225 | } |
5226 | if (GET_CODE (x) == REG) | |
df0651dc | 5227 | { |
35661368 | 5228 | fputs (reg_names [REGNO (x)], file); |
5e3c5739 | 5229 | if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4) |
5230 | { | |
5231 | fputs ("R", file); | |
5232 | return; | |
5233 | } | |
5234 | if (FP_REG_P (x) | |
5235 | && GET_MODE_SIZE (GET_MODE (x)) <= 4 | |
5236 | && (REGNO (x) & 1) == 0) | |
35661368 | 5237 | fputs ("L", file); |
df0651dc | 5238 | } |
87ad11b0 | 5239 | else if (GET_CODE (x) == MEM) |
5240 | { | |
5241 | int size = GET_MODE_SIZE (GET_MODE (x)); | |
f7dff90d | 5242 | rtx base = NULL_RTX; |
87ad11b0 | 5243 | switch (GET_CODE (XEXP (x, 0))) |
5244 | { | |
5245 | case PRE_DEC: | |
5246 | case POST_DEC: | |
5e3c5739 | 5247 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 5248 | fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5249 | break; |
5250 | case PRE_INC: | |
5251 | case POST_INC: | |
5e3c5739 | 5252 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 5253 | fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 5254 | break; |
dbd3d89d | 5255 | case PLUS: |
5256 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT) | |
34940871 | 5257 | fprintf (file, "%s(%s)", |
27ef382d | 5258 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))], |
5259 | reg_names [REGNO (XEXP (XEXP (x, 0), 1))]); | |
dbd3d89d | 5260 | else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) |
34940871 | 5261 | fprintf (file, "%s(%s)", |
27ef382d | 5262 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))], |
5263 | reg_names [REGNO (XEXP (XEXP (x, 0), 0))]); | |
dbd3d89d | 5264 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
5265 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
5266 | { | |
5267 | /* Because the REG_POINTER flag can get lost during reload, | |
5268 | GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the | |
5269 | index and base registers in the combined move patterns. */ | |
5270 | rtx base = XEXP (XEXP (x, 0), 1); | |
5271 | rtx index = XEXP (XEXP (x, 0), 0); | |
5272 | ||
5273 | fprintf (file, "%s(%s)", | |
5274 | reg_names [REGNO (index)], reg_names [REGNO (base)]); | |
5275 | } | |
27ef382d | 5276 | else |
5277 | output_address (XEXP (x, 0)); | |
87ad11b0 | 5278 | break; |
dbd3d89d | 5279 | default: |
5280 | output_address (XEXP (x, 0)); | |
5281 | break; | |
87ad11b0 | 5282 | } |
5283 | } | |
87ad11b0 | 5284 | else |
5285 | output_addr_const (file, x); | |
5286 | } | |
5287 | ||
6dc3b0d9 | 5288 | /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */ |
87ad11b0 | 5289 | |
5290 | void | |
5c1d8983 | 5291 | output_global_address (FILE *file, rtx x, int round_constant) |
87ad11b0 | 5292 | { |
2ee034bc | 5293 | |
5294 | /* Imagine (high (const (plus ...))). */ | |
5295 | if (GET_CODE (x) == HIGH) | |
5296 | x = XEXP (x, 0); | |
5297 | ||
611a88e1 | 5298 | if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode)) |
5f43b4f6 | 5299 | output_addr_const (file, x); |
b4a7bf10 | 5300 | else if (GET_CODE (x) == SYMBOL_REF && !flag_pic) |
87ad11b0 | 5301 | { |
5f43b4f6 | 5302 | output_addr_const (file, x); |
9c0ac0fd | 5303 | fputs ("-$global$", file); |
87ad11b0 | 5304 | } |
5305 | else if (GET_CODE (x) == CONST) | |
5306 | { | |
611a88e1 | 5307 | const char *sep = ""; |
87ad11b0 | 5308 | int offset = 0; /* assembler wants -$global$ at end */ |
33ae0dba | 5309 | rtx base = NULL_RTX; |
6d36483b | 5310 | |
ecf2283d | 5311 | switch (GET_CODE (XEXP (XEXP (x, 0), 0))) |
87ad11b0 | 5312 | { |
ecf2283d | 5313 | case SYMBOL_REF: |
87ad11b0 | 5314 | base = XEXP (XEXP (x, 0), 0); |
5315 | output_addr_const (file, base); | |
ecf2283d | 5316 | break; |
5317 | case CONST_INT: | |
5318 | offset = INTVAL (XEXP (XEXP (x, 0), 0)); | |
5319 | break; | |
5320 | default: | |
5321 | gcc_unreachable (); | |
87ad11b0 | 5322 | } |
87ad11b0 | 5323 | |
ecf2283d | 5324 | switch (GET_CODE (XEXP (XEXP (x, 0), 1))) |
87ad11b0 | 5325 | { |
ecf2283d | 5326 | case SYMBOL_REF: |
87ad11b0 | 5327 | base = XEXP (XEXP (x, 0), 1); |
5328 | output_addr_const (file, base); | |
ecf2283d | 5329 | break; |
5330 | case CONST_INT: | |
5331 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
5332 | break; | |
5333 | default: | |
5334 | gcc_unreachable (); | |
87ad11b0 | 5335 | } |
87ad11b0 | 5336 | |
f9333726 | 5337 | /* How bogus. The compiler is apparently responsible for |
5338 | rounding the constant if it uses an LR field selector. | |
5339 | ||
5340 | The linker and/or assembler seem a better place since | |
5341 | they have to do this kind of thing already. | |
5342 | ||
5343 | If we fail to do this, HP's optimizing linker may eliminate | |
5344 | an addil, but not update the ldw/stw/ldo instruction that | |
5345 | uses the result of the addil. */ | |
5346 | if (round_constant) | |
5347 | offset = ((offset + 0x1000) & ~0x1fff); | |
5348 | ||
ecf2283d | 5349 | switch (GET_CODE (XEXP (x, 0))) |
87ad11b0 | 5350 | { |
ecf2283d | 5351 | case PLUS: |
87ad11b0 | 5352 | if (offset < 0) |
5353 | { | |
5354 | offset = -offset; | |
5355 | sep = "-"; | |
5356 | } | |
5357 | else | |
5358 | sep = "+"; | |
ecf2283d | 5359 | break; |
5360 | ||
5361 | case MINUS: | |
5362 | gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF); | |
5363 | sep = "-"; | |
5364 | break; | |
87ad11b0 | 5365 | |
ecf2283d | 5366 | default: |
5367 | gcc_unreachable (); | |
5368 | } | |
5369 | ||
611a88e1 | 5370 | if (!read_only_operand (base, VOIDmode) && !flag_pic) |
9c0ac0fd | 5371 | fputs ("-$global$", file); |
f9333726 | 5372 | if (offset) |
ea52c577 | 5373 | fprintf (file, "%s%d", sep, offset); |
87ad11b0 | 5374 | } |
5375 | else | |
5376 | output_addr_const (file, x); | |
5377 | } | |
5378 | ||
92c473b8 | 5379 | /* Output boilerplate text to appear at the beginning of the file. |
5380 | There are several possible versions. */ | |
5381 | #define aputs(x) fputs(x, asm_out_file) | |
5382 | static inline void | |
5c1d8983 | 5383 | pa_file_start_level (void) |
92c473b8 | 5384 | { |
5385 | if (TARGET_64BIT) | |
5386 | aputs ("\t.LEVEL 2.0w\n"); | |
5387 | else if (TARGET_PA_20) | |
5388 | aputs ("\t.LEVEL 2.0\n"); | |
5389 | else if (TARGET_PA_11) | |
5390 | aputs ("\t.LEVEL 1.1\n"); | |
5391 | else | |
5392 | aputs ("\t.LEVEL 1.0\n"); | |
5393 | } | |
5394 | ||
5395 | static inline void | |
5c1d8983 | 5396 | pa_file_start_space (int sortspace) |
92c473b8 | 5397 | { |
5398 | aputs ("\t.SPACE $PRIVATE$"); | |
5399 | if (sortspace) | |
5400 | aputs (",SORT=16"); | |
5401 | aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31" | |
5402 | "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82" | |
5403 | "\n\t.SPACE $TEXT$"); | |
5404 | if (sortspace) | |
5405 | aputs (",SORT=8"); | |
5406 | aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44" | |
5407 | "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n"); | |
5408 | } | |
5409 | ||
5410 | static inline void | |
5c1d8983 | 5411 | pa_file_start_file (int want_version) |
92c473b8 | 5412 | { |
5413 | if (write_symbols != NO_DEBUG) | |
5414 | { | |
5415 | output_file_directive (asm_out_file, main_input_filename); | |
5416 | if (want_version) | |
5417 | aputs ("\t.version\t\"01.01\"\n"); | |
5418 | } | |
5419 | } | |
5420 | ||
5421 | static inline void | |
5c1d8983 | 5422 | pa_file_start_mcount (const char *aswhat) |
92c473b8 | 5423 | { |
5424 | if (profile_flag) | |
5425 | fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat); | |
5426 | } | |
5427 | ||
5428 | static void | |
5c1d8983 | 5429 | pa_elf_file_start (void) |
92c473b8 | 5430 | { |
5431 | pa_file_start_level (); | |
5432 | pa_file_start_mcount ("ENTRY"); | |
5433 | pa_file_start_file (0); | |
5434 | } | |
5435 | ||
5436 | static void | |
5c1d8983 | 5437 | pa_som_file_start (void) |
92c473b8 | 5438 | { |
5439 | pa_file_start_level (); | |
5440 | pa_file_start_space (0); | |
5441 | aputs ("\t.IMPORT $global$,DATA\n" | |
5442 | "\t.IMPORT $$dyncall,MILLICODE\n"); | |
5443 | pa_file_start_mcount ("CODE"); | |
5444 | pa_file_start_file (0); | |
5445 | } | |
5446 | ||
5447 | static void | |
5c1d8983 | 5448 | pa_linux_file_start (void) |
92c473b8 | 5449 | { |
5450 | pa_file_start_file (1); | |
5451 | pa_file_start_level (); | |
5452 | pa_file_start_mcount ("CODE"); | |
5453 | } | |
5454 | ||
5455 | static void | |
5c1d8983 | 5456 | pa_hpux64_gas_file_start (void) |
92c473b8 | 5457 | { |
5458 | pa_file_start_level (); | |
5459 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
5460 | if (profile_flag) | |
5461 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function"); | |
5462 | #endif | |
5463 | pa_file_start_file (1); | |
5464 | } | |
5465 | ||
5466 | static void | |
5c1d8983 | 5467 | pa_hpux64_hpas_file_start (void) |
92c473b8 | 5468 | { |
5469 | pa_file_start_level (); | |
5470 | pa_file_start_space (1); | |
5471 | pa_file_start_mcount ("CODE"); | |
5472 | pa_file_start_file (0); | |
5473 | } | |
5474 | #undef aputs | |
5475 | ||
4e75439e | 5476 | /* Search the deferred plabel list for SYMBOL and return its internal |
5477 | label. If an entry for SYMBOL is not found, a new entry is created. */ | |
5478 | ||
5479 | rtx | |
5480 | get_deferred_plabel (rtx symbol) | |
ece88821 | 5481 | { |
5f43b4f6 | 5482 | const char *fname = XSTR (symbol, 0); |
ece88821 | 5483 | size_t i; |
5484 | ||
5485 | /* See if we have already put this function on the list of deferred | |
5486 | plabels. This list is generally small, so a liner search is not | |
5487 | too ugly. If it proves too slow replace it with something faster. */ | |
5488 | for (i = 0; i < n_deferred_plabels; i++) | |
5f43b4f6 | 5489 | if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0) |
ece88821 | 5490 | break; |
5491 | ||
5492 | /* If the deferred plabel list is empty, or this entry was not found | |
5493 | on the list, create a new entry on the list. */ | |
5494 | if (deferred_plabels == NULL || i == n_deferred_plabels) | |
5495 | { | |
5f43b4f6 | 5496 | tree id; |
5497 | ||
ece88821 | 5498 | if (deferred_plabels == 0) |
ba72912a | 5499 | deferred_plabels = ggc_alloc_deferred_plabel (); |
ece88821 | 5500 | else |
ba72912a | 5501 | deferred_plabels = GGC_RESIZEVEC (struct deferred_plabel, |
5502 | deferred_plabels, | |
5503 | n_deferred_plabels + 1); | |
ece88821 | 5504 | |
5505 | i = n_deferred_plabels++; | |
5506 | deferred_plabels[i].internal_label = gen_label_rtx (); | |
5f43b4f6 | 5507 | deferred_plabels[i].symbol = symbol; |
ece88821 | 5508 | |
5f43b4f6 | 5509 | /* Gross. We have just implicitly taken the address of this |
5510 | function. Mark it in the same manner as assemble_name. */ | |
5511 | id = maybe_get_identifier (targetm.strip_name_encoding (fname)); | |
5512 | if (id) | |
5513 | mark_referenced (id); | |
ece88821 | 5514 | } |
5515 | ||
4e75439e | 5516 | return deferred_plabels[i].internal_label; |
ece88821 | 5517 | } |
5518 | ||
f6940372 | 5519 | static void |
5c1d8983 | 5520 | output_deferred_plabels (void) |
5cc6b2bc | 5521 | { |
e11bd7e5 | 5522 | size_t i; |
78962d38 | 5523 | |
5524 | /* If we have some deferred plabels, then we need to switch into the | |
5525 | data or readonly data section, and align it to a 4 byte boundary | |
191ec5a2 | 5526 | before outputting the deferred plabels. */ |
5cc6b2bc | 5527 | if (n_deferred_plabels) |
5528 | { | |
78962d38 | 5529 | switch_to_section (flag_pic ? data_section : readonly_data_section); |
f6940372 | 5530 | ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2); |
5cc6b2bc | 5531 | } |
5532 | ||
5533 | /* Now output the deferred plabels. */ | |
5534 | for (i = 0; i < n_deferred_plabels; i++) | |
5535 | { | |
c5559ed4 | 5536 | targetm.asm_out.internal_label (asm_out_file, "L", |
f6940372 | 5537 | CODE_LABEL_NUMBER (deferred_plabels[i].internal_label)); |
5f43b4f6 | 5538 | assemble_integer (deferred_plabels[i].symbol, |
b70ea764 | 5539 | TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1); |
5cc6b2bc | 5540 | } |
5541 | } | |
5542 | ||
0f9c87cc | 5543 | #if HPUX_LONG_DOUBLE_LIBRARY |
f2f543a3 | 5544 | /* Initialize optabs to point to HPUX long double emulation routines. */ |
5545 | static void | |
5546 | pa_hpux_init_libfuncs (void) | |
5547 | { | |
5548 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
5549 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
5550 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
5551 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
5552 | set_optab_libfunc (smin_optab, TFmode, "_U_Qmin"); | |
5553 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
5554 | set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt"); | |
5555 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
5556 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
5557 | ||
c88a6ebd | 5558 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); |
5559 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
5560 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
5561 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
5562 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
5563 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
6b27baea | 5564 | set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord"); |
f2f543a3 | 5565 | |
a7cc195f | 5566 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); |
5567 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
5568 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
5569 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
5570 | ||
5571 | set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT | |
5572 | ? "__U_Qfcnvfxt_quad_to_sgl" | |
5573 | : "_U_Qfcnvfxt_quad_to_sgl"); | |
5574 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl"); | |
5575 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl"); | |
5576 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl"); | |
5577 | ||
5578 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad"); | |
5579 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad"); | |
3e647485 | 5580 | set_conv_libfunc (ufloat_optab, TFmode, SImode, "_U_Qfcnvxf_usgl_to_quad"); |
5581 | set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxf_udbl_to_quad"); | |
f2f543a3 | 5582 | } |
5583 | #endif | |
5584 | ||
87ad11b0 | 5585 | /* HP's millicode routines mean something special to the assembler. |
5586 | Keep track of which ones we have used. */ | |
5587 | ||
c2271c34 | 5588 | enum millicodes { remI, remU, divI, divU, mulI, end1000 }; |
5c1d8983 | 5589 | static void import_milli (enum millicodes); |
ea52c577 | 5590 | static char imported[(int) end1000]; |
c2271c34 | 5591 | static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"}; |
e99c3a1d | 5592 | static const char import_string[] = ".IMPORT $$....,MILLICODE"; |
87ad11b0 | 5593 | #define MILLI_START 10 |
5594 | ||
57ed30e5 | 5595 | static void |
5c1d8983 | 5596 | import_milli (enum millicodes code) |
87ad11b0 | 5597 | { |
5598 | char str[sizeof (import_string)]; | |
6d36483b | 5599 | |
ea52c577 | 5600 | if (!imported[(int) code]) |
87ad11b0 | 5601 | { |
ea52c577 | 5602 | imported[(int) code] = 1; |
87ad11b0 | 5603 | strcpy (str, import_string); |
ea52c577 | 5604 | strncpy (str + MILLI_START, milli_names[(int) code], 4); |
87ad11b0 | 5605 | output_asm_insn (str, 0); |
5606 | } | |
5607 | } | |
5608 | ||
6d36483b | 5609 | /* The register constraints have put the operands and return value in |
6dc3b0d9 | 5610 | the proper registers. */ |
87ad11b0 | 5611 | |
611a88e1 | 5612 | const char * |
5c1d8983 | 5613 | output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn) |
87ad11b0 | 5614 | { |
d178f670 | 5615 | import_milli (mulI); |
440c23df | 5616 | return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI")); |
87ad11b0 | 5617 | } |
5618 | ||
6dc3b0d9 | 5619 | /* Emit the rtl for doing a division by a constant. */ |
87ad11b0 | 5620 | |
d178f670 | 5621 | /* Do magic division millicodes exist for this value? */ |
913de4b4 | 5622 | const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1}; |
87ad11b0 | 5623 | |
6d36483b | 5624 | /* We'll use an array to keep track of the magic millicodes and |
87ad11b0 | 5625 | whether or not we've used them already. [n][0] is signed, [n][1] is |
6dc3b0d9 | 5626 | unsigned. */ |
87ad11b0 | 5627 | |
87ad11b0 | 5628 | static int div_milli[16][2]; |
5629 | ||
87ad11b0 | 5630 | int |
5c1d8983 | 5631 | emit_hpdiv_const (rtx *operands, int unsignedp) |
87ad11b0 | 5632 | { |
5633 | if (GET_CODE (operands[2]) == CONST_INT | |
5634 | && INTVAL (operands[2]) > 0 | |
5635 | && INTVAL (operands[2]) < 16 | |
5636 | && magic_milli[INTVAL (operands[2])]) | |
5637 | { | |
2013ddf6 | 5638 | rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31); |
5639 | ||
ad851752 | 5640 | emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]); |
87ad11b0 | 5641 | emit |
75b1a41a | 5642 | (gen_rtx_PARALLEL |
5643 | (VOIDmode, | |
c2078db8 | 5644 | gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29), |
ad851752 | 5645 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, |
5646 | SImode, | |
5647 | gen_rtx_REG (SImode, 26), | |
5648 | operands[2])), | |
c2078db8 | 5649 | gen_rtx_CLOBBER (VOIDmode, operands[4]), |
ad851752 | 5650 | gen_rtx_CLOBBER (VOIDmode, operands[3]), |
5651 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)), | |
5652 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)), | |
2013ddf6 | 5653 | gen_rtx_CLOBBER (VOIDmode, ret)))); |
ad851752 | 5654 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 29)); |
87ad11b0 | 5655 | return 1; |
5656 | } | |
5657 | return 0; | |
5658 | } | |
5659 | ||
611a88e1 | 5660 | const char * |
5c1d8983 | 5661 | output_div_insn (rtx *operands, int unsignedp, rtx insn) |
87ad11b0 | 5662 | { |
5663 | int divisor; | |
6d36483b | 5664 | |
5665 | /* If the divisor is a constant, try to use one of the special | |
87ad11b0 | 5666 | opcodes .*/ |
5667 | if (GET_CODE (operands[0]) == CONST_INT) | |
5668 | { | |
d6686e21 | 5669 | static char buf[100]; |
87ad11b0 | 5670 | divisor = INTVAL (operands[0]); |
5671 | if (!div_milli[divisor][unsignedp]) | |
5672 | { | |
d6686e21 | 5673 | div_milli[divisor][unsignedp] = 1; |
87ad11b0 | 5674 | if (unsignedp) |
5675 | output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands); | |
5676 | else | |
5677 | output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands); | |
87ad11b0 | 5678 | } |
5679 | if (unsignedp) | |
d6686e21 | 5680 | { |
4840a03a | 5681 | sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC, |
5682 | INTVAL (operands[0])); | |
c7a4e712 | 5683 | return output_millicode_call (insn, |
ad851752 | 5684 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5685 | } |
5686 | else | |
5687 | { | |
4840a03a | 5688 | sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC, |
5689 | INTVAL (operands[0])); | |
c7a4e712 | 5690 | return output_millicode_call (insn, |
ad851752 | 5691 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5692 | } |
87ad11b0 | 5693 | } |
6dc3b0d9 | 5694 | /* Divisor isn't a special constant. */ |
87ad11b0 | 5695 | else |
5696 | { | |
5697 | if (unsignedp) | |
5698 | { | |
5699 | import_milli (divU); | |
c7a4e712 | 5700 | return output_millicode_call (insn, |
ad851752 | 5701 | gen_rtx_SYMBOL_REF (SImode, "$$divU")); |
87ad11b0 | 5702 | } |
5703 | else | |
5704 | { | |
5705 | import_milli (divI); | |
c7a4e712 | 5706 | return output_millicode_call (insn, |
ad851752 | 5707 | gen_rtx_SYMBOL_REF (SImode, "$$divI")); |
87ad11b0 | 5708 | } |
5709 | } | |
5710 | } | |
5711 | ||
6dc3b0d9 | 5712 | /* Output a $$rem millicode to do mod. */ |
87ad11b0 | 5713 | |
611a88e1 | 5714 | const char * |
5c1d8983 | 5715 | output_mod_insn (int unsignedp, rtx insn) |
87ad11b0 | 5716 | { |
5717 | if (unsignedp) | |
5718 | { | |
5719 | import_milli (remU); | |
c7a4e712 | 5720 | return output_millicode_call (insn, |
ad851752 | 5721 | gen_rtx_SYMBOL_REF (SImode, "$$remU")); |
87ad11b0 | 5722 | } |
5723 | else | |
5724 | { | |
5725 | import_milli (remI); | |
c7a4e712 | 5726 | return output_millicode_call (insn, |
ad851752 | 5727 | gen_rtx_SYMBOL_REF (SImode, "$$remI")); |
87ad11b0 | 5728 | } |
5729 | } | |
5730 | ||
5731 | void | |
5c1d8983 | 5732 | output_arg_descriptor (rtx call_insn) |
87ad11b0 | 5733 | { |
611a88e1 | 5734 | const char *arg_regs[4]; |
87ad11b0 | 5735 | enum machine_mode arg_mode; |
df0651dc | 5736 | rtx link; |
87ad11b0 | 5737 | int i, output_flag = 0; |
5738 | int regno; | |
6d36483b | 5739 | |
5e3c5739 | 5740 | /* We neither need nor want argument location descriptors for the |
5d0619cc | 5741 | 64bit runtime environment or the ELF32 environment. */ |
5742 | if (TARGET_64BIT || TARGET_ELF32) | |
5e3c5739 | 5743 | return; |
5744 | ||
87ad11b0 | 5745 | for (i = 0; i < 4; i++) |
5746 | arg_regs[i] = 0; | |
5747 | ||
738176ab | 5748 | /* Specify explicitly that no argument relocations should take place |
5749 | if using the portable runtime calling conventions. */ | |
5750 | if (TARGET_PORTABLE_RUNTIME) | |
5751 | { | |
9c0ac0fd | 5752 | fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n", |
5753 | asm_out_file); | |
738176ab | 5754 | return; |
5755 | } | |
5756 | ||
ecf2283d | 5757 | gcc_assert (GET_CODE (call_insn) == CALL_INSN); |
5758 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); | |
5759 | link; link = XEXP (link, 1)) | |
87ad11b0 | 5760 | { |
df0651dc | 5761 | rtx use = XEXP (link, 0); |
c12afafd | 5762 | |
df0651dc | 5763 | if (! (GET_CODE (use) == USE |
5764 | && GET_CODE (XEXP (use, 0)) == REG | |
5765 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
c12afafd | 5766 | continue; |
5767 | ||
df0651dc | 5768 | arg_mode = GET_MODE (XEXP (use, 0)); |
5769 | regno = REGNO (XEXP (use, 0)); | |
87ad11b0 | 5770 | if (regno >= 23 && regno <= 26) |
372ef038 | 5771 | { |
5772 | arg_regs[26 - regno] = "GR"; | |
5773 | if (arg_mode == DImode) | |
5774 | arg_regs[25 - regno] = "GR"; | |
5775 | } | |
df0651dc | 5776 | else if (regno >= 32 && regno <= 39) |
87ad11b0 | 5777 | { |
5778 | if (arg_mode == SFmode) | |
df0651dc | 5779 | arg_regs[(regno - 32) / 2] = "FR"; |
e6ba640e | 5780 | else |
87ad11b0 | 5781 | { |
eeec72c0 | 5782 | #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED |
df0651dc | 5783 | arg_regs[(regno - 34) / 2] = "FR"; |
5784 | arg_regs[(regno - 34) / 2 + 1] = "FU"; | |
87ad11b0 | 5785 | #else |
df0651dc | 5786 | arg_regs[(regno - 34) / 2] = "FU"; |
5787 | arg_regs[(regno - 34) / 2 + 1] = "FR"; | |
87ad11b0 | 5788 | #endif |
5789 | } | |
87ad11b0 | 5790 | } |
5791 | } | |
5792 | fputs ("\t.CALL ", asm_out_file); | |
5793 | for (i = 0; i < 4; i++) | |
5794 | { | |
5795 | if (arg_regs[i]) | |
5796 | { | |
5797 | if (output_flag++) | |
5798 | fputc (',', asm_out_file); | |
5799 | fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]); | |
5800 | } | |
5801 | } | |
5802 | fputc ('\n', asm_out_file); | |
5803 | } | |
5804 | \f | |
5ddb2975 | 5805 | /* Inform reload about cases where moving X with a mode MODE to a register in |
5806 | RCLASS requires an extra scratch or immediate register. Return the class | |
5807 | needed for the immediate register. */ | |
5808 | ||
964229b7 | 5809 | static reg_class_t |
5810 | pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, | |
5655a0e5 | 5811 | enum machine_mode mode, secondary_reload_info *sri) |
5812 | { | |
c9b20949 | 5813 | int regno; |
964229b7 | 5814 | enum reg_class rclass = (enum reg_class) rclass_i; |
9c0ac0fd | 5815 | |
5655a0e5 | 5816 | /* Handle the easy stuff first. */ |
8deb3959 | 5817 | if (rclass == R1_REGS) |
5655a0e5 | 5818 | return NO_REGS; |
9c0ac0fd | 5819 | |
5655a0e5 | 5820 | if (REG_P (x)) |
5821 | { | |
5822 | regno = REGNO (x); | |
8deb3959 | 5823 | if (rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER) |
5655a0e5 | 5824 | return NO_REGS; |
5825 | } | |
cca0fae1 | 5826 | else |
5827 | regno = -1; | |
87ad11b0 | 5828 | |
5655a0e5 | 5829 | /* If we have something like (mem (mem (...)), we can safely assume the |
5830 | inner MEM will end up in a general register after reloading, so there's | |
5831 | no need for a secondary reload. */ | |
5832 | if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM) | |
5833 | return NO_REGS; | |
87ad11b0 | 5834 | |
b4a7bf10 | 5835 | /* Trying to load a constant into a FP register during PIC code |
5655a0e5 | 5836 | generation requires %r1 as a scratch register. */ |
fc44315f | 5837 | if (flag_pic |
9c0b6987 | 5838 | && (mode == SImode || mode == DImode) |
8deb3959 | 5839 | && FP_REG_CLASS_P (rclass) |
5655a0e5 | 5840 | && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) |
9c0ac0fd | 5841 | { |
5655a0e5 | 5842 | sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1 |
5843 | : CODE_FOR_reload_indi_r1); | |
5844 | return NO_REGS; | |
9c0ac0fd | 5845 | } |
9c0ac0fd | 5846 | |
c9b20949 | 5847 | /* Secondary reloads of symbolic operands require %r1 as a scratch |
5848 | register when we're generating PIC code and when the operand isn't | |
5849 | readonly. */ | |
5850 | if (symbolic_expression_p (x)) | |
5851 | { | |
5852 | if (GET_CODE (x) == HIGH) | |
5853 | x = XEXP (x, 0); | |
5854 | ||
5855 | if (flag_pic || !read_only_operand (x, VOIDmode)) | |
5856 | { | |
5857 | gcc_assert (mode == SImode || mode == DImode); | |
5858 | sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1 | |
5859 | : CODE_FOR_reload_indi_r1); | |
5860 | return NO_REGS; | |
5861 | } | |
5862 | } | |
5863 | ||
5655a0e5 | 5864 | /* Profiling showed the PA port spends about 1.3% of its compilation |
5865 | time in true_regnum from calls inside pa_secondary_reload_class. */ | |
5866 | if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG) | |
5867 | regno = true_regnum (x); | |
76a0ced5 | 5868 | |
7050ff73 | 5869 | /* In order to allow 14-bit displacements in integer loads and stores, |
5870 | we need to prevent reload from generating out of range integer mode | |
5871 | loads and stores to the floating point registers. Previously, we | |
5872 | used to call for a secondary reload and have emit_move_sequence() | |
5873 | fix the instruction sequence. However, reload occasionally wouldn't | |
5874 | generate the reload and we would end up with an invalid REG+D memory | |
5875 | address. So, now we use an intermediate general register for most | |
5876 | memory loads and stores. */ | |
5877 | if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1) | |
5878 | && GET_MODE_CLASS (mode) == MODE_INT | |
8deb3959 | 5879 | && FP_REG_CLASS_P (rclass)) |
7050ff73 | 5880 | { |
5881 | /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check | |
5882 | the secondary reload needed for a pseudo. It never passes a | |
5883 | REG+D address. */ | |
5884 | if (GET_CODE (x) == MEM) | |
5885 | { | |
5886 | x = XEXP (x, 0); | |
5887 | ||
5888 | /* We don't need an intermediate for indexed and LO_SUM DLT | |
5889 | memory addresses. When INT14_OK_STRICT is true, it might | |
5890 | appear that we could directly allow register indirect | |
5891 | memory addresses. However, this doesn't work because we | |
5892 | don't support SUBREGs in floating-point register copies | |
5893 | and reload doesn't tell us when it's going to use a SUBREG. */ | |
5894 | if (IS_INDEX_ADDR_P (x) | |
5895 | || IS_LO_SUM_DLT_ADDR_P (x)) | |
5896 | return NO_REGS; | |
5897 | ||
5898 | /* Otherwise, we need an intermediate general register. */ | |
5899 | return GENERAL_REGS; | |
5900 | } | |
5901 | ||
5902 | /* Request a secondary reload with a general scratch register | |
5903 | for everthing else. ??? Could symbolic operands be handled | |
5904 | directly when generating non-pic PA 2.0 code? */ | |
6b531606 | 5905 | sri->icode = (in_p |
5906 | ? direct_optab_handler (reload_in_optab, mode) | |
5907 | : direct_optab_handler (reload_out_optab, mode)); | |
7050ff73 | 5908 | return NO_REGS; |
5909 | } | |
5910 | ||
5ddb2975 | 5911 | /* A SAR<->FP register copy requires an intermediate general register |
5912 | and secondary memory. We need a secondary reload with a general | |
5913 | scratch register for spills. */ | |
5914 | if (rclass == SHIFT_REGS) | |
5655a0e5 | 5915 | { |
5ddb2975 | 5916 | /* Handle spill. */ |
5917 | if (regno >= FIRST_PSEUDO_REGISTER || regno < 0) | |
5918 | { | |
5919 | sri->icode = (in_p | |
5920 | ? direct_optab_handler (reload_in_optab, mode) | |
5921 | : direct_optab_handler (reload_out_optab, mode)); | |
5922 | return NO_REGS; | |
5923 | } | |
5924 | ||
5925 | /* Handle FP copy. */ | |
5926 | if (FP_REG_CLASS_P (REGNO_REG_CLASS (regno))) | |
5927 | return GENERAL_REGS; | |
5655a0e5 | 5928 | } |
d2c1d63d | 5929 | |
7c4b32f3 | 5930 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER |
5ddb2975 | 5931 | && REGNO_REG_CLASS (regno) == SHIFT_REGS |
5932 | && FP_REG_CLASS_P (rclass)) | |
5933 | return GENERAL_REGS; | |
2ee034bc | 5934 | |
d2c1d63d | 5935 | return NO_REGS; |
87ad11b0 | 5936 | } |
5937 | ||
df6b92e4 | 5938 | /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer |
5939 | is only marked as live on entry by df-scan when it is a fixed | |
5940 | register. It isn't a fixed register in the 64-bit runtime, | |
5941 | so we need to mark it here. */ | |
5942 | ||
5943 | static void | |
5944 | pa_extra_live_on_entry (bitmap regs) | |
5945 | { | |
5946 | if (TARGET_64BIT) | |
5947 | bitmap_set_bit (regs, ARG_POINTER_REGNUM); | |
5948 | } | |
5949 | ||
5950 | /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile | |
5951 | to prevent it from being deleted. */ | |
5952 | ||
5953 | rtx | |
5954 | pa_eh_return_handler_rtx (void) | |
5955 | { | |
5956 | rtx tmp; | |
5957 | ||
68bc9ae6 | 5958 | tmp = gen_rtx_PLUS (word_mode, hard_frame_pointer_rtx, |
df6b92e4 | 5959 | TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)); |
5960 | tmp = gen_rtx_MEM (word_mode, tmp); | |
5961 | tmp->volatil = 1; | |
5962 | return tmp; | |
5963 | } | |
5964 | ||
b981d932 | 5965 | /* In the 32-bit runtime, arguments larger than eight bytes are passed |
5966 | by invisible reference. As a GCC extension, we also pass anything | |
5967 | with a zero or variable size by reference. | |
5968 | ||
5969 | The 64-bit runtime does not describe passing any types by invisible | |
5970 | reference. The internals of GCC can't currently handle passing | |
5971 | empty structures, and zero or variable length arrays when they are | |
5972 | not passed entirely on the stack or by reference. Thus, as a GCC | |
5973 | extension, we pass these types by reference. The HP compiler doesn't | |
5974 | support these types, so hopefully there shouldn't be any compatibility | |
5975 | issues. This may have to be revisited when HP releases a C99 compiler | |
5976 | or updates the ABI. */ | |
5977 | ||
5978 | static bool | |
39cba157 | 5979 | pa_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED, |
fb80456a | 5980 | enum machine_mode mode, const_tree type, |
b981d932 | 5981 | bool named ATTRIBUTE_UNUSED) |
5982 | { | |
5983 | HOST_WIDE_INT size; | |
5984 | ||
5985 | if (type) | |
5986 | size = int_size_in_bytes (type); | |
5987 | else | |
5988 | size = GET_MODE_SIZE (mode); | |
5989 | ||
5990 | if (TARGET_64BIT) | |
5991 | return size <= 0; | |
5992 | else | |
5993 | return size <= 0 || size > 8; | |
5994 | } | |
5995 | ||
87ad11b0 | 5996 | enum direction |
fb80456a | 5997 | function_arg_padding (enum machine_mode mode, const_tree type) |
87ad11b0 | 5998 | { |
ac965869 | 5999 | if (mode == BLKmode |
ef669d1a | 6000 | || (TARGET_64BIT |
6001 | && type | |
6002 | && (AGGREGATE_TYPE_P (type) | |
6003 | || TREE_CODE (type) == COMPLEX_TYPE | |
6004 | || TREE_CODE (type) == VECTOR_TYPE))) | |
ac965869 | 6005 | { |
6006 | /* Return none if justification is not required. */ | |
6007 | if (type | |
6008 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
6009 | && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0) | |
6010 | return none; | |
6011 | ||
6012 | /* The directions set here are ignored when a BLKmode argument larger | |
6013 | than a word is placed in a register. Different code is used for | |
6014 | the stack and registers. This makes it difficult to have a | |
6015 | consistent data representation for both the stack and registers. | |
6016 | For both runtimes, the justification and padding for arguments on | |
6017 | the stack and in registers should be identical. */ | |
6018 | if (TARGET_64BIT) | |
6019 | /* The 64-bit runtime specifies left justification for aggregates. */ | |
6020 | return upward; | |
87ad11b0 | 6021 | else |
ac965869 | 6022 | /* The 32-bit runtime architecture specifies right justification. |
6023 | When the argument is passed on the stack, the argument is padded | |
6024 | with garbage on the left. The HP compiler pads with zeros. */ | |
6025 | return downward; | |
87ad11b0 | 6026 | } |
ac965869 | 6027 | |
6028 | if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
87ad11b0 | 6029 | return downward; |
87ad11b0 | 6030 | else |
6031 | return none; | |
6032 | } | |
6033 | ||
87ad11b0 | 6034 | \f |
55f54832 | 6035 | /* Do what is necessary for `va_start'. We look at the current function |
6036 | to determine if stdargs or varargs is used and fill in an initial | |
6037 | va_list. A pointer to this constructor is returned. */ | |
87ad11b0 | 6038 | |
b8debbe8 | 6039 | static rtx |
5c1d8983 | 6040 | hppa_builtin_saveregs (void) |
87ad11b0 | 6041 | { |
01251cbc | 6042 | rtx offset, dest; |
87ad11b0 | 6043 | tree fntype = TREE_TYPE (current_function_decl); |
257d99c3 | 6044 | int argadj = ((!stdarg_p (fntype)) |
87ad11b0 | 6045 | ? UNITS_PER_WORD : 0); |
6046 | ||
6047 | if (argadj) | |
abe32cce | 6048 | offset = plus_constant (crtl->args.arg_offset_rtx, argadj); |
87ad11b0 | 6049 | else |
abe32cce | 6050 | offset = crtl->args.arg_offset_rtx; |
9c6d4825 | 6051 | |
5e3c5739 | 6052 | if (TARGET_64BIT) |
6053 | { | |
6054 | int i, off; | |
9840d99d | 6055 | |
5e3c5739 | 6056 | /* Adjust for varargs/stdarg differences. */ |
6057 | if (argadj) | |
abe32cce | 6058 | offset = plus_constant (crtl->args.arg_offset_rtx, -argadj); |
5e3c5739 | 6059 | else |
abe32cce | 6060 | offset = crtl->args.arg_offset_rtx; |
5e3c5739 | 6061 | |
6062 | /* We need to save %r26 .. %r19 inclusive starting at offset -64 | |
6063 | from the incoming arg pointer and growing to larger addresses. */ | |
6064 | for (i = 26, off = -64; i >= 19; i--, off += 8) | |
6065 | emit_move_insn (gen_rtx_MEM (word_mode, | |
6066 | plus_constant (arg_pointer_rtx, off)), | |
6067 | gen_rtx_REG (word_mode, i)); | |
6068 | ||
6069 | /* The incoming args pointer points just beyond the flushback area; | |
8ef587dc | 6070 | normally this is not a serious concern. However, when we are doing |
5e3c5739 | 6071 | varargs/stdargs we want to make the arg pointer point to the start |
6072 | of the incoming argument area. */ | |
6073 | emit_move_insn (virtual_incoming_args_rtx, | |
6074 | plus_constant (arg_pointer_rtx, -64)); | |
6075 | ||
6076 | /* Now return a pointer to the first anonymous argument. */ | |
6077 | return copy_to_reg (expand_binop (Pmode, add_optab, | |
6078 | virtual_incoming_args_rtx, | |
6079 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
6080 | } | |
6081 | ||
6dc3b0d9 | 6082 | /* Store general registers on the stack. */ |
ad851752 | 6083 | dest = gen_rtx_MEM (BLKmode, |
abe32cce | 6084 | plus_constant (crtl->args.internal_arg_pointer, |
ad851752 | 6085 | -16)); |
ab6ab77e | 6086 | set_mem_alias_set (dest, get_varargs_alias_set ()); |
2a631e19 | 6087 | set_mem_align (dest, BITS_PER_WORD); |
530178a9 | 6088 | move_block_from_reg (23, dest, 4); |
01251cbc | 6089 | |
76a0ced5 | 6090 | /* move_block_from_reg will emit code to store the argument registers |
6091 | individually as scalar stores. | |
6092 | ||
6093 | However, other insns may later load from the same addresses for | |
ad87de1e | 6094 | a structure load (passing a struct to a varargs routine). |
76a0ced5 | 6095 | |
6096 | The alias code assumes that such aliasing can never happen, so we | |
6097 | have to keep memory referencing insns from moving up beyond the | |
6098 | last argument register store. So we emit a blockage insn here. */ | |
6099 | emit_insn (gen_blockage ()); | |
6100 | ||
9c6d4825 | 6101 | return copy_to_reg (expand_binop (Pmode, add_optab, |
abe32cce | 6102 | crtl->args.internal_arg_pointer, |
9c6d4825 | 6103 | offset, 0, 0, OPTAB_LIB_WIDEN)); |
87ad11b0 | 6104 | } |
d6f01525 | 6105 | |
8a58ed0a | 6106 | static void |
5c1d8983 | 6107 | hppa_va_start (tree valist, rtx nextarg) |
72899a61 | 6108 | { |
6109 | nextarg = expand_builtin_saveregs (); | |
7df226a2 | 6110 | std_expand_builtin_va_start (valist, nextarg); |
72899a61 | 6111 | } |
6112 | ||
4c33eb68 | 6113 | static tree |
75a70cf9 | 6114 | hppa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
6115 | gimple_seq *post_p) | |
72899a61 | 6116 | { |
5e3c5739 | 6117 | if (TARGET_64BIT) |
6118 | { | |
4c33eb68 | 6119 | /* Args grow upward. We can use the generic routines. */ |
bef380a4 | 6120 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
72899a61 | 6121 | } |
ac965869 | 6122 | else /* !TARGET_64BIT */ |
72899a61 | 6123 | { |
4c33eb68 | 6124 | tree ptr = build_pointer_type (type); |
6125 | tree valist_type; | |
6126 | tree t, u; | |
6127 | unsigned int size, ofs; | |
bef380a4 | 6128 | bool indirect; |
72899a61 | 6129 | |
bef380a4 | 6130 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0); |
4c33eb68 | 6131 | if (indirect) |
ac965869 | 6132 | { |
4c33eb68 | 6133 | type = ptr; |
6134 | ptr = build_pointer_type (type); | |
72899a61 | 6135 | } |
4c33eb68 | 6136 | size = int_size_in_bytes (type); |
6137 | valist_type = TREE_TYPE (valist); | |
ac965869 | 6138 | |
4c33eb68 | 6139 | /* Args grow down. Not handled by generic routines. */ |
ac965869 | 6140 | |
0de36bdb | 6141 | u = fold_convert (sizetype, size_in_bytes (type)); |
6142 | u = fold_build1 (NEGATE_EXPR, sizetype, u); | |
2cc66f2a | 6143 | t = fold_build_pointer_plus (valist, u); |
ac965869 | 6144 | |
175fd0a9 | 6145 | /* Align to 4 or 8 byte boundary depending on argument size. */ |
6146 | ||
6147 | u = build_int_cst (TREE_TYPE (t), (HOST_WIDE_INT)(size > 4 ? -8 : -4)); | |
6148 | t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u); | |
0de36bdb | 6149 | t = fold_convert (valist_type, t); |
4c33eb68 | 6150 | |
33b1284b | 6151 | t = build2 (MODIFY_EXPR, valist_type, valist, t); |
72899a61 | 6152 | |
4c33eb68 | 6153 | ofs = (8 - size) % 4; |
6154 | if (ofs != 0) | |
2cc66f2a | 6155 | t = fold_build_pointer_plus_hwi (t, ofs); |
72899a61 | 6156 | |
4c33eb68 | 6157 | t = fold_convert (ptr, t); |
063f5fdd | 6158 | t = build_va_arg_indirect_ref (t); |
72899a61 | 6159 | |
4c33eb68 | 6160 | if (indirect) |
063f5fdd | 6161 | t = build_va_arg_indirect_ref (t); |
72899a61 | 6162 | |
4c33eb68 | 6163 | return t; |
6164 | } | |
6165 | } | |
72899a61 | 6166 | |
2b1e7cc3 | 6167 | /* True if MODE is valid for the target. By "valid", we mean able to |
6168 | be manipulated in non-trivial ways. In particular, this means all | |
6169 | the arithmetic is supported. | |
6170 | ||
6171 | Currently, TImode is not valid as the HP 64-bit runtime documentation | |
6172 | doesn't document the alignment and calling conventions for this type. | |
6173 | Thus, we return false when PRECISION is 2 * BITS_PER_WORD and | |
6174 | 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */ | |
6175 | ||
6176 | static bool | |
6177 | pa_scalar_mode_supported_p (enum machine_mode mode) | |
6178 | { | |
6179 | int precision = GET_MODE_PRECISION (mode); | |
6180 | ||
6181 | switch (GET_MODE_CLASS (mode)) | |
6182 | { | |
6183 | case MODE_PARTIAL_INT: | |
6184 | case MODE_INT: | |
6185 | if (precision == CHAR_TYPE_SIZE) | |
6186 | return true; | |
6187 | if (precision == SHORT_TYPE_SIZE) | |
6188 | return true; | |
6189 | if (precision == INT_TYPE_SIZE) | |
6190 | return true; | |
6191 | if (precision == LONG_TYPE_SIZE) | |
6192 | return true; | |
6193 | if (precision == LONG_LONG_TYPE_SIZE) | |
6194 | return true; | |
6195 | return false; | |
6196 | ||
6197 | case MODE_FLOAT: | |
6198 | if (precision == FLOAT_TYPE_SIZE) | |
6199 | return true; | |
6200 | if (precision == DOUBLE_TYPE_SIZE) | |
6201 | return true; | |
6202 | if (precision == LONG_DOUBLE_TYPE_SIZE) | |
6203 | return true; | |
6204 | return false; | |
6205 | ||
2af936a9 | 6206 | case MODE_DECIMAL_FLOAT: |
6207 | return false; | |
6208 | ||
2b1e7cc3 | 6209 | default: |
6210 | gcc_unreachable (); | |
6211 | } | |
6212 | } | |
6213 | ||
317754f4 | 6214 | /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and |
ebeae299 | 6215 | it branches into the delay slot. Otherwise, return FALSE. */ |
317754f4 | 6216 | |
6217 | static bool | |
6218 | branch_to_delay_slot_p (rtx insn) | |
6219 | { | |
ebeae299 | 6220 | rtx jump_insn; |
6221 | ||
317754f4 | 6222 | if (dbr_sequence_length ()) |
6223 | return FALSE; | |
6224 | ||
ebeae299 | 6225 | jump_insn = next_active_insn (JUMP_LABEL (insn)); |
6226 | while (insn) | |
6227 | { | |
6228 | insn = next_active_insn (insn); | |
6229 | if (jump_insn == insn) | |
6230 | return TRUE; | |
6231 | ||
6232 | /* We can't rely on the length of asms. So, we return FALSE when | |
6233 | the branch is followed by an asm. */ | |
6234 | if (!insn | |
6235 | || GET_CODE (PATTERN (insn)) == ASM_INPUT | |
6236 | || extract_asm_operands (PATTERN (insn)) != NULL_RTX | |
6237 | || get_attr_length (insn) > 0) | |
6238 | break; | |
6239 | } | |
6240 | ||
6241 | return FALSE; | |
317754f4 | 6242 | } |
6243 | ||
ebeae299 | 6244 | /* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot. |
317754f4 | 6245 | |
6246 | This occurs when INSN has an unfilled delay slot and is followed | |
ebeae299 | 6247 | by an asm. Disaster can occur if the asm is empty and the jump |
6248 | branches into the delay slot. So, we add a nop in the delay slot | |
6249 | when this occurs. */ | |
317754f4 | 6250 | |
6251 | static bool | |
6252 | branch_needs_nop_p (rtx insn) | |
6253 | { | |
ebeae299 | 6254 | rtx jump_insn; |
317754f4 | 6255 | |
6256 | if (dbr_sequence_length ()) | |
6257 | return FALSE; | |
6258 | ||
ebeae299 | 6259 | jump_insn = next_active_insn (JUMP_LABEL (insn)); |
6260 | while (insn) | |
6261 | { | |
6262 | insn = next_active_insn (insn); | |
6263 | if (!insn || jump_insn == insn) | |
6264 | return TRUE; | |
6265 | ||
6266 | if (!(GET_CODE (PATTERN (insn)) == ASM_INPUT | |
6267 | || extract_asm_operands (PATTERN (insn)) != NULL_RTX) | |
6268 | && get_attr_length (insn) > 0) | |
6269 | break; | |
6270 | } | |
6271 | ||
6272 | return FALSE; | |
6273 | } | |
6274 | ||
6275 | /* Return TRUE if INSN, a forward jump insn, can use nullification | |
6276 | to skip the following instruction. This avoids an extra cycle due | |
6277 | to a mis-predicted branch when we fall through. */ | |
6278 | ||
6279 | static bool | |
6280 | use_skip_p (rtx insn) | |
6281 | { | |
6282 | rtx jump_insn = next_active_insn (JUMP_LABEL (insn)); | |
6283 | ||
6284 | while (insn) | |
6285 | { | |
6286 | insn = next_active_insn (insn); | |
6287 | ||
6288 | /* We can't rely on the length of asms, so we can't skip asms. */ | |
6289 | if (!insn | |
6290 | || GET_CODE (PATTERN (insn)) == ASM_INPUT | |
6291 | || extract_asm_operands (PATTERN (insn)) != NULL_RTX) | |
6292 | break; | |
6293 | if (get_attr_length (insn) == 4 | |
6294 | && jump_insn == next_active_insn (insn)) | |
6295 | return TRUE; | |
6296 | if (get_attr_length (insn) > 0) | |
6297 | break; | |
6298 | } | |
6299 | ||
6300 | return FALSE; | |
317754f4 | 6301 | } |
6302 | ||
6d36483b | 6303 | /* This routine handles all the normal conditional branch sequences we |
6304 | might need to generate. It handles compare immediate vs compare | |
6305 | register, nullification of delay slots, varying length branches, | |
0d986529 | 6306 | negated branches, and all combinations of the above. It returns the |
6d36483b | 6307 | output appropriate to emit the branch corresponding to all given |
0d986529 | 6308 | parameters. */ |
6309 | ||
611a88e1 | 6310 | const char * |
f26036bb | 6311 | output_cbranch (rtx *operands, int negated, rtx insn) |
29a4502c | 6312 | { |
0d986529 | 6313 | static char buf[100]; |
ebeae299 | 6314 | bool useskip; |
f26036bb | 6315 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6316 | int length = get_attr_length (insn); | |
6317 | int xdelay; | |
0d986529 | 6318 | |
a361b456 | 6319 | /* A conditional branch to the following instruction (e.g. the delay slot) |
ece0fa59 | 6320 | is asking for a disaster. This can happen when not optimizing and |
6321 | when jump optimization fails. | |
29a4502c | 6322 | |
38efba6c | 6323 | While it is usually safe to emit nothing, this can fail if the |
6324 | preceding instruction is a nullified branch with an empty delay | |
6325 | slot and the same branch target as this branch. We could check | |
6326 | for this but jump optimization should eliminate nop jumps. It | |
6327 | is always safe to emit a nop. */ | |
317754f4 | 6328 | if (branch_to_delay_slot_p (insn)) |
ece0fa59 | 6329 | return "nop"; |
6d36483b | 6330 | |
22699a7e | 6331 | /* The doubleword form of the cmpib instruction doesn't have the LEU |
6332 | and GTU conditions while the cmpb instruction does. Since we accept | |
6333 | zero for cmpb, we must ensure that we use cmpb for the comparison. */ | |
6334 | if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx) | |
6335 | operands[2] = gen_rtx_REG (DImode, 0); | |
d65b8df8 | 6336 | if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx) |
6337 | operands[1] = gen_rtx_REG (DImode, 0); | |
22699a7e | 6338 | |
5fbd5940 | 6339 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6340 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6341 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6342 | nullify = 1; |
6343 | ||
6344 | /* If this is a short forward conditional branch which did not get | |
6345 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6346 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6347 | nullify = forward_branch_p (insn); |
6348 | ||
6d36483b | 6349 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6350 | comclr instruction. This avoids a single cycle penalty due to |
6351 | mis-predicted branch if we fall through (branch not taken). */ | |
ebeae299 | 6352 | useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; |
0d986529 | 6353 | |
6354 | switch (length) | |
6355 | { | |
5fbd5940 | 6356 | /* All short conditional branches except backwards with an unfilled |
6357 | delay slot. */ | |
5a1231ef | 6358 | case 4: |
0d986529 | 6359 | if (useskip) |
e4065f95 | 6360 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
0d986529 | 6361 | else |
e4065f95 | 6362 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6363 | if (GET_MODE (operands[1]) == DImode) |
6364 | strcat (buf, "*"); | |
0d986529 | 6365 | if (negated) |
6366 | strcat (buf, "%B3"); | |
6367 | else | |
6368 | strcat (buf, "%S3"); | |
6369 | if (useskip) | |
5a811d43 | 6370 | strcat (buf, " %2,%r1,%%r0"); |
0d986529 | 6371 | else if (nullify) |
317754f4 | 6372 | { |
6373 | if (branch_needs_nop_p (insn)) | |
6374 | strcat (buf, ",n %2,%r1,%0%#"); | |
6375 | else | |
6376 | strcat (buf, ",n %2,%r1,%0"); | |
6377 | } | |
6d36483b | 6378 | else |
9e49be0e | 6379 | strcat (buf, " %2,%r1,%0"); |
0d986529 | 6380 | break; |
6381 | ||
87fcb603 | 6382 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6383 | unfilled delay slot is treated just like a long backward branch |
6384 | with an unfilled delay slot. */ | |
5a1231ef | 6385 | case 8: |
5fbd5940 | 6386 | /* Handle weird backwards branch with a filled delay slot |
f26036bb | 6387 | which is nullified. */ |
5fbd5940 | 6388 | if (dbr_sequence_length () != 0 |
6389 | && ! forward_branch_p (insn) | |
6390 | && nullify) | |
6391 | { | |
e4065f95 | 6392 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6393 | if (GET_MODE (operands[1]) == DImode) |
6394 | strcat (buf, "*"); | |
5fbd5940 | 6395 | if (negated) |
6396 | strcat (buf, "%S3"); | |
6397 | else | |
6398 | strcat (buf, "%B3"); | |
5a811d43 | 6399 | strcat (buf, ",n %2,%r1,.+12\n\tb %0"); |
5fbd5940 | 6400 | } |
43f0c1f2 | 6401 | /* Handle short backwards branch with an unfilled delay slot. |
6402 | Using a comb;nop rather than comiclr;bl saves 1 cycle for both | |
6403 | taken and untaken branches. */ | |
6404 | else if (dbr_sequence_length () == 0 | |
6405 | && ! forward_branch_p (insn) | |
47fc0706 | 6406 | && INSN_ADDRESSES_SET_P () |
6407 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6408 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6409 | { |
e4065f95 | 6410 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 6411 | if (GET_MODE (operands[1]) == DImode) |
6412 | strcat (buf, "*"); | |
43f0c1f2 | 6413 | if (negated) |
9e49be0e | 6414 | strcat (buf, "%B3 %2,%r1,%0%#"); |
43f0c1f2 | 6415 | else |
9e49be0e | 6416 | strcat (buf, "%S3 %2,%r1,%0%#"); |
43f0c1f2 | 6417 | } |
0d986529 | 6418 | else |
5fbd5940 | 6419 | { |
e4065f95 | 6420 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
5e3c5739 | 6421 | if (GET_MODE (operands[1]) == DImode) |
6422 | strcat (buf, "*"); | |
5fbd5940 | 6423 | if (negated) |
6424 | strcat (buf, "%S3"); | |
6425 | else | |
6426 | strcat (buf, "%B3"); | |
6427 | if (nullify) | |
5a811d43 | 6428 | strcat (buf, " %2,%r1,%%r0\n\tb,n %0"); |
5fbd5940 | 6429 | else |
5a811d43 | 6430 | strcat (buf, " %2,%r1,%%r0\n\tb %0"); |
5fbd5940 | 6431 | } |
0d986529 | 6432 | break; |
6433 | ||
f26036bb | 6434 | default: |
e9ec370e | 6435 | /* The reversed conditional branch must branch over one additional |
f26036bb | 6436 | instruction if the delay slot is filled and needs to be extracted |
6437 | by output_lbranch. If the delay slot is empty or this is a | |
6438 | nullified forward branch, the instruction after the reversed | |
6439 | condition branch must be nullified. */ | |
6440 | if (dbr_sequence_length () == 0 | |
6441 | || (nullify && forward_branch_p (insn))) | |
6442 | { | |
6443 | nullify = 1; | |
6444 | xdelay = 0; | |
6445 | operands[4] = GEN_INT (length); | |
6446 | } | |
6447 | else | |
6448 | { | |
6449 | xdelay = 1; | |
6450 | operands[4] = GEN_INT (length + 4); | |
6451 | } | |
c8a0e52b | 6452 | |
6453 | /* Create a reversed conditional branch which branches around | |
6454 | the following insns. */ | |
e9ec370e | 6455 | if (GET_MODE (operands[1]) != DImode) |
6456 | { | |
6457 | if (nullify) | |
6458 | { | |
6459 | if (negated) | |
6460 | strcpy (buf, | |
6461 | "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}"); | |
6462 | else | |
6463 | strcpy (buf, | |
6464 | "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}"); | |
6465 | } | |
6466 | else | |
6467 | { | |
6468 | if (negated) | |
6469 | strcpy (buf, | |
6470 | "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}"); | |
6471 | else | |
6472 | strcpy (buf, | |
6473 | "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}"); | |
6474 | } | |
6475 | } | |
c8a0e52b | 6476 | else |
5e3c5739 | 6477 | { |
e9ec370e | 6478 | if (nullify) |
6479 | { | |
6480 | if (negated) | |
6481 | strcpy (buf, | |
6482 | "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}"); | |
6483 | else | |
6484 | strcpy (buf, | |
6485 | "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}"); | |
6486 | } | |
5e3c5739 | 6487 | else |
e9ec370e | 6488 | { |
6489 | if (negated) | |
6490 | strcpy (buf, | |
6491 | "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}"); | |
6492 | else | |
6493 | strcpy (buf, | |
6494 | "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}"); | |
6495 | } | |
5e3c5739 | 6496 | } |
c8a0e52b | 6497 | |
f26036bb | 6498 | output_asm_insn (buf, operands); |
6499 | return output_lbranch (operands[0], insn, xdelay); | |
e9ec370e | 6500 | } |
6501 | return buf; | |
6502 | } | |
c8a0e52b | 6503 | |
f26036bb | 6504 | /* This routine handles output of long unconditional branches that |
6505 | exceed the maximum range of a simple branch instruction. Since | |
6506 | we don't have a register available for the branch, we save register | |
6507 | %r1 in the frame marker, load the branch destination DEST into %r1, | |
6508 | execute the branch, and restore %r1 in the delay slot of the branch. | |
6509 | ||
6510 | Since long branches may have an insn in the delay slot and the | |
6511 | delay slot is used to restore %r1, we in general need to extract | |
6512 | this insn and execute it before the branch. However, to facilitate | |
6513 | use of this function by conditional branches, we also provide an | |
6514 | option to not extract the delay insn so that it will be emitted | |
6515 | after the long branch. So, if there is an insn in the delay slot, | |
6516 | it is extracted if XDELAY is nonzero. | |
6517 | ||
6518 | The lengths of the various long-branch sequences are 20, 16 and 24 | |
6519 | bytes for the portable runtime, non-PIC and PIC cases, respectively. */ | |
c8a0e52b | 6520 | |
e9ec370e | 6521 | const char * |
f26036bb | 6522 | output_lbranch (rtx dest, rtx insn, int xdelay) |
e9ec370e | 6523 | { |
6524 | rtx xoperands[2]; | |
6525 | ||
6526 | xoperands[0] = dest; | |
c8a0e52b | 6527 | |
e9ec370e | 6528 | /* First, free up the delay slot. */ |
f26036bb | 6529 | if (xdelay && dbr_sequence_length () != 0) |
e9ec370e | 6530 | { |
6531 | /* We can't handle a jump in the delay slot. */ | |
ecf2283d | 6532 | gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN); |
c8a0e52b | 6533 | |
e9ec370e | 6534 | final_scan_insn (NEXT_INSN (insn), asm_out_file, |
4bf029b0 | 6535 | optimize, 0, NULL); |
c8a0e52b | 6536 | |
e9ec370e | 6537 | /* Now delete the delay insn. */ |
ad4583d9 | 6538 | SET_INSN_DELETED (NEXT_INSN (insn)); |
e9ec370e | 6539 | } |
c8a0e52b | 6540 | |
e9ec370e | 6541 | /* Output an insn to save %r1. The runtime documentation doesn't |
6542 | specify whether the "Clean Up" slot in the callers frame can | |
6543 | be clobbered by the callee. It isn't copied by HP's builtin | |
6544 | alloca, so this suggests that it can be clobbered if necessary. | |
6545 | The "Static Link" location is copied by HP builtin alloca, so | |
6546 | we avoid using it. Using the cleanup slot might be a problem | |
6547 | if we have to interoperate with languages that pass cleanup | |
6548 | information. However, it should be possible to handle these | |
6549 | situations with GCC's asm feature. | |
6550 | ||
6551 | The "Current RP" slot is reserved for the called procedure, so | |
6552 | we try to use it when we don't have a frame of our own. It's | |
6553 | rather unlikely that we won't have a frame when we need to emit | |
6554 | a very long branch. | |
6555 | ||
6556 | Really the way to go long term is a register scavenger; goto | |
6557 | the target of the jump and find a register which we can use | |
6558 | as a scratch to hold the value in %r1. Then, we wouldn't have | |
6559 | to free up the delay slot or clobber a slot that may be needed | |
6560 | for other purposes. */ | |
6561 | if (TARGET_64BIT) | |
6562 | { | |
3072d30e | 6563 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6564 | /* Use the return pointer slot in the frame marker. */ |
6565 | output_asm_insn ("std %%r1,-16(%%r30)", xoperands); | |
6566 | else | |
6567 | /* Use the slot at -40 in the frame marker since HP builtin | |
6568 | alloca doesn't copy it. */ | |
6569 | output_asm_insn ("std %%r1,-40(%%r30)", xoperands); | |
6570 | } | |
6571 | else | |
6572 | { | |
3072d30e | 6573 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6574 | /* Use the return pointer slot in the frame marker. */ |
6575 | output_asm_insn ("stw %%r1,-20(%%r30)", xoperands); | |
6576 | else | |
6577 | /* Use the "Clean Up" slot in the frame marker. In GCC, | |
6578 | the only other use of this location is for copying a | |
6579 | floating point double argument from a floating-point | |
6580 | register to two general registers. The copy is done | |
19ee40ed | 6581 | as an "atomic" operation when outputting a call, so it |
e9ec370e | 6582 | won't interfere with our using the location here. */ |
6583 | output_asm_insn ("stw %%r1,-12(%%r30)", xoperands); | |
6584 | } | |
b70ea764 | 6585 | |
2247cc5f | 6586 | if (TARGET_PORTABLE_RUNTIME) |
6587 | { | |
6588 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6589 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
6590 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6591 | } | |
6592 | else if (flag_pic) | |
e9ec370e | 6593 | { |
6594 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
6595 | if (TARGET_SOM || !TARGET_GAS) | |
6596 | { | |
6597 | xoperands[1] = gen_label_rtx (); | |
6598 | output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands); | |
c5559ed4 | 6599 | targetm.asm_out.internal_label (asm_out_file, "L", |
6600 | CODE_LABEL_NUMBER (xoperands[1])); | |
e9ec370e | 6601 | output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands); |
c8a0e52b | 6602 | } |
e9ec370e | 6603 | else |
6604 | { | |
6605 | output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6606 | output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6607 | } | |
6608 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6609 | } | |
6610 | else | |
6611 | /* Now output a very long branch to the original target. */ | |
6612 | output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands); | |
c8a0e52b | 6613 | |
e9ec370e | 6614 | /* Now restore the value of %r1 in the delay slot. */ |
6615 | if (TARGET_64BIT) | |
6616 | { | |
3072d30e | 6617 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6618 | return "ldd -16(%%r30),%%r1"; |
6619 | else | |
6620 | return "ldd -40(%%r30),%%r1"; | |
6621 | } | |
6622 | else | |
6623 | { | |
3072d30e | 6624 | if (actual_fsize == 0 && !df_regs_ever_live_p (2)) |
e9ec370e | 6625 | return "ldw -20(%%r30),%%r1"; |
6626 | else | |
6627 | return "ldw -12(%%r30),%%r1"; | |
5fbd5940 | 6628 | } |
0d986529 | 6629 | } |
6630 | ||
6d36483b | 6631 | /* This routine handles all the branch-on-bit conditional branch sequences we |
0d986529 | 6632 | might need to generate. It handles nullification of delay slots, |
6633 | varying length branches, negated branches and all combinations of the | |
6634 | above. it returns the appropriate output template to emit the branch. */ | |
6635 | ||
611a88e1 | 6636 | const char * |
f26036bb | 6637 | output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
29a4502c | 6638 | { |
0d986529 | 6639 | static char buf[100]; |
ebeae299 | 6640 | bool useskip; |
f26036bb | 6641 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6642 | int length = get_attr_length (insn); | |
6643 | int xdelay; | |
0d986529 | 6644 | |
a361b456 | 6645 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 6646 | asking for a disaster. I do not think this can happen as this pattern |
6d36483b | 6647 | is only used when optimizing; jump optimization should eliminate the |
29a4502c | 6648 | jump. But be prepared just in case. */ |
6d36483b | 6649 | |
317754f4 | 6650 | if (branch_to_delay_slot_p (insn)) |
ece0fa59 | 6651 | return "nop"; |
6d36483b | 6652 | |
5fbd5940 | 6653 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6654 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6655 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6656 | nullify = 1; |
6657 | ||
6658 | /* If this is a short forward conditional branch which did not get | |
6659 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6660 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6661 | nullify = forward_branch_p (insn); |
6662 | ||
6d36483b | 6663 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6664 | extrs instruction. This avoids a single cycle penalty due to |
6665 | mis-predicted branch if we fall through (branch not taken). */ | |
ebeae299 | 6666 | useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; |
0d986529 | 6667 | |
6668 | switch (length) | |
6669 | { | |
6670 | ||
5fbd5940 | 6671 | /* All short conditional branches except backwards with an unfilled |
6672 | delay slot. */ | |
5a1231ef | 6673 | case 4: |
0d986529 | 6674 | if (useskip) |
e4065f95 | 6675 | strcpy (buf, "{extrs,|extrw,s,}"); |
6d36483b | 6676 | else |
0d986529 | 6677 | strcpy (buf, "bb,"); |
5e3c5739 | 6678 | if (useskip && GET_MODE (operands[0]) == DImode) |
6679 | strcpy (buf, "extrd,s,*"); | |
6680 | else if (GET_MODE (operands[0]) == DImode) | |
6681 | strcpy (buf, "bb,*"); | |
0d986529 | 6682 | if ((which == 0 && negated) |
6683 | || (which == 1 && ! negated)) | |
6684 | strcat (buf, ">="); | |
6685 | else | |
6686 | strcat (buf, "<"); | |
6687 | if (useskip) | |
5a811d43 | 6688 | strcat (buf, " %0,%1,1,%%r0"); |
0d986529 | 6689 | else if (nullify && negated) |
317754f4 | 6690 | { |
6691 | if (branch_needs_nop_p (insn)) | |
6692 | strcat (buf, ",n %0,%1,%3%#"); | |
6693 | else | |
6694 | strcat (buf, ",n %0,%1,%3"); | |
6695 | } | |
0d986529 | 6696 | else if (nullify && ! negated) |
317754f4 | 6697 | { |
6698 | if (branch_needs_nop_p (insn)) | |
6699 | strcat (buf, ",n %0,%1,%2%#"); | |
6700 | else | |
6701 | strcat (buf, ",n %0,%1,%2"); | |
6702 | } | |
0d986529 | 6703 | else if (! nullify && negated) |
317754f4 | 6704 | strcat (buf, " %0,%1,%3"); |
0d986529 | 6705 | else if (! nullify && ! negated) |
5fbd5940 | 6706 | strcat (buf, " %0,%1,%2"); |
0d986529 | 6707 | break; |
6708 | ||
87fcb603 | 6709 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6710 | unfilled delay slot is treated just like a long backward branch |
6711 | with an unfilled delay slot. */ | |
5a1231ef | 6712 | case 8: |
5fbd5940 | 6713 | /* Handle weird backwards branch with a filled delay slot |
f26036bb | 6714 | which is nullified. */ |
5fbd5940 | 6715 | if (dbr_sequence_length () != 0 |
6716 | && ! forward_branch_p (insn) | |
6717 | && nullify) | |
6718 | { | |
6719 | strcpy (buf, "bb,"); | |
5e3c5739 | 6720 | if (GET_MODE (operands[0]) == DImode) |
6721 | strcat (buf, "*"); | |
5fbd5940 | 6722 | if ((which == 0 && negated) |
6723 | || (which == 1 && ! negated)) | |
6724 | strcat (buf, "<"); | |
6725 | else | |
6726 | strcat (buf, ">="); | |
6727 | if (negated) | |
5a811d43 | 6728 | strcat (buf, ",n %0,%1,.+12\n\tb %3"); |
5fbd5940 | 6729 | else |
5a811d43 | 6730 | strcat (buf, ",n %0,%1,.+12\n\tb %2"); |
5fbd5940 | 6731 | } |
43f0c1f2 | 6732 | /* Handle short backwards branch with an unfilled delay slot. |
6733 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6734 | taken and untaken branches. */ | |
6735 | else if (dbr_sequence_length () == 0 | |
6736 | && ! forward_branch_p (insn) | |
47fc0706 | 6737 | && INSN_ADDRESSES_SET_P () |
6738 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6739 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6740 | { |
6741 | strcpy (buf, "bb,"); | |
5e3c5739 | 6742 | if (GET_MODE (operands[0]) == DImode) |
6743 | strcat (buf, "*"); | |
43f0c1f2 | 6744 | if ((which == 0 && negated) |
6745 | || (which == 1 && ! negated)) | |
6746 | strcat (buf, ">="); | |
6747 | else | |
6748 | strcat (buf, "<"); | |
6749 | if (negated) | |
6750 | strcat (buf, " %0,%1,%3%#"); | |
6751 | else | |
6752 | strcat (buf, " %0,%1,%2%#"); | |
6753 | } | |
0d986529 | 6754 | else |
5fbd5940 | 6755 | { |
5e3c5739 | 6756 | if (GET_MODE (operands[0]) == DImode) |
6757 | strcpy (buf, "extrd,s,*"); | |
f26036bb | 6758 | else |
6759 | strcpy (buf, "{extrs,|extrw,s,}"); | |
5fbd5940 | 6760 | if ((which == 0 && negated) |
6761 | || (which == 1 && ! negated)) | |
6762 | strcat (buf, "<"); | |
6763 | else | |
6764 | strcat (buf, ">="); | |
6765 | if (nullify && negated) | |
c6ae275c | 6766 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %3"); |
5fbd5940 | 6767 | else if (nullify && ! negated) |
c6ae275c | 6768 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %2"); |
5fbd5940 | 6769 | else if (negated) |
5a811d43 | 6770 | strcat (buf, " %0,%1,1,%%r0\n\tb %3"); |
6d36483b | 6771 | else |
5a811d43 | 6772 | strcat (buf, " %0,%1,1,%%r0\n\tb %2"); |
5fbd5940 | 6773 | } |
0d986529 | 6774 | break; |
6775 | ||
6776 | default: | |
f26036bb | 6777 | /* The reversed conditional branch must branch over one additional |
6778 | instruction if the delay slot is filled and needs to be extracted | |
6779 | by output_lbranch. If the delay slot is empty or this is a | |
6780 | nullified forward branch, the instruction after the reversed | |
6781 | condition branch must be nullified. */ | |
6782 | if (dbr_sequence_length () == 0 | |
6783 | || (nullify && forward_branch_p (insn))) | |
6784 | { | |
6785 | nullify = 1; | |
6786 | xdelay = 0; | |
d9e3874e | 6787 | operands[4] = GEN_INT (length); |
f26036bb | 6788 | } |
6789 | else | |
6790 | { | |
6791 | xdelay = 1; | |
d9e3874e | 6792 | operands[4] = GEN_INT (length + 4); |
f26036bb | 6793 | } |
6794 | ||
6795 | if (GET_MODE (operands[0]) == DImode) | |
d9e3874e | 6796 | strcpy (buf, "bb,*"); |
f26036bb | 6797 | else |
d9e3874e | 6798 | strcpy (buf, "bb,"); |
f26036bb | 6799 | if ((which == 0 && negated) |
6800 | || (which == 1 && !negated)) | |
d9e3874e | 6801 | strcat (buf, "<"); |
f26036bb | 6802 | else |
d9e3874e | 6803 | strcat (buf, ">="); |
f26036bb | 6804 | if (nullify) |
d9e3874e | 6805 | strcat (buf, ",n %0,%1,.+%4"); |
f26036bb | 6806 | else |
d9e3874e | 6807 | strcat (buf, " %0,%1,.+%4"); |
f26036bb | 6808 | output_asm_insn (buf, operands); |
6809 | return output_lbranch (negated ? operands[3] : operands[2], | |
6810 | insn, xdelay); | |
5fbd5940 | 6811 | } |
0d986529 | 6812 | return buf; |
6813 | } | |
6814 | ||
c7a4e712 | 6815 | /* This routine handles all the branch-on-variable-bit conditional branch |
6816 | sequences we might need to generate. It handles nullification of delay | |
6817 | slots, varying length branches, negated branches and all combinations | |
6818 | of the above. it returns the appropriate output template to emit the | |
6819 | branch. */ | |
6820 | ||
611a88e1 | 6821 | const char * |
f26036bb | 6822 | output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which) |
c7a4e712 | 6823 | { |
6824 | static char buf[100]; | |
ebeae299 | 6825 | bool useskip; |
f26036bb | 6826 | int nullify = INSN_ANNULLED_BRANCH_P (insn); |
6827 | int length = get_attr_length (insn); | |
6828 | int xdelay; | |
c7a4e712 | 6829 | |
a361b456 | 6830 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
c7a4e712 | 6831 | asking for a disaster. I do not think this can happen as this pattern |
6832 | is only used when optimizing; jump optimization should eliminate the | |
6833 | jump. But be prepared just in case. */ | |
6834 | ||
317754f4 | 6835 | if (branch_to_delay_slot_p (insn)) |
ece0fa59 | 6836 | return "nop"; |
c7a4e712 | 6837 | |
6838 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6839 | as it can nullify the delay slot and save a nop. */ | |
6840 | if (length == 8 && dbr_sequence_length () == 0) | |
6841 | nullify = 1; | |
6842 | ||
6843 | /* If this is a short forward conditional branch which did not get | |
6844 | its delay slot filled, the delay slot can still be nullified. */ | |
6845 | if (! nullify && length == 4 && dbr_sequence_length () == 0) | |
6846 | nullify = forward_branch_p (insn); | |
6847 | ||
6848 | /* A forward branch over a single nullified insn can be done with a | |
6849 | extrs instruction. This avoids a single cycle penalty due to | |
6850 | mis-predicted branch if we fall through (branch not taken). */ | |
ebeae299 | 6851 | useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE; |
c7a4e712 | 6852 | |
6853 | switch (length) | |
6854 | { | |
6855 | ||
6856 | /* All short conditional branches except backwards with an unfilled | |
6857 | delay slot. */ | |
6858 | case 4: | |
6859 | if (useskip) | |
e4065f95 | 6860 | strcpy (buf, "{vextrs,|extrw,s,}"); |
c7a4e712 | 6861 | else |
e4065f95 | 6862 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6863 | if (useskip && GET_MODE (operands[0]) == DImode) |
e75269fd | 6864 | strcpy (buf, "extrd,s,*"); |
5e3c5739 | 6865 | else if (GET_MODE (operands[0]) == DImode) |
6866 | strcpy (buf, "bb,*"); | |
c7a4e712 | 6867 | if ((which == 0 && negated) |
6868 | || (which == 1 && ! negated)) | |
6869 | strcat (buf, ">="); | |
6870 | else | |
6871 | strcat (buf, "<"); | |
6872 | if (useskip) | |
e4065f95 | 6873 | strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}"); |
c7a4e712 | 6874 | else if (nullify && negated) |
317754f4 | 6875 | { |
6876 | if (branch_needs_nop_p (insn)) | |
6877 | strcat (buf, "{,n %0,%3%#|,n %0,%%sar,%3%#}"); | |
6878 | else | |
6879 | strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}"); | |
6880 | } | |
c7a4e712 | 6881 | else if (nullify && ! negated) |
317754f4 | 6882 | { |
6883 | if (branch_needs_nop_p (insn)) | |
6884 | strcat (buf, "{,n %0,%2%#|,n %0,%%sar,%2%#}"); | |
6885 | else | |
6886 | strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}"); | |
6887 | } | |
c7a4e712 | 6888 | else if (! nullify && negated) |
317754f4 | 6889 | strcat (buf, "{ %0,%3| %0,%%sar,%3}"); |
c7a4e712 | 6890 | else if (! nullify && ! negated) |
e4065f95 | 6891 | strcat (buf, "{ %0,%2| %0,%%sar,%2}"); |
c7a4e712 | 6892 | break; |
6893 | ||
87fcb603 | 6894 | /* All long conditionals. Note a short backward branch with an |
c7a4e712 | 6895 | unfilled delay slot is treated just like a long backward branch |
6896 | with an unfilled delay slot. */ | |
6897 | case 8: | |
6898 | /* Handle weird backwards branch with a filled delay slot | |
f26036bb | 6899 | which is nullified. */ |
c7a4e712 | 6900 | if (dbr_sequence_length () != 0 |
6901 | && ! forward_branch_p (insn) | |
6902 | && nullify) | |
6903 | { | |
e4065f95 | 6904 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6905 | if (GET_MODE (operands[0]) == DImode) |
6906 | strcat (buf, "*"); | |
c7a4e712 | 6907 | if ((which == 0 && negated) |
6908 | || (which == 1 && ! negated)) | |
6909 | strcat (buf, "<"); | |
6910 | else | |
6911 | strcat (buf, ">="); | |
6912 | if (negated) | |
e4065f95 | 6913 | strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}"); |
c7a4e712 | 6914 | else |
e4065f95 | 6915 | strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}"); |
c7a4e712 | 6916 | } |
6917 | /* Handle short backwards branch with an unfilled delay slot. | |
6918 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6919 | taken and untaken branches. */ | |
6920 | else if (dbr_sequence_length () == 0 | |
6921 | && ! forward_branch_p (insn) | |
47fc0706 | 6922 | && INSN_ADDRESSES_SET_P () |
6923 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6924 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
c7a4e712 | 6925 | { |
e4065f95 | 6926 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6927 | if (GET_MODE (operands[0]) == DImode) |
6928 | strcat (buf, "*"); | |
c7a4e712 | 6929 | if ((which == 0 && negated) |
6930 | || (which == 1 && ! negated)) | |
6931 | strcat (buf, ">="); | |
6932 | else | |
6933 | strcat (buf, "<"); | |
6934 | if (negated) | |
e4065f95 | 6935 | strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}"); |
c7a4e712 | 6936 | else |
e4065f95 | 6937 | strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}"); |
c7a4e712 | 6938 | } |
6939 | else | |
6940 | { | |
e4065f95 | 6941 | strcpy (buf, "{vextrs,|extrw,s,}"); |
5e3c5739 | 6942 | if (GET_MODE (operands[0]) == DImode) |
6943 | strcpy (buf, "extrd,s,*"); | |
c7a4e712 | 6944 | if ((which == 0 && negated) |
6945 | || (which == 1 && ! negated)) | |
6946 | strcat (buf, "<"); | |
6947 | else | |
6948 | strcat (buf, ">="); | |
6949 | if (nullify && negated) | |
e4065f95 | 6950 | strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}"); |
c7a4e712 | 6951 | else if (nullify && ! negated) |
e4065f95 | 6952 | strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}"); |
c7a4e712 | 6953 | else if (negated) |
e4065f95 | 6954 | strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}"); |
c7a4e712 | 6955 | else |
e4065f95 | 6956 | strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}"); |
c7a4e712 | 6957 | } |
6958 | break; | |
6959 | ||
6960 | default: | |
f26036bb | 6961 | /* The reversed conditional branch must branch over one additional |
6962 | instruction if the delay slot is filled and needs to be extracted | |
6963 | by output_lbranch. If the delay slot is empty or this is a | |
6964 | nullified forward branch, the instruction after the reversed | |
6965 | condition branch must be nullified. */ | |
6966 | if (dbr_sequence_length () == 0 | |
6967 | || (nullify && forward_branch_p (insn))) | |
6968 | { | |
6969 | nullify = 1; | |
6970 | xdelay = 0; | |
d9e3874e | 6971 | operands[4] = GEN_INT (length); |
f26036bb | 6972 | } |
6973 | else | |
6974 | { | |
6975 | xdelay = 1; | |
d9e3874e | 6976 | operands[4] = GEN_INT (length + 4); |
f26036bb | 6977 | } |
6978 | ||
6979 | if (GET_MODE (operands[0]) == DImode) | |
d9e3874e | 6980 | strcpy (buf, "bb,*"); |
f26036bb | 6981 | else |
d9e3874e | 6982 | strcpy (buf, "{bvb,|bb,}"); |
f26036bb | 6983 | if ((which == 0 && negated) |
6984 | || (which == 1 && !negated)) | |
d9e3874e | 6985 | strcat (buf, "<"); |
f26036bb | 6986 | else |
d9e3874e | 6987 | strcat (buf, ">="); |
f26036bb | 6988 | if (nullify) |
d9e3874e | 6989 | strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}"); |
f26036bb | 6990 | else |
d9e3874e | 6991 | strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}"); |
f26036bb | 6992 | output_asm_insn (buf, operands); |
6993 | return output_lbranch (negated ? operands[3] : operands[2], | |
6994 | insn, xdelay); | |
c7a4e712 | 6995 | } |
6996 | return buf; | |
6997 | } | |
6998 | ||
29a4502c | 6999 | /* Return the output template for emitting a dbra type insn. |
7000 | ||
7001 | Note it may perform some output operations on its own before | |
7002 | returning the final output string. */ | |
611a88e1 | 7003 | const char * |
5c1d8983 | 7004 | output_dbra (rtx *operands, rtx insn, int which_alternative) |
29a4502c | 7005 | { |
f26036bb | 7006 | int length = get_attr_length (insn); |
29a4502c | 7007 | |
a361b456 | 7008 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 7009 | asking for a disaster. Be prepared! */ |
7010 | ||
317754f4 | 7011 | if (branch_to_delay_slot_p (insn)) |
29a4502c | 7012 | { |
7013 | if (which_alternative == 0) | |
7014 | return "ldo %1(%0),%0"; | |
7015 | else if (which_alternative == 1) | |
7016 | { | |
ea52c577 | 7017 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands); |
7018 | output_asm_insn ("ldw -16(%%r30),%4", operands); | |
34940871 | 7019 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
e4065f95 | 7020 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 7021 | } |
7022 | else | |
7023 | { | |
7024 | output_asm_insn ("ldw %0,%4", operands); | |
7025 | return "ldo %1(%4),%4\n\tstw %4,%0"; | |
7026 | } | |
7027 | } | |
7028 | ||
7029 | if (which_alternative == 0) | |
7030 | { | |
7031 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
f26036bb | 7032 | int xdelay; |
29a4502c | 7033 | |
7034 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
7035 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 7036 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 7037 | nullify = 1; |
7038 | ||
7039 | /* If this is a short forward conditional branch which did not get | |
7040 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 7041 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 7042 | nullify = forward_branch_p (insn); |
7043 | ||
ecf2283d | 7044 | switch (length) |
29a4502c | 7045 | { |
ecf2283d | 7046 | case 4: |
7047 | if (nullify) | |
317754f4 | 7048 | { |
7049 | if (branch_needs_nop_p (insn)) | |
7050 | return "addib,%C2,n %1,%0,%3%#"; | |
7051 | else | |
7052 | return "addib,%C2,n %1,%0,%3"; | |
7053 | } | |
ecf2283d | 7054 | else |
7055 | return "addib,%C2 %1,%0,%3"; | |
7056 | ||
7057 | case 8: | |
6d36483b | 7058 | /* Handle weird backwards branch with a fulled delay slot |
29a4502c | 7059 | which is nullified. */ |
7060 | if (dbr_sequence_length () != 0 | |
7061 | && ! forward_branch_p (insn) | |
7062 | && nullify) | |
5a811d43 | 7063 | return "addib,%N2,n %1,%0,.+12\n\tb %3"; |
43f0c1f2 | 7064 | /* Handle short backwards branch with an unfilled delay slot. |
7065 | Using a addb;nop rather than addi;bl saves 1 cycle for both | |
7066 | taken and untaken branches. */ | |
7067 | else if (dbr_sequence_length () == 0 | |
7068 | && ! forward_branch_p (insn) | |
47fc0706 | 7069 | && INSN_ADDRESSES_SET_P () |
7070 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
7071 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 7072 | return "addib,%C2 %1,%0,%3%#"; |
6d36483b | 7073 | |
7074 | /* Handle normal cases. */ | |
29a4502c | 7075 | if (nullify) |
5a811d43 | 7076 | return "addi,%N2 %1,%0,%0\n\tb,n %3"; |
29a4502c | 7077 | else |
5a811d43 | 7078 | return "addi,%N2 %1,%0,%0\n\tb %3"; |
ecf2283d | 7079 | |
7080 | default: | |
f26036bb | 7081 | /* The reversed conditional branch must branch over one additional |
7082 | instruction if the delay slot is filled and needs to be extracted | |
7083 | by output_lbranch. If the delay slot is empty or this is a | |
7084 | nullified forward branch, the instruction after the reversed | |
7085 | condition branch must be nullified. */ | |
7086 | if (dbr_sequence_length () == 0 | |
7087 | || (nullify && forward_branch_p (insn))) | |
7088 | { | |
7089 | nullify = 1; | |
7090 | xdelay = 0; | |
7091 | operands[4] = GEN_INT (length); | |
7092 | } | |
7093 | else | |
7094 | { | |
7095 | xdelay = 1; | |
7096 | operands[4] = GEN_INT (length + 4); | |
7097 | } | |
7098 | ||
7099 | if (nullify) | |
7100 | output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands); | |
7101 | else | |
7102 | output_asm_insn ("addib,%N2 %1,%0,.+%4", operands); | |
7103 | ||
7104 | return output_lbranch (operands[3], insn, xdelay); | |
29a4502c | 7105 | } |
ecf2283d | 7106 | |
29a4502c | 7107 | } |
7108 | /* Deal with gross reload from FP register case. */ | |
7109 | else if (which_alternative == 1) | |
7110 | { | |
7111 | /* Move loop counter from FP register to MEM then into a GR, | |
7112 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 7113 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 7114 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4", |
7115 | operands); | |
34940871 | 7116 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
f26036bb | 7117 | if (length == 24) |
e4065f95 | 7118 | return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7119 | else if (length == 28) |
e4065f95 | 7120 | return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7121 | else |
7122 | { | |
d9e3874e | 7123 | operands[5] = GEN_INT (length - 16); |
7124 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands); | |
f26036bb | 7125 | output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands); |
7126 | return output_lbranch (operands[3], insn, 0); | |
7127 | } | |
29a4502c | 7128 | } |
7129 | /* Deal with gross reload from memory case. */ | |
7130 | else | |
7131 | { | |
7132 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 7133 | happens in the branch's delay slot. */ |
29a4502c | 7134 | output_asm_insn ("ldw %0,%4", operands); |
f26036bb | 7135 | if (length == 12) |
29a4502c | 7136 | return "addib,%C2 %1,%4,%3\n\tstw %4,%0"; |
f26036bb | 7137 | else if (length == 16) |
5a811d43 | 7138 | return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0"; |
f26036bb | 7139 | else |
7140 | { | |
d9e3874e | 7141 | operands[5] = GEN_INT (length - 4); |
7142 | output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands); | |
f26036bb | 7143 | return output_lbranch (operands[3], insn, 0); |
7144 | } | |
29a4502c | 7145 | } |
7146 | } | |
7147 | ||
f26036bb | 7148 | /* Return the output template for emitting a movb type insn. |
29a4502c | 7149 | |
7150 | Note it may perform some output operations on its own before | |
7151 | returning the final output string. */ | |
611a88e1 | 7152 | const char * |
5c1d8983 | 7153 | output_movb (rtx *operands, rtx insn, int which_alternative, |
7154 | int reverse_comparison) | |
29a4502c | 7155 | { |
f26036bb | 7156 | int length = get_attr_length (insn); |
29a4502c | 7157 | |
a361b456 | 7158 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 7159 | asking for a disaster. Be prepared! */ |
7160 | ||
317754f4 | 7161 | if (branch_to_delay_slot_p (insn)) |
29a4502c | 7162 | { |
7163 | if (which_alternative == 0) | |
7164 | return "copy %1,%0"; | |
7165 | else if (which_alternative == 1) | |
7166 | { | |
ea52c577 | 7167 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
e4065f95 | 7168 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 7169 | } |
546a40bd | 7170 | else if (which_alternative == 2) |
29a4502c | 7171 | return "stw %1,%0"; |
546a40bd | 7172 | else |
7173 | return "mtsar %r1"; | |
29a4502c | 7174 | } |
7175 | ||
7176 | /* Support the second variant. */ | |
7177 | if (reverse_comparison) | |
7178 | PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2]))); | |
7179 | ||
7180 | if (which_alternative == 0) | |
7181 | { | |
7182 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
f26036bb | 7183 | int xdelay; |
29a4502c | 7184 | |
7185 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
7186 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 7187 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 7188 | nullify = 1; |
7189 | ||
7190 | /* If this is a short forward conditional branch which did not get | |
7191 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 7192 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 7193 | nullify = forward_branch_p (insn); |
7194 | ||
ecf2283d | 7195 | switch (length) |
29a4502c | 7196 | { |
ecf2283d | 7197 | case 4: |
7198 | if (nullify) | |
317754f4 | 7199 | { |
7200 | if (branch_needs_nop_p (insn)) | |
7201 | return "movb,%C2,n %1,%0,%3%#"; | |
7202 | else | |
7203 | return "movb,%C2,n %1,%0,%3"; | |
7204 | } | |
ecf2283d | 7205 | else |
7206 | return "movb,%C2 %1,%0,%3"; | |
7207 | ||
7208 | case 8: | |
6d36483b | 7209 | /* Handle weird backwards branch with a filled delay slot |
29a4502c | 7210 | which is nullified. */ |
7211 | if (dbr_sequence_length () != 0 | |
7212 | && ! forward_branch_p (insn) | |
7213 | && nullify) | |
5a811d43 | 7214 | return "movb,%N2,n %1,%0,.+12\n\tb %3"; |
6d36483b | 7215 | |
43f0c1f2 | 7216 | /* Handle short backwards branch with an unfilled delay slot. |
7217 | Using a movb;nop rather than or;bl saves 1 cycle for both | |
7218 | taken and untaken branches. */ | |
7219 | else if (dbr_sequence_length () == 0 | |
7220 | && ! forward_branch_p (insn) | |
47fc0706 | 7221 | && INSN_ADDRESSES_SET_P () |
7222 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
7223 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 7224 | return "movb,%C2 %1,%0,%3%#"; |
6d36483b | 7225 | /* Handle normal cases. */ |
29a4502c | 7226 | if (nullify) |
5a811d43 | 7227 | return "or,%N2 %1,%%r0,%0\n\tb,n %3"; |
29a4502c | 7228 | else |
5a811d43 | 7229 | return "or,%N2 %1,%%r0,%0\n\tb %3"; |
ecf2283d | 7230 | |
7231 | default: | |
f26036bb | 7232 | /* The reversed conditional branch must branch over one additional |
7233 | instruction if the delay slot is filled and needs to be extracted | |
7234 | by output_lbranch. If the delay slot is empty or this is a | |
7235 | nullified forward branch, the instruction after the reversed | |
7236 | condition branch must be nullified. */ | |
7237 | if (dbr_sequence_length () == 0 | |
7238 | || (nullify && forward_branch_p (insn))) | |
7239 | { | |
7240 | nullify = 1; | |
7241 | xdelay = 0; | |
7242 | operands[4] = GEN_INT (length); | |
7243 | } | |
7244 | else | |
7245 | { | |
7246 | xdelay = 1; | |
7247 | operands[4] = GEN_INT (length + 4); | |
7248 | } | |
7249 | ||
7250 | if (nullify) | |
7251 | output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands); | |
7252 | else | |
7253 | output_asm_insn ("movb,%N2 %1,%0,.+%4", operands); | |
7254 | ||
7255 | return output_lbranch (operands[3], insn, xdelay); | |
29a4502c | 7256 | } |
29a4502c | 7257 | } |
f26036bb | 7258 | /* Deal with gross reload for FP destination register case. */ |
29a4502c | 7259 | else if (which_alternative == 1) |
7260 | { | |
f26036bb | 7261 | /* Move source register to MEM, perform the branch test, then |
7262 | finally load the FP register from MEM from within the branch's | |
7263 | delay slot. */ | |
ea52c577 | 7264 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
f26036bb | 7265 | if (length == 12) |
e4065f95 | 7266 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7267 | else if (length == 16) |
e4065f95 | 7268 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
f26036bb | 7269 | else |
7270 | { | |
d9e3874e | 7271 | operands[4] = GEN_INT (length - 4); |
7272 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands); | |
f26036bb | 7273 | output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands); |
7274 | return output_lbranch (operands[3], insn, 0); | |
7275 | } | |
29a4502c | 7276 | } |
7277 | /* Deal with gross reload from memory case. */ | |
546a40bd | 7278 | else if (which_alternative == 2) |
29a4502c | 7279 | { |
7280 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 7281 | happens in the branch's delay slot. */ |
f26036bb | 7282 | if (length == 8) |
e4065f95 | 7283 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0"; |
f26036bb | 7284 | else if (length == 12) |
e4065f95 | 7285 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0"; |
f26036bb | 7286 | else |
7287 | { | |
d9e3874e | 7288 | operands[4] = GEN_INT (length); |
7289 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0", | |
7290 | operands); | |
f26036bb | 7291 | return output_lbranch (operands[3], insn, 0); |
7292 | } | |
29a4502c | 7293 | } |
546a40bd | 7294 | /* Handle SAR as a destination. */ |
7295 | else | |
7296 | { | |
f26036bb | 7297 | if (length == 8) |
e4065f95 | 7298 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1"; |
f26036bb | 7299 | else if (length == 12) |
be7770ad | 7300 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1"; |
f26036bb | 7301 | else |
7302 | { | |
d9e3874e | 7303 | operands[4] = GEN_INT (length); |
7304 | output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1", | |
7305 | operands); | |
f26036bb | 7306 | return output_lbranch (operands[3], insn, 0); |
7307 | } | |
546a40bd | 7308 | } |
29a4502c | 7309 | } |
7310 | ||
ece88821 | 7311 | /* Copy any FP arguments in INSN into integer registers. */ |
7312 | static void | |
5c1d8983 | 7313 | copy_fp_args (rtx insn) |
ece88821 | 7314 | { |
7315 | rtx link; | |
7316 | rtx xoperands[2]; | |
29a4502c | 7317 | |
ece88821 | 7318 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
7319 | { | |
7320 | int arg_mode, regno; | |
7321 | rtx use = XEXP (link, 0); | |
3683f840 | 7322 | |
ece88821 | 7323 | if (! (GET_CODE (use) == USE |
7324 | && GET_CODE (XEXP (use, 0)) == REG | |
7325 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
7326 | continue; | |
d6686e21 | 7327 | |
ece88821 | 7328 | arg_mode = GET_MODE (XEXP (use, 0)); |
7329 | regno = REGNO (XEXP (use, 0)); | |
5e3c5739 | 7330 | |
ece88821 | 7331 | /* Is it a floating point register? */ |
7332 | if (regno >= 32 && regno <= 39) | |
7333 | { | |
7334 | /* Copy the FP register into an integer register via memory. */ | |
7335 | if (arg_mode == SFmode) | |
7336 | { | |
7337 | xoperands[0] = XEXP (use, 0); | |
7338 | xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2); | |
7339 | output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands); | |
7340 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
7341 | } | |
7342 | else | |
7343 | { | |
7344 | xoperands[0] = XEXP (use, 0); | |
7345 | xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2); | |
7346 | output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands); | |
7347 | output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands); | |
7348 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
7349 | } | |
7350 | } | |
06ddb6f8 | 7351 | } |
ece88821 | 7352 | } |
7353 | ||
7354 | /* Compute length of the FP argument copy sequence for INSN. */ | |
7355 | static int | |
5c1d8983 | 7356 | length_fp_args (rtx insn) |
ece88821 | 7357 | { |
7358 | int length = 0; | |
7359 | rtx link; | |
06ddb6f8 | 7360 | |
ece88821 | 7361 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
c7a4e712 | 7362 | { |
ece88821 | 7363 | int arg_mode, regno; |
7364 | rtx use = XEXP (link, 0); | |
7365 | ||
7366 | if (! (GET_CODE (use) == USE | |
7367 | && GET_CODE (XEXP (use, 0)) == REG | |
7368 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
7369 | continue; | |
c7a4e712 | 7370 | |
ece88821 | 7371 | arg_mode = GET_MODE (XEXP (use, 0)); |
7372 | regno = REGNO (XEXP (use, 0)); | |
7373 | ||
7374 | /* Is it a floating point register? */ | |
7375 | if (regno >= 32 && regno <= 39) | |
c7a4e712 | 7376 | { |
ece88821 | 7377 | if (arg_mode == SFmode) |
7378 | length += 8; | |
7379 | else | |
7380 | length += 12; | |
c7a4e712 | 7381 | } |
ece88821 | 7382 | } |
c7a4e712 | 7383 | |
ece88821 | 7384 | return length; |
7385 | } | |
b70ea764 | 7386 | |
cd0dfcc5 | 7387 | /* Return the attribute length for the millicode call instruction INSN. |
7388 | The length must match the code generated by output_millicode_call. | |
7389 | We include the delay slot in the returned length as it is better to | |
ece88821 | 7390 | over estimate the length than to under estimate it. */ |
b29897dd | 7391 | |
ece88821 | 7392 | int |
5c1d8983 | 7393 | attr_length_millicode_call (rtx insn) |
ece88821 | 7394 | { |
cd0dfcc5 | 7395 | unsigned long distance = -1; |
8a05c3c2 | 7396 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
ece88821 | 7397 | |
cd0dfcc5 | 7398 | if (INSN_ADDRESSES_SET_P ()) |
7399 | { | |
2247cc5f | 7400 | distance = (total + insn_current_reference_address (insn)); |
7401 | if (distance < total) | |
cd0dfcc5 | 7402 | distance = -1; |
7403 | } | |
ece88821 | 7404 | |
7405 | if (TARGET_64BIT) | |
7406 | { | |
7407 | if (!TARGET_LONG_CALLS && distance < 7600000) | |
cd0dfcc5 | 7408 | return 8; |
ece88821 | 7409 | |
cd0dfcc5 | 7410 | return 20; |
ece88821 | 7411 | } |
7412 | else if (TARGET_PORTABLE_RUNTIME) | |
cd0dfcc5 | 7413 | return 24; |
ece88821 | 7414 | else |
7415 | { | |
7416 | if (!TARGET_LONG_CALLS && distance < 240000) | |
cd0dfcc5 | 7417 | return 8; |
ece88821 | 7418 | |
7419 | if (TARGET_LONG_ABS_CALL && !flag_pic) | |
cd0dfcc5 | 7420 | return 12; |
ece88821 | 7421 | |
cd0dfcc5 | 7422 | return 24; |
ece88821 | 7423 | } |
7424 | } | |
7425 | ||
7426 | /* INSN is a function call. It may have an unconditional jump | |
7427 | in its delay slot. | |
b29897dd | 7428 | |
ece88821 | 7429 | CALL_DEST is the routine we are calling. */ |
b29897dd | 7430 | |
ece88821 | 7431 | const char * |
5c1d8983 | 7432 | output_millicode_call (rtx insn, rtx call_dest) |
ece88821 | 7433 | { |
7434 | int attr_length = get_attr_length (insn); | |
7435 | int seq_length = dbr_sequence_length (); | |
7436 | int distance; | |
7437 | rtx seq_insn; | |
7438 | rtx xoperands[3]; | |
b29897dd | 7439 | |
ece88821 | 7440 | xoperands[0] = call_dest; |
7441 | xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31); | |
7442 | ||
7443 | /* Handle the common case where we are sure that the branch will | |
7444 | reach the beginning of the $CODE$ subspace. The within reach | |
7445 | form of the $$sh_func_adrs call has a length of 28. Because | |
a8b24921 | 7446 | it has an attribute type of multi, it never has a nonzero |
ece88821 | 7447 | sequence length. The length of the $$sh_func_adrs is the same |
7448 | as certain out of reach PIC calls to other routines. */ | |
7449 | if (!TARGET_LONG_CALLS | |
7450 | && ((seq_length == 0 | |
7451 | && (attr_length == 12 | |
7452 | || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI))) | |
7453 | || (seq_length != 0 && attr_length == 8))) | |
7454 | { | |
7455 | output_asm_insn ("{bl|b,l} %0,%2", xoperands); | |
7456 | } | |
7457 | else | |
7458 | { | |
7459 | if (TARGET_64BIT) | |
7460 | { | |
7461 | /* It might seem that one insn could be saved by accessing | |
7462 | the millicode function using the linkage table. However, | |
7463 | this doesn't work in shared libraries and other dynamically | |
7464 | loaded objects. Using a pc-relative sequence also avoids | |
7465 | problems related to the implicit use of the gp register. */ | |
7466 | output_asm_insn ("b,l .+8,%%r1", xoperands); | |
9bd9af5d | 7467 | |
7468 | if (TARGET_GAS) | |
7469 | { | |
7470 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); | |
7471 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
7472 | } | |
7473 | else | |
7474 | { | |
7475 | xoperands[1] = gen_label_rtx (); | |
7476 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
c5559ed4 | 7477 | targetm.asm_out.internal_label (asm_out_file, "L", |
9bd9af5d | 7478 | CODE_LABEL_NUMBER (xoperands[1])); |
7479 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
7480 | } | |
7481 | ||
ece88821 | 7482 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); |
c7a4e712 | 7483 | } |
c7a4e712 | 7484 | else if (TARGET_PORTABLE_RUNTIME) |
7485 | { | |
ece88821 | 7486 | /* Pure portable runtime doesn't allow be/ble; we also don't |
7487 | have PIC support in the assembler/linker, so this sequence | |
7488 | is needed. */ | |
c7a4e712 | 7489 | |
ece88821 | 7490 | /* Get the address of our target into %r1. */ |
7491 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
7492 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
c7a4e712 | 7493 | |
ece88821 | 7494 | /* Get our return address into %r31. */ |
7495 | output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands); | |
7496 | output_asm_insn ("addi 8,%%r31,%%r31", xoperands); | |
c7a4e712 | 7497 | |
ece88821 | 7498 | /* Jump to our target address in %r1. */ |
7499 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 7500 | } |
ece88821 | 7501 | else if (!flag_pic) |
c7a4e712 | 7502 | { |
ece88821 | 7503 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
356267e0 | 7504 | if (TARGET_PA_20) |
ece88821 | 7505 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands); |
356267e0 | 7506 | else |
ece88821 | 7507 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); |
c7a4e712 | 7508 | } |
ece88821 | 7509 | else |
c7a4e712 | 7510 | { |
9bd9af5d | 7511 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
7512 | output_asm_insn ("addi 16,%%r1,%%r31", xoperands); | |
7513 | ||
ece88821 | 7514 | if (TARGET_SOM || !TARGET_GAS) |
7515 | { | |
7516 | /* The HP assembler can generate relocations for the | |
7517 | difference of two symbols. GAS can do this for a | |
7518 | millicode symbol but not an arbitrary external | |
7519 | symbol when generating SOM output. */ | |
7520 | xoperands[1] = gen_label_rtx (); | |
c5559ed4 | 7521 | targetm.asm_out.internal_label (asm_out_file, "L", |
ece88821 | 7522 | CODE_LABEL_NUMBER (xoperands[1])); |
7523 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
7524 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
7525 | } | |
7526 | else | |
7527 | { | |
ece88821 | 7528 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands); |
7529 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1", | |
7530 | xoperands); | |
7531 | } | |
c7a4e712 | 7532 | |
ece88821 | 7533 | /* Jump to our target address in %r1. */ |
7534 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 7535 | } |
c7a4e712 | 7536 | } |
7537 | ||
ece88821 | 7538 | if (seq_length == 0) |
7539 | output_asm_insn ("nop", xoperands); | |
c7a4e712 | 7540 | |
ece88821 | 7541 | /* We are done if there isn't a jump in the delay slot. */ |
7542 | if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7543 | return ""; | |
c7a4e712 | 7544 | |
ece88821 | 7545 | /* This call has an unconditional jump in its delay slot. */ |
7546 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
c7a4e712 | 7547 | |
ece88821 | 7548 | /* See if the return address can be adjusted. Use the containing |
7549 | sequence insn's address. */ | |
cd0dfcc5 | 7550 | if (INSN_ADDRESSES_SET_P ()) |
c7a4e712 | 7551 | { |
cd0dfcc5 | 7552 | seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); |
7553 | distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7554 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7555 | ||
7556 | if (VAL_14_BITS_P (distance)) | |
7557 | { | |
7558 | xoperands[1] = gen_label_rtx (); | |
7559 | output_asm_insn ("ldo %0-%1(%2),%2", xoperands); | |
c5559ed4 | 7560 | targetm.asm_out.internal_label (asm_out_file, "L", |
7561 | CODE_LABEL_NUMBER (xoperands[1])); | |
cd0dfcc5 | 7562 | } |
7563 | else | |
7564 | /* ??? This branch may not reach its target. */ | |
7565 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 7566 | } |
ece88821 | 7567 | else |
7568 | /* ??? This branch may not reach its target. */ | |
7569 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 7570 | |
7571 | /* Delete the jump. */ | |
ad4583d9 | 7572 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 7573 | |
c7a4e712 | 7574 | return ""; |
7575 | } | |
7576 | ||
cd0dfcc5 | 7577 | /* Return the attribute length of the call instruction INSN. The SIBCALL |
7578 | flag indicates whether INSN is a regular call or a sibling call. The | |
faf3f8c1 | 7579 | length returned must be longer than the code actually generated by |
7580 | output_call. Since branch shortening is done before delay branch | |
7581 | sequencing, there is no way to determine whether or not the delay | |
7582 | slot will be filled during branch shortening. Even when the delay | |
7583 | slot is filled, we may have to add a nop if the delay slot contains | |
7584 | a branch that can't reach its target. Thus, we always have to include | |
7585 | the delay slot in the length estimate. This used to be done in | |
7586 | pa_adjust_insn_length but we do it here now as some sequences always | |
7587 | fill the delay slot and we can save four bytes in the estimate for | |
7588 | these sequences. */ | |
ece88821 | 7589 | |
7590 | int | |
5c1d8983 | 7591 | attr_length_call (rtx insn, int sibcall) |
ece88821 | 7592 | { |
faf3f8c1 | 7593 | int local_call; |
f7bb6501 | 7594 | rtx call, call_dest; |
faf3f8c1 | 7595 | tree call_decl; |
7596 | int length = 0; | |
7597 | rtx pat = PATTERN (insn); | |
cd0dfcc5 | 7598 | unsigned long distance = -1; |
ece88821 | 7599 | |
f7bb6501 | 7600 | gcc_assert (GET_CODE (insn) == CALL_INSN); |
7601 | ||
cd0dfcc5 | 7602 | if (INSN_ADDRESSES_SET_P ()) |
7603 | { | |
faf3f8c1 | 7604 | unsigned long total; |
7605 | ||
7606 | total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; | |
2247cc5f | 7607 | distance = (total + insn_current_reference_address (insn)); |
7608 | if (distance < total) | |
cd0dfcc5 | 7609 | distance = -1; |
7610 | } | |
ece88821 | 7611 | |
f7bb6501 | 7612 | gcc_assert (GET_CODE (pat) == PARALLEL); |
ece88821 | 7613 | |
f7bb6501 | 7614 | /* Get the call rtx. */ |
7615 | call = XVECEXP (pat, 0, 0); | |
7616 | if (GET_CODE (call) == SET) | |
7617 | call = SET_SRC (call); | |
7618 | ||
7619 | gcc_assert (GET_CODE (call) == CALL); | |
7620 | ||
7621 | /* Determine if this is a local call. */ | |
7622 | call_dest = XEXP (XEXP (call, 0), 0); | |
faf3f8c1 | 7623 | call_decl = SYMBOL_REF_DECL (call_dest); |
c5559ed4 | 7624 | local_call = call_decl && targetm.binds_local_p (call_decl); |
ece88821 | 7625 | |
faf3f8c1 | 7626 | /* pc-relative branch. */ |
7627 | if (!TARGET_LONG_CALLS | |
7628 | && ((TARGET_PA_20 && !sibcall && distance < 7600000) | |
7629 | || distance < 240000)) | |
7630 | length += 8; | |
ece88821 | 7631 | |
faf3f8c1 | 7632 | /* 64-bit plabel sequence. */ |
7633 | else if (TARGET_64BIT && !local_call) | |
7634 | length += sibcall ? 28 : 24; | |
ece88821 | 7635 | |
faf3f8c1 | 7636 | /* non-pic long absolute branch sequence. */ |
7637 | else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) | |
7638 | length += 12; | |
ece88821 | 7639 | |
faf3f8c1 | 7640 | /* long pc-relative branch sequence. */ |
feb01ed5 | 7641 | else if (TARGET_LONG_PIC_SDIFF_CALL |
ea24f9f4 | 7642 | || (TARGET_GAS && !TARGET_SOM |
7643 | && (TARGET_LONG_PIC_PCREL_CALL || local_call))) | |
faf3f8c1 | 7644 | { |
7645 | length += 20; | |
ece88821 | 7646 | |
226f6453 | 7647 | if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS && (!local_call || flag_pic)) |
faf3f8c1 | 7648 | length += 8; |
7649 | } | |
8a05c3c2 | 7650 | |
faf3f8c1 | 7651 | /* 32-bit plabel sequence. */ |
7652 | else | |
7653 | { | |
7654 | length += 32; | |
ece88821 | 7655 | |
faf3f8c1 | 7656 | if (TARGET_SOM) |
7657 | length += length_fp_args (insn); | |
7658 | ||
7659 | if (flag_pic) | |
7660 | length += 4; | |
ee376abe | 7661 | |
faf3f8c1 | 7662 | if (!TARGET_PA_20) |
7663 | { | |
ece88821 | 7664 | if (!sibcall) |
7665 | length += 8; | |
7666 | ||
226f6453 | 7667 | if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic)) |
faf3f8c1 | 7668 | length += 8; |
ece88821 | 7669 | } |
7670 | } | |
faf3f8c1 | 7671 | |
7672 | return length; | |
ece88821 | 7673 | } |
7674 | ||
7675 | /* INSN is a function call. It may have an unconditional jump | |
c7a4e712 | 7676 | in its delay slot. |
7677 | ||
7678 | CALL_DEST is the routine we are calling. */ | |
7679 | ||
611a88e1 | 7680 | const char * |
5c1d8983 | 7681 | output_call (rtx insn, rtx call_dest, int sibcall) |
c7a4e712 | 7682 | { |
ece88821 | 7683 | int delay_insn_deleted = 0; |
7684 | int delay_slot_filled = 0; | |
b70ea764 | 7685 | int seq_length = dbr_sequence_length (); |
2247cc5f | 7686 | tree call_decl = SYMBOL_REF_DECL (call_dest); |
c5559ed4 | 7687 | int local_call = call_decl && targetm.binds_local_p (call_decl); |
ece88821 | 7688 | rtx xoperands[2]; |
7689 | ||
7690 | xoperands[0] = call_dest; | |
c7a4e712 | 7691 | |
ece88821 | 7692 | /* Handle the common case where we're sure that the branch will reach |
2247cc5f | 7693 | the beginning of the "$CODE$" subspace. This is the beginning of |
7694 | the current function if we are in a named section. */ | |
cd0dfcc5 | 7695 | if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8) |
d6686e21 | 7696 | { |
5e3c5739 | 7697 | xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2); |
ece88821 | 7698 | output_asm_insn ("{bl|b,l} %0,%1", xoperands); |
06ddb6f8 | 7699 | } |
ece88821 | 7700 | else |
06ddb6f8 | 7701 | { |
2247cc5f | 7702 | if (TARGET_64BIT && !local_call) |
3683f840 | 7703 | { |
ece88821 | 7704 | /* ??? As far as I can tell, the HP linker doesn't support the |
7705 | long pc-relative sequence described in the 64-bit runtime | |
7706 | architecture. So, we use a slightly longer indirect call. */ | |
4e75439e | 7707 | xoperands[0] = get_deferred_plabel (call_dest); |
ece88821 | 7708 | xoperands[1] = gen_label_rtx (); |
7709 | ||
7710 | /* If this isn't a sibcall, we put the load of %r27 into the | |
7711 | delay slot. We can't do this in a sibcall as we don't | |
7712 | have a second call-clobbered scratch register available. */ | |
7713 | if (seq_length != 0 | |
7714 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7715 | && !sibcall) | |
7716 | { | |
7717 | final_scan_insn (NEXT_INSN (insn), asm_out_file, | |
4bf029b0 | 7718 | optimize, 0, NULL); |
ece88821 | 7719 | |
7720 | /* Now delete the delay insn. */ | |
ad4583d9 | 7721 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 7722 | delay_insn_deleted = 1; |
7723 | } | |
06ddb6f8 | 7724 | |
ece88821 | 7725 | output_asm_insn ("addil LT'%0,%%r27", xoperands); |
7726 | output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands); | |
7727 | output_asm_insn ("ldd 0(%%r1),%%r1", xoperands); | |
06ddb6f8 | 7728 | |
ece88821 | 7729 | if (sibcall) |
06ddb6f8 | 7730 | { |
ece88821 | 7731 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); |
7732 | output_asm_insn ("ldd 16(%%r1),%%r1", xoperands); | |
7733 | output_asm_insn ("bve (%%r1)", xoperands); | |
7734 | } | |
7735 | else | |
7736 | { | |
7737 | output_asm_insn ("ldd 16(%%r1),%%r2", xoperands); | |
7738 | output_asm_insn ("bve,l (%%r2),%%r2", xoperands); | |
7739 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); | |
7740 | delay_slot_filled = 1; | |
06ddb6f8 | 7741 | } |
7742 | } | |
ece88821 | 7743 | else |
e3f53689 | 7744 | { |
ece88821 | 7745 | int indirect_call = 0; |
7746 | ||
7747 | /* Emit a long call. There are several different sequences | |
7748 | of increasing length and complexity. In most cases, | |
7749 | they don't allow an instruction in the delay slot. */ | |
2247cc5f | 7750 | if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
feb01ed5 | 7751 | && !TARGET_LONG_PIC_SDIFF_CALL |
ea24f9f4 | 7752 | && !(TARGET_GAS && !TARGET_SOM |
7753 | && (TARGET_LONG_PIC_PCREL_CALL || local_call)) | |
2247cc5f | 7754 | && !TARGET_64BIT) |
ece88821 | 7755 | indirect_call = 1; |
7756 | ||
7757 | if (seq_length != 0 | |
7758 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7759 | && !sibcall | |
c4b36071 | 7760 | && (!TARGET_PA_20 |
7761 | || indirect_call | |
7762 | || ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic))) | |
5cc6b2bc | 7763 | { |
ece88821 | 7764 | /* A non-jump insn in the delay slot. By definition we can |
7765 | emit this insn before the call (and in fact before argument | |
7766 | relocating. */ | |
4bf029b0 | 7767 | final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, |
fbf5169c | 7768 | NULL); |
ece88821 | 7769 | |
7770 | /* Now delete the delay insn. */ | |
ad4583d9 | 7771 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 7772 | delay_insn_deleted = 1; |
5cc6b2bc | 7773 | } |
e3f53689 | 7774 | |
2247cc5f | 7775 | if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
5cc6b2bc | 7776 | { |
ece88821 | 7777 | /* This is the best sequence for making long calls in |
7778 | non-pic code. Unfortunately, GNU ld doesn't provide | |
7779 | the stub needed for external calls, and GAS's support | |
2247cc5f | 7780 | for this with the SOM linker is buggy. It is safe |
7781 | to use this for local calls. */ | |
ece88821 | 7782 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
7783 | if (sibcall) | |
7784 | output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands); | |
7785 | else | |
7786 | { | |
7787 | if (TARGET_PA_20) | |
7788 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", | |
7789 | xoperands); | |
7790 | else | |
7791 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); | |
c7a4e712 | 7792 | |
ece88821 | 7793 | output_asm_insn ("copy %%r31,%%r2", xoperands); |
7794 | delay_slot_filled = 1; | |
7795 | } | |
7796 | } | |
7797 | else | |
7798 | { | |
feb01ed5 | 7799 | if (TARGET_LONG_PIC_SDIFF_CALL) |
b70ea764 | 7800 | { |
ece88821 | 7801 | /* The HP assembler and linker can handle relocations |
feb01ed5 | 7802 | for the difference of two symbols. The HP assembler |
7803 | recognizes the sequence as a pc-relative call and | |
7804 | the linker provides stubs when needed. */ | |
ece88821 | 7805 | xoperands[1] = gen_label_rtx (); |
7806 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7807 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
c5559ed4 | 7808 | targetm.asm_out.internal_label (asm_out_file, "L", |
b70ea764 | 7809 | CODE_LABEL_NUMBER (xoperands[1])); |
ece88821 | 7810 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); |
7811 | } | |
ea24f9f4 | 7812 | else if (TARGET_GAS && !TARGET_SOM |
7813 | && (TARGET_LONG_PIC_PCREL_CALL || local_call)) | |
b70ea764 | 7814 | { |
ece88821 | 7815 | /* GAS currently can't generate the relocations that |
7816 | are needed for the SOM linker under HP-UX using this | |
7817 | sequence. The GNU linker doesn't generate the stubs | |
7818 | that are needed for external calls on TARGET_ELF32 | |
7819 | with this sequence. For now, we have to use a | |
7820 | longer plabel sequence when using GAS. */ | |
7821 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7822 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", | |
b70ea764 | 7823 | xoperands); |
ece88821 | 7824 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", |
b70ea764 | 7825 | xoperands); |
7826 | } | |
5e3c5739 | 7827 | else |
7828 | { | |
ece88821 | 7829 | /* Emit a long plabel-based call sequence. This is |
7830 | essentially an inline implementation of $$dyncall. | |
7831 | We don't actually try to call $$dyncall as this is | |
7832 | as difficult as calling the function itself. */ | |
4e75439e | 7833 | xoperands[0] = get_deferred_plabel (call_dest); |
ece88821 | 7834 | xoperands[1] = gen_label_rtx (); |
7835 | ||
7836 | /* Since the call is indirect, FP arguments in registers | |
7837 | need to be copied to the general registers. Then, the | |
7838 | argument relocation stub will copy them back. */ | |
7839 | if (TARGET_SOM) | |
7840 | copy_fp_args (insn); | |
7841 | ||
7842 | if (flag_pic) | |
7843 | { | |
7844 | output_asm_insn ("addil LT'%0,%%r19", xoperands); | |
7845 | output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands); | |
7846 | output_asm_insn ("ldw 0(%%r1),%%r1", xoperands); | |
7847 | } | |
7848 | else | |
7849 | { | |
7850 | output_asm_insn ("addil LR'%0-$global$,%%r27", | |
7851 | xoperands); | |
7852 | output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1", | |
7853 | xoperands); | |
7854 | } | |
06ddb6f8 | 7855 | |
ece88821 | 7856 | output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands); |
7857 | output_asm_insn ("depi 0,31,2,%%r1", xoperands); | |
7858 | output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands); | |
7859 | output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands); | |
c7a4e712 | 7860 | |
ece88821 | 7861 | if (!sibcall && !TARGET_PA_20) |
7862 | { | |
7863 | output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands); | |
226f6453 | 7864 | if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic)) |
ee376abe | 7865 | output_asm_insn ("addi 8,%%r2,%%r2", xoperands); |
7866 | else | |
7867 | output_asm_insn ("addi 16,%%r2,%%r2", xoperands); | |
ece88821 | 7868 | } |
7869 | } | |
c7a4e712 | 7870 | |
ece88821 | 7871 | if (TARGET_PA_20) |
5e3c5739 | 7872 | { |
ece88821 | 7873 | if (sibcall) |
7874 | output_asm_insn ("bve (%%r1)", xoperands); | |
7875 | else | |
7876 | { | |
7877 | if (indirect_call) | |
7878 | { | |
7879 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7880 | output_asm_insn ("stw %%r2,-24(%%sp)", xoperands); | |
7881 | delay_slot_filled = 1; | |
7882 | } | |
7883 | else | |
7884 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7885 | } | |
5e3c5739 | 7886 | } |
7887 | else | |
7888 | { | |
226f6453 | 7889 | if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic)) |
ee376abe | 7890 | output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0", |
7891 | xoperands); | |
06ddb6f8 | 7892 | |
ece88821 | 7893 | if (sibcall) |
ee376abe | 7894 | { |
226f6453 | 7895 | if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic)) |
ee376abe | 7896 | output_asm_insn ("be 0(%%sr4,%%r1)", xoperands); |
7897 | else | |
7898 | output_asm_insn ("be 0(%%sr0,%%r1)", xoperands); | |
7899 | } | |
ece88821 | 7900 | else |
7901 | { | |
226f6453 | 7902 | if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic)) |
ee376abe | 7903 | output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands); |
7904 | else | |
7905 | output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands); | |
06ddb6f8 | 7906 | |
ece88821 | 7907 | if (indirect_call) |
7908 | output_asm_insn ("stw %%r31,-24(%%sp)", xoperands); | |
7909 | else | |
7910 | output_asm_insn ("copy %%r31,%%r2", xoperands); | |
7911 | delay_slot_filled = 1; | |
7912 | } | |
7913 | } | |
7914 | } | |
06ddb6f8 | 7915 | } |
d6686e21 | 7916 | } |
6d36483b | 7917 | |
8a05c3c2 | 7918 | if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted)) |
ece88821 | 7919 | output_asm_insn ("nop", xoperands); |
d6686e21 | 7920 | |
ece88821 | 7921 | /* We are done if there isn't a jump in the delay slot. */ |
7922 | if (seq_length == 0 | |
7923 | || delay_insn_deleted | |
7924 | || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7925 | return ""; | |
d6686e21 | 7926 | |
ece88821 | 7927 | /* A sibcall should never have a branch in the delay slot. */ |
ecf2283d | 7928 | gcc_assert (!sibcall); |
d6686e21 | 7929 | |
ece88821 | 7930 | /* This call has an unconditional jump in its delay slot. */ |
7931 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
d6686e21 | 7932 | |
cd0dfcc5 | 7933 | if (!delay_slot_filled && INSN_ADDRESSES_SET_P ()) |
d6686e21 | 7934 | { |
ece88821 | 7935 | /* See if the return address can be adjusted. Use the containing |
1b448af3 | 7936 | sequence insn's address. This would break the regular call/return@ |
7937 | relationship assumed by the table based eh unwinder, so only do that | |
7938 | if the call is not possibly throwing. */ | |
ece88821 | 7939 | rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); |
7940 | int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7941 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7942 | ||
1b448af3 | 7943 | if (VAL_14_BITS_P (distance) |
7944 | && !(can_throw_internal (insn) || can_throw_external (insn))) | |
ece88821 | 7945 | { |
7946 | xoperands[1] = gen_label_rtx (); | |
7947 | output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands); | |
c5559ed4 | 7948 | targetm.asm_out.internal_label (asm_out_file, "L", |
7949 | CODE_LABEL_NUMBER (xoperands[1])); | |
ece88821 | 7950 | } |
7951 | else | |
ece88821 | 7952 | output_asm_insn ("nop\n\tb,n %0", xoperands); |
d6686e21 | 7953 | } |
ece88821 | 7954 | else |
ece88821 | 7955 | output_asm_insn ("b,n %0", xoperands); |
d6686e21 | 7956 | |
7957 | /* Delete the jump. */ | |
ad4583d9 | 7958 | SET_INSN_DELETED (NEXT_INSN (insn)); |
ece88821 | 7959 | |
d6686e21 | 7960 | return ""; |
7961 | } | |
7962 | ||
cd0dfcc5 | 7963 | /* Return the attribute length of the indirect call instruction INSN. |
7964 | The length must match the code generated by output_indirect call. | |
7965 | The returned length includes the delay slot. Currently, the delay | |
7966 | slot of an indirect call sequence is not exposed and it is used by | |
7967 | the sequence itself. */ | |
7968 | ||
7969 | int | |
5c1d8983 | 7970 | attr_length_indirect_call (rtx insn) |
cd0dfcc5 | 7971 | { |
7972 | unsigned long distance = -1; | |
8a05c3c2 | 7973 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
cd0dfcc5 | 7974 | |
7975 | if (INSN_ADDRESSES_SET_P ()) | |
7976 | { | |
2247cc5f | 7977 | distance = (total + insn_current_reference_address (insn)); |
7978 | if (distance < total) | |
cd0dfcc5 | 7979 | distance = -1; |
7980 | } | |
7981 | ||
7982 | if (TARGET_64BIT) | |
7983 | return 12; | |
7984 | ||
7985 | if (TARGET_FAST_INDIRECT_CALLS | |
7986 | || (!TARGET_PORTABLE_RUNTIME | |
5925d47a | 7987 | && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000) |
7988 | || distance < 240000))) | |
cd0dfcc5 | 7989 | return 8; |
7990 | ||
7991 | if (flag_pic) | |
7992 | return 24; | |
7993 | ||
7994 | if (TARGET_PORTABLE_RUNTIME) | |
7995 | return 20; | |
7996 | ||
7997 | /* Out of reach, can use ble. */ | |
7998 | return 12; | |
7999 | } | |
8000 | ||
8001 | const char * | |
5c1d8983 | 8002 | output_indirect_call (rtx insn, rtx call_dest) |
cd0dfcc5 | 8003 | { |
8004 | rtx xoperands[1]; | |
8005 | ||
8006 | if (TARGET_64BIT) | |
8007 | { | |
8008 | xoperands[0] = call_dest; | |
8009 | output_asm_insn ("ldd 16(%0),%%r2", xoperands); | |
8010 | output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands); | |
8011 | return ""; | |
8012 | } | |
8013 | ||
8014 | /* First the special case for kernels, level 0 systems, etc. */ | |
8015 | if (TARGET_FAST_INDIRECT_CALLS) | |
8016 | return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2"; | |
8017 | ||
8018 | /* Now the normal case -- we can reach $$dyncall directly or | |
8019 | we're sure that we can get there via a long-branch stub. | |
8020 | ||
8021 | No need to check target flags as the length uniquely identifies | |
8022 | the remaining cases. */ | |
8023 | if (attr_length_indirect_call (insn) == 8) | |
f707acb9 | 8024 | { |
5925d47a | 8025 | /* The HP linker sometimes substitutes a BLE for BL/B,L calls to |
8026 | $$dyncall. Since BLE uses %r31 as the link register, the 22-bit | |
8027 | variant of the B,L instruction can't be used on the SOM target. */ | |
8028 | if (TARGET_PA_20 && !TARGET_SOM) | |
f707acb9 | 8029 | return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31"; |
8030 | else | |
8031 | return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2"; | |
8032 | } | |
cd0dfcc5 | 8033 | |
8034 | /* Long millicode call, but we are not generating PIC or portable runtime | |
8035 | code. */ | |
8036 | if (attr_length_indirect_call (insn) == 12) | |
8037 | return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2"; | |
8038 | ||
8039 | /* Long millicode call for portable runtime. */ | |
8040 | if (attr_length_indirect_call (insn) == 20) | |
8041 | return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop"; | |
8042 | ||
8043 | /* We need a long PIC call to $$dyncall. */ | |
8044 | xoperands[0] = NULL_RTX; | |
8045 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
8046 | if (TARGET_SOM || !TARGET_GAS) | |
8047 | { | |
8048 | xoperands[0] = gen_label_rtx (); | |
8049 | output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands); | |
c5559ed4 | 8050 | targetm.asm_out.internal_label (asm_out_file, "L", |
8051 | CODE_LABEL_NUMBER (xoperands[0])); | |
cd0dfcc5 | 8052 | output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands); |
8053 | } | |
8054 | else | |
8055 | { | |
8056 | output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands); | |
8057 | output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1", | |
8058 | xoperands); | |
8059 | } | |
8060 | output_asm_insn ("blr %%r0,%%r2", xoperands); | |
8061 | output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands); | |
8062 | return ""; | |
8063 | } | |
8064 | ||
8065 | /* Return the total length of the save and restore instructions needed for | |
8066 | the data linkage table pointer (i.e., the PIC register) across the call | |
8067 | instruction INSN. No-return calls do not require a save and restore. | |
8068 | In addition, we may be able to avoid the save and restore for calls | |
8069 | within the same translation unit. */ | |
8070 | ||
8071 | int | |
5c1d8983 | 8072 | attr_length_save_restore_dltp (rtx insn) |
cd0dfcc5 | 8073 | { |
8074 | if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
8075 | return 0; | |
8076 | ||
8077 | return 8; | |
8078 | } | |
8079 | ||
d6f01525 | 8080 | /* In HPUX 8.0's shared library scheme, special relocations are needed |
6d36483b | 8081 | for function labels if they might be passed to a function |
d6f01525 | 8082 | in a shared library (because shared libraries don't live in code |
44acf429 | 8083 | space), and special magic is needed to construct their address. */ |
d6f01525 | 8084 | |
8085 | void | |
5c1d8983 | 8086 | hppa_encode_label (rtx sym) |
d6f01525 | 8087 | { |
611a88e1 | 8088 | const char *str = XSTR (sym, 0); |
cccfb31e | 8089 | int len = strlen (str) + 1; |
8090 | char *newstr, *p; | |
d6f01525 | 8091 | |
225ab426 | 8092 | p = newstr = XALLOCAVEC (char, len + 1); |
cccfb31e | 8093 | *p++ = '@'; |
8094 | strcpy (p, str); | |
74d80a9a | 8095 | |
ea52c577 | 8096 | XSTR (sym, 0) = ggc_alloc_string (newstr, len); |
d6f01525 | 8097 | } |
6d36483b | 8098 | |
7811991d | 8099 | static void |
5c1d8983 | 8100 | pa_encode_section_info (tree decl, rtx rtl, int first) |
7811991d | 8101 | { |
54d7a10c | 8102 | int old_referenced = 0; |
8103 | ||
8104 | if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF) | |
8105 | old_referenced | |
8106 | = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED; | |
8107 | ||
716b2c5a | 8108 | default_encode_section_info (decl, rtl, first); |
8109 | ||
7811991d | 8110 | if (first && TEXT_SPACE_P (decl)) |
8111 | { | |
7811991d | 8112 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
8113 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2c129d70 | 8114 | hppa_encode_label (XEXP (rtl, 0)); |
7811991d | 8115 | } |
54d7a10c | 8116 | else if (old_referenced) |
8117 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced; | |
7811991d | 8118 | } |
8119 | ||
7b4a38a6 | 8120 | /* This is sort of inverse to pa_encode_section_info. */ |
8121 | ||
8122 | static const char * | |
5c1d8983 | 8123 | pa_strip_name_encoding (const char *str) |
7b4a38a6 | 8124 | { |
c0264367 | 8125 | str += (*str == '@'); |
8126 | str += (*str == '*'); | |
8127 | return str; | |
7b4a38a6 | 8128 | } |
8129 | ||
166bf021 | 8130 | /* Returns 1 if OP is a function label involved in a simple addition |
8131 | with a constant. Used to keep certain patterns from matching | |
8132 | during instruction combination. */ | |
8133 | int | |
5c1d8983 | 8134 | is_function_label_plus_const (rtx op) |
166bf021 | 8135 | { |
8136 | /* Strip off any CONST. */ | |
8137 | if (GET_CODE (op) == CONST) | |
8138 | op = XEXP (op, 0); | |
8139 | ||
8140 | return (GET_CODE (op) == PLUS | |
39ec41d4 | 8141 | && function_label_operand (XEXP (op, 0), VOIDmode) |
166bf021 | 8142 | && GET_CODE (XEXP (op, 1)) == CONST_INT); |
8143 | } | |
8144 | ||
f1752b7e | 8145 | /* Output assembly code for a thunk to FUNCTION. */ |
8146 | ||
6988553d | 8147 | static void |
5c1d8983 | 8148 | pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, |
8149 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
8150 | tree function) | |
f1752b7e | 8151 | { |
e678758c | 8152 | static unsigned int current_thunk_number; |
2247cc5f | 8153 | int val_14 = VAL_14_BITS_P (delta); |
21a47bc9 | 8154 | unsigned int old_last_address = last_address, nbytes = 0; |
f1752b7e | 8155 | char label[16]; |
e678758c | 8156 | rtx xoperands[4]; |
2247cc5f | 8157 | |
e678758c | 8158 | xoperands[0] = XEXP (DECL_RTL (function), 0); |
8159 | xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0); | |
8160 | xoperands[2] = GEN_INT (delta); | |
2247cc5f | 8161 | |
e678758c | 8162 | ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0)); |
8163 | fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); | |
2247cc5f | 8164 | |
8165 | /* Output the thunk. We know that the function is in the same | |
8166 | translation unit (i.e., the same space) as the thunk, and that | |
8167 | thunks are output after their method. Thus, we don't need an | |
8168 | external branch to reach the function. With SOM and GAS, | |
8169 | functions and thunks are effectively in different sections. | |
8170 | Thus, we can always use a IA-relative branch and the linker | |
8171 | will add a long branch stub if necessary. | |
8172 | ||
8173 | However, we have to be careful when generating PIC code on the | |
8174 | SOM port to ensure that the sequence does not transfer to an | |
8175 | import stub for the target function as this could clobber the | |
8176 | return value saved at SP-24. This would also apply to the | |
8177 | 32-bit linux port if the multi-space model is implemented. */ | |
8178 | if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
8179 | && !(flag_pic && TREE_PUBLIC (function)) | |
8180 | && (TARGET_GAS || last_address < 262132)) | |
8181 | || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
218e3e4e | 8182 | && ((targetm_common.have_named_sections |
2247cc5f | 8183 | && DECL_SECTION_NAME (thunk_fndecl) != NULL |
8184 | /* The GNU 64-bit linker has rather poor stub management. | |
8185 | So, we use a long branch from thunks that aren't in | |
8186 | the same section as the target function. */ | |
8187 | && ((!TARGET_64BIT | |
8188 | && (DECL_SECTION_NAME (thunk_fndecl) | |
8189 | != DECL_SECTION_NAME (function))) | |
8190 | || ((DECL_SECTION_NAME (thunk_fndecl) | |
8191 | == DECL_SECTION_NAME (function)) | |
8192 | && last_address < 262132))) | |
218e3e4e | 8193 | || (targetm_common.have_named_sections |
55e0e460 | 8194 | && DECL_SECTION_NAME (thunk_fndecl) == NULL |
8195 | && DECL_SECTION_NAME (function) == NULL | |
8196 | && last_address < 262132) | |
218e3e4e | 8197 | || (!targetm_common.have_named_sections |
8198 | && last_address < 262132)))) | |
2247cc5f | 8199 | { |
e678758c | 8200 | if (!val_14) |
8201 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8202 | ||
8203 | output_asm_insn ("b %0", xoperands); | |
8204 | ||
2247cc5f | 8205 | if (val_14) |
8206 | { | |
e678758c | 8207 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8208 | nbytes += 8; |
8209 | } | |
8210 | else | |
8211 | { | |
e678758c | 8212 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8213 | nbytes += 12; |
8214 | } | |
8215 | } | |
8216 | else if (TARGET_64BIT) | |
8217 | { | |
8218 | /* We only have one call-clobbered scratch register, so we can't | |
8219 | make use of the delay slot if delta doesn't fit in 14 bits. */ | |
8220 | if (!val_14) | |
e678758c | 8221 | { |
8222 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8223 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); | |
8224 | } | |
2247cc5f | 8225 | |
e678758c | 8226 | output_asm_insn ("b,l .+8,%%r1", xoperands); |
2247cc5f | 8227 | |
8228 | if (TARGET_GAS) | |
8229 | { | |
e678758c | 8230 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
8231 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
2247cc5f | 8232 | } |
8233 | else | |
8234 | { | |
e678758c | 8235 | xoperands[3] = GEN_INT (val_14 ? 8 : 16); |
8236 | output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands); | |
2247cc5f | 8237 | } |
8238 | ||
8239 | if (val_14) | |
8240 | { | |
e678758c | 8241 | output_asm_insn ("bv %%r0(%%r1)", xoperands); |
8242 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); | |
2247cc5f | 8243 | nbytes += 20; |
8244 | } | |
8245 | else | |
8246 | { | |
e678758c | 8247 | output_asm_insn ("bv,n %%r0(%%r1)", xoperands); |
2247cc5f | 8248 | nbytes += 24; |
8249 | } | |
8250 | } | |
8251 | else if (TARGET_PORTABLE_RUNTIME) | |
8252 | { | |
e678758c | 8253 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
8254 | output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands); | |
8255 | ||
8256 | if (!val_14) | |
8257 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8258 | ||
8259 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
2247cc5f | 8260 | |
8261 | if (val_14) | |
8262 | { | |
e678758c | 8263 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8264 | nbytes += 16; |
8265 | } | |
8266 | else | |
8267 | { | |
e678758c | 8268 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8269 | nbytes += 20; |
8270 | } | |
8271 | } | |
8272 | else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
8273 | { | |
8274 | /* The function is accessible from outside this module. The only | |
8275 | way to avoid an import stub between the thunk and function is to | |
8276 | call the function directly with an indirect sequence similar to | |
8277 | that used by $$dyncall. This is possible because $$dyncall acts | |
8278 | as the import stub in an indirect call. */ | |
2247cc5f | 8279 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number); |
e678758c | 8280 | xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label); |
8281 | output_asm_insn ("addil LT'%3,%%r19", xoperands); | |
8282 | output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands); | |
8283 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
8284 | output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands); | |
8285 | output_asm_insn ("depi 0,31,2,%%r22", xoperands); | |
8286 | output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands); | |
8287 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
8288 | ||
2247cc5f | 8289 | if (!val_14) |
8290 | { | |
e678758c | 8291 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
2247cc5f | 8292 | nbytes += 4; |
8293 | } | |
e678758c | 8294 | |
2247cc5f | 8295 | if (TARGET_PA_20) |
8296 | { | |
e678758c | 8297 | output_asm_insn ("bve (%%r22)", xoperands); |
8298 | nbytes += 36; | |
8299 | } | |
8300 | else if (TARGET_NO_SPACE_REGS) | |
8301 | { | |
8302 | output_asm_insn ("be 0(%%sr4,%%r22)", xoperands); | |
2247cc5f | 8303 | nbytes += 36; |
8304 | } | |
8305 | else | |
f1752b7e | 8306 | { |
e678758c | 8307 | output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands); |
8308 | output_asm_insn ("mtsp %%r21,%%sr0", xoperands); | |
8309 | output_asm_insn ("be 0(%%sr0,%%r22)", xoperands); | |
8310 | nbytes += 44; | |
2247cc5f | 8311 | } |
8312 | ||
8313 | if (val_14) | |
e678758c | 8314 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8315 | else |
e678758c | 8316 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8317 | } |
8318 | else if (flag_pic) | |
8319 | { | |
e678758c | 8320 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
2247cc5f | 8321 | |
8322 | if (TARGET_SOM || !TARGET_GAS) | |
8323 | { | |
e678758c | 8324 | output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands); |
8325 | output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands); | |
2247cc5f | 8326 | } |
8327 | else | |
8328 | { | |
e678758c | 8329 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
8330 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands); | |
2247cc5f | 8331 | } |
8332 | ||
e678758c | 8333 | if (!val_14) |
8334 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
8335 | ||
8336 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
8337 | ||
2247cc5f | 8338 | if (val_14) |
8339 | { | |
e678758c | 8340 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8341 | nbytes += 20; |
f1752b7e | 8342 | } |
8343 | else | |
2247cc5f | 8344 | { |
e678758c | 8345 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8346 | nbytes += 24; |
8347 | } | |
f1752b7e | 8348 | } |
8349 | else | |
8350 | { | |
2247cc5f | 8351 | if (!val_14) |
e678758c | 8352 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
2247cc5f | 8353 | |
e678758c | 8354 | output_asm_insn ("ldil L'%0,%%r22", xoperands); |
8355 | output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands); | |
2247cc5f | 8356 | |
8357 | if (val_14) | |
f1752b7e | 8358 | { |
e678758c | 8359 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 8360 | nbytes += 12; |
f1752b7e | 8361 | } |
8362 | else | |
2247cc5f | 8363 | { |
e678758c | 8364 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 8365 | nbytes += 16; |
8366 | } | |
f1752b7e | 8367 | } |
2247cc5f | 8368 | |
f1752b7e | 8369 | fprintf (file, "\t.EXIT\n\t.PROCEND\n"); |
2247cc5f | 8370 | |
78962d38 | 8371 | if (TARGET_SOM && TARGET_GAS) |
8372 | { | |
8373 | /* We done with this subspace except possibly for some additional | |
8374 | debug information. Forget that we are in this subspace to ensure | |
8375 | that the next function is output in its own subspace. */ | |
8376 | in_section = NULL; | |
8377 | cfun->machine->in_nsubspa = 2; | |
8378 | } | |
8379 | ||
2247cc5f | 8380 | if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) |
f1752b7e | 8381 | { |
2f14b1f9 | 8382 | switch_to_section (data_section); |
e678758c | 8383 | output_asm_insn (".align 4", xoperands); |
2247cc5f | 8384 | ASM_OUTPUT_LABEL (file, label); |
e678758c | 8385 | output_asm_insn (".word P'%0", xoperands); |
f1752b7e | 8386 | } |
2247cc5f | 8387 | |
f1752b7e | 8388 | current_thunk_number++; |
2247cc5f | 8389 | nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) |
8390 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
8391 | last_address += nbytes; | |
21a47bc9 | 8392 | if (old_last_address > last_address) |
8393 | last_address = UINT_MAX; | |
2247cc5f | 8394 | update_total_code_bytes (nbytes); |
f1752b7e | 8395 | } |
8396 | ||
805e22b2 | 8397 | /* Only direct calls to static functions are allowed to be sibling (tail) |
8398 | call optimized. | |
8399 | ||
8400 | This restriction is necessary because some linker generated stubs will | |
8401 | store return pointers into rp' in some cases which might clobber a | |
8402 | live value already in rp'. | |
8403 | ||
8404 | In a sibcall the current function and the target function share stack | |
8405 | space. Thus if the path to the current function and the path to the | |
8406 | target function save a value in rp', they save the value into the | |
8407 | same stack slot, which has undesirable consequences. | |
8408 | ||
8409 | Because of the deferred binding nature of shared libraries any function | |
8410 | with external scope could be in a different load module and thus require | |
8411 | rp' to be saved when calling that function. So sibcall optimizations | |
8412 | can only be safe for static function. | |
8413 | ||
8414 | Note that GCC never needs return value relocations, so we don't have to | |
8415 | worry about static calls with return value relocations (which require | |
8416 | saving rp'). | |
8417 | ||
8418 | It is safe to perform a sibcall optimization when the target function | |
8419 | will never return. */ | |
8420 | static bool | |
5c1d8983 | 8421 | pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
805e22b2 | 8422 | { |
e11e9ae3 | 8423 | if (TARGET_PORTABLE_RUNTIME) |
8424 | return false; | |
8425 | ||
f62b73b6 | 8426 | /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in |
8427 | single subspace mode and the call is not indirect. As far as I know, | |
8428 | there is no operating system support for the multiple subspace mode. | |
8429 | It might be possible to support indirect calls if we didn't use | |
8430 | $$dyncall (see the indirect sequence generated in output_call). */ | |
8431 | if (TARGET_ELF32) | |
8432 | return (decl != NULL_TREE); | |
8433 | ||
8434 | /* Sibcalls are not ok because the arg pointer register is not a fixed | |
2cecd772 | 8435 | register. This prevents the sibcall optimization from occurring. In |
f62b73b6 | 8436 | addition, there are problems with stub placement using GNU ld. This |
8437 | is because a normal sibcall branch uses a 17-bit relocation while | |
8438 | a regular call branch uses a 22-bit relocation. As a result, more | |
8439 | care needs to be taken in the placement of long-branch stubs. */ | |
8440 | if (TARGET_64BIT) | |
8441 | return false; | |
8442 | ||
e11e9ae3 | 8443 | /* Sibcalls are only ok within a translation unit. */ |
8444 | return (decl && !TREE_PUBLIC (decl)); | |
805e22b2 | 8445 | } |
8446 | ||
280566a7 | 8447 | /* ??? Addition is not commutative on the PA due to the weird implicit |
8448 | space register selection rules for memory addresses. Therefore, we | |
8449 | don't consider a + b == b + a, as this might be inside a MEM. */ | |
8450 | static bool | |
a9f1838b | 8451 | pa_commutative_p (const_rtx x, int outer_code) |
280566a7 | 8452 | { |
8453 | return (COMMUTATIVE_P (x) | |
55e3fa6d | 8454 | && (TARGET_NO_SPACE_REGS |
8455 | || (outer_code != UNKNOWN && outer_code != MEM) | |
280566a7 | 8456 | || GET_CODE (x) != PLUS)); |
8457 | } | |
8458 | ||
37580c80 | 8459 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
8460 | use in fmpyadd instructions. */ | |
4ed6ee50 | 8461 | int |
5c1d8983 | 8462 | fmpyaddoperands (rtx *operands) |
4ed6ee50 | 8463 | { |
201f01e9 | 8464 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 8465 | |
ab449421 | 8466 | /* Must be a floating point mode. */ |
8467 | if (mode != SFmode && mode != DFmode) | |
8468 | return 0; | |
8469 | ||
4ed6ee50 | 8470 | /* All modes must be the same. */ |
201f01e9 | 8471 | if (! (mode == GET_MODE (operands[1]) |
8472 | && mode == GET_MODE (operands[2]) | |
8473 | && mode == GET_MODE (operands[3]) | |
8474 | && mode == GET_MODE (operands[4]) | |
8475 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 8476 | return 0; |
8477 | ||
ab449421 | 8478 | /* All operands must be registers. */ |
8479 | if (! (GET_CODE (operands[1]) == REG | |
8480 | && GET_CODE (operands[2]) == REG | |
8481 | && GET_CODE (operands[3]) == REG | |
8482 | && GET_CODE (operands[4]) == REG | |
8483 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 8484 | return 0; |
8485 | ||
37580c80 | 8486 | /* Only 2 real operands to the addition. One of the input operands must |
8487 | be the same as the output operand. */ | |
4ed6ee50 | 8488 | if (! rtx_equal_p (operands[3], operands[4]) |
8489 | && ! rtx_equal_p (operands[3], operands[5])) | |
8490 | return 0; | |
8491 | ||
33f88b1c | 8492 | /* Inout operand of add cannot conflict with any operands from multiply. */ |
4ed6ee50 | 8493 | if (rtx_equal_p (operands[3], operands[0]) |
8494 | || rtx_equal_p (operands[3], operands[1]) | |
8495 | || rtx_equal_p (operands[3], operands[2])) | |
8496 | return 0; | |
8497 | ||
33f88b1c | 8498 | /* multiply cannot feed into addition operands. */ |
4ed6ee50 | 8499 | if (rtx_equal_p (operands[4], operands[0]) |
8500 | || rtx_equal_p (operands[5], operands[0])) | |
8501 | return 0; | |
8502 | ||
ab449421 | 8503 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8504 | if (mode == SFmode | |
bac38c40 | 8505 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8506 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8507 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8508 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8509 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8510 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 8511 | return 0; |
8512 | ||
4ed6ee50 | 8513 | /* Passed. Operands are suitable for fmpyadd. */ |
8514 | return 1; | |
8515 | } | |
8516 | ||
de419443 | 8517 | #if !defined(USE_COLLECT2) |
8518 | static void | |
5c1d8983 | 8519 | pa_asm_out_constructor (rtx symbol, int priority) |
de419443 | 8520 | { |
8521 | if (!function_label_operand (symbol, VOIDmode)) | |
8522 | hppa_encode_label (symbol); | |
8523 | ||
8524 | #ifdef CTORS_SECTION_ASM_OP | |
8525 | default_ctor_section_asm_out_constructor (symbol, priority); | |
8526 | #else | |
8527 | # ifdef TARGET_ASM_NAMED_SECTION | |
8528 | default_named_section_asm_out_constructor (symbol, priority); | |
8529 | # else | |
8530 | default_stabs_asm_out_constructor (symbol, priority); | |
8531 | # endif | |
8532 | #endif | |
8533 | } | |
8534 | ||
8535 | static void | |
5c1d8983 | 8536 | pa_asm_out_destructor (rtx symbol, int priority) |
de419443 | 8537 | { |
8538 | if (!function_label_operand (symbol, VOIDmode)) | |
8539 | hppa_encode_label (symbol); | |
8540 | ||
8541 | #ifdef DTORS_SECTION_ASM_OP | |
8542 | default_dtor_section_asm_out_destructor (symbol, priority); | |
8543 | #else | |
8544 | # ifdef TARGET_ASM_NAMED_SECTION | |
8545 | default_named_section_asm_out_destructor (symbol, priority); | |
8546 | # else | |
8547 | default_stabs_asm_out_destructor (symbol, priority); | |
8548 | # endif | |
8549 | #endif | |
8550 | } | |
8551 | #endif | |
8552 | ||
ff59d376 | 8553 | /* This function places uninitialized global data in the bss section. |
8554 | The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this | |
8555 | function on the SOM port to prevent uninitialized global data from | |
8556 | being placed in the data section. */ | |
8557 | ||
8558 | void | |
8559 | pa_asm_output_aligned_bss (FILE *stream, | |
8560 | const char *name, | |
8561 | unsigned HOST_WIDE_INT size, | |
8562 | unsigned int align) | |
8563 | { | |
2f14b1f9 | 8564 | switch_to_section (bss_section); |
ff59d376 | 8565 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); |
8566 | ||
8567 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
8568 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); | |
8569 | #endif | |
8570 | ||
8571 | #ifdef ASM_OUTPUT_SIZE_DIRECTIVE | |
8572 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
8573 | #endif | |
8574 | ||
8575 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); | |
8576 | ASM_OUTPUT_LABEL (stream, name); | |
8577 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
8578 | } | |
8579 | ||
8580 | /* Both the HP and GNU assemblers under HP-UX provide a .comm directive | |
8581 | that doesn't allow the alignment of global common storage to be directly | |
8582 | specified. The SOM linker aligns common storage based on the rounded | |
8583 | value of the NUM_BYTES parameter in the .comm directive. It's not | |
8584 | possible to use the .align directive as it doesn't affect the alignment | |
8585 | of the label associated with a .comm directive. */ | |
8586 | ||
8587 | void | |
8588 | pa_asm_output_aligned_common (FILE *stream, | |
8589 | const char *name, | |
8590 | unsigned HOST_WIDE_INT size, | |
8591 | unsigned int align) | |
8592 | { | |
33cd7888 | 8593 | unsigned int max_common_align; |
8594 | ||
8595 | max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64); | |
8596 | if (align > max_common_align) | |
8597 | { | |
c3ceba8e | 8598 | warning (0, "alignment (%u) for %s exceeds maximum alignment " |
33cd7888 | 8599 | "for global common data. Using %u", |
8600 | align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT); | |
8601 | align = max_common_align; | |
8602 | } | |
8603 | ||
2f14b1f9 | 8604 | switch_to_section (bss_section); |
ff59d376 | 8605 | |
8606 | assemble_name (stream, name); | |
8607 | fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n", | |
8608 | MAX (size, align / BITS_PER_UNIT)); | |
8609 | } | |
8610 | ||
8611 | /* We can't use .comm for local common storage as the SOM linker effectively | |
8612 | treats the symbol as universal and uses the same storage for local symbols | |
8613 | with the same name in different object files. The .block directive | |
8614 | reserves an uninitialized block of storage. However, it's not common | |
8615 | storage. Fortunately, GCC never requests common storage with the same | |
8616 | name in any given translation unit. */ | |
8617 | ||
8618 | void | |
8619 | pa_asm_output_aligned_local (FILE *stream, | |
8620 | const char *name, | |
8621 | unsigned HOST_WIDE_INT size, | |
8622 | unsigned int align) | |
8623 | { | |
2f14b1f9 | 8624 | switch_to_section (bss_section); |
ff59d376 | 8625 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); |
8626 | ||
8627 | #ifdef LOCAL_ASM_OP | |
8628 | fprintf (stream, "%s", LOCAL_ASM_OP); | |
8629 | assemble_name (stream, name); | |
8630 | fprintf (stream, "\n"); | |
8631 | #endif | |
8632 | ||
8633 | ASM_OUTPUT_LABEL (stream, name); | |
8634 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
8635 | } | |
8636 | ||
37580c80 | 8637 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
8638 | use in fmpysub instructions. */ | |
4ed6ee50 | 8639 | int |
5c1d8983 | 8640 | fmpysuboperands (rtx *operands) |
4ed6ee50 | 8641 | { |
201f01e9 | 8642 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 8643 | |
ab449421 | 8644 | /* Must be a floating point mode. */ |
8645 | if (mode != SFmode && mode != DFmode) | |
8646 | return 0; | |
8647 | ||
4ed6ee50 | 8648 | /* All modes must be the same. */ |
201f01e9 | 8649 | if (! (mode == GET_MODE (operands[1]) |
8650 | && mode == GET_MODE (operands[2]) | |
8651 | && mode == GET_MODE (operands[3]) | |
8652 | && mode == GET_MODE (operands[4]) | |
8653 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 8654 | return 0; |
8655 | ||
ab449421 | 8656 | /* All operands must be registers. */ |
8657 | if (! (GET_CODE (operands[1]) == REG | |
8658 | && GET_CODE (operands[2]) == REG | |
8659 | && GET_CODE (operands[3]) == REG | |
8660 | && GET_CODE (operands[4]) == REG | |
8661 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 8662 | return 0; |
8663 | ||
37580c80 | 8664 | /* Only 2 real operands to the subtraction. Subtraction is not a commutative |
8665 | operation, so operands[4] must be the same as operand[3]. */ | |
4ed6ee50 | 8666 | if (! rtx_equal_p (operands[3], operands[4])) |
8667 | return 0; | |
8668 | ||
33f88b1c | 8669 | /* multiply cannot feed into subtraction. */ |
37580c80 | 8670 | if (rtx_equal_p (operands[5], operands[0])) |
4ed6ee50 | 8671 | return 0; |
8672 | ||
33f88b1c | 8673 | /* Inout operand of sub cannot conflict with any operands from multiply. */ |
4ed6ee50 | 8674 | if (rtx_equal_p (operands[3], operands[0]) |
8675 | || rtx_equal_p (operands[3], operands[1]) | |
8676 | || rtx_equal_p (operands[3], operands[2])) | |
8677 | return 0; | |
8678 | ||
ab449421 | 8679 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
8680 | if (mode == SFmode | |
bac38c40 | 8681 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
8682 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
8683 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
8684 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
8685 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
8686 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 8687 | return 0; |
8688 | ||
4ed6ee50 | 8689 | /* Passed. Operands are suitable for fmpysub. */ |
8690 | return 1; | |
8691 | } | |
8692 | ||
6720f95e | 8693 | /* Return 1 if the given constant is 2, 4, or 8. These are the valid |
8694 | constants for shadd instructions. */ | |
913de4b4 | 8695 | int |
5c1d8983 | 8696 | shadd_constant_p (int val) |
6720f95e | 8697 | { |
8698 | if (val == 2 || val == 4 || val == 8) | |
8699 | return 1; | |
8700 | else | |
8701 | return 0; | |
8702 | } | |
3a16146d | 8703 | |
372b3fe2 | 8704 | /* Return TRUE if INSN branches forward. */ |
8705 | ||
8706 | static bool | |
5c1d8983 | 8707 | forward_branch_p (rtx insn) |
5fbd5940 | 8708 | { |
372b3fe2 | 8709 | rtx lab = JUMP_LABEL (insn); |
8710 | ||
8711 | /* The INSN must have a jump label. */ | |
8712 | gcc_assert (lab != NULL_RTX); | |
8713 | ||
8714 | if (INSN_ADDRESSES_SET_P ()) | |
8715 | return INSN_ADDRESSES (INSN_UID (lab)) > INSN_ADDRESSES (INSN_UID (insn)); | |
5fbd5940 | 8716 | |
8717 | while (insn) | |
8718 | { | |
372b3fe2 | 8719 | if (insn == lab) |
8720 | return true; | |
5fbd5940 | 8721 | else |
8722 | insn = NEXT_INSN (insn); | |
8723 | } | |
8724 | ||
372b3fe2 | 8725 | return false; |
5fbd5940 | 8726 | } |
8727 | ||
d6686e21 | 8728 | /* Return 1 if INSN is in the delay slot of a call instruction. */ |
8729 | int | |
5c1d8983 | 8730 | jump_in_call_delay (rtx insn) |
d6686e21 | 8731 | { |
8732 | ||
8733 | if (GET_CODE (insn) != JUMP_INSN) | |
8734 | return 0; | |
8735 | ||
8736 | if (PREV_INSN (insn) | |
8737 | && PREV_INSN (PREV_INSN (insn)) | |
ece0fa59 | 8738 | && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN) |
d6686e21 | 8739 | { |
ece0fa59 | 8740 | rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn))); |
d6686e21 | 8741 | |
8742 | return (GET_CODE (PATTERN (test_insn)) == SEQUENCE | |
8743 | && XVECEXP (PATTERN (test_insn), 0, 1) == insn); | |
8744 | ||
8745 | } | |
8746 | else | |
8747 | return 0; | |
8748 | } | |
3b1e673e | 8749 | |
546a40bd | 8750 | /* Output an unconditional move and branch insn. */ |
8751 | ||
611a88e1 | 8752 | const char * |
f26036bb | 8753 | output_parallel_movb (rtx *operands, rtx insn) |
546a40bd | 8754 | { |
f26036bb | 8755 | int length = get_attr_length (insn); |
8756 | ||
546a40bd | 8757 | /* These are the cases in which we win. */ |
8758 | if (length == 4) | |
8759 | return "mov%I1b,tr %1,%0,%2"; | |
8760 | ||
f26036bb | 8761 | /* None of the following cases win, but they don't lose either. */ |
8762 | if (length == 8) | |
546a40bd | 8763 | { |
f26036bb | 8764 | if (dbr_sequence_length () == 0) |
8765 | { | |
8766 | /* Nothing in the delay slot, fake it by putting the combined | |
8767 | insn (the copy or add) in the delay slot of a bl. */ | |
8768 | if (GET_CODE (operands[1]) == CONST_INT) | |
8769 | return "b %2\n\tldi %1,%0"; | |
8770 | else | |
8771 | return "b %2\n\tcopy %1,%0"; | |
8772 | } | |
546a40bd | 8773 | else |
f26036bb | 8774 | { |
8775 | /* Something in the delay slot, but we've got a long branch. */ | |
8776 | if (GET_CODE (operands[1]) == CONST_INT) | |
8777 | return "ldi %1,%0\n\tb %2"; | |
8778 | else | |
8779 | return "copy %1,%0\n\tb %2"; | |
8780 | } | |
546a40bd | 8781 | } |
f26036bb | 8782 | |
8783 | if (GET_CODE (operands[1]) == CONST_INT) | |
8784 | output_asm_insn ("ldi %1,%0", operands); | |
546a40bd | 8785 | else |
f26036bb | 8786 | output_asm_insn ("copy %1,%0", operands); |
8787 | return output_lbranch (operands[2], insn, 1); | |
546a40bd | 8788 | } |
8789 | ||
8790 | /* Output an unconditional add and branch insn. */ | |
8791 | ||
611a88e1 | 8792 | const char * |
f26036bb | 8793 | output_parallel_addb (rtx *operands, rtx insn) |
546a40bd | 8794 | { |
f26036bb | 8795 | int length = get_attr_length (insn); |
8796 | ||
546a40bd | 8797 | /* To make life easy we want operand0 to be the shared input/output |
8798 | operand and operand1 to be the readonly operand. */ | |
8799 | if (operands[0] == operands[1]) | |
8800 | operands[1] = operands[2]; | |
8801 | ||
8802 | /* These are the cases in which we win. */ | |
8803 | if (length == 4) | |
8804 | return "add%I1b,tr %1,%0,%3"; | |
8805 | ||
f26036bb | 8806 | /* None of the following cases win, but they don't lose either. */ |
8807 | if (length == 8) | |
546a40bd | 8808 | { |
f26036bb | 8809 | if (dbr_sequence_length () == 0) |
8810 | /* Nothing in the delay slot, fake it by putting the combined | |
8811 | insn (the copy or add) in the delay slot of a bl. */ | |
8812 | return "b %3\n\tadd%I1 %1,%0,%0"; | |
8813 | else | |
8814 | /* Something in the delay slot, but we've got a long branch. */ | |
8815 | return "add%I1 %1,%0,%0\n\tb %3"; | |
546a40bd | 8816 | } |
f26036bb | 8817 | |
8818 | output_asm_insn ("add%I1 %1,%0,%0", operands); | |
8819 | return output_lbranch (operands[3], insn, 1); | |
546a40bd | 8820 | } |
8821 | ||
7c5101fc | 8822 | /* Return nonzero if INSN (a jump insn) immediately follows a call |
8823 | to a named function. This is used to avoid filling the delay slot | |
8824 | of the jump since it can usually be eliminated by modifying RP in | |
8825 | the delay slot of the call. */ | |
9840d99d | 8826 | |
7d27e4c9 | 8827 | int |
5c1d8983 | 8828 | following_call (rtx insn) |
546a40bd | 8829 | { |
ed1b0769 | 8830 | if (! TARGET_JUMP_IN_DELAY) |
1b6f11e2 | 8831 | return 0; |
8832 | ||
546a40bd | 8833 | /* Find the previous real insn, skipping NOTEs. */ |
8834 | insn = PREV_INSN (insn); | |
8835 | while (insn && GET_CODE (insn) == NOTE) | |
8836 | insn = PREV_INSN (insn); | |
8837 | ||
8838 | /* Check for CALL_INSNs and millicode calls. */ | |
8839 | if (insn | |
1d2e016c | 8840 | && ((GET_CODE (insn) == CALL_INSN |
8841 | && get_attr_type (insn) != TYPE_DYNCALL) | |
546a40bd | 8842 | || (GET_CODE (insn) == INSN |
8843 | && GET_CODE (PATTERN (insn)) != SEQUENCE | |
8844 | && GET_CODE (PATTERN (insn)) != USE | |
8845 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8846 | && get_attr_type (insn) == TYPE_MILLI))) | |
8847 | return 1; | |
8848 | ||
8849 | return 0; | |
8850 | } | |
8851 | ||
3b1e673e | 8852 | /* We use this hook to perform a PA specific optimization which is difficult |
8853 | to do in earlier passes. | |
8854 | ||
8855 | We want the delay slots of branches within jump tables to be filled. | |
8856 | None of the compiler passes at the moment even has the notion that a | |
8857 | PA jump table doesn't contain addresses, but instead contains actual | |
8858 | instructions! | |
8859 | ||
8860 | Because we actually jump into the table, the addresses of each entry | |
01cc3b75 | 8861 | must stay constant in relation to the beginning of the table (which |
3b1e673e | 8862 | itself must stay constant relative to the instruction to jump into |
8863 | it). I don't believe we can guarantee earlier passes of the compiler | |
8864 | will adhere to those rules. | |
8865 | ||
8866 | So, late in the compilation process we find all the jump tables, and | |
a361b456 | 8867 | expand them into real code -- e.g. each entry in the jump table vector |
3b1e673e | 8868 | will get an appropriate label followed by a jump to the final target. |
8869 | ||
8870 | Reorg and the final jump pass can then optimize these branches and | |
8871 | fill their delay slots. We end up with smaller, more efficient code. | |
8872 | ||
9840d99d | 8873 | The jump instructions within the table are special; we must be able |
3b1e673e | 8874 | to identify them during assembly output (if the jumps don't get filled |
8875 | we need to emit a nop rather than nullifying the delay slot)). We | |
b932f66c | 8876 | identify jumps in switch tables by using insns with the attribute |
8877 | type TYPE_BTABLE_BRANCH. | |
9239127b | 8878 | |
8879 | We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB | |
8880 | insns. This serves two purposes, first it prevents jump.c from | |
8881 | noticing that the last N entries in the table jump to the instruction | |
8882 | immediately after the table and deleting the jumps. Second, those | |
8883 | insns mark where we should emit .begin_brtab and .end_brtab directives | |
8884 | when using GAS (allows for better link time optimizations). */ | |
3b1e673e | 8885 | |
2efea8c0 | 8886 | static void |
5c1d8983 | 8887 | pa_reorg (void) |
3b1e673e | 8888 | { |
8889 | rtx insn; | |
8890 | ||
2efea8c0 | 8891 | remove_useless_addtr_insns (1); |
3d457930 | 8892 | |
342aabd9 | 8893 | if (pa_cpu < PROCESSOR_8000) |
2efea8c0 | 8894 | pa_combine_instructions (); |
342aabd9 | 8895 | |
bd49d362 | 8896 | |
3d457930 | 8897 | /* This is fairly cheap, so always run it if optimizing. */ |
a66555b2 | 8898 | if (optimize > 0 && !TARGET_BIG_SWITCH) |
3b1e673e | 8899 | { |
b41266d4 | 8900 | /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */ |
2efea8c0 | 8901 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
3b1e673e | 8902 | { |
b932f66c | 8903 | rtx pattern, tmp, location, label; |
3b1e673e | 8904 | unsigned int length, i; |
8905 | ||
b41266d4 | 8906 | /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */ |
3b1e673e | 8907 | if (GET_CODE (insn) != JUMP_INSN |
b41266d4 | 8908 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8909 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
3b1e673e | 8910 | continue; |
8911 | ||
9239127b | 8912 | /* Emit marker for the beginning of the branch table. */ |
8913 | emit_insn_before (gen_begin_brtab (), insn); | |
f9333726 | 8914 | |
3b1e673e | 8915 | pattern = PATTERN (insn); |
8916 | location = PREV_INSN (insn); | |
b41266d4 | 8917 | length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC); |
f9333726 | 8918 | |
3b1e673e | 8919 | for (i = 0; i < length; i++) |
8920 | { | |
a66555b2 | 8921 | /* Emit a label before each jump to keep jump.c from |
8922 | removing this code. */ | |
8923 | tmp = gen_label_rtx (); | |
8924 | LABEL_NUSES (tmp) = 1; | |
8925 | emit_label_after (tmp, location); | |
8926 | location = NEXT_INSN (location); | |
8927 | ||
b41266d4 | 8928 | if (GET_CODE (pattern) == ADDR_VEC) |
b932f66c | 8929 | label = XEXP (XVECEXP (pattern, 0, i), 0); |
b41266d4 | 8930 | else |
b932f66c | 8931 | label = XEXP (XVECEXP (pattern, 1, i), 0); |
8932 | ||
8933 | tmp = gen_short_jump (label); | |
8934 | ||
8935 | /* Emit the jump itself. */ | |
8936 | tmp = emit_jump_insn_after (tmp, location); | |
8937 | JUMP_LABEL (tmp) = label; | |
8938 | LABEL_NUSES (label)++; | |
8939 | location = NEXT_INSN (location); | |
3b1e673e | 8940 | |
8941 | /* Emit a BARRIER after the jump. */ | |
3b1e673e | 8942 | emit_barrier_after (location); |
3b1e673e | 8943 | location = NEXT_INSN (location); |
8944 | } | |
f9333726 | 8945 | |
9239127b | 8946 | /* Emit marker for the end of the branch table. */ |
8947 | emit_insn_before (gen_end_brtab (), location); | |
8948 | location = NEXT_INSN (location); | |
8949 | emit_barrier_after (location); | |
a66555b2 | 8950 | |
b41266d4 | 8951 | /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */ |
3b1e673e | 8952 | delete_insn (insn); |
8953 | } | |
8954 | } | |
9239127b | 8955 | else |
f9333726 | 8956 | { |
b932f66c | 8957 | /* Still need brtab marker insns. FIXME: the presence of these |
8958 | markers disables output of the branch table to readonly memory, | |
8959 | and any alignment directives that might be needed. Possibly, | |
8960 | the begin_brtab insn should be output before the label for the | |
7bd28bba | 8961 | table. This doesn't matter at the moment since the tables are |
b932f66c | 8962 | always output in the text section. */ |
2efea8c0 | 8963 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
f9333726 | 8964 | { |
8965 | /* Find an ADDR_VEC insn. */ | |
8966 | if (GET_CODE (insn) != JUMP_INSN | |
b41266d4 | 8967 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8968 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
f9333726 | 8969 | continue; |
8970 | ||
8971 | /* Now generate markers for the beginning and end of the | |
ad87de1e | 8972 | branch table. */ |
f9333726 | 8973 | emit_insn_before (gen_begin_brtab (), insn); |
8974 | emit_insn_after (gen_end_brtab (), insn); | |
8975 | } | |
8976 | } | |
d3287673 | 8977 | } |
bd49d362 | 8978 | |
8979 | /* The PA has a number of odd instructions which can perform multiple | |
8980 | tasks at once. On first generation PA machines (PA1.0 and PA1.1) | |
8981 | it may be profitable to combine two instructions into one instruction | |
8982 | with two outputs. It's not profitable PA2.0 machines because the | |
8983 | two outputs would take two slots in the reorder buffers. | |
8984 | ||
8985 | This routine finds instructions which can be combined and combines | |
8986 | them. We only support some of the potential combinations, and we | |
8987 | only try common ways to find suitable instructions. | |
8988 | ||
8989 | * addb can add two registers or a register and a small integer | |
8990 | and jump to a nearby (+-8k) location. Normally the jump to the | |
8991 | nearby location is conditional on the result of the add, but by | |
8992 | using the "true" condition we can make the jump unconditional. | |
8993 | Thus addb can perform two independent operations in one insn. | |
8994 | ||
8995 | * movb is similar to addb in that it can perform a reg->reg | |
8996 | or small immediate->reg copy and jump to a nearby (+-8k location). | |
8997 | ||
8998 | * fmpyadd and fmpysub can perform a FP multiply and either an | |
8999 | FP add or FP sub if the operands of the multiply and add/sub are | |
9000 | independent (there are other minor restrictions). Note both | |
9001 | the fmpy and fadd/fsub can in theory move to better spots according | |
9002 | to data dependencies, but for now we require the fmpy stay at a | |
9003 | fixed location. | |
9004 | ||
9005 | * Many of the memory operations can perform pre & post updates | |
9006 | of index registers. GCC's pre/post increment/decrement addressing | |
9007 | is far too simple to take advantage of all the possibilities. This | |
9008 | pass may not be suitable since those insns may not be independent. | |
9009 | ||
9010 | * comclr can compare two ints or an int and a register, nullify | |
9011 | the following instruction and zero some other register. This | |
9012 | is more difficult to use as it's harder to find an insn which | |
9013 | will generate a comclr than finding something like an unconditional | |
9014 | branch. (conditional moves & long branches create comclr insns). | |
9015 | ||
9016 | * Most arithmetic operations can conditionally skip the next | |
9017 | instruction. They can be viewed as "perform this operation | |
9018 | and conditionally jump to this nearby location" (where nearby | |
9019 | is an insns away). These are difficult to use due to the | |
9020 | branch length restrictions. */ | |
9021 | ||
7d27e4c9 | 9022 | static void |
5c1d8983 | 9023 | pa_combine_instructions (void) |
bd49d362 | 9024 | { |
8deb3959 | 9025 | rtx anchor, new_rtx; |
bd49d362 | 9026 | |
9027 | /* This can get expensive since the basic algorithm is on the | |
9028 | order of O(n^2) (or worse). Only do it for -O2 or higher | |
ad87de1e | 9029 | levels of optimization. */ |
bd49d362 | 9030 | if (optimize < 2) |
9031 | return; | |
9032 | ||
9033 | /* Walk down the list of insns looking for "anchor" insns which | |
9034 | may be combined with "floating" insns. As the name implies, | |
9035 | "anchor" instructions don't move, while "floating" insns may | |
9036 | move around. */ | |
8deb3959 | 9037 | new_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX)); |
9038 | new_rtx = make_insn_raw (new_rtx); | |
bd49d362 | 9039 | |
9040 | for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor)) | |
9041 | { | |
9042 | enum attr_pa_combine_type anchor_attr; | |
9043 | enum attr_pa_combine_type floater_attr; | |
9044 | ||
9045 | /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs. | |
9046 | Also ignore any special USE insns. */ | |
7d27e4c9 | 9047 | if ((GET_CODE (anchor) != INSN |
bd49d362 | 9048 | && GET_CODE (anchor) != JUMP_INSN |
7d27e4c9 | 9049 | && GET_CODE (anchor) != CALL_INSN) |
bd49d362 | 9050 | || GET_CODE (PATTERN (anchor)) == USE |
9051 | || GET_CODE (PATTERN (anchor)) == CLOBBER | |
9052 | || GET_CODE (PATTERN (anchor)) == ADDR_VEC | |
9053 | || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC) | |
9054 | continue; | |
9055 | ||
9056 | anchor_attr = get_attr_pa_combine_type (anchor); | |
9057 | /* See if anchor is an insn suitable for combination. */ | |
9058 | if (anchor_attr == PA_COMBINE_TYPE_FMPY | |
9059 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9060 | || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
9061 | && ! forward_branch_p (anchor))) | |
9062 | { | |
9063 | rtx floater; | |
9064 | ||
9065 | for (floater = PREV_INSN (anchor); | |
9066 | floater; | |
9067 | floater = PREV_INSN (floater)) | |
9068 | { | |
9069 | if (GET_CODE (floater) == NOTE | |
9070 | || (GET_CODE (floater) == INSN | |
9071 | && (GET_CODE (PATTERN (floater)) == USE | |
9072 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
9073 | continue; | |
9074 | ||
9075 | /* Anything except a regular INSN will stop our search. */ | |
9076 | if (GET_CODE (floater) != INSN | |
9077 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
9078 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
9079 | { | |
9080 | floater = NULL_RTX; | |
9081 | break; | |
9082 | } | |
9083 | ||
9084 | /* See if FLOATER is suitable for combination with the | |
9085 | anchor. */ | |
9086 | floater_attr = get_attr_pa_combine_type (floater); | |
9087 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
9088 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
9089 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9090 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
9091 | { | |
9092 | /* If ANCHOR and FLOATER can be combined, then we're | |
9093 | done with this pass. */ | |
8deb3959 | 9094 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
bd49d362 | 9095 | SET_DEST (PATTERN (floater)), |
9096 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
9097 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
9098 | break; | |
9099 | } | |
9100 | ||
9101 | else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
9102 | && floater_attr == PA_COMBINE_TYPE_ADDMOVE) | |
9103 | { | |
9104 | if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS) | |
9105 | { | |
8deb3959 | 9106 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
bd49d362 | 9107 | SET_DEST (PATTERN (floater)), |
9108 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
9109 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
9110 | break; | |
9111 | } | |
9112 | else | |
9113 | { | |
8deb3959 | 9114 | if (pa_can_combine_p (new_rtx, anchor, floater, 0, |
bd49d362 | 9115 | SET_DEST (PATTERN (floater)), |
9116 | SET_SRC (PATTERN (floater)), | |
9117 | SET_SRC (PATTERN (floater)))) | |
9118 | break; | |
9119 | } | |
9120 | } | |
9121 | } | |
9122 | ||
9123 | /* If we didn't find anything on the backwards scan try forwards. */ | |
9124 | if (!floater | |
9125 | && (anchor_attr == PA_COMBINE_TYPE_FMPY | |
9126 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB)) | |
9127 | { | |
9128 | for (floater = anchor; floater; floater = NEXT_INSN (floater)) | |
9129 | { | |
9130 | if (GET_CODE (floater) == NOTE | |
9131 | || (GET_CODE (floater) == INSN | |
9132 | && (GET_CODE (PATTERN (floater)) == USE | |
9133 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
9840d99d | 9134 | |
bd49d362 | 9135 | continue; |
9136 | ||
9137 | /* Anything except a regular INSN will stop our search. */ | |
9138 | if (GET_CODE (floater) != INSN | |
9139 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
9140 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
9141 | { | |
9142 | floater = NULL_RTX; | |
9143 | break; | |
9144 | } | |
9145 | ||
9146 | /* See if FLOATER is suitable for combination with the | |
9147 | anchor. */ | |
9148 | floater_attr = get_attr_pa_combine_type (floater); | |
9149 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
9150 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
9151 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9152 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
9153 | { | |
9154 | /* If ANCHOR and FLOATER can be combined, then we're | |
9155 | done with this pass. */ | |
8deb3959 | 9156 | if (pa_can_combine_p (new_rtx, anchor, floater, 1, |
bd49d362 | 9157 | SET_DEST (PATTERN (floater)), |
ea52c577 | 9158 | XEXP (SET_SRC (PATTERN (floater)), |
9159 | 0), | |
9160 | XEXP (SET_SRC (PATTERN (floater)), | |
9161 | 1))) | |
bd49d362 | 9162 | break; |
9163 | } | |
9164 | } | |
9165 | } | |
9166 | ||
9167 | /* FLOATER will be nonzero if we found a suitable floating | |
9168 | insn for combination with ANCHOR. */ | |
9169 | if (floater | |
9170 | && (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
9171 | || anchor_attr == PA_COMBINE_TYPE_FMPY)) | |
9172 | { | |
9173 | /* Emit the new instruction and delete the old anchor. */ | |
7014838c | 9174 | emit_insn_before (gen_rtx_PARALLEL |
9175 | (VOIDmode, | |
9176 | gen_rtvec (2, PATTERN (anchor), | |
9177 | PATTERN (floater))), | |
9178 | anchor); | |
9179 | ||
ad4583d9 | 9180 | SET_INSN_DELETED (anchor); |
bd49d362 | 9181 | |
9182 | /* Emit a special USE insn for FLOATER, then delete | |
9183 | the floating insn. */ | |
ad851752 | 9184 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 9185 | delete_insn (floater); |
9186 | ||
9187 | continue; | |
9188 | } | |
9189 | else if (floater | |
9190 | && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH) | |
9191 | { | |
9192 | rtx temp; | |
9193 | /* Emit the new_jump instruction and delete the old anchor. */ | |
7014838c | 9194 | temp |
9195 | = emit_jump_insn_before (gen_rtx_PARALLEL | |
9196 | (VOIDmode, | |
9197 | gen_rtvec (2, PATTERN (anchor), | |
9198 | PATTERN (floater))), | |
9199 | anchor); | |
9200 | ||
bd49d362 | 9201 | JUMP_LABEL (temp) = JUMP_LABEL (anchor); |
ad4583d9 | 9202 | SET_INSN_DELETED (anchor); |
bd49d362 | 9203 | |
9204 | /* Emit a special USE insn for FLOATER, then delete | |
9205 | the floating insn. */ | |
ad851752 | 9206 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 9207 | delete_insn (floater); |
9208 | continue; | |
9209 | } | |
9210 | } | |
9211 | } | |
9212 | } | |
9213 | ||
9aadea62 | 9214 | static int |
8deb3959 | 9215 | pa_can_combine_p (rtx new_rtx, rtx anchor, rtx floater, int reversed, rtx dest, |
5c1d8983 | 9216 | rtx src1, rtx src2) |
bd49d362 | 9217 | { |
9218 | int insn_code_number; | |
9219 | rtx start, end; | |
9220 | ||
9221 | /* Create a PARALLEL with the patterns of ANCHOR and | |
9222 | FLOATER, try to recognize it, then test constraints | |
9223 | for the resulting pattern. | |
9224 | ||
9225 | If the pattern doesn't match or the constraints | |
9226 | aren't met keep searching for a suitable floater | |
9227 | insn. */ | |
8deb3959 | 9228 | XVECEXP (PATTERN (new_rtx), 0, 0) = PATTERN (anchor); |
9229 | XVECEXP (PATTERN (new_rtx), 0, 1) = PATTERN (floater); | |
9230 | INSN_CODE (new_rtx) = -1; | |
9231 | insn_code_number = recog_memoized (new_rtx); | |
bd49d362 | 9232 | if (insn_code_number < 0 |
8deb3959 | 9233 | || (extract_insn (new_rtx), ! constrain_operands (1))) |
bd49d362 | 9234 | return 0; |
9235 | ||
9236 | if (reversed) | |
9237 | { | |
9238 | start = anchor; | |
9239 | end = floater; | |
9240 | } | |
9241 | else | |
9242 | { | |
9243 | start = floater; | |
9244 | end = anchor; | |
9245 | } | |
9246 | ||
9247 | /* There's up to three operands to consider. One | |
9248 | output and two inputs. | |
9249 | ||
9250 | The output must not be used between FLOATER & ANCHOR | |
9251 | exclusive. The inputs must not be set between | |
9252 | FLOATER and ANCHOR exclusive. */ | |
9253 | ||
9254 | if (reg_used_between_p (dest, start, end)) | |
9255 | return 0; | |
9256 | ||
9257 | if (reg_set_between_p (src1, start, end)) | |
9258 | return 0; | |
9259 | ||
9260 | if (reg_set_between_p (src2, start, end)) | |
9261 | return 0; | |
9262 | ||
9263 | /* If we get here, then everything is good. */ | |
9264 | return 1; | |
9265 | } | |
14d18de3 | 9266 | |
a6582a53 | 9267 | /* Return nonzero if references for INSN are delayed. |
14d18de3 | 9268 | |
9269 | Millicode insns are actually function calls with some special | |
9270 | constraints on arguments and register usage. | |
9271 | ||
9272 | Millicode calls always expect their arguments in the integer argument | |
9273 | registers, and always return their result in %r29 (ret1). They | |
2013ddf6 | 9274 | are expected to clobber their arguments, %r1, %r29, and the return |
9275 | pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else. | |
9276 | ||
9277 | This function tells reorg that the references to arguments and | |
9278 | millicode calls do not appear to happen until after the millicode call. | |
9279 | This allows reorg to put insns which set the argument registers into the | |
9280 | delay slot of the millicode call -- thus they act more like traditional | |
9281 | CALL_INSNs. | |
9282 | ||
33f88b1c | 9283 | Note we cannot consider side effects of the insn to be delayed because |
2013ddf6 | 9284 | the branch and link insn will clobber the return pointer. If we happened |
9285 | to use the return pointer in the delay slot of the call, then we lose. | |
14d18de3 | 9286 | |
9287 | get_attr_type will try to recognize the given insn, so make sure to | |
9288 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
9289 | in particular. */ | |
9290 | int | |
5c1d8983 | 9291 | insn_refs_are_delayed (rtx insn) |
14d18de3 | 9292 | { |
9840d99d | 9293 | return ((GET_CODE (insn) == INSN |
14d18de3 | 9294 | && GET_CODE (PATTERN (insn)) != SEQUENCE |
9295 | && GET_CODE (PATTERN (insn)) != USE | |
9296 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
9297 | && get_attr_type (insn) == TYPE_MILLI)); | |
9298 | } | |
5cb4669a | 9299 | |
3b2411a8 | 9300 | /* Promote the return value, but not the arguments. */ |
9301 | ||
a6b21a58 | 9302 | static enum machine_mode |
3b2411a8 | 9303 | pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, |
9304 | enum machine_mode mode, | |
9305 | int *punsignedp ATTRIBUTE_UNUSED, | |
9306 | const_tree fntype ATTRIBUTE_UNUSED, | |
9307 | int for_return) | |
9308 | { | |
c879dbcf | 9309 | if (for_return == 0) |
3b2411a8 | 9310 | return mode; |
a6b21a58 | 9311 | return promote_mode (type, mode, punsignedp); |
3b2411a8 | 9312 | } |
9313 | ||
58a72cce | 9314 | /* On the HP-PA the value is found in register(s) 28(-29), unless |
9315 | the mode is SF or DF. Then the value is returned in fr4 (32). | |
9316 | ||
3b2411a8 | 9317 | This must perform the same promotions as PROMOTE_MODE, else promoting |
9318 | return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly. | |
58a72cce | 9319 | |
9320 | Small structures must be returned in a PARALLEL on PA64 in order | |
9321 | to match the HP Compiler ABI. */ | |
9322 | ||
93d3ee56 | 9323 | static rtx |
cb0b8817 | 9324 | pa_function_value (const_tree valtype, |
9325 | const_tree func ATTRIBUTE_UNUSED, | |
9326 | bool outgoing ATTRIBUTE_UNUSED) | |
58a72cce | 9327 | { |
9328 | enum machine_mode valmode; | |
9329 | ||
4779159e | 9330 | if (AGGREGATE_TYPE_P (valtype) |
9331 | || TREE_CODE (valtype) == COMPLEX_TYPE | |
9332 | || TREE_CODE (valtype) == VECTOR_TYPE) | |
58a72cce | 9333 | { |
b105ef41 | 9334 | if (TARGET_64BIT) |
9335 | { | |
9336 | /* Aggregates with a size less than or equal to 128 bits are | |
9337 | returned in GR 28(-29). They are left justified. The pad | |
9338 | bits are undefined. Larger aggregates are returned in | |
9339 | memory. */ | |
9340 | rtx loc[2]; | |
9341 | int i, offset = 0; | |
9342 | int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2; | |
9343 | ||
9344 | for (i = 0; i < ub; i++) | |
9345 | { | |
9346 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
9347 | gen_rtx_REG (DImode, 28 + i), | |
9348 | GEN_INT (offset)); | |
9349 | offset += 8; | |
9350 | } | |
58a72cce | 9351 | |
b105ef41 | 9352 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc)); |
9353 | } | |
9354 | else if (int_size_in_bytes (valtype) > UNITS_PER_WORD) | |
58a72cce | 9355 | { |
b105ef41 | 9356 | /* Aggregates 5 to 8 bytes in size are returned in general |
9357 | registers r28-r29 in the same manner as other non | |
9358 | floating-point objects. The data is right-justified and | |
9359 | zero-extended to 64 bits. This is opposite to the normal | |
9360 | justification used on big endian targets and requires | |
9361 | special treatment. */ | |
9362 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, | |
9363 | gen_rtx_REG (DImode, 28), const0_rtx); | |
9364 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc)); | |
58a72cce | 9365 | } |
58a72cce | 9366 | } |
9367 | ||
9368 | if ((INTEGRAL_TYPE_P (valtype) | |
eb46b0b6 | 9369 | && GET_MODE_BITSIZE (TYPE_MODE (valtype)) < BITS_PER_WORD) |
58a72cce | 9370 | || POINTER_TYPE_P (valtype)) |
9371 | valmode = word_mode; | |
9372 | else | |
9373 | valmode = TYPE_MODE (valtype); | |
9374 | ||
9375 | if (TREE_CODE (valtype) == REAL_TYPE | |
b105ef41 | 9376 | && !AGGREGATE_TYPE_P (valtype) |
58a72cce | 9377 | && TYPE_MODE (valtype) != TFmode |
9378 | && !TARGET_SOFT_FLOAT) | |
9379 | return gen_rtx_REG (valmode, 32); | |
9380 | ||
9381 | return gen_rtx_REG (valmode, 28); | |
9382 | } | |
9383 | ||
93d3ee56 | 9384 | /* Implement the TARGET_LIBCALL_VALUE hook. */ |
9385 | ||
9386 | static rtx | |
9387 | pa_libcall_value (enum machine_mode mode, | |
9388 | const_rtx fun ATTRIBUTE_UNUSED) | |
9389 | { | |
9390 | if (! TARGET_SOFT_FLOAT | |
9391 | && (mode == SFmode || mode == DFmode)) | |
9392 | return gen_rtx_REG (mode, 32); | |
9393 | else | |
9394 | return gen_rtx_REG (mode, 28); | |
9395 | } | |
9396 | ||
9397 | /* Implement the TARGET_FUNCTION_VALUE_REGNO_P hook. */ | |
9398 | ||
9399 | static bool | |
9400 | pa_function_value_regno_p (const unsigned int regno) | |
9401 | { | |
9402 | if (regno == 28 | |
9403 | || (! TARGET_SOFT_FLOAT && regno == 32)) | |
9404 | return true; | |
9405 | ||
9406 | return false; | |
9407 | } | |
9408 | ||
8b4bd662 | 9409 | /* Update the data in CUM to advance over an argument |
9410 | of mode MODE and data type TYPE. | |
9411 | (TYPE is null for libcalls where that information may not be available.) */ | |
9412 | ||
9413 | static void | |
39cba157 | 9414 | pa_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, |
8b4bd662 | 9415 | const_tree type, bool named ATTRIBUTE_UNUSED) |
9416 | { | |
39cba157 | 9417 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
8b4bd662 | 9418 | int arg_size = FUNCTION_ARG_SIZE (mode, type); |
9419 | ||
9420 | cum->nargs_prototype--; | |
9421 | cum->words += (arg_size | |
9422 | + ((cum->words & 01) | |
9423 | && type != NULL_TREE | |
9424 | && arg_size > 1)); | |
9425 | } | |
9426 | ||
5e3c5739 | 9427 | /* Return the location of a parameter that is passed in a register or NULL |
9428 | if the parameter has any component that is passed in memory. | |
9429 | ||
9430 | This is new code and will be pushed to into the net sources after | |
9840d99d | 9431 | further testing. |
5e3c5739 | 9432 | |
9433 | ??? We might want to restructure this so that it looks more like other | |
9434 | ports. */ | |
8b4bd662 | 9435 | static rtx |
39cba157 | 9436 | pa_function_arg (cumulative_args_t cum_v, enum machine_mode mode, |
8b4bd662 | 9437 | const_tree type, bool named ATTRIBUTE_UNUSED) |
5e3c5739 | 9438 | { |
39cba157 | 9439 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
5e3c5739 | 9440 | int max_arg_words = (TARGET_64BIT ? 8 : 4); |
2a075f91 | 9441 | int alignment = 0; |
ac965869 | 9442 | int arg_size; |
5e3c5739 | 9443 | int fpr_reg_base; |
9444 | int gpr_reg_base; | |
9445 | rtx retval; | |
9446 | ||
ac965869 | 9447 | if (mode == VOIDmode) |
9448 | return NULL_RTX; | |
9449 | ||
9450 | arg_size = FUNCTION_ARG_SIZE (mode, type); | |
9451 | ||
9452 | /* If this arg would be passed partially or totally on the stack, then | |
f054eb3c | 9453 | this routine should return zero. pa_arg_partial_bytes will |
ac965869 | 9454 | handle arguments which are split between regs and stack slots if |
9455 | the ABI mandates split arguments. */ | |
4779159e | 9456 | if (!TARGET_64BIT) |
5e3c5739 | 9457 | { |
ac965869 | 9458 | /* The 32-bit ABI does not split arguments. */ |
9459 | if (cum->words + arg_size > max_arg_words) | |
5e3c5739 | 9460 | return NULL_RTX; |
9461 | } | |
9462 | else | |
9463 | { | |
2a075f91 | 9464 | if (arg_size > 1) |
9465 | alignment = cum->words & 1; | |
ac965869 | 9466 | if (cum->words + alignment >= max_arg_words) |
5e3c5739 | 9467 | return NULL_RTX; |
9468 | } | |
9469 | ||
9470 | /* The 32bit ABIs and the 64bit ABIs are rather different, | |
9471 | particularly in their handling of FP registers. We might | |
9472 | be able to cleverly share code between them, but I'm not | |
9aadea62 | 9473 | going to bother in the hope that splitting them up results |
2a075f91 | 9474 | in code that is more easily understood. */ |
5e3c5739 | 9475 | |
5e3c5739 | 9476 | if (TARGET_64BIT) |
9477 | { | |
9478 | /* Advance the base registers to their current locations. | |
9479 | ||
9480 | Remember, gprs grow towards smaller register numbers while | |
2a075f91 | 9481 | fprs grow to higher register numbers. Also remember that |
9482 | although FP regs are 32-bit addressable, we pretend that | |
9483 | the registers are 64-bits wide. */ | |
5e3c5739 | 9484 | gpr_reg_base = 26 - cum->words; |
9485 | fpr_reg_base = 32 + cum->words; | |
9840d99d | 9486 | |
ac965869 | 9487 | /* Arguments wider than one word and small aggregates need special |
9488 | treatment. */ | |
9489 | if (arg_size > 1 | |
9490 | || mode == BLKmode | |
4779159e | 9491 | || (type && (AGGREGATE_TYPE_P (type) |
9492 | || TREE_CODE (type) == COMPLEX_TYPE | |
9493 | || TREE_CODE (type) == VECTOR_TYPE))) | |
5e3c5739 | 9494 | { |
2a075f91 | 9495 | /* Double-extended precision (80-bit), quad-precision (128-bit) |
9496 | and aggregates including complex numbers are aligned on | |
9497 | 128-bit boundaries. The first eight 64-bit argument slots | |
9498 | are associated one-to-one, with general registers r26 | |
9499 | through r19, and also with floating-point registers fr4 | |
9500 | through fr11. Arguments larger than one word are always | |
ac965869 | 9501 | passed in general registers. |
9502 | ||
9503 | Using a PARALLEL with a word mode register results in left | |
9504 | justified data on a big-endian target. */ | |
2a075f91 | 9505 | |
9506 | rtx loc[8]; | |
9507 | int i, offset = 0, ub = arg_size; | |
9508 | ||
9509 | /* Align the base register. */ | |
9510 | gpr_reg_base -= alignment; | |
9511 | ||
9512 | ub = MIN (ub, max_arg_words - cum->words - alignment); | |
9513 | for (i = 0; i < ub; i++) | |
5e3c5739 | 9514 | { |
2a075f91 | 9515 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, |
9516 | gen_rtx_REG (DImode, gpr_reg_base), | |
9517 | GEN_INT (offset)); | |
9518 | gpr_reg_base -= 1; | |
9519 | offset += 8; | |
5e3c5739 | 9520 | } |
2a075f91 | 9521 | |
e2810de9 | 9522 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc)); |
5e3c5739 | 9523 | } |
ac965869 | 9524 | } |
5e3c5739 | 9525 | else |
9526 | { | |
9527 | /* If the argument is larger than a word, then we know precisely | |
9528 | which registers we must use. */ | |
2a075f91 | 9529 | if (arg_size > 1) |
5e3c5739 | 9530 | { |
9531 | if (cum->words) | |
9532 | { | |
9533 | gpr_reg_base = 23; | |
9534 | fpr_reg_base = 38; | |
9535 | } | |
9536 | else | |
9537 | { | |
9538 | gpr_reg_base = 25; | |
9539 | fpr_reg_base = 34; | |
9540 | } | |
ac965869 | 9541 | |
9542 | /* Structures 5 to 8 bytes in size are passed in the general | |
9543 | registers in the same manner as other non floating-point | |
9544 | objects. The data is right-justified and zero-extended | |
9f0b40a7 | 9545 | to 64 bits. This is opposite to the normal justification |
9546 | used on big endian targets and requires special treatment. | |
4779159e | 9547 | We now define BLOCK_REG_PADDING to pad these objects. |
9548 | Aggregates, complex and vector types are passed in the same | |
9549 | manner as structures. */ | |
9550 | if (mode == BLKmode | |
9551 | || (type && (AGGREGATE_TYPE_P (type) | |
9552 | || TREE_CODE (type) == COMPLEX_TYPE | |
9553 | || TREE_CODE (type) == VECTOR_TYPE))) | |
ac965869 | 9554 | { |
58a72cce | 9555 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, |
9556 | gen_rtx_REG (DImode, gpr_reg_base), | |
9557 | const0_rtx); | |
b105ef41 | 9558 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc)); |
ac965869 | 9559 | } |
5e3c5739 | 9560 | } |
9561 | else | |
9562 | { | |
9563 | /* We have a single word (32 bits). A simple computation | |
9564 | will get us the register #s we need. */ | |
9565 | gpr_reg_base = 26 - cum->words; | |
9566 | fpr_reg_base = 32 + 2 * cum->words; | |
9567 | } | |
9568 | } | |
9569 | ||
9503b0f7 | 9570 | /* Determine if the argument needs to be passed in both general and |
5e3c5739 | 9571 | floating point registers. */ |
9503b0f7 | 9572 | if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32) |
9573 | /* If we are doing soft-float with portable runtime, then there | |
9574 | is no need to worry about FP regs. */ | |
f336e0bc | 9575 | && !TARGET_SOFT_FLOAT |
4779159e | 9576 | /* The parameter must be some kind of scalar float, else we just |
9503b0f7 | 9577 | pass it in integer registers. */ |
4779159e | 9578 | && GET_MODE_CLASS (mode) == MODE_FLOAT |
9503b0f7 | 9579 | /* The target function must not have a prototype. */ |
9580 | && cum->nargs_prototype <= 0 | |
9581 | /* libcalls do not need to pass items in both FP and general | |
9582 | registers. */ | |
9583 | && type != NULL_TREE | |
f336e0bc | 9584 | /* All this hair applies to "outgoing" args only. This includes |
9585 | sibcall arguments setup with FUNCTION_INCOMING_ARG. */ | |
9586 | && !cum->incoming) | |
9503b0f7 | 9587 | /* Also pass outgoing floating arguments in both registers in indirect |
9588 | calls with the 32 bit ABI and the HP assembler since there is no | |
9589 | way to the specify argument locations in static functions. */ | |
f336e0bc | 9590 | || (!TARGET_64BIT |
9591 | && !TARGET_GAS | |
9592 | && !cum->incoming | |
9503b0f7 | 9593 | && cum->indirect |
4779159e | 9594 | && GET_MODE_CLASS (mode) == MODE_FLOAT)) |
5e3c5739 | 9595 | { |
9596 | retval | |
9597 | = gen_rtx_PARALLEL | |
9598 | (mode, | |
9599 | gen_rtvec (2, | |
9600 | gen_rtx_EXPR_LIST (VOIDmode, | |
9601 | gen_rtx_REG (mode, fpr_reg_base), | |
9602 | const0_rtx), | |
9603 | gen_rtx_EXPR_LIST (VOIDmode, | |
9604 | gen_rtx_REG (mode, gpr_reg_base), | |
9605 | const0_rtx))); | |
9606 | } | |
9607 | else | |
9608 | { | |
9609 | /* See if we should pass this parameter in a general register. */ | |
9610 | if (TARGET_SOFT_FLOAT | |
9611 | /* Indirect calls in the normal 32bit ABI require all arguments | |
9612 | to be passed in general registers. */ | |
9613 | || (!TARGET_PORTABLE_RUNTIME | |
9614 | && !TARGET_64BIT | |
a052da6f | 9615 | && !TARGET_ELF32 |
5e3c5739 | 9616 | && cum->indirect) |
4779159e | 9617 | /* If the parameter is not a scalar floating-point parameter, |
9618 | then it belongs in GPRs. */ | |
9619 | || GET_MODE_CLASS (mode) != MODE_FLOAT | |
b105ef41 | 9620 | /* Structure with single SFmode field belongs in GPR. */ |
9621 | || (type && AGGREGATE_TYPE_P (type))) | |
5e3c5739 | 9622 | retval = gen_rtx_REG (mode, gpr_reg_base); |
9623 | else | |
9624 | retval = gen_rtx_REG (mode, fpr_reg_base); | |
9625 | } | |
9626 | return retval; | |
9627 | } | |
9628 | ||
bd99ba64 | 9629 | /* Arguments larger than one word are double word aligned. */ |
9630 | ||
9631 | static unsigned int | |
9632 | pa_function_arg_boundary (enum machine_mode mode, const_tree type) | |
9633 | { | |
bd99ba64 | 9634 | bool singleword = (type |
57a9c540 | 9635 | ? (integer_zerop (TYPE_SIZE (type)) |
9636 | || !TREE_CONSTANT (TYPE_SIZE (type)) | |
bd99ba64 | 9637 | || int_size_in_bytes (type) <= UNITS_PER_WORD) |
23e85af8 | 9638 | : GET_MODE_SIZE (mode) <= UNITS_PER_WORD); |
bd99ba64 | 9639 | |
9640 | return singleword ? PARM_BOUNDARY : MAX_PARM_BOUNDARY; | |
9641 | } | |
5e3c5739 | 9642 | |
9643 | /* If this arg would be passed totally in registers or totally on the stack, | |
f054eb3c | 9644 | then this routine should return zero. */ |
9645 | ||
9646 | static int | |
39cba157 | 9647 | pa_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode, |
f054eb3c | 9648 | tree type, bool named ATTRIBUTE_UNUSED) |
5e3c5739 | 9649 | { |
39cba157 | 9650 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
b7d86581 | 9651 | unsigned int max_arg_words = 8; |
9652 | unsigned int offset = 0; | |
5e3c5739 | 9653 | |
f054eb3c | 9654 | if (!TARGET_64BIT) |
9655 | return 0; | |
9656 | ||
b7d86581 | 9657 | if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1)) |
5e3c5739 | 9658 | offset = 1; |
9659 | ||
b7d86581 | 9660 | if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words) |
6dc3b0d9 | 9661 | /* Arg fits fully into registers. */ |
5e3c5739 | 9662 | return 0; |
9840d99d | 9663 | else if (cum->words + offset >= max_arg_words) |
6dc3b0d9 | 9664 | /* Arg fully on the stack. */ |
5e3c5739 | 9665 | return 0; |
9666 | else | |
6dc3b0d9 | 9667 | /* Arg is split. */ |
f054eb3c | 9668 | return (max_arg_words - cum->words - offset) * UNITS_PER_WORD; |
5e3c5739 | 9669 | } |
9670 | ||
9671 | ||
2f14b1f9 | 9672 | /* A get_unnamed_section callback for switching to the text section. |
916c9cef | 9673 | |
9674 | This function is only used with SOM. Because we don't support | |
9675 | named subspaces, we can only create a new subspace or switch back | |
99c11254 | 9676 | to the default text subspace. */ |
99c11254 | 9677 | |
2f14b1f9 | 9678 | static void |
9679 | som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED) | |
9680 | { | |
9681 | gcc_assert (TARGET_SOM); | |
99c11254 | 9682 | if (TARGET_GAS) |
916c9cef | 9683 | { |
9f4a0384 | 9684 | if (cfun && cfun->machine && !cfun->machine->in_nsubspa) |
916c9cef | 9685 | { |
9686 | /* We only want to emit a .nsubspa directive once at the | |
9687 | start of the function. */ | |
9688 | cfun->machine->in_nsubspa = 1; | |
9689 | ||
9690 | /* Create a new subspace for the text. This provides | |
9691 | better stub placement and one-only functions. */ | |
9692 | if (cfun->decl | |
9693 | && DECL_ONE_ONLY (cfun->decl) | |
9694 | && !DECL_WEAK (cfun->decl)) | |
78962d38 | 9695 | { |
9696 | output_section_asm_op ("\t.SPACE $TEXT$\n" | |
9697 | "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8," | |
9698 | "ACCESS=44,SORT=24,COMDAT"); | |
9699 | return; | |
9700 | } | |
916c9cef | 9701 | } |
9702 | else | |
9703 | { | |
9704 | /* There isn't a current function or the body of the current | |
9705 | function has been completed. So, we are changing to the | |
78962d38 | 9706 | text section to output debugging information. Thus, we |
9707 | need to forget that we are in the text section so that | |
9708 | varasm.c will call us when text_section is selected again. */ | |
9f4a0384 | 9709 | gcc_assert (!cfun || !cfun->machine |
9710 | || cfun->machine->in_nsubspa == 2); | |
2f14b1f9 | 9711 | in_section = NULL; |
916c9cef | 9712 | } |
78962d38 | 9713 | output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$"); |
9714 | return; | |
916c9cef | 9715 | } |
2f14b1f9 | 9716 | output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$"); |
9717 | } | |
9718 | ||
78962d38 | 9719 | /* A get_unnamed_section callback for switching to comdat data |
9720 | sections. This function is only used with SOM. */ | |
9721 | ||
9722 | static void | |
9723 | som_output_comdat_data_section_asm_op (const void *data) | |
9724 | { | |
9725 | in_section = NULL; | |
9726 | output_section_asm_op (data); | |
9727 | } | |
9728 | ||
2f14b1f9 | 9729 | /* Implement TARGET_ASM_INITIALIZE_SECTIONS */ |
916c9cef | 9730 | |
2f14b1f9 | 9731 | static void |
9732 | pa_som_asm_init_sections (void) | |
9733 | { | |
9734 | text_section | |
9735 | = get_unnamed_section (0, som_output_text_section_asm_op, NULL); | |
9736 | ||
9737 | /* SOM puts readonly data in the default $LIT$ subspace when PIC code | |
9738 | is not being generated. */ | |
9739 | som_readonly_data_section | |
9740 | = get_unnamed_section (0, output_section_asm_op, | |
9741 | "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$"); | |
9742 | ||
9743 | /* When secondary definitions are not supported, SOM makes readonly | |
9744 | data one-only by creating a new $LIT$ subspace in $TEXT$ with | |
9745 | the comdat flag. */ | |
9746 | som_one_only_readonly_data_section | |
78962d38 | 9747 | = get_unnamed_section (0, som_output_comdat_data_section_asm_op, |
2f14b1f9 | 9748 | "\t.SPACE $TEXT$\n" |
9749 | "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8," | |
9750 | "ACCESS=0x2c,SORT=16,COMDAT"); | |
9751 | ||
9752 | ||
9753 | /* When secondary definitions are not supported, SOM makes data one-only | |
9754 | by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */ | |
9755 | som_one_only_data_section | |
78962d38 | 9756 | = get_unnamed_section (SECTION_WRITE, |
9757 | som_output_comdat_data_section_asm_op, | |
2f14b1f9 | 9758 | "\t.SPACE $PRIVATE$\n" |
9759 | "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8," | |
9760 | "ACCESS=31,SORT=24,COMDAT"); | |
9761 | ||
9762 | /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups | |
9763 | which reference data within the $TEXT$ space (for example constant | |
9764 | strings in the $LIT$ subspace). | |
9765 | ||
9766 | The assemblers (GAS and HP as) both have problems with handling | |
9767 | the difference of two symbols which is the other correct way to | |
9768 | reference constant data during PIC code generation. | |
9769 | ||
9770 | So, there's no way to reference constant data which is in the | |
9771 | $TEXT$ space during PIC generation. Instead place all constant | |
9772 | data into the $PRIVATE$ subspace (this reduces sharing, but it | |
9773 | works correctly). */ | |
9774 | readonly_data_section = flag_pic ? data_section : som_readonly_data_section; | |
9775 | ||
9776 | /* We must not have a reference to an external symbol defined in a | |
9777 | shared library in a readonly section, else the SOM linker will | |
9778 | complain. | |
9779 | ||
9780 | So, we force exception information into the data section. */ | |
9781 | exception_section = data_section; | |
916c9cef | 9782 | } |
9783 | ||
52470889 | 9784 | /* On hpux10, the linker will give an error if we have a reference |
9785 | in the read-only data section to a symbol defined in a shared | |
9786 | library. Therefore, expressions that might require a reloc can | |
9787 | not be placed in the read-only data section. */ | |
9788 | ||
2f14b1f9 | 9789 | static section * |
b572d1a5 | 9790 | pa_select_section (tree exp, int reloc, |
9791 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
52470889 | 9792 | { |
9793 | if (TREE_CODE (exp) == VAR_DECL | |
9794 | && TREE_READONLY (exp) | |
9795 | && !TREE_THIS_VOLATILE (exp) | |
9796 | && DECL_INITIAL (exp) | |
9797 | && (DECL_INITIAL (exp) == error_mark_node | |
9798 | || TREE_CONSTANT (DECL_INITIAL (exp))) | |
9799 | && !reloc) | |
916c9cef | 9800 | { |
9801 | if (TARGET_SOM | |
9802 | && DECL_ONE_ONLY (exp) | |
9803 | && !DECL_WEAK (exp)) | |
2f14b1f9 | 9804 | return som_one_only_readonly_data_section; |
916c9cef | 9805 | else |
2f14b1f9 | 9806 | return readonly_data_section; |
916c9cef | 9807 | } |
ce45a448 | 9808 | else if (CONSTANT_CLASS_P (exp) && !reloc) |
2f14b1f9 | 9809 | return readonly_data_section; |
916c9cef | 9810 | else if (TARGET_SOM |
9811 | && TREE_CODE (exp) == VAR_DECL | |
9812 | && DECL_ONE_ONLY (exp) | |
2455c36b | 9813 | && !DECL_WEAK (exp)) |
2f14b1f9 | 9814 | return som_one_only_data_section; |
52470889 | 9815 | else |
2f14b1f9 | 9816 | return data_section; |
52470889 | 9817 | } |
1f3233d1 | 9818 | |
67c1e638 | 9819 | static void |
5c1d8983 | 9820 | pa_globalize_label (FILE *stream, const char *name) |
67c1e638 | 9821 | { |
9822 | /* We only handle DATA objects here, functions are globalized in | |
9823 | ASM_DECLARE_FUNCTION_NAME. */ | |
9824 | if (! FUNCTION_NAME_P (name)) | |
9825 | { | |
9826 | fputs ("\t.EXPORT ", stream); | |
9827 | assemble_name (stream, name); | |
9828 | fputs (",DATA\n", stream); | |
9829 | } | |
9830 | } | |
b8debbe8 | 9831 | |
6644435d | 9832 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
9833 | ||
b8debbe8 | 9834 | static rtx |
9835 | pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
9836 | int incoming ATTRIBUTE_UNUSED) | |
9837 | { | |
9838 | return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM); | |
9839 | } | |
9840 | ||
6644435d | 9841 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
9842 | ||
b8debbe8 | 9843 | bool |
fb80456a | 9844 | pa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) |
b8debbe8 | 9845 | { |
9846 | /* SOM ABI says that objects larger than 64 bits are returned in memory. | |
9847 | PA64 ABI says that objects larger than 128 bits are returned in memory. | |
9848 | Note, int_size_in_bytes can return -1 if the size of the object is | |
9849 | variable or larger than the maximum value that can be expressed as | |
9850 | a HOST_WIDE_INT. It can also return zero for an empty type. The | |
9851 | simplest way to handle variable and empty types is to pass them in | |
9852 | memory. This avoids problems in defining the boundaries of argument | |
9853 | slots, allocating registers, etc. */ | |
9854 | return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8) | |
9855 | || int_size_in_bytes (type) <= 0); | |
9856 | } | |
9857 | ||
5f43b4f6 | 9858 | /* Structure to hold declaration and name of external symbols that are |
9859 | emitted by GCC. We generate a vector of these symbols and output them | |
9860 | at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true. | |
9861 | This avoids putting out names that are never really used. */ | |
9862 | ||
fb1e4f4a | 9863 | typedef struct GTY(()) extern_symbol |
5f43b4f6 | 9864 | { |
9865 | tree decl; | |
9866 | const char *name; | |
046bfc77 | 9867 | } extern_symbol; |
5f43b4f6 | 9868 | |
9869 | /* Define gc'd vector type for extern_symbol. */ | |
046bfc77 | 9870 | DEF_VEC_O(extern_symbol); |
9871 | DEF_VEC_ALLOC_O(extern_symbol,gc); | |
5f43b4f6 | 9872 | |
9873 | /* Vector of extern_symbol pointers. */ | |
046bfc77 | 9874 | static GTY(()) VEC(extern_symbol,gc) *extern_symbols; |
5f43b4f6 | 9875 | |
9876 | #ifdef ASM_OUTPUT_EXTERNAL_REAL | |
9877 | /* Mark DECL (name NAME) as an external reference (assembler output | |
9878 | file FILE). This saves the names to output at the end of the file | |
9879 | if actually referenced. */ | |
9880 | ||
9881 | void | |
9882 | pa_hpux_asm_output_external (FILE *file, tree decl, const char *name) | |
9883 | { | |
046bfc77 | 9884 | extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL); |
5f43b4f6 | 9885 | |
9886 | gcc_assert (file == asm_out_file); | |
9887 | p->decl = decl; | |
9888 | p->name = name; | |
5f43b4f6 | 9889 | } |
9890 | ||
9891 | /* Output text required at the end of an assembler file. | |
9892 | This includes deferred plabels and .import directives for | |
9893 | all external symbols that were actually referenced. */ | |
9894 | ||
9895 | static void | |
9896 | pa_hpux_file_end (void) | |
9897 | { | |
9898 | unsigned int i; | |
046bfc77 | 9899 | extern_symbol *p; |
5f43b4f6 | 9900 | |
bb1bc2ca | 9901 | if (!NO_DEFERRED_PROFILE_COUNTERS) |
9902 | output_deferred_profile_counters (); | |
9903 | ||
5f43b4f6 | 9904 | output_deferred_plabels (); |
9905 | ||
9906 | for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++) | |
9907 | { | |
9908 | tree decl = p->decl; | |
9909 | ||
9910 | if (!TREE_ASM_WRITTEN (decl) | |
9911 | && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0))) | |
9912 | ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name); | |
9913 | } | |
9914 | ||
046bfc77 | 9915 | VEC_free (extern_symbol, gc, extern_symbols); |
5f43b4f6 | 9916 | } |
9917 | #endif | |
9918 | ||
7050ff73 | 9919 | /* Return true if a change from mode FROM to mode TO for a register |
8deb3959 | 9920 | in register class RCLASS is invalid. */ |
7050ff73 | 9921 | |
9922 | bool | |
9923 | pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to, | |
8deb3959 | 9924 | enum reg_class rclass) |
7050ff73 | 9925 | { |
9926 | if (from == to) | |
9927 | return false; | |
9928 | ||
9929 | /* Reject changes to/from complex and vector modes. */ | |
9930 | if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from) | |
9931 | || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to)) | |
9932 | return true; | |
9933 | ||
9934 | if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to)) | |
9935 | return false; | |
9936 | ||
9937 | /* There is no way to load QImode or HImode values directly from | |
9938 | memory. SImode loads to the FP registers are not zero extended. | |
9939 | On the 64-bit target, this conflicts with the definition of | |
9940 | LOAD_EXTEND_OP. Thus, we can't allow changing between modes | |
9941 | with different sizes in the floating-point registers. */ | |
8deb3959 | 9942 | if (MAYBE_FP_REG_CLASS_P (rclass)) |
7050ff73 | 9943 | return true; |
9944 | ||
9945 | /* HARD_REGNO_MODE_OK places modes with sizes larger than a word | |
9946 | in specific sets of registers. Thus, we cannot allow changing | |
9947 | to a larger mode when it's larger than a word. */ | |
9948 | if (GET_MODE_SIZE (to) > UNITS_PER_WORD | |
9949 | && GET_MODE_SIZE (to) > GET_MODE_SIZE (from)) | |
9950 | return true; | |
9951 | ||
9952 | return false; | |
9953 | } | |
9954 | ||
9955 | /* Returns TRUE if it is a good idea to tie two pseudo registers | |
9956 | when one has mode MODE1 and one has mode MODE2. | |
9957 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
9958 | for any hard reg, then this must be FALSE for correct output. | |
9959 | ||
9960 | We should return FALSE for QImode and HImode because these modes | |
9961 | are not ok in the floating-point registers. However, this prevents | |
9962 | tieing these modes to SImode and DImode in the general registers. | |
9963 | So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and | |
9964 | CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used | |
9965 | in the floating-point registers. */ | |
9966 | ||
9967 | bool | |
9968 | pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) | |
9969 | { | |
9970 | /* Don't tie modes in different classes. */ | |
9971 | if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2)) | |
9972 | return false; | |
9973 | ||
9974 | return true; | |
9975 | } | |
9976 | ||
623a97bc | 9977 | \f |
9978 | /* Length in units of the trampoline instruction code. */ | |
9979 | ||
9980 | #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40)) | |
9981 | ||
9982 | ||
9983 | /* Output assembler code for a block containing the constant parts | |
9984 | of a trampoline, leaving space for the variable parts.\ | |
9985 | ||
9986 | The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM | |
9987 | and then branches to the specified routine. | |
9988 | ||
9989 | This code template is copied from text segment to stack location | |
9990 | and then patched with pa_trampoline_init to contain valid values, | |
9991 | and then entered as a subroutine. | |
9992 | ||
9993 | It is best to keep this as small as possible to avoid having to | |
9994 | flush multiple lines in the cache. */ | |
9995 | ||
9996 | static void | |
9997 | pa_asm_trampoline_template (FILE *f) | |
9998 | { | |
9999 | if (!TARGET_64BIT) | |
10000 | { | |
10001 | fputs ("\tldw 36(%r22),%r21\n", f); | |
10002 | fputs ("\tbb,>=,n %r21,30,.+16\n", f); | |
10003 | if (ASSEMBLER_DIALECT == 0) | |
10004 | fputs ("\tdepi 0,31,2,%r21\n", f); | |
10005 | else | |
10006 | fputs ("\tdepwi 0,31,2,%r21\n", f); | |
10007 | fputs ("\tldw 4(%r21),%r19\n", f); | |
10008 | fputs ("\tldw 0(%r21),%r21\n", f); | |
10009 | if (TARGET_PA_20) | |
10010 | { | |
10011 | fputs ("\tbve (%r21)\n", f); | |
10012 | fputs ("\tldw 40(%r22),%r29\n", f); | |
10013 | fputs ("\t.word 0\n", f); | |
10014 | fputs ("\t.word 0\n", f); | |
10015 | } | |
10016 | else | |
10017 | { | |
10018 | fputs ("\tldsid (%r21),%r1\n", f); | |
10019 | fputs ("\tmtsp %r1,%sr0\n", f); | |
10020 | fputs ("\tbe 0(%sr0,%r21)\n", f); | |
10021 | fputs ("\tldw 40(%r22),%r29\n", f); | |
10022 | } | |
10023 | fputs ("\t.word 0\n", f); | |
10024 | fputs ("\t.word 0\n", f); | |
10025 | fputs ("\t.word 0\n", f); | |
10026 | fputs ("\t.word 0\n", f); | |
10027 | } | |
10028 | else | |
10029 | { | |
10030 | fputs ("\t.dword 0\n", f); | |
10031 | fputs ("\t.dword 0\n", f); | |
10032 | fputs ("\t.dword 0\n", f); | |
10033 | fputs ("\t.dword 0\n", f); | |
10034 | fputs ("\tmfia %r31\n", f); | |
10035 | fputs ("\tldd 24(%r31),%r1\n", f); | |
10036 | fputs ("\tldd 24(%r1),%r27\n", f); | |
10037 | fputs ("\tldd 16(%r1),%r1\n", f); | |
10038 | fputs ("\tbve (%r1)\n", f); | |
10039 | fputs ("\tldd 32(%r31),%r31\n", f); | |
10040 | fputs ("\t.dword 0 ; fptr\n", f); | |
10041 | fputs ("\t.dword 0 ; static link\n", f); | |
10042 | } | |
10043 | } | |
10044 | ||
10045 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
10046 | FNADDR is an RTX for the address of the function's pure code. | |
10047 | CXT is an RTX for the static chain value for the function. | |
10048 | ||
10049 | Move the function address to the trampoline template at offset 36. | |
10050 | Move the static chain value to trampoline template at offset 40. | |
10051 | Move the trampoline address to trampoline template at offset 44. | |
10052 | Move r19 to trampoline template at offset 48. The latter two | |
10053 | words create a plabel for the indirect call to the trampoline. | |
10054 | ||
10055 | A similar sequence is used for the 64-bit port but the plabel is | |
10056 | at the beginning of the trampoline. | |
10057 | ||
10058 | Finally, the cache entries for the trampoline code are flushed. | |
10059 | This is necessary to ensure that the trampoline instruction sequence | |
10060 | is written to memory prior to any attempts at prefetching the code | |
10061 | sequence. */ | |
10062 | ||
10063 | static void | |
10064 | pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
10065 | { | |
10066 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); | |
10067 | rtx start_addr = gen_reg_rtx (Pmode); | |
10068 | rtx end_addr = gen_reg_rtx (Pmode); | |
10069 | rtx line_length = gen_reg_rtx (Pmode); | |
10070 | rtx r_tramp, tmp; | |
10071 | ||
10072 | emit_block_move (m_tramp, assemble_trampoline_template (), | |
10073 | GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); | |
10074 | r_tramp = force_reg (Pmode, XEXP (m_tramp, 0)); | |
10075 | ||
10076 | if (!TARGET_64BIT) | |
10077 | { | |
10078 | tmp = adjust_address (m_tramp, Pmode, 36); | |
10079 | emit_move_insn (tmp, fnaddr); | |
10080 | tmp = adjust_address (m_tramp, Pmode, 40); | |
10081 | emit_move_insn (tmp, chain_value); | |
10082 | ||
10083 | /* Create a fat pointer for the trampoline. */ | |
10084 | tmp = adjust_address (m_tramp, Pmode, 44); | |
10085 | emit_move_insn (tmp, r_tramp); | |
10086 | tmp = adjust_address (m_tramp, Pmode, 48); | |
10087 | emit_move_insn (tmp, gen_rtx_REG (Pmode, 19)); | |
10088 | ||
10089 | /* fdc and fic only use registers for the address to flush, | |
10090 | they do not accept integer displacements. We align the | |
10091 | start and end addresses to the beginning of their respective | |
10092 | cache lines to minimize the number of lines flushed. */ | |
10093 | emit_insn (gen_andsi3 (start_addr, r_tramp, | |
10094 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
10095 | tmp = force_reg (Pmode, plus_constant (r_tramp, TRAMPOLINE_CODE_SIZE-1)); | |
10096 | emit_insn (gen_andsi3 (end_addr, tmp, | |
10097 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
10098 | emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); | |
10099 | emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length)); | |
10100 | emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length, | |
10101 | gen_reg_rtx (Pmode), | |
10102 | gen_reg_rtx (Pmode))); | |
10103 | } | |
10104 | else | |
10105 | { | |
10106 | tmp = adjust_address (m_tramp, Pmode, 56); | |
10107 | emit_move_insn (tmp, fnaddr); | |
10108 | tmp = adjust_address (m_tramp, Pmode, 64); | |
10109 | emit_move_insn (tmp, chain_value); | |
10110 | ||
10111 | /* Create a fat pointer for the trampoline. */ | |
10112 | tmp = adjust_address (m_tramp, Pmode, 16); | |
10113 | emit_move_insn (tmp, force_reg (Pmode, plus_constant (r_tramp, 32))); | |
10114 | tmp = adjust_address (m_tramp, Pmode, 24); | |
10115 | emit_move_insn (tmp, gen_rtx_REG (Pmode, 27)); | |
10116 | ||
10117 | /* fdc and fic only use registers for the address to flush, | |
10118 | they do not accept integer displacements. We align the | |
10119 | start and end addresses to the beginning of their respective | |
10120 | cache lines to minimize the number of lines flushed. */ | |
10121 | tmp = force_reg (Pmode, plus_constant (r_tramp, 32)); | |
10122 | emit_insn (gen_anddi3 (start_addr, tmp, | |
10123 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
10124 | tmp = force_reg (Pmode, plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); | |
10125 | emit_insn (gen_anddi3 (end_addr, tmp, | |
10126 | GEN_INT (-MIN_CACHELINE_SIZE))); | |
10127 | emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); | |
10128 | emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length)); | |
10129 | emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length, | |
10130 | gen_reg_rtx (Pmode), | |
10131 | gen_reg_rtx (Pmode))); | |
10132 | } | |
10133 | } | |
10134 | ||
10135 | /* Perform any machine-specific adjustment in the address of the trampoline. | |
10136 | ADDR contains the address that was passed to pa_trampoline_init. | |
10137 | Adjust the trampoline address to point to the plabel at offset 44. */ | |
10138 | ||
10139 | static rtx | |
10140 | pa_trampoline_adjust_address (rtx addr) | |
10141 | { | |
10142 | if (!TARGET_64BIT) | |
10143 | addr = memory_address (Pmode, plus_constant (addr, 46)); | |
10144 | return addr; | |
10145 | } | |
c731c4f5 | 10146 | |
10147 | static rtx | |
10148 | pa_delegitimize_address (rtx orig_x) | |
10149 | { | |
10150 | rtx x = delegitimize_mem_from_attrs (orig_x); | |
10151 | ||
10152 | if (GET_CODE (x) == LO_SUM | |
10153 | && GET_CODE (XEXP (x, 1)) == UNSPEC | |
10154 | && XINT (XEXP (x, 1), 1) == UNSPEC_DLTIND14R) | |
10155 | return gen_const_mem (Pmode, XVECEXP (XEXP (x, 1), 0, 0)); | |
10156 | return x; | |
10157 | } | |
623a97bc | 10158 | \f |
68bc9ae6 | 10159 | static rtx |
10160 | pa_internal_arg_pointer (void) | |
10161 | { | |
10162 | /* The argument pointer and the hard frame pointer are the same in | |
10163 | the 32-bit runtime, so we don't need a copy. */ | |
10164 | if (TARGET_64BIT) | |
10165 | return copy_to_reg (virtual_incoming_args_rtx); | |
10166 | else | |
10167 | return virtual_incoming_args_rtx; | |
10168 | } | |
10169 | ||
10170 | /* Given FROM and TO register numbers, say whether this elimination is allowed. | |
10171 | Frame pointer elimination is automatically handled. */ | |
10172 | ||
10173 | static bool | |
10174 | pa_can_eliminate (const int from, const int to) | |
10175 | { | |
10176 | /* The argument cannot be eliminated in the 64-bit runtime. */ | |
10177 | if (TARGET_64BIT && from == ARG_POINTER_REGNUM) | |
10178 | return false; | |
10179 | ||
10180 | return (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM | |
10181 | ? ! frame_pointer_needed | |
10182 | : true); | |
10183 | } | |
10184 | ||
10185 | /* Define the offset between two registers, FROM to be eliminated and its | |
10186 | replacement TO, at the start of a routine. */ | |
10187 | HOST_WIDE_INT | |
10188 | pa_initial_elimination_offset (int from, int to) | |
10189 | { | |
10190 | HOST_WIDE_INT offset; | |
10191 | ||
10192 | if ((from == HARD_FRAME_POINTER_REGNUM || from == FRAME_POINTER_REGNUM) | |
10193 | && to == STACK_POINTER_REGNUM) | |
10194 | offset = -compute_frame_size (get_frame_size (), 0); | |
10195 | else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) | |
10196 | offset = 0; | |
10197 | else | |
10198 | gcc_unreachable (); | |
10199 | ||
10200 | return offset; | |
10201 | } | |
10202 | ||
b2d7ede1 | 10203 | static void |
10204 | pa_conditional_register_usage (void) | |
10205 | { | |
10206 | int i; | |
10207 | ||
10208 | if (!TARGET_64BIT && !TARGET_PA_11) | |
10209 | { | |
10210 | for (i = 56; i <= FP_REG_LAST; i++) | |
10211 | fixed_regs[i] = call_used_regs[i] = 1; | |
10212 | for (i = 33; i < 56; i += 2) | |
10213 | fixed_regs[i] = call_used_regs[i] = 1; | |
10214 | } | |
10215 | if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT) | |
10216 | { | |
10217 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
10218 | fixed_regs[i] = call_used_regs[i] = 1; | |
10219 | } | |
10220 | if (flag_pic) | |
10221 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
10222 | } | |
10223 | ||
0f9c87cc | 10224 | /* Target hook for c_mode_for_suffix. */ |
10225 | ||
10226 | static enum machine_mode | |
10227 | pa_c_mode_for_suffix (char suffix) | |
10228 | { | |
10229 | if (HPUX_LONG_DOUBLE_LIBRARY) | |
10230 | { | |
10231 | if (suffix == 'q') | |
10232 | return TFmode; | |
10233 | } | |
10234 | ||
10235 | return VOIDmode; | |
10236 | } | |
10237 | ||
c9b4a514 | 10238 | /* Target hook for function_section. */ |
10239 | ||
10240 | static section * | |
10241 | pa_function_section (tree decl, enum node_frequency freq, | |
10242 | bool startup, bool exit) | |
10243 | { | |
10244 | /* Put functions in text section if target doesn't have named sections. */ | |
218e3e4e | 10245 | if (!targetm_common.have_named_sections) |
c9b4a514 | 10246 | return text_section; |
10247 | ||
10248 | /* Force nested functions into the same section as the containing | |
10249 | function. */ | |
10250 | if (decl | |
10251 | && DECL_SECTION_NAME (decl) == NULL_TREE | |
10252 | && DECL_CONTEXT (decl) != NULL_TREE | |
10253 | && TREE_CODE (DECL_CONTEXT (decl)) == FUNCTION_DECL | |
10254 | && DECL_SECTION_NAME (DECL_CONTEXT (decl)) == NULL_TREE) | |
10255 | return function_section (DECL_CONTEXT (decl)); | |
10256 | ||
10257 | /* Otherwise, use the default function section. */ | |
10258 | return default_function_section (decl, freq, startup, exit); | |
10259 | } | |
10260 | ||
ca316360 | 10261 | /* Implement TARGET_LEGITIMATE_CONSTANT_P. |
10262 | ||
10263 | In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS | |
10264 | that need more than three instructions to load prior to reload. This | |
10265 | limit is somewhat arbitrary. It takes three instructions to load a | |
10266 | CONST_INT from memory but two are memory accesses. It may be better | |
10267 | to increase the allowed range for CONST_INTS. We may also be able | |
10268 | to handle CONST_DOUBLES. */ | |
10269 | ||
10270 | static bool | |
10271 | pa_legitimate_constant_p (enum machine_mode mode, rtx x) | |
10272 | { | |
10273 | if (GET_MODE_CLASS (mode) == MODE_FLOAT && x != CONST0_RTX (mode)) | |
10274 | return false; | |
10275 | ||
10276 | if (!NEW_HP_ASSEMBLER && !TARGET_GAS && GET_CODE (x) == LABEL_REF) | |
10277 | return false; | |
10278 | ||
f784d2ac | 10279 | /* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not |
10280 | legitimate constants. */ | |
10281 | if (PA_SYMBOL_REF_TLS_P (x)) | |
10282 | { | |
10283 | enum tls_model model = SYMBOL_REF_TLS_MODEL (x); | |
10284 | ||
10285 | if (model == TLS_MODEL_GLOBAL_DYNAMIC || model == TLS_MODEL_LOCAL_DYNAMIC) | |
10286 | return false; | |
10287 | } | |
10288 | ||
ca316360 | 10289 | if (TARGET_64BIT && GET_CODE (x) == CONST_DOUBLE) |
10290 | return false; | |
10291 | ||
10292 | if (TARGET_64BIT | |
10293 | && HOST_BITS_PER_WIDE_INT > 32 | |
10294 | && GET_CODE (x) == CONST_INT | |
10295 | && !reload_in_progress | |
10296 | && !reload_completed | |
10297 | && !LEGITIMATE_64BIT_CONST_INT_P (INTVAL (x)) | |
10298 | && !cint_ok_for_move (INTVAL (x))) | |
10299 | return false; | |
10300 | ||
10301 | if (function_label_operand (x, mode)) | |
10302 | return false; | |
10303 | ||
10304 | return true; | |
10305 | } | |
10306 | ||
1f3233d1 | 10307 | #include "gt-pa.h" |