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87ad11b0 | 1 | /* Subroutines for insn-output.c for HPPA. |
a9ac13e4 | 2 | Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, |
ace694ca | 3 | 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
87ad11b0 | 4 | Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c |
5 | ||
5c1d8983 | 6 | This file is part of GCC. |
87ad11b0 | 7 | |
5c1d8983 | 8 | GCC is free software; you can redistribute it and/or modify |
87ad11b0 | 9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
5c1d8983 | 13 | GCC is distributed in the hope that it will be useful, |
87ad11b0 | 14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
5c1d8983 | 19 | along with GCC; see the file COPYING. If not, write to |
01e379d0 | 20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
87ad11b0 | 22 | |
87ad11b0 | 23 | #include "config.h" |
b1ca791d | 24 | #include "system.h" |
805e22b2 | 25 | #include "coretypes.h" |
26 | #include "tm.h" | |
87ad11b0 | 27 | #include "rtl.h" |
28 | #include "regs.h" | |
29 | #include "hard-reg-set.h" | |
30 | #include "real.h" | |
31 | #include "insn-config.h" | |
32 | #include "conditions.h" | |
87ad11b0 | 33 | #include "insn-attr.h" |
34 | #include "flags.h" | |
35 | #include "tree.h" | |
9d2d8bd6 | 36 | #include "output.h" |
a584fe8a | 37 | #include "except.h" |
32509e56 | 38 | #include "expr.h" |
d8fc4d0b | 39 | #include "optabs.h" |
d8fc4d0b | 40 | #include "reload.h" |
d7e2f694 | 41 | #include "integrate.h" |
0a893c29 | 42 | #include "function.h" |
b1ca791d | 43 | #include "toplev.h" |
5cb4669a | 44 | #include "ggc.h" |
611a88e1 | 45 | #include "recog.h" |
a584fe8a | 46 | #include "predict.h" |
611a88e1 | 47 | #include "tm_p.h" |
a767736d | 48 | #include "target.h" |
49 | #include "target-def.h" | |
87ad11b0 | 50 | |
cde3e16c | 51 | /* Return nonzero if there is a bypass for the output of |
52 | OUT_INSN and the fp store IN_INSN. */ | |
53 | int | |
5c1d8983 | 54 | hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn) |
cde3e16c | 55 | { |
56 | enum machine_mode store_mode; | |
57 | enum machine_mode other_mode; | |
58 | rtx set; | |
59 | ||
60 | if (recog_memoized (in_insn) < 0 | |
61 | || get_attr_type (in_insn) != TYPE_FPSTORE | |
62 | || recog_memoized (out_insn) < 0) | |
63 | return 0; | |
64 | ||
65 | store_mode = GET_MODE (SET_SRC (PATTERN (in_insn))); | |
66 | ||
67 | set = single_set (out_insn); | |
68 | if (!set) | |
69 | return 0; | |
70 | ||
71 | other_mode = GET_MODE (SET_SRC (set)); | |
72 | ||
73 | return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode)); | |
74 | } | |
75 | ||
76 | ||
cc858176 | 77 | #ifndef DO_FRAME_NOTES |
78 | #ifdef INCOMING_RETURN_ADDR_RTX | |
79 | #define DO_FRAME_NOTES 1 | |
80 | #else | |
81 | #define DO_FRAME_NOTES 0 | |
82 | #endif | |
83 | #endif | |
84 | ||
dbd3d89d | 85 | static void copy_reg_pointer (rtx, rtx); |
320e1276 | 86 | static void fix_range (const char *); |
bd57250e | 87 | static bool pa_handle_option (size_t, const char *, int); |
5c1d8983 | 88 | static int hppa_address_cost (rtx); |
89 | static bool hppa_rtx_costs (rtx, int, int, int *); | |
90 | static inline rtx force_mode (enum machine_mode, rtx); | |
91 | static void pa_reorg (void); | |
92 | static void pa_combine_instructions (void); | |
93 | static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx); | |
94 | static int forward_branch_p (rtx); | |
5c1d8983 | 95 | static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *); |
008c057d | 96 | static int compute_movmem_length (rtx); |
97 | static int compute_clrmem_length (rtx); | |
5c1d8983 | 98 | static bool pa_assemble_integer (rtx, unsigned int, int); |
99 | static void remove_useless_addtr_insns (int); | |
6bcdc1fb | 100 | static void store_reg (int, HOST_WIDE_INT, int); |
101 | static void store_reg_modify (int, int, HOST_WIDE_INT); | |
102 | static void load_reg (int, HOST_WIDE_INT, int); | |
103 | static void set_reg_plus_d (int, int, HOST_WIDE_INT, int); | |
5c1d8983 | 104 | static void pa_output_function_prologue (FILE *, HOST_WIDE_INT); |
105 | static void update_total_code_bytes (int); | |
106 | static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT); | |
107 | static int pa_adjust_cost (rtx, rtx, rtx, int); | |
108 | static int pa_adjust_priority (rtx, int); | |
109 | static int pa_issue_rate (void); | |
110 | static void pa_select_section (tree, int, unsigned HOST_WIDE_INT) | |
52470889 | 111 | ATTRIBUTE_UNUSED; |
5c1d8983 | 112 | static void pa_encode_section_info (tree, rtx, int); |
113 | static const char *pa_strip_name_encoding (const char *); | |
114 | static bool pa_function_ok_for_sibcall (tree, tree); | |
115 | static void pa_globalize_label (FILE *, const char *) | |
63b8cd48 | 116 | ATTRIBUTE_UNUSED; |
5c1d8983 | 117 | static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, |
118 | HOST_WIDE_INT, tree); | |
de419443 | 119 | #if !defined(USE_COLLECT2) |
5c1d8983 | 120 | static void pa_asm_out_constructor (rtx, int); |
121 | static void pa_asm_out_destructor (rtx, int); | |
de419443 | 122 | #endif |
5c1d8983 | 123 | static void pa_init_builtins (void); |
b8debbe8 | 124 | static rtx hppa_builtin_saveregs (void); |
4c33eb68 | 125 | static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *); |
2b1e7cc3 | 126 | static bool pa_scalar_mode_supported_p (enum machine_mode); |
5c1d8983 | 127 | static void copy_fp_args (rtx) ATTRIBUTE_UNUSED; |
128 | static int length_fp_args (rtx) ATTRIBUTE_UNUSED; | |
5f43b4f6 | 129 | static struct deferred_plabel *get_plabel (rtx) ATTRIBUTE_UNUSED; |
5c1d8983 | 130 | static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED; |
131 | static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED; | |
132 | static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED; | |
133 | static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED; | |
134 | static void pa_elf_file_start (void) ATTRIBUTE_UNUSED; | |
135 | static void pa_som_file_start (void) ATTRIBUTE_UNUSED; | |
136 | static void pa_linux_file_start (void) ATTRIBUTE_UNUSED; | |
137 | static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED; | |
138 | static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED; | |
139 | static void output_deferred_plabels (void); | |
5f43b4f6 | 140 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
141 | static void pa_hpux_file_end (void); | |
142 | #endif | |
f2f543a3 | 143 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
144 | static void pa_hpux_init_libfuncs (void); | |
145 | #endif | |
b8debbe8 | 146 | static rtx pa_struct_value_rtx (tree, int); |
f054eb3c | 147 | static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, |
b981d932 | 148 | tree, bool); |
f054eb3c | 149 | static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, |
150 | tree, bool); | |
916c9cef | 151 | static struct machine_function * pa_init_machine_status (void); |
b981d932 | 152 | |
9d3ddb8f | 153 | |
87ad11b0 | 154 | /* Save the operands last given to a compare for use when we |
155 | generate a scc or bcc insn. */ | |
87ad11b0 | 156 | rtx hppa_compare_op0, hppa_compare_op1; |
157 | enum cmp_type hppa_branch_type; | |
158 | ||
320e1276 | 159 | /* Which cpu we are scheduling for. */ |
bd57250e | 160 | enum processor_type pa_cpu = TARGET_SCHED_DEFAULT; |
8ab32933 | 161 | |
162 | /* The UNIX standard to use for predefines and linking. */ | |
bd57250e | 163 | int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993; |
8ab32933 | 164 | |
a9960cdc | 165 | /* Counts for the number of callee-saved general and floating point |
166 | registers which were saved by the current function's prologue. */ | |
167 | static int gr_saved, fr_saved; | |
168 | ||
5c1d8983 | 169 | static rtx find_addr_reg (rtx); |
87ad11b0 | 170 | |
2247cc5f | 171 | /* Keep track of the number of bytes we have output in the CODE subspace |
06ddb6f8 | 172 | during this compilation so we'll know when to emit inline long-calls. */ |
ece88821 | 173 | unsigned long total_code_bytes; |
06ddb6f8 | 174 | |
2247cc5f | 175 | /* The last address of the previous function plus the number of bytes in |
176 | associated thunks that have been output. This is used to determine if | |
177 | a thunk can use an IA-relative branch to reach its target function. */ | |
178 | static int last_address; | |
179 | ||
e3f53689 | 180 | /* Variables to handle plabels that we discover are necessary at assembly |
01cc3b75 | 181 | output time. They are output after the current function. */ |
1f3233d1 | 182 | struct deferred_plabel GTY(()) |
e3f53689 | 183 | { |
184 | rtx internal_label; | |
5f43b4f6 | 185 | rtx symbol; |
1f3233d1 | 186 | }; |
187 | static GTY((length ("n_deferred_plabels"))) struct deferred_plabel * | |
188 | deferred_plabels; | |
e11bd7e5 | 189 | static size_t n_deferred_plabels = 0; |
f6940372 | 190 | |
a767736d | 191 | \f |
192 | /* Initialize the GCC target structure. */ | |
58356836 | 193 | |
194 | #undef TARGET_ASM_ALIGNED_HI_OP | |
195 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
196 | #undef TARGET_ASM_ALIGNED_SI_OP | |
197 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
198 | #undef TARGET_ASM_ALIGNED_DI_OP | |
199 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
200 | #undef TARGET_ASM_UNALIGNED_HI_OP | |
201 | #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP | |
202 | #undef TARGET_ASM_UNALIGNED_SI_OP | |
203 | #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP | |
204 | #undef TARGET_ASM_UNALIGNED_DI_OP | |
205 | #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP | |
206 | #undef TARGET_ASM_INTEGER | |
207 | #define TARGET_ASM_INTEGER pa_assemble_integer | |
208 | ||
17d9b0c3 | 209 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
210 | #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue | |
211 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
212 | #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue | |
e3f53689 | 213 | |
747af5e7 | 214 | #undef TARGET_SCHED_ADJUST_COST |
215 | #define TARGET_SCHED_ADJUST_COST pa_adjust_cost | |
216 | #undef TARGET_SCHED_ADJUST_PRIORITY | |
217 | #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority | |
218 | #undef TARGET_SCHED_ISSUE_RATE | |
219 | #define TARGET_SCHED_ISSUE_RATE pa_issue_rate | |
220 | ||
7811991d | 221 | #undef TARGET_ENCODE_SECTION_INFO |
222 | #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info | |
7b4a38a6 | 223 | #undef TARGET_STRIP_NAME_ENCODING |
224 | #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding | |
7811991d | 225 | |
805e22b2 | 226 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
227 | #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall | |
228 | ||
6988553d | 229 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
230 | #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk | |
eb344f43 | 231 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK |
232 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
6988553d | 233 | |
f6940372 | 234 | #undef TARGET_ASM_FILE_END |
5f43b4f6 | 235 | #ifdef ASM_OUTPUT_EXTERNAL_REAL |
236 | #define TARGET_ASM_FILE_END pa_hpux_file_end | |
237 | #else | |
f6940372 | 238 | #define TARGET_ASM_FILE_END output_deferred_plabels |
5f43b4f6 | 239 | #endif |
f6940372 | 240 | |
de419443 | 241 | #if !defined(USE_COLLECT2) |
242 | #undef TARGET_ASM_CONSTRUCTOR | |
243 | #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor | |
244 | #undef TARGET_ASM_DESTRUCTOR | |
245 | #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor | |
246 | #endif | |
247 | ||
bd57250e | 248 | #undef TARGET_DEFAULT_TARGET_FLAGS |
249 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT) | |
250 | #undef TARGET_HANDLE_OPTION | |
251 | #define TARGET_HANDLE_OPTION pa_handle_option | |
252 | ||
ffa8918b | 253 | #undef TARGET_INIT_BUILTINS |
254 | #define TARGET_INIT_BUILTINS pa_init_builtins | |
255 | ||
fab7adbf | 256 | #undef TARGET_RTX_COSTS |
257 | #define TARGET_RTX_COSTS hppa_rtx_costs | |
ec0457a8 | 258 | #undef TARGET_ADDRESS_COST |
259 | #define TARGET_ADDRESS_COST hppa_address_cost | |
fab7adbf | 260 | |
2efea8c0 | 261 | #undef TARGET_MACHINE_DEPENDENT_REORG |
262 | #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg | |
263 | ||
f2f543a3 | 264 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
265 | #undef TARGET_INIT_LIBFUNCS | |
266 | #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs | |
267 | #endif | |
268 | ||
b8debbe8 | 269 | #undef TARGET_PROMOTE_FUNCTION_RETURN |
270 | #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true | |
271 | #undef TARGET_PROMOTE_PROTOTYPES | |
272 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true | |
273 | ||
274 | #undef TARGET_STRUCT_VALUE_RTX | |
275 | #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx | |
276 | #undef TARGET_RETURN_IN_MEMORY | |
277 | #define TARGET_RETURN_IN_MEMORY pa_return_in_memory | |
0336f0f0 | 278 | #undef TARGET_MUST_PASS_IN_STACK |
279 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
b981d932 | 280 | #undef TARGET_PASS_BY_REFERENCE |
281 | #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference | |
13f08ee7 | 282 | #undef TARGET_CALLEE_COPIES |
283 | #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true | |
f054eb3c | 284 | #undef TARGET_ARG_PARTIAL_BYTES |
285 | #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes | |
b8debbe8 | 286 | |
287 | #undef TARGET_EXPAND_BUILTIN_SAVEREGS | |
288 | #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs | |
4c33eb68 | 289 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
290 | #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr | |
b8debbe8 | 291 | |
2b1e7cc3 | 292 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
293 | #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p | |
294 | ||
57e4bbfb | 295 | struct gcc_target targetm = TARGET_INITIALIZER; |
a767736d | 296 | \f |
320e1276 | 297 | /* Parse the -mfixed-range= option string. */ |
298 | ||
299 | static void | |
300 | fix_range (const char *const_str) | |
301 | { | |
302 | int i, first, last; | |
303 | char *str, *dash, *comma; | |
304 | ||
305 | /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and | |
306 | REG2 are either register names or register numbers. The effect | |
307 | of this option is to mark the registers in the range from REG1 to | |
308 | REG2 as ``fixed'' so they won't be used by the compiler. This is | |
309 | used, e.g., to ensure that kernel mode code doesn't use f32-f127. */ | |
310 | ||
311 | i = strlen (const_str); | |
312 | str = (char *) alloca (i + 1); | |
313 | memcpy (str, const_str, i + 1); | |
314 | ||
315 | while (1) | |
316 | { | |
317 | dash = strchr (str, '-'); | |
318 | if (!dash) | |
319 | { | |
320 | warning ("value of -mfixed-range must have form REG1-REG2"); | |
321 | return; | |
322 | } | |
323 | *dash = '\0'; | |
324 | ||
325 | comma = strchr (dash + 1, ','); | |
326 | if (comma) | |
327 | *comma = '\0'; | |
328 | ||
329 | first = decode_reg_name (str); | |
330 | if (first < 0) | |
331 | { | |
332 | warning ("unknown register name: %s", str); | |
333 | return; | |
334 | } | |
335 | ||
336 | last = decode_reg_name (dash + 1); | |
337 | if (last < 0) | |
338 | { | |
339 | warning ("unknown register name: %s", dash + 1); | |
340 | return; | |
341 | } | |
342 | ||
343 | *dash = '-'; | |
344 | ||
345 | if (first > last) | |
346 | { | |
347 | warning ("%s-%s is an empty range", str, dash + 1); | |
348 | return; | |
349 | } | |
350 | ||
351 | for (i = first; i <= last; ++i) | |
352 | fixed_regs[i] = call_used_regs[i] = 1; | |
353 | ||
354 | if (!comma) | |
355 | break; | |
356 | ||
357 | *comma = ','; | |
358 | str = comma + 1; | |
359 | } | |
360 | ||
361 | /* Check if all floating point registers have been fixed. */ | |
362 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
363 | if (!fixed_regs[i]) | |
364 | break; | |
365 | ||
366 | if (i > FP_REG_LAST) | |
367 | target_flags |= MASK_DISABLE_FPREGS; | |
368 | } | |
369 | ||
bd57250e | 370 | /* Implement TARGET_HANDLE_OPTION. */ |
c7a4e712 | 371 | |
bd57250e | 372 | static bool |
373 | pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
374 | { | |
375 | switch (code) | |
4dc42288 | 376 | { |
bd57250e | 377 | case OPT_mnosnake: |
378 | case OPT_mpa_risc_1_0: | |
379 | case OPT_march_1_0: | |
4dc42288 | 380 | target_flags &= ~(MASK_PA_11 | MASK_PA_20); |
bd57250e | 381 | return true; |
382 | ||
383 | case OPT_msnake: | |
384 | case OPT_mpa_risc_1_1: | |
385 | case OPT_march_1_1: | |
4dc42288 | 386 | target_flags &= ~MASK_PA_20; |
387 | target_flags |= MASK_PA_11; | |
bd57250e | 388 | return true; |
4dc42288 | 389 | |
bd57250e | 390 | case OPT_mpa_risc_2_0: |
391 | case OPT_march_2_0: | |
392 | target_flags |= MASK_PA_11 | MASK_PA_20; | |
393 | return true; | |
394 | ||
395 | case OPT_mschedule_: | |
396 | if (strcmp (arg, "8000") == 0) | |
397 | pa_cpu = PROCESSOR_8000; | |
398 | else if (strcmp (arg, "7100") == 0) | |
399 | pa_cpu = PROCESSOR_7100; | |
400 | else if (strcmp (arg, "700") == 0) | |
401 | pa_cpu = PROCESSOR_700; | |
402 | else if (strcmp (arg, "7100LC") == 0) | |
403 | pa_cpu = PROCESSOR_7100LC; | |
404 | else if (strcmp (arg, "7200") == 0) | |
405 | pa_cpu = PROCESSOR_7200; | |
406 | else if (strcmp (arg, "7300") == 0) | |
407 | pa_cpu = PROCESSOR_7300; | |
8ab32933 | 408 | else |
bd57250e | 409 | return false; |
410 | return true; | |
8ab32933 | 411 | |
bd57250e | 412 | case OPT_mfixed_range_: |
413 | fix_range (arg); | |
414 | return true; | |
320e1276 | 415 | |
bd57250e | 416 | #if TARGET_HPUX |
417 | case OPT_munix_93: | |
418 | flag_pa_unix = 1993; | |
419 | return true; | |
420 | #endif | |
421 | ||
422 | #if TARGET_HPUX_10_10 | |
423 | case OPT_munix_95: | |
424 | flag_pa_unix = 1995; | |
425 | return true; | |
426 | #endif | |
427 | ||
428 | #if TARGET_HPUX_11_11 | |
429 | case OPT_munix_98: | |
430 | flag_pa_unix = 1998; | |
431 | return true; | |
432 | #endif | |
433 | ||
434 | default: | |
435 | return true; | |
436 | } | |
437 | } | |
438 | ||
439 | void | |
440 | override_options (void) | |
441 | { | |
7c5101fc | 442 | /* Unconditional branches in the delay slot are not compatible with dwarf2 |
443 | call frame information. There is no benefit in using this optimization | |
444 | on PA8000 and later processors. */ | |
445 | if (pa_cpu >= PROCESSOR_8000 | |
446 | || (! USING_SJLJ_EXCEPTIONS && flag_exceptions) | |
447 | || flag_unwind_tables) | |
448 | target_flags &= ~MASK_JUMP_IN_DELAY; | |
449 | ||
c7a4e712 | 450 | if (flag_pic && TARGET_PORTABLE_RUNTIME) |
451 | { | |
452 | warning ("PIC code generation is not supported in the portable runtime model\n"); | |
453 | } | |
454 | ||
b29897dd | 455 | if (flag_pic && TARGET_FAST_INDIRECT_CALLS) |
c7a4e712 | 456 | { |
ad87de1e | 457 | warning ("PIC code generation is not compatible with fast indirect calls\n"); |
c7a4e712 | 458 | } |
751e64a1 | 459 | |
5bd7b548 | 460 | if (! TARGET_GAS && write_symbols != NO_DEBUG) |
461 | { | |
462 | warning ("-g is only supported when using GAS on this processor,"); | |
68435912 | 463 | warning ("-g option disabled"); |
5bd7b548 | 464 | write_symbols = NO_DEBUG; |
465 | } | |
5cb4669a | 466 | |
fc44315f | 467 | /* We only support the "big PIC" model now. And we always generate PIC |
468 | code when in 64bit mode. */ | |
469 | if (flag_pic == 1 || TARGET_64BIT) | |
5e3c5739 | 470 | flag_pic = 2; |
471 | ||
58356836 | 472 | /* We can't guarantee that .dword is available for 32-bit targets. */ |
473 | if (UNITS_PER_WORD == 4) | |
474 | targetm.asm_out.aligned_op.di = NULL; | |
475 | ||
476 | /* The unaligned ops are only available when using GAS. */ | |
477 | if (!TARGET_GAS) | |
478 | { | |
479 | targetm.asm_out.unaligned_op.hi = NULL; | |
480 | targetm.asm_out.unaligned_op.si = NULL; | |
481 | targetm.asm_out.unaligned_op.di = NULL; | |
482 | } | |
916c9cef | 483 | |
484 | init_machine_status = pa_init_machine_status; | |
134b4858 | 485 | } |
486 | ||
066397a3 | 487 | static void |
5c1d8983 | 488 | pa_init_builtins (void) |
ffa8918b | 489 | { |
490 | #ifdef DONT_HAVE_FPUTC_UNLOCKED | |
491 | built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE; | |
5ddc8fb8 | 492 | implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE; |
ffa8918b | 493 | #endif |
494 | } | |
495 | ||
916c9cef | 496 | /* Function to init struct machine_function. |
497 | This will be called, via a pointer variable, | |
498 | from push_function_context. */ | |
499 | ||
500 | static struct machine_function * | |
501 | pa_init_machine_status (void) | |
502 | { | |
503 | return ggc_alloc_cleared (sizeof (machine_function)); | |
504 | } | |
505 | ||
dbd3d89d | 506 | /* If FROM is a probable pointer register, mark TO as a probable |
507 | pointer register with the same pointer alignment as FROM. */ | |
508 | ||
509 | static void | |
510 | copy_reg_pointer (rtx to, rtx from) | |
511 | { | |
512 | if (REG_POINTER (from)) | |
513 | mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from))); | |
514 | } | |
515 | ||
6d36483b | 516 | /* Return 1 if X contains a symbolic expression. We know these |
517 | expressions will have one of a few well defined forms, so | |
347b5848 | 518 | we need only check those forms. */ |
519 | int | |
5c1d8983 | 520 | symbolic_expression_p (rtx x) |
347b5848 | 521 | { |
522 | ||
6dc3b0d9 | 523 | /* Strip off any HIGH. */ |
347b5848 | 524 | if (GET_CODE (x) == HIGH) |
525 | x = XEXP (x, 0); | |
526 | ||
527 | return (symbolic_operand (x, VOIDmode)); | |
528 | } | |
529 | ||
7c4d3047 | 530 | /* Accept any constant that can be moved in one instruction into a |
d9d7c968 | 531 | general register. */ |
6d36483b | 532 | int |
5c1d8983 | 533 | cint_ok_for_move (HOST_WIDE_INT intval) |
d9d7c968 | 534 | { |
535 | /* OK if ldo, ldil, or zdepi, can be used. */ | |
d8d5c4ff | 536 | return (CONST_OK_FOR_LETTER_P (intval, 'J') |
537 | || CONST_OK_FOR_LETTER_P (intval, 'N') | |
538 | || CONST_OK_FOR_LETTER_P (intval, 'K')); | |
d9d7c968 | 539 | } |
87ad11b0 | 540 | \f |
2a91e628 | 541 | /* Return truth value of whether OP can be used as an operand in a |
542 | adddi3 insn. */ | |
543 | int | |
5c1d8983 | 544 | adddi3_operand (rtx op, enum machine_mode mode) |
2a91e628 | 545 | { |
546 | return (register_operand (op, mode) | |
547 | || (GET_CODE (op) == CONST_INT | |
548 | && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op)))); | |
549 | } | |
550 | ||
ea52c577 | 551 | /* True iff zdepi can be used to generate this CONST_INT. |
552 | zdepi first sign extends a 5 bit signed number to a given field | |
553 | length, then places this field anywhere in a zero. */ | |
e057641f | 554 | int |
5c1d8983 | 555 | zdepi_cint_p (unsigned HOST_WIDE_INT x) |
fad0b60f | 556 | { |
3745c59b | 557 | unsigned HOST_WIDE_INT lsb_mask, t; |
fad0b60f | 558 | |
559 | /* This might not be obvious, but it's at least fast. | |
01cc3b75 | 560 | This function is critical; we don't have the time loops would take. */ |
42faba01 | 561 | lsb_mask = x & -x; |
562 | t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1); | |
563 | /* Return true iff t is a power of two. */ | |
fad0b60f | 564 | return ((t & (t - 1)) == 0); |
565 | } | |
566 | ||
6d36483b | 567 | /* True iff depi or extru can be used to compute (reg & mask). |
568 | Accept bit pattern like these: | |
569 | 0....01....1 | |
570 | 1....10....0 | |
571 | 1..10..01..1 */ | |
e057641f | 572 | int |
5c1d8983 | 573 | and_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 574 | { |
575 | mask = ~mask; | |
576 | mask += mask & -mask; | |
577 | return (mask & (mask - 1)) == 0; | |
578 | } | |
579 | ||
e057641f | 580 | /* True iff depi can be used to compute (reg | MASK). */ |
581 | int | |
5c1d8983 | 582 | ior_mask_p (unsigned HOST_WIDE_INT mask) |
e057641f | 583 | { |
584 | mask += mask & -mask; | |
585 | return (mask & (mask - 1)) == 0; | |
586 | } | |
87ad11b0 | 587 | \f |
588 | /* Legitimize PIC addresses. If the address is already | |
589 | position-independent, we return ORIG. Newly generated | |
590 | position-independent addresses go to REG. If we need more | |
591 | than one register, we lose. */ | |
592 | ||
593 | rtx | |
5c1d8983 | 594 | legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) |
87ad11b0 | 595 | { |
596 | rtx pic_ref = orig; | |
597 | ||
b090827b | 598 | /* Labels need special handling. */ |
611a88e1 | 599 | if (pic_label_operand (orig, mode)) |
b4a7bf10 | 600 | { |
2536cc16 | 601 | /* We do not want to go through the movXX expanders here since that |
602 | would create recursion. | |
603 | ||
604 | Nor do we really want to call a generator for a named pattern | |
605 | since that requires multiple patterns if we want to support | |
606 | multiple word sizes. | |
607 | ||
608 | So instead we just emit the raw set, which avoids the movXX | |
609 | expanders completely. */ | |
dbd3d89d | 610 | mark_reg_pointer (reg, BITS_PER_UNIT); |
2536cc16 | 611 | emit_insn (gen_rtx_SET (VOIDmode, reg, orig)); |
b4a7bf10 | 612 | current_function_uses_pic_offset_table = 1; |
613 | return reg; | |
614 | } | |
87ad11b0 | 615 | if (GET_CODE (orig) == SYMBOL_REF) |
616 | { | |
f9c1ba9d | 617 | rtx insn, tmp_reg; |
618 | ||
ecf2283d | 619 | gcc_assert (reg); |
87ad11b0 | 620 | |
f9c1ba9d | 621 | /* Before reload, allocate a temporary register for the intermediate |
622 | result. This allows the sequence to be deleted when the final | |
623 | result is unused and the insns are trivially dead. */ | |
624 | tmp_reg = ((reload_in_progress || reload_completed) | |
625 | ? reg : gen_reg_rtx (Pmode)); | |
626 | ||
627 | emit_move_insn (tmp_reg, | |
fc44315f | 628 | gen_rtx_PLUS (word_mode, pic_offset_table_rtx, |
629 | gen_rtx_HIGH (word_mode, orig))); | |
630 | pic_ref | |
e265a6da | 631 | = gen_const_mem (Pmode, |
632 | gen_rtx_LO_SUM (Pmode, tmp_reg, | |
633 | gen_rtx_UNSPEC (Pmode, | |
634 | gen_rtvec (1, orig), | |
635 | UNSPEC_DLTIND14R))); | |
7014838c | 636 | |
87ad11b0 | 637 | current_function_uses_pic_offset_table = 1; |
dbd3d89d | 638 | mark_reg_pointer (reg, BITS_PER_UNIT); |
f9c1ba9d | 639 | insn = emit_move_insn (reg, pic_ref); |
640 | ||
641 | /* Put a REG_EQUAL note on this insn, so that it can be optimized. */ | |
642 | REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn)); | |
643 | ||
87ad11b0 | 644 | return reg; |
645 | } | |
646 | else if (GET_CODE (orig) == CONST) | |
647 | { | |
57ed30e5 | 648 | rtx base; |
87ad11b0 | 649 | |
650 | if (GET_CODE (XEXP (orig, 0)) == PLUS | |
651 | && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) | |
652 | return orig; | |
653 | ||
ecf2283d | 654 | gcc_assert (reg); |
655 | gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); | |
656 | ||
657 | base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); | |
658 | orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, | |
659 | base == reg ? 0 : reg); | |
dbd3d89d | 660 | |
87ad11b0 | 661 | if (GET_CODE (orig) == CONST_INT) |
662 | { | |
42faba01 | 663 | if (INT_14_BITS (orig)) |
b244d4c7 | 664 | return plus_constant (base, INTVAL (orig)); |
87ad11b0 | 665 | orig = force_reg (Pmode, orig); |
666 | } | |
ad851752 | 667 | pic_ref = gen_rtx_PLUS (Pmode, base, orig); |
87ad11b0 | 668 | /* Likewise, should we set special REG_NOTEs here? */ |
669 | } | |
dbd3d89d | 670 | |
87ad11b0 | 671 | return pic_ref; |
672 | } | |
673 | ||
347b5848 | 674 | /* Try machine-dependent ways of modifying an illegitimate address |
675 | to be legitimate. If we find one, return the new, valid address. | |
676 | This macro is used in only one place: `memory_address' in explow.c. | |
677 | ||
678 | OLDX is the address as it was before break_out_memory_refs was called. | |
679 | In some cases it is useful to look at this to decide what needs to be done. | |
680 | ||
681 | MODE and WIN are passed so that this macro can use | |
682 | GO_IF_LEGITIMATE_ADDRESS. | |
683 | ||
684 | It is always safe for this macro to do nothing. It exists to recognize | |
6d36483b | 685 | opportunities to optimize the output. |
347b5848 | 686 | |
687 | For the PA, transform: | |
688 | ||
689 | memory(X + <large int>) | |
690 | ||
691 | into: | |
692 | ||
693 | if (<large int> & mask) >= 16 | |
694 | Y = (<large int> & ~mask) + mask + 1 Round up. | |
695 | else | |
696 | Y = (<large int> & ~mask) Round down. | |
697 | Z = X + Y | |
698 | memory (Z + (<large int> - Y)); | |
699 | ||
6d36483b | 700 | This is for CSE to find several similar references, and only use one Z. |
347b5848 | 701 | |
33f88b1c | 702 | X can either be a SYMBOL_REF or REG, but because combine cannot |
347b5848 | 703 | perform a 4->2 combination we do nothing for SYMBOL_REF + D where |
704 | D will not fit in 14 bits. | |
705 | ||
706 | MODE_FLOAT references allow displacements which fit in 5 bits, so use | |
6d36483b | 707 | 0x1f as the mask. |
347b5848 | 708 | |
709 | MODE_INT references allow displacements which fit in 14 bits, so use | |
6d36483b | 710 | 0x3fff as the mask. |
347b5848 | 711 | |
712 | This relies on the fact that most mode MODE_FLOAT references will use FP | |
713 | registers and most mode MODE_INT references will use integer registers. | |
714 | (In the rare case of an FP register used in an integer MODE, we depend | |
715 | on secondary reloads to clean things up.) | |
716 | ||
717 | ||
718 | It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special | |
719 | manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed | |
01cc3b75 | 720 | addressing modes to be used). |
347b5848 | 721 | |
722 | Put X and Z into registers. Then put the entire expression into | |
723 | a register. */ | |
724 | ||
725 | rtx | |
5c1d8983 | 726 | hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, |
727 | enum machine_mode mode) | |
347b5848 | 728 | { |
347b5848 | 729 | rtx orig = x; |
730 | ||
dbd3d89d | 731 | /* We need to canonicalize the order of operands in unscaled indexed |
732 | addresses since the code that checks if an address is valid doesn't | |
733 | always try both orders. */ | |
734 | if (!TARGET_NO_SPACE_REGS | |
735 | && GET_CODE (x) == PLUS | |
736 | && GET_MODE (x) == Pmode | |
737 | && REG_P (XEXP (x, 0)) | |
738 | && REG_P (XEXP (x, 1)) | |
739 | && REG_POINTER (XEXP (x, 0)) | |
740 | && !REG_POINTER (XEXP (x, 1))) | |
741 | return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0)); | |
742 | ||
b4a7bf10 | 743 | if (flag_pic) |
744 | return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode)); | |
745 | ||
6dc3b0d9 | 746 | /* Strip off CONST. */ |
347b5848 | 747 | if (GET_CODE (x) == CONST) |
748 | x = XEXP (x, 0); | |
749 | ||
42819d4e | 750 | /* Special case. Get the SYMBOL_REF into a register and use indexing. |
751 | That should always be safe. */ | |
752 | if (GET_CODE (x) == PLUS | |
753 | && GET_CODE (XEXP (x, 0)) == REG | |
754 | && GET_CODE (XEXP (x, 1)) == SYMBOL_REF) | |
755 | { | |
440c23df | 756 | rtx reg = force_reg (Pmode, XEXP (x, 1)); |
757 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0))); | |
42819d4e | 758 | } |
759 | ||
166bf021 | 760 | /* Note we must reject symbols which represent function addresses |
761 | since the assembler/linker can't handle arithmetic on plabels. */ | |
347b5848 | 762 | if (GET_CODE (x) == PLUS |
763 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
166bf021 | 764 | && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF |
765 | && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0))) | |
347b5848 | 766 | || GET_CODE (XEXP (x, 0)) == REG)) |
767 | { | |
768 | rtx int_part, ptr_reg; | |
769 | int newoffset; | |
770 | int offset = INTVAL (XEXP (x, 1)); | |
1b6f11e2 | 771 | int mask; |
772 | ||
773 | mask = (GET_MODE_CLASS (mode) == MODE_FLOAT | |
774 | ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff); | |
347b5848 | 775 | |
6d36483b | 776 | /* Choose which way to round the offset. Round up if we |
347b5848 | 777 | are >= halfway to the next boundary. */ |
778 | if ((offset & mask) >= ((mask + 1) / 2)) | |
779 | newoffset = (offset & ~ mask) + mask + 1; | |
780 | else | |
781 | newoffset = (offset & ~ mask); | |
782 | ||
783 | /* If the newoffset will not fit in 14 bits (ldo), then | |
784 | handling this would take 4 or 5 instructions (2 to load | |
785 | the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to | |
786 | add the new offset and the SYMBOL_REF.) Combine can | |
787 | not handle 4->2 or 5->2 combinations, so do not create | |
788 | them. */ | |
789 | if (! VAL_14_BITS_P (newoffset) | |
790 | && GET_CODE (XEXP (x, 0)) == SYMBOL_REF) | |
791 | { | |
7014838c | 792 | rtx const_part = plus_constant (XEXP (x, 0), newoffset); |
347b5848 | 793 | rtx tmp_reg |
339613b4 | 794 | = force_reg (Pmode, |
ad851752 | 795 | gen_rtx_HIGH (Pmode, const_part)); |
347b5848 | 796 | ptr_reg |
339613b4 | 797 | = force_reg (Pmode, |
7014838c | 798 | gen_rtx_LO_SUM (Pmode, |
799 | tmp_reg, const_part)); | |
347b5848 | 800 | } |
801 | else | |
802 | { | |
803 | if (! VAL_14_BITS_P (newoffset)) | |
339613b4 | 804 | int_part = force_reg (Pmode, GEN_INT (newoffset)); |
347b5848 | 805 | else |
806 | int_part = GEN_INT (newoffset); | |
807 | ||
339613b4 | 808 | ptr_reg = force_reg (Pmode, |
ad851752 | 809 | gen_rtx_PLUS (Pmode, |
810 | force_reg (Pmode, XEXP (x, 0)), | |
811 | int_part)); | |
347b5848 | 812 | } |
813 | return plus_constant (ptr_reg, offset - newoffset); | |
814 | } | |
45f1285a | 815 | |
5115683e | 816 | /* Handle (plus (mult (a) (shadd_constant)) (b)). */ |
45f1285a | 817 | |
347b5848 | 818 | if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT |
819 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
45f1285a | 820 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))) |
6720e96c | 821 | && (OBJECT_P (XEXP (x, 1)) |
45f1285a | 822 | || GET_CODE (XEXP (x, 1)) == SUBREG) |
823 | && GET_CODE (XEXP (x, 1)) != CONST) | |
347b5848 | 824 | { |
825 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
826 | rtx reg1, reg2; | |
5115683e | 827 | |
828 | reg1 = XEXP (x, 1); | |
829 | if (GET_CODE (reg1) != REG) | |
830 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
831 | ||
832 | reg2 = XEXP (XEXP (x, 0), 0); | |
833 | if (GET_CODE (reg2) != REG) | |
834 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
835 | ||
ad851752 | 836 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 837 | gen_rtx_MULT (Pmode, |
838 | reg2, | |
839 | GEN_INT (val)), | |
ad851752 | 840 | reg1)); |
347b5848 | 841 | } |
45f1285a | 842 | |
00a87639 | 843 | /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)). |
844 | ||
845 | Only do so for floating point modes since this is more speculative | |
846 | and we lose if it's an integer store. */ | |
5115683e | 847 | if (GET_CODE (x) == PLUS |
00a87639 | 848 | && GET_CODE (XEXP (x, 0)) == PLUS |
849 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
850 | && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT | |
5115683e | 851 | && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) |
852 | && (mode == SFmode || mode == DFmode)) | |
00a87639 | 853 | { |
5115683e | 854 | |
855 | /* First, try and figure out what to use as a base register. */ | |
856 | rtx reg1, reg2, base, idx, orig_base; | |
857 | ||
858 | reg1 = XEXP (XEXP (x, 0), 1); | |
859 | reg2 = XEXP (x, 1); | |
860 | base = NULL_RTX; | |
861 | idx = NULL_RTX; | |
862 | ||
863 | /* Make sure they're both regs. If one was a SYMBOL_REF [+ const], | |
e61a0a7f | 864 | then emit_move_sequence will turn on REG_POINTER so we'll know |
865 | it's a base register below. */ | |
5115683e | 866 | if (GET_CODE (reg1) != REG) |
867 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
868 | ||
869 | if (GET_CODE (reg2) != REG) | |
870 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
871 | ||
872 | /* Figure out what the base and index are. */ | |
9840d99d | 873 | |
5115683e | 874 | if (GET_CODE (reg1) == REG |
e61a0a7f | 875 | && REG_POINTER (reg1)) |
5115683e | 876 | { |
877 | base = reg1; | |
878 | orig_base = XEXP (XEXP (x, 0), 1); | |
ad851752 | 879 | idx = gen_rtx_PLUS (Pmode, |
880 | gen_rtx_MULT (Pmode, | |
881 | XEXP (XEXP (XEXP (x, 0), 0), 0), | |
882 | XEXP (XEXP (XEXP (x, 0), 0), 1)), | |
883 | XEXP (x, 1)); | |
5115683e | 884 | } |
885 | else if (GET_CODE (reg2) == REG | |
e61a0a7f | 886 | && REG_POINTER (reg2)) |
5115683e | 887 | { |
888 | base = reg2; | |
889 | orig_base = XEXP (x, 1); | |
890 | idx = XEXP (x, 0); | |
891 | } | |
892 | ||
893 | if (base == 0) | |
21f3ee9c | 894 | return orig; |
5115683e | 895 | |
896 | /* If the index adds a large constant, try to scale the | |
897 | constant so that it can be loaded with only one insn. */ | |
898 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
899 | && VAL_14_BITS_P (INTVAL (XEXP (idx, 1)) | |
900 | / INTVAL (XEXP (XEXP (idx, 0), 1))) | |
901 | && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0) | |
902 | { | |
903 | /* Divide the CONST_INT by the scale factor, then add it to A. */ | |
904 | int val = INTVAL (XEXP (idx, 1)); | |
905 | ||
906 | val /= INTVAL (XEXP (XEXP (idx, 0), 1)); | |
907 | reg1 = XEXP (XEXP (idx, 0), 0); | |
908 | if (GET_CODE (reg1) != REG) | |
909 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
910 | ||
ad851752 | 911 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val))); |
5115683e | 912 | |
913 | /* We can now generate a simple scaled indexed address. */ | |
7014838c | 914 | return |
915 | force_reg | |
916 | (Pmode, gen_rtx_PLUS (Pmode, | |
917 | gen_rtx_MULT (Pmode, reg1, | |
918 | XEXP (XEXP (idx, 0), 1)), | |
919 | base)); | |
5115683e | 920 | } |
921 | ||
922 | /* If B + C is still a valid base register, then add them. */ | |
923 | if (GET_CODE (XEXP (idx, 1)) == CONST_INT | |
924 | && INTVAL (XEXP (idx, 1)) <= 4096 | |
925 | && INTVAL (XEXP (idx, 1)) >= -4096) | |
926 | { | |
927 | int val = INTVAL (XEXP (XEXP (idx, 0), 1)); | |
928 | rtx reg1, reg2; | |
929 | ||
ad851752 | 930 | reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1))); |
5115683e | 931 | |
932 | reg2 = XEXP (XEXP (idx, 0), 0); | |
933 | if (GET_CODE (reg2) != CONST_INT) | |
934 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
935 | ||
ad851752 | 936 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, |
7014838c | 937 | gen_rtx_MULT (Pmode, |
938 | reg2, | |
ad851752 | 939 | GEN_INT (val)), |
940 | reg1)); | |
5115683e | 941 | } |
942 | ||
943 | /* Get the index into a register, then add the base + index and | |
944 | return a register holding the result. */ | |
945 | ||
946 | /* First get A into a register. */ | |
947 | reg1 = XEXP (XEXP (idx, 0), 0); | |
948 | if (GET_CODE (reg1) != REG) | |
949 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
950 | ||
951 | /* And get B into a register. */ | |
952 | reg2 = XEXP (idx, 1); | |
953 | if (GET_CODE (reg2) != REG) | |
954 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
955 | ||
ad851752 | 956 | reg1 = force_reg (Pmode, |
957 | gen_rtx_PLUS (Pmode, | |
958 | gen_rtx_MULT (Pmode, reg1, | |
959 | XEXP (XEXP (idx, 0), 1)), | |
960 | reg2)); | |
5115683e | 961 | |
962 | /* Add the result to our base register and return. */ | |
ad851752 | 963 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1)); |
9840d99d | 964 | |
00a87639 | 965 | } |
966 | ||
6d36483b | 967 | /* Uh-oh. We might have an address for x[n-100000]. This needs |
fb5390c1 | 968 | special handling to avoid creating an indexed memory address |
969 | with x-100000 as the base. | |
9840d99d | 970 | |
fb5390c1 | 971 | If the constant part is small enough, then it's still safe because |
972 | there is a guard page at the beginning and end of the data segment. | |
973 | ||
974 | Scaled references are common enough that we want to try and rearrange the | |
975 | terms so that we can use indexing for these addresses too. Only | |
00a87639 | 976 | do the optimization for floatint point modes. */ |
45f1285a | 977 | |
fb5390c1 | 978 | if (GET_CODE (x) == PLUS |
979 | && symbolic_expression_p (XEXP (x, 1))) | |
45f1285a | 980 | { |
981 | /* Ugly. We modify things here so that the address offset specified | |
982 | by the index expression is computed first, then added to x to form | |
fb5390c1 | 983 | the entire address. */ |
45f1285a | 984 | |
00a87639 | 985 | rtx regx1, regx2, regy1, regy2, y; |
45f1285a | 986 | |
987 | /* Strip off any CONST. */ | |
988 | y = XEXP (x, 1); | |
989 | if (GET_CODE (y) == CONST) | |
990 | y = XEXP (y, 0); | |
991 | ||
7ee96d6e | 992 | if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS) |
993 | { | |
00a87639 | 994 | /* See if this looks like |
995 | (plus (mult (reg) (shadd_const)) | |
996 | (const (plus (symbol_ref) (const_int)))) | |
997 | ||
5115683e | 998 | Where const_int is small. In that case the const |
9840d99d | 999 | expression is a valid pointer for indexing. |
5115683e | 1000 | |
1001 | If const_int is big, but can be divided evenly by shadd_const | |
1002 | and added to (reg). This allows more scaled indexed addresses. */ | |
1003 | if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1004 | && GET_CODE (XEXP (x, 0)) == MULT | |
00a87639 | 1005 | && GET_CODE (XEXP (y, 1)) == CONST_INT |
5115683e | 1006 | && INTVAL (XEXP (y, 1)) >= -4096 |
1007 | && INTVAL (XEXP (y, 1)) <= 4095 | |
1008 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1009 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
1010 | { | |
1011 | int val = INTVAL (XEXP (XEXP (x, 0), 1)); | |
1012 | rtx reg1, reg2; | |
1013 | ||
1014 | reg1 = XEXP (x, 1); | |
1015 | if (GET_CODE (reg1) != REG) | |
1016 | reg1 = force_reg (Pmode, force_operand (reg1, 0)); | |
1017 | ||
1018 | reg2 = XEXP (XEXP (x, 0), 0); | |
1019 | if (GET_CODE (reg2) != REG) | |
1020 | reg2 = force_reg (Pmode, force_operand (reg2, 0)); | |
1021 | ||
ad851752 | 1022 | return force_reg (Pmode, |
1023 | gen_rtx_PLUS (Pmode, | |
7014838c | 1024 | gen_rtx_MULT (Pmode, |
1025 | reg2, | |
ad851752 | 1026 | GEN_INT (val)), |
7014838c | 1027 | reg1)); |
5115683e | 1028 | } |
1029 | else if ((mode == DFmode || mode == SFmode) | |
1030 | && GET_CODE (XEXP (y, 0)) == SYMBOL_REF | |
1031 | && GET_CODE (XEXP (x, 0)) == MULT | |
1032 | && GET_CODE (XEXP (y, 1)) == CONST_INT | |
1033 | && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0 | |
1034 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
1035 | && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))) | |
00a87639 | 1036 | { |
1037 | regx1 | |
1038 | = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1)) | |
1039 | / INTVAL (XEXP (XEXP (x, 0), 1)))); | |
1040 | regx2 = XEXP (XEXP (x, 0), 0); | |
1041 | if (GET_CODE (regx2) != REG) | |
1042 | regx2 = force_reg (Pmode, force_operand (regx2, 0)); | |
ad851752 | 1043 | regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1044 | regx2, regx1)); | |
7014838c | 1045 | return |
1046 | force_reg (Pmode, | |
1047 | gen_rtx_PLUS (Pmode, | |
1048 | gen_rtx_MULT (Pmode, regx2, | |
1049 | XEXP (XEXP (x, 0), 1)), | |
1050 | force_reg (Pmode, XEXP (y, 0)))); | |
00a87639 | 1051 | } |
fb5390c1 | 1052 | else if (GET_CODE (XEXP (y, 1)) == CONST_INT |
1053 | && INTVAL (XEXP (y, 1)) >= -4096 | |
1054 | && INTVAL (XEXP (y, 1)) <= 4095) | |
1055 | { | |
1056 | /* This is safe because of the guard page at the | |
1057 | beginning and end of the data space. Just | |
1058 | return the original address. */ | |
1059 | return orig; | |
1060 | } | |
00a87639 | 1061 | else |
1062 | { | |
1063 | /* Doesn't look like one we can optimize. */ | |
1064 | regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0)); | |
1065 | regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0)); | |
1066 | regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0)); | |
1067 | regx1 = force_reg (Pmode, | |
ad851752 | 1068 | gen_rtx_fmt_ee (GET_CODE (y), Pmode, |
1069 | regx1, regy2)); | |
1070 | return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1)); | |
00a87639 | 1071 | } |
7ee96d6e | 1072 | } |
45f1285a | 1073 | } |
1074 | ||
347b5848 | 1075 | return orig; |
1076 | } | |
1077 | ||
87ad11b0 | 1078 | /* For the HPPA, REG and REG+CONST is cost 0 |
1079 | and addresses involving symbolic constants are cost 2. | |
1080 | ||
1081 | PIC addresses are very expensive. | |
1082 | ||
1083 | It is no coincidence that this has the same structure | |
1084 | as GO_IF_LEGITIMATE_ADDRESS. */ | |
ec0457a8 | 1085 | |
1086 | static int | |
5c1d8983 | 1087 | hppa_address_cost (rtx X) |
87ad11b0 | 1088 | { |
ec0457a8 | 1089 | switch (GET_CODE (X)) |
1090 | { | |
1091 | case REG: | |
1092 | case PLUS: | |
1093 | case LO_SUM: | |
87ad11b0 | 1094 | return 1; |
ec0457a8 | 1095 | case HIGH: |
1096 | return 2; | |
1097 | default: | |
1098 | return 4; | |
1099 | } | |
87ad11b0 | 1100 | } |
1101 | ||
fab7adbf | 1102 | /* Compute a (partial) cost for rtx X. Return true if the complete |
1103 | cost has been computed, and false if subexpressions should be | |
1104 | scanned. In either case, *TOTAL contains the cost result. */ | |
1105 | ||
1106 | static bool | |
5c1d8983 | 1107 | hppa_rtx_costs (rtx x, int code, int outer_code, int *total) |
fab7adbf | 1108 | { |
1109 | switch (code) | |
1110 | { | |
1111 | case CONST_INT: | |
1112 | if (INTVAL (x) == 0) | |
1113 | *total = 0; | |
1114 | else if (INT_14_BITS (x)) | |
1115 | *total = 1; | |
1116 | else | |
1117 | *total = 2; | |
1118 | return true; | |
1119 | ||
1120 | case HIGH: | |
1121 | *total = 2; | |
1122 | return true; | |
1123 | ||
1124 | case CONST: | |
1125 | case LABEL_REF: | |
1126 | case SYMBOL_REF: | |
1127 | *total = 4; | |
1128 | return true; | |
1129 | ||
1130 | case CONST_DOUBLE: | |
1131 | if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode)) | |
1132 | && outer_code != SET) | |
1133 | *total = 0; | |
1134 | else | |
1135 | *total = 8; | |
1136 | return true; | |
1137 | ||
1138 | case MULT: | |
1139 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1140 | *total = COSTS_N_INSNS (3); | |
1141 | else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT) | |
1142 | *total = COSTS_N_INSNS (8); | |
1143 | else | |
1144 | *total = COSTS_N_INSNS (20); | |
1145 | return true; | |
1146 | ||
1147 | case DIV: | |
1148 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1149 | { | |
1150 | *total = COSTS_N_INSNS (14); | |
1151 | return true; | |
1152 | } | |
8e262b5e | 1153 | /* FALLTHRU */ |
fab7adbf | 1154 | |
1155 | case UDIV: | |
1156 | case MOD: | |
1157 | case UMOD: | |
1158 | *total = COSTS_N_INSNS (60); | |
1159 | return true; | |
1160 | ||
1161 | case PLUS: /* this includes shNadd insns */ | |
1162 | case MINUS: | |
1163 | if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
1164 | *total = COSTS_N_INSNS (3); | |
1165 | else | |
1166 | *total = COSTS_N_INSNS (1); | |
1167 | return true; | |
1168 | ||
1169 | case ASHIFT: | |
1170 | case ASHIFTRT: | |
1171 | case LSHIFTRT: | |
1172 | *total = COSTS_N_INSNS (1); | |
1173 | return true; | |
1174 | ||
1175 | default: | |
1176 | return false; | |
1177 | } | |
1178 | } | |
1179 | ||
9840d99d | 1180 | /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a |
1181 | new rtx with the correct mode. */ | |
1182 | static inline rtx | |
5c1d8983 | 1183 | force_mode (enum machine_mode mode, rtx orig) |
9840d99d | 1184 | { |
1185 | if (mode == GET_MODE (orig)) | |
1186 | return orig; | |
1187 | ||
ecf2283d | 1188 | gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER); |
9840d99d | 1189 | |
1190 | return gen_rtx_REG (mode, REGNO (orig)); | |
1191 | } | |
1192 | ||
87ad11b0 | 1193 | /* Emit insns to move operands[1] into operands[0]. |
1194 | ||
1195 | Return 1 if we have written out everything that needs to be done to | |
1196 | do the move. Otherwise, return 0 and the caller will emit the move | |
9840d99d | 1197 | normally. |
f756078b | 1198 | |
1199 | Note SCRATCH_REG may not be in the proper mode depending on how it | |
2cecd772 | 1200 | will be used. This routine is responsible for creating a new copy |
f756078b | 1201 | of SCRATCH_REG in the proper mode. */ |
87ad11b0 | 1202 | |
1203 | int | |
5c1d8983 | 1204 | emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg) |
87ad11b0 | 1205 | { |
1206 | register rtx operand0 = operands[0]; | |
1207 | register rtx operand1 = operands[1]; | |
4a155b0f | 1208 | register rtx tem; |
87ad11b0 | 1209 | |
dbd3d89d | 1210 | /* We can only handle indexed addresses in the destination operand |
1211 | of floating point stores. Thus, we need to break out indexed | |
1212 | addresses from the destination operand. */ | |
1213 | if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0))) | |
1214 | { | |
1215 | /* This is only safe up to the beginning of life analysis. */ | |
ecf2283d | 1216 | gcc_assert (!no_new_pseudos); |
dbd3d89d | 1217 | |
1218 | tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0)); | |
1219 | operand0 = replace_equiv_address (operand0, tem); | |
1220 | } | |
1221 | ||
1222 | /* On targets with non-equivalent space registers, break out unscaled | |
1223 | indexed addresses from the source operand before the final CSE. | |
1224 | We have to do this because the REG_POINTER flag is not correctly | |
1225 | carried through various optimization passes and CSE may substitute | |
1226 | a pseudo without the pointer set for one with the pointer set. As | |
5aedf60c | 1227 | a result, we loose various opportunities to create insns with |
dbd3d89d | 1228 | unscaled indexed addresses. */ |
1229 | if (!TARGET_NO_SPACE_REGS | |
1230 | && !cse_not_expected | |
1231 | && GET_CODE (operand1) == MEM | |
1232 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1233 | && REG_P (XEXP (XEXP (operand1, 0), 0)) | |
1234 | && REG_P (XEXP (XEXP (operand1, 0), 1))) | |
1235 | operand1 | |
1236 | = replace_equiv_address (operand1, | |
1237 | copy_to_mode_reg (Pmode, XEXP (operand1, 0))); | |
1238 | ||
2d4dc8d2 | 1239 | if (scratch_reg |
1240 | && reload_in_progress && GET_CODE (operand0) == REG | |
d1e2bb73 | 1241 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) |
1242 | operand0 = reg_equiv_mem[REGNO (operand0)]; | |
2d4dc8d2 | 1243 | else if (scratch_reg |
1244 | && reload_in_progress && GET_CODE (operand0) == SUBREG | |
d1e2bb73 | 1245 | && GET_CODE (SUBREG_REG (operand0)) == REG |
1246 | && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1247 | { |
701e46d0 | 1248 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1249 | the code which tracks sets/uses for delete_output_reload. */ |
1250 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), | |
1251 | reg_equiv_mem [REGNO (SUBREG_REG (operand0))], | |
701e46d0 | 1252 | SUBREG_BYTE (operand0)); |
e00b80b2 | 1253 | operand0 = alter_subreg (&temp); |
a3afad75 | 1254 | } |
d1e2bb73 | 1255 | |
2d4dc8d2 | 1256 | if (scratch_reg |
1257 | && reload_in_progress && GET_CODE (operand1) == REG | |
d1e2bb73 | 1258 | && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) |
1259 | operand1 = reg_equiv_mem[REGNO (operand1)]; | |
2d4dc8d2 | 1260 | else if (scratch_reg |
1261 | && reload_in_progress && GET_CODE (operand1) == SUBREG | |
d1e2bb73 | 1262 | && GET_CODE (SUBREG_REG (operand1)) == REG |
1263 | && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) | |
a3afad75 | 1264 | { |
701e46d0 | 1265 | /* We must not alter SUBREG_BYTE (operand0) since that would confuse |
d3c3f88d | 1266 | the code which tracks sets/uses for delete_output_reload. */ |
1267 | rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), | |
1268 | reg_equiv_mem [REGNO (SUBREG_REG (operand1))], | |
701e46d0 | 1269 | SUBREG_BYTE (operand1)); |
e00b80b2 | 1270 | operand1 = alter_subreg (&temp); |
a3afad75 | 1271 | } |
d1e2bb73 | 1272 | |
2d4dc8d2 | 1273 | if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM |
4a155b0f | 1274 | && ((tem = find_replacement (&XEXP (operand0, 0))) |
1275 | != XEXP (operand0, 0))) | |
ad851752 | 1276 | operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); |
dbd3d89d | 1277 | |
2d4dc8d2 | 1278 | if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM |
4a155b0f | 1279 | && ((tem = find_replacement (&XEXP (operand1, 0))) |
1280 | != XEXP (operand1, 0))) | |
ad851752 | 1281 | operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); |
4a155b0f | 1282 | |
e8fdbafa | 1283 | /* Handle secondary reloads for loads/stores of FP registers from |
047e3121 | 1284 | REG+D addresses where D does not fit in 5 or 14 bits, including |
42819d4e | 1285 | (subreg (mem (addr))) cases. */ |
6bcdc1fb | 1286 | if (scratch_reg |
1287 | && fp_reg_operand (operand0, mode) | |
6b1c36c2 | 1288 | && ((GET_CODE (operand1) == MEM |
047e3121 | 1289 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode), |
1290 | XEXP (operand1, 0))) | |
6b1c36c2 | 1291 | || ((GET_CODE (operand1) == SUBREG |
1292 | && GET_CODE (XEXP (operand1, 0)) == MEM | |
047e3121 | 1293 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1294 | ? SFmode : DFmode), | |
1295 | XEXP (XEXP (operand1, 0), 0)))))) | |
d6f01525 | 1296 | { |
6b1c36c2 | 1297 | if (GET_CODE (operand1) == SUBREG) |
1298 | operand1 = XEXP (operand1, 0); | |
1299 | ||
f756078b | 1300 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1301 | it in WORD_MODE regardless of what mode it was originally given | |
1302 | to us. */ | |
9840d99d | 1303 | scratch_reg = force_mode (word_mode, scratch_reg); |
7ee39d73 | 1304 | |
1305 | /* D might not fit in 14 bits either; for such cases load D into | |
1306 | scratch reg. */ | |
440c23df | 1307 | if (!memory_address_p (Pmode, XEXP (operand1, 0))) |
7ee39d73 | 1308 | { |
1309 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); | |
dbd3d89d | 1310 | emit_move_insn (scratch_reg, |
1311 | gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), | |
1312 | Pmode, | |
1313 | XEXP (XEXP (operand1, 0), 0), | |
1314 | scratch_reg)); | |
7ee39d73 | 1315 | } |
1316 | else | |
1317 | emit_move_insn (scratch_reg, XEXP (operand1, 0)); | |
7014838c | 1318 | emit_insn (gen_rtx_SET (VOIDmode, operand0, |
1319 | gen_rtx_MEM (mode, scratch_reg))); | |
d6f01525 | 1320 | return 1; |
1321 | } | |
6bcdc1fb | 1322 | else if (scratch_reg |
1323 | && fp_reg_operand (operand1, mode) | |
6b1c36c2 | 1324 | && ((GET_CODE (operand0) == MEM |
047e3121 | 1325 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1326 | ? SFmode : DFmode), | |
1327 | XEXP (operand0, 0))) | |
6b1c36c2 | 1328 | || ((GET_CODE (operand0) == SUBREG) |
1329 | && GET_CODE (XEXP (operand0, 0)) == MEM | |
047e3121 | 1330 | && !memory_address_p ((GET_MODE_SIZE (mode) == 4 |
1331 | ? SFmode : DFmode), | |
6bcdc1fb | 1332 | XEXP (XEXP (operand0, 0), 0))))) |
d6f01525 | 1333 | { |
6b1c36c2 | 1334 | if (GET_CODE (operand0) == SUBREG) |
1335 | operand0 = XEXP (operand0, 0); | |
1336 | ||
f756078b | 1337 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1338 | it in WORD_MODE regardless of what mode it was originally given | |
1339 | to us. */ | |
9840d99d | 1340 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1341 | |
7ee39d73 | 1342 | /* D might not fit in 14 bits either; for such cases load D into |
1343 | scratch reg. */ | |
440c23df | 1344 | if (!memory_address_p (Pmode, XEXP (operand0, 0))) |
7ee39d73 | 1345 | { |
1346 | emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); | |
ad851752 | 1347 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, |
1348 | 0)), | |
440c23df | 1349 | Pmode, |
ad851752 | 1350 | XEXP (XEXP (operand0, 0), |
1351 | 0), | |
1352 | scratch_reg)); | |
7ee39d73 | 1353 | } |
1354 | else | |
1355 | emit_move_insn (scratch_reg, XEXP (operand0, 0)); | |
ad851752 | 1356 | emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), |
1357 | operand1)); | |
d6f01525 | 1358 | return 1; |
1359 | } | |
753bd06a | 1360 | /* Handle secondary reloads for loads of FP registers from constant |
1361 | expressions by forcing the constant into memory. | |
1362 | ||
6bcdc1fb | 1363 | Use scratch_reg to hold the address of the memory location. |
753bd06a | 1364 | |
9dc4cbf1 | 1365 | The proper fix is to change PREFERRED_RELOAD_CLASS to return |
87fcb603 | 1366 | NO_REGS when presented with a const_int and a register class |
753bd06a | 1367 | containing only FP registers. Doing so unfortunately creates |
1368 | more problems than it solves. Fix this for 2.5. */ | |
6bcdc1fb | 1369 | else if (scratch_reg |
753bd06a | 1370 | && CONSTANT_P (operand1) |
6bcdc1fb | 1371 | && fp_reg_operand (operand0, mode)) |
753bd06a | 1372 | { |
1373 | rtx xoperands[2]; | |
1374 | ||
f756078b | 1375 | /* SCRATCH_REG will hold an address and maybe the actual data. We want |
1376 | it in WORD_MODE regardless of what mode it was originally given | |
1377 | to us. */ | |
9840d99d | 1378 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1379 | |
753bd06a | 1380 | /* Force the constant into memory and put the address of the |
1381 | memory location into scratch_reg. */ | |
1382 | xoperands[0] = scratch_reg; | |
1383 | xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); | |
8f258b49 | 1384 | emit_move_sequence (xoperands, Pmode, 0); |
753bd06a | 1385 | |
1386 | /* Now load the destination register. */ | |
7014838c | 1387 | emit_insn (gen_rtx_SET (mode, operand0, |
1388 | gen_rtx_MEM (mode, scratch_reg))); | |
753bd06a | 1389 | return 1; |
1390 | } | |
e8fdbafa | 1391 | /* Handle secondary reloads for SAR. These occur when trying to load |
2a170404 | 1392 | the SAR from memory, FP register, or with a constant. */ |
6bcdc1fb | 1393 | else if (scratch_reg |
1394 | && GET_CODE (operand0) == REG | |
2a170404 | 1395 | && REGNO (operand0) < FIRST_PSEUDO_REGISTER |
e8fdbafa | 1396 | && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS |
1397 | && (GET_CODE (operand1) == MEM | |
7d43e0f7 | 1398 | || GET_CODE (operand1) == CONST_INT |
e8fdbafa | 1399 | || (GET_CODE (operand1) == REG |
6bcdc1fb | 1400 | && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))) |
e8fdbafa | 1401 | { |
7eac600c | 1402 | /* D might not fit in 14 bits either; for such cases load D into |
1403 | scratch reg. */ | |
1404 | if (GET_CODE (operand1) == MEM | |
440c23df | 1405 | && !memory_address_p (Pmode, XEXP (operand1, 0))) |
7eac600c | 1406 | { |
fc4d127d | 1407 | /* We are reloading the address into the scratch register, so we |
1408 | want to make sure the scratch register is a full register. */ | |
9840d99d | 1409 | scratch_reg = force_mode (word_mode, scratch_reg); |
fc4d127d | 1410 | |
9840d99d | 1411 | emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); |
ad851752 | 1412 | emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, |
1413 | 0)), | |
440c23df | 1414 | Pmode, |
ad851752 | 1415 | XEXP (XEXP (operand1, 0), |
1416 | 0), | |
1417 | scratch_reg)); | |
fc4d127d | 1418 | |
1419 | /* Now we are going to load the scratch register from memory, | |
1420 | we want to load it in the same width as the original MEM, | |
1421 | which must be the same as the width of the ultimate destination, | |
1422 | OPERAND0. */ | |
9840d99d | 1423 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1424 | ||
fc4d127d | 1425 | emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0), |
ad851752 | 1426 | scratch_reg)); |
7eac600c | 1427 | } |
1428 | else | |
fc4d127d | 1429 | { |
1430 | /* We want to load the scratch register using the same mode as | |
1431 | the ultimate destination. */ | |
9840d99d | 1432 | scratch_reg = force_mode (GET_MODE (operand0), scratch_reg); |
1433 | ||
fc4d127d | 1434 | emit_move_insn (scratch_reg, operand1); |
1435 | } | |
1436 | ||
1437 | /* And emit the insn to set the ultimate destination. We know that | |
1438 | the scratch register has the same mode as the destination at this | |
1439 | point. */ | |
e8fdbafa | 1440 | emit_move_insn (operand0, scratch_reg); |
1441 | return 1; | |
1442 | } | |
dbd3d89d | 1443 | /* Handle the most common case: storing into a register. */ |
d6f01525 | 1444 | else if (register_operand (operand0, mode)) |
87ad11b0 | 1445 | { |
1446 | if (register_operand (operand1, mode) | |
93f6e1c7 | 1447 | || (GET_CODE (operand1) == CONST_INT |
1448 | && cint_ok_for_move (INTVAL (operand1))) | |
891b55b4 | 1449 | || (operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1450 | || (GET_CODE (operand1) == HIGH |
df0651dc | 1451 | && !symbolic_operand (XEXP (operand1, 0), VOIDmode)) |
87ad11b0 | 1452 | /* Only `general_operands' can come here, so MEM is ok. */ |
1453 | || GET_CODE (operand1) == MEM) | |
1454 | { | |
dbd3d89d | 1455 | /* Various sets are created during RTL generation which don't |
1456 | have the REG_POINTER flag correctly set. After the CSE pass, | |
1457 | instruction recognition can fail if we don't consistently | |
1458 | set this flag when performing register copies. This should | |
1459 | also improve the opportunities for creating insns that use | |
1460 | unscaled indexing. */ | |
1461 | if (REG_P (operand0) && REG_P (operand1)) | |
1462 | { | |
1463 | if (REG_POINTER (operand1) | |
1464 | && !REG_POINTER (operand0) | |
1465 | && !HARD_REGISTER_P (operand0)) | |
1466 | copy_reg_pointer (operand0, operand1); | |
1467 | else if (REG_POINTER (operand0) | |
1468 | && !REG_POINTER (operand1) | |
1469 | && !HARD_REGISTER_P (operand1)) | |
1470 | copy_reg_pointer (operand1, operand0); | |
1471 | } | |
1472 | ||
1473 | /* When MEMs are broken out, the REG_POINTER flag doesn't | |
1474 | get set. In some cases, we can set the REG_POINTER flag | |
1475 | from the declaration for the MEM. */ | |
1476 | if (REG_P (operand0) | |
1477 | && GET_CODE (operand1) == MEM | |
1478 | && !REG_POINTER (operand0)) | |
1479 | { | |
1480 | tree decl = MEM_EXPR (operand1); | |
1481 | ||
1482 | /* Set the register pointer flag and register alignment | |
1483 | if the declaration for this memory reference is a | |
1484 | pointer type. Fortran indirect argument references | |
1485 | are ignored. */ | |
1486 | if (decl | |
1487 | && !(flag_argument_noalias > 1 | |
1488 | && TREE_CODE (decl) == INDIRECT_REF | |
1489 | && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL)) | |
1490 | { | |
1491 | tree type; | |
1492 | ||
1493 | /* If this is a COMPONENT_REF, use the FIELD_DECL from | |
1494 | tree operand 1. */ | |
1495 | if (TREE_CODE (decl) == COMPONENT_REF) | |
1496 | decl = TREE_OPERAND (decl, 1); | |
1497 | ||
1498 | type = TREE_TYPE (decl); | |
1499 | if (TREE_CODE (type) == ARRAY_TYPE) | |
1500 | type = get_inner_array_type (type); | |
1501 | ||
1502 | if (POINTER_TYPE_P (type)) | |
1503 | { | |
1504 | int align; | |
1505 | ||
1506 | type = TREE_TYPE (type); | |
1507 | /* Using TYPE_ALIGN_OK is rather conservative as | |
1508 | only the ada frontend actually sets it. */ | |
1509 | align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type) | |
1510 | : BITS_PER_UNIT); | |
1511 | mark_reg_pointer (operand0, align); | |
1512 | } | |
1513 | } | |
1514 | } | |
1515 | ||
ad851752 | 1516 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1517 | return 1; |
1518 | } | |
1519 | } | |
1520 | else if (GET_CODE (operand0) == MEM) | |
1521 | { | |
85eb4c6e | 1522 | if (mode == DFmode && operand1 == CONST0_RTX (mode) |
1523 | && !(reload_in_progress || reload_completed)) | |
1524 | { | |
1525 | rtx temp = gen_reg_rtx (DFmode); | |
1526 | ||
ad851752 | 1527 | emit_insn (gen_rtx_SET (VOIDmode, temp, operand1)); |
1528 | emit_insn (gen_rtx_SET (VOIDmode, operand0, temp)); | |
85eb4c6e | 1529 | return 1; |
1530 | } | |
891b55b4 | 1531 | if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode)) |
87ad11b0 | 1532 | { |
1533 | /* Run this case quickly. */ | |
ad851752 | 1534 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1)); |
87ad11b0 | 1535 | return 1; |
1536 | } | |
2ff4bf8d | 1537 | if (! (reload_in_progress || reload_completed)) |
87ad11b0 | 1538 | { |
1539 | operands[0] = validize_mem (operand0); | |
1540 | operands[1] = operand1 = force_reg (mode, operand1); | |
1541 | } | |
1542 | } | |
1543 | ||
37a75d53 | 1544 | /* Simplify the source if we need to. |
1545 | Note we do have to handle function labels here, even though we do | |
1546 | not consider them legitimate constants. Loop optimizations can | |
bea60f66 | 1547 | call the emit_move_xxx with one as a source. */ |
57ed30e5 | 1548 | if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode)) |
37a75d53 | 1549 | || function_label_operand (operand1, mode) |
2ee034bc | 1550 | || (GET_CODE (operand1) == HIGH |
63882853 | 1551 | && symbolic_operand (XEXP (operand1, 0), mode))) |
87ad11b0 | 1552 | { |
2ee034bc | 1553 | int ishighonly = 0; |
1554 | ||
1555 | if (GET_CODE (operand1) == HIGH) | |
1556 | { | |
1557 | ishighonly = 1; | |
1558 | operand1 = XEXP (operand1, 0); | |
1559 | } | |
87ad11b0 | 1560 | if (symbolic_operand (operand1, mode)) |
1561 | { | |
005a7dd0 | 1562 | /* Argh. The assembler and linker can't handle arithmetic |
81653f9b | 1563 | involving plabels. |
005a7dd0 | 1564 | |
81653f9b | 1565 | So we force the plabel into memory, load operand0 from |
1566 | the memory location, then add in the constant part. */ | |
37a75d53 | 1567 | if ((GET_CODE (operand1) == CONST |
1568 | && GET_CODE (XEXP (operand1, 0)) == PLUS | |
1569 | && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode)) | |
1570 | || function_label_operand (operand1, mode)) | |
005a7dd0 | 1571 | { |
b3d569a0 | 1572 | rtx temp, const_part; |
81653f9b | 1573 | |
1574 | /* Figure out what (if any) scratch register to use. */ | |
1575 | if (reload_in_progress || reload_completed) | |
f756078b | 1576 | { |
1577 | scratch_reg = scratch_reg ? scratch_reg : operand0; | |
1578 | /* SCRATCH_REG will hold an address and maybe the actual | |
1579 | data. We want it in WORD_MODE regardless of what mode it | |
1580 | was originally given to us. */ | |
9840d99d | 1581 | scratch_reg = force_mode (word_mode, scratch_reg); |
f756078b | 1582 | } |
81653f9b | 1583 | else if (flag_pic) |
1584 | scratch_reg = gen_reg_rtx (Pmode); | |
1585 | ||
37a75d53 | 1586 | if (GET_CODE (operand1) == CONST) |
1587 | { | |
1588 | /* Save away the constant part of the expression. */ | |
1589 | const_part = XEXP (XEXP (operand1, 0), 1); | |
ecf2283d | 1590 | gcc_assert (GET_CODE (const_part) == CONST_INT); |
37a75d53 | 1591 | |
1592 | /* Force the function label into memory. */ | |
1593 | temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0)); | |
1594 | } | |
1595 | else | |
1596 | { | |
1597 | /* No constant part. */ | |
1598 | const_part = NULL_RTX; | |
005a7dd0 | 1599 | |
37a75d53 | 1600 | /* Force the function label into memory. */ |
1601 | temp = force_const_mem (mode, operand1); | |
1602 | } | |
9840d99d | 1603 | |
81653f9b | 1604 | |
1605 | /* Get the address of the memory location. PIC-ify it if | |
1606 | necessary. */ | |
1607 | temp = XEXP (temp, 0); | |
1608 | if (flag_pic) | |
1609 | temp = legitimize_pic_address (temp, mode, scratch_reg); | |
1610 | ||
1611 | /* Put the address of the memory location into our destination | |
1612 | register. */ | |
1613 | operands[1] = temp; | |
1614 | emit_move_sequence (operands, mode, scratch_reg); | |
1615 | ||
1616 | /* Now load from the memory location into our destination | |
1617 | register. */ | |
ad851752 | 1618 | operands[1] = gen_rtx_MEM (Pmode, operands[0]); |
81653f9b | 1619 | emit_move_sequence (operands, mode, scratch_reg); |
1620 | ||
1621 | /* And add back in the constant part. */ | |
37a75d53 | 1622 | if (const_part != NULL_RTX) |
1623 | expand_inc (operand0, const_part); | |
81653f9b | 1624 | |
1625 | return 1; | |
005a7dd0 | 1626 | } |
1627 | ||
87ad11b0 | 1628 | if (flag_pic) |
1629 | { | |
2ff4bf8d | 1630 | rtx temp; |
1631 | ||
1632 | if (reload_in_progress || reload_completed) | |
f756078b | 1633 | { |
1634 | temp = scratch_reg ? scratch_reg : operand0; | |
1635 | /* TEMP will hold an address and maybe the actual | |
1636 | data. We want it in WORD_MODE regardless of what mode it | |
1637 | was originally given to us. */ | |
9840d99d | 1638 | temp = force_mode (word_mode, temp); |
f756078b | 1639 | } |
2ff4bf8d | 1640 | else |
1641 | temp = gen_reg_rtx (Pmode); | |
6d36483b | 1642 | |
81653f9b | 1643 | /* (const (plus (symbol) (const_int))) must be forced to |
1644 | memory during/after reload if the const_int will not fit | |
1645 | in 14 bits. */ | |
1646 | if (GET_CODE (operand1) == CONST | |
96b86ab6 | 1647 | && GET_CODE (XEXP (operand1, 0)) == PLUS |
1648 | && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT | |
1649 | && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)) | |
1650 | && (reload_completed || reload_in_progress) | |
1651 | && flag_pic) | |
1652 | { | |
1653 | operands[1] = force_const_mem (mode, operand1); | |
1654 | operands[1] = legitimize_pic_address (XEXP (operands[1], 0), | |
1655 | mode, temp); | |
f3c9071d | 1656 | operands[1] = gen_rtx_MEM (mode, operands[1]); |
96b86ab6 | 1657 | emit_move_sequence (operands, mode, temp); |
1658 | } | |
005a7dd0 | 1659 | else |
1660 | { | |
1661 | operands[1] = legitimize_pic_address (operand1, mode, temp); | |
dbd3d89d | 1662 | if (REG_P (operand0) && REG_P (operands[1])) |
1663 | copy_reg_pointer (operand0, operands[1]); | |
ad851752 | 1664 | emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1])); |
005a7dd0 | 1665 | } |
87ad11b0 | 1666 | } |
b4a7bf10 | 1667 | /* On the HPPA, references to data space are supposed to use dp, |
1668 | register 27, but showing it in the RTL inhibits various cse | |
1669 | and loop optimizations. */ | |
6d36483b | 1670 | else |
87ad11b0 | 1671 | { |
005a7dd0 | 1672 | rtx temp, set; |
2ee034bc | 1673 | |
6d36483b | 1674 | if (reload_in_progress || reload_completed) |
f756078b | 1675 | { |
1676 | temp = scratch_reg ? scratch_reg : operand0; | |
1677 | /* TEMP will hold an address and maybe the actual | |
1678 | data. We want it in WORD_MODE regardless of what mode it | |
1679 | was originally given to us. */ | |
9840d99d | 1680 | temp = force_mode (word_mode, temp); |
f756078b | 1681 | } |
2ee034bc | 1682 | else |
1683 | temp = gen_reg_rtx (mode); | |
1684 | ||
42819d4e | 1685 | /* Loading a SYMBOL_REF into a register makes that register |
9840d99d | 1686 | safe to be used as the base in an indexed address. |
42819d4e | 1687 | |
1688 | Don't mark hard registers though. That loses. */ | |
47a61b79 | 1689 | if (GET_CODE (operand0) == REG |
1690 | && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) | |
dbd3d89d | 1691 | mark_reg_pointer (operand0, BITS_PER_UNIT); |
42819d4e | 1692 | if (REGNO (temp) >= FIRST_PSEUDO_REGISTER) |
dbd3d89d | 1693 | mark_reg_pointer (temp, BITS_PER_UNIT); |
1694 | ||
2ee034bc | 1695 | if (ishighonly) |
ad851752 | 1696 | set = gen_rtx_SET (mode, operand0, temp); |
2ee034bc | 1697 | else |
7014838c | 1698 | set = gen_rtx_SET (VOIDmode, |
1699 | operand0, | |
ad851752 | 1700 | gen_rtx_LO_SUM (mode, temp, operand1)); |
6d36483b | 1701 | |
ad851752 | 1702 | emit_insn (gen_rtx_SET (VOIDmode, |
1703 | temp, | |
1704 | gen_rtx_HIGH (mode, operand1))); | |
d2498717 | 1705 | emit_insn (set); |
166bf021 | 1706 | |
87ad11b0 | 1707 | } |
2ee034bc | 1708 | return 1; |
87ad11b0 | 1709 | } |
42faba01 | 1710 | else if (GET_CODE (operand1) != CONST_INT |
6bcdc1fb | 1711 | || !cint_ok_for_move (INTVAL (operand1))) |
87ad11b0 | 1712 | { |
6bcdc1fb | 1713 | rtx insn, temp; |
1714 | rtx op1 = operand1; | |
6edde44b | 1715 | HOST_WIDE_INT value = 0; |
6bcdc1fb | 1716 | HOST_WIDE_INT insv = 0; |
1717 | int insert = 0; | |
1718 | ||
6edde44b | 1719 | if (GET_CODE (operand1) == CONST_INT) |
1720 | value = INTVAL (operand1); | |
1721 | ||
6bcdc1fb | 1722 | if (TARGET_64BIT |
1723 | && GET_CODE (operand1) == CONST_INT | |
b7d86581 | 1724 | && HOST_BITS_PER_WIDE_INT > 32 |
5e3c5739 | 1725 | && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32) |
1726 | { | |
b7d86581 | 1727 | HOST_WIDE_INT nval; |
5e3c5739 | 1728 | |
93f6e1c7 | 1729 | /* Extract the low order 32 bits of the value and sign extend. |
1730 | If the new value is the same as the original value, we can | |
1731 | can use the original value as-is. If the new value is | |
1732 | different, we use it and insert the most-significant 32-bits | |
1733 | of the original value into the final result. */ | |
6bcdc1fb | 1734 | nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1)) |
b7d86581 | 1735 | ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31); |
6bcdc1fb | 1736 | if (value != nval) |
5e3c5739 | 1737 | { |
93f6e1c7 | 1738 | #if HOST_BITS_PER_WIDE_INT > 32 |
6bcdc1fb | 1739 | insv = value >= 0 ? value >> 32 : ~(~value >> 32); |
93f6e1c7 | 1740 | #endif |
6bcdc1fb | 1741 | insert = 1; |
1742 | value = nval; | |
5e3c5739 | 1743 | operand1 = GEN_INT (nval); |
1744 | } | |
1745 | } | |
2ff4bf8d | 1746 | |
1747 | if (reload_in_progress || reload_completed) | |
6bcdc1fb | 1748 | temp = scratch_reg ? scratch_reg : operand0; |
2ff4bf8d | 1749 | else |
1750 | temp = gen_reg_rtx (mode); | |
1751 | ||
7c4d3047 | 1752 | /* We don't directly split DImode constants on 32-bit targets |
1753 | because PLUS uses an 11-bit immediate and the insn sequence | |
1754 | generated is not as efficient as the one using HIGH/LO_SUM. */ | |
1755 | if (GET_CODE (operand1) == CONST_INT | |
6bcdc1fb | 1756 | && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT |
1757 | && !insert) | |
93f6e1c7 | 1758 | { |
7c4d3047 | 1759 | /* Directly break constant into high and low parts. This |
93f6e1c7 | 1760 | provides better optimization opportunities because various |
1761 | passes recognize constants split with PLUS but not LO_SUM. | |
1762 | We use a 14-bit signed low part except when the addition | |
1763 | of 0x4000 to the high part might change the sign of the | |
1764 | high part. */ | |
93f6e1c7 | 1765 | HOST_WIDE_INT low = value & 0x3fff; |
1766 | HOST_WIDE_INT high = value & ~ 0x3fff; | |
1767 | ||
1768 | if (low >= 0x2000) | |
1769 | { | |
1770 | if (high == 0x7fffc000 || (mode == HImode && high == 0x4000)) | |
1771 | high += 0x2000; | |
1772 | else | |
1773 | high += 0x4000; | |
1774 | } | |
1775 | ||
1776 | low = value - high; | |
5e3c5739 | 1777 | |
93f6e1c7 | 1778 | emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high))); |
1779 | operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low)); | |
1780 | } | |
1781 | else | |
5e3c5739 | 1782 | { |
93f6e1c7 | 1783 | emit_insn (gen_rtx_SET (VOIDmode, temp, |
1784 | gen_rtx_HIGH (mode, operand1))); | |
1785 | operands[1] = gen_rtx_LO_SUM (mode, temp, operand1); | |
5e3c5739 | 1786 | } |
9840d99d | 1787 | |
6bcdc1fb | 1788 | insn = emit_move_insn (operands[0], operands[1]); |
1789 | ||
1790 | /* Now insert the most significant 32 bits of the value | |
1791 | into the register. When we don't have a second register | |
1792 | available, it could take up to nine instructions to load | |
1793 | a 64-bit integer constant. Prior to reload, we force | |
1794 | constants that would take more than three instructions | |
1795 | to load to the constant pool. During and after reload, | |
1796 | we have to handle all possible values. */ | |
1797 | if (insert) | |
1798 | { | |
1799 | /* Use a HIGH/LO_SUM/INSV sequence if we have a second | |
1800 | register and the value to be inserted is outside the | |
1801 | range that can be loaded with three depdi instructions. */ | |
1802 | if (temp != operand0 && (insv >= 16384 || insv < -16384)) | |
1803 | { | |
1804 | operand1 = GEN_INT (insv); | |
1805 | ||
1806 | emit_insn (gen_rtx_SET (VOIDmode, temp, | |
1807 | gen_rtx_HIGH (mode, operand1))); | |
1808 | emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1)); | |
1809 | emit_insn (gen_insv (operand0, GEN_INT (32), | |
1810 | const0_rtx, temp)); | |
1811 | } | |
1812 | else | |
1813 | { | |
1814 | int len = 5, pos = 27; | |
1815 | ||
1816 | /* Insert the bits using the depdi instruction. */ | |
1817 | while (pos >= 0) | |
1818 | { | |
1819 | HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16; | |
1820 | HOST_WIDE_INT sign = v5 < 0; | |
1821 | ||
1822 | /* Left extend the insertion. */ | |
1823 | insv = (insv >= 0 ? insv >> len : ~(~insv >> len)); | |
1824 | while (pos > 0 && (insv & 1) == sign) | |
1825 | { | |
1826 | insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1)); | |
1827 | len += 1; | |
1828 | pos -= 1; | |
1829 | } | |
1830 | ||
1831 | emit_insn (gen_insv (operand0, GEN_INT (len), | |
1832 | GEN_INT (pos), GEN_INT (v5))); | |
1833 | ||
1834 | len = pos > 0 && pos < 5 ? pos : 5; | |
1835 | pos -= len; | |
1836 | } | |
1837 | } | |
1838 | } | |
93f6e1c7 | 1839 | |
6bcdc1fb | 1840 | REG_NOTES (insn) |
1841 | = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn)); | |
93f6e1c7 | 1842 | |
5e3c5739 | 1843 | return 1; |
87ad11b0 | 1844 | } |
1845 | } | |
1846 | /* Now have insn-emit do whatever it normally does. */ | |
1847 | return 0; | |
1848 | } | |
1849 | ||
1946138e | 1850 | /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning |
bd49d362 | 1851 | it will need a link/runtime reloc). */ |
1946138e | 1852 | |
1853 | int | |
5c1d8983 | 1854 | reloc_needed (tree exp) |
1946138e | 1855 | { |
1856 | int reloc = 0; | |
1857 | ||
1858 | switch (TREE_CODE (exp)) | |
1859 | { | |
1860 | case ADDR_EXPR: | |
1861 | return 1; | |
1862 | ||
1863 | case PLUS_EXPR: | |
1864 | case MINUS_EXPR: | |
1865 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
1866 | reloc |= reloc_needed (TREE_OPERAND (exp, 1)); | |
1867 | break; | |
1868 | ||
1869 | case NOP_EXPR: | |
1870 | case CONVERT_EXPR: | |
1871 | case NON_LVALUE_EXPR: | |
1872 | reloc = reloc_needed (TREE_OPERAND (exp, 0)); | |
1873 | break; | |
1874 | ||
1875 | case CONSTRUCTOR: | |
1876 | { | |
1877 | register tree link; | |
1878 | for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link)) | |
1879 | if (TREE_VALUE (link) != 0) | |
1880 | reloc |= reloc_needed (TREE_VALUE (link)); | |
1881 | } | |
1882 | break; | |
1883 | ||
1884 | case ERROR_MARK: | |
1885 | break; | |
7d27e4c9 | 1886 | |
1887 | default: | |
1888 | break; | |
1946138e | 1889 | } |
1890 | return reloc; | |
1891 | } | |
1892 | ||
7811991d | 1893 | /* Does operand (which is a symbolic_operand) live in text space? |
1894 | If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info, | |
1895 | will be true. */ | |
87ad11b0 | 1896 | |
1897 | int | |
5c1d8983 | 1898 | read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED) |
87ad11b0 | 1899 | { |
1900 | if (GET_CODE (operand) == CONST) | |
1901 | operand = XEXP (XEXP (operand, 0), 0); | |
b4a7bf10 | 1902 | if (flag_pic) |
1903 | { | |
1904 | if (GET_CODE (operand) == SYMBOL_REF) | |
1905 | return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand); | |
1906 | } | |
1907 | else | |
1908 | { | |
1909 | if (GET_CODE (operand) == SYMBOL_REF) | |
1910 | return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand); | |
1911 | } | |
87ad11b0 | 1912 | return 1; |
1913 | } | |
6d36483b | 1914 | |
87ad11b0 | 1915 | \f |
1916 | /* Return the best assembler insn template | |
5aedf60c | 1917 | for moving operands[1] into operands[0] as a fullword. */ |
611a88e1 | 1918 | const char * |
5c1d8983 | 1919 | singlemove_string (rtx *operands) |
87ad11b0 | 1920 | { |
3745c59b | 1921 | HOST_WIDE_INT intval; |
1922 | ||
87ad11b0 | 1923 | if (GET_CODE (operands[0]) == MEM) |
1924 | return "stw %r1,%0"; | |
3745c59b | 1925 | if (GET_CODE (operands[1]) == MEM) |
87ad11b0 | 1926 | return "ldw %1,%0"; |
3745c59b | 1927 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
9d5108ea | 1928 | { |
3745c59b | 1929 | long i; |
1930 | REAL_VALUE_TYPE d; | |
9d5108ea | 1931 | |
ecf2283d | 1932 | gcc_assert (GET_MODE (operands[1]) == SFmode); |
9d5108ea | 1933 | |
3745c59b | 1934 | /* Translate the CONST_DOUBLE to a CONST_INT with the same target |
1935 | bit pattern. */ | |
1936 | REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]); | |
1937 | REAL_VALUE_TO_TARGET_SINGLE (d, i); | |
9d5108ea | 1938 | |
3745c59b | 1939 | operands[1] = GEN_INT (i); |
1940 | /* Fall through to CONST_INT case. */ | |
1941 | } | |
1942 | if (GET_CODE (operands[1]) == CONST_INT) | |
9d5108ea | 1943 | { |
3745c59b | 1944 | intval = INTVAL (operands[1]); |
1945 | ||
1946 | if (VAL_14_BITS_P (intval)) | |
1947 | return "ldi %1,%0"; | |
1948 | else if ((intval & 0x7ff) == 0) | |
1949 | return "ldil L'%1,%0"; | |
1950 | else if (zdepi_cint_p (intval)) | |
e4065f95 | 1951 | return "{zdepi %Z1,%0|depwi,z %Z1,%0}"; |
9d5108ea | 1952 | else |
1953 | return "ldil L'%1,%0\n\tldo R'%1(%0),%0"; | |
1954 | } | |
87ad11b0 | 1955 | return "copy %1,%0"; |
1956 | } | |
1957 | \f | |
1958 | ||
201f01e9 | 1959 | /* Compute position (in OP[1]) and width (in OP[2]) |
1960 | useful for copying IMM to a register using the zdepi | |
1961 | instructions. Store the immediate value to insert in OP[0]. */ | |
611a88e1 | 1962 | static void |
5c1d8983 | 1963 | compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
7e10ba53 | 1964 | { |
e057641f | 1965 | int lsb, len; |
7e10ba53 | 1966 | |
e057641f | 1967 | /* Find the least significant set bit in IMM. */ |
1968 | for (lsb = 0; lsb < 32; lsb++) | |
7e10ba53 | 1969 | { |
e057641f | 1970 | if ((imm & 1) != 0) |
7e10ba53 | 1971 | break; |
e057641f | 1972 | imm >>= 1; |
7e10ba53 | 1973 | } |
1974 | ||
e057641f | 1975 | /* Choose variants based on *sign* of the 5-bit field. */ |
1976 | if ((imm & 0x10) == 0) | |
1977 | len = (lsb <= 28) ? 4 : 32 - lsb; | |
7e10ba53 | 1978 | else |
1979 | { | |
e057641f | 1980 | /* Find the width of the bitstring in IMM. */ |
1981 | for (len = 5; len < 32; len++) | |
7e10ba53 | 1982 | { |
e057641f | 1983 | if ((imm & (1 << len)) == 0) |
7e10ba53 | 1984 | break; |
7e10ba53 | 1985 | } |
1986 | ||
e057641f | 1987 | /* Sign extend IMM as a 5-bit value. */ |
1988 | imm = (imm & 0xf) - 0x10; | |
7e10ba53 | 1989 | } |
1990 | ||
42faba01 | 1991 | op[0] = imm; |
1992 | op[1] = 31 - lsb; | |
1993 | op[2] = len; | |
7e10ba53 | 1994 | } |
1995 | ||
5e3c5739 | 1996 | /* Compute position (in OP[1]) and width (in OP[2]) |
1997 | useful for copying IMM to a register using the depdi,z | |
1998 | instructions. Store the immediate value to insert in OP[0]. */ | |
1999 | void | |
5c1d8983 | 2000 | compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op) |
5e3c5739 | 2001 | { |
2002 | HOST_WIDE_INT lsb, len; | |
2003 | ||
2004 | /* Find the least significant set bit in IMM. */ | |
2005 | for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++) | |
2006 | { | |
2007 | if ((imm & 1) != 0) | |
2008 | break; | |
2009 | imm >>= 1; | |
2010 | } | |
2011 | ||
2012 | /* Choose variants based on *sign* of the 5-bit field. */ | |
2013 | if ((imm & 0x10) == 0) | |
2014 | len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4) | |
2015 | ? 4 : HOST_BITS_PER_WIDE_INT - lsb); | |
2016 | else | |
2017 | { | |
2018 | /* Find the width of the bitstring in IMM. */ | |
2019 | for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++) | |
2020 | { | |
ea52c577 | 2021 | if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0) |
5e3c5739 | 2022 | break; |
2023 | } | |
2024 | ||
2025 | /* Sign extend IMM as a 5-bit value. */ | |
2026 | imm = (imm & 0xf) - 0x10; | |
2027 | } | |
2028 | ||
2029 | op[0] = imm; | |
2030 | op[1] = 63 - lsb; | |
2031 | op[2] = len; | |
2032 | } | |
2033 | ||
87ad11b0 | 2034 | /* Output assembler code to perform a doubleword move insn |
2035 | with operands OPERANDS. */ | |
2036 | ||
611a88e1 | 2037 | const char * |
5c1d8983 | 2038 | output_move_double (rtx *operands) |
87ad11b0 | 2039 | { |
2040 | enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1; | |
2041 | rtx latehalf[2]; | |
2042 | rtx addreg0 = 0, addreg1 = 0; | |
2043 | ||
2044 | /* First classify both operands. */ | |
2045 | ||
2046 | if (REG_P (operands[0])) | |
2047 | optype0 = REGOP; | |
2048 | else if (offsettable_memref_p (operands[0])) | |
2049 | optype0 = OFFSOP; | |
2050 | else if (GET_CODE (operands[0]) == MEM) | |
2051 | optype0 = MEMOP; | |
2052 | else | |
2053 | optype0 = RNDOP; | |
2054 | ||
2055 | if (REG_P (operands[1])) | |
2056 | optype1 = REGOP; | |
2057 | else if (CONSTANT_P (operands[1])) | |
2058 | optype1 = CNSTOP; | |
2059 | else if (offsettable_memref_p (operands[1])) | |
2060 | optype1 = OFFSOP; | |
2061 | else if (GET_CODE (operands[1]) == MEM) | |
2062 | optype1 = MEMOP; | |
2063 | else | |
2064 | optype1 = RNDOP; | |
2065 | ||
2066 | /* Check for the cases that the operand constraints are not | |
ecf2283d | 2067 | supposed to allow to happen. */ |
2068 | gcc_assert (optype0 == REGOP || optype1 == REGOP); | |
87ad11b0 | 2069 | |
2070 | /* Handle auto decrementing and incrementing loads and stores | |
2071 | specifically, since the structure of the function doesn't work | |
2072 | for them without major modification. Do it better when we learn | |
2073 | this port about the general inc/dec addressing of PA. | |
2074 | (This was written by tege. Chide him if it doesn't work.) */ | |
2075 | ||
2076 | if (optype0 == MEMOP) | |
2077 | { | |
1df0058a | 2078 | /* We have to output the address syntax ourselves, since print_operand |
2079 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2080 | ||
87ad11b0 | 2081 | rtx addr = XEXP (operands[0], 0); |
1df0058a | 2082 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) |
87ad11b0 | 2083 | { |
ad851752 | 2084 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2085 | |
2086 | operands[0] = XEXP (addr, 0); | |
ecf2283d | 2087 | gcc_assert (GET_CODE (operands[1]) == REG |
2088 | && GET_CODE (operands[0]) == REG); | |
1df0058a | 2089 | |
ecf2283d | 2090 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); |
2091 | ||
2092 | /* No overlap between high target register and address | |
2093 | register. (We do this in a non-obvious way to | |
2094 | save a register file writeback) */ | |
2095 | if (GET_CODE (addr) == POST_INC) | |
2096 | return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)"; | |
2097 | return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)"; | |
a3217f65 | 2098 | } |
1df0058a | 2099 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) |
a3217f65 | 2100 | { |
ad851752 | 2101 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0); |
1df0058a | 2102 | |
2103 | operands[0] = XEXP (addr, 0); | |
ecf2283d | 2104 | gcc_assert (GET_CODE (operands[1]) == REG |
2105 | && GET_CODE (operands[0]) == REG); | |
2106 | ||
2107 | gcc_assert (!reg_overlap_mentioned_p (high_reg, addr)); | |
2108 | /* No overlap between high target register and address | |
2109 | register. (We do this in a non-obvious way to save a | |
2110 | register file writeback) */ | |
2111 | if (GET_CODE (addr) == PRE_INC) | |
2112 | return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)"; | |
2113 | return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)"; | |
87ad11b0 | 2114 | } |
2115 | } | |
2116 | if (optype1 == MEMOP) | |
2117 | { | |
2118 | /* We have to output the address syntax ourselves, since print_operand | |
2119 | doesn't deal with the addresses we want to use. Fix this later. */ | |
2120 | ||
2121 | rtx addr = XEXP (operands[1], 0); | |
2122 | if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC) | |
2123 | { | |
ad851752 | 2124 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2125 | |
2126 | operands[1] = XEXP (addr, 0); | |
ecf2283d | 2127 | gcc_assert (GET_CODE (operands[0]) == REG |
2128 | && GET_CODE (operands[1]) == REG); | |
87ad11b0 | 2129 | |
2130 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2131 | { | |
2132 | /* No overlap between high target register and address | |
3857fa62 | 2133 | register. (We do this in a non-obvious way to |
87ad11b0 | 2134 | save a register file writeback) */ |
2135 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2136 | return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0"; |
01fd4b49 | 2137 | return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0"; |
87ad11b0 | 2138 | } |
2139 | else | |
2140 | { | |
2141 | /* This is an undefined situation. We should load into the | |
2142 | address register *and* update that register. Probably | |
2143 | we don't need to handle this at all. */ | |
2144 | if (GET_CODE (addr) == POST_INC) | |
e4065f95 | 2145 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0"; |
2146 | return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0"; | |
87ad11b0 | 2147 | } |
2148 | } | |
2149 | else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC) | |
2150 | { | |
ad851752 | 2151 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
87ad11b0 | 2152 | |
2153 | operands[1] = XEXP (addr, 0); | |
ecf2283d | 2154 | gcc_assert (GET_CODE (operands[0]) == REG |
2155 | && GET_CODE (operands[1]) == REG); | |
87ad11b0 | 2156 | |
2157 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2158 | { | |
2159 | /* No overlap between high target register and address | |
3857fa62 | 2160 | register. (We do this in a non-obvious way to |
87ad11b0 | 2161 | save a register file writeback) */ |
2162 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2163 | return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0"; |
2164 | return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0"; | |
87ad11b0 | 2165 | } |
2166 | else | |
2167 | { | |
2168 | /* This is an undefined situation. We should load into the | |
2169 | address register *and* update that register. Probably | |
2170 | we don't need to handle this at all. */ | |
2171 | if (GET_CODE (addr) == PRE_INC) | |
e4065f95 | 2172 | return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0"; |
2173 | return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0"; | |
87ad11b0 | 2174 | } |
2175 | } | |
12b02046 | 2176 | else if (GET_CODE (addr) == PLUS |
2177 | && GET_CODE (XEXP (addr, 0)) == MULT) | |
2178 | { | |
ad851752 | 2179 | rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0); |
12b02046 | 2180 | |
2181 | if (!reg_overlap_mentioned_p (high_reg, addr)) | |
2182 | { | |
2183 | rtx xoperands[3]; | |
2184 | ||
2185 | xoperands[0] = high_reg; | |
2186 | xoperands[1] = XEXP (addr, 1); | |
2187 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2188 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2189 | output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}", |
2190 | xoperands); | |
34940871 | 2191 | return "ldw 4(%0),%R0\n\tldw 0(%0),%0"; |
12b02046 | 2192 | } |
2193 | else | |
2194 | { | |
2195 | rtx xoperands[3]; | |
2196 | ||
2197 | xoperands[0] = high_reg; | |
2198 | xoperands[1] = XEXP (addr, 1); | |
2199 | xoperands[2] = XEXP (XEXP (addr, 0), 0); | |
2200 | xoperands[3] = XEXP (XEXP (addr, 0), 1); | |
e4065f95 | 2201 | output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}", |
2202 | xoperands); | |
34940871 | 2203 | return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0"; |
12b02046 | 2204 | } |
12b02046 | 2205 | } |
87ad11b0 | 2206 | } |
2207 | ||
2208 | /* If an operand is an unoffsettable memory ref, find a register | |
2209 | we can increment temporarily to make it refer to the second word. */ | |
2210 | ||
2211 | if (optype0 == MEMOP) | |
2212 | addreg0 = find_addr_reg (XEXP (operands[0], 0)); | |
2213 | ||
2214 | if (optype1 == MEMOP) | |
2215 | addreg1 = find_addr_reg (XEXP (operands[1], 0)); | |
2216 | ||
2217 | /* Ok, we can do one word at a time. | |
2218 | Normally we do the low-numbered word first. | |
2219 | ||
2220 | In either case, set up in LATEHALF the operands to use | |
2221 | for the high-numbered word and in some cases alter the | |
2222 | operands in OPERANDS to be suitable for the low-numbered word. */ | |
2223 | ||
2224 | if (optype0 == REGOP) | |
ad851752 | 2225 | latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); |
87ad11b0 | 2226 | else if (optype0 == OFFSOP) |
eafc6604 | 2227 | latehalf[0] = adjust_address (operands[0], SImode, 4); |
87ad11b0 | 2228 | else |
2229 | latehalf[0] = operands[0]; | |
2230 | ||
2231 | if (optype1 == REGOP) | |
ad851752 | 2232 | latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
87ad11b0 | 2233 | else if (optype1 == OFFSOP) |
eafc6604 | 2234 | latehalf[1] = adjust_address (operands[1], SImode, 4); |
87ad11b0 | 2235 | else if (optype1 == CNSTOP) |
2236 | split_double (operands[1], &operands[1], &latehalf[1]); | |
2237 | else | |
2238 | latehalf[1] = operands[1]; | |
2239 | ||
2240 | /* If the first move would clobber the source of the second one, | |
2241 | do them in the other order. | |
2242 | ||
cf489d53 | 2243 | This can happen in two cases: |
87ad11b0 | 2244 | |
cf489d53 | 2245 | mem -> register where the first half of the destination register |
2246 | is the same register used in the memory's address. Reload | |
2247 | can create such insns. | |
87ad11b0 | 2248 | |
cf489d53 | 2249 | mem in this case will be either register indirect or register |
9840d99d | 2250 | indirect plus a valid offset. |
cf489d53 | 2251 | |
2252 | register -> register move where REGNO(dst) == REGNO(src + 1) | |
9840d99d | 2253 | someone (Tim/Tege?) claimed this can happen for parameter loads. |
cf489d53 | 2254 | |
2255 | Handle mem -> register case first. */ | |
2256 | if (optype0 == REGOP | |
2257 | && (optype1 == MEMOP || optype1 == OFFSOP) | |
2258 | && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2259 | operands[1], 0)) | |
87ad11b0 | 2260 | { |
87ad11b0 | 2261 | /* Do the late half first. */ |
2262 | if (addreg1) | |
6a5d085a | 2263 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2264 | output_asm_insn (singlemove_string (latehalf), latehalf); |
cf489d53 | 2265 | |
2266 | /* Then clobber. */ | |
87ad11b0 | 2267 | if (addreg1) |
6a5d085a | 2268 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2269 | return singlemove_string (operands); |
2270 | } | |
2271 | ||
cf489d53 | 2272 | /* Now handle register -> register case. */ |
c4fa5937 | 2273 | if (optype0 == REGOP && optype1 == REGOP |
2274 | && REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
2275 | { | |
2276 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2277 | return singlemove_string (operands); | |
2278 | } | |
2279 | ||
87ad11b0 | 2280 | /* Normal case: do the two words, low-numbered first. */ |
2281 | ||
2282 | output_asm_insn (singlemove_string (operands), operands); | |
2283 | ||
2284 | /* Make any unoffsettable addresses point at high-numbered word. */ | |
2285 | if (addreg0) | |
6a5d085a | 2286 | output_asm_insn ("ldo 4(%0),%0", &addreg0); |
87ad11b0 | 2287 | if (addreg1) |
6a5d085a | 2288 | output_asm_insn ("ldo 4(%0),%0", &addreg1); |
87ad11b0 | 2289 | |
2290 | /* Do that word. */ | |
2291 | output_asm_insn (singlemove_string (latehalf), latehalf); | |
2292 | ||
2293 | /* Undo the adds we just did. */ | |
2294 | if (addreg0) | |
6a5d085a | 2295 | output_asm_insn ("ldo -4(%0),%0", &addreg0); |
87ad11b0 | 2296 | if (addreg1) |
6a5d085a | 2297 | output_asm_insn ("ldo -4(%0),%0", &addreg1); |
87ad11b0 | 2298 | |
2299 | return ""; | |
2300 | } | |
2301 | \f | |
611a88e1 | 2302 | const char * |
5c1d8983 | 2303 | output_fp_move_double (rtx *operands) |
87ad11b0 | 2304 | { |
2305 | if (FP_REG_P (operands[0])) | |
2306 | { | |
6d36483b | 2307 | if (FP_REG_P (operands[1]) |
891b55b4 | 2308 | || operands[1] == CONST0_RTX (GET_MODE (operands[0]))) |
c6ae275c | 2309 | output_asm_insn ("fcpy,dbl %f1,%0", operands); |
6d36483b | 2310 | else |
27ef382d | 2311 | output_asm_insn ("fldd%F1 %1,%0", operands); |
87ad11b0 | 2312 | } |
2313 | else if (FP_REG_P (operands[1])) | |
2314 | { | |
27ef382d | 2315 | output_asm_insn ("fstd%F0 %1,%0", operands); |
87ad11b0 | 2316 | } |
ecf2283d | 2317 | else |
891b55b4 | 2318 | { |
ecf2283d | 2319 | rtx xoperands[2]; |
2320 | ||
2321 | gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0]))); | |
2322 | ||
6d36483b | 2323 | /* This is a pain. You have to be prepared to deal with an |
01cc3b75 | 2324 | arbitrary address here including pre/post increment/decrement. |
891b55b4 | 2325 | |
2326 | so avoid this in the MD. */ | |
ecf2283d | 2327 | gcc_assert (GET_CODE (operands[0]) == REG); |
2328 | ||
2329 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); | |
2330 | xoperands[0] = operands[0]; | |
2331 | output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands); | |
891b55b4 | 2332 | } |
87ad11b0 | 2333 | return ""; |
2334 | } | |
2335 | \f | |
2336 | /* Return a REG that occurs in ADDR with coefficient 1. | |
2337 | ADDR can be effectively incremented by incrementing REG. */ | |
2338 | ||
2339 | static rtx | |
5c1d8983 | 2340 | find_addr_reg (rtx addr) |
87ad11b0 | 2341 | { |
2342 | while (GET_CODE (addr) == PLUS) | |
2343 | { | |
2344 | if (GET_CODE (XEXP (addr, 0)) == REG) | |
2345 | addr = XEXP (addr, 0); | |
2346 | else if (GET_CODE (XEXP (addr, 1)) == REG) | |
2347 | addr = XEXP (addr, 1); | |
2348 | else if (CONSTANT_P (XEXP (addr, 0))) | |
2349 | addr = XEXP (addr, 1); | |
2350 | else if (CONSTANT_P (XEXP (addr, 1))) | |
2351 | addr = XEXP (addr, 0); | |
2352 | else | |
ecf2283d | 2353 | gcc_unreachable (); |
87ad11b0 | 2354 | } |
ecf2283d | 2355 | gcc_assert (GET_CODE (addr) == REG); |
2356 | return addr; | |
87ad11b0 | 2357 | } |
2358 | ||
87ad11b0 | 2359 | /* Emit code to perform a block move. |
2360 | ||
87ad11b0 | 2361 | OPERANDS[0] is the destination pointer as a REG, clobbered. |
2362 | OPERANDS[1] is the source pointer as a REG, clobbered. | |
42819d4e | 2363 | OPERANDS[2] is a register for temporary storage. |
87ad11b0 | 2364 | OPERANDS[3] is a register for temporary storage. |
a7e1bb24 | 2365 | OPERANDS[4] is the size as a CONST_INT |
9840d99d | 2366 | OPERANDS[5] is the alignment safe to use, as a CONST_INT. |
5aedf60c | 2367 | OPERANDS[6] is another temporary register. */ |
87ad11b0 | 2368 | |
611a88e1 | 2369 | const char * |
5c1d8983 | 2370 | output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) |
87ad11b0 | 2371 | { |
2372 | int align = INTVAL (operands[5]); | |
42819d4e | 2373 | unsigned long n_bytes = INTVAL (operands[4]); |
87ad11b0 | 2374 | |
a7e1bb24 | 2375 | /* We can't move more than a word at a time because the PA |
87ad11b0 | 2376 | has no longer integer move insns. (Could use fp mem ops?) */ |
a7e1bb24 | 2377 | if (align > (TARGET_64BIT ? 8 : 4)) |
2378 | align = (TARGET_64BIT ? 8 : 4); | |
87ad11b0 | 2379 | |
42819d4e | 2380 | /* Note that we know each loop below will execute at least twice |
2381 | (else we would have open-coded the copy). */ | |
2382 | switch (align) | |
87ad11b0 | 2383 | { |
a7e1bb24 | 2384 | case 8: |
2385 | /* Pre-adjust the loop counter. */ | |
2386 | operands[4] = GEN_INT (n_bytes - 16); | |
2387 | output_asm_insn ("ldi %4,%2", operands); | |
2388 | ||
2389 | /* Copying loop. */ | |
2390 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2391 | output_asm_insn ("ldd,ma 8(%1),%6", operands); | |
2392 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2393 | output_asm_insn ("addib,>= -16,%2,.-12", operands); | |
2394 | output_asm_insn ("std,ma %6,8(%0)", operands); | |
2395 | ||
2396 | /* Handle the residual. There could be up to 7 bytes of | |
2397 | residual to copy! */ | |
2398 | if (n_bytes % 16 != 0) | |
2399 | { | |
2400 | operands[4] = GEN_INT (n_bytes % 8); | |
2401 | if (n_bytes % 16 >= 8) | |
2402 | output_asm_insn ("ldd,ma 8(%1),%3", operands); | |
2403 | if (n_bytes % 8 != 0) | |
2404 | output_asm_insn ("ldd 0(%1),%6", operands); | |
2405 | if (n_bytes % 16 >= 8) | |
2406 | output_asm_insn ("std,ma %3,8(%0)", operands); | |
2407 | if (n_bytes % 8 != 0) | |
2408 | output_asm_insn ("stdby,e %6,%4(%0)", operands); | |
2409 | } | |
2410 | return ""; | |
2411 | ||
42819d4e | 2412 | case 4: |
2413 | /* Pre-adjust the loop counter. */ | |
2414 | operands[4] = GEN_INT (n_bytes - 8); | |
2415 | output_asm_insn ("ldi %4,%2", operands); | |
2416 | ||
2417 | /* Copying loop. */ | |
e4065f95 | 2418 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
2419 | output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands); | |
2420 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); | |
42819d4e | 2421 | output_asm_insn ("addib,>= -8,%2,.-12", operands); |
e4065f95 | 2422 | output_asm_insn ("{stws|stw},ma %6,4(%0)", operands); |
42819d4e | 2423 | |
2424 | /* Handle the residual. There could be up to 7 bytes of | |
2425 | residual to copy! */ | |
2426 | if (n_bytes % 8 != 0) | |
2427 | { | |
2428 | operands[4] = GEN_INT (n_bytes % 4); | |
2429 | if (n_bytes % 8 >= 4) | |
e4065f95 | 2430 | output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands); |
42819d4e | 2431 | if (n_bytes % 4 != 0) |
34940871 | 2432 | output_asm_insn ("ldw 0(%1),%6", operands); |
42819d4e | 2433 | if (n_bytes % 8 >= 4) |
e4065f95 | 2434 | output_asm_insn ("{stws|stw},ma %3,4(%0)", operands); |
42819d4e | 2435 | if (n_bytes % 4 != 0) |
e4065f95 | 2436 | output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands); |
42819d4e | 2437 | } |
2438 | return ""; | |
87ad11b0 | 2439 | |
42819d4e | 2440 | case 2: |
2441 | /* Pre-adjust the loop counter. */ | |
2442 | operands[4] = GEN_INT (n_bytes - 4); | |
2443 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2444 | |
42819d4e | 2445 | /* Copying loop. */ |
e4065f95 | 2446 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
2447 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands); | |
2448 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); | |
42819d4e | 2449 | output_asm_insn ("addib,>= -4,%2,.-12", operands); |
e4065f95 | 2450 | output_asm_insn ("{sths|sth},ma %6,2(%0)", operands); |
87ad11b0 | 2451 | |
42819d4e | 2452 | /* Handle the residual. */ |
2453 | if (n_bytes % 4 != 0) | |
2454 | { | |
2455 | if (n_bytes % 4 >= 2) | |
e4065f95 | 2456 | output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands); |
42819d4e | 2457 | if (n_bytes % 2 != 0) |
34940871 | 2458 | output_asm_insn ("ldb 0(%1),%6", operands); |
42819d4e | 2459 | if (n_bytes % 4 >= 2) |
e4065f95 | 2460 | output_asm_insn ("{sths|sth},ma %3,2(%0)", operands); |
42819d4e | 2461 | if (n_bytes % 2 != 0) |
34940871 | 2462 | output_asm_insn ("stb %6,0(%0)", operands); |
42819d4e | 2463 | } |
2464 | return ""; | |
87ad11b0 | 2465 | |
42819d4e | 2466 | case 1: |
2467 | /* Pre-adjust the loop counter. */ | |
2468 | operands[4] = GEN_INT (n_bytes - 2); | |
2469 | output_asm_insn ("ldi %4,%2", operands); | |
87ad11b0 | 2470 | |
42819d4e | 2471 | /* Copying loop. */ |
e4065f95 | 2472 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands); |
2473 | output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands); | |
2474 | output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands); | |
42819d4e | 2475 | output_asm_insn ("addib,>= -2,%2,.-12", operands); |
e4065f95 | 2476 | output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands); |
87ad11b0 | 2477 | |
42819d4e | 2478 | /* Handle the residual. */ |
2479 | if (n_bytes % 2 != 0) | |
2480 | { | |
34940871 | 2481 | output_asm_insn ("ldb 0(%1),%3", operands); |
2482 | output_asm_insn ("stb %3,0(%0)", operands); | |
42819d4e | 2483 | } |
2484 | return ""; | |
87ad11b0 | 2485 | |
42819d4e | 2486 | default: |
ecf2283d | 2487 | gcc_unreachable (); |
87ad11b0 | 2488 | } |
87ad11b0 | 2489 | } |
58e17b0b | 2490 | |
2491 | /* Count the number of insns necessary to handle this block move. | |
2492 | ||
2493 | Basic structure is the same as emit_block_move, except that we | |
2494 | count insns rather than emit them. */ | |
2495 | ||
611a88e1 | 2496 | static int |
008c057d | 2497 | compute_movmem_length (rtx insn) |
58e17b0b | 2498 | { |
2499 | rtx pat = PATTERN (insn); | |
fc1fb057 | 2500 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0)); |
2501 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0)); | |
42819d4e | 2502 | unsigned int n_insns = 0; |
58e17b0b | 2503 | |
2504 | /* We can't move more than four bytes at a time because the PA | |
2505 | has no longer integer move insns. (Could use fp mem ops?) */ | |
a7e1bb24 | 2506 | if (align > (TARGET_64BIT ? 8 : 4)) |
2507 | align = (TARGET_64BIT ? 8 : 4); | |
58e17b0b | 2508 | |
79bfe6ae | 2509 | /* The basic copying loop. */ |
42819d4e | 2510 | n_insns = 6; |
58e17b0b | 2511 | |
42819d4e | 2512 | /* Residuals. */ |
2513 | if (n_bytes % (2 * align) != 0) | |
58e17b0b | 2514 | { |
79bfe6ae | 2515 | if ((n_bytes % (2 * align)) >= align) |
2516 | n_insns += 2; | |
2517 | ||
2518 | if ((n_bytes % align) != 0) | |
2519 | n_insns += 2; | |
58e17b0b | 2520 | } |
42819d4e | 2521 | |
2522 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2523 | return n_insns * 4; | |
58e17b0b | 2524 | } |
a7e1bb24 | 2525 | |
2526 | /* Emit code to perform a block clear. | |
2527 | ||
2528 | OPERANDS[0] is the destination pointer as a REG, clobbered. | |
2529 | OPERANDS[1] is a register for temporary storage. | |
2530 | OPERANDS[2] is the size as a CONST_INT | |
2531 | OPERANDS[3] is the alignment safe to use, as a CONST_INT. */ | |
2532 | ||
2533 | const char * | |
2534 | output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED) | |
2535 | { | |
2536 | int align = INTVAL (operands[3]); | |
2537 | unsigned long n_bytes = INTVAL (operands[2]); | |
2538 | ||
2539 | /* We can't clear more than a word at a time because the PA | |
2540 | has no longer integer move insns. */ | |
2541 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2542 | align = (TARGET_64BIT ? 8 : 4); | |
2543 | ||
2544 | /* Note that we know each loop below will execute at least twice | |
2545 | (else we would have open-coded the copy). */ | |
2546 | switch (align) | |
2547 | { | |
2548 | case 8: | |
2549 | /* Pre-adjust the loop counter. */ | |
2550 | operands[2] = GEN_INT (n_bytes - 16); | |
2551 | output_asm_insn ("ldi %2,%1", operands); | |
2552 | ||
2553 | /* Loop. */ | |
2554 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2555 | output_asm_insn ("addib,>= -16,%1,.-4", operands); | |
2556 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2557 | ||
2558 | /* Handle the residual. There could be up to 7 bytes of | |
2559 | residual to copy! */ | |
2560 | if (n_bytes % 16 != 0) | |
2561 | { | |
2562 | operands[2] = GEN_INT (n_bytes % 8); | |
2563 | if (n_bytes % 16 >= 8) | |
2564 | output_asm_insn ("std,ma %%r0,8(%0)", operands); | |
2565 | if (n_bytes % 8 != 0) | |
2566 | output_asm_insn ("stdby,e %%r0,%2(%0)", operands); | |
2567 | } | |
2568 | return ""; | |
2569 | ||
2570 | case 4: | |
2571 | /* Pre-adjust the loop counter. */ | |
2572 | operands[2] = GEN_INT (n_bytes - 8); | |
2573 | output_asm_insn ("ldi %2,%1", operands); | |
2574 | ||
2575 | /* Loop. */ | |
2576 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2577 | output_asm_insn ("addib,>= -8,%1,.-4", operands); | |
2578 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2579 | ||
2580 | /* Handle the residual. There could be up to 7 bytes of | |
2581 | residual to copy! */ | |
2582 | if (n_bytes % 8 != 0) | |
2583 | { | |
2584 | operands[2] = GEN_INT (n_bytes % 4); | |
2585 | if (n_bytes % 8 >= 4) | |
2586 | output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands); | |
2587 | if (n_bytes % 4 != 0) | |
2588 | output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands); | |
2589 | } | |
2590 | return ""; | |
2591 | ||
2592 | case 2: | |
2593 | /* Pre-adjust the loop counter. */ | |
2594 | operands[2] = GEN_INT (n_bytes - 4); | |
2595 | output_asm_insn ("ldi %2,%1", operands); | |
2596 | ||
2597 | /* Loop. */ | |
2598 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2599 | output_asm_insn ("addib,>= -4,%1,.-4", operands); | |
2600 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2601 | ||
2602 | /* Handle the residual. */ | |
2603 | if (n_bytes % 4 != 0) | |
2604 | { | |
2605 | if (n_bytes % 4 >= 2) | |
2606 | output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands); | |
2607 | if (n_bytes % 2 != 0) | |
2608 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2609 | } | |
2610 | return ""; | |
2611 | ||
2612 | case 1: | |
2613 | /* Pre-adjust the loop counter. */ | |
2614 | operands[2] = GEN_INT (n_bytes - 2); | |
2615 | output_asm_insn ("ldi %2,%1", operands); | |
2616 | ||
2617 | /* Loop. */ | |
2618 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2619 | output_asm_insn ("addib,>= -2,%1,.-4", operands); | |
2620 | output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands); | |
2621 | ||
2622 | /* Handle the residual. */ | |
2623 | if (n_bytes % 2 != 0) | |
2624 | output_asm_insn ("stb %%r0,0(%0)", operands); | |
2625 | ||
2626 | return ""; | |
2627 | ||
2628 | default: | |
ecf2283d | 2629 | gcc_unreachable (); |
a7e1bb24 | 2630 | } |
2631 | } | |
2632 | ||
2633 | /* Count the number of insns necessary to handle this block move. | |
2634 | ||
2635 | Basic structure is the same as emit_block_move, except that we | |
2636 | count insns rather than emit them. */ | |
2637 | ||
2638 | static int | |
008c057d | 2639 | compute_clrmem_length (rtx insn) |
a7e1bb24 | 2640 | { |
2641 | rtx pat = PATTERN (insn); | |
2642 | unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0)); | |
2643 | unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0)); | |
2644 | unsigned int n_insns = 0; | |
2645 | ||
2646 | /* We can't clear more than a word at a time because the PA | |
2647 | has no longer integer move insns. */ | |
2648 | if (align > (TARGET_64BIT ? 8 : 4)) | |
2649 | align = (TARGET_64BIT ? 8 : 4); | |
2650 | ||
2651 | /* The basic loop. */ | |
2652 | n_insns = 4; | |
2653 | ||
2654 | /* Residuals. */ | |
2655 | if (n_bytes % (2 * align) != 0) | |
2656 | { | |
2657 | if ((n_bytes % (2 * align)) >= align) | |
2658 | n_insns++; | |
2659 | ||
2660 | if ((n_bytes % align) != 0) | |
2661 | n_insns++; | |
2662 | } | |
2663 | ||
2664 | /* Lengths are expressed in bytes now; each insn is 4 bytes. */ | |
2665 | return n_insns * 4; | |
2666 | } | |
87ad11b0 | 2667 | \f |
2668 | ||
611a88e1 | 2669 | const char * |
5c1d8983 | 2670 | output_and (rtx *operands) |
e057641f | 2671 | { |
d6f01525 | 2672 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) |
e057641f | 2673 | { |
3745c59b | 2674 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
e057641f | 2675 | int ls0, ls1, ms0, p, len; |
2676 | ||
2677 | for (ls0 = 0; ls0 < 32; ls0++) | |
2678 | if ((mask & (1 << ls0)) == 0) | |
2679 | break; | |
2680 | ||
2681 | for (ls1 = ls0; ls1 < 32; ls1++) | |
2682 | if ((mask & (1 << ls1)) != 0) | |
2683 | break; | |
2684 | ||
2685 | for (ms0 = ls1; ms0 < 32; ms0++) | |
2686 | if ((mask & (1 << ms0)) == 0) | |
2687 | break; | |
2688 | ||
ecf2283d | 2689 | gcc_assert (ms0 == 32); |
e057641f | 2690 | |
2691 | if (ls1 == 32) | |
2692 | { | |
2693 | len = ls0; | |
2694 | ||
ecf2283d | 2695 | gcc_assert (len); |
e057641f | 2696 | |
ef618fe4 | 2697 | operands[2] = GEN_INT (len); |
e4065f95 | 2698 | return "{extru|extrw,u} %1,31,%2,%0"; |
e057641f | 2699 | } |
2700 | else | |
2701 | { | |
2702 | /* We could use this `depi' for the case above as well, but `depi' | |
2703 | requires one more register file access than an `extru'. */ | |
2704 | ||
2705 | p = 31 - ls0; | |
2706 | len = ls1 - ls0; | |
2707 | ||
ef618fe4 | 2708 | operands[2] = GEN_INT (p); |
2709 | operands[3] = GEN_INT (len); | |
e4065f95 | 2710 | return "{depi|depwi} 0,%2,%3,%0"; |
e057641f | 2711 | } |
2712 | } | |
2713 | else | |
2714 | return "and %1,%2,%0"; | |
2715 | } | |
2716 | ||
5e3c5739 | 2717 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] |
2718 | storing the result in operands[0]. */ | |
9aadea62 | 2719 | const char * |
5c1d8983 | 2720 | output_64bit_and (rtx *operands) |
5e3c5739 | 2721 | { |
2722 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0) | |
2723 | { | |
2724 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 2725 | int ls0, ls1, ms0, p, len; |
5e3c5739 | 2726 | |
2727 | for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++) | |
b7d86581 | 2728 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0) |
5e3c5739 | 2729 | break; |
2730 | ||
2731 | for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++) | |
b7d86581 | 2732 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0) |
5e3c5739 | 2733 | break; |
2734 | ||
2735 | for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++) | |
b7d86581 | 2736 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0) |
5e3c5739 | 2737 | break; |
2738 | ||
ecf2283d | 2739 | gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT); |
5e3c5739 | 2740 | |
2741 | if (ls1 == HOST_BITS_PER_WIDE_INT) | |
2742 | { | |
2743 | len = ls0; | |
2744 | ||
ecf2283d | 2745 | gcc_assert (len); |
5e3c5739 | 2746 | |
2747 | operands[2] = GEN_INT (len); | |
2748 | return "extrd,u %1,63,%2,%0"; | |
2749 | } | |
2750 | else | |
2751 | { | |
2752 | /* We could use this `depi' for the case above as well, but `depi' | |
2753 | requires one more register file access than an `extru'. */ | |
2754 | ||
2755 | p = 63 - ls0; | |
2756 | len = ls1 - ls0; | |
2757 | ||
2758 | operands[2] = GEN_INT (p); | |
2759 | operands[3] = GEN_INT (len); | |
2760 | return "depdi 0,%2,%3,%0"; | |
2761 | } | |
2762 | } | |
2763 | else | |
2764 | return "and %1,%2,%0"; | |
2765 | } | |
2766 | ||
611a88e1 | 2767 | const char * |
5c1d8983 | 2768 | output_ior (rtx *operands) |
e057641f | 2769 | { |
3745c59b | 2770 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); |
57ed30e5 | 2771 | int bs0, bs1, p, len; |
6d36483b | 2772 | |
c9da5f4d | 2773 | if (INTVAL (operands[2]) == 0) |
2774 | return "copy %1,%0"; | |
e057641f | 2775 | |
c9da5f4d | 2776 | for (bs0 = 0; bs0 < 32; bs0++) |
2777 | if ((mask & (1 << bs0)) != 0) | |
2778 | break; | |
e057641f | 2779 | |
c9da5f4d | 2780 | for (bs1 = bs0; bs1 < 32; bs1++) |
2781 | if ((mask & (1 << bs1)) == 0) | |
2782 | break; | |
e057641f | 2783 | |
ecf2283d | 2784 | gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); |
e057641f | 2785 | |
c9da5f4d | 2786 | p = 31 - bs0; |
2787 | len = bs1 - bs0; | |
e057641f | 2788 | |
ef618fe4 | 2789 | operands[2] = GEN_INT (p); |
2790 | operands[3] = GEN_INT (len); | |
e4065f95 | 2791 | return "{depi|depwi} -1,%2,%3,%0"; |
e057641f | 2792 | } |
5e3c5739 | 2793 | |
2794 | /* Return a string to perform a bitwise-and of operands[1] with operands[2] | |
2795 | storing the result in operands[0]. */ | |
9aadea62 | 2796 | const char * |
5c1d8983 | 2797 | output_64bit_ior (rtx *operands) |
5e3c5739 | 2798 | { |
2799 | unsigned HOST_WIDE_INT mask = INTVAL (operands[2]); | |
b7d86581 | 2800 | int bs0, bs1, p, len; |
5e3c5739 | 2801 | |
2802 | if (INTVAL (operands[2]) == 0) | |
2803 | return "copy %1,%0"; | |
2804 | ||
2805 | for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++) | |
b7d86581 | 2806 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0) |
5e3c5739 | 2807 | break; |
2808 | ||
2809 | for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++) | |
b7d86581 | 2810 | if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0) |
5e3c5739 | 2811 | break; |
2812 | ||
ecf2283d | 2813 | gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT |
2814 | || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask); | |
5e3c5739 | 2815 | |
2816 | p = 63 - bs0; | |
2817 | len = bs1 - bs0; | |
2818 | ||
2819 | operands[2] = GEN_INT (p); | |
2820 | operands[3] = GEN_INT (len); | |
2821 | return "depdi -1,%2,%3,%0"; | |
2822 | } | |
e057641f | 2823 | \f |
58356836 | 2824 | /* Target hook for assembling integer objects. This code handles |
e678758c | 2825 | aligned SI and DI integers specially since function references |
2826 | must be preceded by P%. */ | |
58356836 | 2827 | |
2828 | static bool | |
5c1d8983 | 2829 | pa_assemble_integer (rtx x, unsigned int size, int aligned_p) |
58356836 | 2830 | { |
e678758c | 2831 | if (size == UNITS_PER_WORD |
2832 | && aligned_p | |
58356836 | 2833 | && function_label_operand (x, VOIDmode)) |
2834 | { | |
2835 | fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file); | |
2836 | output_addr_const (asm_out_file, x); | |
2837 | fputc ('\n', asm_out_file); | |
2838 | return true; | |
2839 | } | |
2840 | return default_assemble_integer (x, size, aligned_p); | |
2841 | } | |
2842 | \f | |
87ad11b0 | 2843 | /* Output an ascii string. */ |
57ed30e5 | 2844 | void |
5c1d8983 | 2845 | output_ascii (FILE *file, const char *p, int size) |
87ad11b0 | 2846 | { |
2847 | int i; | |
2848 | int chars_output; | |
5aedf60c | 2849 | unsigned char partial_output[16]; /* Max space 4 chars can occupy. */ |
87ad11b0 | 2850 | |
2851 | /* The HP assembler can only take strings of 256 characters at one | |
2852 | time. This is a limitation on input line length, *not* the | |
2853 | length of the string. Sigh. Even worse, it seems that the | |
2854 | restriction is in number of input characters (see \xnn & | |
2855 | \whatever). So we have to do this very carefully. */ | |
2856 | ||
9c0ac0fd | 2857 | fputs ("\t.STRING \"", file); |
87ad11b0 | 2858 | |
2859 | chars_output = 0; | |
2860 | for (i = 0; i < size; i += 4) | |
2861 | { | |
2862 | int co = 0; | |
2863 | int io = 0; | |
2864 | for (io = 0, co = 0; io < MIN (4, size - i); io++) | |
2865 | { | |
bf8aac3e | 2866 | register unsigned int c = (unsigned char) p[i + io]; |
87ad11b0 | 2867 | |
2868 | if (c == '\"' || c == '\\') | |
2869 | partial_output[co++] = '\\'; | |
2870 | if (c >= ' ' && c < 0177) | |
2871 | partial_output[co++] = c; | |
2872 | else | |
2873 | { | |
2874 | unsigned int hexd; | |
2875 | partial_output[co++] = '\\'; | |
2876 | partial_output[co++] = 'x'; | |
2877 | hexd = c / 16 - 0 + '0'; | |
2878 | if (hexd > '9') | |
2879 | hexd -= '9' - 'a' + 1; | |
2880 | partial_output[co++] = hexd; | |
2881 | hexd = c % 16 - 0 + '0'; | |
2882 | if (hexd > '9') | |
2883 | hexd -= '9' - 'a' + 1; | |
2884 | partial_output[co++] = hexd; | |
2885 | } | |
2886 | } | |
2887 | if (chars_output + co > 243) | |
2888 | { | |
9c0ac0fd | 2889 | fputs ("\"\n\t.STRING \"", file); |
87ad11b0 | 2890 | chars_output = 0; |
2891 | } | |
a584fe8a | 2892 | fwrite (partial_output, 1, (size_t) co, file); |
87ad11b0 | 2893 | chars_output += co; |
2894 | co = 0; | |
2895 | } | |
9c0ac0fd | 2896 | fputs ("\"\n", file); |
87ad11b0 | 2897 | } |
c533da59 | 2898 | |
2899 | /* Try to rewrite floating point comparisons & branches to avoid | |
2900 | useless add,tr insns. | |
2901 | ||
2902 | CHECK_NOTES is nonzero if we should examine REG_DEAD notes | |
2903 | to see if FPCC is dead. CHECK_NOTES is nonzero for the | |
2904 | first attempt to remove useless add,tr insns. It is zero | |
2905 | for the second pass as reorg sometimes leaves bogus REG_DEAD | |
2906 | notes lying around. | |
2907 | ||
2908 | When CHECK_NOTES is zero we can only eliminate add,tr insns | |
2909 | when there's a 1:1 correspondence between fcmp and ftest/fbranch | |
2910 | instructions. */ | |
611a88e1 | 2911 | static void |
5c1d8983 | 2912 | remove_useless_addtr_insns (int check_notes) |
c533da59 | 2913 | { |
2914 | rtx insn; | |
c533da59 | 2915 | static int pass = 0; |
2916 | ||
2917 | /* This is fairly cheap, so always run it when optimizing. */ | |
2918 | if (optimize > 0) | |
2919 | { | |
2920 | int fcmp_count = 0; | |
2921 | int fbranch_count = 0; | |
2922 | ||
2923 | /* Walk all the insns in this function looking for fcmp & fbranch | |
2924 | instructions. Keep track of how many of each we find. */ | |
2efea8c0 | 2925 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 2926 | { |
2927 | rtx tmp; | |
2928 | ||
2929 | /* Ignore anything that isn't an INSN or a JUMP_INSN. */ | |
2930 | if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN) | |
2931 | continue; | |
2932 | ||
2933 | tmp = PATTERN (insn); | |
2934 | ||
2935 | /* It must be a set. */ | |
2936 | if (GET_CODE (tmp) != SET) | |
2937 | continue; | |
2938 | ||
2939 | /* If the destination is CCFP, then we've found an fcmp insn. */ | |
2940 | tmp = SET_DEST (tmp); | |
2941 | if (GET_CODE (tmp) == REG && REGNO (tmp) == 0) | |
2942 | { | |
2943 | fcmp_count++; | |
2944 | continue; | |
2945 | } | |
9840d99d | 2946 | |
c533da59 | 2947 | tmp = PATTERN (insn); |
2948 | /* If this is an fbranch instruction, bump the fbranch counter. */ | |
2949 | if (GET_CODE (tmp) == SET | |
2950 | && SET_DEST (tmp) == pc_rtx | |
2951 | && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE | |
2952 | && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE | |
2953 | && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG | |
2954 | && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0) | |
2955 | { | |
2956 | fbranch_count++; | |
2957 | continue; | |
2958 | } | |
2959 | } | |
2960 | ||
2961 | ||
2962 | /* Find all floating point compare + branch insns. If possible, | |
2963 | reverse the comparison & the branch to avoid add,tr insns. */ | |
2efea8c0 | 2964 | for (insn = get_insns (); insn; insn = next_insn (insn)) |
c533da59 | 2965 | { |
2966 | rtx tmp, next; | |
2967 | ||
2968 | /* Ignore anything that isn't an INSN. */ | |
2969 | if (GET_CODE (insn) != INSN) | |
2970 | continue; | |
2971 | ||
2972 | tmp = PATTERN (insn); | |
2973 | ||
2974 | /* It must be a set. */ | |
2975 | if (GET_CODE (tmp) != SET) | |
2976 | continue; | |
2977 | ||
2978 | /* The destination must be CCFP, which is register zero. */ | |
2979 | tmp = SET_DEST (tmp); | |
2980 | if (GET_CODE (tmp) != REG || REGNO (tmp) != 0) | |
2981 | continue; | |
2982 | ||
2983 | /* INSN should be a set of CCFP. | |
2984 | ||
2985 | See if the result of this insn is used in a reversed FP | |
2986 | conditional branch. If so, reverse our condition and | |
2987 | the branch. Doing so avoids useless add,tr insns. */ | |
2988 | next = next_insn (insn); | |
2989 | while (next) | |
2990 | { | |
2991 | /* Jumps, calls and labels stop our search. */ | |
2992 | if (GET_CODE (next) == JUMP_INSN | |
2993 | || GET_CODE (next) == CALL_INSN | |
2994 | || GET_CODE (next) == CODE_LABEL) | |
2995 | break; | |
2996 | ||
2997 | /* As does another fcmp insn. */ | |
2998 | if (GET_CODE (next) == INSN | |
2999 | && GET_CODE (PATTERN (next)) == SET | |
3000 | && GET_CODE (SET_DEST (PATTERN (next))) == REG | |
3001 | && REGNO (SET_DEST (PATTERN (next))) == 0) | |
3002 | break; | |
3003 | ||
3004 | next = next_insn (next); | |
3005 | } | |
3006 | ||
3007 | /* Is NEXT_INSN a branch? */ | |
3008 | if (next | |
3009 | && GET_CODE (next) == JUMP_INSN) | |
3010 | { | |
3011 | rtx pattern = PATTERN (next); | |
3012 | ||
a361b456 | 3013 | /* If it a reversed fp conditional branch (e.g. uses add,tr) |
c533da59 | 3014 | and CCFP dies, then reverse our conditional and the branch |
3015 | to avoid the add,tr. */ | |
3016 | if (GET_CODE (pattern) == SET | |
3017 | && SET_DEST (pattern) == pc_rtx | |
3018 | && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE | |
3019 | && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE | |
3020 | && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG | |
3021 | && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0 | |
3022 | && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC | |
3023 | && (fcmp_count == fbranch_count | |
3024 | || (check_notes | |
3025 | && find_regno_note (next, REG_DEAD, 0)))) | |
3026 | { | |
3027 | /* Reverse the branch. */ | |
3028 | tmp = XEXP (SET_SRC (pattern), 1); | |
3029 | XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2); | |
3030 | XEXP (SET_SRC (pattern), 2) = tmp; | |
3031 | INSN_CODE (next) = -1; | |
3032 | ||
3033 | /* Reverse our condition. */ | |
3034 | tmp = PATTERN (insn); | |
3035 | PUT_CODE (XEXP (tmp, 1), | |
ea52c577 | 3036 | (reverse_condition_maybe_unordered |
3037 | (GET_CODE (XEXP (tmp, 1))))); | |
c533da59 | 3038 | } |
3039 | } | |
3040 | } | |
3041 | } | |
3042 | ||
3043 | pass = !pass; | |
3044 | ||
3045 | } | |
87ad11b0 | 3046 | \f |
ea52c577 | 3047 | /* You may have trouble believing this, but this is the 32 bit HP-PA |
3048 | stack layout. Wow. | |
87ad11b0 | 3049 | |
3050 | Offset Contents | |
3051 | ||
3052 | Variable arguments (optional; any number may be allocated) | |
3053 | ||
3054 | SP-(4*(N+9)) arg word N | |
3055 | : : | |
3056 | SP-56 arg word 5 | |
3057 | SP-52 arg word 4 | |
3058 | ||
3059 | Fixed arguments (must be allocated; may remain unused) | |
3060 | ||
3061 | SP-48 arg word 3 | |
3062 | SP-44 arg word 2 | |
3063 | SP-40 arg word 1 | |
3064 | SP-36 arg word 0 | |
3065 | ||
3066 | Frame Marker | |
3067 | ||
3068 | SP-32 External Data Pointer (DP) | |
3069 | SP-28 External sr4 | |
3070 | SP-24 External/stub RP (RP') | |
3071 | SP-20 Current RP | |
3072 | SP-16 Static Link | |
3073 | SP-12 Clean up | |
3074 | SP-8 Calling Stub RP (RP'') | |
3075 | SP-4 Previous SP | |
3076 | ||
3077 | Top of Frame | |
3078 | ||
3079 | SP-0 Stack Pointer (points to next available address) | |
3080 | ||
3081 | */ | |
3082 | ||
3083 | /* This function saves registers as follows. Registers marked with ' are | |
3084 | this function's registers (as opposed to the previous function's). | |
3085 | If a frame_pointer isn't needed, r4 is saved as a general register; | |
3086 | the space for the frame pointer is still allocated, though, to keep | |
3087 | things simple. | |
3088 | ||
3089 | ||
3090 | Top of Frame | |
3091 | ||
3092 | SP (FP') Previous FP | |
3093 | SP + 4 Alignment filler (sigh) | |
3094 | SP + 8 Space for locals reserved here. | |
3095 | . | |
3096 | . | |
3097 | . | |
3098 | SP + n All call saved register used. | |
3099 | . | |
3100 | . | |
3101 | . | |
3102 | SP + o All call saved fp registers used. | |
3103 | . | |
3104 | . | |
3105 | . | |
3106 | SP + p (SP') points to next available address. | |
6d36483b | 3107 | |
87ad11b0 | 3108 | */ |
3109 | ||
17d9b0c3 | 3110 | /* Global variables set by output_function_prologue(). */ |
cc858176 | 3111 | /* Size of frame. Need to know this to emit return insns from |
3112 | leaf procedures. */ | |
6bcdc1fb | 3113 | static HOST_WIDE_INT actual_fsize, local_fsize; |
3114 | static int save_fregs; | |
cc858176 | 3115 | |
daee63dd | 3116 | /* Emit RTL to store REG at the memory location specified by BASE+DISP. |
359a0be8 | 3117 | Handle case where DISP > 8k by using the add_high_const patterns. |
daee63dd | 3118 | |
3119 | Note in DISP > 8k case, we will leave the high part of the address | |
3120 | in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/ | |
7014838c | 3121 | |
6a2c16d6 | 3122 | static void |
6bcdc1fb | 3123 | store_reg (int reg, HOST_WIDE_INT disp, int base) |
87ad11b0 | 3124 | { |
6a2c16d6 | 3125 | rtx insn, dest, src, basereg; |
cc858176 | 3126 | |
3127 | src = gen_rtx_REG (word_mode, reg); | |
3128 | basereg = gen_rtx_REG (Pmode, base); | |
87ad11b0 | 3129 | if (VAL_14_BITS_P (disp)) |
daee63dd | 3130 | { |
cc858176 | 3131 | dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
6a2c16d6 | 3132 | insn = emit_move_insn (dest, src); |
daee63dd | 3133 | } |
6bcdc1fb | 3134 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3135 | { | |
3136 | rtx delta = GEN_INT (disp); | |
3137 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3138 | ||
3139 | emit_move_insn (tmpreg, delta); | |
3140 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
3141 | dest = gen_rtx_MEM (word_mode, tmpreg); | |
3142 | insn = emit_move_insn (dest, src); | |
3143 | if (DO_FRAME_NOTES) | |
3144 | { | |
3145 | REG_NOTES (insn) | |
3146 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3147 | gen_rtx_SET (VOIDmode, | |
3148 | gen_rtx_MEM (word_mode, | |
3149 | gen_rtx_PLUS (word_mode, basereg, | |
3150 | delta)), | |
3151 | src), | |
3152 | REG_NOTES (insn)); | |
3153 | } | |
3154 | } | |
daee63dd | 3155 | else |
3156 | { | |
cc858176 | 3157 | rtx delta = GEN_INT (disp); |
3158 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3159 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 3160 | |
cc858176 | 3161 | emit_move_insn (tmpreg, high); |
3162 | dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
6a2c16d6 | 3163 | insn = emit_move_insn (dest, src); |
3164 | if (DO_FRAME_NOTES) | |
3165 | { | |
3166 | REG_NOTES (insn) | |
3167 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3168 | gen_rtx_SET (VOIDmode, | |
3169 | gen_rtx_MEM (word_mode, | |
3170 | gen_rtx_PLUS (word_mode, basereg, | |
3171 | delta)), | |
3172 | src), | |
3173 | REG_NOTES (insn)); | |
3174 | } | |
daee63dd | 3175 | } |
6a2c16d6 | 3176 | |
3177 | if (DO_FRAME_NOTES) | |
3178 | RTX_FRAME_RELATED_P (insn) = 1; | |
daee63dd | 3179 | } |
3180 | ||
a584fe8a | 3181 | /* Emit RTL to store REG at the memory location specified by BASE and then |
3182 | add MOD to BASE. MOD must be <= 8k. */ | |
daee63dd | 3183 | |
a584fe8a | 3184 | static void |
6bcdc1fb | 3185 | store_reg_modify (int base, int reg, HOST_WIDE_INT mod) |
a584fe8a | 3186 | { |
3187 | rtx insn, basereg, srcreg, delta; | |
3188 | ||
ecf2283d | 3189 | gcc_assert (VAL_14_BITS_P (mod)); |
a584fe8a | 3190 | |
3191 | basereg = gen_rtx_REG (Pmode, base); | |
3192 | srcreg = gen_rtx_REG (word_mode, reg); | |
3193 | delta = GEN_INT (mod); | |
3194 | ||
3195 | insn = emit_insn (gen_post_store (basereg, srcreg, delta)); | |
3196 | if (DO_FRAME_NOTES) | |
3197 | { | |
3198 | RTX_FRAME_RELATED_P (insn) = 1; | |
3199 | ||
3200 | /* RTX_FRAME_RELATED_P must be set on each frame related set | |
3201 | in a parallel with more than one element. Don't set | |
3202 | RTX_FRAME_RELATED_P in the first set if reg is temporary | |
3203 | register 1. The effect of this operation is recorded in | |
3204 | the initial copy. */ | |
3205 | if (reg != 1) | |
3206 | { | |
3207 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1; | |
3208 | RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1; | |
3209 | } | |
3210 | else | |
3211 | { | |
3212 | /* The first element of a PARALLEL is always processed if it is | |
3213 | a SET. Thus, we need an expression list for this case. */ | |
3214 | REG_NOTES (insn) | |
3215 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3216 | gen_rtx_SET (VOIDmode, basereg, | |
3217 | gen_rtx_PLUS (word_mode, basereg, delta)), | |
3218 | REG_NOTES (insn)); | |
3219 | } | |
3220 | } | |
3221 | } | |
3222 | ||
3223 | /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case | |
3224 | where DISP > 8k by using the add_high_const patterns. NOTE indicates | |
3225 | whether to add a frame note or not. | |
3226 | ||
3227 | In the DISP > 8k case, we leave the high part of the address in %r1. | |
3228 | There is code in expand_hppa_{prologue,epilogue} that knows about this. */ | |
7014838c | 3229 | |
6a2c16d6 | 3230 | static void |
6bcdc1fb | 3231 | set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note) |
87ad11b0 | 3232 | { |
6a2c16d6 | 3233 | rtx insn; |
cc858176 | 3234 | |
87ad11b0 | 3235 | if (VAL_14_BITS_P (disp)) |
cc858176 | 3236 | { |
6a2c16d6 | 3237 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
3238 | plus_constant (gen_rtx_REG (Pmode, base), disp)); | |
cc858176 | 3239 | } |
6bcdc1fb | 3240 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) |
3241 | { | |
3242 | rtx basereg = gen_rtx_REG (Pmode, base); | |
3243 | rtx delta = GEN_INT (disp); | |
3244 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3245 | ||
3246 | emit_move_insn (tmpreg, delta); | |
3247 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), | |
3248 | gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
3249 | } | |
87ad11b0 | 3250 | else |
daee63dd | 3251 | { |
6a2c16d6 | 3252 | rtx basereg = gen_rtx_REG (Pmode, base); |
cc858176 | 3253 | rtx delta = GEN_INT (disp); |
6bcdc1fb | 3254 | rtx tmpreg = gen_rtx_REG (Pmode, 1); |
6a2c16d6 | 3255 | |
6bcdc1fb | 3256 | emit_move_insn (tmpreg, |
6a2c16d6 | 3257 | gen_rtx_PLUS (Pmode, basereg, |
cc858176 | 3258 | gen_rtx_HIGH (Pmode, delta))); |
6a2c16d6 | 3259 | insn = emit_move_insn (gen_rtx_REG (Pmode, reg), |
6bcdc1fb | 3260 | gen_rtx_LO_SUM (Pmode, tmpreg, delta)); |
daee63dd | 3261 | } |
6a2c16d6 | 3262 | |
a584fe8a | 3263 | if (DO_FRAME_NOTES && note) |
6a2c16d6 | 3264 | RTX_FRAME_RELATED_P (insn) = 1; |
87ad11b0 | 3265 | } |
3266 | ||
6bcdc1fb | 3267 | HOST_WIDE_INT |
3268 | compute_frame_size (HOST_WIDE_INT size, int *fregs_live) | |
87ad11b0 | 3269 | { |
256f9b65 | 3270 | int freg_saved = 0; |
3271 | int i, j; | |
3272 | ||
3273 | /* The code in hppa_expand_prologue and hppa_expand_epilogue must | |
3274 | be consistent with the rounding and size calculation done here. | |
3275 | Change them at the same time. */ | |
3276 | ||
3277 | /* We do our own stack alignment. First, round the size of the | |
3278 | stack locals up to a word boundary. */ | |
3279 | size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3280 | ||
3281 | /* Space for previous frame pointer + filler. If any frame is | |
3282 | allocated, we need to add in the STARTING_FRAME_OFFSET. We | |
3283 | waste some space here for the sake of HP compatibility. The | |
3284 | first slot is only used when the frame pointer is needed. */ | |
3285 | if (size || frame_pointer_needed) | |
3286 | size += STARTING_FRAME_OFFSET; | |
3287 | ||
a584fe8a | 3288 | /* If the current function calls __builtin_eh_return, then we need |
3289 | to allocate stack space for registers that will hold data for | |
3290 | the exception handler. */ | |
3291 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3292 | { | |
3293 | unsigned int i; | |
3294 | ||
3295 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) | |
3296 | continue; | |
256f9b65 | 3297 | size += i * UNITS_PER_WORD; |
a584fe8a | 3298 | } |
3299 | ||
3a51bad9 | 3300 | /* Account for space used by the callee general register saves. */ |
256f9b65 | 3301 | for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--) |
7f7c4869 | 3302 | if (regs_ever_live[i]) |
256f9b65 | 3303 | size += UNITS_PER_WORD; |
df0651dc | 3304 | |
3a51bad9 | 3305 | /* Account for space used by the callee floating point register saves. */ |
bac38c40 | 3306 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
5e3c5739 | 3307 | if (regs_ever_live[i] |
256f9b65 | 3308 | || (!TARGET_64BIT && regs_ever_live[i + 1])) |
df0651dc | 3309 | { |
256f9b65 | 3310 | freg_saved = 1; |
002fc5f7 | 3311 | |
3a51bad9 | 3312 | /* We always save both halves of the FP register, so always |
3313 | increment the frame size by 8 bytes. */ | |
256f9b65 | 3314 | size += 8; |
df0651dc | 3315 | } |
3316 | ||
256f9b65 | 3317 | /* If any of the floating registers are saved, account for the |
3318 | alignment needed for the floating point register save block. */ | |
3319 | if (freg_saved) | |
3320 | { | |
3321 | size = (size + 7) & ~7; | |
3322 | if (fregs_live) | |
3323 | *fregs_live = 1; | |
3324 | } | |
3325 | ||
3a51bad9 | 3326 | /* The various ABIs include space for the outgoing parameters in the |
256f9b65 | 3327 | size of the current function's stack frame. We don't need to align |
3328 | for the outgoing arguments as their alignment is set by the final | |
3329 | rounding for the frame as a whole. */ | |
3330 | size += current_function_outgoing_args_size; | |
3a51bad9 | 3331 | |
3332 | /* Allocate space for the fixed frame marker. This space must be | |
e9ec370e | 3333 | allocated for any function that makes calls or allocates |
3a51bad9 | 3334 | stack space. */ |
256f9b65 | 3335 | if (!current_function_is_leaf || size) |
e9ec370e | 3336 | size += TARGET_64BIT ? 48 : 32; |
5e3c5739 | 3337 | |
256f9b65 | 3338 | /* Finally, round to the preferred stack boundary. */ |
2247cc5f | 3339 | return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1) |
3340 | & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
87ad11b0 | 3341 | } |
6d36483b | 3342 | |
17d9b0c3 | 3343 | /* Generate the assembly code for function entry. FILE is a stdio |
3344 | stream to output the code to. SIZE is an int: how many units of | |
3345 | temporary storage to allocate. | |
3346 | ||
3347 | Refer to the array `regs_ever_live' to determine which registers to | |
3348 | save; `regs_ever_live[I]' is nonzero if register number I is ever | |
3349 | used in the function. This function is responsible for knowing | |
3350 | which registers should not be saved even if used. */ | |
3351 | ||
3352 | /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block | |
3353 | of memory. If any fpu reg is used in the function, we allocate | |
3354 | such a block here, at the bottom of the frame, just in case it's needed. | |
3355 | ||
3356 | If this function is a leaf procedure, then we may choose not | |
3357 | to do a "save" insn. The decision about whether or not | |
3358 | to do this is made in regclass.c. */ | |
3359 | ||
6988553d | 3360 | static void |
5c1d8983 | 3361 | pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 3362 | { |
d151162a | 3363 | /* The function's label and associated .PROC must never be |
3364 | separated and must be output *after* any profiling declarations | |
3365 | to avoid changing spaces/subspaces within a procedure. */ | |
3366 | ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); | |
3367 | fputs ("\t.PROC\n", file); | |
3368 | ||
daee63dd | 3369 | /* hppa_expand_prologue does the dirty work now. We just need |
3370 | to output the assembler directives which denote the start | |
3371 | of a function. */ | |
6bcdc1fb | 3372 | fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize); |
df6edefa | 3373 | if (regs_ever_live[2]) |
9c0ac0fd | 3374 | fputs (",CALLS,SAVE_RP", file); |
daee63dd | 3375 | else |
9c0ac0fd | 3376 | fputs (",NO_CALLS", file); |
f3ba7709 | 3377 | |
e9ec370e | 3378 | /* The SAVE_SP flag is used to indicate that register %r3 is stored |
3379 | at the beginning of the frame and that it is used as the frame | |
3380 | pointer for the frame. We do this because our current frame | |
3381 | layout doesn't conform to that specified in the the HP runtime | |
3382 | documentation and we need a way to indicate to programs such as | |
3383 | GDB where %r3 is saved. The SAVE_SP flag was chosen because it | |
3384 | isn't used by HP compilers but is supported by the assembler. | |
3385 | However, SAVE_SP is supposed to indicate that the previous stack | |
3386 | pointer has been saved in the frame marker. */ | |
f3ba7709 | 3387 | if (frame_pointer_needed) |
9c0ac0fd | 3388 | fputs (",SAVE_SP", file); |
f3ba7709 | 3389 | |
a9960cdc | 3390 | /* Pass on information about the number of callee register saves |
9b0c95be | 3391 | performed in the prologue. |
3392 | ||
3393 | The compiler is supposed to pass the highest register number | |
6d36483b | 3394 | saved, the assembler then has to adjust that number before |
9b0c95be | 3395 | entering it into the unwind descriptor (to account for any |
6d36483b | 3396 | caller saved registers with lower register numbers than the |
9b0c95be | 3397 | first callee saved register). */ |
3398 | if (gr_saved) | |
3399 | fprintf (file, ",ENTRY_GR=%d", gr_saved + 2); | |
3400 | ||
3401 | if (fr_saved) | |
3402 | fprintf (file, ",ENTRY_FR=%d", fr_saved + 11); | |
a9960cdc | 3403 | |
9c0ac0fd | 3404 | fputs ("\n\t.ENTRY\n", file); |
daee63dd | 3405 | |
2efea8c0 | 3406 | remove_useless_addtr_insns (0); |
daee63dd | 3407 | } |
3408 | ||
57ed30e5 | 3409 | void |
5c1d8983 | 3410 | hppa_expand_prologue (void) |
daee63dd | 3411 | { |
afd7b680 | 3412 | int merge_sp_adjust_with_store = 0; |
6bcdc1fb | 3413 | HOST_WIDE_INT size = get_frame_size (); |
3414 | HOST_WIDE_INT offset; | |
3415 | int i; | |
a584fe8a | 3416 | rtx insn, tmpreg; |
daee63dd | 3417 | |
a9960cdc | 3418 | gr_saved = 0; |
3419 | fr_saved = 0; | |
3ddcbb9d | 3420 | save_fregs = 0; |
3a51bad9 | 3421 | |
256f9b65 | 3422 | /* Compute total size for frame pointer, filler, locals and rounding to |
3423 | the next word boundary. Similar code appears in compute_frame_size | |
3424 | and must be changed in tandem with this code. */ | |
3425 | local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1); | |
3426 | if (local_fsize || frame_pointer_needed) | |
3427 | local_fsize += STARTING_FRAME_OFFSET; | |
3a51bad9 | 3428 | |
a1ab4fa3 | 3429 | actual_fsize = compute_frame_size (size, &save_fregs); |
87ad11b0 | 3430 | |
daee63dd | 3431 | /* Compute a few things we will use often. */ |
440c23df | 3432 | tmpreg = gen_rtx_REG (word_mode, 1); |
87ad11b0 | 3433 | |
6d36483b | 3434 | /* Save RP first. The calling conventions manual states RP will |
cc858176 | 3435 | always be stored into the caller's frame at sp - 20 or sp - 16 |
5e3c5739 | 3436 | depending on which ABI is in use. */ |
a584fe8a | 3437 | if (regs_ever_live[2] || current_function_calls_eh_return) |
6a2c16d6 | 3438 | store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM); |
6d36483b | 3439 | |
daee63dd | 3440 | /* Allocate the local frame and set up the frame pointer if needed. */ |
58361f39 | 3441 | if (actual_fsize != 0) |
3442 | { | |
3443 | if (frame_pointer_needed) | |
3444 | { | |
3445 | /* Copy the old frame pointer temporarily into %r1. Set up the | |
3446 | new stack pointer, then store away the saved old frame pointer | |
a584fe8a | 3447 | into the stack at sp and at the same time update the stack |
3448 | pointer by actual_fsize bytes. Two versions, first | |
58361f39 | 3449 | handles small (<8k) frames. The second handles large (>=8k) |
3450 | frames. */ | |
a584fe8a | 3451 | insn = emit_move_insn (tmpreg, frame_pointer_rtx); |
3452 | if (DO_FRAME_NOTES) | |
cc858176 | 3453 | { |
a584fe8a | 3454 | /* We need to record the frame pointer save here since the |
3455 | new frame pointer is set in the following insn. */ | |
3456 | RTX_FRAME_RELATED_P (insn) = 1; | |
3457 | REG_NOTES (insn) | |
3458 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3459 | gen_rtx_SET (VOIDmode, | |
3460 | gen_rtx_MEM (word_mode, stack_pointer_rtx), | |
3461 | frame_pointer_rtx), | |
3462 | REG_NOTES (insn)); | |
cc858176 | 3463 | } |
a584fe8a | 3464 | |
3465 | insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); | |
3466 | if (DO_FRAME_NOTES) | |
3467 | RTX_FRAME_RELATED_P (insn) = 1; | |
3468 | ||
3469 | if (VAL_14_BITS_P (actual_fsize)) | |
3470 | store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize); | |
58361f39 | 3471 | else |
3472 | { | |
3473 | /* It is incorrect to store the saved frame pointer at *sp, | |
3474 | then increment sp (writes beyond the current stack boundary). | |
3475 | ||
3476 | So instead use stwm to store at *sp and post-increment the | |
3477 | stack pointer as an atomic operation. Then increment sp to | |
3478 | finish allocating the new frame. */ | |
6bcdc1fb | 3479 | HOST_WIDE_INT adjust1 = 8192 - 64; |
3480 | HOST_WIDE_INT adjust2 = actual_fsize - adjust1; | |
cc858176 | 3481 | |
a584fe8a | 3482 | store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1); |
6a2c16d6 | 3483 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3484 | adjust2, 1); |
58361f39 | 3485 | } |
a584fe8a | 3486 | |
e9ec370e | 3487 | /* We set SAVE_SP in frames that need a frame pointer. Thus, |
3488 | we need to store the previous stack pointer (frame pointer) | |
3489 | into the frame marker on targets that use the HP unwind | |
3490 | library. This allows the HP unwind library to be used to | |
3491 | unwind GCC frames. However, we are not fully compatible | |
3492 | with the HP library because our frame layout differs from | |
3493 | that specified in the HP runtime specification. | |
3494 | ||
3495 | We don't want a frame note on this instruction as the frame | |
3496 | marker moves during dynamic stack allocation. | |
3497 | ||
3498 | This instruction also serves as a blockage to prevent | |
3499 | register spills from being scheduled before the stack | |
3500 | pointer is raised. This is necessary as we store | |
3501 | registers using the frame pointer as a base register, | |
3502 | and the frame pointer is set before sp is raised. */ | |
3503 | if (TARGET_HPUX_UNWIND_LIBRARY) | |
3504 | { | |
3505 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, | |
3506 | GEN_INT (TARGET_64BIT ? -8 : -4)); | |
3507 | ||
3508 | emit_move_insn (gen_rtx_MEM (word_mode, addr), | |
3509 | frame_pointer_rtx); | |
3510 | } | |
3511 | else | |
3512 | emit_insn (gen_blockage ()); | |
58361f39 | 3513 | } |
3514 | /* no frame pointer needed. */ | |
3515 | else | |
3516 | { | |
3517 | /* In some cases we can perform the first callee register save | |
3518 | and allocating the stack frame at the same time. If so, just | |
3519 | make a note of it and defer allocating the frame until saving | |
3520 | the callee registers. */ | |
df6edefa | 3521 | if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0) |
58361f39 | 3522 | merge_sp_adjust_with_store = 1; |
3523 | /* Can not optimize. Adjust the stack frame by actual_fsize | |
3524 | bytes. */ | |
3525 | else | |
6a2c16d6 | 3526 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3527 | actual_fsize, 1); |
58361f39 | 3528 | } |
372ef038 | 3529 | } |
3530 | ||
6d36483b | 3531 | /* Normal register save. |
daee63dd | 3532 | |
3533 | Do not save the frame pointer in the frame_pointer_needed case. It | |
3534 | was done earlier. */ | |
87ad11b0 | 3535 | if (frame_pointer_needed) |
3536 | { | |
a584fe8a | 3537 | offset = local_fsize; |
3538 | ||
3539 | /* Saving the EH return data registers in the frame is the simplest | |
3540 | way to get the frame unwind information emitted. We put them | |
3541 | just before the general registers. */ | |
3542 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3543 | { | |
3544 | unsigned int i, regno; | |
3545 | ||
3546 | for (i = 0; ; ++i) | |
3547 | { | |
3548 | regno = EH_RETURN_DATA_REGNO (i); | |
3549 | if (regno == INVALID_REGNUM) | |
3550 | break; | |
3551 | ||
3552 | store_reg (regno, offset, FRAME_POINTER_REGNUM); | |
3553 | offset += UNITS_PER_WORD; | |
3554 | } | |
3555 | } | |
3556 | ||
3557 | for (i = 18; i >= 4; i--) | |
98328a39 | 3558 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3559 | { |
6a2c16d6 | 3560 | store_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 3561 | offset += UNITS_PER_WORD; |
a9960cdc | 3562 | gr_saved++; |
87ad11b0 | 3563 | } |
7f7c4869 | 3564 | /* Account for %r3 which is saved in a special place. */ |
9b0c95be | 3565 | gr_saved++; |
87ad11b0 | 3566 | } |
daee63dd | 3567 | /* No frame pointer needed. */ |
87ad11b0 | 3568 | else |
3569 | { | |
a584fe8a | 3570 | offset = local_fsize - actual_fsize; |
3571 | ||
3572 | /* Saving the EH return data registers in the frame is the simplest | |
3573 | way to get the frame unwind information emitted. */ | |
3574 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3575 | { | |
3576 | unsigned int i, regno; | |
3577 | ||
3578 | for (i = 0; ; ++i) | |
3579 | { | |
3580 | regno = EH_RETURN_DATA_REGNO (i); | |
3581 | if (regno == INVALID_REGNUM) | |
3582 | break; | |
3583 | ||
3584 | /* If merge_sp_adjust_with_store is nonzero, then we can | |
3585 | optimize the first save. */ | |
3586 | if (merge_sp_adjust_with_store) | |
3587 | { | |
3588 | store_reg_modify (STACK_POINTER_REGNUM, regno, -offset); | |
3589 | merge_sp_adjust_with_store = 0; | |
3590 | } | |
3591 | else | |
3592 | store_reg (regno, offset, STACK_POINTER_REGNUM); | |
3593 | offset += UNITS_PER_WORD; | |
3594 | } | |
3595 | } | |
3596 | ||
3597 | for (i = 18; i >= 3; i--) | |
98328a39 | 3598 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3599 | { |
6d36483b | 3600 | /* If merge_sp_adjust_with_store is nonzero, then we can |
afd7b680 | 3601 | optimize the first GR save. */ |
201f01e9 | 3602 | if (merge_sp_adjust_with_store) |
afd7b680 | 3603 | { |
a584fe8a | 3604 | store_reg_modify (STACK_POINTER_REGNUM, i, -offset); |
afd7b680 | 3605 | merge_sp_adjust_with_store = 0; |
afd7b680 | 3606 | } |
3607 | else | |
6a2c16d6 | 3608 | store_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 3609 | offset += UNITS_PER_WORD; |
a9960cdc | 3610 | gr_saved++; |
87ad11b0 | 3611 | } |
daee63dd | 3612 | |
afd7b680 | 3613 | /* If we wanted to merge the SP adjustment with a GR save, but we never |
daee63dd | 3614 | did any GR saves, then just emit the adjustment here. */ |
201f01e9 | 3615 | if (merge_sp_adjust_with_store) |
6a2c16d6 | 3616 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
a584fe8a | 3617 | actual_fsize, 1); |
87ad11b0 | 3618 | } |
6d36483b | 3619 | |
df6edefa | 3620 | /* The hppa calling conventions say that %r19, the pic offset |
3621 | register, is saved at sp - 32 (in this function's frame) | |
3622 | when generating PIC code. FIXME: What is the correct thing | |
3623 | to do for functions which make no calls and allocate no | |
3624 | frame? Do we need to allocate a frame, or can we just omit | |
8f177faf | 3625 | the save? For now we'll just omit the save. |
3626 | ||
3627 | We don't want a note on this insn as the frame marker can | |
3628 | move if there is a dynamic stack allocation. */ | |
df6edefa | 3629 | if (flag_pic && actual_fsize != 0 && !TARGET_64BIT) |
8f177faf | 3630 | { |
3631 | rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32)); | |
3632 | ||
3633 | emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx); | |
3634 | ||
3635 | } | |
df6edefa | 3636 | |
87ad11b0 | 3637 | /* Align pointer properly (doubleword boundary). */ |
3638 | offset = (offset + 7) & ~7; | |
3639 | ||
3640 | /* Floating point register store. */ | |
3641 | if (save_fregs) | |
87ad11b0 | 3642 | { |
a584fe8a | 3643 | rtx base; |
3644 | ||
daee63dd | 3645 | /* First get the frame or stack pointer to the start of the FP register |
3646 | save area. */ | |
a1ab4fa3 | 3647 | if (frame_pointer_needed) |
a584fe8a | 3648 | { |
3649 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); | |
3650 | base = frame_pointer_rtx; | |
3651 | } | |
a1ab4fa3 | 3652 | else |
a584fe8a | 3653 | { |
3654 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); | |
3655 | base = stack_pointer_rtx; | |
3656 | } | |
daee63dd | 3657 | |
3658 | /* Now actually save the FP registers. */ | |
bac38c40 | 3659 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
7f7c4869 | 3660 | { |
5e3c5739 | 3661 | if (regs_ever_live[i] |
3662 | || (! TARGET_64BIT && regs_ever_live[i + 1])) | |
7f7c4869 | 3663 | { |
6a2c16d6 | 3664 | rtx addr, insn, reg; |
cc858176 | 3665 | addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); |
3666 | reg = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 3667 | insn = emit_move_insn (addr, reg); |
3668 | if (DO_FRAME_NOTES) | |
3669 | { | |
3670 | RTX_FRAME_RELATED_P (insn) = 1; | |
a584fe8a | 3671 | if (TARGET_64BIT) |
3672 | { | |
3673 | rtx mem = gen_rtx_MEM (DFmode, | |
3674 | plus_constant (base, offset)); | |
3675 | REG_NOTES (insn) | |
3676 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3677 | gen_rtx_SET (VOIDmode, mem, reg), | |
3678 | REG_NOTES (insn)); | |
3679 | } | |
3680 | else | |
3681 | { | |
3682 | rtx meml = gen_rtx_MEM (SFmode, | |
3683 | plus_constant (base, offset)); | |
3684 | rtx memr = gen_rtx_MEM (SFmode, | |
3685 | plus_constant (base, offset + 4)); | |
3686 | rtx regl = gen_rtx_REG (SFmode, i); | |
3687 | rtx regr = gen_rtx_REG (SFmode, i + 1); | |
3688 | rtx setl = gen_rtx_SET (VOIDmode, meml, regl); | |
3689 | rtx setr = gen_rtx_SET (VOIDmode, memr, regr); | |
3690 | rtvec vec; | |
3691 | ||
3692 | RTX_FRAME_RELATED_P (setl) = 1; | |
3693 | RTX_FRAME_RELATED_P (setr) = 1; | |
3694 | vec = gen_rtvec (2, setl, setr); | |
3695 | REG_NOTES (insn) | |
3696 | = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
3697 | gen_rtx_SEQUENCE (VOIDmode, vec), | |
3698 | REG_NOTES (insn)); | |
3699 | } | |
6a2c16d6 | 3700 | } |
3701 | offset += GET_MODE_SIZE (DFmode); | |
7f7c4869 | 3702 | fr_saved++; |
3703 | } | |
3704 | } | |
87ad11b0 | 3705 | } |
3706 | } | |
3707 | ||
cc858176 | 3708 | /* Emit RTL to load REG from the memory location specified by BASE+DISP. |
3709 | Handle case where DISP > 8k by using the add_high_const patterns. */ | |
3710 | ||
6a2c16d6 | 3711 | static void |
6bcdc1fb | 3712 | load_reg (int reg, HOST_WIDE_INT disp, int base) |
cc858176 | 3713 | { |
6bcdc1fb | 3714 | rtx dest = gen_rtx_REG (word_mode, reg); |
3715 | rtx basereg = gen_rtx_REG (Pmode, base); | |
3716 | rtx src; | |
cc858176 | 3717 | |
cc858176 | 3718 | if (VAL_14_BITS_P (disp)) |
6bcdc1fb | 3719 | src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp)); |
3720 | else if (TARGET_64BIT && !VAL_32_BITS_P (disp)) | |
cc858176 | 3721 | { |
6bcdc1fb | 3722 | rtx delta = GEN_INT (disp); |
3723 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
3724 | ||
3725 | emit_move_insn (tmpreg, delta); | |
3726 | if (TARGET_DISABLE_INDEXING) | |
3727 | { | |
3728 | emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
3729 | src = gen_rtx_MEM (word_mode, tmpreg); | |
3730 | } | |
3731 | else | |
3732 | src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg)); | |
cc858176 | 3733 | } |
3734 | else | |
3735 | { | |
3736 | rtx delta = GEN_INT (disp); | |
3737 | rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta)); | |
3738 | rtx tmpreg = gen_rtx_REG (Pmode, 1); | |
6bcdc1fb | 3739 | |
cc858176 | 3740 | emit_move_insn (tmpreg, high); |
3741 | src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta)); | |
cc858176 | 3742 | } |
6bcdc1fb | 3743 | |
3744 | emit_move_insn (dest, src); | |
cc858176 | 3745 | } |
daee63dd | 3746 | |
2247cc5f | 3747 | /* Update the total code bytes output to the text section. */ |
3748 | ||
3749 | static void | |
5c1d8983 | 3750 | update_total_code_bytes (int nbytes) |
2247cc5f | 3751 | { |
3752 | if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM) | |
8a05c3c2 | 3753 | && !IN_NAMED_SECTION_P (cfun->decl)) |
2247cc5f | 3754 | { |
3755 | if (INSN_ADDRESSES_SET_P ()) | |
3756 | { | |
3757 | unsigned long old_total = total_code_bytes; | |
3758 | ||
3759 | total_code_bytes += nbytes; | |
3760 | ||
3761 | /* Be prepared to handle overflows. */ | |
3762 | if (old_total > total_code_bytes) | |
3763 | total_code_bytes = -1; | |
3764 | } | |
3765 | else | |
3766 | total_code_bytes = -1; | |
3767 | } | |
3768 | } | |
3769 | ||
17d9b0c3 | 3770 | /* This function generates the assembly code for function exit. |
3771 | Args are as for output_function_prologue (). | |
3772 | ||
3773 | The function epilogue should not depend on the current stack | |
3774 | pointer! It should use the frame pointer only. This is mandatory | |
3775 | because of alloca; we also take advantage of it to omit stack | |
6dc3b0d9 | 3776 | adjustments before returning. */ |
17d9b0c3 | 3777 | |
3778 | static void | |
5c1d8983 | 3779 | pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) |
87ad11b0 | 3780 | { |
3695c664 | 3781 | rtx insn = get_last_insn (); |
3782 | ||
2247cc5f | 3783 | last_address = 0; |
3784 | ||
daee63dd | 3785 | /* hppa_expand_epilogue does the dirty work now. We just need |
3786 | to output the assembler directives which denote the end | |
3695c664 | 3787 | of a function. |
3788 | ||
3789 | To make debuggers happy, emit a nop if the epilogue was completely | |
3790 | eliminated due to a volatile call as the last insn in the | |
6d36483b | 3791 | current function. That way the return address (in %r2) will |
3695c664 | 3792 | always point to a valid instruction in the current function. */ |
3793 | ||
3794 | /* Get the last real insn. */ | |
3795 | if (GET_CODE (insn) == NOTE) | |
3796 | insn = prev_real_insn (insn); | |
3797 | ||
3798 | /* If it is a sequence, then look inside. */ | |
3799 | if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE) | |
3800 | insn = XVECEXP (PATTERN (insn), 0, 0); | |
3801 | ||
6d36483b | 3802 | /* If insn is a CALL_INSN, then it must be a call to a volatile |
3695c664 | 3803 | function (otherwise there would be epilogue insns). */ |
3804 | if (insn && GET_CODE (insn) == CALL_INSN) | |
90c41894 | 3805 | { |
3806 | fputs ("\tnop\n", file); | |
3807 | last_address += 4; | |
3808 | } | |
6d36483b | 3809 | |
9c0ac0fd | 3810 | fputs ("\t.EXIT\n\t.PROCEND\n", file); |
90c41894 | 3811 | |
916c9cef | 3812 | if (TARGET_SOM && TARGET_GAS) |
3813 | { | |
3814 | /* We done with this subspace except possibly for some additional | |
3815 | debug information. Forget that we are in this subspace to ensure | |
3816 | that the next function is output in its own subspace. */ | |
3817 | forget_section (); | |
3818 | } | |
3819 | ||
2247cc5f | 3820 | if (INSN_ADDRESSES_SET_P ()) |
90c41894 | 3821 | { |
2247cc5f | 3822 | insn = get_last_nonnote_insn (); |
3823 | last_address += INSN_ADDRESSES (INSN_UID (insn)); | |
3824 | if (INSN_P (insn)) | |
3825 | last_address += insn_default_length (insn); | |
3826 | last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) | |
3827 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
90c41894 | 3828 | } |
2247cc5f | 3829 | |
3830 | /* Finally, update the total number of code bytes output so far. */ | |
3831 | update_total_code_bytes (last_address); | |
daee63dd | 3832 | } |
afd7b680 | 3833 | |
daee63dd | 3834 | void |
5c1d8983 | 3835 | hppa_expand_epilogue (void) |
daee63dd | 3836 | { |
6d36483b | 3837 | rtx tmpreg; |
6bcdc1fb | 3838 | HOST_WIDE_INT offset; |
3839 | HOST_WIDE_INT ret_off = 0; | |
3840 | int i; | |
58361f39 | 3841 | int merge_sp_adjust_with_load = 0; |
daee63dd | 3842 | |
3843 | /* We will use this often. */ | |
440c23df | 3844 | tmpreg = gen_rtx_REG (word_mode, 1); |
daee63dd | 3845 | |
3846 | /* Try to restore RP early to avoid load/use interlocks when | |
3847 | RP gets used in the return (bv) instruction. This appears to still | |
6dc3b0d9 | 3848 | be necessary even when we schedule the prologue and epilogue. */ |
a584fe8a | 3849 | if (regs_ever_live [2] || current_function_calls_eh_return) |
58361f39 | 3850 | { |
3851 | ret_off = TARGET_64BIT ? -16 : -20; | |
3852 | if (frame_pointer_needed) | |
3853 | { | |
6a2c16d6 | 3854 | load_reg (2, ret_off, FRAME_POINTER_REGNUM); |
58361f39 | 3855 | ret_off = 0; |
3856 | } | |
3857 | else | |
3858 | { | |
3859 | /* No frame pointer, and stack is smaller than 8k. */ | |
3860 | if (VAL_14_BITS_P (ret_off - actual_fsize)) | |
3861 | { | |
6a2c16d6 | 3862 | load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM); |
58361f39 | 3863 | ret_off = 0; |
3864 | } | |
3865 | } | |
3866 | } | |
daee63dd | 3867 | |
3868 | /* General register restores. */ | |
87ad11b0 | 3869 | if (frame_pointer_needed) |
3870 | { | |
a584fe8a | 3871 | offset = local_fsize; |
3872 | ||
3873 | /* If the current function calls __builtin_eh_return, then we need | |
3874 | to restore the saved EH data registers. */ | |
3875 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3876 | { | |
3877 | unsigned int i, regno; | |
3878 | ||
3879 | for (i = 0; ; ++i) | |
3880 | { | |
3881 | regno = EH_RETURN_DATA_REGNO (i); | |
3882 | if (regno == INVALID_REGNUM) | |
3883 | break; | |
3884 | ||
3885 | load_reg (regno, offset, FRAME_POINTER_REGNUM); | |
3886 | offset += UNITS_PER_WORD; | |
3887 | } | |
3888 | } | |
3889 | ||
3890 | for (i = 18; i >= 4; i--) | |
98328a39 | 3891 | if (regs_ever_live[i] && ! call_used_regs[i]) |
87ad11b0 | 3892 | { |
6a2c16d6 | 3893 | load_reg (i, offset, FRAME_POINTER_REGNUM); |
6ec4380b | 3894 | offset += UNITS_PER_WORD; |
87ad11b0 | 3895 | } |
87ad11b0 | 3896 | } |
3897 | else | |
3898 | { | |
a584fe8a | 3899 | offset = local_fsize - actual_fsize; |
3900 | ||
3901 | /* If the current function calls __builtin_eh_return, then we need | |
3902 | to restore the saved EH data registers. */ | |
3903 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
3904 | { | |
3905 | unsigned int i, regno; | |
3906 | ||
3907 | for (i = 0; ; ++i) | |
3908 | { | |
3909 | regno = EH_RETURN_DATA_REGNO (i); | |
3910 | if (regno == INVALID_REGNUM) | |
3911 | break; | |
3912 | ||
3913 | /* Only for the first load. | |
3914 | merge_sp_adjust_with_load holds the register load | |
3915 | with which we will merge the sp adjustment. */ | |
3916 | if (merge_sp_adjust_with_load == 0 | |
3917 | && local_fsize == 0 | |
3918 | && VAL_14_BITS_P (-actual_fsize)) | |
3919 | merge_sp_adjust_with_load = regno; | |
3920 | else | |
3921 | load_reg (regno, offset, STACK_POINTER_REGNUM); | |
3922 | offset += UNITS_PER_WORD; | |
3923 | } | |
3924 | } | |
3925 | ||
3926 | for (i = 18; i >= 3; i--) | |
7f7c4869 | 3927 | { |
98328a39 | 3928 | if (regs_ever_live[i] && ! call_used_regs[i]) |
7f7c4869 | 3929 | { |
7f7c4869 | 3930 | /* Only for the first load. |
3931 | merge_sp_adjust_with_load holds the register load | |
3932 | with which we will merge the sp adjustment. */ | |
58361f39 | 3933 | if (merge_sp_adjust_with_load == 0 |
7f7c4869 | 3934 | && local_fsize == 0 |
58361f39 | 3935 | && VAL_14_BITS_P (-actual_fsize)) |
7f7c4869 | 3936 | merge_sp_adjust_with_load = i; |
3937 | else | |
6a2c16d6 | 3938 | load_reg (i, offset, STACK_POINTER_REGNUM); |
6ec4380b | 3939 | offset += UNITS_PER_WORD; |
7f7c4869 | 3940 | } |
3941 | } | |
87ad11b0 | 3942 | } |
daee63dd | 3943 | |
87ad11b0 | 3944 | /* Align pointer properly (doubleword boundary). */ |
3945 | offset = (offset + 7) & ~7; | |
3946 | ||
daee63dd | 3947 | /* FP register restores. */ |
87ad11b0 | 3948 | if (save_fregs) |
87ad11b0 | 3949 | { |
daee63dd | 3950 | /* Adjust the register to index off of. */ |
a1ab4fa3 | 3951 | if (frame_pointer_needed) |
a584fe8a | 3952 | set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0); |
a1ab4fa3 | 3953 | else |
a584fe8a | 3954 | set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0); |
daee63dd | 3955 | |
3956 | /* Actually do the restores now. */ | |
bac38c40 | 3957 | for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP) |
cc858176 | 3958 | if (regs_ever_live[i] |
3959 | || (! TARGET_64BIT && regs_ever_live[i + 1])) | |
3960 | { | |
3961 | rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg)); | |
3962 | rtx dest = gen_rtx_REG (DFmode, i); | |
6a2c16d6 | 3963 | emit_move_insn (dest, src); |
cc858176 | 3964 | } |
87ad11b0 | 3965 | } |
daee63dd | 3966 | |
14660146 | 3967 | /* Emit a blockage insn here to keep these insns from being moved to |
3968 | an earlier spot in the epilogue, or into the main instruction stream. | |
3969 | ||
3970 | This is necessary as we must not cut the stack back before all the | |
3971 | restores are finished. */ | |
3972 | emit_insn (gen_blockage ()); | |
daee63dd | 3973 | |
9840d99d | 3974 | /* Reset stack pointer (and possibly frame pointer). The stack |
42819d4e | 3975 | pointer is initially set to fp + 64 to avoid a race condition. */ |
58361f39 | 3976 | if (frame_pointer_needed) |
87ad11b0 | 3977 | { |
cc858176 | 3978 | rtx delta = GEN_INT (-64); |
a584fe8a | 3979 | |
3980 | set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0); | |
3981 | emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta)); | |
87ad11b0 | 3982 | } |
daee63dd | 3983 | /* If we were deferring a callee register restore, do it now. */ |
58361f39 | 3984 | else if (merge_sp_adjust_with_load) |
3985 | { | |
3986 | rtx delta = GEN_INT (-actual_fsize); | |
cc858176 | 3987 | rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load); |
a584fe8a | 3988 | |
3989 | emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta)); | |
58361f39 | 3990 | } |
daee63dd | 3991 | else if (actual_fsize != 0) |
a584fe8a | 3992 | set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, |
3993 | - actual_fsize, 0); | |
58361f39 | 3994 | |
3995 | /* If we haven't restored %r2 yet (no frame pointer, and a stack | |
3996 | frame greater than 8k), do so now. */ | |
3997 | if (ret_off != 0) | |
6a2c16d6 | 3998 | load_reg (2, ret_off, STACK_POINTER_REGNUM); |
a584fe8a | 3999 | |
4000 | if (DO_FRAME_NOTES && current_function_calls_eh_return) | |
4001 | { | |
4002 | rtx sa = EH_RETURN_STACKADJ_RTX; | |
4003 | ||
4004 | emit_insn (gen_blockage ()); | |
4005 | emit_insn (TARGET_64BIT | |
4006 | ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa) | |
4007 | : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa)); | |
4008 | } | |
87ad11b0 | 4009 | } |
4010 | ||
d7e2f694 | 4011 | rtx |
5c1d8983 | 4012 | hppa_pic_save_rtx (void) |
cf3de5bb | 4013 | { |
d7e2f694 | 4014 | return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM); |
df6edefa | 4015 | } |
4016 | ||
4017 | void | |
5c1d8983 | 4018 | hppa_profile_hook (int label_no) |
df6edefa | 4019 | { |
4da37e2f | 4020 | /* We use SImode for the address of the function in both 32 and |
4021 | 64-bit code to avoid having to provide DImode versions of the | |
4022 | lcla2 and load_offset_label_address insn patterns. */ | |
4023 | rtx reg = gen_reg_rtx (SImode); | |
4024 | rtx label_rtx = gen_label_rtx (); | |
a9ac13e4 | 4025 | rtx begin_label_rtx, call_insn; |
4026 | char begin_label_name[16]; | |
df6edefa | 4027 | |
a9ac13e4 | 4028 | ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL, |
b8a21949 | 4029 | label_no); |
4da37e2f | 4030 | begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name)); |
df6edefa | 4031 | |
4032 | if (TARGET_64BIT) | |
4033 | emit_move_insn (arg_pointer_rtx, | |
4034 | gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, | |
4035 | GEN_INT (64))); | |
4036 | ||
df6edefa | 4037 | emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2)); |
4038 | ||
4da37e2f | 4039 | /* The address of the function is loaded into %r25 with a instruction- |
4040 | relative sequence that avoids the use of relocations. The sequence | |
4041 | is split so that the load_offset_label_address instruction can | |
4042 | occupy the delay slot of the call to _mcount. */ | |
4043 | if (TARGET_PA_20) | |
4044 | emit_insn (gen_lcla2 (reg, label_rtx)); | |
4045 | else | |
4046 | emit_insn (gen_lcla1 (reg, label_rtx)); | |
4047 | ||
4048 | emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25), | |
4049 | reg, begin_label_rtx, label_rtx)); | |
4050 | ||
df6edefa | 4051 | #ifndef NO_PROFILE_COUNTERS |
4052 | { | |
4053 | rtx count_label_rtx, addr, r24; | |
a9ac13e4 | 4054 | char count_label_name[16]; |
df6edefa | 4055 | |
a9ac13e4 | 4056 | ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no); |
4057 | count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name)); | |
df6edefa | 4058 | |
831a12d9 | 4059 | addr = force_reg (Pmode, count_label_rtx); |
df6edefa | 4060 | r24 = gen_rtx_REG (Pmode, 24); |
4061 | emit_move_insn (r24, addr); | |
4062 | ||
df6edefa | 4063 | call_insn = |
4da37e2f | 4064 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4065 | gen_rtx_SYMBOL_REF (Pmode, | |
4066 | "_mcount")), | |
4067 | GEN_INT (TARGET_64BIT ? 24 : 12))); | |
df6edefa | 4068 | |
4069 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24); | |
4070 | } | |
4071 | #else | |
4da37e2f | 4072 | |
df6edefa | 4073 | call_insn = |
4da37e2f | 4074 | emit_call_insn (gen_call (gen_rtx_MEM (Pmode, |
4075 | gen_rtx_SYMBOL_REF (Pmode, | |
4076 | "_mcount")), | |
4077 | GEN_INT (TARGET_64BIT ? 16 : 8))); | |
4078 | ||
df6edefa | 4079 | #endif |
4080 | ||
4da37e2f | 4081 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25)); |
4082 | use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26)); | |
4083 | ||
df6edefa | 4084 | /* Indicate the _mcount call cannot throw, nor will it execute a |
4085 | non-local goto. */ | |
4086 | REG_NOTES (call_insn) | |
4087 | = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn)); | |
cf3de5bb | 4088 | } |
4089 | ||
e07ff380 | 4090 | /* Fetch the return address for the frame COUNT steps up from |
4091 | the current frame, after the prologue. FRAMEADDR is the | |
4092 | frame pointer of the COUNT frame. | |
4093 | ||
f49b2e77 | 4094 | We want to ignore any export stub remnants here. To handle this, |
4095 | we examine the code at the return address, and if it is an export | |
4096 | stub, we return a memory rtx for the stub return address stored | |
4097 | at frame-24. | |
a6c6fd6c | 4098 | |
4099 | The value returned is used in two different ways: | |
4100 | ||
4101 | 1. To find a function's caller. | |
4102 | ||
4103 | 2. To change the return address for a function. | |
4104 | ||
4105 | This function handles most instances of case 1; however, it will | |
4106 | fail if there are two levels of stubs to execute on the return | |
4107 | path. The only way I believe that can happen is if the return value | |
4108 | needs a parameter relocation, which never happens for C code. | |
4109 | ||
4110 | This function handles most instances of case 2; however, it will | |
4111 | fail if we did not originally have stub code on the return path | |
f49b2e77 | 4112 | but will need stub code on the new return path. This can happen if |
a6c6fd6c | 4113 | the caller & callee are both in the main program, but the new |
f49b2e77 | 4114 | return location is in a shared library. */ |
e07ff380 | 4115 | |
4116 | rtx | |
5c1d8983 | 4117 | return_addr_rtx (int count, rtx frameaddr) |
e07ff380 | 4118 | { |
4119 | rtx label; | |
f49b2e77 | 4120 | rtx rp; |
e07ff380 | 4121 | rtx saved_rp; |
4122 | rtx ins; | |
4123 | ||
f49b2e77 | 4124 | if (count != 0) |
4125 | return NULL_RTX; | |
b29897dd | 4126 | |
f49b2e77 | 4127 | rp = get_hard_reg_initial_val (Pmode, 2); |
e07ff380 | 4128 | |
f49b2e77 | 4129 | if (TARGET_64BIT || TARGET_NO_SPACE_REGS) |
4130 | return rp; | |
e07ff380 | 4131 | |
b29897dd | 4132 | saved_rp = gen_reg_rtx (Pmode); |
f49b2e77 | 4133 | emit_move_insn (saved_rp, rp); |
e07ff380 | 4134 | |
4135 | /* Get pointer to the instruction stream. We have to mask out the | |
4136 | privilege level from the two low order bits of the return address | |
4137 | pointer here so that ins will point to the start of the first | |
4138 | instruction that would have been executed if we returned. */ | |
f49b2e77 | 4139 | ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR)); |
e07ff380 | 4140 | label = gen_label_rtx (); |
4141 | ||
4142 | /* Check the instruction stream at the normal return address for the | |
4143 | export stub: | |
4144 | ||
4145 | 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp | |
4146 | 0x004010a1 | stub+12: ldsid (sr0,rp),r1 | |
4147 | 0x00011820 | stub+16: mtsp r1,sr0 | |
4148 | 0xe0400002 | stub+20: be,n 0(sr0,rp) | |
4149 | ||
4150 | If it is an export stub, than our return address is really in | |
4151 | -24[frameaddr]. */ | |
4152 | ||
e00b80b2 | 4153 | emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE, |
4154 | NULL_RTX, SImode, 1); | |
e07ff380 | 4155 | emit_jump_insn (gen_bne (label)); |
4156 | ||
ad851752 | 4157 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)), |
e00b80b2 | 4158 | GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4159 | emit_jump_insn (gen_bne (label)); |
4160 | ||
ad851752 | 4161 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)), |
e00b80b2 | 4162 | GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4163 | emit_jump_insn (gen_bne (label)); |
4164 | ||
ad851752 | 4165 | emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)), |
e00b80b2 | 4166 | GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1); |
e07ff380 | 4167 | |
f49b2e77 | 4168 | /* If there is no export stub then just use the value saved from |
4169 | the return pointer register. */ | |
e07ff380 | 4170 | |
4171 | emit_jump_insn (gen_bne (label)); | |
4172 | ||
f49b2e77 | 4173 | /* Here we know that our return address points to an export |
e07ff380 | 4174 | stub. We don't want to return the address of the export stub, |
f49b2e77 | 4175 | but rather the return address of the export stub. That return |
4176 | address is stored at -24[frameaddr]. */ | |
e07ff380 | 4177 | |
f49b2e77 | 4178 | emit_move_insn (saved_rp, |
4179 | gen_rtx_MEM (Pmode, | |
4180 | memory_address (Pmode, | |
4181 | plus_constant (frameaddr, | |
4182 | -24)))); | |
e07ff380 | 4183 | |
4184 | emit_label (label); | |
f49b2e77 | 4185 | return saved_rp; |
e07ff380 | 4186 | } |
4187 | ||
757d4970 | 4188 | /* This is only valid once reload has completed because it depends on |
4189 | knowing exactly how much (if any) frame there is and... | |
4190 | ||
4191 | It's only valid if there is no frame marker to de-allocate and... | |
4192 | ||
4193 | It's only valid if %r2 hasn't been saved into the caller's frame | |
4194 | (we're not profiling and %r2 isn't live anywhere). */ | |
4195 | int | |
5c1d8983 | 4196 | hppa_can_use_return_insn_p (void) |
757d4970 | 4197 | { |
4198 | return (reload_completed | |
4199 | && (compute_frame_size (get_frame_size (), 0) ? 0 : 1) | |
757d4970 | 4200 | && ! regs_ever_live[2] |
4201 | && ! frame_pointer_needed); | |
4202 | } | |
4203 | ||
87ad11b0 | 4204 | void |
5c1d8983 | 4205 | emit_bcond_fp (enum rtx_code code, rtx operand0) |
87ad11b0 | 4206 | { |
ad851752 | 4207 | emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, |
4208 | gen_rtx_IF_THEN_ELSE (VOIDmode, | |
4209 | gen_rtx_fmt_ee (code, | |
4210 | VOIDmode, | |
4211 | gen_rtx_REG (CCFPmode, 0), | |
4212 | const0_rtx), | |
4213 | gen_rtx_LABEL_REF (VOIDmode, operand0), | |
4214 | pc_rtx))); | |
87ad11b0 | 4215 | |
4216 | } | |
4217 | ||
4218 | rtx | |
5c1d8983 | 4219 | gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1) |
87ad11b0 | 4220 | { |
ad851752 | 4221 | return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0), |
4222 | gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1)); | |
87ad11b0 | 4223 | } |
4224 | ||
8b49b3c7 | 4225 | /* Adjust the cost of a scheduling dependency. Return the new cost of |
4226 | a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ | |
4227 | ||
747af5e7 | 4228 | static int |
5c1d8983 | 4229 | pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) |
8b49b3c7 | 4230 | { |
43048d2c | 4231 | enum attr_type attr_type; |
4232 | ||
cde3e16c | 4233 | /* Don't adjust costs for a pa8000 chip, also do not adjust any |
4234 | true dependencies as they are described with bypasses now. */ | |
4235 | if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0) | |
342aabd9 | 4236 | return cost; |
4237 | ||
d402da4b | 4238 | if (! recog_memoized (insn)) |
4239 | return 0; | |
8b49b3c7 | 4240 | |
43048d2c | 4241 | attr_type = get_attr_type (insn); |
4242 | ||
ecf2283d | 4243 | switch (REG_NOTE_KIND (link)) |
8b49b3c7 | 4244 | { |
ecf2283d | 4245 | case REG_DEP_ANTI: |
8b49b3c7 | 4246 | /* Anti dependency; DEP_INSN reads a register that INSN writes some |
4247 | cycles later. */ | |
4248 | ||
43048d2c | 4249 | if (attr_type == TYPE_FPLOAD) |
8b49b3c7 | 4250 | { |
d402da4b | 4251 | rtx pat = PATTERN (insn); |
4252 | rtx dep_pat = PATTERN (dep_insn); | |
4253 | if (GET_CODE (pat) == PARALLEL) | |
4254 | { | |
4255 | /* This happens for the fldXs,mb patterns. */ | |
4256 | pat = XVECEXP (pat, 0, 0); | |
4257 | } | |
4258 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
8b49b3c7 | 4259 | /* If this happens, we have to extend this to schedule |
d402da4b | 4260 | optimally. Return 0 for now. */ |
4261 | return 0; | |
8b49b3c7 | 4262 | |
d402da4b | 4263 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) |
8b49b3c7 | 4264 | { |
d402da4b | 4265 | if (! recog_memoized (dep_insn)) |
4266 | return 0; | |
8b49b3c7 | 4267 | switch (get_attr_type (dep_insn)) |
4268 | { | |
4269 | case TYPE_FPALU: | |
134b4858 | 4270 | case TYPE_FPMULSGL: |
4271 | case TYPE_FPMULDBL: | |
8b49b3c7 | 4272 | case TYPE_FPDIVSGL: |
4273 | case TYPE_FPDIVDBL: | |
4274 | case TYPE_FPSQRTSGL: | |
4275 | case TYPE_FPSQRTDBL: | |
d402da4b | 4276 | /* A fpload can't be issued until one cycle before a |
01cc3b75 | 4277 | preceding arithmetic operation has finished if |
d402da4b | 4278 | the target of the fpload is any of the sources |
4279 | (or destination) of the arithmetic operation. */ | |
cde3e16c | 4280 | return insn_default_latency (dep_insn) - 1; |
134b4858 | 4281 | |
4282 | default: | |
4283 | return 0; | |
4284 | } | |
4285 | } | |
4286 | } | |
43048d2c | 4287 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4288 | { |
4289 | rtx pat = PATTERN (insn); | |
4290 | rtx dep_pat = PATTERN (dep_insn); | |
4291 | if (GET_CODE (pat) == PARALLEL) | |
4292 | { | |
4293 | /* This happens for the fldXs,mb patterns. */ | |
4294 | pat = XVECEXP (pat, 0, 0); | |
4295 | } | |
4296 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4297 | /* If this happens, we have to extend this to schedule | |
4298 | optimally. Return 0 for now. */ | |
4299 | return 0; | |
4300 | ||
4301 | if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat))) | |
4302 | { | |
4303 | if (! recog_memoized (dep_insn)) | |
4304 | return 0; | |
4305 | switch (get_attr_type (dep_insn)) | |
4306 | { | |
4307 | case TYPE_FPDIVSGL: | |
4308 | case TYPE_FPDIVDBL: | |
4309 | case TYPE_FPSQRTSGL: | |
4310 | case TYPE_FPSQRTDBL: | |
4311 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4312 | preceding divide or sqrt operation has finished if |
134b4858 | 4313 | the target of the ALU flop is any of the sources |
4314 | (or destination) of the divide or sqrt operation. */ | |
cde3e16c | 4315 | return insn_default_latency (dep_insn) - 2; |
8b49b3c7 | 4316 | |
4317 | default: | |
4318 | return 0; | |
4319 | } | |
4320 | } | |
4321 | } | |
4322 | ||
4323 | /* For other anti dependencies, the cost is 0. */ | |
4324 | return 0; | |
ecf2283d | 4325 | |
4326 | case REG_DEP_OUTPUT: | |
134b4858 | 4327 | /* Output dependency; DEP_INSN writes a register that INSN writes some |
4328 | cycles later. */ | |
43048d2c | 4329 | if (attr_type == TYPE_FPLOAD) |
134b4858 | 4330 | { |
4331 | rtx pat = PATTERN (insn); | |
4332 | rtx dep_pat = PATTERN (dep_insn); | |
4333 | if (GET_CODE (pat) == PARALLEL) | |
4334 | { | |
4335 | /* This happens for the fldXs,mb patterns. */ | |
4336 | pat = XVECEXP (pat, 0, 0); | |
4337 | } | |
4338 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4339 | /* If this happens, we have to extend this to schedule | |
4340 | optimally. Return 0 for now. */ | |
4341 | return 0; | |
4342 | ||
4343 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4344 | { | |
4345 | if (! recog_memoized (dep_insn)) | |
4346 | return 0; | |
4347 | switch (get_attr_type (dep_insn)) | |
4348 | { | |
4349 | case TYPE_FPALU: | |
4350 | case TYPE_FPMULSGL: | |
4351 | case TYPE_FPMULDBL: | |
4352 | case TYPE_FPDIVSGL: | |
4353 | case TYPE_FPDIVDBL: | |
4354 | case TYPE_FPSQRTSGL: | |
4355 | case TYPE_FPSQRTDBL: | |
4356 | /* A fpload can't be issued until one cycle before a | |
01cc3b75 | 4357 | preceding arithmetic operation has finished if |
134b4858 | 4358 | the target of the fpload is the destination of the |
bea4bad2 | 4359 | arithmetic operation. |
4360 | ||
4361 | Exception: For PA7100LC, PA7200 and PA7300, the cost | |
4362 | is 3 cycles, unless they bundle together. We also | |
4363 | pay the penalty if the second insn is a fpload. */ | |
cde3e16c | 4364 | return insn_default_latency (dep_insn) - 1; |
8b49b3c7 | 4365 | |
134b4858 | 4366 | default: |
4367 | return 0; | |
4368 | } | |
4369 | } | |
4370 | } | |
43048d2c | 4371 | else if (attr_type == TYPE_FPALU) |
134b4858 | 4372 | { |
4373 | rtx pat = PATTERN (insn); | |
4374 | rtx dep_pat = PATTERN (dep_insn); | |
4375 | if (GET_CODE (pat) == PARALLEL) | |
4376 | { | |
4377 | /* This happens for the fldXs,mb patterns. */ | |
4378 | pat = XVECEXP (pat, 0, 0); | |
4379 | } | |
4380 | if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) | |
4381 | /* If this happens, we have to extend this to schedule | |
4382 | optimally. Return 0 for now. */ | |
4383 | return 0; | |
4384 | ||
4385 | if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat))) | |
4386 | { | |
4387 | if (! recog_memoized (dep_insn)) | |
4388 | return 0; | |
4389 | switch (get_attr_type (dep_insn)) | |
4390 | { | |
4391 | case TYPE_FPDIVSGL: | |
4392 | case TYPE_FPDIVDBL: | |
4393 | case TYPE_FPSQRTSGL: | |
4394 | case TYPE_FPSQRTDBL: | |
4395 | /* An ALU flop can't be issued until two cycles before a | |
01cc3b75 | 4396 | preceding divide or sqrt operation has finished if |
134b4858 | 4397 | the target of the ALU flop is also the target of |
3398e91d | 4398 | the divide or sqrt operation. */ |
cde3e16c | 4399 | return insn_default_latency (dep_insn) - 2; |
134b4858 | 4400 | |
4401 | default: | |
4402 | return 0; | |
4403 | } | |
4404 | } | |
4405 | } | |
4406 | ||
4407 | /* For other output dependencies, the cost is 0. */ | |
4408 | return 0; | |
ecf2283d | 4409 | |
4410 | default: | |
4411 | gcc_unreachable (); | |
134b4858 | 4412 | } |
8b49b3c7 | 4413 | } |
87ad11b0 | 4414 | |
747af5e7 | 4415 | /* Adjust scheduling priorities. We use this to try and keep addil |
4416 | and the next use of %r1 close together. */ | |
4417 | static int | |
5c1d8983 | 4418 | pa_adjust_priority (rtx insn, int priority) |
747af5e7 | 4419 | { |
4420 | rtx set = single_set (insn); | |
4421 | rtx src, dest; | |
4422 | if (set) | |
4423 | { | |
4424 | src = SET_SRC (set); | |
4425 | dest = SET_DEST (set); | |
4426 | if (GET_CODE (src) == LO_SUM | |
4427 | && symbolic_operand (XEXP (src, 1), VOIDmode) | |
4428 | && ! read_only_operand (XEXP (src, 1), VOIDmode)) | |
4429 | priority >>= 3; | |
4430 | ||
4431 | else if (GET_CODE (src) == MEM | |
4432 | && GET_CODE (XEXP (src, 0)) == LO_SUM | |
4433 | && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode) | |
4434 | && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode)) | |
4435 | priority >>= 1; | |
4436 | ||
4437 | else if (GET_CODE (dest) == MEM | |
4438 | && GET_CODE (XEXP (dest, 0)) == LO_SUM | |
4439 | && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode) | |
4440 | && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)) | |
4441 | priority >>= 3; | |
4442 | } | |
4443 | return priority; | |
4444 | } | |
4445 | ||
4446 | /* The 700 can only issue a single insn at a time. | |
4447 | The 7XXX processors can issue two insns at a time. | |
4448 | The 8000 can issue 4 insns at a time. */ | |
4449 | static int | |
5c1d8983 | 4450 | pa_issue_rate (void) |
747af5e7 | 4451 | { |
4452 | switch (pa_cpu) | |
4453 | { | |
4454 | case PROCESSOR_700: return 1; | |
4455 | case PROCESSOR_7100: return 2; | |
4456 | case PROCESSOR_7100LC: return 2; | |
4457 | case PROCESSOR_7200: return 2; | |
bea4bad2 | 4458 | case PROCESSOR_7300: return 2; |
747af5e7 | 4459 | case PROCESSOR_8000: return 4; |
4460 | ||
4461 | default: | |
ecf2283d | 4462 | gcc_unreachable (); |
747af5e7 | 4463 | } |
4464 | } | |
4465 | ||
4466 | ||
4467 | ||
58e17b0b | 4468 | /* Return any length adjustment needed by INSN which already has its length |
6d36483b | 4469 | computed as LENGTH. Return zero if no adjustment is necessary. |
58e17b0b | 4470 | |
5fbd5940 | 4471 | For the PA: function calls, millicode calls, and backwards short |
6d36483b | 4472 | conditional branches with unfilled delay slots need an adjustment by +1 |
5fbd5940 | 4473 | (to account for the NOP which will be inserted into the instruction stream). |
58e17b0b | 4474 | |
4475 | Also compute the length of an inline block move here as it is too | |
5fbd5940 | 4476 | complicated to express as a length attribute in pa.md. */ |
58e17b0b | 4477 | int |
5c1d8983 | 4478 | pa_adjust_insn_length (rtx insn, int length) |
58e17b0b | 4479 | { |
4480 | rtx pat = PATTERN (insn); | |
4481 | ||
faf3f8c1 | 4482 | /* Jumps inside switch tables which have unfilled delay slots need |
4483 | adjustment. */ | |
4484 | if (GET_CODE (insn) == JUMP_INSN | |
b932f66c | 4485 | && GET_CODE (pat) == PARALLEL |
4486 | && get_attr_type (insn) == TYPE_BTABLE_BRANCH) | |
3b1e673e | 4487 | return 4; |
58e17b0b | 4488 | /* Millicode insn with an unfilled delay slot. */ |
4489 | else if (GET_CODE (insn) == INSN | |
4490 | && GET_CODE (pat) != SEQUENCE | |
4491 | && GET_CODE (pat) != USE | |
4492 | && GET_CODE (pat) != CLOBBER | |
4493 | && get_attr_type (insn) == TYPE_MILLI) | |
5a1231ef | 4494 | return 4; |
58e17b0b | 4495 | /* Block move pattern. */ |
4496 | else if (GET_CODE (insn) == INSN | |
4497 | && GET_CODE (pat) == PARALLEL | |
f2ebcf32 | 4498 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET |
58e17b0b | 4499 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM |
4500 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM | |
4501 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode | |
4502 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode) | |
008c057d | 4503 | return compute_movmem_length (insn) - 4; |
a7e1bb24 | 4504 | /* Block clear pattern. */ |
4505 | else if (GET_CODE (insn) == INSN | |
4506 | && GET_CODE (pat) == PARALLEL | |
4507 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET | |
4508 | && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM | |
4509 | && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx | |
4510 | && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode) | |
008c057d | 4511 | return compute_clrmem_length (insn) - 4; |
58e17b0b | 4512 | /* Conditional branch with an unfilled delay slot. */ |
5fbd5940 | 4513 | else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn)) |
4514 | { | |
4515 | /* Adjust a short backwards conditional with an unfilled delay slot. */ | |
4516 | if (GET_CODE (pat) == SET | |
5a1231ef | 4517 | && length == 4 |
5fbd5940 | 4518 | && ! forward_branch_p (insn)) |
5a1231ef | 4519 | return 4; |
546a40bd | 4520 | else if (GET_CODE (pat) == PARALLEL |
4521 | && get_attr_type (insn) == TYPE_PARALLEL_BRANCH | |
4522 | && length == 4) | |
4523 | return 4; | |
5fbd5940 | 4524 | /* Adjust dbra insn with short backwards conditional branch with |
6d36483b | 4525 | unfilled delay slot -- only for case where counter is in a |
6dc3b0d9 | 4526 | general register register. */ |
5fbd5940 | 4527 | else if (GET_CODE (pat) == PARALLEL |
4528 | && GET_CODE (XVECEXP (pat, 0, 1)) == SET | |
4529 | && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG | |
6d36483b | 4530 | && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0)) |
5a1231ef | 4531 | && length == 4 |
5fbd5940 | 4532 | && ! forward_branch_p (insn)) |
5a1231ef | 4533 | return 4; |
5fbd5940 | 4534 | else |
4535 | return 0; | |
4536 | } | |
546a40bd | 4537 | return 0; |
58e17b0b | 4538 | } |
4539 | ||
87ad11b0 | 4540 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
4541 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
4542 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
4543 | ||
4544 | void | |
5c1d8983 | 4545 | print_operand (FILE *file, rtx x, int code) |
87ad11b0 | 4546 | { |
4547 | switch (code) | |
4548 | { | |
4549 | case '#': | |
4550 | /* Output a 'nop' if there's nothing for the delay slot. */ | |
4551 | if (dbr_sequence_length () == 0) | |
4552 | fputs ("\n\tnop", file); | |
4553 | return; | |
4554 | case '*': | |
87fcb603 | 4555 | /* Output a nullification completer if there's nothing for the */ |
6d36483b | 4556 | /* delay slot or nullification is requested. */ |
87ad11b0 | 4557 | if (dbr_sequence_length () == 0 || |
4558 | (final_sequence && | |
4559 | INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))) | |
4560 | fputs (",n", file); | |
4561 | return; | |
4562 | case 'R': | |
4563 | /* Print out the second register name of a register pair. | |
4564 | I.e., R (6) => 7. */ | |
ea52c577 | 4565 | fputs (reg_names[REGNO (x) + 1], file); |
87ad11b0 | 4566 | return; |
4567 | case 'r': | |
6dc3b0d9 | 4568 | /* A register or zero. */ |
891b55b4 | 4569 | if (x == const0_rtx |
4570 | || (x == CONST0_RTX (DFmode)) | |
4571 | || (x == CONST0_RTX (SFmode))) | |
87ad11b0 | 4572 | { |
c6ae275c | 4573 | fputs ("%r0", file); |
4574 | return; | |
4575 | } | |
4576 | else | |
4577 | break; | |
4578 | case 'f': | |
6dc3b0d9 | 4579 | /* A register or zero (floating point). */ |
c6ae275c | 4580 | if (x == const0_rtx |
4581 | || (x == CONST0_RTX (DFmode)) | |
4582 | || (x == CONST0_RTX (SFmode))) | |
4583 | { | |
4584 | fputs ("%fr0", file); | |
87ad11b0 | 4585 | return; |
4586 | } | |
4587 | else | |
4588 | break; | |
2d14b1f0 | 4589 | case 'A': |
4590 | { | |
4591 | rtx xoperands[2]; | |
4592 | ||
4593 | xoperands[0] = XEXP (XEXP (x, 0), 0); | |
4594 | xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0); | |
4595 | output_global_address (file, xoperands[1], 0); | |
4596 | fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]); | |
4597 | return; | |
4598 | } | |
4599 | ||
c8975385 | 4600 | case 'C': /* Plain (C)ondition */ |
87ad11b0 | 4601 | case 'X': |
4602 | switch (GET_CODE (x)) | |
6d36483b | 4603 | { |
87ad11b0 | 4604 | case EQ: |
9c0ac0fd | 4605 | fputs ("=", file); break; |
87ad11b0 | 4606 | case NE: |
9c0ac0fd | 4607 | fputs ("<>", file); break; |
87ad11b0 | 4608 | case GT: |
9c0ac0fd | 4609 | fputs (">", file); break; |
87ad11b0 | 4610 | case GE: |
9c0ac0fd | 4611 | fputs (">=", file); break; |
87ad11b0 | 4612 | case GEU: |
9c0ac0fd | 4613 | fputs (">>=", file); break; |
87ad11b0 | 4614 | case GTU: |
9c0ac0fd | 4615 | fputs (">>", file); break; |
87ad11b0 | 4616 | case LT: |
9c0ac0fd | 4617 | fputs ("<", file); break; |
87ad11b0 | 4618 | case LE: |
9c0ac0fd | 4619 | fputs ("<=", file); break; |
87ad11b0 | 4620 | case LEU: |
9c0ac0fd | 4621 | fputs ("<<=", file); break; |
87ad11b0 | 4622 | case LTU: |
9c0ac0fd | 4623 | fputs ("<<", file); break; |
87ad11b0 | 4624 | default: |
ecf2283d | 4625 | gcc_unreachable (); |
87ad11b0 | 4626 | } |
4627 | return; | |
c8975385 | 4628 | case 'N': /* Condition, (N)egated */ |
87ad11b0 | 4629 | switch (GET_CODE (x)) |
4630 | { | |
4631 | case EQ: | |
9c0ac0fd | 4632 | fputs ("<>", file); break; |
87ad11b0 | 4633 | case NE: |
9c0ac0fd | 4634 | fputs ("=", file); break; |
87ad11b0 | 4635 | case GT: |
9c0ac0fd | 4636 | fputs ("<=", file); break; |
87ad11b0 | 4637 | case GE: |
9c0ac0fd | 4638 | fputs ("<", file); break; |
87ad11b0 | 4639 | case GEU: |
9c0ac0fd | 4640 | fputs ("<<", file); break; |
87ad11b0 | 4641 | case GTU: |
9c0ac0fd | 4642 | fputs ("<<=", file); break; |
87ad11b0 | 4643 | case LT: |
9c0ac0fd | 4644 | fputs (">=", file); break; |
87ad11b0 | 4645 | case LE: |
9c0ac0fd | 4646 | fputs (">", file); break; |
87ad11b0 | 4647 | case LEU: |
9c0ac0fd | 4648 | fputs (">>", file); break; |
87ad11b0 | 4649 | case LTU: |
9c0ac0fd | 4650 | fputs (">>=", file); break; |
87ad11b0 | 4651 | default: |
ecf2283d | 4652 | gcc_unreachable (); |
87ad11b0 | 4653 | } |
4654 | return; | |
ea52c577 | 4655 | /* For floating point comparisons. Note that the output |
321c1598 | 4656 | predicates are the complement of the desired mode. The |
4657 | conditions for GT, GE, LT, LE and LTGT cause an invalid | |
4658 | operation exception if the result is unordered and this | |
4659 | exception is enabled in the floating-point status register. */ | |
61230bc9 | 4660 | case 'Y': |
4661 | switch (GET_CODE (x)) | |
4662 | { | |
4663 | case EQ: | |
9c0ac0fd | 4664 | fputs ("!=", file); break; |
61230bc9 | 4665 | case NE: |
9c0ac0fd | 4666 | fputs ("=", file); break; |
61230bc9 | 4667 | case GT: |
32509e56 | 4668 | fputs ("!>", file); break; |
61230bc9 | 4669 | case GE: |
32509e56 | 4670 | fputs ("!>=", file); break; |
61230bc9 | 4671 | case LT: |
32509e56 | 4672 | fputs ("!<", file); break; |
61230bc9 | 4673 | case LE: |
32509e56 | 4674 | fputs ("!<=", file); break; |
4675 | case LTGT: | |
4676 | fputs ("!<>", file); break; | |
4677 | case UNLE: | |
321c1598 | 4678 | fputs ("!?<=", file); break; |
32509e56 | 4679 | case UNLT: |
321c1598 | 4680 | fputs ("!?<", file); break; |
32509e56 | 4681 | case UNGE: |
321c1598 | 4682 | fputs ("!?>=", file); break; |
32509e56 | 4683 | case UNGT: |
321c1598 | 4684 | fputs ("!?>", file); break; |
32509e56 | 4685 | case UNEQ: |
321c1598 | 4686 | fputs ("!?=", file); break; |
32509e56 | 4687 | case UNORDERED: |
321c1598 | 4688 | fputs ("!?", file); break; |
32509e56 | 4689 | case ORDERED: |
321c1598 | 4690 | fputs ("?", file); break; |
61230bc9 | 4691 | default: |
ecf2283d | 4692 | gcc_unreachable (); |
61230bc9 | 4693 | } |
4694 | return; | |
c8975385 | 4695 | case 'S': /* Condition, operands are (S)wapped. */ |
4696 | switch (GET_CODE (x)) | |
4697 | { | |
4698 | case EQ: | |
9c0ac0fd | 4699 | fputs ("=", file); break; |
c8975385 | 4700 | case NE: |
9c0ac0fd | 4701 | fputs ("<>", file); break; |
c8975385 | 4702 | case GT: |
9c0ac0fd | 4703 | fputs ("<", file); break; |
c8975385 | 4704 | case GE: |
9c0ac0fd | 4705 | fputs ("<=", file); break; |
c8975385 | 4706 | case GEU: |
9c0ac0fd | 4707 | fputs ("<<=", file); break; |
c8975385 | 4708 | case GTU: |
9c0ac0fd | 4709 | fputs ("<<", file); break; |
c8975385 | 4710 | case LT: |
9c0ac0fd | 4711 | fputs (">", file); break; |
c8975385 | 4712 | case LE: |
9c0ac0fd | 4713 | fputs (">=", file); break; |
c8975385 | 4714 | case LEU: |
9c0ac0fd | 4715 | fputs (">>=", file); break; |
c8975385 | 4716 | case LTU: |
9c0ac0fd | 4717 | fputs (">>", file); break; |
c8975385 | 4718 | default: |
ecf2283d | 4719 | gcc_unreachable (); |
6d36483b | 4720 | } |
c8975385 | 4721 | return; |
4722 | case 'B': /* Condition, (B)oth swapped and negate. */ | |
4723 | switch (GET_CODE (x)) | |
4724 | { | |
4725 | case EQ: | |
9c0ac0fd | 4726 | fputs ("<>", file); break; |
c8975385 | 4727 | case NE: |
9c0ac0fd | 4728 | fputs ("=", file); break; |
c8975385 | 4729 | case GT: |
9c0ac0fd | 4730 | fputs (">=", file); break; |
c8975385 | 4731 | case GE: |
9c0ac0fd | 4732 | fputs (">", file); break; |
c8975385 | 4733 | case GEU: |
9c0ac0fd | 4734 | fputs (">>", file); break; |
c8975385 | 4735 | case GTU: |
9c0ac0fd | 4736 | fputs (">>=", file); break; |
c8975385 | 4737 | case LT: |
9c0ac0fd | 4738 | fputs ("<=", file); break; |
c8975385 | 4739 | case LE: |
9c0ac0fd | 4740 | fputs ("<", file); break; |
c8975385 | 4741 | case LEU: |
9c0ac0fd | 4742 | fputs ("<<", file); break; |
c8975385 | 4743 | case LTU: |
9c0ac0fd | 4744 | fputs ("<<=", file); break; |
c8975385 | 4745 | default: |
ecf2283d | 4746 | gcc_unreachable (); |
6d36483b | 4747 | } |
c8975385 | 4748 | return; |
4749 | case 'k': | |
ecf2283d | 4750 | gcc_assert (GET_CODE (x) == CONST_INT); |
4751 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x)); | |
4752 | return; | |
5e3c5739 | 4753 | case 'Q': |
ecf2283d | 4754 | gcc_assert (GET_CODE (x) == CONST_INT); |
4755 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63)); | |
4756 | return; | |
e5965947 | 4757 | case 'L': |
ecf2283d | 4758 | gcc_assert (GET_CODE (x) == CONST_INT); |
4759 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31)); | |
4760 | return; | |
3a16146d | 4761 | case 'O': |
ecf2283d | 4762 | gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0); |
4763 | fprintf (file, "%d", exact_log2 (INTVAL (x))); | |
4764 | return; | |
5e3c5739 | 4765 | case 'p': |
ecf2283d | 4766 | gcc_assert (GET_CODE (x) == CONST_INT); |
4767 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63)); | |
4768 | return; | |
e5965947 | 4769 | case 'P': |
ecf2283d | 4770 | gcc_assert (GET_CODE (x) == CONST_INT); |
4771 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31)); | |
4772 | return; | |
c8975385 | 4773 | case 'I': |
4774 | if (GET_CODE (x) == CONST_INT) | |
4775 | fputs ("i", file); | |
4776 | return; | |
87ad11b0 | 4777 | case 'M': |
27ef382d | 4778 | case 'F': |
87ad11b0 | 4779 | switch (GET_CODE (XEXP (x, 0))) |
4780 | { | |
4781 | case PRE_DEC: | |
4782 | case PRE_INC: | |
e4065f95 | 4783 | if (ASSEMBLER_DIALECT == 0) |
4784 | fputs ("s,mb", file); | |
4785 | else | |
4786 | fputs (",mb", file); | |
87ad11b0 | 4787 | break; |
4788 | case POST_DEC: | |
4789 | case POST_INC: | |
e4065f95 | 4790 | if (ASSEMBLER_DIALECT == 0) |
4791 | fputs ("s,ma", file); | |
4792 | else | |
4793 | fputs (",ma", file); | |
87ad11b0 | 4794 | break; |
27ef382d | 4795 | case PLUS: |
dbd3d89d | 4796 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
4797 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
4798 | { | |
4799 | if (ASSEMBLER_DIALECT == 0) | |
4800 | fputs ("x", file); | |
4801 | } | |
4802 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT | |
4803 | || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) | |
e4065f95 | 4804 | { |
4805 | if (ASSEMBLER_DIALECT == 0) | |
4806 | fputs ("x,s", file); | |
4807 | else | |
4808 | fputs (",s", file); | |
4809 | } | |
4810 | else if (code == 'F' && ASSEMBLER_DIALECT == 0) | |
27ef382d | 4811 | fputs ("s", file); |
87ad11b0 | 4812 | break; |
4813 | default: | |
e4065f95 | 4814 | if (code == 'F' && ASSEMBLER_DIALECT == 0) |
27ef382d | 4815 | fputs ("s", file); |
87ad11b0 | 4816 | break; |
4817 | } | |
4818 | return; | |
4819 | case 'G': | |
f9333726 | 4820 | output_global_address (file, x, 0); |
4821 | return; | |
4822 | case 'H': | |
4823 | output_global_address (file, x, 1); | |
87ad11b0 | 4824 | return; |
4825 | case 0: /* Don't do anything special */ | |
4826 | break; | |
42faba01 | 4827 | case 'Z': |
4828 | { | |
4829 | unsigned op[3]; | |
fb22aedc | 4830 | compute_zdepwi_operands (INTVAL (x), op); |
42faba01 | 4831 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); |
4832 | return; | |
4833 | } | |
5e3c5739 | 4834 | case 'z': |
4835 | { | |
4836 | unsigned op[3]; | |
4837 | compute_zdepdi_operands (INTVAL (x), op); | |
4838 | fprintf (file, "%d,%d,%d", op[0], op[1], op[2]); | |
4839 | return; | |
4840 | } | |
c9cc98e1 | 4841 | case 'c': |
4842 | /* We can get here from a .vtable_inherit due to our | |
4843 | CONSTANT_ADDRESS_P rejecting perfectly good constant | |
4844 | addresses. */ | |
4845 | break; | |
87ad11b0 | 4846 | default: |
ecf2283d | 4847 | gcc_unreachable (); |
87ad11b0 | 4848 | } |
4849 | if (GET_CODE (x) == REG) | |
df0651dc | 4850 | { |
35661368 | 4851 | fputs (reg_names [REGNO (x)], file); |
5e3c5739 | 4852 | if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4) |
4853 | { | |
4854 | fputs ("R", file); | |
4855 | return; | |
4856 | } | |
4857 | if (FP_REG_P (x) | |
4858 | && GET_MODE_SIZE (GET_MODE (x)) <= 4 | |
4859 | && (REGNO (x) & 1) == 0) | |
35661368 | 4860 | fputs ("L", file); |
df0651dc | 4861 | } |
87ad11b0 | 4862 | else if (GET_CODE (x) == MEM) |
4863 | { | |
4864 | int size = GET_MODE_SIZE (GET_MODE (x)); | |
f7dff90d | 4865 | rtx base = NULL_RTX; |
87ad11b0 | 4866 | switch (GET_CODE (XEXP (x, 0))) |
4867 | { | |
4868 | case PRE_DEC: | |
4869 | case POST_DEC: | |
5e3c5739 | 4870 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 4871 | fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 4872 | break; |
4873 | case PRE_INC: | |
4874 | case POST_INC: | |
5e3c5739 | 4875 | base = XEXP (XEXP (x, 0), 0); |
34940871 | 4876 | fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]); |
87ad11b0 | 4877 | break; |
dbd3d89d | 4878 | case PLUS: |
4879 | if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT) | |
34940871 | 4880 | fprintf (file, "%s(%s)", |
27ef382d | 4881 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))], |
4882 | reg_names [REGNO (XEXP (XEXP (x, 0), 1))]); | |
dbd3d89d | 4883 | else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT) |
34940871 | 4884 | fprintf (file, "%s(%s)", |
27ef382d | 4885 | reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))], |
4886 | reg_names [REGNO (XEXP (XEXP (x, 0), 0))]); | |
dbd3d89d | 4887 | else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG |
4888 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG) | |
4889 | { | |
4890 | /* Because the REG_POINTER flag can get lost during reload, | |
4891 | GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the | |
4892 | index and base registers in the combined move patterns. */ | |
4893 | rtx base = XEXP (XEXP (x, 0), 1); | |
4894 | rtx index = XEXP (XEXP (x, 0), 0); | |
4895 | ||
4896 | fprintf (file, "%s(%s)", | |
4897 | reg_names [REGNO (index)], reg_names [REGNO (base)]); | |
4898 | } | |
27ef382d | 4899 | else |
4900 | output_address (XEXP (x, 0)); | |
87ad11b0 | 4901 | break; |
dbd3d89d | 4902 | default: |
4903 | output_address (XEXP (x, 0)); | |
4904 | break; | |
87ad11b0 | 4905 | } |
4906 | } | |
87ad11b0 | 4907 | else |
4908 | output_addr_const (file, x); | |
4909 | } | |
4910 | ||
6dc3b0d9 | 4911 | /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */ |
87ad11b0 | 4912 | |
4913 | void | |
5c1d8983 | 4914 | output_global_address (FILE *file, rtx x, int round_constant) |
87ad11b0 | 4915 | { |
2ee034bc | 4916 | |
4917 | /* Imagine (high (const (plus ...))). */ | |
4918 | if (GET_CODE (x) == HIGH) | |
4919 | x = XEXP (x, 0); | |
4920 | ||
611a88e1 | 4921 | if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode)) |
5f43b4f6 | 4922 | output_addr_const (file, x); |
b4a7bf10 | 4923 | else if (GET_CODE (x) == SYMBOL_REF && !flag_pic) |
87ad11b0 | 4924 | { |
5f43b4f6 | 4925 | output_addr_const (file, x); |
9c0ac0fd | 4926 | fputs ("-$global$", file); |
87ad11b0 | 4927 | } |
4928 | else if (GET_CODE (x) == CONST) | |
4929 | { | |
611a88e1 | 4930 | const char *sep = ""; |
87ad11b0 | 4931 | int offset = 0; /* assembler wants -$global$ at end */ |
33ae0dba | 4932 | rtx base = NULL_RTX; |
6d36483b | 4933 | |
ecf2283d | 4934 | switch (GET_CODE (XEXP (XEXP (x, 0), 0))) |
87ad11b0 | 4935 | { |
ecf2283d | 4936 | case SYMBOL_REF: |
87ad11b0 | 4937 | base = XEXP (XEXP (x, 0), 0); |
4938 | output_addr_const (file, base); | |
ecf2283d | 4939 | break; |
4940 | case CONST_INT: | |
4941 | offset = INTVAL (XEXP (XEXP (x, 0), 0)); | |
4942 | break; | |
4943 | default: | |
4944 | gcc_unreachable (); | |
87ad11b0 | 4945 | } |
87ad11b0 | 4946 | |
ecf2283d | 4947 | switch (GET_CODE (XEXP (XEXP (x, 0), 1))) |
87ad11b0 | 4948 | { |
ecf2283d | 4949 | case SYMBOL_REF: |
87ad11b0 | 4950 | base = XEXP (XEXP (x, 0), 1); |
4951 | output_addr_const (file, base); | |
ecf2283d | 4952 | break; |
4953 | case CONST_INT: | |
4954 | offset = INTVAL (XEXP (XEXP (x, 0), 1)); | |
4955 | break; | |
4956 | default: | |
4957 | gcc_unreachable (); | |
87ad11b0 | 4958 | } |
87ad11b0 | 4959 | |
f9333726 | 4960 | /* How bogus. The compiler is apparently responsible for |
4961 | rounding the constant if it uses an LR field selector. | |
4962 | ||
4963 | The linker and/or assembler seem a better place since | |
4964 | they have to do this kind of thing already. | |
4965 | ||
4966 | If we fail to do this, HP's optimizing linker may eliminate | |
4967 | an addil, but not update the ldw/stw/ldo instruction that | |
4968 | uses the result of the addil. */ | |
4969 | if (round_constant) | |
4970 | offset = ((offset + 0x1000) & ~0x1fff); | |
4971 | ||
ecf2283d | 4972 | switch (GET_CODE (XEXP (x, 0))) |
87ad11b0 | 4973 | { |
ecf2283d | 4974 | case PLUS: |
87ad11b0 | 4975 | if (offset < 0) |
4976 | { | |
4977 | offset = -offset; | |
4978 | sep = "-"; | |
4979 | } | |
4980 | else | |
4981 | sep = "+"; | |
ecf2283d | 4982 | break; |
4983 | ||
4984 | case MINUS: | |
4985 | gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF); | |
4986 | sep = "-"; | |
4987 | break; | |
87ad11b0 | 4988 | |
ecf2283d | 4989 | default: |
4990 | gcc_unreachable (); | |
4991 | } | |
4992 | ||
611a88e1 | 4993 | if (!read_only_operand (base, VOIDmode) && !flag_pic) |
9c0ac0fd | 4994 | fputs ("-$global$", file); |
f9333726 | 4995 | if (offset) |
ea52c577 | 4996 | fprintf (file, "%s%d", sep, offset); |
87ad11b0 | 4997 | } |
4998 | else | |
4999 | output_addr_const (file, x); | |
5000 | } | |
5001 | ||
92c473b8 | 5002 | /* Output boilerplate text to appear at the beginning of the file. |
5003 | There are several possible versions. */ | |
5004 | #define aputs(x) fputs(x, asm_out_file) | |
5005 | static inline void | |
5c1d8983 | 5006 | pa_file_start_level (void) |
92c473b8 | 5007 | { |
5008 | if (TARGET_64BIT) | |
5009 | aputs ("\t.LEVEL 2.0w\n"); | |
5010 | else if (TARGET_PA_20) | |
5011 | aputs ("\t.LEVEL 2.0\n"); | |
5012 | else if (TARGET_PA_11) | |
5013 | aputs ("\t.LEVEL 1.1\n"); | |
5014 | else | |
5015 | aputs ("\t.LEVEL 1.0\n"); | |
5016 | } | |
5017 | ||
5018 | static inline void | |
5c1d8983 | 5019 | pa_file_start_space (int sortspace) |
92c473b8 | 5020 | { |
5021 | aputs ("\t.SPACE $PRIVATE$"); | |
5022 | if (sortspace) | |
5023 | aputs (",SORT=16"); | |
5024 | aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31" | |
5025 | "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82" | |
5026 | "\n\t.SPACE $TEXT$"); | |
5027 | if (sortspace) | |
5028 | aputs (",SORT=8"); | |
5029 | aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44" | |
5030 | "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n"); | |
5031 | } | |
5032 | ||
5033 | static inline void | |
5c1d8983 | 5034 | pa_file_start_file (int want_version) |
92c473b8 | 5035 | { |
5036 | if (write_symbols != NO_DEBUG) | |
5037 | { | |
5038 | output_file_directive (asm_out_file, main_input_filename); | |
5039 | if (want_version) | |
5040 | aputs ("\t.version\t\"01.01\"\n"); | |
5041 | } | |
5042 | } | |
5043 | ||
5044 | static inline void | |
5c1d8983 | 5045 | pa_file_start_mcount (const char *aswhat) |
92c473b8 | 5046 | { |
5047 | if (profile_flag) | |
5048 | fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat); | |
5049 | } | |
5050 | ||
5051 | static void | |
5c1d8983 | 5052 | pa_elf_file_start (void) |
92c473b8 | 5053 | { |
5054 | pa_file_start_level (); | |
5055 | pa_file_start_mcount ("ENTRY"); | |
5056 | pa_file_start_file (0); | |
5057 | } | |
5058 | ||
5059 | static void | |
5c1d8983 | 5060 | pa_som_file_start (void) |
92c473b8 | 5061 | { |
5062 | pa_file_start_level (); | |
5063 | pa_file_start_space (0); | |
5064 | aputs ("\t.IMPORT $global$,DATA\n" | |
5065 | "\t.IMPORT $$dyncall,MILLICODE\n"); | |
5066 | pa_file_start_mcount ("CODE"); | |
5067 | pa_file_start_file (0); | |
5068 | } | |
5069 | ||
5070 | static void | |
5c1d8983 | 5071 | pa_linux_file_start (void) |
92c473b8 | 5072 | { |
5073 | pa_file_start_file (1); | |
5074 | pa_file_start_level (); | |
5075 | pa_file_start_mcount ("CODE"); | |
5076 | } | |
5077 | ||
5078 | static void | |
5c1d8983 | 5079 | pa_hpux64_gas_file_start (void) |
92c473b8 | 5080 | { |
5081 | pa_file_start_level (); | |
5082 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
5083 | if (profile_flag) | |
5084 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function"); | |
5085 | #endif | |
5086 | pa_file_start_file (1); | |
5087 | } | |
5088 | ||
5089 | static void | |
5c1d8983 | 5090 | pa_hpux64_hpas_file_start (void) |
92c473b8 | 5091 | { |
5092 | pa_file_start_level (); | |
5093 | pa_file_start_space (1); | |
5094 | pa_file_start_mcount ("CODE"); | |
5095 | pa_file_start_file (0); | |
5096 | } | |
5097 | #undef aputs | |
5098 | ||
ece88821 | 5099 | static struct deferred_plabel * |
5f43b4f6 | 5100 | get_plabel (rtx symbol) |
ece88821 | 5101 | { |
5f43b4f6 | 5102 | const char *fname = XSTR (symbol, 0); |
ece88821 | 5103 | size_t i; |
5104 | ||
5105 | /* See if we have already put this function on the list of deferred | |
5106 | plabels. This list is generally small, so a liner search is not | |
5107 | too ugly. If it proves too slow replace it with something faster. */ | |
5108 | for (i = 0; i < n_deferred_plabels; i++) | |
5f43b4f6 | 5109 | if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0) |
ece88821 | 5110 | break; |
5111 | ||
5112 | /* If the deferred plabel list is empty, or this entry was not found | |
5113 | on the list, create a new entry on the list. */ | |
5114 | if (deferred_plabels == NULL || i == n_deferred_plabels) | |
5115 | { | |
5f43b4f6 | 5116 | tree id; |
5117 | ||
ece88821 | 5118 | if (deferred_plabels == 0) |
5119 | deferred_plabels = (struct deferred_plabel *) | |
5120 | ggc_alloc (sizeof (struct deferred_plabel)); | |
5121 | else | |
5122 | deferred_plabels = (struct deferred_plabel *) | |
5123 | ggc_realloc (deferred_plabels, | |
5124 | ((n_deferred_plabels + 1) | |
5125 | * sizeof (struct deferred_plabel))); | |
5126 | ||
5127 | i = n_deferred_plabels++; | |
5128 | deferred_plabels[i].internal_label = gen_label_rtx (); | |
5f43b4f6 | 5129 | deferred_plabels[i].symbol = symbol; |
ece88821 | 5130 | |
5f43b4f6 | 5131 | /* Gross. We have just implicitly taken the address of this |
5132 | function. Mark it in the same manner as assemble_name. */ | |
5133 | id = maybe_get_identifier (targetm.strip_name_encoding (fname)); | |
5134 | if (id) | |
5135 | mark_referenced (id); | |
ece88821 | 5136 | } |
5137 | ||
5138 | return &deferred_plabels[i]; | |
5139 | } | |
5140 | ||
f6940372 | 5141 | static void |
5c1d8983 | 5142 | output_deferred_plabels (void) |
5cc6b2bc | 5143 | { |
e11bd7e5 | 5144 | size_t i; |
5cc6b2bc | 5145 | /* If we have deferred plabels, then we need to switch into the data |
5146 | section and align it to a 4 byte boundary before we output the | |
5147 | deferred plabels. */ | |
5148 | if (n_deferred_plabels) | |
5149 | { | |
5150 | data_section (); | |
f6940372 | 5151 | ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2); |
5cc6b2bc | 5152 | } |
5153 | ||
5154 | /* Now output the deferred plabels. */ | |
5155 | for (i = 0; i < n_deferred_plabels; i++) | |
5156 | { | |
f6940372 | 5157 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
5158 | CODE_LABEL_NUMBER (deferred_plabels[i].internal_label)); | |
5f43b4f6 | 5159 | assemble_integer (deferred_plabels[i].symbol, |
b70ea764 | 5160 | TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1); |
5cc6b2bc | 5161 | } |
5162 | } | |
5163 | ||
f2f543a3 | 5164 | #ifdef HPUX_LONG_DOUBLE_LIBRARY |
5165 | /* Initialize optabs to point to HPUX long double emulation routines. */ | |
5166 | static void | |
5167 | pa_hpux_init_libfuncs (void) | |
5168 | { | |
5169 | set_optab_libfunc (add_optab, TFmode, "_U_Qfadd"); | |
5170 | set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub"); | |
5171 | set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy"); | |
5172 | set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv"); | |
5173 | set_optab_libfunc (smin_optab, TFmode, "_U_Qmin"); | |
5174 | set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax"); | |
5175 | set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt"); | |
5176 | set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs"); | |
5177 | set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg"); | |
5178 | ||
c88a6ebd | 5179 | set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq"); |
5180 | set_optab_libfunc (ne_optab, TFmode, "_U_Qfne"); | |
5181 | set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt"); | |
5182 | set_optab_libfunc (ge_optab, TFmode, "_U_Qfge"); | |
5183 | set_optab_libfunc (lt_optab, TFmode, "_U_Qflt"); | |
5184 | set_optab_libfunc (le_optab, TFmode, "_U_Qfle"); | |
6b27baea | 5185 | set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord"); |
f2f543a3 | 5186 | |
a7cc195f | 5187 | set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad"); |
5188 | set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad"); | |
5189 | set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl"); | |
5190 | set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl"); | |
5191 | ||
5192 | set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT | |
5193 | ? "__U_Qfcnvfxt_quad_to_sgl" | |
5194 | : "_U_Qfcnvfxt_quad_to_sgl"); | |
5195 | set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl"); | |
5196 | set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl"); | |
5197 | set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl"); | |
5198 | ||
5199 | set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad"); | |
5200 | set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad"); | |
f2f543a3 | 5201 | } |
5202 | #endif | |
5203 | ||
87ad11b0 | 5204 | /* HP's millicode routines mean something special to the assembler. |
5205 | Keep track of which ones we have used. */ | |
5206 | ||
c2271c34 | 5207 | enum millicodes { remI, remU, divI, divU, mulI, end1000 }; |
5c1d8983 | 5208 | static void import_milli (enum millicodes); |
ea52c577 | 5209 | static char imported[(int) end1000]; |
c2271c34 | 5210 | static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"}; |
e99c3a1d | 5211 | static const char import_string[] = ".IMPORT $$....,MILLICODE"; |
87ad11b0 | 5212 | #define MILLI_START 10 |
5213 | ||
57ed30e5 | 5214 | static void |
5c1d8983 | 5215 | import_milli (enum millicodes code) |
87ad11b0 | 5216 | { |
5217 | char str[sizeof (import_string)]; | |
6d36483b | 5218 | |
ea52c577 | 5219 | if (!imported[(int) code]) |
87ad11b0 | 5220 | { |
ea52c577 | 5221 | imported[(int) code] = 1; |
87ad11b0 | 5222 | strcpy (str, import_string); |
ea52c577 | 5223 | strncpy (str + MILLI_START, milli_names[(int) code], 4); |
87ad11b0 | 5224 | output_asm_insn (str, 0); |
5225 | } | |
5226 | } | |
5227 | ||
6d36483b | 5228 | /* The register constraints have put the operands and return value in |
6dc3b0d9 | 5229 | the proper registers. */ |
87ad11b0 | 5230 | |
611a88e1 | 5231 | const char * |
5c1d8983 | 5232 | output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn) |
87ad11b0 | 5233 | { |
d178f670 | 5234 | import_milli (mulI); |
440c23df | 5235 | return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI")); |
87ad11b0 | 5236 | } |
5237 | ||
6dc3b0d9 | 5238 | /* Emit the rtl for doing a division by a constant. */ |
87ad11b0 | 5239 | |
d178f670 | 5240 | /* Do magic division millicodes exist for this value? */ |
913de4b4 | 5241 | const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1}; |
87ad11b0 | 5242 | |
6d36483b | 5243 | /* We'll use an array to keep track of the magic millicodes and |
87ad11b0 | 5244 | whether or not we've used them already. [n][0] is signed, [n][1] is |
6dc3b0d9 | 5245 | unsigned. */ |
87ad11b0 | 5246 | |
87ad11b0 | 5247 | static int div_milli[16][2]; |
5248 | ||
87ad11b0 | 5249 | int |
5c1d8983 | 5250 | emit_hpdiv_const (rtx *operands, int unsignedp) |
87ad11b0 | 5251 | { |
5252 | if (GET_CODE (operands[2]) == CONST_INT | |
5253 | && INTVAL (operands[2]) > 0 | |
5254 | && INTVAL (operands[2]) < 16 | |
5255 | && magic_milli[INTVAL (operands[2])]) | |
5256 | { | |
2013ddf6 | 5257 | rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31); |
5258 | ||
ad851752 | 5259 | emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]); |
87ad11b0 | 5260 | emit |
75b1a41a | 5261 | (gen_rtx_PARALLEL |
5262 | (VOIDmode, | |
c2078db8 | 5263 | gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29), |
ad851752 | 5264 | gen_rtx_fmt_ee (unsignedp ? UDIV : DIV, |
5265 | SImode, | |
5266 | gen_rtx_REG (SImode, 26), | |
5267 | operands[2])), | |
c2078db8 | 5268 | gen_rtx_CLOBBER (VOIDmode, operands[4]), |
ad851752 | 5269 | gen_rtx_CLOBBER (VOIDmode, operands[3]), |
5270 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)), | |
5271 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)), | |
2013ddf6 | 5272 | gen_rtx_CLOBBER (VOIDmode, ret)))); |
ad851752 | 5273 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 29)); |
87ad11b0 | 5274 | return 1; |
5275 | } | |
5276 | return 0; | |
5277 | } | |
5278 | ||
611a88e1 | 5279 | const char * |
5c1d8983 | 5280 | output_div_insn (rtx *operands, int unsignedp, rtx insn) |
87ad11b0 | 5281 | { |
5282 | int divisor; | |
6d36483b | 5283 | |
5284 | /* If the divisor is a constant, try to use one of the special | |
87ad11b0 | 5285 | opcodes .*/ |
5286 | if (GET_CODE (operands[0]) == CONST_INT) | |
5287 | { | |
d6686e21 | 5288 | static char buf[100]; |
87ad11b0 | 5289 | divisor = INTVAL (operands[0]); |
5290 | if (!div_milli[divisor][unsignedp]) | |
5291 | { | |
d6686e21 | 5292 | div_milli[divisor][unsignedp] = 1; |
87ad11b0 | 5293 | if (unsignedp) |
5294 | output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands); | |
5295 | else | |
5296 | output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands); | |
87ad11b0 | 5297 | } |
5298 | if (unsignedp) | |
d6686e21 | 5299 | { |
4840a03a | 5300 | sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC, |
5301 | INTVAL (operands[0])); | |
c7a4e712 | 5302 | return output_millicode_call (insn, |
ad851752 | 5303 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5304 | } |
5305 | else | |
5306 | { | |
4840a03a | 5307 | sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC, |
5308 | INTVAL (operands[0])); | |
c7a4e712 | 5309 | return output_millicode_call (insn, |
ad851752 | 5310 | gen_rtx_SYMBOL_REF (SImode, buf)); |
d6686e21 | 5311 | } |
87ad11b0 | 5312 | } |
6dc3b0d9 | 5313 | /* Divisor isn't a special constant. */ |
87ad11b0 | 5314 | else |
5315 | { | |
5316 | if (unsignedp) | |
5317 | { | |
5318 | import_milli (divU); | |
c7a4e712 | 5319 | return output_millicode_call (insn, |
ad851752 | 5320 | gen_rtx_SYMBOL_REF (SImode, "$$divU")); |
87ad11b0 | 5321 | } |
5322 | else | |
5323 | { | |
5324 | import_milli (divI); | |
c7a4e712 | 5325 | return output_millicode_call (insn, |
ad851752 | 5326 | gen_rtx_SYMBOL_REF (SImode, "$$divI")); |
87ad11b0 | 5327 | } |
5328 | } | |
5329 | } | |
5330 | ||
6dc3b0d9 | 5331 | /* Output a $$rem millicode to do mod. */ |
87ad11b0 | 5332 | |
611a88e1 | 5333 | const char * |
5c1d8983 | 5334 | output_mod_insn (int unsignedp, rtx insn) |
87ad11b0 | 5335 | { |
5336 | if (unsignedp) | |
5337 | { | |
5338 | import_milli (remU); | |
c7a4e712 | 5339 | return output_millicode_call (insn, |
ad851752 | 5340 | gen_rtx_SYMBOL_REF (SImode, "$$remU")); |
87ad11b0 | 5341 | } |
5342 | else | |
5343 | { | |
5344 | import_milli (remI); | |
c7a4e712 | 5345 | return output_millicode_call (insn, |
ad851752 | 5346 | gen_rtx_SYMBOL_REF (SImode, "$$remI")); |
87ad11b0 | 5347 | } |
5348 | } | |
5349 | ||
5350 | void | |
5c1d8983 | 5351 | output_arg_descriptor (rtx call_insn) |
87ad11b0 | 5352 | { |
611a88e1 | 5353 | const char *arg_regs[4]; |
87ad11b0 | 5354 | enum machine_mode arg_mode; |
df0651dc | 5355 | rtx link; |
87ad11b0 | 5356 | int i, output_flag = 0; |
5357 | int regno; | |
6d36483b | 5358 | |
5e3c5739 | 5359 | /* We neither need nor want argument location descriptors for the |
5d0619cc | 5360 | 64bit runtime environment or the ELF32 environment. */ |
5361 | if (TARGET_64BIT || TARGET_ELF32) | |
5e3c5739 | 5362 | return; |
5363 | ||
87ad11b0 | 5364 | for (i = 0; i < 4; i++) |
5365 | arg_regs[i] = 0; | |
5366 | ||
738176ab | 5367 | /* Specify explicitly that no argument relocations should take place |
5368 | if using the portable runtime calling conventions. */ | |
5369 | if (TARGET_PORTABLE_RUNTIME) | |
5370 | { | |
9c0ac0fd | 5371 | fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n", |
5372 | asm_out_file); | |
738176ab | 5373 | return; |
5374 | } | |
5375 | ||
ecf2283d | 5376 | gcc_assert (GET_CODE (call_insn) == CALL_INSN); |
5377 | for (link = CALL_INSN_FUNCTION_USAGE (call_insn); | |
5378 | link; link = XEXP (link, 1)) | |
87ad11b0 | 5379 | { |
df0651dc | 5380 | rtx use = XEXP (link, 0); |
c12afafd | 5381 | |
df0651dc | 5382 | if (! (GET_CODE (use) == USE |
5383 | && GET_CODE (XEXP (use, 0)) == REG | |
5384 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
c12afafd | 5385 | continue; |
5386 | ||
df0651dc | 5387 | arg_mode = GET_MODE (XEXP (use, 0)); |
5388 | regno = REGNO (XEXP (use, 0)); | |
87ad11b0 | 5389 | if (regno >= 23 && regno <= 26) |
372ef038 | 5390 | { |
5391 | arg_regs[26 - regno] = "GR"; | |
5392 | if (arg_mode == DImode) | |
5393 | arg_regs[25 - regno] = "GR"; | |
5394 | } | |
df0651dc | 5395 | else if (regno >= 32 && regno <= 39) |
87ad11b0 | 5396 | { |
5397 | if (arg_mode == SFmode) | |
df0651dc | 5398 | arg_regs[(regno - 32) / 2] = "FR"; |
e6ba640e | 5399 | else |
87ad11b0 | 5400 | { |
eeec72c0 | 5401 | #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED |
df0651dc | 5402 | arg_regs[(regno - 34) / 2] = "FR"; |
5403 | arg_regs[(regno - 34) / 2 + 1] = "FU"; | |
87ad11b0 | 5404 | #else |
df0651dc | 5405 | arg_regs[(regno - 34) / 2] = "FU"; |
5406 | arg_regs[(regno - 34) / 2 + 1] = "FR"; | |
87ad11b0 | 5407 | #endif |
5408 | } | |
87ad11b0 | 5409 | } |
5410 | } | |
5411 | fputs ("\t.CALL ", asm_out_file); | |
5412 | for (i = 0; i < 4; i++) | |
5413 | { | |
5414 | if (arg_regs[i]) | |
5415 | { | |
5416 | if (output_flag++) | |
5417 | fputc (',', asm_out_file); | |
5418 | fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]); | |
5419 | } | |
5420 | } | |
5421 | fputc ('\n', asm_out_file); | |
5422 | } | |
5423 | \f | |
9c0ac0fd | 5424 | /* Return the class of any secondary reload register that is needed to |
5425 | move IN into a register in class CLASS using mode MODE. | |
5426 | ||
5427 | Profiling has showed this routine and its descendants account for | |
5428 | a significant amount of compile time (~7%). So it has been | |
5429 | optimized to reduce redundant computations and eliminate useless | |
5430 | function calls. | |
5431 | ||
5432 | It might be worthwhile to try and make this a leaf function too. */ | |
87ad11b0 | 5433 | |
5434 | enum reg_class | |
5c1d8983 | 5435 | secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in) |
87ad11b0 | 5436 | { |
9c0ac0fd | 5437 | int regno, is_symbolic; |
87ad11b0 | 5438 | |
b4a7bf10 | 5439 | /* Trying to load a constant into a FP register during PIC code |
5440 | generation will require %r1 as a scratch register. */ | |
fc44315f | 5441 | if (flag_pic |
b4a7bf10 | 5442 | && GET_MODE_CLASS (mode) == MODE_INT |
5443 | && FP_REG_CLASS_P (class) | |
5444 | && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE)) | |
5445 | return R1_REGS; | |
5446 | ||
9c0ac0fd | 5447 | /* Profiling showed the PA port spends about 1.3% of its compilation |
5448 | time in true_regnum from calls inside secondary_reload_class. */ | |
5449 | ||
5450 | if (GET_CODE (in) == REG) | |
5451 | { | |
5452 | regno = REGNO (in); | |
5453 | if (regno >= FIRST_PSEUDO_REGISTER) | |
5454 | regno = true_regnum (in); | |
5455 | } | |
5456 | else if (GET_CODE (in) == SUBREG) | |
5457 | regno = true_regnum (in); | |
9c0ac0fd | 5458 | else |
5459 | regno = -1; | |
5460 | ||
76a0ced5 | 5461 | /* If we have something like (mem (mem (...)), we can safely assume the |
5462 | inner MEM will end up in a general register after reloading, so there's | |
5463 | no need for a secondary reload. */ | |
5464 | if (GET_CODE (in) == MEM | |
5465 | && GET_CODE (XEXP (in, 0)) == MEM) | |
5466 | return NO_REGS; | |
5467 | ||
5468 | /* Handle out of range displacement for integer mode loads/stores of | |
5469 | FP registers. */ | |
d2498717 | 5470 | if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1) |
6d36483b | 5471 | && GET_MODE_CLASS (mode) == MODE_INT |
5472 | && FP_REG_CLASS_P (class)) | |
d6f01525 | 5473 | || (class == SHIFT_REGS && (regno <= 0 || regno >= 32))) |
9c6d4825 | 5474 | return GENERAL_REGS; |
d2c1d63d | 5475 | |
7c4b32f3 | 5476 | /* A SAR<->FP register copy requires a secondary register (GPR) as |
5477 | well as secondary memory. */ | |
5478 | if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER | |
5479 | && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class)) | |
5480 | || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno))))) | |
5481 | return GENERAL_REGS; | |
5482 | ||
2ee034bc | 5483 | if (GET_CODE (in) == HIGH) |
5484 | in = XEXP (in, 0); | |
5485 | ||
9c0ac0fd | 5486 | /* Profiling has showed GCC spends about 2.6% of its compilation |
5487 | time in symbolic_operand from calls inside secondary_reload_class. | |
5488 | ||
5489 | We use an inline copy and only compute its return value once to avoid | |
5490 | useless work. */ | |
5491 | switch (GET_CODE (in)) | |
5492 | { | |
5493 | rtx tmp; | |
5494 | ||
5495 | case SYMBOL_REF: | |
5496 | case LABEL_REF: | |
5497 | is_symbolic = 1; | |
5498 | break; | |
5499 | case CONST: | |
5500 | tmp = XEXP (in, 0); | |
5501 | is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF | |
5502 | || GET_CODE (XEXP (tmp, 0)) == LABEL_REF) | |
5503 | && GET_CODE (XEXP (tmp, 1)) == CONST_INT); | |
5504 | break; | |
76a0ced5 | 5505 | |
9c0ac0fd | 5506 | default: |
5507 | is_symbolic = 0; | |
5508 | break; | |
5509 | } | |
9840d99d | 5510 | |
b4a7bf10 | 5511 | if (!flag_pic |
9c0ac0fd | 5512 | && is_symbolic |
611a88e1 | 5513 | && read_only_operand (in, VOIDmode)) |
b4a7bf10 | 5514 | return NO_REGS; |
5515 | ||
9c0ac0fd | 5516 | if (class != R1_REGS && is_symbolic) |
2ee034bc | 5517 | return R1_REGS; |
5518 | ||
d2c1d63d | 5519 | return NO_REGS; |
87ad11b0 | 5520 | } |
5521 | ||
b981d932 | 5522 | /* In the 32-bit runtime, arguments larger than eight bytes are passed |
5523 | by invisible reference. As a GCC extension, we also pass anything | |
5524 | with a zero or variable size by reference. | |
5525 | ||
5526 | The 64-bit runtime does not describe passing any types by invisible | |
5527 | reference. The internals of GCC can't currently handle passing | |
5528 | empty structures, and zero or variable length arrays when they are | |
5529 | not passed entirely on the stack or by reference. Thus, as a GCC | |
5530 | extension, we pass these types by reference. The HP compiler doesn't | |
5531 | support these types, so hopefully there shouldn't be any compatibility | |
5532 | issues. This may have to be revisited when HP releases a C99 compiler | |
5533 | or updates the ABI. */ | |
5534 | ||
5535 | static bool | |
5536 | pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, | |
5537 | enum machine_mode mode, tree type, | |
5538 | bool named ATTRIBUTE_UNUSED) | |
5539 | { | |
5540 | HOST_WIDE_INT size; | |
5541 | ||
5542 | if (type) | |
5543 | size = int_size_in_bytes (type); | |
5544 | else | |
5545 | size = GET_MODE_SIZE (mode); | |
5546 | ||
5547 | if (TARGET_64BIT) | |
5548 | return size <= 0; | |
5549 | else | |
5550 | return size <= 0 || size > 8; | |
5551 | } | |
5552 | ||
87ad11b0 | 5553 | enum direction |
5c1d8983 | 5554 | function_arg_padding (enum machine_mode mode, tree type) |
87ad11b0 | 5555 | { |
ac965869 | 5556 | if (mode == BLKmode |
5557 | || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type))) | |
5558 | { | |
5559 | /* Return none if justification is not required. */ | |
5560 | if (type | |
5561 | && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST | |
5562 | && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0) | |
5563 | return none; | |
5564 | ||
5565 | /* The directions set here are ignored when a BLKmode argument larger | |
5566 | than a word is placed in a register. Different code is used for | |
5567 | the stack and registers. This makes it difficult to have a | |
5568 | consistent data representation for both the stack and registers. | |
5569 | For both runtimes, the justification and padding for arguments on | |
5570 | the stack and in registers should be identical. */ | |
5571 | if (TARGET_64BIT) | |
5572 | /* The 64-bit runtime specifies left justification for aggregates. */ | |
5573 | return upward; | |
87ad11b0 | 5574 | else |
ac965869 | 5575 | /* The 32-bit runtime architecture specifies right justification. |
5576 | When the argument is passed on the stack, the argument is padded | |
5577 | with garbage on the left. The HP compiler pads with zeros. */ | |
5578 | return downward; | |
87ad11b0 | 5579 | } |
ac965869 | 5580 | |
5581 | if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY) | |
87ad11b0 | 5582 | return downward; |
87ad11b0 | 5583 | else |
5584 | return none; | |
5585 | } | |
5586 | ||
87ad11b0 | 5587 | \f |
55f54832 | 5588 | /* Do what is necessary for `va_start'. We look at the current function |
5589 | to determine if stdargs or varargs is used and fill in an initial | |
5590 | va_list. A pointer to this constructor is returned. */ | |
87ad11b0 | 5591 | |
b8debbe8 | 5592 | static rtx |
5c1d8983 | 5593 | hppa_builtin_saveregs (void) |
87ad11b0 | 5594 | { |
01251cbc | 5595 | rtx offset, dest; |
87ad11b0 | 5596 | tree fntype = TREE_TYPE (current_function_decl); |
5597 | int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0 | |
5598 | && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) | |
5599 | != void_type_node))) | |
5600 | ? UNITS_PER_WORD : 0); | |
5601 | ||
5602 | if (argadj) | |
5603 | offset = plus_constant (current_function_arg_offset_rtx, argadj); | |
5604 | else | |
5605 | offset = current_function_arg_offset_rtx; | |
9c6d4825 | 5606 | |
5e3c5739 | 5607 | if (TARGET_64BIT) |
5608 | { | |
5609 | int i, off; | |
9840d99d | 5610 | |
5e3c5739 | 5611 | /* Adjust for varargs/stdarg differences. */ |
5612 | if (argadj) | |
5613 | offset = plus_constant (current_function_arg_offset_rtx, -argadj); | |
5614 | else | |
5615 | offset = current_function_arg_offset_rtx; | |
5616 | ||
5617 | /* We need to save %r26 .. %r19 inclusive starting at offset -64 | |
5618 | from the incoming arg pointer and growing to larger addresses. */ | |
5619 | for (i = 26, off = -64; i >= 19; i--, off += 8) | |
5620 | emit_move_insn (gen_rtx_MEM (word_mode, | |
5621 | plus_constant (arg_pointer_rtx, off)), | |
5622 | gen_rtx_REG (word_mode, i)); | |
5623 | ||
5624 | /* The incoming args pointer points just beyond the flushback area; | |
8ef587dc | 5625 | normally this is not a serious concern. However, when we are doing |
5e3c5739 | 5626 | varargs/stdargs we want to make the arg pointer point to the start |
5627 | of the incoming argument area. */ | |
5628 | emit_move_insn (virtual_incoming_args_rtx, | |
5629 | plus_constant (arg_pointer_rtx, -64)); | |
5630 | ||
5631 | /* Now return a pointer to the first anonymous argument. */ | |
5632 | return copy_to_reg (expand_binop (Pmode, add_optab, | |
5633 | virtual_incoming_args_rtx, | |
5634 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
5635 | } | |
5636 | ||
6dc3b0d9 | 5637 | /* Store general registers on the stack. */ |
ad851752 | 5638 | dest = gen_rtx_MEM (BLKmode, |
5639 | plus_constant (current_function_internal_arg_pointer, | |
5640 | -16)); | |
ab6ab77e | 5641 | set_mem_alias_set (dest, get_varargs_alias_set ()); |
2a631e19 | 5642 | set_mem_align (dest, BITS_PER_WORD); |
530178a9 | 5643 | move_block_from_reg (23, dest, 4); |
01251cbc | 5644 | |
76a0ced5 | 5645 | /* move_block_from_reg will emit code to store the argument registers |
5646 | individually as scalar stores. | |
5647 | ||
5648 | However, other insns may later load from the same addresses for | |
ad87de1e | 5649 | a structure load (passing a struct to a varargs routine). |
76a0ced5 | 5650 | |
5651 | The alias code assumes that such aliasing can never happen, so we | |
5652 | have to keep memory referencing insns from moving up beyond the | |
5653 | last argument register store. So we emit a blockage insn here. */ | |
5654 | emit_insn (gen_blockage ()); | |
5655 | ||
9c6d4825 | 5656 | return copy_to_reg (expand_binop (Pmode, add_optab, |
5657 | current_function_internal_arg_pointer, | |
5658 | offset, 0, 0, OPTAB_LIB_WIDEN)); | |
87ad11b0 | 5659 | } |
d6f01525 | 5660 | |
72899a61 | 5661 | void |
5c1d8983 | 5662 | hppa_va_start (tree valist, rtx nextarg) |
72899a61 | 5663 | { |
5664 | nextarg = expand_builtin_saveregs (); | |
7df226a2 | 5665 | std_expand_builtin_va_start (valist, nextarg); |
72899a61 | 5666 | } |
5667 | ||
4c33eb68 | 5668 | static tree |
5669 | hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p) | |
72899a61 | 5670 | { |
5e3c5739 | 5671 | if (TARGET_64BIT) |
5672 | { | |
4c33eb68 | 5673 | /* Args grow upward. We can use the generic routines. */ |
bef380a4 | 5674 | return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
72899a61 | 5675 | } |
ac965869 | 5676 | else /* !TARGET_64BIT */ |
72899a61 | 5677 | { |
4c33eb68 | 5678 | tree ptr = build_pointer_type (type); |
5679 | tree valist_type; | |
5680 | tree t, u; | |
5681 | unsigned int size, ofs; | |
bef380a4 | 5682 | bool indirect; |
72899a61 | 5683 | |
bef380a4 | 5684 | indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0); |
4c33eb68 | 5685 | if (indirect) |
ac965869 | 5686 | { |
4c33eb68 | 5687 | type = ptr; |
5688 | ptr = build_pointer_type (type); | |
72899a61 | 5689 | } |
4c33eb68 | 5690 | size = int_size_in_bytes (type); |
5691 | valist_type = TREE_TYPE (valist); | |
ac965869 | 5692 | |
4c33eb68 | 5693 | /* Args grow down. Not handled by generic routines. */ |
ac965869 | 5694 | |
4c33eb68 | 5695 | u = fold_convert (valist_type, size_in_bytes (type)); |
5696 | t = build (MINUS_EXPR, valist_type, valist, u); | |
ac965869 | 5697 | |
4c33eb68 | 5698 | /* Copied from va-pa.h, but we probably don't need to align to |
5699 | word size, since we generate and preserve that invariant. */ | |
7016c612 | 5700 | u = build_int_cst (valist_type, (size > 4 ? -8 : -4)); |
4c33eb68 | 5701 | t = build (BIT_AND_EXPR, valist_type, t, u); |
5702 | ||
5703 | t = build (MODIFY_EXPR, valist_type, valist, t); | |
72899a61 | 5704 | |
4c33eb68 | 5705 | ofs = (8 - size) % 4; |
5706 | if (ofs != 0) | |
5707 | { | |
5708 | u = fold_convert (valist_type, size_int (ofs)); | |
5709 | t = build (PLUS_EXPR, valist_type, t, u); | |
ac965869 | 5710 | } |
72899a61 | 5711 | |
4c33eb68 | 5712 | t = fold_convert (ptr, t); |
5713 | t = build_fold_indirect_ref (t); | |
72899a61 | 5714 | |
4c33eb68 | 5715 | if (indirect) |
5716 | t = build_fold_indirect_ref (t); | |
72899a61 | 5717 | |
4c33eb68 | 5718 | return t; |
5719 | } | |
5720 | } | |
72899a61 | 5721 | |
2b1e7cc3 | 5722 | /* True if MODE is valid for the target. By "valid", we mean able to |
5723 | be manipulated in non-trivial ways. In particular, this means all | |
5724 | the arithmetic is supported. | |
5725 | ||
5726 | Currently, TImode is not valid as the HP 64-bit runtime documentation | |
5727 | doesn't document the alignment and calling conventions for this type. | |
5728 | Thus, we return false when PRECISION is 2 * BITS_PER_WORD and | |
5729 | 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */ | |
5730 | ||
5731 | static bool | |
5732 | pa_scalar_mode_supported_p (enum machine_mode mode) | |
5733 | { | |
5734 | int precision = GET_MODE_PRECISION (mode); | |
5735 | ||
5736 | switch (GET_MODE_CLASS (mode)) | |
5737 | { | |
5738 | case MODE_PARTIAL_INT: | |
5739 | case MODE_INT: | |
5740 | if (precision == CHAR_TYPE_SIZE) | |
5741 | return true; | |
5742 | if (precision == SHORT_TYPE_SIZE) | |
5743 | return true; | |
5744 | if (precision == INT_TYPE_SIZE) | |
5745 | return true; | |
5746 | if (precision == LONG_TYPE_SIZE) | |
5747 | return true; | |
5748 | if (precision == LONG_LONG_TYPE_SIZE) | |
5749 | return true; | |
5750 | return false; | |
5751 | ||
5752 | case MODE_FLOAT: | |
5753 | if (precision == FLOAT_TYPE_SIZE) | |
5754 | return true; | |
5755 | if (precision == DOUBLE_TYPE_SIZE) | |
5756 | return true; | |
5757 | if (precision == LONG_DOUBLE_TYPE_SIZE) | |
5758 | return true; | |
5759 | return false; | |
5760 | ||
5761 | default: | |
5762 | gcc_unreachable (); | |
5763 | } | |
5764 | } | |
5765 | ||
6d36483b | 5766 | /* This routine handles all the normal conditional branch sequences we |
5767 | might need to generate. It handles compare immediate vs compare | |
5768 | register, nullification of delay slots, varying length branches, | |
0d986529 | 5769 | negated branches, and all combinations of the above. It returns the |
6d36483b | 5770 | output appropriate to emit the branch corresponding to all given |
0d986529 | 5771 | parameters. */ |
5772 | ||
611a88e1 | 5773 | const char * |
5c1d8983 | 5774 | output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn) |
29a4502c | 5775 | { |
0d986529 | 5776 | static char buf[100]; |
5777 | int useskip = 0; | |
e9ec370e | 5778 | rtx xoperands[5]; |
0d986529 | 5779 | |
a361b456 | 5780 | /* A conditional branch to the following instruction (e.g. the delay slot) |
ece0fa59 | 5781 | is asking for a disaster. This can happen when not optimizing and |
5782 | when jump optimization fails. | |
29a4502c | 5783 | |
38efba6c | 5784 | While it is usually safe to emit nothing, this can fail if the |
5785 | preceding instruction is a nullified branch with an empty delay | |
5786 | slot and the same branch target as this branch. We could check | |
5787 | for this but jump optimization should eliminate nop jumps. It | |
5788 | is always safe to emit a nop. */ | |
ece0fa59 | 5789 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
5790 | return "nop"; | |
6d36483b | 5791 | |
22699a7e | 5792 | /* The doubleword form of the cmpib instruction doesn't have the LEU |
5793 | and GTU conditions while the cmpb instruction does. Since we accept | |
5794 | zero for cmpb, we must ensure that we use cmpb for the comparison. */ | |
5795 | if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx) | |
5796 | operands[2] = gen_rtx_REG (DImode, 0); | |
5797 | ||
5fbd5940 | 5798 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
5799 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 5800 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 5801 | nullify = 1; |
5802 | ||
5803 | /* If this is a short forward conditional branch which did not get | |
5804 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 5805 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 5806 | nullify = forward_branch_p (insn); |
5807 | ||
6d36483b | 5808 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 5809 | comclr instruction. This avoids a single cycle penalty due to |
5810 | mis-predicted branch if we fall through (branch not taken). */ | |
5a1231ef | 5811 | if (length == 4 |
5fbd5940 | 5812 | && next_real_insn (insn) != 0 |
5a1231ef | 5813 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 5814 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 5815 | && nullify) |
5816 | useskip = 1; | |
5817 | ||
5818 | switch (length) | |
5819 | { | |
5fbd5940 | 5820 | /* All short conditional branches except backwards with an unfilled |
5821 | delay slot. */ | |
5a1231ef | 5822 | case 4: |
0d986529 | 5823 | if (useskip) |
e4065f95 | 5824 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
0d986529 | 5825 | else |
e4065f95 | 5826 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 5827 | if (GET_MODE (operands[1]) == DImode) |
5828 | strcat (buf, "*"); | |
0d986529 | 5829 | if (negated) |
5830 | strcat (buf, "%B3"); | |
5831 | else | |
5832 | strcat (buf, "%S3"); | |
5833 | if (useskip) | |
5a811d43 | 5834 | strcat (buf, " %2,%r1,%%r0"); |
0d986529 | 5835 | else if (nullify) |
9e49be0e | 5836 | strcat (buf, ",n %2,%r1,%0"); |
6d36483b | 5837 | else |
9e49be0e | 5838 | strcat (buf, " %2,%r1,%0"); |
0d986529 | 5839 | break; |
5840 | ||
87fcb603 | 5841 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 5842 | unfilled delay slot is treated just like a long backward branch |
5843 | with an unfilled delay slot. */ | |
5a1231ef | 5844 | case 8: |
5fbd5940 | 5845 | /* Handle weird backwards branch with a filled delay slot |
5846 | with is nullified. */ | |
5847 | if (dbr_sequence_length () != 0 | |
5848 | && ! forward_branch_p (insn) | |
5849 | && nullify) | |
5850 | { | |
e4065f95 | 5851 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 5852 | if (GET_MODE (operands[1]) == DImode) |
5853 | strcat (buf, "*"); | |
5fbd5940 | 5854 | if (negated) |
5855 | strcat (buf, "%S3"); | |
5856 | else | |
5857 | strcat (buf, "%B3"); | |
5a811d43 | 5858 | strcat (buf, ",n %2,%r1,.+12\n\tb %0"); |
5fbd5940 | 5859 | } |
43f0c1f2 | 5860 | /* Handle short backwards branch with an unfilled delay slot. |
5861 | Using a comb;nop rather than comiclr;bl saves 1 cycle for both | |
5862 | taken and untaken branches. */ | |
5863 | else if (dbr_sequence_length () == 0 | |
5864 | && ! forward_branch_p (insn) | |
47fc0706 | 5865 | && INSN_ADDRESSES_SET_P () |
5866 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
5867 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 5868 | { |
e4065f95 | 5869 | strcpy (buf, "{com%I2b,|cmp%I2b,}"); |
5e3c5739 | 5870 | if (GET_MODE (operands[1]) == DImode) |
5871 | strcat (buf, "*"); | |
43f0c1f2 | 5872 | if (negated) |
9e49be0e | 5873 | strcat (buf, "%B3 %2,%r1,%0%#"); |
43f0c1f2 | 5874 | else |
9e49be0e | 5875 | strcat (buf, "%S3 %2,%r1,%0%#"); |
43f0c1f2 | 5876 | } |
0d986529 | 5877 | else |
5fbd5940 | 5878 | { |
e4065f95 | 5879 | strcpy (buf, "{com%I2clr,|cmp%I2clr,}"); |
5e3c5739 | 5880 | if (GET_MODE (operands[1]) == DImode) |
5881 | strcat (buf, "*"); | |
5fbd5940 | 5882 | if (negated) |
5883 | strcat (buf, "%S3"); | |
5884 | else | |
5885 | strcat (buf, "%B3"); | |
5886 | if (nullify) | |
5a811d43 | 5887 | strcat (buf, " %2,%r1,%%r0\n\tb,n %0"); |
5fbd5940 | 5888 | else |
5a811d43 | 5889 | strcat (buf, " %2,%r1,%%r0\n\tb %0"); |
5fbd5940 | 5890 | } |
0d986529 | 5891 | break; |
5892 | ||
c8a0e52b | 5893 | case 20: |
e9ec370e | 5894 | case 28: |
5895 | xoperands[0] = operands[0]; | |
5896 | xoperands[1] = operands[1]; | |
5897 | xoperands[2] = operands[2]; | |
5898 | xoperands[3] = operands[3]; | |
5899 | ||
5900 | /* The reversed conditional branch must branch over one additional | |
5901 | instruction if the delay slot is filled. If the delay slot | |
5902 | is empty, the instruction after the reversed condition branch | |
5903 | must be nullified. */ | |
5904 | nullify = dbr_sequence_length () == 0; | |
5905 | xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4); | |
c8a0e52b | 5906 | |
5907 | /* Create a reversed conditional branch which branches around | |
5908 | the following insns. */ | |
e9ec370e | 5909 | if (GET_MODE (operands[1]) != DImode) |
5910 | { | |
5911 | if (nullify) | |
5912 | { | |
5913 | if (negated) | |
5914 | strcpy (buf, | |
5915 | "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}"); | |
5916 | else | |
5917 | strcpy (buf, | |
5918 | "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}"); | |
5919 | } | |
5920 | else | |
5921 | { | |
5922 | if (negated) | |
5923 | strcpy (buf, | |
5924 | "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}"); | |
5925 | else | |
5926 | strcpy (buf, | |
5927 | "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}"); | |
5928 | } | |
5929 | } | |
c8a0e52b | 5930 | else |
5e3c5739 | 5931 | { |
e9ec370e | 5932 | if (nullify) |
5933 | { | |
5934 | if (negated) | |
5935 | strcpy (buf, | |
5936 | "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}"); | |
5937 | else | |
5938 | strcpy (buf, | |
5939 | "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}"); | |
5940 | } | |
5e3c5739 | 5941 | else |
e9ec370e | 5942 | { |
5943 | if (negated) | |
5944 | strcpy (buf, | |
5945 | "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}"); | |
5946 | else | |
5947 | strcpy (buf, | |
5948 | "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}"); | |
5949 | } | |
5e3c5739 | 5950 | } |
c8a0e52b | 5951 | |
e9ec370e | 5952 | output_asm_insn (buf, xoperands); |
5953 | return output_lbranch (operands[0], insn); | |
c8a0e52b | 5954 | |
e9ec370e | 5955 | default: |
ecf2283d | 5956 | gcc_unreachable (); |
e9ec370e | 5957 | } |
5958 | return buf; | |
5959 | } | |
c8a0e52b | 5960 | |
e9ec370e | 5961 | /* This routine handles long unconditional branches that exceed the |
5962 | maximum range of a simple branch instruction. */ | |
c8a0e52b | 5963 | |
e9ec370e | 5964 | const char * |
5c1d8983 | 5965 | output_lbranch (rtx dest, rtx insn) |
e9ec370e | 5966 | { |
5967 | rtx xoperands[2]; | |
5968 | ||
5969 | xoperands[0] = dest; | |
c8a0e52b | 5970 | |
e9ec370e | 5971 | /* First, free up the delay slot. */ |
5972 | if (dbr_sequence_length () != 0) | |
5973 | { | |
5974 | /* We can't handle a jump in the delay slot. */ | |
ecf2283d | 5975 | gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN); |
c8a0e52b | 5976 | |
e9ec370e | 5977 | final_scan_insn (NEXT_INSN (insn), asm_out_file, |
4bf029b0 | 5978 | optimize, 0, NULL); |
c8a0e52b | 5979 | |
e9ec370e | 5980 | /* Now delete the delay insn. */ |
5981 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
5982 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
5983 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
5984 | } | |
c8a0e52b | 5985 | |
e9ec370e | 5986 | /* Output an insn to save %r1. The runtime documentation doesn't |
5987 | specify whether the "Clean Up" slot in the callers frame can | |
5988 | be clobbered by the callee. It isn't copied by HP's builtin | |
5989 | alloca, so this suggests that it can be clobbered if necessary. | |
5990 | The "Static Link" location is copied by HP builtin alloca, so | |
5991 | we avoid using it. Using the cleanup slot might be a problem | |
5992 | if we have to interoperate with languages that pass cleanup | |
5993 | information. However, it should be possible to handle these | |
5994 | situations with GCC's asm feature. | |
5995 | ||
5996 | The "Current RP" slot is reserved for the called procedure, so | |
5997 | we try to use it when we don't have a frame of our own. It's | |
5998 | rather unlikely that we won't have a frame when we need to emit | |
5999 | a very long branch. | |
6000 | ||
6001 | Really the way to go long term is a register scavenger; goto | |
6002 | the target of the jump and find a register which we can use | |
6003 | as a scratch to hold the value in %r1. Then, we wouldn't have | |
6004 | to free up the delay slot or clobber a slot that may be needed | |
6005 | for other purposes. */ | |
6006 | if (TARGET_64BIT) | |
6007 | { | |
6008 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6009 | /* Use the return pointer slot in the frame marker. */ | |
6010 | output_asm_insn ("std %%r1,-16(%%r30)", xoperands); | |
6011 | else | |
6012 | /* Use the slot at -40 in the frame marker since HP builtin | |
6013 | alloca doesn't copy it. */ | |
6014 | output_asm_insn ("std %%r1,-40(%%r30)", xoperands); | |
6015 | } | |
6016 | else | |
6017 | { | |
6018 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6019 | /* Use the return pointer slot in the frame marker. */ | |
6020 | output_asm_insn ("stw %%r1,-20(%%r30)", xoperands); | |
6021 | else | |
6022 | /* Use the "Clean Up" slot in the frame marker. In GCC, | |
6023 | the only other use of this location is for copying a | |
6024 | floating point double argument from a floating-point | |
6025 | register to two general registers. The copy is done | |
19ee40ed | 6026 | as an "atomic" operation when outputting a call, so it |
e9ec370e | 6027 | won't interfere with our using the location here. */ |
6028 | output_asm_insn ("stw %%r1,-12(%%r30)", xoperands); | |
6029 | } | |
b70ea764 | 6030 | |
2247cc5f | 6031 | if (TARGET_PORTABLE_RUNTIME) |
6032 | { | |
6033 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6034 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
6035 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6036 | } | |
6037 | else if (flag_pic) | |
e9ec370e | 6038 | { |
6039 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
6040 | if (TARGET_SOM || !TARGET_GAS) | |
6041 | { | |
6042 | xoperands[1] = gen_label_rtx (); | |
6043 | output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands); | |
6044 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
6045 | CODE_LABEL_NUMBER (xoperands[1])); | |
6046 | output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands); | |
c8a0e52b | 6047 | } |
e9ec370e | 6048 | else |
6049 | { | |
6050 | output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6051 | output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6052 | } | |
6053 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
6054 | } | |
6055 | else | |
6056 | /* Now output a very long branch to the original target. */ | |
6057 | output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands); | |
c8a0e52b | 6058 | |
e9ec370e | 6059 | /* Now restore the value of %r1 in the delay slot. */ |
6060 | if (TARGET_64BIT) | |
6061 | { | |
6062 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6063 | return "ldd -16(%%r30),%%r1"; | |
6064 | else | |
6065 | return "ldd -40(%%r30),%%r1"; | |
6066 | } | |
6067 | else | |
6068 | { | |
6069 | if (actual_fsize == 0 && !regs_ever_live[2]) | |
6070 | return "ldw -20(%%r30),%%r1"; | |
6071 | else | |
6072 | return "ldw -12(%%r30),%%r1"; | |
5fbd5940 | 6073 | } |
0d986529 | 6074 | } |
6075 | ||
6d36483b | 6076 | /* This routine handles all the branch-on-bit conditional branch sequences we |
0d986529 | 6077 | might need to generate. It handles nullification of delay slots, |
6078 | varying length branches, negated branches and all combinations of the | |
6079 | above. it returns the appropriate output template to emit the branch. */ | |
6080 | ||
611a88e1 | 6081 | const char * |
5c1d8983 | 6082 | output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length, |
6083 | int negated, rtx insn, int which) | |
29a4502c | 6084 | { |
0d986529 | 6085 | static char buf[100]; |
6086 | int useskip = 0; | |
6087 | ||
a361b456 | 6088 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 6089 | asking for a disaster. I do not think this can happen as this pattern |
6d36483b | 6090 | is only used when optimizing; jump optimization should eliminate the |
29a4502c | 6091 | jump. But be prepared just in case. */ |
6d36483b | 6092 | |
ece0fa59 | 6093 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6094 | return "nop"; | |
6d36483b | 6095 | |
5fbd5940 | 6096 | /* If this is a long branch with its delay slot unfilled, set `nullify' |
6097 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6098 | if (length == 8 && dbr_sequence_length () == 0) |
5fbd5940 | 6099 | nullify = 1; |
6100 | ||
6101 | /* If this is a short forward conditional branch which did not get | |
6102 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6103 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
5fbd5940 | 6104 | nullify = forward_branch_p (insn); |
6105 | ||
6d36483b | 6106 | /* A forward branch over a single nullified insn can be done with a |
0d986529 | 6107 | extrs instruction. This avoids a single cycle penalty due to |
6108 | mis-predicted branch if we fall through (branch not taken). */ | |
6109 | ||
5a1231ef | 6110 | if (length == 4 |
5fbd5940 | 6111 | && next_real_insn (insn) != 0 |
5a1231ef | 6112 | && get_attr_length (next_real_insn (insn)) == 4 |
5fbd5940 | 6113 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) |
0d986529 | 6114 | && nullify) |
6115 | useskip = 1; | |
6116 | ||
6117 | switch (length) | |
6118 | { | |
6119 | ||
5fbd5940 | 6120 | /* All short conditional branches except backwards with an unfilled |
6121 | delay slot. */ | |
5a1231ef | 6122 | case 4: |
0d986529 | 6123 | if (useskip) |
e4065f95 | 6124 | strcpy (buf, "{extrs,|extrw,s,}"); |
6d36483b | 6125 | else |
0d986529 | 6126 | strcpy (buf, "bb,"); |
5e3c5739 | 6127 | if (useskip && GET_MODE (operands[0]) == DImode) |
6128 | strcpy (buf, "extrd,s,*"); | |
6129 | else if (GET_MODE (operands[0]) == DImode) | |
6130 | strcpy (buf, "bb,*"); | |
0d986529 | 6131 | if ((which == 0 && negated) |
6132 | || (which == 1 && ! negated)) | |
6133 | strcat (buf, ">="); | |
6134 | else | |
6135 | strcat (buf, "<"); | |
6136 | if (useskip) | |
5a811d43 | 6137 | strcat (buf, " %0,%1,1,%%r0"); |
0d986529 | 6138 | else if (nullify && negated) |
6139 | strcat (buf, ",n %0,%1,%3"); | |
6140 | else if (nullify && ! negated) | |
6141 | strcat (buf, ",n %0,%1,%2"); | |
6142 | else if (! nullify && negated) | |
5fbd5940 | 6143 | strcat (buf, "%0,%1,%3"); |
0d986529 | 6144 | else if (! nullify && ! negated) |
5fbd5940 | 6145 | strcat (buf, " %0,%1,%2"); |
0d986529 | 6146 | break; |
6147 | ||
87fcb603 | 6148 | /* All long conditionals. Note a short backward branch with an |
5fbd5940 | 6149 | unfilled delay slot is treated just like a long backward branch |
6150 | with an unfilled delay slot. */ | |
5a1231ef | 6151 | case 8: |
5fbd5940 | 6152 | /* Handle weird backwards branch with a filled delay slot |
6153 | with is nullified. */ | |
6154 | if (dbr_sequence_length () != 0 | |
6155 | && ! forward_branch_p (insn) | |
6156 | && nullify) | |
6157 | { | |
6158 | strcpy (buf, "bb,"); | |
5e3c5739 | 6159 | if (GET_MODE (operands[0]) == DImode) |
6160 | strcat (buf, "*"); | |
5fbd5940 | 6161 | if ((which == 0 && negated) |
6162 | || (which == 1 && ! negated)) | |
6163 | strcat (buf, "<"); | |
6164 | else | |
6165 | strcat (buf, ">="); | |
6166 | if (negated) | |
5a811d43 | 6167 | strcat (buf, ",n %0,%1,.+12\n\tb %3"); |
5fbd5940 | 6168 | else |
5a811d43 | 6169 | strcat (buf, ",n %0,%1,.+12\n\tb %2"); |
5fbd5940 | 6170 | } |
43f0c1f2 | 6171 | /* Handle short backwards branch with an unfilled delay slot. |
6172 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6173 | taken and untaken branches. */ | |
6174 | else if (dbr_sequence_length () == 0 | |
6175 | && ! forward_branch_p (insn) | |
47fc0706 | 6176 | && INSN_ADDRESSES_SET_P () |
6177 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6178 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6179 | { |
6180 | strcpy (buf, "bb,"); | |
5e3c5739 | 6181 | if (GET_MODE (operands[0]) == DImode) |
6182 | strcat (buf, "*"); | |
43f0c1f2 | 6183 | if ((which == 0 && negated) |
6184 | || (which == 1 && ! negated)) | |
6185 | strcat (buf, ">="); | |
6186 | else | |
6187 | strcat (buf, "<"); | |
6188 | if (negated) | |
6189 | strcat (buf, " %0,%1,%3%#"); | |
6190 | else | |
6191 | strcat (buf, " %0,%1,%2%#"); | |
6192 | } | |
0d986529 | 6193 | else |
5fbd5940 | 6194 | { |
e4065f95 | 6195 | strcpy (buf, "{extrs,|extrw,s,}"); |
5e3c5739 | 6196 | if (GET_MODE (operands[0]) == DImode) |
6197 | strcpy (buf, "extrd,s,*"); | |
5fbd5940 | 6198 | if ((which == 0 && negated) |
6199 | || (which == 1 && ! negated)) | |
6200 | strcat (buf, "<"); | |
6201 | else | |
6202 | strcat (buf, ">="); | |
6203 | if (nullify && negated) | |
c6ae275c | 6204 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %3"); |
5fbd5940 | 6205 | else if (nullify && ! negated) |
c6ae275c | 6206 | strcat (buf, " %0,%1,1,%%r0\n\tb,n %2"); |
5fbd5940 | 6207 | else if (negated) |
5a811d43 | 6208 | strcat (buf, " %0,%1,1,%%r0\n\tb %3"); |
6d36483b | 6209 | else |
5a811d43 | 6210 | strcat (buf, " %0,%1,1,%%r0\n\tb %2"); |
5fbd5940 | 6211 | } |
0d986529 | 6212 | break; |
6213 | ||
6214 | default: | |
ecf2283d | 6215 | gcc_unreachable (); |
5fbd5940 | 6216 | } |
0d986529 | 6217 | return buf; |
6218 | } | |
6219 | ||
c7a4e712 | 6220 | /* This routine handles all the branch-on-variable-bit conditional branch |
6221 | sequences we might need to generate. It handles nullification of delay | |
6222 | slots, varying length branches, negated branches and all combinations | |
6223 | of the above. it returns the appropriate output template to emit the | |
6224 | branch. */ | |
6225 | ||
611a88e1 | 6226 | const char * |
5c1d8983 | 6227 | output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length, |
6228 | int negated, rtx insn, int which) | |
c7a4e712 | 6229 | { |
6230 | static char buf[100]; | |
6231 | int useskip = 0; | |
6232 | ||
a361b456 | 6233 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
c7a4e712 | 6234 | asking for a disaster. I do not think this can happen as this pattern |
6235 | is only used when optimizing; jump optimization should eliminate the | |
6236 | jump. But be prepared just in case. */ | |
6237 | ||
ece0fa59 | 6238 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
6239 | return "nop"; | |
c7a4e712 | 6240 | |
6241 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6242 | as it can nullify the delay slot and save a nop. */ | |
6243 | if (length == 8 && dbr_sequence_length () == 0) | |
6244 | nullify = 1; | |
6245 | ||
6246 | /* If this is a short forward conditional branch which did not get | |
6247 | its delay slot filled, the delay slot can still be nullified. */ | |
6248 | if (! nullify && length == 4 && dbr_sequence_length () == 0) | |
6249 | nullify = forward_branch_p (insn); | |
6250 | ||
6251 | /* A forward branch over a single nullified insn can be done with a | |
6252 | extrs instruction. This avoids a single cycle penalty due to | |
6253 | mis-predicted branch if we fall through (branch not taken). */ | |
6254 | ||
6255 | if (length == 4 | |
6256 | && next_real_insn (insn) != 0 | |
6257 | && get_attr_length (next_real_insn (insn)) == 4 | |
6258 | && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn)) | |
6259 | && nullify) | |
6260 | useskip = 1; | |
6261 | ||
6262 | switch (length) | |
6263 | { | |
6264 | ||
6265 | /* All short conditional branches except backwards with an unfilled | |
6266 | delay slot. */ | |
6267 | case 4: | |
6268 | if (useskip) | |
e4065f95 | 6269 | strcpy (buf, "{vextrs,|extrw,s,}"); |
c7a4e712 | 6270 | else |
e4065f95 | 6271 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6272 | if (useskip && GET_MODE (operands[0]) == DImode) |
e75269fd | 6273 | strcpy (buf, "extrd,s,*"); |
5e3c5739 | 6274 | else if (GET_MODE (operands[0]) == DImode) |
6275 | strcpy (buf, "bb,*"); | |
c7a4e712 | 6276 | if ((which == 0 && negated) |
6277 | || (which == 1 && ! negated)) | |
6278 | strcat (buf, ">="); | |
6279 | else | |
6280 | strcat (buf, "<"); | |
6281 | if (useskip) | |
e4065f95 | 6282 | strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}"); |
c7a4e712 | 6283 | else if (nullify && negated) |
e4065f95 | 6284 | strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}"); |
c7a4e712 | 6285 | else if (nullify && ! negated) |
e4065f95 | 6286 | strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}"); |
c7a4e712 | 6287 | else if (! nullify && negated) |
e4065f95 | 6288 | strcat (buf, "{%0,%3|%0,%%sar,%3}"); |
c7a4e712 | 6289 | else if (! nullify && ! negated) |
e4065f95 | 6290 | strcat (buf, "{ %0,%2| %0,%%sar,%2}"); |
c7a4e712 | 6291 | break; |
6292 | ||
87fcb603 | 6293 | /* All long conditionals. Note a short backward branch with an |
c7a4e712 | 6294 | unfilled delay slot is treated just like a long backward branch |
6295 | with an unfilled delay slot. */ | |
6296 | case 8: | |
6297 | /* Handle weird backwards branch with a filled delay slot | |
6298 | with is nullified. */ | |
6299 | if (dbr_sequence_length () != 0 | |
6300 | && ! forward_branch_p (insn) | |
6301 | && nullify) | |
6302 | { | |
e4065f95 | 6303 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6304 | if (GET_MODE (operands[0]) == DImode) |
6305 | strcat (buf, "*"); | |
c7a4e712 | 6306 | if ((which == 0 && negated) |
6307 | || (which == 1 && ! negated)) | |
6308 | strcat (buf, "<"); | |
6309 | else | |
6310 | strcat (buf, ">="); | |
6311 | if (negated) | |
e4065f95 | 6312 | strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}"); |
c7a4e712 | 6313 | else |
e4065f95 | 6314 | strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}"); |
c7a4e712 | 6315 | } |
6316 | /* Handle short backwards branch with an unfilled delay slot. | |
6317 | Using a bb;nop rather than extrs;bl saves 1 cycle for both | |
6318 | taken and untaken branches. */ | |
6319 | else if (dbr_sequence_length () == 0 | |
6320 | && ! forward_branch_p (insn) | |
47fc0706 | 6321 | && INSN_ADDRESSES_SET_P () |
6322 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6323 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
c7a4e712 | 6324 | { |
e4065f95 | 6325 | strcpy (buf, "{bvb,|bb,}"); |
5e3c5739 | 6326 | if (GET_MODE (operands[0]) == DImode) |
6327 | strcat (buf, "*"); | |
c7a4e712 | 6328 | if ((which == 0 && negated) |
6329 | || (which == 1 && ! negated)) | |
6330 | strcat (buf, ">="); | |
6331 | else | |
6332 | strcat (buf, "<"); | |
6333 | if (negated) | |
e4065f95 | 6334 | strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}"); |
c7a4e712 | 6335 | else |
e4065f95 | 6336 | strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}"); |
c7a4e712 | 6337 | } |
6338 | else | |
6339 | { | |
e4065f95 | 6340 | strcpy (buf, "{vextrs,|extrw,s,}"); |
5e3c5739 | 6341 | if (GET_MODE (operands[0]) == DImode) |
6342 | strcpy (buf, "extrd,s,*"); | |
c7a4e712 | 6343 | if ((which == 0 && negated) |
6344 | || (which == 1 && ! negated)) | |
6345 | strcat (buf, "<"); | |
6346 | else | |
6347 | strcat (buf, ">="); | |
6348 | if (nullify && negated) | |
e4065f95 | 6349 | strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}"); |
c7a4e712 | 6350 | else if (nullify && ! negated) |
e4065f95 | 6351 | strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}"); |
c7a4e712 | 6352 | else if (negated) |
e4065f95 | 6353 | strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}"); |
c7a4e712 | 6354 | else |
e4065f95 | 6355 | strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}"); |
c7a4e712 | 6356 | } |
6357 | break; | |
6358 | ||
6359 | default: | |
ecf2283d | 6360 | gcc_unreachable (); |
c7a4e712 | 6361 | } |
6362 | return buf; | |
6363 | } | |
6364 | ||
29a4502c | 6365 | /* Return the output template for emitting a dbra type insn. |
6366 | ||
6367 | Note it may perform some output operations on its own before | |
6368 | returning the final output string. */ | |
611a88e1 | 6369 | const char * |
5c1d8983 | 6370 | output_dbra (rtx *operands, rtx insn, int which_alternative) |
29a4502c | 6371 | { |
6372 | ||
a361b456 | 6373 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 6374 | asking for a disaster. Be prepared! */ |
6375 | ||
ece0fa59 | 6376 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
29a4502c | 6377 | { |
6378 | if (which_alternative == 0) | |
6379 | return "ldo %1(%0),%0"; | |
6380 | else if (which_alternative == 1) | |
6381 | { | |
ea52c577 | 6382 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands); |
6383 | output_asm_insn ("ldw -16(%%r30),%4", operands); | |
34940871 | 6384 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
e4065f95 | 6385 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6386 | } |
6387 | else | |
6388 | { | |
6389 | output_asm_insn ("ldw %0,%4", operands); | |
6390 | return "ldo %1(%4),%4\n\tstw %4,%0"; | |
6391 | } | |
6392 | } | |
6393 | ||
6394 | if (which_alternative == 0) | |
6395 | { | |
6396 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
6397 | int length = get_attr_length (insn); | |
6398 | ||
6399 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6400 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6401 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 6402 | nullify = 1; |
6403 | ||
6404 | /* If this is a short forward conditional branch which did not get | |
6405 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6406 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 6407 | nullify = forward_branch_p (insn); |
6408 | ||
ecf2283d | 6409 | switch (length) |
29a4502c | 6410 | { |
ecf2283d | 6411 | case 4: |
6412 | if (nullify) | |
6413 | return "addib,%C2,n %1,%0,%3"; | |
6414 | else | |
6415 | return "addib,%C2 %1,%0,%3"; | |
6416 | ||
6417 | case 8: | |
6d36483b | 6418 | /* Handle weird backwards branch with a fulled delay slot |
29a4502c | 6419 | which is nullified. */ |
6420 | if (dbr_sequence_length () != 0 | |
6421 | && ! forward_branch_p (insn) | |
6422 | && nullify) | |
5a811d43 | 6423 | return "addib,%N2,n %1,%0,.+12\n\tb %3"; |
43f0c1f2 | 6424 | /* Handle short backwards branch with an unfilled delay slot. |
6425 | Using a addb;nop rather than addi;bl saves 1 cycle for both | |
6426 | taken and untaken branches. */ | |
6427 | else if (dbr_sequence_length () == 0 | |
6428 | && ! forward_branch_p (insn) | |
47fc0706 | 6429 | && INSN_ADDRESSES_SET_P () |
6430 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6431 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6432 | return "addib,%C2 %1,%0,%3%#"; |
6d36483b | 6433 | |
6434 | /* Handle normal cases. */ | |
29a4502c | 6435 | if (nullify) |
5a811d43 | 6436 | return "addi,%N2 %1,%0,%0\n\tb,n %3"; |
29a4502c | 6437 | else |
5a811d43 | 6438 | return "addi,%N2 %1,%0,%0\n\tb %3"; |
ecf2283d | 6439 | |
6440 | default: | |
6441 | gcc_unreachable (); | |
29a4502c | 6442 | } |
ecf2283d | 6443 | |
29a4502c | 6444 | } |
6445 | /* Deal with gross reload from FP register case. */ | |
6446 | else if (which_alternative == 1) | |
6447 | { | |
6448 | /* Move loop counter from FP register to MEM then into a GR, | |
6449 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 6450 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 6451 | output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4", |
6452 | operands); | |
34940871 | 6453 | output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands); |
5a1231ef | 6454 | if (get_attr_length (insn) == 24) |
e4065f95 | 6455 | return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6456 | else |
e4065f95 | 6457 | return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6458 | } |
6459 | /* Deal with gross reload from memory case. */ | |
6460 | else | |
6461 | { | |
6462 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 6463 | happens in the branch's delay slot. */ |
29a4502c | 6464 | output_asm_insn ("ldw %0,%4", operands); |
5a1231ef | 6465 | if (get_attr_length (insn) == 12) |
29a4502c | 6466 | return "addib,%C2 %1,%4,%3\n\tstw %4,%0"; |
6467 | else | |
5a811d43 | 6468 | return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0"; |
29a4502c | 6469 | } |
6470 | } | |
6471 | ||
6472 | /* Return the output template for emitting a dbra type insn. | |
6473 | ||
6474 | Note it may perform some output operations on its own before | |
6475 | returning the final output string. */ | |
611a88e1 | 6476 | const char * |
5c1d8983 | 6477 | output_movb (rtx *operands, rtx insn, int which_alternative, |
6478 | int reverse_comparison) | |
29a4502c | 6479 | { |
6480 | ||
a361b456 | 6481 | /* A conditional branch to the following instruction (e.g. the delay slot) is |
29a4502c | 6482 | asking for a disaster. Be prepared! */ |
6483 | ||
ece0fa59 | 6484 | if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) |
29a4502c | 6485 | { |
6486 | if (which_alternative == 0) | |
6487 | return "copy %1,%0"; | |
6488 | else if (which_alternative == 1) | |
6489 | { | |
ea52c577 | 6490 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
e4065f95 | 6491 | return "{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6492 | } |
546a40bd | 6493 | else if (which_alternative == 2) |
29a4502c | 6494 | return "stw %1,%0"; |
546a40bd | 6495 | else |
6496 | return "mtsar %r1"; | |
29a4502c | 6497 | } |
6498 | ||
6499 | /* Support the second variant. */ | |
6500 | if (reverse_comparison) | |
6501 | PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2]))); | |
6502 | ||
6503 | if (which_alternative == 0) | |
6504 | { | |
6505 | int nullify = INSN_ANNULLED_BRANCH_P (insn); | |
6506 | int length = get_attr_length (insn); | |
6507 | ||
6508 | /* If this is a long branch with its delay slot unfilled, set `nullify' | |
6509 | as it can nullify the delay slot and save a nop. */ | |
5a1231ef | 6510 | if (length == 8 && dbr_sequence_length () == 0) |
29a4502c | 6511 | nullify = 1; |
6512 | ||
6513 | /* If this is a short forward conditional branch which did not get | |
6514 | its delay slot filled, the delay slot can still be nullified. */ | |
5a1231ef | 6515 | if (! nullify && length == 4 && dbr_sequence_length () == 0) |
29a4502c | 6516 | nullify = forward_branch_p (insn); |
6517 | ||
ecf2283d | 6518 | switch (length) |
29a4502c | 6519 | { |
ecf2283d | 6520 | case 4: |
6521 | if (nullify) | |
6522 | return "movb,%C2,n %1,%0,%3"; | |
6523 | else | |
6524 | return "movb,%C2 %1,%0,%3"; | |
6525 | ||
6526 | case 8: | |
6d36483b | 6527 | /* Handle weird backwards branch with a filled delay slot |
29a4502c | 6528 | which is nullified. */ |
6529 | if (dbr_sequence_length () != 0 | |
6530 | && ! forward_branch_p (insn) | |
6531 | && nullify) | |
5a811d43 | 6532 | return "movb,%N2,n %1,%0,.+12\n\tb %3"; |
6d36483b | 6533 | |
43f0c1f2 | 6534 | /* Handle short backwards branch with an unfilled delay slot. |
6535 | Using a movb;nop rather than or;bl saves 1 cycle for both | |
6536 | taken and untaken branches. */ | |
6537 | else if (dbr_sequence_length () == 0 | |
6538 | && ! forward_branch_p (insn) | |
47fc0706 | 6539 | && INSN_ADDRESSES_SET_P () |
6540 | && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn))) | |
6541 | - INSN_ADDRESSES (INSN_UID (insn)) - 8)) | |
43f0c1f2 | 6542 | return "movb,%C2 %1,%0,%3%#"; |
6d36483b | 6543 | /* Handle normal cases. */ |
29a4502c | 6544 | if (nullify) |
5a811d43 | 6545 | return "or,%N2 %1,%%r0,%0\n\tb,n %3"; |
29a4502c | 6546 | else |
5a811d43 | 6547 | return "or,%N2 %1,%%r0,%0\n\tb %3"; |
ecf2283d | 6548 | |
6549 | default: | |
6550 | gcc_unreachable (); | |
29a4502c | 6551 | } |
29a4502c | 6552 | } |
6553 | /* Deal with gross reload from FP register case. */ | |
6554 | else if (which_alternative == 1) | |
6555 | { | |
6556 | /* Move loop counter from FP register to MEM then into a GR, | |
6557 | increment the GR, store the GR into MEM, and finally reload | |
6d36483b | 6558 | the FP register from MEM from within the branch's delay slot. */ |
ea52c577 | 6559 | output_asm_insn ("stw %1,-16(%%r30)", operands); |
5a1231ef | 6560 | if (get_attr_length (insn) == 12) |
e4065f95 | 6561 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6562 | else |
e4065f95 | 6563 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0"; |
29a4502c | 6564 | } |
6565 | /* Deal with gross reload from memory case. */ | |
546a40bd | 6566 | else if (which_alternative == 2) |
29a4502c | 6567 | { |
6568 | /* Reload loop counter from memory, the store back to memory | |
5aedf60c | 6569 | happens in the branch's delay slot. */ |
5a1231ef | 6570 | if (get_attr_length (insn) == 8) |
e4065f95 | 6571 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0"; |
29a4502c | 6572 | else |
e4065f95 | 6573 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0"; |
29a4502c | 6574 | } |
546a40bd | 6575 | /* Handle SAR as a destination. */ |
6576 | else | |
6577 | { | |
6578 | if (get_attr_length (insn) == 8) | |
e4065f95 | 6579 | return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1"; |
546a40bd | 6580 | else |
be7770ad | 6581 | return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1"; |
546a40bd | 6582 | } |
29a4502c | 6583 | } |
6584 | ||
ece88821 | 6585 | /* Copy any FP arguments in INSN into integer registers. */ |
6586 | static void | |
5c1d8983 | 6587 | copy_fp_args (rtx insn) |
ece88821 | 6588 | { |
6589 | rtx link; | |
6590 | rtx xoperands[2]; | |
29a4502c | 6591 | |
ece88821 | 6592 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
6593 | { | |
6594 | int arg_mode, regno; | |
6595 | rtx use = XEXP (link, 0); | |
3683f840 | 6596 | |
ece88821 | 6597 | if (! (GET_CODE (use) == USE |
6598 | && GET_CODE (XEXP (use, 0)) == REG | |
6599 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
6600 | continue; | |
d6686e21 | 6601 | |
ece88821 | 6602 | arg_mode = GET_MODE (XEXP (use, 0)); |
6603 | regno = REGNO (XEXP (use, 0)); | |
5e3c5739 | 6604 | |
ece88821 | 6605 | /* Is it a floating point register? */ |
6606 | if (regno >= 32 && regno <= 39) | |
6607 | { | |
6608 | /* Copy the FP register into an integer register via memory. */ | |
6609 | if (arg_mode == SFmode) | |
6610 | { | |
6611 | xoperands[0] = XEXP (use, 0); | |
6612 | xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2); | |
6613 | output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands); | |
6614 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
6615 | } | |
6616 | else | |
6617 | { | |
6618 | xoperands[0] = XEXP (use, 0); | |
6619 | xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2); | |
6620 | output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands); | |
6621 | output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands); | |
6622 | output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands); | |
6623 | } | |
6624 | } | |
06ddb6f8 | 6625 | } |
ece88821 | 6626 | } |
6627 | ||
6628 | /* Compute length of the FP argument copy sequence for INSN. */ | |
6629 | static int | |
5c1d8983 | 6630 | length_fp_args (rtx insn) |
ece88821 | 6631 | { |
6632 | int length = 0; | |
6633 | rtx link; | |
06ddb6f8 | 6634 | |
ece88821 | 6635 | for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) |
c7a4e712 | 6636 | { |
ece88821 | 6637 | int arg_mode, regno; |
6638 | rtx use = XEXP (link, 0); | |
6639 | ||
6640 | if (! (GET_CODE (use) == USE | |
6641 | && GET_CODE (XEXP (use, 0)) == REG | |
6642 | && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0))))) | |
6643 | continue; | |
c7a4e712 | 6644 | |
ece88821 | 6645 | arg_mode = GET_MODE (XEXP (use, 0)); |
6646 | regno = REGNO (XEXP (use, 0)); | |
6647 | ||
6648 | /* Is it a floating point register? */ | |
6649 | if (regno >= 32 && regno <= 39) | |
c7a4e712 | 6650 | { |
ece88821 | 6651 | if (arg_mode == SFmode) |
6652 | length += 8; | |
6653 | else | |
6654 | length += 12; | |
c7a4e712 | 6655 | } |
ece88821 | 6656 | } |
c7a4e712 | 6657 | |
ece88821 | 6658 | return length; |
6659 | } | |
b70ea764 | 6660 | |
cd0dfcc5 | 6661 | /* Return the attribute length for the millicode call instruction INSN. |
6662 | The length must match the code generated by output_millicode_call. | |
6663 | We include the delay slot in the returned length as it is better to | |
ece88821 | 6664 | over estimate the length than to under estimate it. */ |
b29897dd | 6665 | |
ece88821 | 6666 | int |
5c1d8983 | 6667 | attr_length_millicode_call (rtx insn) |
ece88821 | 6668 | { |
cd0dfcc5 | 6669 | unsigned long distance = -1; |
8a05c3c2 | 6670 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
ece88821 | 6671 | |
cd0dfcc5 | 6672 | if (INSN_ADDRESSES_SET_P ()) |
6673 | { | |
2247cc5f | 6674 | distance = (total + insn_current_reference_address (insn)); |
6675 | if (distance < total) | |
cd0dfcc5 | 6676 | distance = -1; |
6677 | } | |
ece88821 | 6678 | |
6679 | if (TARGET_64BIT) | |
6680 | { | |
6681 | if (!TARGET_LONG_CALLS && distance < 7600000) | |
cd0dfcc5 | 6682 | return 8; |
ece88821 | 6683 | |
cd0dfcc5 | 6684 | return 20; |
ece88821 | 6685 | } |
6686 | else if (TARGET_PORTABLE_RUNTIME) | |
cd0dfcc5 | 6687 | return 24; |
ece88821 | 6688 | else |
6689 | { | |
6690 | if (!TARGET_LONG_CALLS && distance < 240000) | |
cd0dfcc5 | 6691 | return 8; |
ece88821 | 6692 | |
6693 | if (TARGET_LONG_ABS_CALL && !flag_pic) | |
cd0dfcc5 | 6694 | return 12; |
ece88821 | 6695 | |
cd0dfcc5 | 6696 | return 24; |
ece88821 | 6697 | } |
6698 | } | |
6699 | ||
6700 | /* INSN is a function call. It may have an unconditional jump | |
6701 | in its delay slot. | |
b29897dd | 6702 | |
ece88821 | 6703 | CALL_DEST is the routine we are calling. */ |
b29897dd | 6704 | |
ece88821 | 6705 | const char * |
5c1d8983 | 6706 | output_millicode_call (rtx insn, rtx call_dest) |
ece88821 | 6707 | { |
6708 | int attr_length = get_attr_length (insn); | |
6709 | int seq_length = dbr_sequence_length (); | |
6710 | int distance; | |
6711 | rtx seq_insn; | |
6712 | rtx xoperands[3]; | |
b29897dd | 6713 | |
ece88821 | 6714 | xoperands[0] = call_dest; |
6715 | xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31); | |
6716 | ||
6717 | /* Handle the common case where we are sure that the branch will | |
6718 | reach the beginning of the $CODE$ subspace. The within reach | |
6719 | form of the $$sh_func_adrs call has a length of 28. Because | |
a8b24921 | 6720 | it has an attribute type of multi, it never has a nonzero |
ece88821 | 6721 | sequence length. The length of the $$sh_func_adrs is the same |
6722 | as certain out of reach PIC calls to other routines. */ | |
6723 | if (!TARGET_LONG_CALLS | |
6724 | && ((seq_length == 0 | |
6725 | && (attr_length == 12 | |
6726 | || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI))) | |
6727 | || (seq_length != 0 && attr_length == 8))) | |
6728 | { | |
6729 | output_asm_insn ("{bl|b,l} %0,%2", xoperands); | |
6730 | } | |
6731 | else | |
6732 | { | |
6733 | if (TARGET_64BIT) | |
6734 | { | |
6735 | /* It might seem that one insn could be saved by accessing | |
6736 | the millicode function using the linkage table. However, | |
6737 | this doesn't work in shared libraries and other dynamically | |
6738 | loaded objects. Using a pc-relative sequence also avoids | |
6739 | problems related to the implicit use of the gp register. */ | |
6740 | output_asm_insn ("b,l .+8,%%r1", xoperands); | |
9bd9af5d | 6741 | |
6742 | if (TARGET_GAS) | |
6743 | { | |
6744 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); | |
6745 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
6746 | } | |
6747 | else | |
6748 | { | |
6749 | xoperands[1] = gen_label_rtx (); | |
6750 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
805e22b2 | 6751 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
9bd9af5d | 6752 | CODE_LABEL_NUMBER (xoperands[1])); |
6753 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
6754 | } | |
6755 | ||
ece88821 | 6756 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); |
c7a4e712 | 6757 | } |
c7a4e712 | 6758 | else if (TARGET_PORTABLE_RUNTIME) |
6759 | { | |
ece88821 | 6760 | /* Pure portable runtime doesn't allow be/ble; we also don't |
6761 | have PIC support in the assembler/linker, so this sequence | |
6762 | is needed. */ | |
c7a4e712 | 6763 | |
ece88821 | 6764 | /* Get the address of our target into %r1. */ |
6765 | output_asm_insn ("ldil L'%0,%%r1", xoperands); | |
6766 | output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands); | |
c7a4e712 | 6767 | |
ece88821 | 6768 | /* Get our return address into %r31. */ |
6769 | output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands); | |
6770 | output_asm_insn ("addi 8,%%r31,%%r31", xoperands); | |
c7a4e712 | 6771 | |
ece88821 | 6772 | /* Jump to our target address in %r1. */ |
6773 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 6774 | } |
ece88821 | 6775 | else if (!flag_pic) |
c7a4e712 | 6776 | { |
ece88821 | 6777 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
356267e0 | 6778 | if (TARGET_PA_20) |
ece88821 | 6779 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands); |
356267e0 | 6780 | else |
ece88821 | 6781 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); |
c7a4e712 | 6782 | } |
ece88821 | 6783 | else |
c7a4e712 | 6784 | { |
9bd9af5d | 6785 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
6786 | output_asm_insn ("addi 16,%%r1,%%r31", xoperands); | |
6787 | ||
ece88821 | 6788 | if (TARGET_SOM || !TARGET_GAS) |
6789 | { | |
6790 | /* The HP assembler can generate relocations for the | |
6791 | difference of two symbols. GAS can do this for a | |
6792 | millicode symbol but not an arbitrary external | |
6793 | symbol when generating SOM output. */ | |
6794 | xoperands[1] = gen_label_rtx (); | |
805e22b2 | 6795 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
ece88821 | 6796 | CODE_LABEL_NUMBER (xoperands[1])); |
6797 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
6798 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); | |
6799 | } | |
6800 | else | |
6801 | { | |
ece88821 | 6802 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands); |
6803 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1", | |
6804 | xoperands); | |
6805 | } | |
c7a4e712 | 6806 | |
ece88821 | 6807 | /* Jump to our target address in %r1. */ |
6808 | output_asm_insn ("bv %%r0(%%r1)", xoperands); | |
c7a4e712 | 6809 | } |
c7a4e712 | 6810 | } |
6811 | ||
ece88821 | 6812 | if (seq_length == 0) |
6813 | output_asm_insn ("nop", xoperands); | |
c7a4e712 | 6814 | |
ece88821 | 6815 | /* We are done if there isn't a jump in the delay slot. */ |
6816 | if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
6817 | return ""; | |
c7a4e712 | 6818 | |
ece88821 | 6819 | /* This call has an unconditional jump in its delay slot. */ |
6820 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
c7a4e712 | 6821 | |
ece88821 | 6822 | /* See if the return address can be adjusted. Use the containing |
6823 | sequence insn's address. */ | |
cd0dfcc5 | 6824 | if (INSN_ADDRESSES_SET_P ()) |
c7a4e712 | 6825 | { |
cd0dfcc5 | 6826 | seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); |
6827 | distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
6828 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
6829 | ||
6830 | if (VAL_14_BITS_P (distance)) | |
6831 | { | |
6832 | xoperands[1] = gen_label_rtx (); | |
6833 | output_asm_insn ("ldo %0-%1(%2),%2", xoperands); | |
6834 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
6835 | CODE_LABEL_NUMBER (xoperands[1])); | |
6836 | } | |
6837 | else | |
6838 | /* ??? This branch may not reach its target. */ | |
6839 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 6840 | } |
ece88821 | 6841 | else |
6842 | /* ??? This branch may not reach its target. */ | |
6843 | output_asm_insn ("nop\n\tb,n %0", xoperands); | |
c7a4e712 | 6844 | |
6845 | /* Delete the jump. */ | |
6846 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
6847 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
6848 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
ece88821 | 6849 | |
c7a4e712 | 6850 | return ""; |
6851 | } | |
6852 | ||
cd0dfcc5 | 6853 | /* Return the attribute length of the call instruction INSN. The SIBCALL |
6854 | flag indicates whether INSN is a regular call or a sibling call. The | |
faf3f8c1 | 6855 | length returned must be longer than the code actually generated by |
6856 | output_call. Since branch shortening is done before delay branch | |
6857 | sequencing, there is no way to determine whether or not the delay | |
6858 | slot will be filled during branch shortening. Even when the delay | |
6859 | slot is filled, we may have to add a nop if the delay slot contains | |
6860 | a branch that can't reach its target. Thus, we always have to include | |
6861 | the delay slot in the length estimate. This used to be done in | |
6862 | pa_adjust_insn_length but we do it here now as some sequences always | |
6863 | fill the delay slot and we can save four bytes in the estimate for | |
6864 | these sequences. */ | |
ece88821 | 6865 | |
6866 | int | |
5c1d8983 | 6867 | attr_length_call (rtx insn, int sibcall) |
ece88821 | 6868 | { |
faf3f8c1 | 6869 | int local_call; |
6870 | rtx call_dest; | |
6871 | tree call_decl; | |
6872 | int length = 0; | |
6873 | rtx pat = PATTERN (insn); | |
cd0dfcc5 | 6874 | unsigned long distance = -1; |
ece88821 | 6875 | |
cd0dfcc5 | 6876 | if (INSN_ADDRESSES_SET_P ()) |
6877 | { | |
faf3f8c1 | 6878 | unsigned long total; |
6879 | ||
6880 | total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; | |
2247cc5f | 6881 | distance = (total + insn_current_reference_address (insn)); |
6882 | if (distance < total) | |
cd0dfcc5 | 6883 | distance = -1; |
6884 | } | |
ece88821 | 6885 | |
faf3f8c1 | 6886 | /* Determine if this is a local call. */ |
6887 | if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL) | |
6888 | call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0); | |
ece88821 | 6889 | else |
faf3f8c1 | 6890 | call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0); |
ece88821 | 6891 | |
faf3f8c1 | 6892 | call_decl = SYMBOL_REF_DECL (call_dest); |
6893 | local_call = call_decl && (*targetm.binds_local_p) (call_decl); | |
ece88821 | 6894 | |
faf3f8c1 | 6895 | /* pc-relative branch. */ |
6896 | if (!TARGET_LONG_CALLS | |
6897 | && ((TARGET_PA_20 && !sibcall && distance < 7600000) | |
6898 | || distance < 240000)) | |
6899 | length += 8; | |
ece88821 | 6900 | |
faf3f8c1 | 6901 | /* 64-bit plabel sequence. */ |
6902 | else if (TARGET_64BIT && !local_call) | |
6903 | length += sibcall ? 28 : 24; | |
ece88821 | 6904 | |
faf3f8c1 | 6905 | /* non-pic long absolute branch sequence. */ |
6906 | else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) | |
6907 | length += 12; | |
ece88821 | 6908 | |
faf3f8c1 | 6909 | /* long pc-relative branch sequence. */ |
6910 | else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) | |
6911 | || (TARGET_64BIT && !TARGET_GAS) | |
6912 | || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))) | |
6913 | { | |
6914 | length += 20; | |
ece88821 | 6915 | |
faf3f8c1 | 6916 | if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS) |
6917 | length += 8; | |
6918 | } | |
8a05c3c2 | 6919 | |
faf3f8c1 | 6920 | /* 32-bit plabel sequence. */ |
6921 | else | |
6922 | { | |
6923 | length += 32; | |
ece88821 | 6924 | |
faf3f8c1 | 6925 | if (TARGET_SOM) |
6926 | length += length_fp_args (insn); | |
6927 | ||
6928 | if (flag_pic) | |
6929 | length += 4; | |
ee376abe | 6930 | |
faf3f8c1 | 6931 | if (!TARGET_PA_20) |
6932 | { | |
ece88821 | 6933 | if (!sibcall) |
6934 | length += 8; | |
6935 | ||
faf3f8c1 | 6936 | if (!TARGET_NO_SPACE_REGS) |
6937 | length += 8; | |
ece88821 | 6938 | } |
6939 | } | |
faf3f8c1 | 6940 | |
6941 | return length; | |
ece88821 | 6942 | } |
6943 | ||
6944 | /* INSN is a function call. It may have an unconditional jump | |
c7a4e712 | 6945 | in its delay slot. |
6946 | ||
6947 | CALL_DEST is the routine we are calling. */ | |
6948 | ||
611a88e1 | 6949 | const char * |
5c1d8983 | 6950 | output_call (rtx insn, rtx call_dest, int sibcall) |
c7a4e712 | 6951 | { |
ece88821 | 6952 | int delay_insn_deleted = 0; |
6953 | int delay_slot_filled = 0; | |
b70ea764 | 6954 | int seq_length = dbr_sequence_length (); |
2247cc5f | 6955 | tree call_decl = SYMBOL_REF_DECL (call_dest); |
faf3f8c1 | 6956 | int local_call = call_decl && (*targetm.binds_local_p) (call_decl); |
ece88821 | 6957 | rtx xoperands[2]; |
6958 | ||
6959 | xoperands[0] = call_dest; | |
c7a4e712 | 6960 | |
ece88821 | 6961 | /* Handle the common case where we're sure that the branch will reach |
2247cc5f | 6962 | the beginning of the "$CODE$" subspace. This is the beginning of |
6963 | the current function if we are in a named section. */ | |
cd0dfcc5 | 6964 | if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8) |
d6686e21 | 6965 | { |
5e3c5739 | 6966 | xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2); |
ece88821 | 6967 | output_asm_insn ("{bl|b,l} %0,%1", xoperands); |
06ddb6f8 | 6968 | } |
ece88821 | 6969 | else |
06ddb6f8 | 6970 | { |
2247cc5f | 6971 | if (TARGET_64BIT && !local_call) |
3683f840 | 6972 | { |
ece88821 | 6973 | /* ??? As far as I can tell, the HP linker doesn't support the |
6974 | long pc-relative sequence described in the 64-bit runtime | |
6975 | architecture. So, we use a slightly longer indirect call. */ | |
5f43b4f6 | 6976 | struct deferred_plabel *p = get_plabel (call_dest); |
ece88821 | 6977 | |
6978 | xoperands[0] = p->internal_label; | |
6979 | xoperands[1] = gen_label_rtx (); | |
6980 | ||
6981 | /* If this isn't a sibcall, we put the load of %r27 into the | |
6982 | delay slot. We can't do this in a sibcall as we don't | |
6983 | have a second call-clobbered scratch register available. */ | |
6984 | if (seq_length != 0 | |
6985 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
6986 | && !sibcall) | |
6987 | { | |
6988 | final_scan_insn (NEXT_INSN (insn), asm_out_file, | |
4bf029b0 | 6989 | optimize, 0, NULL); |
ece88821 | 6990 | |
6991 | /* Now delete the delay insn. */ | |
6992 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
6993 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
6994 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
6995 | delay_insn_deleted = 1; | |
6996 | } | |
06ddb6f8 | 6997 | |
ece88821 | 6998 | output_asm_insn ("addil LT'%0,%%r27", xoperands); |
6999 | output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands); | |
7000 | output_asm_insn ("ldd 0(%%r1),%%r1", xoperands); | |
06ddb6f8 | 7001 | |
ece88821 | 7002 | if (sibcall) |
06ddb6f8 | 7003 | { |
ece88821 | 7004 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); |
7005 | output_asm_insn ("ldd 16(%%r1),%%r1", xoperands); | |
7006 | output_asm_insn ("bve (%%r1)", xoperands); | |
7007 | } | |
7008 | else | |
7009 | { | |
7010 | output_asm_insn ("ldd 16(%%r1),%%r2", xoperands); | |
7011 | output_asm_insn ("bve,l (%%r2),%%r2", xoperands); | |
7012 | output_asm_insn ("ldd 24(%%r1),%%r27", xoperands); | |
7013 | delay_slot_filled = 1; | |
06ddb6f8 | 7014 | } |
7015 | } | |
ece88821 | 7016 | else |
e3f53689 | 7017 | { |
ece88821 | 7018 | int indirect_call = 0; |
7019 | ||
7020 | /* Emit a long call. There are several different sequences | |
7021 | of increasing length and complexity. In most cases, | |
7022 | they don't allow an instruction in the delay slot. */ | |
2247cc5f | 7023 | if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
ece88821 | 7024 | && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) |
2247cc5f | 7025 | && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)) |
7026 | && !TARGET_64BIT) | |
ece88821 | 7027 | indirect_call = 1; |
7028 | ||
7029 | if (seq_length != 0 | |
7030 | && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN | |
7031 | && !sibcall | |
7032 | && (!TARGET_PA_20 || indirect_call)) | |
5cc6b2bc | 7033 | { |
ece88821 | 7034 | /* A non-jump insn in the delay slot. By definition we can |
7035 | emit this insn before the call (and in fact before argument | |
7036 | relocating. */ | |
4bf029b0 | 7037 | final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, |
fbf5169c | 7038 | NULL); |
ece88821 | 7039 | |
7040 | /* Now delete the delay insn. */ | |
7041 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7042 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7043 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
7044 | delay_insn_deleted = 1; | |
5cc6b2bc | 7045 | } |
e3f53689 | 7046 | |
2247cc5f | 7047 | if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic) |
5cc6b2bc | 7048 | { |
ece88821 | 7049 | /* This is the best sequence for making long calls in |
7050 | non-pic code. Unfortunately, GNU ld doesn't provide | |
7051 | the stub needed for external calls, and GAS's support | |
2247cc5f | 7052 | for this with the SOM linker is buggy. It is safe |
7053 | to use this for local calls. */ | |
ece88821 | 7054 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
7055 | if (sibcall) | |
7056 | output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands); | |
7057 | else | |
7058 | { | |
7059 | if (TARGET_PA_20) | |
7060 | output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", | |
7061 | xoperands); | |
7062 | else | |
7063 | output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands); | |
c7a4e712 | 7064 | |
ece88821 | 7065 | output_asm_insn ("copy %%r31,%%r2", xoperands); |
7066 | delay_slot_filled = 1; | |
7067 | } | |
7068 | } | |
7069 | else | |
7070 | { | |
2247cc5f | 7071 | if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL) |
7072 | || (TARGET_64BIT && !TARGET_GAS)) | |
b70ea764 | 7073 | { |
ece88821 | 7074 | /* The HP assembler and linker can handle relocations |
7075 | for the difference of two symbols. GAS and the HP | |
7076 | linker can't do this when one of the symbols is | |
7077 | external. */ | |
7078 | xoperands[1] = gen_label_rtx (); | |
7079 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7080 | output_asm_insn ("addil L'%0-%l1,%%r1", xoperands); | |
805e22b2 | 7081 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
b70ea764 | 7082 | CODE_LABEL_NUMBER (xoperands[1])); |
ece88821 | 7083 | output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands); |
7084 | } | |
2247cc5f | 7085 | else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)) |
b70ea764 | 7086 | { |
ece88821 | 7087 | /* GAS currently can't generate the relocations that |
7088 | are needed for the SOM linker under HP-UX using this | |
7089 | sequence. The GNU linker doesn't generate the stubs | |
7090 | that are needed for external calls on TARGET_ELF32 | |
7091 | with this sequence. For now, we have to use a | |
7092 | longer plabel sequence when using GAS. */ | |
7093 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7094 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", | |
b70ea764 | 7095 | xoperands); |
ece88821 | 7096 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", |
b70ea764 | 7097 | xoperands); |
7098 | } | |
5e3c5739 | 7099 | else |
7100 | { | |
ece88821 | 7101 | /* Emit a long plabel-based call sequence. This is |
7102 | essentially an inline implementation of $$dyncall. | |
7103 | We don't actually try to call $$dyncall as this is | |
7104 | as difficult as calling the function itself. */ | |
5f43b4f6 | 7105 | struct deferred_plabel *p = get_plabel (call_dest); |
ece88821 | 7106 | |
7107 | xoperands[0] = p->internal_label; | |
7108 | xoperands[1] = gen_label_rtx (); | |
7109 | ||
7110 | /* Since the call is indirect, FP arguments in registers | |
7111 | need to be copied to the general registers. Then, the | |
7112 | argument relocation stub will copy them back. */ | |
7113 | if (TARGET_SOM) | |
7114 | copy_fp_args (insn); | |
7115 | ||
7116 | if (flag_pic) | |
7117 | { | |
7118 | output_asm_insn ("addil LT'%0,%%r19", xoperands); | |
7119 | output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands); | |
7120 | output_asm_insn ("ldw 0(%%r1),%%r1", xoperands); | |
7121 | } | |
7122 | else | |
7123 | { | |
7124 | output_asm_insn ("addil LR'%0-$global$,%%r27", | |
7125 | xoperands); | |
7126 | output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1", | |
7127 | xoperands); | |
7128 | } | |
06ddb6f8 | 7129 | |
ece88821 | 7130 | output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands); |
7131 | output_asm_insn ("depi 0,31,2,%%r1", xoperands); | |
7132 | output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands); | |
7133 | output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands); | |
c7a4e712 | 7134 | |
ece88821 | 7135 | if (!sibcall && !TARGET_PA_20) |
7136 | { | |
7137 | output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands); | |
ee376abe | 7138 | if (TARGET_NO_SPACE_REGS) |
7139 | output_asm_insn ("addi 8,%%r2,%%r2", xoperands); | |
7140 | else | |
7141 | output_asm_insn ("addi 16,%%r2,%%r2", xoperands); | |
ece88821 | 7142 | } |
7143 | } | |
c7a4e712 | 7144 | |
ece88821 | 7145 | if (TARGET_PA_20) |
5e3c5739 | 7146 | { |
ece88821 | 7147 | if (sibcall) |
7148 | output_asm_insn ("bve (%%r1)", xoperands); | |
7149 | else | |
7150 | { | |
7151 | if (indirect_call) | |
7152 | { | |
7153 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7154 | output_asm_insn ("stw %%r2,-24(%%sp)", xoperands); | |
7155 | delay_slot_filled = 1; | |
7156 | } | |
7157 | else | |
7158 | output_asm_insn ("bve,l (%%r1),%%r2", xoperands); | |
7159 | } | |
5e3c5739 | 7160 | } |
7161 | else | |
7162 | { | |
ee376abe | 7163 | if (!TARGET_NO_SPACE_REGS) |
7164 | output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0", | |
7165 | xoperands); | |
06ddb6f8 | 7166 | |
ece88821 | 7167 | if (sibcall) |
ee376abe | 7168 | { |
7169 | if (TARGET_NO_SPACE_REGS) | |
7170 | output_asm_insn ("be 0(%%sr4,%%r1)", xoperands); | |
7171 | else | |
7172 | output_asm_insn ("be 0(%%sr0,%%r1)", xoperands); | |
7173 | } | |
ece88821 | 7174 | else |
7175 | { | |
ee376abe | 7176 | if (TARGET_NO_SPACE_REGS) |
7177 | output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands); | |
7178 | else | |
7179 | output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands); | |
06ddb6f8 | 7180 | |
ece88821 | 7181 | if (indirect_call) |
7182 | output_asm_insn ("stw %%r31,-24(%%sp)", xoperands); | |
7183 | else | |
7184 | output_asm_insn ("copy %%r31,%%r2", xoperands); | |
7185 | delay_slot_filled = 1; | |
7186 | } | |
7187 | } | |
7188 | } | |
06ddb6f8 | 7189 | } |
d6686e21 | 7190 | } |
6d36483b | 7191 | |
8a05c3c2 | 7192 | if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted)) |
ece88821 | 7193 | output_asm_insn ("nop", xoperands); |
d6686e21 | 7194 | |
ece88821 | 7195 | /* We are done if there isn't a jump in the delay slot. */ |
7196 | if (seq_length == 0 | |
7197 | || delay_insn_deleted | |
7198 | || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN) | |
7199 | return ""; | |
d6686e21 | 7200 | |
ece88821 | 7201 | /* A sibcall should never have a branch in the delay slot. */ |
ecf2283d | 7202 | gcc_assert (!sibcall); |
d6686e21 | 7203 | |
ece88821 | 7204 | /* This call has an unconditional jump in its delay slot. */ |
7205 | xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); | |
d6686e21 | 7206 | |
cd0dfcc5 | 7207 | if (!delay_slot_filled && INSN_ADDRESSES_SET_P ()) |
d6686e21 | 7208 | { |
ece88821 | 7209 | /* See if the return address can be adjusted. Use the containing |
7210 | sequence insn's address. */ | |
7211 | rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); | |
7212 | int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) | |
7213 | - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); | |
7214 | ||
7215 | if (VAL_14_BITS_P (distance)) | |
7216 | { | |
7217 | xoperands[1] = gen_label_rtx (); | |
7218 | output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands); | |
805e22b2 | 7219 | (*targetm.asm_out.internal_label) (asm_out_file, "L", |
7220 | CODE_LABEL_NUMBER (xoperands[1])); | |
ece88821 | 7221 | } |
7222 | else | |
ece88821 | 7223 | output_asm_insn ("nop\n\tb,n %0", xoperands); |
d6686e21 | 7224 | } |
ece88821 | 7225 | else |
ece88821 | 7226 | output_asm_insn ("b,n %0", xoperands); |
d6686e21 | 7227 | |
7228 | /* Delete the jump. */ | |
7229 | PUT_CODE (NEXT_INSN (insn), NOTE); | |
7230 | NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; | |
7231 | NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; | |
ece88821 | 7232 | |
d6686e21 | 7233 | return ""; |
7234 | } | |
7235 | ||
cd0dfcc5 | 7236 | /* Return the attribute length of the indirect call instruction INSN. |
7237 | The length must match the code generated by output_indirect call. | |
7238 | The returned length includes the delay slot. Currently, the delay | |
7239 | slot of an indirect call sequence is not exposed and it is used by | |
7240 | the sequence itself. */ | |
7241 | ||
7242 | int | |
5c1d8983 | 7243 | attr_length_indirect_call (rtx insn) |
cd0dfcc5 | 7244 | { |
7245 | unsigned long distance = -1; | |
8a05c3c2 | 7246 | unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes; |
cd0dfcc5 | 7247 | |
7248 | if (INSN_ADDRESSES_SET_P ()) | |
7249 | { | |
2247cc5f | 7250 | distance = (total + insn_current_reference_address (insn)); |
7251 | if (distance < total) | |
cd0dfcc5 | 7252 | distance = -1; |
7253 | } | |
7254 | ||
7255 | if (TARGET_64BIT) | |
7256 | return 12; | |
7257 | ||
7258 | if (TARGET_FAST_INDIRECT_CALLS | |
7259 | || (!TARGET_PORTABLE_RUNTIME | |
7260 | && ((TARGET_PA_20 && distance < 7600000) || distance < 240000))) | |
7261 | return 8; | |
7262 | ||
7263 | if (flag_pic) | |
7264 | return 24; | |
7265 | ||
7266 | if (TARGET_PORTABLE_RUNTIME) | |
7267 | return 20; | |
7268 | ||
7269 | /* Out of reach, can use ble. */ | |
7270 | return 12; | |
7271 | } | |
7272 | ||
7273 | const char * | |
5c1d8983 | 7274 | output_indirect_call (rtx insn, rtx call_dest) |
cd0dfcc5 | 7275 | { |
7276 | rtx xoperands[1]; | |
7277 | ||
7278 | if (TARGET_64BIT) | |
7279 | { | |
7280 | xoperands[0] = call_dest; | |
7281 | output_asm_insn ("ldd 16(%0),%%r2", xoperands); | |
7282 | output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands); | |
7283 | return ""; | |
7284 | } | |
7285 | ||
7286 | /* First the special case for kernels, level 0 systems, etc. */ | |
7287 | if (TARGET_FAST_INDIRECT_CALLS) | |
7288 | return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2"; | |
7289 | ||
7290 | /* Now the normal case -- we can reach $$dyncall directly or | |
7291 | we're sure that we can get there via a long-branch stub. | |
7292 | ||
7293 | No need to check target flags as the length uniquely identifies | |
7294 | the remaining cases. */ | |
7295 | if (attr_length_indirect_call (insn) == 8) | |
f707acb9 | 7296 | { |
7297 | /* The HP linker substitutes a BLE for millicode calls using | |
7298 | the short PIC PCREL form. Thus, we must use %r31 as the | |
7299 | link register when generating PA 1.x code. */ | |
7300 | if (TARGET_PA_20) | |
7301 | return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31"; | |
7302 | else | |
7303 | return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2"; | |
7304 | } | |
cd0dfcc5 | 7305 | |
7306 | /* Long millicode call, but we are not generating PIC or portable runtime | |
7307 | code. */ | |
7308 | if (attr_length_indirect_call (insn) == 12) | |
7309 | return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2"; | |
7310 | ||
7311 | /* Long millicode call for portable runtime. */ | |
7312 | if (attr_length_indirect_call (insn) == 20) | |
7313 | return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop"; | |
7314 | ||
7315 | /* We need a long PIC call to $$dyncall. */ | |
7316 | xoperands[0] = NULL_RTX; | |
7317 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); | |
7318 | if (TARGET_SOM || !TARGET_GAS) | |
7319 | { | |
7320 | xoperands[0] = gen_label_rtx (); | |
7321 | output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands); | |
7322 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
7323 | CODE_LABEL_NUMBER (xoperands[0])); | |
7324 | output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands); | |
7325 | } | |
7326 | else | |
7327 | { | |
7328 | output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands); | |
7329 | output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1", | |
7330 | xoperands); | |
7331 | } | |
7332 | output_asm_insn ("blr %%r0,%%r2", xoperands); | |
7333 | output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands); | |
7334 | return ""; | |
7335 | } | |
7336 | ||
7337 | /* Return the total length of the save and restore instructions needed for | |
7338 | the data linkage table pointer (i.e., the PIC register) across the call | |
7339 | instruction INSN. No-return calls do not require a save and restore. | |
7340 | In addition, we may be able to avoid the save and restore for calls | |
7341 | within the same translation unit. */ | |
7342 | ||
7343 | int | |
5c1d8983 | 7344 | attr_length_save_restore_dltp (rtx insn) |
cd0dfcc5 | 7345 | { |
7346 | if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) | |
7347 | return 0; | |
7348 | ||
7349 | return 8; | |
7350 | } | |
7351 | ||
d6f01525 | 7352 | /* In HPUX 8.0's shared library scheme, special relocations are needed |
6d36483b | 7353 | for function labels if they might be passed to a function |
d6f01525 | 7354 | in a shared library (because shared libraries don't live in code |
44acf429 | 7355 | space), and special magic is needed to construct their address. */ |
d6f01525 | 7356 | |
7357 | void | |
5c1d8983 | 7358 | hppa_encode_label (rtx sym) |
d6f01525 | 7359 | { |
611a88e1 | 7360 | const char *str = XSTR (sym, 0); |
cccfb31e | 7361 | int len = strlen (str) + 1; |
7362 | char *newstr, *p; | |
d6f01525 | 7363 | |
cccfb31e | 7364 | p = newstr = alloca (len + 1); |
cccfb31e | 7365 | *p++ = '@'; |
7366 | strcpy (p, str); | |
74d80a9a | 7367 | |
ea52c577 | 7368 | XSTR (sym, 0) = ggc_alloc_string (newstr, len); |
d6f01525 | 7369 | } |
6d36483b | 7370 | |
7811991d | 7371 | static void |
5c1d8983 | 7372 | pa_encode_section_info (tree decl, rtx rtl, int first) |
7811991d | 7373 | { |
7374 | if (first && TEXT_SPACE_P (decl)) | |
7375 | { | |
7811991d | 7376 | SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; |
7377 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
2c129d70 | 7378 | hppa_encode_label (XEXP (rtl, 0)); |
7811991d | 7379 | } |
7380 | } | |
7381 | ||
7b4a38a6 | 7382 | /* This is sort of inverse to pa_encode_section_info. */ |
7383 | ||
7384 | static const char * | |
5c1d8983 | 7385 | pa_strip_name_encoding (const char *str) |
7b4a38a6 | 7386 | { |
c0264367 | 7387 | str += (*str == '@'); |
7388 | str += (*str == '*'); | |
7389 | return str; | |
7b4a38a6 | 7390 | } |
7391 | ||
d6f01525 | 7392 | int |
5c1d8983 | 7393 | function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
d6f01525 | 7394 | { |
c1b3411e | 7395 | return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0)); |
d6f01525 | 7396 | } |
f33e3942 | 7397 | |
166bf021 | 7398 | /* Returns 1 if OP is a function label involved in a simple addition |
7399 | with a constant. Used to keep certain patterns from matching | |
7400 | during instruction combination. */ | |
7401 | int | |
5c1d8983 | 7402 | is_function_label_plus_const (rtx op) |
166bf021 | 7403 | { |
7404 | /* Strip off any CONST. */ | |
7405 | if (GET_CODE (op) == CONST) | |
7406 | op = XEXP (op, 0); | |
7407 | ||
7408 | return (GET_CODE (op) == PLUS | |
7409 | && function_label_operand (XEXP (op, 0), Pmode) | |
7410 | && GET_CODE (XEXP (op, 1)) == CONST_INT); | |
7411 | } | |
7412 | ||
f1752b7e | 7413 | /* Output assembly code for a thunk to FUNCTION. */ |
7414 | ||
6988553d | 7415 | static void |
5c1d8983 | 7416 | pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, |
7417 | HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, | |
7418 | tree function) | |
f1752b7e | 7419 | { |
e678758c | 7420 | static unsigned int current_thunk_number; |
2247cc5f | 7421 | int val_14 = VAL_14_BITS_P (delta); |
7422 | int nbytes = 0; | |
f1752b7e | 7423 | char label[16]; |
e678758c | 7424 | rtx xoperands[4]; |
2247cc5f | 7425 | |
e678758c | 7426 | xoperands[0] = XEXP (DECL_RTL (function), 0); |
7427 | xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0); | |
7428 | xoperands[2] = GEN_INT (delta); | |
2247cc5f | 7429 | |
e678758c | 7430 | ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0)); |
7431 | fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n"); | |
2247cc5f | 7432 | |
7433 | /* Output the thunk. We know that the function is in the same | |
7434 | translation unit (i.e., the same space) as the thunk, and that | |
7435 | thunks are output after their method. Thus, we don't need an | |
7436 | external branch to reach the function. With SOM and GAS, | |
7437 | functions and thunks are effectively in different sections. | |
7438 | Thus, we can always use a IA-relative branch and the linker | |
7439 | will add a long branch stub if necessary. | |
7440 | ||
7441 | However, we have to be careful when generating PIC code on the | |
7442 | SOM port to ensure that the sequence does not transfer to an | |
7443 | import stub for the target function as this could clobber the | |
7444 | return value saved at SP-24. This would also apply to the | |
7445 | 32-bit linux port if the multi-space model is implemented. */ | |
7446 | if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
7447 | && !(flag_pic && TREE_PUBLIC (function)) | |
7448 | && (TARGET_GAS || last_address < 262132)) | |
7449 | || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME | |
7450 | && ((targetm.have_named_sections | |
7451 | && DECL_SECTION_NAME (thunk_fndecl) != NULL | |
7452 | /* The GNU 64-bit linker has rather poor stub management. | |
7453 | So, we use a long branch from thunks that aren't in | |
7454 | the same section as the target function. */ | |
7455 | && ((!TARGET_64BIT | |
7456 | && (DECL_SECTION_NAME (thunk_fndecl) | |
7457 | != DECL_SECTION_NAME (function))) | |
7458 | || ((DECL_SECTION_NAME (thunk_fndecl) | |
7459 | == DECL_SECTION_NAME (function)) | |
7460 | && last_address < 262132))) | |
7461 | || (!targetm.have_named_sections && last_address < 262132)))) | |
7462 | { | |
e678758c | 7463 | if (!val_14) |
7464 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
7465 | ||
7466 | output_asm_insn ("b %0", xoperands); | |
7467 | ||
2247cc5f | 7468 | if (val_14) |
7469 | { | |
e678758c | 7470 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 7471 | nbytes += 8; |
7472 | } | |
7473 | else | |
7474 | { | |
e678758c | 7475 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 7476 | nbytes += 12; |
7477 | } | |
7478 | } | |
7479 | else if (TARGET_64BIT) | |
7480 | { | |
7481 | /* We only have one call-clobbered scratch register, so we can't | |
7482 | make use of the delay slot if delta doesn't fit in 14 bits. */ | |
7483 | if (!val_14) | |
e678758c | 7484 | { |
7485 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
7486 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); | |
7487 | } | |
2247cc5f | 7488 | |
e678758c | 7489 | output_asm_insn ("b,l .+8,%%r1", xoperands); |
2247cc5f | 7490 | |
7491 | if (TARGET_GAS) | |
7492 | { | |
e678758c | 7493 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
7494 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); | |
2247cc5f | 7495 | } |
7496 | else | |
7497 | { | |
e678758c | 7498 | xoperands[3] = GEN_INT (val_14 ? 8 : 16); |
7499 | output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands); | |
2247cc5f | 7500 | } |
7501 | ||
7502 | if (val_14) | |
7503 | { | |
e678758c | 7504 | output_asm_insn ("bv %%r0(%%r1)", xoperands); |
7505 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); | |
2247cc5f | 7506 | nbytes += 20; |
7507 | } | |
7508 | else | |
7509 | { | |
e678758c | 7510 | output_asm_insn ("bv,n %%r0(%%r1)", xoperands); |
2247cc5f | 7511 | nbytes += 24; |
7512 | } | |
7513 | } | |
7514 | else if (TARGET_PORTABLE_RUNTIME) | |
7515 | { | |
e678758c | 7516 | output_asm_insn ("ldil L'%0,%%r1", xoperands); |
7517 | output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands); | |
7518 | ||
7519 | if (!val_14) | |
7520 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
7521 | ||
7522 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
2247cc5f | 7523 | |
7524 | if (val_14) | |
7525 | { | |
e678758c | 7526 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 7527 | nbytes += 16; |
7528 | } | |
7529 | else | |
7530 | { | |
e678758c | 7531 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 7532 | nbytes += 20; |
7533 | } | |
7534 | } | |
7535 | else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
7536 | { | |
7537 | /* The function is accessible from outside this module. The only | |
7538 | way to avoid an import stub between the thunk and function is to | |
7539 | call the function directly with an indirect sequence similar to | |
7540 | that used by $$dyncall. This is possible because $$dyncall acts | |
7541 | as the import stub in an indirect call. */ | |
2247cc5f | 7542 | ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number); |
e678758c | 7543 | xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label); |
7544 | output_asm_insn ("addil LT'%3,%%r19", xoperands); | |
7545 | output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands); | |
7546 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
7547 | output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands); | |
7548 | output_asm_insn ("depi 0,31,2,%%r22", xoperands); | |
7549 | output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands); | |
7550 | output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands); | |
7551 | ||
2247cc5f | 7552 | if (!val_14) |
7553 | { | |
e678758c | 7554 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
2247cc5f | 7555 | nbytes += 4; |
7556 | } | |
e678758c | 7557 | |
2247cc5f | 7558 | if (TARGET_PA_20) |
7559 | { | |
e678758c | 7560 | output_asm_insn ("bve (%%r22)", xoperands); |
7561 | nbytes += 36; | |
7562 | } | |
7563 | else if (TARGET_NO_SPACE_REGS) | |
7564 | { | |
7565 | output_asm_insn ("be 0(%%sr4,%%r22)", xoperands); | |
2247cc5f | 7566 | nbytes += 36; |
7567 | } | |
7568 | else | |
f1752b7e | 7569 | { |
e678758c | 7570 | output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands); |
7571 | output_asm_insn ("mtsp %%r21,%%sr0", xoperands); | |
7572 | output_asm_insn ("be 0(%%sr0,%%r22)", xoperands); | |
7573 | nbytes += 44; | |
2247cc5f | 7574 | } |
7575 | ||
7576 | if (val_14) | |
e678758c | 7577 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 7578 | else |
e678758c | 7579 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 7580 | } |
7581 | else if (flag_pic) | |
7582 | { | |
e678758c | 7583 | output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); |
2247cc5f | 7584 | |
7585 | if (TARGET_SOM || !TARGET_GAS) | |
7586 | { | |
e678758c | 7587 | output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands); |
7588 | output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands); | |
2247cc5f | 7589 | } |
7590 | else | |
7591 | { | |
e678758c | 7592 | output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands); |
7593 | output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands); | |
2247cc5f | 7594 | } |
7595 | ||
e678758c | 7596 | if (!val_14) |
7597 | output_asm_insn ("addil L'%2,%%r26", xoperands); | |
7598 | ||
7599 | output_asm_insn ("bv %%r0(%%r22)", xoperands); | |
7600 | ||
2247cc5f | 7601 | if (val_14) |
7602 | { | |
e678758c | 7603 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 7604 | nbytes += 20; |
f1752b7e | 7605 | } |
7606 | else | |
2247cc5f | 7607 | { |
e678758c | 7608 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 7609 | nbytes += 24; |
7610 | } | |
f1752b7e | 7611 | } |
7612 | else | |
7613 | { | |
2247cc5f | 7614 | if (!val_14) |
e678758c | 7615 | output_asm_insn ("addil L'%2,%%r26", xoperands); |
2247cc5f | 7616 | |
e678758c | 7617 | output_asm_insn ("ldil L'%0,%%r22", xoperands); |
7618 | output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands); | |
2247cc5f | 7619 | |
7620 | if (val_14) | |
f1752b7e | 7621 | { |
e678758c | 7622 | output_asm_insn ("ldo %2(%%r26),%%r26", xoperands); |
2247cc5f | 7623 | nbytes += 12; |
f1752b7e | 7624 | } |
7625 | else | |
2247cc5f | 7626 | { |
e678758c | 7627 | output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands); |
2247cc5f | 7628 | nbytes += 16; |
7629 | } | |
f1752b7e | 7630 | } |
2247cc5f | 7631 | |
f1752b7e | 7632 | fprintf (file, "\t.EXIT\n\t.PROCEND\n"); |
2247cc5f | 7633 | |
7634 | if (TARGET_SOM && flag_pic && TREE_PUBLIC (function)) | |
f1752b7e | 7635 | { |
7636 | data_section (); | |
e678758c | 7637 | output_asm_insn (".align 4", xoperands); |
2247cc5f | 7638 | ASM_OUTPUT_LABEL (file, label); |
e678758c | 7639 | output_asm_insn (".word P'%0", xoperands); |
f1752b7e | 7640 | } |
916c9cef | 7641 | else if (TARGET_SOM && TARGET_GAS) |
7642 | forget_section (); | |
2247cc5f | 7643 | |
f1752b7e | 7644 | current_thunk_number++; |
2247cc5f | 7645 | nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1) |
7646 | & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)); | |
7647 | last_address += nbytes; | |
7648 | update_total_code_bytes (nbytes); | |
f1752b7e | 7649 | } |
7650 | ||
805e22b2 | 7651 | /* Only direct calls to static functions are allowed to be sibling (tail) |
7652 | call optimized. | |
7653 | ||
7654 | This restriction is necessary because some linker generated stubs will | |
7655 | store return pointers into rp' in some cases which might clobber a | |
7656 | live value already in rp'. | |
7657 | ||
7658 | In a sibcall the current function and the target function share stack | |
7659 | space. Thus if the path to the current function and the path to the | |
7660 | target function save a value in rp', they save the value into the | |
7661 | same stack slot, which has undesirable consequences. | |
7662 | ||
7663 | Because of the deferred binding nature of shared libraries any function | |
7664 | with external scope could be in a different load module and thus require | |
7665 | rp' to be saved when calling that function. So sibcall optimizations | |
7666 | can only be safe for static function. | |
7667 | ||
7668 | Note that GCC never needs return value relocations, so we don't have to | |
7669 | worry about static calls with return value relocations (which require | |
7670 | saving rp'). | |
7671 | ||
7672 | It is safe to perform a sibcall optimization when the target function | |
7673 | will never return. */ | |
7674 | static bool | |
5c1d8983 | 7675 | pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) |
805e22b2 | 7676 | { |
e11e9ae3 | 7677 | if (TARGET_PORTABLE_RUNTIME) |
7678 | return false; | |
7679 | ||
f62b73b6 | 7680 | /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in |
7681 | single subspace mode and the call is not indirect. As far as I know, | |
7682 | there is no operating system support for the multiple subspace mode. | |
7683 | It might be possible to support indirect calls if we didn't use | |
7684 | $$dyncall (see the indirect sequence generated in output_call). */ | |
7685 | if (TARGET_ELF32) | |
7686 | return (decl != NULL_TREE); | |
7687 | ||
7688 | /* Sibcalls are not ok because the arg pointer register is not a fixed | |
2cecd772 | 7689 | register. This prevents the sibcall optimization from occurring. In |
f62b73b6 | 7690 | addition, there are problems with stub placement using GNU ld. This |
7691 | is because a normal sibcall branch uses a 17-bit relocation while | |
7692 | a regular call branch uses a 22-bit relocation. As a result, more | |
7693 | care needs to be taken in the placement of long-branch stubs. */ | |
7694 | if (TARGET_64BIT) | |
7695 | return false; | |
7696 | ||
e11e9ae3 | 7697 | /* Sibcalls are only ok within a translation unit. */ |
7698 | return (decl && !TREE_PUBLIC (decl)); | |
805e22b2 | 7699 | } |
7700 | ||
37580c80 | 7701 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
7702 | use in fmpyadd instructions. */ | |
4ed6ee50 | 7703 | int |
5c1d8983 | 7704 | fmpyaddoperands (rtx *operands) |
4ed6ee50 | 7705 | { |
201f01e9 | 7706 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 7707 | |
ab449421 | 7708 | /* Must be a floating point mode. */ |
7709 | if (mode != SFmode && mode != DFmode) | |
7710 | return 0; | |
7711 | ||
4ed6ee50 | 7712 | /* All modes must be the same. */ |
201f01e9 | 7713 | if (! (mode == GET_MODE (operands[1]) |
7714 | && mode == GET_MODE (operands[2]) | |
7715 | && mode == GET_MODE (operands[3]) | |
7716 | && mode == GET_MODE (operands[4]) | |
7717 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 7718 | return 0; |
7719 | ||
ab449421 | 7720 | /* All operands must be registers. */ |
7721 | if (! (GET_CODE (operands[1]) == REG | |
7722 | && GET_CODE (operands[2]) == REG | |
7723 | && GET_CODE (operands[3]) == REG | |
7724 | && GET_CODE (operands[4]) == REG | |
7725 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 7726 | return 0; |
7727 | ||
37580c80 | 7728 | /* Only 2 real operands to the addition. One of the input operands must |
7729 | be the same as the output operand. */ | |
4ed6ee50 | 7730 | if (! rtx_equal_p (operands[3], operands[4]) |
7731 | && ! rtx_equal_p (operands[3], operands[5])) | |
7732 | return 0; | |
7733 | ||
33f88b1c | 7734 | /* Inout operand of add cannot conflict with any operands from multiply. */ |
4ed6ee50 | 7735 | if (rtx_equal_p (operands[3], operands[0]) |
7736 | || rtx_equal_p (operands[3], operands[1]) | |
7737 | || rtx_equal_p (operands[3], operands[2])) | |
7738 | return 0; | |
7739 | ||
33f88b1c | 7740 | /* multiply cannot feed into addition operands. */ |
4ed6ee50 | 7741 | if (rtx_equal_p (operands[4], operands[0]) |
7742 | || rtx_equal_p (operands[5], operands[0])) | |
7743 | return 0; | |
7744 | ||
ab449421 | 7745 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
7746 | if (mode == SFmode | |
bac38c40 | 7747 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
7748 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
7749 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
7750 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
7751 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
7752 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 7753 | return 0; |
7754 | ||
4ed6ee50 | 7755 | /* Passed. Operands are suitable for fmpyadd. */ |
7756 | return 1; | |
7757 | } | |
7758 | ||
de419443 | 7759 | #if !defined(USE_COLLECT2) |
7760 | static void | |
5c1d8983 | 7761 | pa_asm_out_constructor (rtx symbol, int priority) |
de419443 | 7762 | { |
7763 | if (!function_label_operand (symbol, VOIDmode)) | |
7764 | hppa_encode_label (symbol); | |
7765 | ||
7766 | #ifdef CTORS_SECTION_ASM_OP | |
7767 | default_ctor_section_asm_out_constructor (symbol, priority); | |
7768 | #else | |
7769 | # ifdef TARGET_ASM_NAMED_SECTION | |
7770 | default_named_section_asm_out_constructor (symbol, priority); | |
7771 | # else | |
7772 | default_stabs_asm_out_constructor (symbol, priority); | |
7773 | # endif | |
7774 | #endif | |
7775 | } | |
7776 | ||
7777 | static void | |
5c1d8983 | 7778 | pa_asm_out_destructor (rtx symbol, int priority) |
de419443 | 7779 | { |
7780 | if (!function_label_operand (symbol, VOIDmode)) | |
7781 | hppa_encode_label (symbol); | |
7782 | ||
7783 | #ifdef DTORS_SECTION_ASM_OP | |
7784 | default_dtor_section_asm_out_destructor (symbol, priority); | |
7785 | #else | |
7786 | # ifdef TARGET_ASM_NAMED_SECTION | |
7787 | default_named_section_asm_out_destructor (symbol, priority); | |
7788 | # else | |
7789 | default_stabs_asm_out_destructor (symbol, priority); | |
7790 | # endif | |
7791 | #endif | |
7792 | } | |
7793 | #endif | |
7794 | ||
ff59d376 | 7795 | /* This function places uninitialized global data in the bss section. |
7796 | The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this | |
7797 | function on the SOM port to prevent uninitialized global data from | |
7798 | being placed in the data section. */ | |
7799 | ||
7800 | void | |
7801 | pa_asm_output_aligned_bss (FILE *stream, | |
7802 | const char *name, | |
7803 | unsigned HOST_WIDE_INT size, | |
7804 | unsigned int align) | |
7805 | { | |
7806 | bss_section (); | |
7807 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); | |
7808 | ||
7809 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
7810 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); | |
7811 | #endif | |
7812 | ||
7813 | #ifdef ASM_OUTPUT_SIZE_DIRECTIVE | |
7814 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
7815 | #endif | |
7816 | ||
7817 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); | |
7818 | ASM_OUTPUT_LABEL (stream, name); | |
7819 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
7820 | } | |
7821 | ||
7822 | /* Both the HP and GNU assemblers under HP-UX provide a .comm directive | |
7823 | that doesn't allow the alignment of global common storage to be directly | |
7824 | specified. The SOM linker aligns common storage based on the rounded | |
7825 | value of the NUM_BYTES parameter in the .comm directive. It's not | |
7826 | possible to use the .align directive as it doesn't affect the alignment | |
7827 | of the label associated with a .comm directive. */ | |
7828 | ||
7829 | void | |
7830 | pa_asm_output_aligned_common (FILE *stream, | |
7831 | const char *name, | |
7832 | unsigned HOST_WIDE_INT size, | |
7833 | unsigned int align) | |
7834 | { | |
33cd7888 | 7835 | unsigned int max_common_align; |
7836 | ||
7837 | max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64); | |
7838 | if (align > max_common_align) | |
7839 | { | |
7840 | warning ("alignment (%u) for %s exceeds maximum alignment " | |
7841 | "for global common data. Using %u", | |
7842 | align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT); | |
7843 | align = max_common_align; | |
7844 | } | |
7845 | ||
ff59d376 | 7846 | bss_section (); |
7847 | ||
7848 | assemble_name (stream, name); | |
7849 | fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n", | |
7850 | MAX (size, align / BITS_PER_UNIT)); | |
7851 | } | |
7852 | ||
7853 | /* We can't use .comm for local common storage as the SOM linker effectively | |
7854 | treats the symbol as universal and uses the same storage for local symbols | |
7855 | with the same name in different object files. The .block directive | |
7856 | reserves an uninitialized block of storage. However, it's not common | |
7857 | storage. Fortunately, GCC never requests common storage with the same | |
7858 | name in any given translation unit. */ | |
7859 | ||
7860 | void | |
7861 | pa_asm_output_aligned_local (FILE *stream, | |
7862 | const char *name, | |
7863 | unsigned HOST_WIDE_INT size, | |
7864 | unsigned int align) | |
7865 | { | |
7866 | bss_section (); | |
7867 | fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT); | |
7868 | ||
7869 | #ifdef LOCAL_ASM_OP | |
7870 | fprintf (stream, "%s", LOCAL_ASM_OP); | |
7871 | assemble_name (stream, name); | |
7872 | fprintf (stream, "\n"); | |
7873 | #endif | |
7874 | ||
7875 | ASM_OUTPUT_LABEL (stream, name); | |
7876 | fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size); | |
7877 | } | |
7878 | ||
37580c80 | 7879 | /* Returns 1 if the 6 operands specified in OPERANDS are suitable for |
7880 | use in fmpysub instructions. */ | |
4ed6ee50 | 7881 | int |
5c1d8983 | 7882 | fmpysuboperands (rtx *operands) |
4ed6ee50 | 7883 | { |
201f01e9 | 7884 | enum machine_mode mode = GET_MODE (operands[0]); |
4ed6ee50 | 7885 | |
ab449421 | 7886 | /* Must be a floating point mode. */ |
7887 | if (mode != SFmode && mode != DFmode) | |
7888 | return 0; | |
7889 | ||
4ed6ee50 | 7890 | /* All modes must be the same. */ |
201f01e9 | 7891 | if (! (mode == GET_MODE (operands[1]) |
7892 | && mode == GET_MODE (operands[2]) | |
7893 | && mode == GET_MODE (operands[3]) | |
7894 | && mode == GET_MODE (operands[4]) | |
7895 | && mode == GET_MODE (operands[5]))) | |
4ed6ee50 | 7896 | return 0; |
7897 | ||
ab449421 | 7898 | /* All operands must be registers. */ |
7899 | if (! (GET_CODE (operands[1]) == REG | |
7900 | && GET_CODE (operands[2]) == REG | |
7901 | && GET_CODE (operands[3]) == REG | |
7902 | && GET_CODE (operands[4]) == REG | |
7903 | && GET_CODE (operands[5]) == REG)) | |
4ed6ee50 | 7904 | return 0; |
7905 | ||
37580c80 | 7906 | /* Only 2 real operands to the subtraction. Subtraction is not a commutative |
7907 | operation, so operands[4] must be the same as operand[3]. */ | |
4ed6ee50 | 7908 | if (! rtx_equal_p (operands[3], operands[4])) |
7909 | return 0; | |
7910 | ||
33f88b1c | 7911 | /* multiply cannot feed into subtraction. */ |
37580c80 | 7912 | if (rtx_equal_p (operands[5], operands[0])) |
4ed6ee50 | 7913 | return 0; |
7914 | ||
33f88b1c | 7915 | /* Inout operand of sub cannot conflict with any operands from multiply. */ |
4ed6ee50 | 7916 | if (rtx_equal_p (operands[3], operands[0]) |
7917 | || rtx_equal_p (operands[3], operands[1]) | |
7918 | || rtx_equal_p (operands[3], operands[2])) | |
7919 | return 0; | |
7920 | ||
ab449421 | 7921 | /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */ |
7922 | if (mode == SFmode | |
bac38c40 | 7923 | && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS |
7924 | || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS | |
7925 | || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS | |
7926 | || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS | |
7927 | || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS | |
7928 | || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS)) | |
ab449421 | 7929 | return 0; |
7930 | ||
4ed6ee50 | 7931 | /* Passed. Operands are suitable for fmpysub. */ |
7932 | return 1; | |
7933 | } | |
7934 | ||
6720f95e | 7935 | /* Return 1 if the given constant is 2, 4, or 8. These are the valid |
7936 | constants for shadd instructions. */ | |
913de4b4 | 7937 | int |
5c1d8983 | 7938 | shadd_constant_p (int val) |
6720f95e | 7939 | { |
7940 | if (val == 2 || val == 4 || val == 8) | |
7941 | return 1; | |
7942 | else | |
7943 | return 0; | |
7944 | } | |
3a16146d | 7945 | |
dbd3d89d | 7946 | /* Return 1 if OP is valid as a base or index register in a |
7947 | REG+REG address. */ | |
42819d4e | 7948 | |
7949 | int | |
dbd3d89d | 7950 | borx_reg_operand (rtx op, enum machine_mode mode) |
42819d4e | 7951 | { |
dbd3d89d | 7952 | if (GET_CODE (op) != REG) |
21f3ee9c | 7953 | return 0; |
7954 | ||
dbd3d89d | 7955 | /* We must reject virtual registers as the only expressions that |
7956 | can be instantiated are REG and REG+CONST. */ | |
7957 | if (op == virtual_incoming_args_rtx | |
7958 | || op == virtual_stack_vars_rtx | |
7959 | || op == virtual_stack_dynamic_rtx | |
7960 | || op == virtual_outgoing_args_rtx | |
7961 | || op == virtual_cfa_rtx) | |
7962 | return 0; | |
42819d4e | 7963 | |
21f3ee9c | 7964 | /* While it's always safe to index off the frame pointer, it's not |
dbd3d89d | 7965 | profitable to do so when the frame pointer is being eliminated. */ |
7966 | if (!reload_completed | |
7967 | && flag_omit_frame_pointer | |
7968 | && !current_function_calls_alloca | |
7969 | && op == frame_pointer_rtx) | |
7970 | return 0; | |
42819d4e | 7971 | |
dbd3d89d | 7972 | return register_operand (op, mode); |
42819d4e | 7973 | } |
7974 | ||
51987f90 | 7975 | /* Return 1 if this operand is anything other than a hard register. */ |
7976 | ||
7977 | int | |
5c1d8983 | 7978 | non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
51987f90 | 7979 | { |
7980 | return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER); | |
7981 | } | |
7982 | ||
5fbd5940 | 7983 | /* Return 1 if INSN branches forward. Should be using insn_addresses |
6dc3b0d9 | 7984 | to avoid walking through all the insns... */ |
7d27e4c9 | 7985 | static int |
5c1d8983 | 7986 | forward_branch_p (rtx insn) |
5fbd5940 | 7987 | { |
7988 | rtx label = JUMP_LABEL (insn); | |
7989 | ||
7990 | while (insn) | |
7991 | { | |
7992 | if (insn == label) | |
7993 | break; | |
7994 | else | |
7995 | insn = NEXT_INSN (insn); | |
7996 | } | |
7997 | ||
7998 | return (insn == label); | |
7999 | } | |
8000 | ||
29a4502c | 8001 | /* Return 1 if OP is an equality comparison, else return 0. */ |
8002 | int | |
5c1d8983 | 8003 | eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
29a4502c | 8004 | { |
8005 | return (GET_CODE (op) == EQ || GET_CODE (op) == NE); | |
8006 | } | |
8007 | ||
d6686e21 | 8008 | /* Return 1 if INSN is in the delay slot of a call instruction. */ |
8009 | int | |
5c1d8983 | 8010 | jump_in_call_delay (rtx insn) |
d6686e21 | 8011 | { |
8012 | ||
8013 | if (GET_CODE (insn) != JUMP_INSN) | |
8014 | return 0; | |
8015 | ||
8016 | if (PREV_INSN (insn) | |
8017 | && PREV_INSN (PREV_INSN (insn)) | |
ece0fa59 | 8018 | && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN) |
d6686e21 | 8019 | { |
ece0fa59 | 8020 | rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn))); |
d6686e21 | 8021 | |
8022 | return (GET_CODE (PATTERN (test_insn)) == SEQUENCE | |
8023 | && XVECEXP (PATTERN (test_insn), 0, 1) == insn); | |
8024 | ||
8025 | } | |
8026 | else | |
8027 | return 0; | |
8028 | } | |
3b1e673e | 8029 | |
546a40bd | 8030 | /* Output an unconditional move and branch insn. */ |
8031 | ||
611a88e1 | 8032 | const char * |
5c1d8983 | 8033 | output_parallel_movb (rtx *operands, int length) |
546a40bd | 8034 | { |
8035 | /* These are the cases in which we win. */ | |
8036 | if (length == 4) | |
8037 | return "mov%I1b,tr %1,%0,%2"; | |
8038 | ||
8039 | /* None of these cases wins, but they don't lose either. */ | |
8040 | if (dbr_sequence_length () == 0) | |
8041 | { | |
8042 | /* Nothing in the delay slot, fake it by putting the combined | |
8043 | insn (the copy or add) in the delay slot of a bl. */ | |
8044 | if (GET_CODE (operands[1]) == CONST_INT) | |
5a811d43 | 8045 | return "b %2\n\tldi %1,%0"; |
546a40bd | 8046 | else |
5a811d43 | 8047 | return "b %2\n\tcopy %1,%0"; |
546a40bd | 8048 | } |
8049 | else | |
8050 | { | |
8051 | /* Something in the delay slot, but we've got a long branch. */ | |
8052 | if (GET_CODE (operands[1]) == CONST_INT) | |
5a811d43 | 8053 | return "ldi %1,%0\n\tb %2"; |
546a40bd | 8054 | else |
5a811d43 | 8055 | return "copy %1,%0\n\tb %2"; |
546a40bd | 8056 | } |
8057 | } | |
8058 | ||
8059 | /* Output an unconditional add and branch insn. */ | |
8060 | ||
611a88e1 | 8061 | const char * |
5c1d8983 | 8062 | output_parallel_addb (rtx *operands, int length) |
546a40bd | 8063 | { |
8064 | /* To make life easy we want operand0 to be the shared input/output | |
8065 | operand and operand1 to be the readonly operand. */ | |
8066 | if (operands[0] == operands[1]) | |
8067 | operands[1] = operands[2]; | |
8068 | ||
8069 | /* These are the cases in which we win. */ | |
8070 | if (length == 4) | |
8071 | return "add%I1b,tr %1,%0,%3"; | |
8072 | ||
8073 | /* None of these cases win, but they don't lose either. */ | |
8074 | if (dbr_sequence_length () == 0) | |
8075 | { | |
8076 | /* Nothing in the delay slot, fake it by putting the combined | |
8077 | insn (the copy or add) in the delay slot of a bl. */ | |
5a811d43 | 8078 | return "b %3\n\tadd%I1 %1,%0,%0"; |
546a40bd | 8079 | } |
8080 | else | |
8081 | { | |
8082 | /* Something in the delay slot, but we've got a long branch. */ | |
5a811d43 | 8083 | return "add%I1 %1,%0,%0\n\tb %3"; |
546a40bd | 8084 | } |
8085 | } | |
8086 | ||
7c5101fc | 8087 | /* Return nonzero if INSN (a jump insn) immediately follows a call |
8088 | to a named function. This is used to avoid filling the delay slot | |
8089 | of the jump since it can usually be eliminated by modifying RP in | |
8090 | the delay slot of the call. */ | |
9840d99d | 8091 | |
7d27e4c9 | 8092 | int |
5c1d8983 | 8093 | following_call (rtx insn) |
546a40bd | 8094 | { |
ed1b0769 | 8095 | if (! TARGET_JUMP_IN_DELAY) |
1b6f11e2 | 8096 | return 0; |
8097 | ||
546a40bd | 8098 | /* Find the previous real insn, skipping NOTEs. */ |
8099 | insn = PREV_INSN (insn); | |
8100 | while (insn && GET_CODE (insn) == NOTE) | |
8101 | insn = PREV_INSN (insn); | |
8102 | ||
8103 | /* Check for CALL_INSNs and millicode calls. */ | |
8104 | if (insn | |
1d2e016c | 8105 | && ((GET_CODE (insn) == CALL_INSN |
8106 | && get_attr_type (insn) != TYPE_DYNCALL) | |
546a40bd | 8107 | || (GET_CODE (insn) == INSN |
8108 | && GET_CODE (PATTERN (insn)) != SEQUENCE | |
8109 | && GET_CODE (PATTERN (insn)) != USE | |
8110 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8111 | && get_attr_type (insn) == TYPE_MILLI))) | |
8112 | return 1; | |
8113 | ||
8114 | return 0; | |
8115 | } | |
8116 | ||
3b1e673e | 8117 | /* We use this hook to perform a PA specific optimization which is difficult |
8118 | to do in earlier passes. | |
8119 | ||
8120 | We want the delay slots of branches within jump tables to be filled. | |
8121 | None of the compiler passes at the moment even has the notion that a | |
8122 | PA jump table doesn't contain addresses, but instead contains actual | |
8123 | instructions! | |
8124 | ||
8125 | Because we actually jump into the table, the addresses of each entry | |
01cc3b75 | 8126 | must stay constant in relation to the beginning of the table (which |
3b1e673e | 8127 | itself must stay constant relative to the instruction to jump into |
8128 | it). I don't believe we can guarantee earlier passes of the compiler | |
8129 | will adhere to those rules. | |
8130 | ||
8131 | So, late in the compilation process we find all the jump tables, and | |
a361b456 | 8132 | expand them into real code -- e.g. each entry in the jump table vector |
3b1e673e | 8133 | will get an appropriate label followed by a jump to the final target. |
8134 | ||
8135 | Reorg and the final jump pass can then optimize these branches and | |
8136 | fill their delay slots. We end up with smaller, more efficient code. | |
8137 | ||
9840d99d | 8138 | The jump instructions within the table are special; we must be able |
3b1e673e | 8139 | to identify them during assembly output (if the jumps don't get filled |
8140 | we need to emit a nop rather than nullifying the delay slot)). We | |
b932f66c | 8141 | identify jumps in switch tables by using insns with the attribute |
8142 | type TYPE_BTABLE_BRANCH. | |
9239127b | 8143 | |
8144 | We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB | |
8145 | insns. This serves two purposes, first it prevents jump.c from | |
8146 | noticing that the last N entries in the table jump to the instruction | |
8147 | immediately after the table and deleting the jumps. Second, those | |
8148 | insns mark where we should emit .begin_brtab and .end_brtab directives | |
8149 | when using GAS (allows for better link time optimizations). */ | |
3b1e673e | 8150 | |
2efea8c0 | 8151 | static void |
5c1d8983 | 8152 | pa_reorg (void) |
3b1e673e | 8153 | { |
8154 | rtx insn; | |
8155 | ||
2efea8c0 | 8156 | remove_useless_addtr_insns (1); |
3d457930 | 8157 | |
342aabd9 | 8158 | if (pa_cpu < PROCESSOR_8000) |
2efea8c0 | 8159 | pa_combine_instructions (); |
342aabd9 | 8160 | |
bd49d362 | 8161 | |
3d457930 | 8162 | /* This is fairly cheap, so always run it if optimizing. */ |
a66555b2 | 8163 | if (optimize > 0 && !TARGET_BIG_SWITCH) |
3b1e673e | 8164 | { |
b41266d4 | 8165 | /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */ |
2efea8c0 | 8166 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
3b1e673e | 8167 | { |
b932f66c | 8168 | rtx pattern, tmp, location, label; |
3b1e673e | 8169 | unsigned int length, i; |
8170 | ||
b41266d4 | 8171 | /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */ |
3b1e673e | 8172 | if (GET_CODE (insn) != JUMP_INSN |
b41266d4 | 8173 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8174 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
3b1e673e | 8175 | continue; |
8176 | ||
9239127b | 8177 | /* Emit marker for the beginning of the branch table. */ |
8178 | emit_insn_before (gen_begin_brtab (), insn); | |
f9333726 | 8179 | |
3b1e673e | 8180 | pattern = PATTERN (insn); |
8181 | location = PREV_INSN (insn); | |
b41266d4 | 8182 | length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC); |
f9333726 | 8183 | |
3b1e673e | 8184 | for (i = 0; i < length; i++) |
8185 | { | |
a66555b2 | 8186 | /* Emit a label before each jump to keep jump.c from |
8187 | removing this code. */ | |
8188 | tmp = gen_label_rtx (); | |
8189 | LABEL_NUSES (tmp) = 1; | |
8190 | emit_label_after (tmp, location); | |
8191 | location = NEXT_INSN (location); | |
8192 | ||
b41266d4 | 8193 | if (GET_CODE (pattern) == ADDR_VEC) |
b932f66c | 8194 | label = XEXP (XVECEXP (pattern, 0, i), 0); |
b41266d4 | 8195 | else |
b932f66c | 8196 | label = XEXP (XVECEXP (pattern, 1, i), 0); |
8197 | ||
8198 | tmp = gen_short_jump (label); | |
8199 | ||
8200 | /* Emit the jump itself. */ | |
8201 | tmp = emit_jump_insn_after (tmp, location); | |
8202 | JUMP_LABEL (tmp) = label; | |
8203 | LABEL_NUSES (label)++; | |
8204 | location = NEXT_INSN (location); | |
3b1e673e | 8205 | |
8206 | /* Emit a BARRIER after the jump. */ | |
3b1e673e | 8207 | emit_barrier_after (location); |
3b1e673e | 8208 | location = NEXT_INSN (location); |
8209 | } | |
f9333726 | 8210 | |
9239127b | 8211 | /* Emit marker for the end of the branch table. */ |
8212 | emit_insn_before (gen_end_brtab (), location); | |
8213 | location = NEXT_INSN (location); | |
8214 | emit_barrier_after (location); | |
a66555b2 | 8215 | |
b41266d4 | 8216 | /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */ |
3b1e673e | 8217 | delete_insn (insn); |
8218 | } | |
8219 | } | |
9239127b | 8220 | else |
f9333726 | 8221 | { |
b932f66c | 8222 | /* Still need brtab marker insns. FIXME: the presence of these |
8223 | markers disables output of the branch table to readonly memory, | |
8224 | and any alignment directives that might be needed. Possibly, | |
8225 | the begin_brtab insn should be output before the label for the | |
7bd28bba | 8226 | table. This doesn't matter at the moment since the tables are |
b932f66c | 8227 | always output in the text section. */ |
2efea8c0 | 8228 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
f9333726 | 8229 | { |
8230 | /* Find an ADDR_VEC insn. */ | |
8231 | if (GET_CODE (insn) != JUMP_INSN | |
b41266d4 | 8232 | || (GET_CODE (PATTERN (insn)) != ADDR_VEC |
8233 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)) | |
f9333726 | 8234 | continue; |
8235 | ||
8236 | /* Now generate markers for the beginning and end of the | |
ad87de1e | 8237 | branch table. */ |
f9333726 | 8238 | emit_insn_before (gen_begin_brtab (), insn); |
8239 | emit_insn_after (gen_end_brtab (), insn); | |
8240 | } | |
8241 | } | |
d3287673 | 8242 | } |
bd49d362 | 8243 | |
8244 | /* The PA has a number of odd instructions which can perform multiple | |
8245 | tasks at once. On first generation PA machines (PA1.0 and PA1.1) | |
8246 | it may be profitable to combine two instructions into one instruction | |
8247 | with two outputs. It's not profitable PA2.0 machines because the | |
8248 | two outputs would take two slots in the reorder buffers. | |
8249 | ||
8250 | This routine finds instructions which can be combined and combines | |
8251 | them. We only support some of the potential combinations, and we | |
8252 | only try common ways to find suitable instructions. | |
8253 | ||
8254 | * addb can add two registers or a register and a small integer | |
8255 | and jump to a nearby (+-8k) location. Normally the jump to the | |
8256 | nearby location is conditional on the result of the add, but by | |
8257 | using the "true" condition we can make the jump unconditional. | |
8258 | Thus addb can perform two independent operations in one insn. | |
8259 | ||
8260 | * movb is similar to addb in that it can perform a reg->reg | |
8261 | or small immediate->reg copy and jump to a nearby (+-8k location). | |
8262 | ||
8263 | * fmpyadd and fmpysub can perform a FP multiply and either an | |
8264 | FP add or FP sub if the operands of the multiply and add/sub are | |
8265 | independent (there are other minor restrictions). Note both | |
8266 | the fmpy and fadd/fsub can in theory move to better spots according | |
8267 | to data dependencies, but for now we require the fmpy stay at a | |
8268 | fixed location. | |
8269 | ||
8270 | * Many of the memory operations can perform pre & post updates | |
8271 | of index registers. GCC's pre/post increment/decrement addressing | |
8272 | is far too simple to take advantage of all the possibilities. This | |
8273 | pass may not be suitable since those insns may not be independent. | |
8274 | ||
8275 | * comclr can compare two ints or an int and a register, nullify | |
8276 | the following instruction and zero some other register. This | |
8277 | is more difficult to use as it's harder to find an insn which | |
8278 | will generate a comclr than finding something like an unconditional | |
8279 | branch. (conditional moves & long branches create comclr insns). | |
8280 | ||
8281 | * Most arithmetic operations can conditionally skip the next | |
8282 | instruction. They can be viewed as "perform this operation | |
8283 | and conditionally jump to this nearby location" (where nearby | |
8284 | is an insns away). These are difficult to use due to the | |
8285 | branch length restrictions. */ | |
8286 | ||
7d27e4c9 | 8287 | static void |
5c1d8983 | 8288 | pa_combine_instructions (void) |
bd49d362 | 8289 | { |
8290 | rtx anchor, new; | |
8291 | ||
8292 | /* This can get expensive since the basic algorithm is on the | |
8293 | order of O(n^2) (or worse). Only do it for -O2 or higher | |
ad87de1e | 8294 | levels of optimization. */ |
bd49d362 | 8295 | if (optimize < 2) |
8296 | return; | |
8297 | ||
8298 | /* Walk down the list of insns looking for "anchor" insns which | |
8299 | may be combined with "floating" insns. As the name implies, | |
8300 | "anchor" instructions don't move, while "floating" insns may | |
8301 | move around. */ | |
ad851752 | 8302 | new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX)); |
bd49d362 | 8303 | new = make_insn_raw (new); |
8304 | ||
8305 | for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor)) | |
8306 | { | |
8307 | enum attr_pa_combine_type anchor_attr; | |
8308 | enum attr_pa_combine_type floater_attr; | |
8309 | ||
8310 | /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs. | |
8311 | Also ignore any special USE insns. */ | |
7d27e4c9 | 8312 | if ((GET_CODE (anchor) != INSN |
bd49d362 | 8313 | && GET_CODE (anchor) != JUMP_INSN |
7d27e4c9 | 8314 | && GET_CODE (anchor) != CALL_INSN) |
bd49d362 | 8315 | || GET_CODE (PATTERN (anchor)) == USE |
8316 | || GET_CODE (PATTERN (anchor)) == CLOBBER | |
8317 | || GET_CODE (PATTERN (anchor)) == ADDR_VEC | |
8318 | || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC) | |
8319 | continue; | |
8320 | ||
8321 | anchor_attr = get_attr_pa_combine_type (anchor); | |
8322 | /* See if anchor is an insn suitable for combination. */ | |
8323 | if (anchor_attr == PA_COMBINE_TYPE_FMPY | |
8324 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8325 | || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
8326 | && ! forward_branch_p (anchor))) | |
8327 | { | |
8328 | rtx floater; | |
8329 | ||
8330 | for (floater = PREV_INSN (anchor); | |
8331 | floater; | |
8332 | floater = PREV_INSN (floater)) | |
8333 | { | |
8334 | if (GET_CODE (floater) == NOTE | |
8335 | || (GET_CODE (floater) == INSN | |
8336 | && (GET_CODE (PATTERN (floater)) == USE | |
8337 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
8338 | continue; | |
8339 | ||
8340 | /* Anything except a regular INSN will stop our search. */ | |
8341 | if (GET_CODE (floater) != INSN | |
8342 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
8343 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
8344 | { | |
8345 | floater = NULL_RTX; | |
8346 | break; | |
8347 | } | |
8348 | ||
8349 | /* See if FLOATER is suitable for combination with the | |
8350 | anchor. */ | |
8351 | floater_attr = get_attr_pa_combine_type (floater); | |
8352 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
8353 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
8354 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8355 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
8356 | { | |
8357 | /* If ANCHOR and FLOATER can be combined, then we're | |
8358 | done with this pass. */ | |
8359 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8360 | SET_DEST (PATTERN (floater)), | |
8361 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
8362 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
8363 | break; | |
8364 | } | |
8365 | ||
8366 | else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH | |
8367 | && floater_attr == PA_COMBINE_TYPE_ADDMOVE) | |
8368 | { | |
8369 | if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS) | |
8370 | { | |
8371 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8372 | SET_DEST (PATTERN (floater)), | |
8373 | XEXP (SET_SRC (PATTERN (floater)), 0), | |
8374 | XEXP (SET_SRC (PATTERN (floater)), 1))) | |
8375 | break; | |
8376 | } | |
8377 | else | |
8378 | { | |
8379 | if (pa_can_combine_p (new, anchor, floater, 0, | |
8380 | SET_DEST (PATTERN (floater)), | |
8381 | SET_SRC (PATTERN (floater)), | |
8382 | SET_SRC (PATTERN (floater)))) | |
8383 | break; | |
8384 | } | |
8385 | } | |
8386 | } | |
8387 | ||
8388 | /* If we didn't find anything on the backwards scan try forwards. */ | |
8389 | if (!floater | |
8390 | && (anchor_attr == PA_COMBINE_TYPE_FMPY | |
8391 | || anchor_attr == PA_COMBINE_TYPE_FADDSUB)) | |
8392 | { | |
8393 | for (floater = anchor; floater; floater = NEXT_INSN (floater)) | |
8394 | { | |
8395 | if (GET_CODE (floater) == NOTE | |
8396 | || (GET_CODE (floater) == INSN | |
8397 | && (GET_CODE (PATTERN (floater)) == USE | |
8398 | || GET_CODE (PATTERN (floater)) == CLOBBER))) | |
9840d99d | 8399 | |
bd49d362 | 8400 | continue; |
8401 | ||
8402 | /* Anything except a regular INSN will stop our search. */ | |
8403 | if (GET_CODE (floater) != INSN | |
8404 | || GET_CODE (PATTERN (floater)) == ADDR_VEC | |
8405 | || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC) | |
8406 | { | |
8407 | floater = NULL_RTX; | |
8408 | break; | |
8409 | } | |
8410 | ||
8411 | /* See if FLOATER is suitable for combination with the | |
8412 | anchor. */ | |
8413 | floater_attr = get_attr_pa_combine_type (floater); | |
8414 | if ((anchor_attr == PA_COMBINE_TYPE_FMPY | |
8415 | && floater_attr == PA_COMBINE_TYPE_FADDSUB) | |
8416 | || (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8417 | && floater_attr == PA_COMBINE_TYPE_FMPY)) | |
8418 | { | |
8419 | /* If ANCHOR and FLOATER can be combined, then we're | |
8420 | done with this pass. */ | |
8421 | if (pa_can_combine_p (new, anchor, floater, 1, | |
8422 | SET_DEST (PATTERN (floater)), | |
ea52c577 | 8423 | XEXP (SET_SRC (PATTERN (floater)), |
8424 | 0), | |
8425 | XEXP (SET_SRC (PATTERN (floater)), | |
8426 | 1))) | |
bd49d362 | 8427 | break; |
8428 | } | |
8429 | } | |
8430 | } | |
8431 | ||
8432 | /* FLOATER will be nonzero if we found a suitable floating | |
8433 | insn for combination with ANCHOR. */ | |
8434 | if (floater | |
8435 | && (anchor_attr == PA_COMBINE_TYPE_FADDSUB | |
8436 | || anchor_attr == PA_COMBINE_TYPE_FMPY)) | |
8437 | { | |
8438 | /* Emit the new instruction and delete the old anchor. */ | |
7014838c | 8439 | emit_insn_before (gen_rtx_PARALLEL |
8440 | (VOIDmode, | |
8441 | gen_rtvec (2, PATTERN (anchor), | |
8442 | PATTERN (floater))), | |
8443 | anchor); | |
8444 | ||
bd49d362 | 8445 | PUT_CODE (anchor, NOTE); |
8446 | NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED; | |
8447 | NOTE_SOURCE_FILE (anchor) = 0; | |
8448 | ||
8449 | /* Emit a special USE insn for FLOATER, then delete | |
8450 | the floating insn. */ | |
ad851752 | 8451 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 8452 | delete_insn (floater); |
8453 | ||
8454 | continue; | |
8455 | } | |
8456 | else if (floater | |
8457 | && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH) | |
8458 | { | |
8459 | rtx temp; | |
8460 | /* Emit the new_jump instruction and delete the old anchor. */ | |
7014838c | 8461 | temp |
8462 | = emit_jump_insn_before (gen_rtx_PARALLEL | |
8463 | (VOIDmode, | |
8464 | gen_rtvec (2, PATTERN (anchor), | |
8465 | PATTERN (floater))), | |
8466 | anchor); | |
8467 | ||
bd49d362 | 8468 | JUMP_LABEL (temp) = JUMP_LABEL (anchor); |
8469 | PUT_CODE (anchor, NOTE); | |
8470 | NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED; | |
8471 | NOTE_SOURCE_FILE (anchor) = 0; | |
8472 | ||
8473 | /* Emit a special USE insn for FLOATER, then delete | |
8474 | the floating insn. */ | |
ad851752 | 8475 | emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater); |
bd49d362 | 8476 | delete_insn (floater); |
8477 | continue; | |
8478 | } | |
8479 | } | |
8480 | } | |
8481 | } | |
8482 | ||
9aadea62 | 8483 | static int |
5c1d8983 | 8484 | pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest, |
8485 | rtx src1, rtx src2) | |
bd49d362 | 8486 | { |
8487 | int insn_code_number; | |
8488 | rtx start, end; | |
8489 | ||
8490 | /* Create a PARALLEL with the patterns of ANCHOR and | |
8491 | FLOATER, try to recognize it, then test constraints | |
8492 | for the resulting pattern. | |
8493 | ||
8494 | If the pattern doesn't match or the constraints | |
8495 | aren't met keep searching for a suitable floater | |
8496 | insn. */ | |
8497 | XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor); | |
8498 | XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater); | |
8499 | INSN_CODE (new) = -1; | |
8500 | insn_code_number = recog_memoized (new); | |
8501 | if (insn_code_number < 0 | |
bf9fd117 | 8502 | || (extract_insn (new), ! constrain_operands (1))) |
bd49d362 | 8503 | return 0; |
8504 | ||
8505 | if (reversed) | |
8506 | { | |
8507 | start = anchor; | |
8508 | end = floater; | |
8509 | } | |
8510 | else | |
8511 | { | |
8512 | start = floater; | |
8513 | end = anchor; | |
8514 | } | |
8515 | ||
8516 | /* There's up to three operands to consider. One | |
8517 | output and two inputs. | |
8518 | ||
8519 | The output must not be used between FLOATER & ANCHOR | |
8520 | exclusive. The inputs must not be set between | |
8521 | FLOATER and ANCHOR exclusive. */ | |
8522 | ||
8523 | if (reg_used_between_p (dest, start, end)) | |
8524 | return 0; | |
8525 | ||
8526 | if (reg_set_between_p (src1, start, end)) | |
8527 | return 0; | |
8528 | ||
8529 | if (reg_set_between_p (src2, start, end)) | |
8530 | return 0; | |
8531 | ||
8532 | /* If we get here, then everything is good. */ | |
8533 | return 1; | |
8534 | } | |
14d18de3 | 8535 | |
a6582a53 | 8536 | /* Return nonzero if references for INSN are delayed. |
14d18de3 | 8537 | |
8538 | Millicode insns are actually function calls with some special | |
8539 | constraints on arguments and register usage. | |
8540 | ||
8541 | Millicode calls always expect their arguments in the integer argument | |
8542 | registers, and always return their result in %r29 (ret1). They | |
2013ddf6 | 8543 | are expected to clobber their arguments, %r1, %r29, and the return |
8544 | pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else. | |
8545 | ||
8546 | This function tells reorg that the references to arguments and | |
8547 | millicode calls do not appear to happen until after the millicode call. | |
8548 | This allows reorg to put insns which set the argument registers into the | |
8549 | delay slot of the millicode call -- thus they act more like traditional | |
8550 | CALL_INSNs. | |
8551 | ||
33f88b1c | 8552 | Note we cannot consider side effects of the insn to be delayed because |
2013ddf6 | 8553 | the branch and link insn will clobber the return pointer. If we happened |
8554 | to use the return pointer in the delay slot of the call, then we lose. | |
14d18de3 | 8555 | |
8556 | get_attr_type will try to recognize the given insn, so make sure to | |
8557 | filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns | |
8558 | in particular. */ | |
8559 | int | |
5c1d8983 | 8560 | insn_refs_are_delayed (rtx insn) |
14d18de3 | 8561 | { |
9840d99d | 8562 | return ((GET_CODE (insn) == INSN |
14d18de3 | 8563 | && GET_CODE (PATTERN (insn)) != SEQUENCE |
8564 | && GET_CODE (PATTERN (insn)) != USE | |
8565 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
8566 | && get_attr_type (insn) == TYPE_MILLI)); | |
8567 | } | |
5cb4669a | 8568 | |
58a72cce | 8569 | /* On the HP-PA the value is found in register(s) 28(-29), unless |
8570 | the mode is SF or DF. Then the value is returned in fr4 (32). | |
8571 | ||
8572 | This must perform the same promotions as PROMOTE_MODE, else | |
b8debbe8 | 8573 | TARGET_PROMOTE_FUNCTION_RETURN will not work correctly. |
58a72cce | 8574 | |
8575 | Small structures must be returned in a PARALLEL on PA64 in order | |
8576 | to match the HP Compiler ABI. */ | |
8577 | ||
8578 | rtx | |
5c1d8983 | 8579 | function_value (tree valtype, tree func ATTRIBUTE_UNUSED) |
58a72cce | 8580 | { |
8581 | enum machine_mode valmode; | |
8582 | ||
8583 | /* Aggregates with a size less than or equal to 128 bits are returned | |
8584 | in GR 28(-29). They are left justified. The pad bits are undefined. | |
8585 | Larger aggregates are returned in memory. */ | |
8586 | if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype)) | |
8587 | { | |
8588 | rtx loc[2]; | |
8589 | int i, offset = 0; | |
8590 | int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2; | |
8591 | ||
8592 | for (i = 0; i < ub; i++) | |
8593 | { | |
8594 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, | |
8595 | gen_rtx_REG (DImode, 28 + i), | |
8596 | GEN_INT (offset)); | |
8597 | offset += 8; | |
8598 | } | |
8599 | ||
8600 | return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc)); | |
8601 | } | |
8602 | ||
8603 | if ((INTEGRAL_TYPE_P (valtype) | |
8604 | && TYPE_PRECISION (valtype) < BITS_PER_WORD) | |
8605 | || POINTER_TYPE_P (valtype)) | |
8606 | valmode = word_mode; | |
8607 | else | |
8608 | valmode = TYPE_MODE (valtype); | |
8609 | ||
8610 | if (TREE_CODE (valtype) == REAL_TYPE | |
8611 | && TYPE_MODE (valtype) != TFmode | |
8612 | && !TARGET_SOFT_FLOAT) | |
8613 | return gen_rtx_REG (valmode, 32); | |
8614 | ||
8615 | return gen_rtx_REG (valmode, 28); | |
8616 | } | |
8617 | ||
5e3c5739 | 8618 | /* Return the location of a parameter that is passed in a register or NULL |
8619 | if the parameter has any component that is passed in memory. | |
8620 | ||
8621 | This is new code and will be pushed to into the net sources after | |
9840d99d | 8622 | further testing. |
5e3c5739 | 8623 | |
8624 | ??? We might want to restructure this so that it looks more like other | |
8625 | ports. */ | |
8626 | rtx | |
5c1d8983 | 8627 | function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, |
8628 | int named ATTRIBUTE_UNUSED) | |
5e3c5739 | 8629 | { |
8630 | int max_arg_words = (TARGET_64BIT ? 8 : 4); | |
2a075f91 | 8631 | int alignment = 0; |
ac965869 | 8632 | int arg_size; |
5e3c5739 | 8633 | int fpr_reg_base; |
8634 | int gpr_reg_base; | |
8635 | rtx retval; | |
8636 | ||
ac965869 | 8637 | if (mode == VOIDmode) |
8638 | return NULL_RTX; | |
8639 | ||
8640 | arg_size = FUNCTION_ARG_SIZE (mode, type); | |
8641 | ||
8642 | /* If this arg would be passed partially or totally on the stack, then | |
f054eb3c | 8643 | this routine should return zero. pa_arg_partial_bytes will |
ac965869 | 8644 | handle arguments which are split between regs and stack slots if |
8645 | the ABI mandates split arguments. */ | |
5e3c5739 | 8646 | if (! TARGET_64BIT) |
8647 | { | |
ac965869 | 8648 | /* The 32-bit ABI does not split arguments. */ |
8649 | if (cum->words + arg_size > max_arg_words) | |
5e3c5739 | 8650 | return NULL_RTX; |
8651 | } | |
8652 | else | |
8653 | { | |
2a075f91 | 8654 | if (arg_size > 1) |
8655 | alignment = cum->words & 1; | |
ac965869 | 8656 | if (cum->words + alignment >= max_arg_words) |
5e3c5739 | 8657 | return NULL_RTX; |
8658 | } | |
8659 | ||
8660 | /* The 32bit ABIs and the 64bit ABIs are rather different, | |
8661 | particularly in their handling of FP registers. We might | |
8662 | be able to cleverly share code between them, but I'm not | |
9aadea62 | 8663 | going to bother in the hope that splitting them up results |
2a075f91 | 8664 | in code that is more easily understood. */ |
5e3c5739 | 8665 | |
5e3c5739 | 8666 | if (TARGET_64BIT) |
8667 | { | |
8668 | /* Advance the base registers to their current locations. | |
8669 | ||
8670 | Remember, gprs grow towards smaller register numbers while | |
2a075f91 | 8671 | fprs grow to higher register numbers. Also remember that |
8672 | although FP regs are 32-bit addressable, we pretend that | |
8673 | the registers are 64-bits wide. */ | |
5e3c5739 | 8674 | gpr_reg_base = 26 - cum->words; |
8675 | fpr_reg_base = 32 + cum->words; | |
9840d99d | 8676 | |
ac965869 | 8677 | /* Arguments wider than one word and small aggregates need special |
8678 | treatment. */ | |
8679 | if (arg_size > 1 | |
8680 | || mode == BLKmode | |
8681 | || (type && AGGREGATE_TYPE_P (type))) | |
5e3c5739 | 8682 | { |
2a075f91 | 8683 | /* Double-extended precision (80-bit), quad-precision (128-bit) |
8684 | and aggregates including complex numbers are aligned on | |
8685 | 128-bit boundaries. The first eight 64-bit argument slots | |
8686 | are associated one-to-one, with general registers r26 | |
8687 | through r19, and also with floating-point registers fr4 | |
8688 | through fr11. Arguments larger than one word are always | |
ac965869 | 8689 | passed in general registers. |
8690 | ||
8691 | Using a PARALLEL with a word mode register results in left | |
8692 | justified data on a big-endian target. */ | |
2a075f91 | 8693 | |
8694 | rtx loc[8]; | |
8695 | int i, offset = 0, ub = arg_size; | |
8696 | ||
8697 | /* Align the base register. */ | |
8698 | gpr_reg_base -= alignment; | |
8699 | ||
8700 | ub = MIN (ub, max_arg_words - cum->words - alignment); | |
8701 | for (i = 0; i < ub; i++) | |
5e3c5739 | 8702 | { |
2a075f91 | 8703 | loc[i] = gen_rtx_EXPR_LIST (VOIDmode, |
8704 | gen_rtx_REG (DImode, gpr_reg_base), | |
8705 | GEN_INT (offset)); | |
8706 | gpr_reg_base -= 1; | |
8707 | offset += 8; | |
5e3c5739 | 8708 | } |
2a075f91 | 8709 | |
8710 | return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc)); | |
5e3c5739 | 8711 | } |
ac965869 | 8712 | } |
5e3c5739 | 8713 | else |
8714 | { | |
8715 | /* If the argument is larger than a word, then we know precisely | |
8716 | which registers we must use. */ | |
2a075f91 | 8717 | if (arg_size > 1) |
5e3c5739 | 8718 | { |
8719 | if (cum->words) | |
8720 | { | |
8721 | gpr_reg_base = 23; | |
8722 | fpr_reg_base = 38; | |
8723 | } | |
8724 | else | |
8725 | { | |
8726 | gpr_reg_base = 25; | |
8727 | fpr_reg_base = 34; | |
8728 | } | |
ac965869 | 8729 | |
8730 | /* Structures 5 to 8 bytes in size are passed in the general | |
8731 | registers in the same manner as other non floating-point | |
8732 | objects. The data is right-justified and zero-extended | |
9f0b40a7 | 8733 | to 64 bits. This is opposite to the normal justification |
8734 | used on big endian targets and requires special treatment. | |
8735 | We now define BLOCK_REG_PADDING to pad these objects. */ | |
ac965869 | 8736 | if (mode == BLKmode) |
8737 | { | |
58a72cce | 8738 | rtx loc = gen_rtx_EXPR_LIST (VOIDmode, |
8739 | gen_rtx_REG (DImode, gpr_reg_base), | |
8740 | const0_rtx); | |
8741 | return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc)); | |
ac965869 | 8742 | } |
5e3c5739 | 8743 | } |
8744 | else | |
8745 | { | |
8746 | /* We have a single word (32 bits). A simple computation | |
8747 | will get us the register #s we need. */ | |
8748 | gpr_reg_base = 26 - cum->words; | |
8749 | fpr_reg_base = 32 + 2 * cum->words; | |
8750 | } | |
8751 | } | |
8752 | ||
9503b0f7 | 8753 | /* Determine if the argument needs to be passed in both general and |
5e3c5739 | 8754 | floating point registers. */ |
9503b0f7 | 8755 | if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32) |
8756 | /* If we are doing soft-float with portable runtime, then there | |
8757 | is no need to worry about FP regs. */ | |
f336e0bc | 8758 | && !TARGET_SOFT_FLOAT |
9503b0f7 | 8759 | /* The parameter must be some kind of float, else we can just |
8760 | pass it in integer registers. */ | |
8761 | && FLOAT_MODE_P (mode) | |
8762 | /* The target function must not have a prototype. */ | |
8763 | && cum->nargs_prototype <= 0 | |
8764 | /* libcalls do not need to pass items in both FP and general | |
8765 | registers. */ | |
8766 | && type != NULL_TREE | |
f336e0bc | 8767 | /* All this hair applies to "outgoing" args only. This includes |
8768 | sibcall arguments setup with FUNCTION_INCOMING_ARG. */ | |
8769 | && !cum->incoming) | |
9503b0f7 | 8770 | /* Also pass outgoing floating arguments in both registers in indirect |
8771 | calls with the 32 bit ABI and the HP assembler since there is no | |
8772 | way to the specify argument locations in static functions. */ | |
f336e0bc | 8773 | || (!TARGET_64BIT |
8774 | && !TARGET_GAS | |
8775 | && !cum->incoming | |
9503b0f7 | 8776 | && cum->indirect |
8777 | && FLOAT_MODE_P (mode))) | |
5e3c5739 | 8778 | { |
8779 | retval | |
8780 | = gen_rtx_PARALLEL | |
8781 | (mode, | |
8782 | gen_rtvec (2, | |
8783 | gen_rtx_EXPR_LIST (VOIDmode, | |
8784 | gen_rtx_REG (mode, fpr_reg_base), | |
8785 | const0_rtx), | |
8786 | gen_rtx_EXPR_LIST (VOIDmode, | |
8787 | gen_rtx_REG (mode, gpr_reg_base), | |
8788 | const0_rtx))); | |
8789 | } | |
8790 | else | |
8791 | { | |
8792 | /* See if we should pass this parameter in a general register. */ | |
8793 | if (TARGET_SOFT_FLOAT | |
8794 | /* Indirect calls in the normal 32bit ABI require all arguments | |
8795 | to be passed in general registers. */ | |
8796 | || (!TARGET_PORTABLE_RUNTIME | |
8797 | && !TARGET_64BIT | |
a052da6f | 8798 | && !TARGET_ELF32 |
5e3c5739 | 8799 | && cum->indirect) |
8800 | /* If the parameter is not a floating point parameter, then | |
8801 | it belongs in GPRs. */ | |
8802 | || !FLOAT_MODE_P (mode)) | |
8803 | retval = gen_rtx_REG (mode, gpr_reg_base); | |
8804 | else | |
8805 | retval = gen_rtx_REG (mode, fpr_reg_base); | |
8806 | } | |
8807 | return retval; | |
8808 | } | |
8809 | ||
8810 | ||
8811 | /* If this arg would be passed totally in registers or totally on the stack, | |
f054eb3c | 8812 | then this routine should return zero. */ |
8813 | ||
8814 | static int | |
8815 | pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
8816 | tree type, bool named ATTRIBUTE_UNUSED) | |
5e3c5739 | 8817 | { |
b7d86581 | 8818 | unsigned int max_arg_words = 8; |
8819 | unsigned int offset = 0; | |
5e3c5739 | 8820 | |
f054eb3c | 8821 | if (!TARGET_64BIT) |
8822 | return 0; | |
8823 | ||
b7d86581 | 8824 | if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1)) |
5e3c5739 | 8825 | offset = 1; |
8826 | ||
b7d86581 | 8827 | if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words) |
6dc3b0d9 | 8828 | /* Arg fits fully into registers. */ |
5e3c5739 | 8829 | return 0; |
9840d99d | 8830 | else if (cum->words + offset >= max_arg_words) |
6dc3b0d9 | 8831 | /* Arg fully on the stack. */ |
5e3c5739 | 8832 | return 0; |
8833 | else | |
6dc3b0d9 | 8834 | /* Arg is split. */ |
f054eb3c | 8835 | return (max_arg_words - cum->words - offset) * UNITS_PER_WORD; |
5e3c5739 | 8836 | } |
8837 | ||
8838 | ||
99c11254 | 8839 | /* Return a string to output before text in the current function. |
916c9cef | 8840 | |
8841 | This function is only used with SOM. Because we don't support | |
8842 | named subspaces, we can only create a new subspace or switch back | |
99c11254 | 8843 | to the default text subspace. */ |
916c9cef | 8844 | const char * |
8845 | som_text_section_asm_op (void) | |
8846 | { | |
99c11254 | 8847 | if (!TARGET_SOM) |
8848 | return ""; | |
8849 | ||
8850 | if (TARGET_GAS) | |
916c9cef | 8851 | { |
8852 | if (cfun && !cfun->machine->in_nsubspa) | |
8853 | { | |
8854 | /* We only want to emit a .nsubspa directive once at the | |
8855 | start of the function. */ | |
8856 | cfun->machine->in_nsubspa = 1; | |
8857 | ||
8858 | /* Create a new subspace for the text. This provides | |
8859 | better stub placement and one-only functions. */ | |
8860 | if (cfun->decl | |
8861 | && DECL_ONE_ONLY (cfun->decl) | |
8862 | && !DECL_WEAK (cfun->decl)) | |
99c11254 | 8863 | return |
8864 | "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT"; | |
916c9cef | 8865 | |
99c11254 | 8866 | return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$"; |
916c9cef | 8867 | } |
8868 | else | |
8869 | { | |
8870 | /* There isn't a current function or the body of the current | |
8871 | function has been completed. So, we are changing to the | |
8872 | text section to output debugging information. Do this in | |
8873 | the default text section. We need to forget that we are | |
99c11254 | 8874 | in the text section so that the function text_section in |
8875 | varasm.c will call us the next time around. */ | |
916c9cef | 8876 | forget_section (); |
8877 | } | |
8878 | } | |
8879 | ||
99c11254 | 8880 | return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$"; |
916c9cef | 8881 | } |
8882 | ||
52470889 | 8883 | /* On hpux10, the linker will give an error if we have a reference |
8884 | in the read-only data section to a symbol defined in a shared | |
8885 | library. Therefore, expressions that might require a reloc can | |
8886 | not be placed in the read-only data section. */ | |
8887 | ||
8888 | static void | |
b572d1a5 | 8889 | pa_select_section (tree exp, int reloc, |
8890 | unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) | |
52470889 | 8891 | { |
8892 | if (TREE_CODE (exp) == VAR_DECL | |
8893 | && TREE_READONLY (exp) | |
8894 | && !TREE_THIS_VOLATILE (exp) | |
8895 | && DECL_INITIAL (exp) | |
8896 | && (DECL_INITIAL (exp) == error_mark_node | |
8897 | || TREE_CONSTANT (DECL_INITIAL (exp))) | |
8898 | && !reloc) | |
916c9cef | 8899 | { |
8900 | if (TARGET_SOM | |
8901 | && DECL_ONE_ONLY (exp) | |
8902 | && !DECL_WEAK (exp)) | |
99c11254 | 8903 | som_one_only_readonly_data_section (); |
916c9cef | 8904 | else |
8905 | readonly_data_section (); | |
8906 | } | |
ce45a448 | 8907 | else if (CONSTANT_CLASS_P (exp) && !reloc) |
52470889 | 8908 | readonly_data_section (); |
916c9cef | 8909 | else if (TARGET_SOM |
8910 | && TREE_CODE (exp) == VAR_DECL | |
8911 | && DECL_ONE_ONLY (exp) | |
2455c36b | 8912 | && !DECL_WEAK (exp)) |
99c11254 | 8913 | som_one_only_data_section (); |
52470889 | 8914 | else |
8915 | data_section (); | |
8916 | } | |
1f3233d1 | 8917 | |
67c1e638 | 8918 | static void |
5c1d8983 | 8919 | pa_globalize_label (FILE *stream, const char *name) |
67c1e638 | 8920 | { |
8921 | /* We only handle DATA objects here, functions are globalized in | |
8922 | ASM_DECLARE_FUNCTION_NAME. */ | |
8923 | if (! FUNCTION_NAME_P (name)) | |
8924 | { | |
8925 | fputs ("\t.EXPORT ", stream); | |
8926 | assemble_name (stream, name); | |
8927 | fputs (",DATA\n", stream); | |
8928 | } | |
8929 | } | |
b8debbe8 | 8930 | |
6644435d | 8931 | /* Worker function for TARGET_STRUCT_VALUE_RTX. */ |
8932 | ||
b8debbe8 | 8933 | static rtx |
8934 | pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
8935 | int incoming ATTRIBUTE_UNUSED) | |
8936 | { | |
8937 | return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM); | |
8938 | } | |
8939 | ||
6644435d | 8940 | /* Worker function for TARGET_RETURN_IN_MEMORY. */ |
8941 | ||
b8debbe8 | 8942 | bool |
8943 | pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) | |
8944 | { | |
8945 | /* SOM ABI says that objects larger than 64 bits are returned in memory. | |
8946 | PA64 ABI says that objects larger than 128 bits are returned in memory. | |
8947 | Note, int_size_in_bytes can return -1 if the size of the object is | |
8948 | variable or larger than the maximum value that can be expressed as | |
8949 | a HOST_WIDE_INT. It can also return zero for an empty type. The | |
8950 | simplest way to handle variable and empty types is to pass them in | |
8951 | memory. This avoids problems in defining the boundaries of argument | |
8952 | slots, allocating registers, etc. */ | |
8953 | return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8) | |
8954 | || int_size_in_bytes (type) <= 0); | |
8955 | } | |
8956 | ||
5f43b4f6 | 8957 | /* Structure to hold declaration and name of external symbols that are |
8958 | emitted by GCC. We generate a vector of these symbols and output them | |
8959 | at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true. | |
8960 | This avoids putting out names that are never really used. */ | |
8961 | ||
046bfc77 | 8962 | typedef struct extern_symbol GTY(()) |
5f43b4f6 | 8963 | { |
8964 | tree decl; | |
8965 | const char *name; | |
046bfc77 | 8966 | } extern_symbol; |
5f43b4f6 | 8967 | |
8968 | /* Define gc'd vector type for extern_symbol. */ | |
046bfc77 | 8969 | DEF_VEC_O(extern_symbol); |
8970 | DEF_VEC_ALLOC_O(extern_symbol,gc); | |
5f43b4f6 | 8971 | |
8972 | /* Vector of extern_symbol pointers. */ | |
046bfc77 | 8973 | static GTY(()) VEC(extern_symbol,gc) *extern_symbols; |
5f43b4f6 | 8974 | |
8975 | #ifdef ASM_OUTPUT_EXTERNAL_REAL | |
8976 | /* Mark DECL (name NAME) as an external reference (assembler output | |
8977 | file FILE). This saves the names to output at the end of the file | |
8978 | if actually referenced. */ | |
8979 | ||
8980 | void | |
8981 | pa_hpux_asm_output_external (FILE *file, tree decl, const char *name) | |
8982 | { | |
046bfc77 | 8983 | extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL); |
5f43b4f6 | 8984 | |
8985 | gcc_assert (file == asm_out_file); | |
8986 | p->decl = decl; | |
8987 | p->name = name; | |
5f43b4f6 | 8988 | } |
8989 | ||
8990 | /* Output text required at the end of an assembler file. | |
8991 | This includes deferred plabels and .import directives for | |
8992 | all external symbols that were actually referenced. */ | |
8993 | ||
8994 | static void | |
8995 | pa_hpux_file_end (void) | |
8996 | { | |
8997 | unsigned int i; | |
046bfc77 | 8998 | extern_symbol *p; |
5f43b4f6 | 8999 | |
9000 | output_deferred_plabels (); | |
9001 | ||
9002 | for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++) | |
9003 | { | |
9004 | tree decl = p->decl; | |
9005 | ||
9006 | if (!TREE_ASM_WRITTEN (decl) | |
9007 | && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0))) | |
9008 | ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name); | |
9009 | } | |
9010 | ||
046bfc77 | 9011 | VEC_free (extern_symbol, gc, extern_symbols); |
5f43b4f6 | 9012 | } |
9013 | #endif | |
9014 | ||
1f3233d1 | 9015 | #include "gt-pa.h" |