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09cae750 | 1 | ;; Predicate description for RISC-V target. |
83ffe9cd | 2 | ;; Copyright (C) 2011-2023 Free Software Foundation, Inc. |
09cae750 PD |
3 | ;; Contributed by Andrew Waterman (andrew@sifive.com). |
4 | ;; Based on MIPS target for GNU compiler. | |
5 | ;; | |
6 | ;; This file is part of GCC. | |
7 | ;; | |
8 | ;; GCC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 3, or (at your option) | |
11 | ;; any later version. | |
12 | ;; | |
13 | ;; GCC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ;; | |
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GCC; see the file COPYING3. If not see | |
20 | ;; <http://www.gnu.org/licenses/>. | |
21 | ||
22 | (define_predicate "const_arith_operand" | |
23 | (and (match_code "const_int") | |
24 | (match_test "SMALL_OPERAND (INTVAL (op))"))) | |
25 | ||
26 | (define_predicate "arith_operand" | |
27 | (ior (match_operand 0 "const_arith_operand") | |
28 | (match_operand 0 "register_operand"))) | |
29 | ||
4f475391 AW |
30 | (define_predicate "lui_operand" |
31 | (and (match_code "const_int") | |
32 | (match_test "LUI_OPERAND (INTVAL (op))"))) | |
33 | ||
34 | (define_predicate "sfb_alu_operand" | |
35 | (ior (match_operand 0 "arith_operand") | |
36 | (match_operand 0 "lui_operand"))) | |
37 | ||
09cae750 PD |
38 | (define_predicate "const_csr_operand" |
39 | (and (match_code "const_int") | |
40 | (match_test "IN_RANGE (INTVAL (op), 0, 31)"))) | |
41 | ||
42 | (define_predicate "csr_operand" | |
43 | (ior (match_operand 0 "const_csr_operand") | |
44 | (match_operand 0 "register_operand"))) | |
45 | ||
46 | (define_predicate "sle_operand" | |
47 | (and (match_code "const_int") | |
48 | (match_test "SMALL_OPERAND (INTVAL (op) + 1)"))) | |
49 | ||
50 | (define_predicate "sleu_operand" | |
51 | (and (match_operand 0 "sle_operand") | |
52 | (match_test "INTVAL (op) + 1 != 0"))) | |
53 | ||
54 | (define_predicate "const_0_operand" | |
ef85d150 | 55 | (and (match_code "const_int,const_wide_int,const_vector") |
09cae750 PD |
56 | (match_test "op == CONST0_RTX (GET_MODE (op))"))) |
57 | ||
58 | (define_predicate "reg_or_0_operand" | |
59 | (ior (match_operand 0 "const_0_operand") | |
60 | (match_operand 0 "register_operand"))) | |
61 | ||
62 | ;; Only use branch-on-bit sequences when the mask is not an ANDI immediate. | |
63 | (define_predicate "branch_on_bit_operand" | |
64 | (and (match_code "const_int") | |
65 | (match_test "INTVAL (op) >= IMM_BITS - 1"))) | |
66 | ||
67 | ;; A legitimate CONST_INT operand that takes more than one instruction | |
68 | ;; to load. | |
69 | (define_predicate "splittable_const_int_operand" | |
70 | (match_code "const_int") | |
71 | { | |
72 | /* Don't handle multi-word moves this way; we don't want to introduce | |
73 | the individual word-mode moves until after reload. */ | |
3496ca4e | 74 | if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD) |
09cae750 PD |
75 | return false; |
76 | ||
4e1e0d79 JW |
77 | /* Check whether the constant can be loaded in a single |
78 | instruction with zbs extensions. */ | |
ffe4f55a | 79 | if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (INTVAL (op))) |
4e1e0d79 JW |
80 | return false; |
81 | ||
09cae750 PD |
82 | /* Otherwise check whether the constant can be loaded in a single |
83 | instruction. */ | |
84 | return !LUI_OPERAND (INTVAL (op)) && !SMALL_OPERAND (INTVAL (op)); | |
85 | }) | |
86 | ||
666fdc46 JW |
87 | (define_predicate "p2m1_shift_operand" |
88 | (match_code "const_int") | |
89 | { | |
90 | int val = exact_log2 (INTVAL (op) + 1); | |
91 | if (val < 12) | |
92 | return false; | |
93 | return true; | |
94 | }) | |
95 | ||
96 | (define_predicate "high_mask_shift_operand" | |
97 | (match_code "const_int") | |
98 | { | |
99 | int val1 = clz_hwi (~ INTVAL (op)); | |
100 | int val0 = ctz_hwi (INTVAL (op)); | |
101 | if ((val0 + val1 == BITS_PER_WORD) | |
102 | && val0 > 31 && val0 < 64) | |
103 | return true; | |
104 | return false; | |
105 | }) | |
106 | ||
09cae750 PD |
107 | (define_predicate "move_operand" |
108 | (match_operand 0 "general_operand") | |
109 | { | |
110 | enum riscv_symbol_type symbol_type; | |
111 | ||
112 | /* The thinking here is as follows: | |
113 | ||
114 | (1) The move expanders should split complex load sequences into | |
115 | individual instructions. Those individual instructions can | |
116 | then be optimized by all rtl passes. | |
117 | ||
118 | (2) The target of pre-reload load sequences should not be used | |
119 | to store temporary results. If the target register is only | |
120 | assigned one value, reload can rematerialize that value | |
121 | on demand, rather than spill it to the stack. | |
122 | ||
123 | (3) If we allowed pre-reload passes like combine and cse to recreate | |
124 | complex load sequences, we would want to be able to split the | |
125 | sequences before reload as well, so that the pre-reload scheduler | |
126 | can see the individual instructions. This falls foul of (2); | |
127 | the splitter would be forced to reuse the target register for | |
128 | intermediate results. | |
129 | ||
130 | (4) We want to define complex load splitters for combine. These | |
131 | splitters can request a temporary scratch register, which avoids | |
132 | the problem in (2). They allow things like: | |
133 | ||
134 | (set (reg T1) (high SYM)) | |
135 | (set (reg T2) (low (reg T1) SYM)) | |
136 | (set (reg X) (plus (reg T2) (const_int OFFSET))) | |
137 | ||
138 | to be combined into: | |
139 | ||
140 | (set (reg T3) (high SYM+OFFSET)) | |
141 | (set (reg X) (lo_sum (reg T3) SYM+OFFSET)) | |
142 | ||
143 | if T2 is only used this once. */ | |
144 | switch (GET_CODE (op)) | |
145 | { | |
146 | case CONST_INT: | |
147 | return !splittable_const_int_operand (op, mode); | |
148 | ||
b4feb49c | 149 | case CONST_POLY_INT: |
150 | return known_eq (rtx_to_poly_int64 (op), BYTES_PER_RISCV_VECTOR); | |
151 | ||
09cae750 PD |
152 | case CONST: |
153 | case SYMBOL_REF: | |
154 | case LABEL_REF: | |
155 | return riscv_symbolic_constant_p (op, &symbol_type) | |
156 | && !riscv_split_symbol_type (symbol_type); | |
157 | ||
158 | case HIGH: | |
159 | op = XEXP (op, 0); | |
160 | return riscv_symbolic_constant_p (op, &symbol_type) | |
161 | && riscv_split_symbol_type (symbol_type) | |
162 | && symbol_type != SYMBOL_PCREL; | |
163 | ||
164 | default: | |
165 | return true; | |
166 | } | |
167 | }) | |
168 | ||
169 | (define_predicate "symbolic_operand" | |
170 | (match_code "const,symbol_ref,label_ref") | |
171 | { | |
172 | enum riscv_symbol_type type; | |
173 | return riscv_symbolic_constant_p (op, &type); | |
174 | }) | |
175 | ||
176 | (define_predicate "absolute_symbolic_operand" | |
177 | (match_code "const,symbol_ref,label_ref") | |
178 | { | |
179 | enum riscv_symbol_type type; | |
180 | return (riscv_symbolic_constant_p (op, &type) | |
181 | && (type == SYMBOL_ABSOLUTE || type == SYMBOL_PCREL)); | |
182 | }) | |
183 | ||
184 | (define_predicate "plt_symbolic_operand" | |
185 | (match_code "const,symbol_ref,label_ref") | |
186 | { | |
187 | enum riscv_symbol_type type; | |
188 | return (riscv_symbolic_constant_p (op, &type) | |
189 | && type == SYMBOL_GOT_DISP && !SYMBOL_REF_WEAK (op) && TARGET_PLT); | |
190 | }) | |
191 | ||
192 | (define_predicate "call_insn_operand" | |
193 | (ior (match_operand 0 "absolute_symbolic_operand") | |
194 | (match_operand 0 "plt_symbolic_operand") | |
195 | (match_operand 0 "register_operand"))) | |
196 | ||
197 | (define_predicate "modular_operator" | |
198 | (match_code "plus,minus,mult,ashift")) | |
199 | ||
200 | (define_predicate "equality_operator" | |
201 | (match_code "eq,ne")) | |
202 | ||
203 | (define_predicate "order_operator" | |
204 | (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu")) | |
205 | ||
206 | (define_predicate "signed_order_operator" | |
207 | (match_code "eq,ne,lt,le,ge,gt")) | |
208 | ||
7ac4dfec MC |
209 | (define_predicate "subreg_lowpart_operator" |
210 | (ior (match_code "truncate") | |
211 | (and (match_code "subreg") | |
212 | (match_test "subreg_lowpart_p (op)")))) | |
213 | ||
09cae750 PD |
214 | (define_predicate "fp_native_comparison" |
215 | (match_code "eq,lt,le,gt,ge")) | |
216 | ||
217 | (define_predicate "fp_scc_comparison" | |
218 | (match_code "unordered,ordered,unlt,unge,unle,ungt,ltgt,ne,eq,lt,le,gt,ge")) | |
219 | ||
220 | (define_predicate "fp_branch_comparison" | |
221 | (match_code "unordered,ordered,unlt,unge,unle,ungt,uneq,ltgt,ne,eq,lt,le,gt,ge")) | |
d0e0c130 KC |
222 | |
223 | (define_special_predicate "gpr_save_operation" | |
224 | (match_code "parallel") | |
225 | { | |
226 | return riscv_gpr_save_operation_p (op); | |
227 | }) | |
4e1e0d79 JW |
228 | |
229 | ;; Predicates for the ZBS extension. | |
230 | (define_predicate "single_bit_mask_operand" | |
231 | (and (match_code "const_int") | |
2c721ea9 | 232 | (match_test "SINGLE_BIT_MASK_OPERAND (UINTVAL (op))"))) |
4e1e0d79 JW |
233 | |
234 | (define_predicate "not_single_bit_mask_operand" | |
235 | (and (match_code "const_int") | |
2c721ea9 | 236 | (match_test "SINGLE_BIT_MASK_OPERAND (~UINTVAL (op))"))) |
4e1e0d79 JW |
237 | |
238 | (define_predicate "const31_operand" | |
239 | (and (match_code "const_int") | |
240 | (match_test "INTVAL (op) == 31"))) | |
241 | ||
242 | (define_predicate "const63_operand" | |
243 | (and (match_code "const_int") | |
244 | (match_test "INTVAL (op) == 63"))) | |
3df3ca90 S |
245 | |
246 | (define_predicate "imm5_operand" | |
247 | (and (match_code "const_int") | |
248 | (match_test "INTVAL (op) < 5"))) | |
4bf0dcb0 | 249 | |
b7d4b734 AP |
250 | ;; A const_int for sh1add/sh2add/sh3add |
251 | (define_predicate "imm123_operand" | |
252 | (and (match_code "const_int") | |
253 | (match_test "IN_RANGE (INTVAL (op), 1, 3)"))) | |
254 | ||
4bf0dcb0 PT |
255 | ;; A CONST_INT operand that consists of a single run of consecutive set bits. |
256 | (define_predicate "consecutive_bits_operand" | |
257 | (match_code "const_int") | |
258 | { | |
259 | unsigned HOST_WIDE_INT val = UINTVAL (op); | |
260 | if (exact_log2 ((val >> ctz_hwi (val)) + 1) < 0) | |
261 | return false; | |
262 | ||
263 | return true; | |
264 | }) | |
f556cd8b JZZ |
265 | |
266 | ;; Predicates for the V extension. | |
267 | (define_special_predicate "vector_length_operand" | |
268 | (ior (match_operand 0 "pmode_register_operand") | |
269 | (match_operand 0 "const_csr_operand"))) | |
270 | ||
271 | (define_predicate "reg_or_mem_operand" | |
272 | (ior (match_operand 0 "register_operand") | |
273 | (match_operand 0 "memory_operand"))) | |
274 | ||
275 | (define_predicate "vector_move_operand" | |
276 | (ior (match_operand 0 "nonimmediate_operand") | |
277 | (match_code "const_vector"))) | |
278 | ||
279 | (define_predicate "vector_mask_operand" | |
280 | (ior (match_operand 0 "register_operand") | |
281 | (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) | |
282 | ||
283 | (define_predicate "vector_merge_operand" | |
284 | (ior (match_operand 0 "memory_operand") | |
285 | (ior (match_operand 0 "register_operand") | |
286 | (match_test "GET_CODE (op) == UNSPEC | |
287 | && (XINT (op, 1) == UNSPEC_VUNDEF)")))) | |
0045d254 | 288 | |
fa144175 JZZ |
289 | ;; The scalar operand can be directly broadcast by RVV instructions. |
290 | (define_predicate "direct_broadcast_operand" | |
291 | (ior (match_operand 0 "register_operand") | |
292 | (match_test "satisfies_constraint_Wdm (op)"))) | |
293 | ||
0045d254 PT |
294 | ;; A CONST_INT operand that has exactly two bits cleared. |
295 | (define_predicate "const_nottwobits_operand" | |
296 | (and (match_code "const_int") | |
297 | (match_test "popcount_hwi (~UINTVAL (op)) == 2"))) | |
acbb5ef0 PT |
298 | |
299 | ;; A CONST_INT operand that consists of a single run of 32 consecutive | |
300 | ;; set bits. | |
301 | (define_predicate "consecutive_bits32_operand" | |
302 | (and (match_operand 0 "consecutive_bits_operand") | |
303 | (match_test "popcount_hwi (UINTVAL (op)) == 32"))) | |
304 | ||
305 | ;; A CONST_INT operand that, if shifted down to start with its least | |
306 | ;; significant non-zero bit, is a SMALL_OPERAND (suitable as an | |
307 | ;; immediate to logical and arithmetic instructions). | |
308 | (define_predicate "shifted_const_arith_operand" | |
309 | (and (match_code "const_int") | |
310 | (match_test "ctz_hwi (INTVAL (op)) > 0") | |
311 | (match_test "SMALL_OPERAND (INTVAL (op) >> ctz_hwi (INTVAL (op)))"))) | |
312 | ||
bc6beecb PT |
313 | ;; A CONST_INT operand that has exactly two bits set. |
314 | (define_predicate "const_twobits_operand" | |
315 | (and (match_code "const_int") | |
316 | (match_test "popcount_hwi (UINTVAL (op)) == 2"))) | |
317 | ||
60d2bcc5 PT |
318 | (define_predicate "const_twobits_not_arith_operand" |
319 | (and (match_code "const_int") | |
320 | (and (not (match_operand 0 "arith_operand")) | |
321 | (match_operand 0 "const_twobits_operand")))) | |
322 | ||
acbb5ef0 | 323 | ;; A CONST_INT operand that fits into the unsigned half of a |
bc6beecb | 324 | ;; signed-immediate after the top bit has been cleared |
acbb5ef0 PT |
325 | (define_predicate "uimm_extra_bit_operand" |
326 | (and (match_code "const_int") | |
bc6beecb PT |
327 | (match_test "UIMM_EXTRA_BIT_OPERAND (UINTVAL (op))"))) |
328 | ||
329 | (define_predicate "uimm_extra_bit_or_twobits" | |
330 | (and (match_code "const_int") | |
331 | (ior (match_operand 0 "uimm_extra_bit_operand") | |
332 | (match_operand 0 "const_twobits_operand")))) | |
333 | ||
334 | ;; A CONST_INT operand that fits into the negative half of a | |
335 | ;; signed-immediate after a single cleared top bit has been | |
336 | ;; set: i.e., a bitwise-negated uimm_extra_bit_operand | |
337 | (define_predicate "not_uimm_extra_bit_operand" | |
338 | (and (match_code "const_int") | |
339 | (match_test "UIMM_EXTRA_BIT_OPERAND (~UINTVAL (op))"))) | |
340 | ||
341 | (define_predicate "not_uimm_extra_bit_or_nottwobits" | |
342 | (and (match_code "const_int") | |
343 | (ior (match_operand 0 "not_uimm_extra_bit_operand") | |
344 | (match_operand 0 "const_nottwobits_operand")))) |