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09cae750 | 1 | ;; Predicate description for RISC-V target. |
83ffe9cd | 2 | ;; Copyright (C) 2011-2023 Free Software Foundation, Inc. |
09cae750 PD |
3 | ;; Contributed by Andrew Waterman (andrew@sifive.com). |
4 | ;; Based on MIPS target for GNU compiler. | |
5 | ;; | |
6 | ;; This file is part of GCC. | |
7 | ;; | |
8 | ;; GCC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 3, or (at your option) | |
11 | ;; any later version. | |
12 | ;; | |
13 | ;; GCC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ;; | |
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GCC; see the file COPYING3. If not see | |
20 | ;; <http://www.gnu.org/licenses/>. | |
21 | ||
22 | (define_predicate "const_arith_operand" | |
23 | (and (match_code "const_int") | |
24 | (match_test "SMALL_OPERAND (INTVAL (op))"))) | |
25 | ||
26 | (define_predicate "arith_operand" | |
27 | (ior (match_operand 0 "const_arith_operand") | |
28 | (match_operand 0 "register_operand"))) | |
29 | ||
10680bc3 JH |
30 | (define_predicate "arith_operand_or_mode_mask" |
31 | (ior (match_operand 0 "arith_operand") | |
32 | (and (match_code "const_int") | |
f5c82bff | 33 | (match_test "UINTVAL (op) == GET_MODE_MASK (HImode) |
37ff12b9 | 34 | || UINTVAL (op) == GET_MODE_MASK (SImode)")))) |
10680bc3 | 35 | |
4f475391 AW |
36 | (define_predicate "lui_operand" |
37 | (and (match_code "const_int") | |
38 | (match_test "LUI_OPERAND (INTVAL (op))"))) | |
39 | ||
40 | (define_predicate "sfb_alu_operand" | |
41 | (ior (match_operand 0 "arith_operand") | |
42 | (match_operand 0 "lui_operand"))) | |
43 | ||
09cae750 PD |
44 | (define_predicate "const_csr_operand" |
45 | (and (match_code "const_int") | |
46 | (match_test "IN_RANGE (INTVAL (op), 0, 31)"))) | |
47 | ||
48 | (define_predicate "csr_operand" | |
49 | (ior (match_operand 0 "const_csr_operand") | |
50 | (match_operand 0 "register_operand"))) | |
51 | ||
0337555c PD |
52 | ;; V has 32-bit unsigned immediates. This happens to be the same constraint as |
53 | ;; the csr_operand, but it's not CSR related. | |
54 | (define_predicate "vector_scalar_shift_operand" | |
55 | (match_operand 0 "csr_operand")) | |
56 | ||
09cae750 PD |
57 | (define_predicate "sle_operand" |
58 | (and (match_code "const_int") | |
59 | (match_test "SMALL_OPERAND (INTVAL (op) + 1)"))) | |
60 | ||
61 | (define_predicate "sleu_operand" | |
62 | (and (match_operand 0 "sle_operand") | |
63 | (match_test "INTVAL (op) + 1 != 0"))) | |
64 | ||
65 | (define_predicate "const_0_operand" | |
ecfa870f | 66 | (and (match_code "const_int,const_wide_int,const_double,const_vector") |
09cae750 PD |
67 | (match_test "op == CONST0_RTX (GET_MODE (op))"))) |
68 | ||
f048af2a JZZ |
69 | (define_predicate "const_1_operand" |
70 | (and (match_code "const_int,const_wide_int,const_vector") | |
71 | (match_test "op == CONST1_RTX (GET_MODE (op))"))) | |
72 | ||
4e35cf2e LD |
73 | (define_predicate "const_1_or_2_operand" |
74 | (and (match_code "const_int") | |
75 | (match_test "INTVAL (op) == 1 || INTVAL (op) == 2"))) | |
76 | ||
77 | (define_predicate "const_1_or_4_operand" | |
78 | (and (match_code "const_int") | |
79 | (match_test "INTVAL (op) == 1 || INTVAL (op) == 4"))) | |
80 | ||
09cae750 PD |
81 | (define_predicate "reg_or_0_operand" |
82 | (ior (match_operand 0 "const_0_operand") | |
83 | (match_operand 0 "register_operand"))) | |
84 | ||
d7b60202 | 85 | ;; ZCMP predicates |
3d1d3132 FG |
86 | (define_predicate "stack_push_up_to_ra_operand" |
87 | (and (match_code "const_int") | |
88 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 1)"))) | |
89 | ||
90 | (define_predicate "stack_push_up_to_s0_operand" | |
91 | (and (match_code "const_int") | |
92 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 2)"))) | |
93 | ||
94 | (define_predicate "stack_push_up_to_s1_operand" | |
95 | (and (match_code "const_int") | |
96 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 3)"))) | |
97 | ||
98 | (define_predicate "stack_push_up_to_s2_operand" | |
99 | (and (match_code "const_int") | |
100 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 4)"))) | |
101 | ||
102 | (define_predicate "stack_push_up_to_s3_operand" | |
103 | (and (match_code "const_int") | |
104 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 5)"))) | |
105 | ||
106 | (define_predicate "stack_push_up_to_s4_operand" | |
107 | (and (match_code "const_int") | |
108 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 6)"))) | |
109 | ||
110 | (define_predicate "stack_push_up_to_s5_operand" | |
111 | (and (match_code "const_int") | |
112 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 7)"))) | |
113 | ||
114 | (define_predicate "stack_push_up_to_s6_operand" | |
115 | (and (match_code "const_int") | |
116 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 8)"))) | |
117 | ||
118 | (define_predicate "stack_push_up_to_s7_operand" | |
119 | (and (match_code "const_int") | |
120 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 9)"))) | |
121 | ||
122 | (define_predicate "stack_push_up_to_s8_operand" | |
123 | (and (match_code "const_int") | |
124 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 10)"))) | |
125 | ||
126 | (define_predicate "stack_push_up_to_s9_operand" | |
127 | (and (match_code "const_int") | |
128 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 11)"))) | |
129 | ||
130 | (define_predicate "stack_push_up_to_s11_operand" | |
131 | (and (match_code "const_int") | |
132 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op) * -1, 13)"))) | |
133 | ||
134 | (define_predicate "stack_pop_up_to_ra_operand" | |
135 | (and (match_code "const_int") | |
136 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 1)"))) | |
137 | ||
138 | (define_predicate "stack_pop_up_to_s0_operand" | |
139 | (and (match_code "const_int") | |
140 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 2)"))) | |
141 | ||
142 | (define_predicate "stack_pop_up_to_s1_operand" | |
143 | (and (match_code "const_int") | |
144 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 3)"))) | |
145 | ||
146 | (define_predicate "stack_pop_up_to_s2_operand" | |
147 | (and (match_code "const_int") | |
148 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 4)"))) | |
149 | ||
150 | (define_predicate "stack_pop_up_to_s3_operand" | |
151 | (and (match_code "const_int") | |
152 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 5)"))) | |
153 | ||
154 | (define_predicate "stack_pop_up_to_s4_operand" | |
155 | (and (match_code "const_int") | |
156 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 6)"))) | |
157 | ||
158 | (define_predicate "stack_pop_up_to_s5_operand" | |
159 | (and (match_code "const_int") | |
160 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 7)"))) | |
161 | ||
162 | (define_predicate "stack_pop_up_to_s6_operand" | |
163 | (and (match_code "const_int") | |
164 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 8)"))) | |
165 | ||
166 | (define_predicate "stack_pop_up_to_s7_operand" | |
167 | (and (match_code "const_int") | |
168 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 9)"))) | |
169 | ||
170 | (define_predicate "stack_pop_up_to_s8_operand" | |
171 | (and (match_code "const_int") | |
172 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 10)"))) | |
173 | ||
174 | (define_predicate "stack_pop_up_to_s9_operand" | |
175 | (and (match_code "const_int") | |
176 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 11)"))) | |
177 | ||
178 | (define_predicate "stack_pop_up_to_s11_operand" | |
179 | (and (match_code "const_int") | |
180 | (match_test "riscv_zcmp_valid_stack_adj_bytes_p (INTVAL (op), 13)"))) | |
181 | ||
490bf0b9 | 182 | (define_predicate "a0a1_reg_operand" |
d7b60202 | 183 | (and (match_code "reg") |
490bf0b9 DL |
184 | (match_test "IN_RANGE (REGNO (op), A0_REGNUM, A1_REGNUM)"))) |
185 | ||
186 | (define_predicate "zcmp_mv_sreg_operand" | |
d7b60202 | 187 | (and (match_code "reg") |
490bf0b9 DL |
188 | (match_test "TARGET_RVE ? IN_RANGE (REGNO (op), S0_REGNUM, S1_REGNUM) |
189 | : IN_RANGE (REGNO (op), S0_REGNUM, S1_REGNUM) | |
190 | || IN_RANGE (REGNO (op), S2_REGNUM, S7_REGNUM)"))) | |
191 | ||
09cae750 PD |
192 | ;; Only use branch-on-bit sequences when the mask is not an ANDI immediate. |
193 | (define_predicate "branch_on_bit_operand" | |
194 | (and (match_code "const_int") | |
195 | (match_test "INTVAL (op) >= IMM_BITS - 1"))) | |
196 | ||
197 | ;; A legitimate CONST_INT operand that takes more than one instruction | |
198 | ;; to load. | |
199 | (define_predicate "splittable_const_int_operand" | |
200 | (match_code "const_int") | |
201 | { | |
202 | /* Don't handle multi-word moves this way; we don't want to introduce | |
203 | the individual word-mode moves until after reload. */ | |
3496ca4e | 204 | if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD) |
09cae750 PD |
205 | return false; |
206 | ||
4e1e0d79 JW |
207 | /* Check whether the constant can be loaded in a single |
208 | instruction with zbs extensions. */ | |
ffe4f55a | 209 | if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (INTVAL (op))) |
4e1e0d79 JW |
210 | return false; |
211 | ||
09cae750 PD |
212 | /* Otherwise check whether the constant can be loaded in a single |
213 | instruction. */ | |
214 | return !LUI_OPERAND (INTVAL (op)) && !SMALL_OPERAND (INTVAL (op)); | |
215 | }) | |
216 | ||
666fdc46 JW |
217 | (define_predicate "p2m1_shift_operand" |
218 | (match_code "const_int") | |
219 | { | |
220 | int val = exact_log2 (INTVAL (op) + 1); | |
221 | if (val < 12) | |
222 | return false; | |
223 | return true; | |
224 | }) | |
225 | ||
226 | (define_predicate "high_mask_shift_operand" | |
227 | (match_code "const_int") | |
228 | { | |
229 | int val1 = clz_hwi (~ INTVAL (op)); | |
230 | int val0 = ctz_hwi (INTVAL (op)); | |
231 | if ((val0 + val1 == BITS_PER_WORD) | |
232 | && val0 > 31 && val0 < 64) | |
233 | return true; | |
234 | return false; | |
235 | }) | |
236 | ||
09cae750 PD |
237 | (define_predicate "move_operand" |
238 | (match_operand 0 "general_operand") | |
239 | { | |
240 | enum riscv_symbol_type symbol_type; | |
241 | ||
242 | /* The thinking here is as follows: | |
243 | ||
244 | (1) The move expanders should split complex load sequences into | |
245 | individual instructions. Those individual instructions can | |
246 | then be optimized by all rtl passes. | |
247 | ||
248 | (2) The target of pre-reload load sequences should not be used | |
249 | to store temporary results. If the target register is only | |
250 | assigned one value, reload can rematerialize that value | |
251 | on demand, rather than spill it to the stack. | |
252 | ||
253 | (3) If we allowed pre-reload passes like combine and cse to recreate | |
254 | complex load sequences, we would want to be able to split the | |
255 | sequences before reload as well, so that the pre-reload scheduler | |
256 | can see the individual instructions. This falls foul of (2); | |
257 | the splitter would be forced to reuse the target register for | |
258 | intermediate results. | |
259 | ||
260 | (4) We want to define complex load splitters for combine. These | |
261 | splitters can request a temporary scratch register, which avoids | |
262 | the problem in (2). They allow things like: | |
263 | ||
264 | (set (reg T1) (high SYM)) | |
265 | (set (reg T2) (low (reg T1) SYM)) | |
266 | (set (reg X) (plus (reg T2) (const_int OFFSET))) | |
267 | ||
268 | to be combined into: | |
269 | ||
270 | (set (reg T3) (high SYM+OFFSET)) | |
271 | (set (reg X) (lo_sum (reg T3) SYM+OFFSET)) | |
272 | ||
273 | if T2 is only used this once. */ | |
274 | switch (GET_CODE (op)) | |
275 | { | |
276 | case CONST_INT: | |
277 | return !splittable_const_int_operand (op, mode); | |
278 | ||
b4feb49c | 279 | case CONST_POLY_INT: |
280 | return known_eq (rtx_to_poly_int64 (op), BYTES_PER_RISCV_VECTOR); | |
281 | ||
09cae750 PD |
282 | case CONST: |
283 | case SYMBOL_REF: | |
284 | case LABEL_REF: | |
285 | return riscv_symbolic_constant_p (op, &symbol_type) | |
286 | && !riscv_split_symbol_type (symbol_type); | |
287 | ||
288 | case HIGH: | |
289 | op = XEXP (op, 0); | |
290 | return riscv_symbolic_constant_p (op, &symbol_type) | |
291 | && riscv_split_symbol_type (symbol_type) | |
292 | && symbol_type != SYMBOL_PCREL; | |
293 | ||
294 | default: | |
295 | return true; | |
296 | } | |
297 | }) | |
298 | ||
299 | (define_predicate "symbolic_operand" | |
300 | (match_code "const,symbol_ref,label_ref") | |
301 | { | |
302 | enum riscv_symbol_type type; | |
303 | return riscv_symbolic_constant_p (op, &type); | |
304 | }) | |
305 | ||
306 | (define_predicate "absolute_symbolic_operand" | |
307 | (match_code "const,symbol_ref,label_ref") | |
308 | { | |
309 | enum riscv_symbol_type type; | |
310 | return (riscv_symbolic_constant_p (op, &type) | |
311 | && (type == SYMBOL_ABSOLUTE || type == SYMBOL_PCREL)); | |
312 | }) | |
313 | ||
314 | (define_predicate "plt_symbolic_operand" | |
315 | (match_code "const,symbol_ref,label_ref") | |
316 | { | |
317 | enum riscv_symbol_type type; | |
318 | return (riscv_symbolic_constant_p (op, &type) | |
319 | && type == SYMBOL_GOT_DISP && !SYMBOL_REF_WEAK (op) && TARGET_PLT); | |
320 | }) | |
321 | ||
322 | (define_predicate "call_insn_operand" | |
323 | (ior (match_operand 0 "absolute_symbolic_operand") | |
324 | (match_operand 0 "plt_symbolic_operand") | |
325 | (match_operand 0 "register_operand"))) | |
326 | ||
327 | (define_predicate "modular_operator" | |
328 | (match_code "plus,minus,mult,ashift")) | |
329 | ||
330 | (define_predicate "equality_operator" | |
331 | (match_code "eq,ne")) | |
332 | ||
333 | (define_predicate "order_operator" | |
334 | (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu")) | |
335 | ||
336 | (define_predicate "signed_order_operator" | |
337 | (match_code "eq,ne,lt,le,ge,gt")) | |
338 | ||
7ac4dfec MC |
339 | (define_predicate "subreg_lowpart_operator" |
340 | (ior (match_code "truncate") | |
341 | (and (match_code "subreg") | |
342 | (match_test "subreg_lowpart_p (op)")))) | |
343 | ||
09cae750 PD |
344 | (define_predicate "fp_native_comparison" |
345 | (match_code "eq,lt,le,gt,ge")) | |
346 | ||
347 | (define_predicate "fp_scc_comparison" | |
348 | (match_code "unordered,ordered,unlt,unge,unle,ungt,ltgt,ne,eq,lt,le,gt,ge")) | |
349 | ||
350 | (define_predicate "fp_branch_comparison" | |
351 | (match_code "unordered,ordered,unlt,unge,unle,ungt,uneq,ltgt,ne,eq,lt,le,gt,ge")) | |
d0e0c130 KC |
352 | |
353 | (define_special_predicate "gpr_save_operation" | |
354 | (match_code "parallel") | |
355 | { | |
356 | return riscv_gpr_save_operation_p (op); | |
357 | }) | |
4e1e0d79 JW |
358 | |
359 | ;; Predicates for the ZBS extension. | |
360 | (define_predicate "single_bit_mask_operand" | |
361 | (and (match_code "const_int") | |
2c721ea9 | 362 | (match_test "SINGLE_BIT_MASK_OPERAND (UINTVAL (op))"))) |
4e1e0d79 JW |
363 | |
364 | (define_predicate "not_single_bit_mask_operand" | |
365 | (and (match_code "const_int") | |
2c721ea9 | 366 | (match_test "SINGLE_BIT_MASK_OPERAND (~UINTVAL (op))"))) |
4e1e0d79 | 367 | |
6da6ed95 | 368 | (define_predicate "const_si_mask_operand" |
4e1e0d79 | 369 | (and (match_code "const_int") |
6da6ed95 JH |
370 | (match_test "(INTVAL (op) & (GET_MODE_BITSIZE (SImode) - 1)) |
371 | == GET_MODE_BITSIZE (SImode) - 1"))) | |
4e1e0d79 | 372 | |
6da6ed95 | 373 | (define_predicate "const_di_mask_operand" |
4e1e0d79 | 374 | (and (match_code "const_int") |
6da6ed95 JH |
375 | (match_test "(INTVAL (op) & (GET_MODE_BITSIZE (DImode) - 1)) |
376 | == GET_MODE_BITSIZE (DImode) - 1"))) | |
3df3ca90 S |
377 | |
378 | (define_predicate "imm5_operand" | |
379 | (and (match_code "const_int") | |
380 | (match_test "INTVAL (op) < 5"))) | |
4bf0dcb0 | 381 | |
b7d4b734 AP |
382 | ;; A const_int for sh1add/sh2add/sh3add |
383 | (define_predicate "imm123_operand" | |
384 | (and (match_code "const_int") | |
385 | (match_test "IN_RANGE (INTVAL (op), 1, 3)"))) | |
386 | ||
4bf0dcb0 PT |
387 | ;; A CONST_INT operand that consists of a single run of consecutive set bits. |
388 | (define_predicate "consecutive_bits_operand" | |
389 | (match_code "const_int") | |
390 | { | |
391 | unsigned HOST_WIDE_INT val = UINTVAL (op); | |
392 | if (exact_log2 ((val >> ctz_hwi (val)) + 1) < 0) | |
393 | return false; | |
394 | ||
395 | return true; | |
396 | }) | |
f556cd8b JZZ |
397 | |
398 | ;; Predicates for the V extension. | |
399 | (define_special_predicate "vector_length_operand" | |
400 | (ior (match_operand 0 "pmode_register_operand") | |
401 | (match_operand 0 "const_csr_operand"))) | |
402 | ||
d42d199e JZ |
403 | (define_special_predicate "autovec_length_operand" |
404 | (ior (match_operand 0 "pmode_register_operand") | |
0618adfa | 405 | (match_code "const_int,const_poly_int"))) |
d42d199e | 406 | |
f556cd8b JZZ |
407 | (define_predicate "reg_or_mem_operand" |
408 | (ior (match_operand 0 "register_operand") | |
409 | (match_operand 0 "memory_operand"))) | |
410 | ||
a035d133 JZZ |
411 | (define_predicate "reg_or_int_operand" |
412 | (ior (match_operand 0 "register_operand") | |
413 | (match_operand 0 "const_int_operand"))) | |
414 | ||
86d80395 LD |
415 | (define_predicate "vector_const_0_operand" |
416 | (and (match_code "const_vector") | |
417 | (match_test "satisfies_constraint_Wc0 (op)"))) | |
418 | ||
973eb0de LD |
419 | (define_predicate "vector_const_int_or_double_0_operand" |
420 | (and (match_code "const_vector") | |
421 | (match_test "satisfies_constraint_vi (op) | |
422 | || satisfies_constraint_Wc0 (op)"))) | |
423 | ||
f556cd8b JZZ |
424 | (define_predicate "vector_move_operand" |
425 | (ior (match_operand 0 "nonimmediate_operand") | |
a035d133 JZZ |
426 | (and (match_code "const_vector") |
427 | (match_test "reload_completed | |
428 | || satisfies_constraint_vi (op) | |
429 | || satisfies_constraint_Wc0 (op)")))) | |
f556cd8b | 430 | |
acb51b5c | 431 | (define_predicate "vector_all_trues_mask_operand" |
ec99ffab | 432 | (and (match_code "const_vector") |
f556cd8b JZZ |
433 | (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) |
434 | ||
ec99ffab JZZ |
435 | (define_predicate "vector_least_significant_set_mask_operand" |
436 | (and (match_code "const_vector") | |
437 | (match_test "rtx_equal_p (op, riscv_vector::gen_scalar_move_mask (GET_MODE (op)))"))) | |
438 | ||
acb51b5c JZZ |
439 | (define_predicate "vector_mask_operand" |
440 | (ior (match_operand 0 "register_operand") | |
441 | (match_operand 0 "vector_all_trues_mask_operand"))) | |
442 | ||
ec99ffab JZZ |
443 | (define_predicate "vector_broadcast_mask_operand" |
444 | (ior (match_operand 0 "vector_least_significant_set_mask_operand") | |
445 | (ior (match_operand 0 "register_operand") | |
446 | (match_operand 0 "vector_all_trues_mask_operand")))) | |
447 | ||
acb51b5c | 448 | (define_predicate "vector_undef_operand" |
272e119d | 449 | (match_test "rtx_equal_p (op, RVV_VUNDEF (GET_MODE (op)))")) |
acb51b5c | 450 | |
f556cd8b | 451 | (define_predicate "vector_merge_operand" |
6271a072 | 452 | (ior (match_operand 0 "register_operand") |
acb51b5c | 453 | (match_operand 0 "vector_undef_operand"))) |
0045d254 | 454 | |
2a937fb5 JZZ |
455 | (define_predicate "vector_arith_operand" |
456 | (ior (match_operand 0 "register_operand") | |
457 | (and (match_code "const_vector") | |
458 | (match_test "riscv_vector::const_vec_all_same_in_range_p (op, -16, 15)")))) | |
459 | ||
460 | (define_predicate "vector_neg_arith_operand" | |
461 | (ior (match_operand 0 "register_operand") | |
462 | (and (match_code "const_vector") | |
463 | (match_test "riscv_vector::const_vec_all_same_in_range_p (op, -15, 16)")))) | |
464 | ||
465 | (define_predicate "vector_shift_operand" | |
466 | (ior (match_operand 0 "register_operand") | |
467 | (and (match_code "const_vector") | |
468 | (match_test "riscv_vector::const_vec_all_same_in_range_p (op, 0, 31)")))) | |
469 | ||
bf9eee73 JZ |
470 | (define_predicate "vector_perm_operand" |
471 | (ior (match_operand 0 "register_operand") | |
472 | (match_code "const_vector"))) | |
473 | ||
f048af2a JZZ |
474 | (define_predicate "vector_gs_scale_operand_64" |
475 | (and (match_code "const_int") | |
476 | (match_test "INTVAL (op) == 1 || (INTVAL (op) == 8 && Pmode == DImode)"))) | |
477 | ||
478 | (define_predicate "vector_gs_extension_operand" | |
479 | (ior (match_operand 0 "const_1_operand") | |
480 | (and (match_operand 0 "const_0_operand") | |
481 | (match_test "Pmode == SImode")))) | |
482 | ||
483 | (define_predicate "vector_gs_scale_operand_16_rv32" | |
484 | (and (match_code "const_int") | |
485 | (match_test "INTVAL (op) == 1 | |
486 | || (INTVAL (op) == 2 && Pmode == SImode)"))) | |
487 | ||
488 | (define_predicate "vector_gs_scale_operand_32_rv32" | |
489 | (and (match_code "const_int") | |
490 | (match_test "INTVAL (op) == 1 | |
491 | || (INTVAL (op) == 4 && Pmode == SImode)"))) | |
492 | ||
acb51b5c JZZ |
493 | (define_predicate "ltge_operator" |
494 | (match_code "lt,ltu,ge,geu")) | |
495 | ||
496 | (define_predicate "comparison_except_ltge_operator" | |
497 | (match_code "eq,ne,le,leu,gt,gtu")) | |
498 | ||
499 | (define_predicate "comparison_except_eqge_operator" | |
500 | (match_code "le,leu,gt,gtu,lt,ltu")) | |
501 | ||
502 | (define_predicate "ge_operator" | |
503 | (match_code "ge,geu")) | |
504 | ||
61122017 JZZ |
505 | ;; pmode_reg_or_uimm5_operand can be used by vsll.vx/vsrl.vx/vsra.vx instructions. |
506 | ;; Since it has the same predicate with vector_length_operand which allows register | |
507 | ;; or immediate (0 ~ 31), we define this predicate same as vector_length_operand here. | |
508 | ;; We don't use vector_length_operand directly to predicate vsll.vx/vsrl.vx/vsra.vx | |
509 | ;; since it may be confusing. | |
510 | (define_special_predicate "pmode_reg_or_uimm5_operand" | |
511 | (match_operand 0 "vector_length_operand")) | |
512 | ||
eb1c2960 JZZ |
513 | (define_special_predicate "pmode_reg_or_0_operand" |
514 | (ior (match_operand 0 "const_0_operand") | |
515 | (match_operand 0 "pmode_register_operand"))) | |
516 | ||
7caa1ae5 JZZ |
517 | ;; A special predicate that doesn't match a particular mode. |
518 | (define_special_predicate "vector_any_register_operand" | |
519 | (match_code "reg")) | |
520 | ||
fa144175 JZZ |
521 | ;; The scalar operand can be directly broadcast by RVV instructions. |
522 | (define_predicate "direct_broadcast_operand" | |
a035d133 | 523 | (and (match_test "!(reload_completed && !FLOAT_MODE_P (GET_MODE (op)) |
ec99ffab JZZ |
524 | && (register_operand (op, GET_MODE (op)) || CONST_INT_P (op) |
525 | || rtx_equal_p (op, CONST0_RTX (GET_MODE (op)))) | |
a035d133 | 526 | && maybe_gt (GET_MODE_BITSIZE (GET_MODE (op)), GET_MODE_BITSIZE (Pmode)))") |
ec99ffab | 527 | (ior (match_test "rtx_equal_p (op, CONST0_RTX (GET_MODE (op)))") |
f048af2a | 528 | (ior (match_code "const_int,const_poly_int") |
ec99ffab JZZ |
529 | (ior (match_operand 0 "register_operand") |
530 | (match_test "satisfies_constraint_Wdm (op)")))))) | |
fa144175 | 531 | |
0045d254 PT |
532 | ;; A CONST_INT operand that has exactly two bits cleared. |
533 | (define_predicate "const_nottwobits_operand" | |
534 | (and (match_code "const_int") | |
535 | (match_test "popcount_hwi (~UINTVAL (op)) == 2"))) | |
acbb5ef0 | 536 | |
392200f8 JH |
537 | (define_predicate "const_nottwobits_not_arith_operand" |
538 | (and (match_code "const_int") | |
539 | (and (not (match_operand 0 "arith_operand")) | |
540 | (match_operand 0 "const_nottwobits_operand")))) | |
541 | ||
acbb5ef0 PT |
542 | ;; A CONST_INT operand that consists of a single run of 32 consecutive |
543 | ;; set bits. | |
544 | (define_predicate "consecutive_bits32_operand" | |
545 | (and (match_operand 0 "consecutive_bits_operand") | |
546 | (match_test "popcount_hwi (UINTVAL (op)) == 32"))) | |
547 | ||
548 | ;; A CONST_INT operand that, if shifted down to start with its least | |
549 | ;; significant non-zero bit, is a SMALL_OPERAND (suitable as an | |
550 | ;; immediate to logical and arithmetic instructions). | |
551 | (define_predicate "shifted_const_arith_operand" | |
552 | (and (match_code "const_int") | |
553 | (match_test "ctz_hwi (INTVAL (op)) > 0") | |
554 | (match_test "SMALL_OPERAND (INTVAL (op) >> ctz_hwi (INTVAL (op)))"))) | |
555 | ||
bc6beecb PT |
556 | ;; A CONST_INT operand that has exactly two bits set. |
557 | (define_predicate "const_twobits_operand" | |
558 | (and (match_code "const_int") | |
559 | (match_test "popcount_hwi (UINTVAL (op)) == 2"))) | |
560 | ||
60d2bcc5 PT |
561 | (define_predicate "const_twobits_not_arith_operand" |
562 | (and (match_code "const_int") | |
563 | (and (not (match_operand 0 "arith_operand")) | |
564 | (match_operand 0 "const_twobits_operand")))) | |
565 | ||
acbb5ef0 | 566 | ;; A CONST_INT operand that fits into the unsigned half of a |
bc6beecb | 567 | ;; signed-immediate after the top bit has been cleared |
acbb5ef0 PT |
568 | (define_predicate "uimm_extra_bit_operand" |
569 | (and (match_code "const_int") | |
bc6beecb PT |
570 | (match_test "UIMM_EXTRA_BIT_OPERAND (UINTVAL (op))"))) |
571 | ||
572 | (define_predicate "uimm_extra_bit_or_twobits" | |
573 | (and (match_code "const_int") | |
574 | (ior (match_operand 0 "uimm_extra_bit_operand") | |
0c5e64c4 | 575 | (match_operand 0 "const_twobits_not_arith_operand")))) |
bc6beecb PT |
576 | |
577 | ;; A CONST_INT operand that fits into the negative half of a | |
578 | ;; signed-immediate after a single cleared top bit has been | |
579 | ;; set: i.e., a bitwise-negated uimm_extra_bit_operand | |
580 | (define_predicate "not_uimm_extra_bit_operand" | |
581 | (and (match_code "const_int") | |
582 | (match_test "UIMM_EXTRA_BIT_OPERAND (~UINTVAL (op))"))) | |
583 | ||
584 | (define_predicate "not_uimm_extra_bit_or_nottwobits" | |
585 | (and (match_code "const_int") | |
586 | (ior (match_operand 0 "not_uimm_extra_bit_operand") | |
392200f8 | 587 | (match_operand 0 "const_nottwobits_not_arith_operand")))) |