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[PATCH v4 1/2] RISC-V: Add support for XCVmac extension in CV32E40P
[thirdparty/gcc.git] / gcc / config / riscv / riscv-builtins.cc
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09cae750 1/* Subroutines used for expanding RISC-V builtins.
83ffe9cd 2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
09cae750
PD
3 Contributed by Andrew Waterman (andrew@sifive.com).
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 3, or (at your option)
10any later version.
11
12GCC is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING3. If not see
19<http://www.gnu.org/licenses/>. */
20
8fcc61f8
RS
21#define IN_TARGET_CODE 1
22
09cae750
PD
23#include "config.h"
24#include "system.h"
25#include "coretypes.h"
26#include "tm.h"
27#include "rtl.h"
28#include "tree.h"
29#include "gimple-expr.h"
30#include "memmodel.h"
31#include "expmed.h"
1b68a156 32#include "profile-count.h"
09cae750
PD
33#include "optabs.h"
34#include "recog.h"
35#include "diagnostic-core.h"
36#include "stor-layout.h"
27d68a60 37#include "stringpool.h"
09cae750
PD
38#include "expr.h"
39#include "langhooks.h"
7d935cdd 40#include "tm_p.h"
60bd33bc
JZZ
41#include "backend.h"
42#include "gimple.h"
43#include "gimple-iterator.h"
09cae750
PD
44
45/* Macros to create an enumeration identifier for a function prototype. */
33d9794b 46#define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
09cae750 47#define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
89456334
LS
48#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
49#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D
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MB
50#define RISCV_FTYPE_NAME4(A, B, C, D, E) \
51 RISCV_##A##_FTYPE_##B##_##C##_##D##_##E
09cae750
PD
52
53/* Classifies the prototype of a built-in function. */
54enum riscv_function_type {
55#define DEF_RISCV_FTYPE(NARGS, LIST) RISCV_FTYPE_NAME##NARGS LIST,
56#include "config/riscv/riscv-ftypes.def"
57#undef DEF_RISCV_FTYPE
58 RISCV_MAX_FTYPE_MAX
59};
60
61/* Specifies how a built-in function should be converted into rtl. */
62enum riscv_builtin_type {
63 /* The function corresponds directly to an .md pattern. */
64 RISCV_BUILTIN_DIRECT,
65
66 /* Likewise, but with return type VOID. */
67 RISCV_BUILTIN_DIRECT_NO_TARGET
68};
69
70/* Declare an availability predicate for built-in functions. */
71#define AVAIL(NAME, COND) \
72 static unsigned int \
73 riscv_builtin_avail_##NAME (void) \
74 { \
75 return (COND); \
76 }
77
78/* This structure describes a single built-in function. */
79struct riscv_builtin_description {
80 /* The code of the main .md file instruction. See riscv_builtin_type
81 for more information. */
82 enum insn_code icode;
83
84 /* The name of the built-in function. */
85 const char *name;
86
87 /* Specifies how the function should be expanded. */
88 enum riscv_builtin_type builtin_type;
89
90 /* The function's prototype. */
91 enum riscv_function_type prototype;
92
93 /* Whether the function is available. */
94 unsigned int (*avail) (void);
95};
96
ac96e906 97AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX)
3df3ca90
S
98AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT)
99AVAIL (clean64, TARGET_ZICBOM && TARGET_64BIT)
100AVAIL (flush32, TARGET_ZICBOM && !TARGET_64BIT)
101AVAIL (flush64, TARGET_ZICBOM && TARGET_64BIT)
102AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT)
103AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT)
104AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT)
105AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT)
106AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
107AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
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LS
108AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT)
109AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT)
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LS
110AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
111AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT)
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LS
112AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT)
113AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
114AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT)
115AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
116AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
9882b814 117AVAIL (crypto_zknh, TARGET_ZKNH)
e6416e43
LS
118AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
119AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
9882b814
TO
120AVAIL (crypto_zksh, TARGET_ZKSH)
121AVAIL (crypto_zksed, TARGET_ZKSED)
d9df45a6
KS
122AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC) && !TARGET_64BIT)
123AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT)
124AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT)
125AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT)
c2d04dd6 126AVAIL (hint_pause, (!0))
3df3ca90 127
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128// CORE-V AVAIL
129AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)
130
09cae750
PD
131/* Construct a riscv_builtin_description from the given arguments.
132
133 INSN is the name of the associated instruction pattern, without the
134 leading CODE_FOR_riscv_.
135
136 NAME is the name of the function itself, without the leading
137 "__builtin_riscv_".
138
139 BUILTIN_TYPE and FUNCTION_TYPE are riscv_builtin_description fields.
140
141 AVAIL is the name of the availability predicate, without the leading
142 riscv_builtin_avail_. */
143#define RISCV_BUILTIN(INSN, NAME, BUILTIN_TYPE, FUNCTION_TYPE, AVAIL) \
144 { CODE_FOR_riscv_ ## INSN, "__builtin_riscv_" NAME, \
145 BUILTIN_TYPE, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
146
147/* Define __builtin_riscv_<INSN>, which is a RISCV_BUILTIN_DIRECT function
148 mapped to instruction CODE_FOR_riscv_<INSN>, FUNCTION_TYPE and AVAIL
149 are as for RISCV_BUILTIN. */
150#define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
151 RISCV_BUILTIN (INSN, #INSN, RISCV_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
152
153/* Define __builtin_riscv_<INSN>, which is a RISCV_BUILTIN_DIRECT_NO_TARGET
154 function mapped to instruction CODE_FOR_riscv_<INSN>, FUNCTION_TYPE
155 and AVAIL are as for RISCV_BUILTIN. */
156#define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
157 RISCV_BUILTIN (INSN, #INSN, RISCV_BUILTIN_DIRECT_NO_TARGET, \
158 FUNCTION_TYPE, AVAIL)
159
160/* Argument types. */
161#define RISCV_ATYPE_VOID void_type_node
a1751681
TO
162#define RISCV_ATYPE_UQI unsigned_intQI_type_node
163#define RISCV_ATYPE_UHI unsigned_intHI_type_node
09cae750 164#define RISCV_ATYPE_USI unsigned_intSI_type_node
a1751681 165#define RISCV_ATYPE_UDI unsigned_intDI_type_node
400efddd 166#define RISCV_ATYPE_SI intSI_type_node
970b03c0 167#define RISCV_ATYPE_VOID_PTR ptr_type_node
09cae750
PD
168
169/* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
170 their associated RISCV_ATYPEs. */
33d9794b
KC
171#define RISCV_FTYPE_ATYPES0(A) \
172 RISCV_ATYPE_##A
09cae750
PD
173#define RISCV_FTYPE_ATYPES1(A, B) \
174 RISCV_ATYPE_##A, RISCV_ATYPE_##B
89456334
LS
175#define RISCV_FTYPE_ATYPES2(A, B, C) \
176 RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
177#define RISCV_FTYPE_ATYPES3(A, B, C, D) \
178 RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
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MB
179#define RISCV_FTYPE_ATYPES4(A, B, C, D, E) \
180 RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D, \
181 RISCV_ATYPE_##E
09cae750
PD
182
183static const struct riscv_builtin_description riscv_builtins[] = {
3df3ca90 184 #include "riscv-cmo.def"
2c809510 185 #include "riscv-scalar-crypto.def"
400efddd 186 #include "corev.def"
3df3ca90 187
33d9794b 188 DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
c717a92d 189 DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),
c2d04dd6 190 RISCV_BUILTIN (pause, "pause", RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE, hint_pause),
09cae750
PD
191};
192
193/* Index I is the function declaration for riscv_builtins[I], or null if the
194 function isn't defined on this target. */
195static GTY(()) tree riscv_builtin_decls[ARRAY_SIZE (riscv_builtins)];
196
197/* Get the index I of the function declaration for riscv_builtin_decls[I]
198 using the instruction code or return null if not defined for the target. */
199static GTY(()) int riscv_builtin_decl_index[NUM_INSN_CODES];
200
201#define GET_BUILTIN_DECL(CODE) \
202 riscv_builtin_decls[riscv_builtin_decl_index[(CODE)]]
203
27d68a60
KC
204tree riscv_float16_type_node = NULL_TREE;
205
09cae750
PD
206/* Return the function type associated with function prototype TYPE. */
207
208static tree
209riscv_build_function_type (enum riscv_function_type type)
210{
211 static tree types[(int) RISCV_MAX_FTYPE_MAX];
212
213 if (types[(int) type] == NULL_TREE)
214 switch (type)
215 {
216#define DEF_RISCV_FTYPE(NUM, ARGS) \
217 case RISCV_FTYPE_NAME##NUM ARGS: \
218 types[(int) type] \
219 = build_function_type_list (RISCV_FTYPE_ATYPES##NUM ARGS, \
220 NULL_TREE); \
221 break;
222#include "config/riscv/riscv-ftypes.def"
223#undef DEF_RISCV_FTYPE
224 default:
225 gcc_unreachable ();
226 }
227
228 return types[(int) type];
229}
230
27d68a60
KC
231static void
232riscv_init_builtin_types (void)
233{
234 /* Provide the _Float16 type and float16_type_node if needed. */
235 if (!float16_type_node)
236 {
237 riscv_float16_type_node = make_node (REAL_TYPE);
238 TYPE_PRECISION (riscv_float16_type_node) = 16;
239 SET_TYPE_MODE (riscv_float16_type_node, HFmode);
240 layout_type (riscv_float16_type_node);
241 }
242 else
243 riscv_float16_type_node = float16_type_node;
244
245 if (!maybe_get_identifier ("_Float16"))
246 lang_hooks.types.register_builtin_type (riscv_float16_type_node,
247 "_Float16");
248}
249
09cae750
PD
250/* Implement TARGET_INIT_BUILTINS. */
251
252void
253riscv_init_builtins (void)
254{
27d68a60 255 riscv_init_builtin_types ();
03f33657 256 riscv_vector::init_builtins ();
27d68a60 257
09cae750
PD
258 for (size_t i = 0; i < ARRAY_SIZE (riscv_builtins); i++)
259 {
260 const struct riscv_builtin_description *d = &riscv_builtins[i];
261 if (d->avail ())
262 {
263 tree type = riscv_build_function_type (d->prototype);
264 riscv_builtin_decls[i]
cbd50570
JZZ
265 = add_builtin_function (d->name, type,
266 (i << RISCV_BUILTIN_SHIFT)
267 + RISCV_BUILTIN_GENERAL,
268 BUILT_IN_MD, NULL, NULL);
09cae750
PD
269 riscv_builtin_decl_index[d->icode] = i;
270 }
271 }
272}
273
274/* Implement TARGET_BUILTIN_DECL. */
275
276tree
277riscv_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
278{
cbd50570
JZZ
279 unsigned int subcode = code >> RISCV_BUILTIN_SHIFT;
280 switch (code & RISCV_BUILTIN_CLASS)
281 {
282 case RISCV_BUILTIN_GENERAL:
283 if (subcode >= ARRAY_SIZE (riscv_builtins))
284 return error_mark_node;
285 return riscv_builtin_decls[subcode];
286
287 case RISCV_BUILTIN_VECTOR:
288 return riscv_vector::builtin_decl (subcode, initialize_p);
289 }
290 return error_mark_node;
09cae750
PD
291}
292
293/* Take argument ARGNO from EXP's argument list and convert it into
294 an expand operand. Store the operand in *OP. */
295
296static void
297riscv_prepare_builtin_arg (struct expand_operand *op, tree exp, unsigned argno)
298{
299 tree arg = CALL_EXPR_ARG (exp, argno);
300 create_input_operand (op, expand_normal (arg), TYPE_MODE (TREE_TYPE (arg)));
301}
302
303/* Expand instruction ICODE as part of a built-in function sequence.
304 Use the first NOPS elements of OPS as the instruction's operands.
305 HAS_TARGET_P is true if operand 0 is a target; it is false if the
306 instruction has no target.
307
308 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
309
310static rtx
311riscv_expand_builtin_insn (enum insn_code icode, unsigned int n_ops,
312 struct expand_operand *ops, bool has_target_p)
313{
314 if (!maybe_expand_insn (icode, n_ops, ops))
315 {
316 error ("invalid argument to built-in function");
317 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
318 }
319
320 return has_target_p ? ops[0].value : const0_rtx;
321}
322
323/* Expand a RISCV_BUILTIN_DIRECT or RISCV_BUILTIN_DIRECT_NO_TARGET function;
324 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
325 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
326 suggests a good place to put the result. */
327
328static rtx
329riscv_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
330 bool has_target_p)
331{
332 struct expand_operand ops[MAX_RECOG_OPERANDS];
333
334 /* Map any target to operand 0. */
335 int opno = 0;
336 if (has_target_p)
337 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
338
339 /* Map the arguments to the other operands. */
340 gcc_assert (opno + call_expr_nargs (exp)
341 == insn_data[icode].n_generator_args);
342 for (int argno = 0; argno < call_expr_nargs (exp); argno++)
343 riscv_prepare_builtin_arg (&ops[opno++], exp, argno);
344
345 return riscv_expand_builtin_insn (icode, opno, ops, has_target_p);
346}
347
60bd33bc
JZZ
348/* Implement TARGET_GIMPLE_FOLD_BUILTIN. */
349
350bool
351riscv_gimple_fold_builtin (gimple_stmt_iterator *gsi)
352{
353 gcall *stmt = as_a<gcall *> (gsi_stmt (*gsi));
354 tree fndecl = gimple_call_fndecl (stmt);
355 unsigned int code = DECL_MD_FUNCTION_CODE (fndecl);
356 unsigned int subcode = code >> RISCV_BUILTIN_SHIFT;
357 gimple *new_stmt = NULL;
358 switch (code & RISCV_BUILTIN_CLASS)
359 {
360 case RISCV_BUILTIN_GENERAL:
361 new_stmt = NULL;
362 break;
363
364 case RISCV_BUILTIN_VECTOR:
365 new_stmt = riscv_vector::gimple_fold_builtin (subcode, gsi, stmt);
366 break;
367 }
368
369 if (!new_stmt)
370 return false;
371
372 gsi_replace (gsi, new_stmt, false);
373 return true;
374}
375
09cae750
PD
376/* Implement TARGET_EXPAND_BUILTIN. */
377
378rtx
379riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
380 machine_mode mode ATTRIBUTE_UNUSED,
381 int ignore ATTRIBUTE_UNUSED)
382{
383 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
4d732405 384 unsigned int fcode = DECL_MD_FUNCTION_CODE (fndecl);
cbd50570
JZZ
385 unsigned int subcode = fcode >> RISCV_BUILTIN_SHIFT;
386 switch (fcode & RISCV_BUILTIN_CLASS)
09cae750 387 {
cbd50570
JZZ
388 case RISCV_BUILTIN_VECTOR:
389 return riscv_vector::expand_builtin (subcode, exp, target);
390 case RISCV_BUILTIN_GENERAL: {
391 const struct riscv_builtin_description *d = &riscv_builtins[subcode];
392
393 switch (d->builtin_type)
394 {
395 case RISCV_BUILTIN_DIRECT:
396 return riscv_expand_builtin_direct (d->icode, target, exp, true);
397
398 case RISCV_BUILTIN_DIRECT_NO_TARGET:
399 return riscv_expand_builtin_direct (d->icode, target, exp, false);
400 }
401 }
09cae750
PD
402 }
403
404 gcc_unreachable ();
405}
406
407/* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
408
409void
410riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
411{
ac96e906 412 if (!(TARGET_HARD_FLOAT || TARGET_ZFINX))
09cae750
PD
413 return;
414
415 tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags);
416 tree fsflags = GET_BUILTIN_DECL (CODE_FOR_riscv_fsflags);
417 tree old_flags = create_tmp_var_raw (RISCV_ATYPE_USI);
418
b4ace720
JJ
419 *hold = build4 (TARGET_EXPR, RISCV_ATYPE_USI, old_flags,
420 build_call_expr (frflags, 0), NULL_TREE, NULL_TREE);
09cae750
PD
421 *clear = build_call_expr (fsflags, 1, old_flags);
422 *update = NULL_TREE;
423}