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09cae750 | 1 | /* RISC-V-specific code for C family languages. |
99dee823 | 2 | Copyright (C) 2011-2021 Free Software Foundation, Inc. |
09cae750 PD |
3 | Contributed by Andrew Waterman (andrew@sifive.com). |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
8fcc61f8 RS |
21 | #define IN_TARGET_CODE 1 |
22 | ||
09cae750 PD |
23 | #include "config.h" |
24 | #include "system.h" | |
25 | #include "coretypes.h" | |
26 | #include "tm.h" | |
27 | #include "c-family/c-common.h" | |
28 | #include "cpplib.h" | |
29 | ||
30 | #define builtin_define(TXT) cpp_define (pfile, TXT) | |
31 | ||
32 | /* Implement TARGET_CPU_CPP_BUILTINS. */ | |
33 | ||
34 | void | |
35 | riscv_cpu_cpp_builtins (cpp_reader *pfile) | |
36 | { | |
37 | builtin_define ("__riscv"); | |
119b4963 | 38 | |
09cae750 PD |
39 | if (TARGET_RVC) |
40 | builtin_define ("__riscv_compressed"); | |
119b4963 | 41 | |
09baee1a KC |
42 | if (TARGET_RVE) |
43 | builtin_define ("__riscv_32e"); | |
44 | ||
09cae750 PD |
45 | if (TARGET_ATOMIC) |
46 | builtin_define ("__riscv_atomic"); | |
119b4963 | 47 | |
09cae750 PD |
48 | if (TARGET_MUL) |
49 | builtin_define ("__riscv_mul"); | |
50 | if (TARGET_DIV) | |
51 | builtin_define ("__riscv_div"); | |
52 | if (TARGET_DIV && TARGET_MUL) | |
53 | builtin_define ("__riscv_muldiv"); | |
119b4963 | 54 | |
09cae750 PD |
55 | builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8); |
56 | if (TARGET_HARD_FLOAT) | |
57 | builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8); | |
119b4963 | 58 | |
09cae750 PD |
59 | if (TARGET_HARD_FLOAT && TARGET_FDIV) |
60 | { | |
61 | builtin_define ("__riscv_fdiv"); | |
62 | builtin_define ("__riscv_fsqrt"); | |
63 | } | |
119b4963 | 64 | |
09cae750 PD |
65 | switch (riscv_abi) |
66 | { | |
09baee1a | 67 | case ABI_ILP32E: |
119b4963 JW |
68 | builtin_define ("__riscv_abi_rve"); |
69 | gcc_fallthrough (); | |
70 | ||
71 | case ABI_ILP32: | |
09cae750 PD |
72 | case ABI_LP64: |
73 | builtin_define ("__riscv_float_abi_soft"); | |
74 | break; | |
119b4963 | 75 | |
09cae750 PD |
76 | case ABI_ILP32F: |
77 | case ABI_LP64F: | |
78 | builtin_define ("__riscv_float_abi_single"); | |
79 | break; | |
119b4963 | 80 | |
09cae750 PD |
81 | case ABI_ILP32D: |
82 | case ABI_LP64D: | |
83 | builtin_define ("__riscv_float_abi_double"); | |
84 | break; | |
85 | } | |
119b4963 | 86 | |
09cae750 PD |
87 | switch (riscv_cmodel) |
88 | { | |
89 | case CM_MEDLOW: | |
90 | builtin_define ("__riscv_cmodel_medlow"); | |
91 | break; | |
119b4963 | 92 | |
30784833 KC |
93 | case CM_PIC: |
94 | /* __riscv_cmodel_pic is deprecated, and will removed in next GCC release. | |
95 | see https://github.com/riscv/riscv-c-api-doc/pull/11 */ | |
96 | builtin_define ("__riscv_cmodel_pic"); | |
97 | /* FALLTHROUGH. */ | |
98 | ||
09cae750 PD |
99 | case CM_MEDANY: |
100 | builtin_define ("__riscv_cmodel_medany"); | |
101 | break; | |
119b4963 | 102 | |
09cae750 PD |
103 | } |
104 | } |