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| Commit | Line | Data |
|---|---|---|
| 72eb8335 | 1 | /* List of supported core and tune info for RISC-V. |
| 83ffe9cd | 2 | Copyright (C) 2020-2023 Free Software Foundation, Inc. |
| 72eb8335 KC |
3 | |
| 4 | This file is part of GCC. | |
| 5 | ||
| 6 | GCC is free software; you can redistribute it and/or modify it | |
| 7 | under the terms of the GNU General Public License as published by | |
| 8 | the Free Software Foundation; either version 3, or (at your option) | |
| 9 | any later version. | |
| 10 | ||
| 11 | GCC is distributed in the hope that it will be useful, but | |
| 12 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | General Public License for more details. | |
| 15 | ||
| 16 | You should have received a copy of the GNU General Public License | |
| 17 | along with GCC; see the file COPYING3. If not see | |
| 18 | <http://www.gnu.org/licenses/>. */ | |
| 19 | ||
| 97d1ed67 KC |
20 | /* This is a list of tune that implement RISC-V. |
| 21 | ||
| 22 | Before using #include to read this file, define a macro: | |
| 23 | ||
| 24 | RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) | |
| 25 | ||
| 26 | The TUNE_NAME is the name of the micro-arch, represented as a string. | |
| 27 | The PIPELINE_MODEL is the pipeline model of the micro-arch, represented as a | |
| 28 | string, defined in riscv.md. | |
| 29 | The TUNE_INFO is the detail cost model for this core, represented as an | |
| 30 | identifier, reference to riscv.cc. */ | |
| 31 | ||
| 32 | #ifndef RISCV_TUNE | |
| 33 | #define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) | |
| 34 | #endif | |
| 35 | ||
| 36 | RISCV_TUNE("rocket", generic, rocket_tune_info) | |
| 37 | RISCV_TUNE("sifive-3-series", generic, rocket_tune_info) | |
| 38 | RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) | |
| 2f6cb9c5 | 39 | RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) |
| 97d1ed67 KC |
40 | RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) |
| 41 | RISCV_TUNE("size", generic, optimize_size_tune_info) | |
| 42 | ||
| 43 | #undef RISCV_TUNE | |
| 44 | ||
| 72eb8335 KC |
45 | /* This is a list of cores that implement RISC-V. |
| 46 | ||
| 47 | Before using #include to read this file, define a macro: | |
| 48 | ||
| 97d1ed67 | 49 | RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH) |
| 72eb8335 KC |
50 | |
| 51 | The CORE_NAME is the name of the core, represented as a string. | |
| 52 | The ARCH is the default arch of the core, represented as a string, | |
| 53 | can be NULL if no default arch. | |
| 54 | The MICRO_ARCH is the name of the core for which scheduling decisions | |
| 97d1ed67 KC |
55 | will be made, represented as an identifier. */ |
| 56 | ||
| 57 | #ifndef RISCV_CORE | |
| 58 | #define RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH) | |
| 59 | #endif | |
| 72eb8335 KC |
60 | |
| 61 | RISCV_CORE("sifive-e20", "rv32imc", "rocket") | |
| 62 | RISCV_CORE("sifive-e21", "rv32imac", "rocket") | |
| 63 | RISCV_CORE("sifive-e24", "rv32imafc", "rocket") | |
| 64 | RISCV_CORE("sifive-e31", "rv32imac", "sifive-3-series") | |
| 65 | RISCV_CORE("sifive-e34", "rv32imafc", "sifive-3-series") | |
| 66 | RISCV_CORE("sifive-e76", "rv32imafc", "sifive-7-series") | |
| 67 | ||
| 68 | RISCV_CORE("sifive-s21", "rv64imac", "rocket") | |
| 69 | RISCV_CORE("sifive-s51", "rv64imac", "sifive-5-series") | |
| 70 | RISCV_CORE("sifive-s54", "rv64imafdc", "sifive-5-series") | |
| 71 | RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") | |
| 72 | ||
| 73 | RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") | |
| 74 | RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") | |
| 75 | ||
| 76 | #undef RISCV_CORE |