projects / thirdparty / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| 09cae750 | 1 | /* Definition of RISC-V target for GNU compiler. |
| 99dee823 | 2 | Copyright (C) 2016-2021 Free Software Foundation, Inc. |
| 09cae750 PD |
3 | Contributed by Andrew Waterman (andrew@sifive.com). |
| 4 | ||
| 5 | This file is part of GCC. | |
| 6 | ||
| 7 | GCC is free software; you can redistribute it and/or modify | |
| 8 | it under the terms of the GNU General Public License as published by | |
| 9 | the Free Software Foundation; either version 3, or (at your option) | |
| 10 | any later version. | |
| 11 | ||
| 12 | GCC is distributed in the hope that it will be useful, | |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | GNU General Public License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with GCC; see the file COPYING3. If not see | |
| 19 | <http://www.gnu.org/licenses/>. */ | |
| 20 | ||
| 21 | #ifndef GCC_RISCV_OPTS_H | |
| 22 | #define GCC_RISCV_OPTS_H | |
| 23 | ||
| 24 | enum riscv_abi_type { | |
| 25 | ABI_ILP32, | |
| 09baee1a | 26 | ABI_ILP32E, |
| 09cae750 PD |
27 | ABI_ILP32F, |
| 28 | ABI_ILP32D, | |
| 29 | ABI_LP64, | |
| 30 | ABI_LP64F, | |
| 31 | ABI_LP64D | |
| 32 | }; | |
| 33 | extern enum riscv_abi_type riscv_abi; | |
| 34 | ||
| 35 | enum riscv_code_model { | |
| 36 | CM_MEDLOW, | |
| 37 | CM_MEDANY, | |
| 38 | CM_PIC | |
| 39 | }; | |
| 40 | extern enum riscv_code_model riscv_cmodel; | |
| 41 | ||
| 4b815282 KC |
42 | enum riscv_isa_spec_class { |
| 43 | ISA_SPEC_CLASS_NONE, | |
| 44 | ||
| 45 | ISA_SPEC_CLASS_2P2, | |
| 46 | ISA_SPEC_CLASS_20190608, | |
| 47 | ISA_SPEC_CLASS_20191213 | |
| 48 | }; | |
| 49 | ||
| 50 | extern enum riscv_isa_spec_class riscv_isa_spec; | |
| 51 | ||
| 88108b27 AW |
52 | /* Keep this list in sync with define_attr "tune" in riscv.md. */ |
| 53 | enum riscv_microarchitecture_type { | |
| 54 | generic, | |
| 55 | sifive_7 | |
| 56 | }; | |
| 57 | extern enum riscv_microarchitecture_type riscv_microarchitecture; | |
| 58 | ||
| ffbb9818 ID |
59 | enum riscv_align_data { |
| 60 | riscv_align_data_type_xlen, | |
| 61 | riscv_align_data_type_natural | |
| 62 | }; | |
| 63 | ||
| c931e8d5 CQ |
64 | /* Where to get the canary for the stack protector. */ |
| 65 | enum stack_protector_guard { | |
| 66 | SSP_TLS, /* per-thread canary in TLS block */ | |
| 67 | SSP_GLOBAL /* global canary */ | |
| 68 | }; | |
| 69 | ||
| b03be74b KC |
70 | #define MASK_ZICSR (1 << 0) |
| 71 | #define MASK_ZIFENCEI (1 << 1) | |
| 72 | ||
| 73 | #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) | |
| 74 | #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) | |
| 75 | ||
| 09cae750 | 76 | #endif /* ! GCC_RISCV_OPTS_H */ |