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09cae750 | 1 | /* Definition of RISC-V target for GNU compiler. |
83ffe9cd | 2 | Copyright (C) 2011-2023 Free Software Foundation, Inc. |
09cae750 PD |
3 | Contributed by Andrew Waterman (andrew@sifive.com). |
4 | Based on MIPS target for GNU compiler. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef GCC_RISCV_PROTOS_H | |
23 | #define GCC_RISCV_PROTOS_H | |
24 | ||
942ab49b PN |
25 | #include "memmodel.h" |
26 | ||
09cae750 PD |
27 | /* Symbol types we understand. The order of this list must match that of |
28 | the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ | |
29 | enum riscv_symbol_type { | |
30 | SYMBOL_ABSOLUTE, | |
31 | SYMBOL_PCREL, | |
32 | SYMBOL_GOT_DISP, | |
33 | SYMBOL_TLS, | |
34 | SYMBOL_TLS_LE, | |
35 | SYMBOL_TLS_IE, | |
36 | SYMBOL_TLS_GD | |
37 | }; | |
38 | #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1) | |
39 | ||
e53b6e56 | 40 | /* Routines implemented in riscv.cc. */ |
09cae750 PD |
41 | extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); |
42 | extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); | |
b8506a8a | 43 | extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool); |
b8506a8a | 44 | extern int riscv_address_insns (rtx, machine_mode, bool); |
09cae750 PD |
45 | extern int riscv_const_insns (rtx); |
46 | extern int riscv_split_const_insns (rtx); | |
47 | extern int riscv_load_store_insns (rtx, rtx_insn *); | |
48 | extern rtx riscv_emit_move (rtx, rtx); | |
05302544 | 49 | extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *); |
09cae750 PD |
50 | extern bool riscv_split_symbol_type (enum riscv_symbol_type); |
51 | extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type); | |
05302544 | 52 | extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode); |
b8506a8a | 53 | extern bool riscv_legitimize_move (machine_mode, rtx, rtx); |
09cae750 PD |
54 | extern rtx riscv_subword (rtx, bool); |
55 | extern bool riscv_split_64bit_move_p (rtx, rtx); | |
56 | extern void riscv_split_doubleword_move (rtx, rtx); | |
57 | extern const char *riscv_output_move (rtx, rtx); | |
8cad5b14 | 58 | extern const char *riscv_output_return (); |
02fcaf41 | 59 | |
09cae750 PD |
60 | #ifdef RTX_CODE |
61 | extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx); | |
62 | extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx); | |
63 | extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx); | |
64 | #endif | |
8e7ffe12 | 65 | extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx); |
09cae750 PD |
66 | extern rtx riscv_legitimize_call_address (rtx); |
67 | extern void riscv_set_return_address (rtx, rtx); | |
68 | extern bool riscv_expand_block_move (rtx, rtx, rtx); | |
69 | extern rtx riscv_return_addr (int, rtx); | |
3496ca4e | 70 | extern poly_int64 riscv_initial_elimination_offset (int, int); |
09cae750 | 71 | extern void riscv_expand_prologue (void); |
fd1e52dc | 72 | extern void riscv_expand_epilogue (int); |
d0ebdd9f | 73 | extern bool riscv_epilogue_uses (unsigned int); |
09cae750 | 74 | extern bool riscv_can_use_return_insn (void); |
6ed01e6b | 75 | extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode); |
6ed01e6b | 76 | extern bool riscv_expand_block_move (rtx, rtx, rtx); |
88108b27 | 77 | extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *); |
d0e0c130 KC |
78 | extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *); |
79 | extern bool riscv_gpr_save_operation_p (rtx); | |
b4feb49c | 80 | extern void riscv_reinit (void); |
f556cd8b | 81 | extern poly_uint64 riscv_regmode_natural_size (machine_mode); |
7e924ba3 | 82 | extern bool riscv_v_ext_vector_mode_p (machine_mode); |
12847288 | 83 | extern bool riscv_v_ext_tuple_mode_p (machine_mode); |
787ac959 | 84 | extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); |
f797260a PN |
85 | extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); |
86 | extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); | |
942ab49b | 87 | extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); |
09cae750 | 88 | |
e53b6e56 | 89 | /* Routines implemented in riscv-c.cc. */ |
09cae750 | 90 | void riscv_cpu_cpp_builtins (cpp_reader *); |
7d935cdd | 91 | void riscv_register_pragmas (void); |
09cae750 | 92 | |
e53b6e56 | 93 | /* Routines implemented in riscv-builtins.cc. */ |
09cae750 | 94 | extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *); |
60bd33bc | 95 | extern bool riscv_gimple_fold_builtin (gimple_stmt_iterator *); |
b8506a8a | 96 | extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int); |
09cae750 PD |
97 | extern tree riscv_builtin_decl (unsigned int, bool); |
98 | extern void riscv_init_builtins (void); | |
99 | ||
e53b6e56 | 100 | /* Routines implemented in riscv-common.cc. */ |
f908b69c | 101 | extern std::string riscv_arch_str (bool version_p = true); |
b4feb49c | 102 | extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t); |
8e966210 | 103 | |
e0a5b313 KC |
104 | extern bool riscv_hard_regno_rename_ok (unsigned, unsigned); |
105 | ||
de6320a8 | 106 | rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt); |
9243c3d1 | 107 | rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt); |
de6320a8 | 108 | |
72eb8335 KC |
109 | /* Information about one CPU we know about. */ |
110 | struct riscv_cpu_info { | |
111 | /* This CPU's canonical name. */ | |
112 | const char *name; | |
113 | ||
114 | /* Default arch for this CPU, could be NULL if no default arch. */ | |
115 | const char *arch; | |
116 | ||
117 | /* Which automaton to use for tuning. */ | |
118 | const char *tune; | |
119 | }; | |
120 | ||
121 | extern const riscv_cpu_info *riscv_find_cpu (const char *); | |
122 | ||
b4feb49c | 123 | /* Routines implemented in riscv-selftests.cc. */ |
124 | #if CHECKING_P | |
125 | namespace selftest { | |
3b6d44f4 | 126 | void riscv_run_selftests (void); |
b4feb49c | 127 | } // namespace selftest |
128 | #endif | |
129 | ||
7d935cdd | 130 | namespace riscv_vector { |
fa144175 | 131 | #define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM) |
272e119d | 132 | #define RVV_VUNDEF(MODE) \ |
7caa1ae5 JZZ |
133 | gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)), \ |
134 | UNSPEC_VUNDEF) | |
3b16afeb JZZ |
135 | enum vlmul_type |
136 | { | |
137 | LMUL_1 = 0, | |
138 | LMUL_2 = 1, | |
139 | LMUL_4 = 2, | |
140 | LMUL_8 = 3, | |
141 | LMUL_RESERVED = 4, | |
142 | LMUL_F8 = 5, | |
143 | LMUL_F4 = 6, | |
144 | LMUL_F2 = 7, | |
ec99ffab | 145 | NUM_LMUL = 8 |
3b16afeb | 146 | }; |
9243c3d1 JZZ |
147 | |
148 | enum avl_type | |
149 | { | |
150 | NONVLMAX, | |
151 | VLMAX, | |
152 | }; | |
7d935cdd | 153 | /* Routines implemented in riscv-vector-builtins.cc. */ |
3b6d44f4 JZZ |
154 | void init_builtins (void); |
155 | const char *mangle_builtin_type (const_tree); | |
7d935cdd | 156 | #ifdef GCC_TARGET_H |
3b6d44f4 | 157 | bool verify_type_context (location_t, type_context_kind, const_tree, bool); |
7d935cdd | 158 | #endif |
3b6d44f4 JZZ |
159 | void handle_pragma_vector (void); |
160 | tree builtin_decl (unsigned, bool); | |
60bd33bc | 161 | gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *); |
3b6d44f4 | 162 | rtx expand_builtin (unsigned int, tree, rtx); |
7caa1ae5 JZZ |
163 | bool check_builtin_call (location_t, vec<location_t>, unsigned int, |
164 | tree, unsigned int, tree *); | |
3b6d44f4 JZZ |
165 | bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
166 | bool legitimize_move (rtx, rtx, machine_mode); | |
cd0c433e | 167 | void emit_vlmax_vsetvl (machine_mode, rtx); |
40fc8e3d | 168 | void emit_hard_vlmax_vsetvl (machine_mode, rtx); |
3b6d44f4 | 169 | void emit_vlmax_op (unsigned, rtx, rtx, machine_mode); |
cd0c433e | 170 | void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode); |
3b6d44f4 JZZ |
171 | void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode); |
172 | enum vlmul_type get_vlmul (machine_mode); | |
173 | unsigned int get_ratio (machine_mode); | |
12847288 JZZ |
174 | unsigned int get_nf (machine_mode); |
175 | machine_mode get_subpart_mode (machine_mode); | |
3b6d44f4 JZZ |
176 | int get_ta (rtx); |
177 | int get_ma (rtx); | |
178 | int get_avl_type (rtx); | |
179 | unsigned int calculate_ratio (unsigned int, enum vlmul_type); | |
f556cd8b JZZ |
180 | enum tail_policy |
181 | { | |
182 | TAIL_UNDISTURBED = 0, | |
183 | TAIL_AGNOSTIC = 1, | |
9243c3d1 | 184 | TAIL_ANY = 2, |
f556cd8b JZZ |
185 | }; |
186 | ||
187 | enum mask_policy | |
188 | { | |
189 | MASK_UNDISTURBED = 0, | |
190 | MASK_AGNOSTIC = 1, | |
9243c3d1 | 191 | MASK_ANY = 2, |
f556cd8b | 192 | }; |
9243c3d1 JZZ |
193 | enum tail_policy get_prefer_tail_policy (); |
194 | enum mask_policy get_prefer_mask_policy (); | |
a143c3f7 | 195 | rtx get_avl_type_rtx (enum avl_type); |
6c9bcb6c | 196 | opt_machine_mode get_vector_mode (scalar_mode, poly_uint64); |
12847288 | 197 | opt_machine_mode get_tuple_mode (machine_mode, unsigned int); |
3b6d44f4 JZZ |
198 | bool simm5_p (rtx); |
199 | bool neg_simm5_p (rtx); | |
a035d133 | 200 | #ifdef RTX_CODE |
3b6d44f4 | 201 | bool has_vi_variant_p (rtx_code, rtx); |
a035d133 | 202 | #endif |
3cb0fa12 JZZ |
203 | bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, machine_mode, |
204 | bool, void (*)(rtx *, rtx)); | |
ec99ffab | 205 | rtx gen_scalar_move_mask (machine_mode); |
1bff101b JZZ |
206 | |
207 | /* RVV vector register sizes. | |
208 | TODO: Currently, we only add RVV_32/RVV_64/RVV_128, we may need to | |
209 | support other values in the future. */ | |
210 | enum vlen_enum | |
211 | { | |
212 | RVV_32 = 32, | |
213 | RVV_64 = 64, | |
214 | RVV_65536 = 65536 | |
215 | }; | |
216 | bool slide1_sew64_helper (int, machine_mode, machine_mode, | |
217 | machine_mode, rtx *); | |
db4f7a9b | 218 | rtx gen_avl_for_scalar_move (rtx); |
12847288 | 219 | void expand_tuple_move (machine_mode, rtx *); |
7d935cdd JZZ |
220 | } |
221 | ||
cbd50570 JZZ |
222 | /* We classify builtin types into two classes: |
223 | 1. General builtin class which is defined in riscv_builtins. | |
224 | 2. Vector builtin class which is a special builtin architecture | |
225 | that implement intrinsic short into "pragma". */ | |
226 | enum riscv_builtin_class | |
227 | { | |
228 | RISCV_BUILTIN_GENERAL, | |
229 | RISCV_BUILTIN_VECTOR | |
230 | }; | |
231 | ||
232 | const unsigned int RISCV_BUILTIN_SHIFT = 1; | |
233 | ||
234 | /* Mask that selects the riscv_builtin_class part of a function code. */ | |
235 | const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1; | |
236 | ||
02fcaf41 CM |
237 | /* Routines implemented in thead.cc. */ |
238 | extern bool th_mempair_operands_p (rtx[4], bool, machine_mode); | |
239 | extern void th_mempair_order_operands (rtx[4], bool, machine_mode); | |
240 | extern void th_mempair_prepare_save_restore_operands (rtx[4], bool, | |
241 | machine_mode, | |
242 | int, HOST_WIDE_INT, | |
243 | int, HOST_WIDE_INT); | |
244 | extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode); | |
245 | #ifdef RTX_CODE | |
246 | extern const char* | |
247 | th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); | |
248 | #endif | |
249 | ||
065be0ff | 250 | extern bool riscv_use_divmod_expander (void); |
09cae750 | 251 | #endif /* ! GCC_RISCV_PROTOS_H */ |