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Revert "RISC-V: Refactor prefix [I/L/LL] rounding API autovec iterator"
[thirdparty/gcc.git] / gcc / config / riscv / riscv-protos.h
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09cae750 1/* Definition of RISC-V target for GNU compiler.
83ffe9cd 2 Copyright (C) 2011-2023 Free Software Foundation, Inc.
09cae750
PD		 3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
5
6This file is part of GCC.
7
8GCC is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 3, or (at your option)
11any later version.
12
13GCC is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with GCC; see the file COPYING3. If not see
20<http://www.gnu.org/licenses/>. */
21
22#ifndef GCC_RISCV_PROTOS_H
23#define GCC_RISCV_PROTOS_H
24
942ab49b
PN		 25#include "memmodel.h"
26
09cae750
PD		 27/* Symbol types we understand. The order of this list must match that of
28 the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */
29enum riscv_symbol_type {
30 SYMBOL_ABSOLUTE,
31 SYMBOL_PCREL,
32 SYMBOL_GOT_DISP,
33 SYMBOL_TLS,
34 SYMBOL_TLS_LE,
35 SYMBOL_TLS_IE,
36 SYMBOL_TLS_GD
37};
38#define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1)
39
96ad6ab2
CM		 40/* Classifies an address.
41
42 ADDRESS_REG
43 A natural register + offset address. The register satisfies
44 riscv_valid_base_register_p and the offset is a const_arith_operand.
45
2d65622f
CM		 46 ADDRESS_REG_REG
47 A base register indexed by (optionally scaled) register.
48
49 ADDRESS_REG_UREG
50 A base register indexed by (optionally scaled) zero-extended register.
51
52 ADDRESS_REG_WB
53 A base register indexed by immediate offset with writeback.
54
96ad6ab2
CM		 55 ADDRESS_LO_SUM
56 A LO_SUM rtx. The first operand is a valid base register and
57 the second operand is a symbolic address.
58
59 ADDRESS_CONST_INT
60 A signed 16-bit constant address.
61
62 ADDRESS_SYMBOLIC:
63 A constant symbolic address. */
64enum riscv_address_type {
65 ADDRESS_REG,
2d65622f
CM		 66 ADDRESS_REG_REG,
67 ADDRESS_REG_UREG,
68 ADDRESS_REG_WB,
96ad6ab2
CM		 69 ADDRESS_LO_SUM,
70 ADDRESS_CONST_INT,
71 ADDRESS_SYMBOLIC
72};
73
74/* Information about an address described by riscv_address_type.
75
76 ADDRESS_CONST_INT
77 No fields are used.
78
79 ADDRESS_REG
80 REG is the base register and OFFSET is the constant offset.
81
2d65622f
CM		 82 ADDRESS_REG_REG and ADDRESS_REG_UREG
83 REG is the base register and OFFSET is the index register.
84
85 ADDRESS_REG_WB
86 REG is the base register, OFFSET is the constant offset, and
87 shift is the shift amount for the offset.
88
96ad6ab2
CM		 89 ADDRESS_LO_SUM
90 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
91 is the type of symbol it references.
92
93 ADDRESS_SYMBOLIC
94 SYMBOL_TYPE is the type of symbol that the address references. */
95struct riscv_address_info {
96 enum riscv_address_type type;
97 rtx reg;
98 rtx offset;
99 enum riscv_symbol_type symbol_type;
2d65622f 100 int shift;
96ad6ab2
CM		 101};
102
e53b6e56 103/* Routines implemented in riscv.cc. */
09cae750
PD		 104extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx);
105extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *);
30699b99 106extern int riscv_float_const_rtx_index_for_fli (rtx);
b8506a8a 107extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool);
2d65622f 108extern bool riscv_valid_base_register_p (rtx, machine_mode, bool);
42360427
CM		 109extern enum reg_class riscv_index_reg_class ();
110extern int riscv_regno_ok_for_index_p (int);
b8506a8a 111extern int riscv_address_insns (rtx, machine_mode, bool);
09cae750
PD		 112extern int riscv_const_insns (rtx);
113extern int riscv_split_const_insns (rtx);
114extern int riscv_load_store_insns (rtx, rtx_insn *);
115extern rtx riscv_emit_move (rtx, rtx);
05302544 116extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *);
09cae750
PD		 117extern bool riscv_split_symbol_type (enum riscv_symbol_type);
118extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);
05302544 119extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode);
b8506a8a 120extern bool riscv_legitimize_move (machine_mode, rtx, rtx);
09cae750
PD		 121extern rtx riscv_subword (rtx, bool);
122extern bool riscv_split_64bit_move_p (rtx, rtx);
123extern void riscv_split_doubleword_move (rtx, rtx);
124extern const char *riscv_output_move (rtx, rtx);
8cad5b14 125extern const char *riscv_output_return ();
4abcc500
LD		 126extern void riscv_declare_function_name (FILE *, const char *, tree);
127extern void riscv_asm_output_alias (FILE *, const tree, const tree);
128extern void riscv_asm_output_external (FILE *, const tree, const char *);
3d1d3132
FG		 129extern bool
130riscv_zcmp_valid_stack_adj_bytes_p (HOST_WIDE_INT, int);
02fcaf41 131
09cae750 132#ifdef RTX_CODE
8ae83274 133extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool *invert_ptr = 0);
09cae750
PD		 134extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
135extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
99bfdb07 136extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y);
09cae750 137#endif
8e7ffe12 138extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx);
09cae750
PD		 139extern rtx riscv_legitimize_call_address (rtx);
140extern void riscv_set_return_address (rtx, rtx);
09cae750 141extern rtx riscv_return_addr (int, rtx);
3496ca4e 142extern poly_int64 riscv_initial_elimination_offset (int, int);
09cae750 143extern void riscv_expand_prologue (void);
fd1e52dc 144extern void riscv_expand_epilogue (int);
d0ebdd9f 145extern bool riscv_epilogue_uses (unsigned int);
09cae750 146extern bool riscv_can_use_return_insn (void);
6ed01e6b 147extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
88108b27 148extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
d0e0c130
KC		 149extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
150extern bool riscv_gpr_save_operation_p (rtx);
b4feb49c 151extern void riscv_reinit (void);
f556cd8b 152extern poly_uint64 riscv_regmode_natural_size (machine_mode);
7e924ba3 153extern bool riscv_v_ext_vector_mode_p (machine_mode);
12847288 154extern bool riscv_v_ext_tuple_mode_p (machine_mode);
33b153ff 155extern bool riscv_v_ext_vls_mode_p (machine_mode);
6ae5565e 156extern int riscv_get_v_regno_alignment (machine_mode);
787ac959 157extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);
f797260a
PN		 158extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *);
159extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *);
942ab49b 160extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel);
09cae750 161
e53b6e56 162/* Routines implemented in riscv-c.cc. */
09cae750 163void riscv_cpu_cpp_builtins (cpp_reader *);
7d935cdd 164void riscv_register_pragmas (void);
09cae750 165
e53b6e56 166/* Routines implemented in riscv-builtins.cc. */
09cae750 167extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *);
60bd33bc 168extern bool riscv_gimple_fold_builtin (gimple_stmt_iterator *);
b8506a8a 169extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int);
09cae750
PD		 170extern tree riscv_builtin_decl (unsigned int, bool);
171extern void riscv_init_builtins (void);
172
e53b6e56 173/* Routines implemented in riscv-common.cc. */
f908b69c 174extern std::string riscv_arch_str (bool version_p = true);
b4feb49c 175extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t);
8e966210 176
e0a5b313
KC		 177extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
178
de6320a8 179rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt);
e37bc2cf 180rtl_opt_pass * make_pass_avlprop (gcc::context *ctxt);
9243c3d1 181rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt);
de6320a8 182
32874560
CM		 183/* Routines implemented in riscv-string.c. */
184extern bool riscv_expand_block_move (rtx, rtx, rtx);
185
72eb8335
KC		 186/* Information about one CPU we know about. */
187struct riscv_cpu_info {
188 /* This CPU's canonical name. */
189 const char *name;
190
191 /* Default arch for this CPU, could be NULL if no default arch. */
192 const char *arch;
193
194 /* Which automaton to use for tuning. */
195 const char *tune;
196};
197
198extern const riscv_cpu_info *riscv_find_cpu (const char *);
199
b4feb49c 200/* Routines implemented in riscv-selftests.cc. */
201#if CHECKING_P
202namespace selftest {
3b6d44f4 203void riscv_run_selftests (void);
b4feb49c 204} // namespace selftest
205#endif
206
7d935cdd 207namespace riscv_vector {
fa144175 208#define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM)
272e119d 209#define RVV_VUNDEF(MODE) \
7caa1ae5
JZZ		 210 gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)), \
211 UNSPEC_VUNDEF)
b3176bdc 212
79ab19bc
LD		 213/* These flags describe how to pass the operands to a rvv insn pattern.
214 e.g.:
215 If a insn has this flags:
216 HAS_DEST_P | HAS_MASK_P | USE_VUNDEF_MERGE_P
217 | TU_POLICY_P | BINARY_OP_P | FRM_DYN_P
218 that means:
219 operands[0] is the dest operand
220 operands[1] is the mask operand
221 operands[2] is the merge operand
222 operands[3] and operands[4] is the two operand to do the operation.
223 operands[5] is the vl operand
224 operands[6] is the tail policy operand
225 operands[7] is the mask policy operands
226 operands[8] is the rounding mode operands
227
228 Then you can call `emit_vlmax_insn (flags, icode, ops)` to emit a insn.
229 and ops[0] is the dest operand (operands[0]), ops[1] is the mask
230 operand (operands[1]), ops[2] and ops[3] is the two
231 operands (operands[3], operands[4]) to do the operation. Other operands
232 will be created by emit_vlmax_insn according to the flags information.
233*/
234enum insn_flags : unsigned int
51fd69ec 235{
79ab19bc
LD		 236 /* flags for dest, mask, merge operands. */
237 /* Means INSN has dest operand. False for STORE insn. */
238 HAS_DEST_P = 1 << 0,
239 /* Means INSN has mask operand. */
240 HAS_MASK_P = 1 << 1,
241 /* Means using ALL_TRUES for mask operand. */
242 USE_ALL_TRUES_MASK_P = 1 << 2,
243 /* Means using ONE_TRUE for mask operand. */
244 USE_ONE_TRUE_MASK_P = 1 << 3,
245 /* Means INSN has merge operand. */
246 HAS_MERGE_P = 1 << 4,
247 /* Means using VUNDEF for merge operand. */
248 USE_VUNDEF_MERGE_P = 1 << 5,
249
250 /* flags for tail policy and mask plicy operands. */
251 /* Means the tail policy is TAIL_UNDISTURBED. */
252 TU_POLICY_P = 1 << 6,
253 /* Means the tail policy is default (return by get_prefer_tail_policy). */
254 TDEFAULT_POLICY_P = 1 << 7,
255 /* Means the mask policy is MASK_UNDISTURBED. */
256 MU_POLICY_P = 1 << 8,
257 /* Means the mask policy is default (return by get_prefer_mask_policy). */
258 MDEFAULT_POLICY_P = 1 << 9,
259
260 /* flags for the number operands to do the operation. */
261 /* Means INSN need zero operand to do the operation. e.g. vid.v */
262 NULLARY_OP_P = 1 << 10,
263 /* Means INSN need one operand to do the operation. */
264 UNARY_OP_P = 1 << 11,
265 /* Means INSN need two operands to do the operation. */
266 BINARY_OP_P = 1 << 12,
267 /* Means INSN need two operands to do the operation. */
268 TERNARY_OP_P = 1 << 13,
269
dd6e5d29
LD		 270 /* flags for get vtype mode from the index number. default from dest operand. */
271 VTYPE_MODE_FROM_OP1_P = 1 << 14,
79ab19bc
LD		 272
273 /* flags for the floating-point rounding mode. */
274 /* Means INSN has FRM operand and the value is FRM_DYN. */
275 FRM_DYN_P = 1 << 15,
8bf5636e
PL		 276
277 /* Means INSN has FRM operand and the value is FRM_RUP. */
278 FRM_RUP_P = 1 << 16,
83441e75
PL		 279
280 /* Means INSN has FRM operand and the value is FRM_RDN. */
281 FRM_RDN_P = 1 << 17,
d324984f
PL		 282
283 /* Means INSN has FRM operand and the value is FRM_RMM. */
284 FRM_RMM_P = 1 << 18,
fcbbf158
PL		 285
286 /* Means INSN has FRM operand and the value is FRM_RNE. */
287 FRM_RNE_P = 1 << 19,
51fd69ec 288};
79ab19bc
LD		 289
290enum insn_type : unsigned int
291{
292 /* some flags macros. */
293 /* For non-mask insn with tama. */
294 __NORMAL_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P
295 | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P,
296 /* For non-mask insn with ta, without mask policy operand. */
297 __NORMAL_OP_TA = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P
298 | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P,
299 /* For non-mask insn with ta, without mask operand and mask policy operand. */
300 __NORMAL_OP_TA2
301 = HAS_DEST_P | HAS_MERGE_P | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P,
302 /* For non-mask insn with ma, without tail policy operand. */
303 __NORMAL_OP_MA = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P
304 | USE_VUNDEF_MERGE_P | MDEFAULT_POLICY_P,
305 /* For mask insn with tama. */
306 __MASK_OP_TAMA = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | USE_VUNDEF_MERGE_P
307 | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P,
308 /* For mask insn with tamu. */
309 __MASK_OP_TAMU
310 = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | TDEFAULT_POLICY_P | MU_POLICY_P,
311 /* For mask insn with tuma. */
312 __MASK_OP_TUMA = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P
313 | TU_POLICY_P | MDEFAULT_POLICY_P,
314 /* For mask insn with mu. */
315 __MASK_OP_MU = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | MU_POLICY_P,
316 /* For mask insn with ta, without mask policy operand. */
317 __MASK_OP_TA = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | USE_VUNDEF_MERGE_P
318 | TDEFAULT_POLICY_P,
319
320 /* Nullary operator. e.g. vid.v */
321 NULLARY_OP = __NORMAL_OP | NULLARY_OP_P,
322
323 /* Unary operator. */
324 UNARY_OP = __NORMAL_OP | UNARY_OP_P,
325 UNARY_OP_TAMA = __MASK_OP_TAMA | UNARY_OP_P,
326 UNARY_OP_TAMU = __MASK_OP_TAMU | UNARY_OP_P,
327 UNARY_OP_FRM_DYN = UNARY_OP | FRM_DYN_P,
2cc4f58a 328 UNARY_OP_FRM_RMM = UNARY_OP | FRM_RMM_P,
51f7bfaa 329 UNARY_OP_FRM_RUP = UNARY_OP | FRM_RUP_P,
8f52040e 330 UNARY_OP_FRM_RDN = UNARY_OP | FRM_RDN_P,
85858c71
PL		 331 UNARY_OP_TAMA_FRM_DYN = UNARY_OP_TAMA | FRM_DYN_P,
332 UNARY_OP_TAMA_FRM_RUP = UNARY_OP_TAMA | FRM_RUP_P,
333 UNARY_OP_TAMA_FRM_RDN = UNARY_OP_TAMA | FRM_RDN_P,
334 UNARY_OP_TAMA_FRM_RMM = UNARY_OP_TAMA | FRM_RMM_P,
335 UNARY_OP_TAMA_FRM_RNE = UNARY_OP_TAMA | FRM_RNE_P,
e2023d2d 336 UNARY_OP_TAMU_FRM_DYN = UNARY_OP_TAMU | FRM_DYN_P,
8bf5636e 337 UNARY_OP_TAMU_FRM_RUP = UNARY_OP_TAMU | FRM_RUP_P,
83441e75 338 UNARY_OP_TAMU_FRM_RDN = UNARY_OP_TAMU | FRM_RDN_P,
d324984f 339 UNARY_OP_TAMU_FRM_RMM = UNARY_OP_TAMU | FRM_RMM_P,
fcbbf158 340 UNARY_OP_TAMU_FRM_RNE = UNARY_OP_TAMU | FRM_RNE_P,
79ab19bc
LD		 341
342 /* Binary operator. */
343 BINARY_OP = __NORMAL_OP | BINARY_OP_P,
344 BINARY_OP_TAMA = __MASK_OP_TAMA | BINARY_OP_P,
345 BINARY_OP_TAMU = __MASK_OP_TAMU | BINARY_OP_P,
346 BINARY_OP_TUMA = __MASK_OP_TUMA | BINARY_OP_P,
347 BINARY_OP_FRM_DYN = BINARY_OP | FRM_DYN_P,
348
349 /* Ternary operator. Always have real merge operand. */
350 TERNARY_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P
351 | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | TERNARY_OP_P,
352 TERNARY_OP_FRM_DYN = TERNARY_OP | FRM_DYN_P,
353
354 /* For vwmacc, no merge operand. */
355 WIDEN_TERNARY_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P
356 | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | TERNARY_OP_P,
357 WIDEN_TERNARY_OP_FRM_DYN = WIDEN_TERNARY_OP | FRM_DYN_P,
358
359 /* For vmerge, no mask operand, no mask policy operand. */
360 MERGE_OP = __NORMAL_OP_TA2 | TERNARY_OP_P,
361
362 /* For vm<compare>, no tail policy operand. */
363 COMPARE_OP = __NORMAL_OP_MA | TERNARY_OP_P,
364 COMPARE_OP_MU = __MASK_OP_MU | TERNARY_OP_P,
365
366 /* For scatter insn: no dest operand, no merge operand, no tail and mask
367 policy operands. */
368 SCATTER_OP_M = HAS_MASK_P | TERNARY_OP_P,
369
370 /* For vcpop.m, no merge operand, no tail and mask policy operands. */
371 CPOP_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | UNARY_OP_P
dd6e5d29 372 | VTYPE_MODE_FROM_OP1_P,
79ab19bc
LD		 373
374 /* For mask instrunctions, no tail and mask policy operands. */
375 UNARY_MASK_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P
376 | USE_VUNDEF_MERGE_P | UNARY_OP_P,
377 BINARY_MASK_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P
378 | USE_VUNDEF_MERGE_P | BINARY_OP_P,
379
380 /* For vcompress.vm */
381 COMPRESS_OP = __NORMAL_OP_TA2 | BINARY_OP_P,
382 /* has merge operand but use ta. */
383 COMPRESS_OP_MERGE
384 = HAS_DEST_P | HAS_MERGE_P | TDEFAULT_POLICY_P | BINARY_OP_P,
385
386 /* For vreduce, no mask policy operand. */
dd6e5d29 387 REDUCE_OP = __NORMAL_OP_TA | BINARY_OP_P | VTYPE_MODE_FROM_OP1_P,
5bc8c83d 388 REDUCE_OP_M = __MASK_OP_TA | BINARY_OP_P | VTYPE_MODE_FROM_OP1_P,
dd6e5d29 389 REDUCE_OP_FRM_DYN = REDUCE_OP | FRM_DYN_P | VTYPE_MODE_FROM_OP1_P,
79ab19bc 390 REDUCE_OP_M_FRM_DYN
dd6e5d29 391 = __MASK_OP_TA | BINARY_OP_P | FRM_DYN_P | VTYPE_MODE_FROM_OP1_P,
79ab19bc
LD		 392
393 /* For vmv.s.x/vfmv.s.f. */
394 SCALAR_MOVE_OP = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P | HAS_MERGE_P
395 | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P
396 | UNARY_OP_P,
28f16f6d
PL		 397
398 SCALAR_MOVE_MERGED_OP = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P
399 | HAS_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P
400 | UNARY_OP_P,
79ab19bc
LD		 401};
402
3b16afeb
JZZ		 403enum vlmul_type
404{
405 LMUL_1 = 0,
406 LMUL_2 = 1,
407 LMUL_4 = 2,
408 LMUL_8 = 3,
409 LMUL_RESERVED = 4,
410 LMUL_F8 = 5,
411 LMUL_F4 = 6,
412 LMUL_F2 = 7,
ec99ffab 413 NUM_LMUL = 8
3b16afeb 414};
9243c3d1 415
e99cdab8
LD		 416/* The RISC-V vsetvli pass uses "known vlmax" operations for optimization.
417 Whether or not an instruction actually is a vlmax operation is not
418 recognizable from the length operand alone but the avl_type operand
419 is used instead. In general, there are two cases:
420
421 - Emit a vlmax operation by calling emit_vlmax_insn[_lra]. Here we emit
422 a vsetvli with vlmax configuration and set the avl_type to VLMAX for
423 VLA modes or VLS for VLS modes.
424 - Emit an operation that uses the existing (last-set) length and
425 set the avl_type to NONVLMAX.
426
427 Sometimes we also need to set the VLMAX or VLS avl_type to an operation that
428 already uses a given length register. This can happen during or after
429 register allocation when we are not allowed to create a new register.
430 For that case we also allow to set the avl_type to VLMAX or VLS.
431*/
9243c3d1
JZZ		 432enum avl_type
433{
e99cdab8
LD		 434 NONVLMAX = 0,
435 VLMAX = 1,
436 VLS = 2,
9243c3d1 437};
7d935cdd 438/* Routines implemented in riscv-vector-builtins.cc. */
3b6d44f4
JZZ		 439void init_builtins (void);
440const char *mangle_builtin_type (const_tree);
509c10a6 441tree lookup_vector_type_attribute (const_tree);
94a4b932 442bool builtin_type_p (const_tree);
7d935cdd 443#ifdef GCC_TARGET_H
3b6d44f4 444bool verify_type_context (location_t, type_context_kind, const_tree, bool);
631e86b7
JZ		 445bool expand_vec_perm_const (machine_mode, machine_mode, rtx, rtx, rtx,
446 const vec_perm_indices &);
7d935cdd 447#endif
3b6d44f4
JZZ		 448void handle_pragma_vector (void);
449tree builtin_decl (unsigned, bool);
60bd33bc 450gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *);
3b6d44f4 451rtx expand_builtin (unsigned int, tree, rtx);
7caa1ae5
JZZ		 452bool check_builtin_call (location_t, vec<location_t>, unsigned int,
453 tree, unsigned int, tree *);
3b6d44f4 454bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
f416a3fd 455bool legitimize_move (rtx, rtx *);
cd0c433e 456void emit_vlmax_vsetvl (machine_mode, rtx);
40fc8e3d 457void emit_hard_vlmax_vsetvl (machine_mode, rtx);
79ab19bc
LD		 458void emit_vlmax_insn (unsigned, unsigned, rtx *);
459void emit_nonvlmax_insn (unsigned, unsigned, rtx *, rtx);
460void emit_vlmax_insn_lra (unsigned, unsigned, rtx *, rtx);
3b6d44f4 461enum vlmul_type get_vlmul (machine_mode);
b3176bdc 462rtx get_vlmax_rtx (machine_mode);
3b6d44f4 463unsigned int get_ratio (machine_mode);
12847288
JZZ		 464unsigned int get_nf (machine_mode);
465machine_mode get_subpart_mode (machine_mode);
3b6d44f4
JZZ		 466int get_ta (rtx);
467int get_ma (rtx);
468int get_avl_type (rtx);
469unsigned int calculate_ratio (unsigned int, enum vlmul_type);
f556cd8b
JZZ		 470enum tail_policy
471{
472 TAIL_UNDISTURBED = 0,
473 TAIL_AGNOSTIC = 1,
9243c3d1 474 TAIL_ANY = 2,
f556cd8b
JZZ		 475};
476
477enum mask_policy
478{
479 MASK_UNDISTURBED = 0,
480 MASK_AGNOSTIC = 1,
9243c3d1 481 MASK_ANY = 2,
f556cd8b 482};
8390a2af 483
e69d050f
LD		 484/* Return true if VALUE is agnostic or any policy. */
485#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1))
486
9243c3d1
JZZ		 487enum tail_policy get_prefer_tail_policy ();
488enum mask_policy get_prefer_mask_policy ();
a143c3f7 489rtx get_avl_type_rtx (enum avl_type);
6c9bcb6c 490opt_machine_mode get_vector_mode (scalar_mode, poly_uint64);
12847288 491opt_machine_mode get_tuple_mode (machine_mode, unsigned int);
3b6d44f4
JZZ		 492bool simm5_p (rtx);
493bool neg_simm5_p (rtx);
a035d133 494#ifdef RTX_CODE
3b6d44f4 495bool has_vi_variant_p (rtx_code, rtx);
e0600a02
JZ		 496void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
497bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
4d1c8b04
LD		 498void expand_cond_len_unop (unsigned, rtx *);
499void expand_cond_len_binop (unsigned, rtx *);
e6413b5d 500void expand_reduction (unsigned, unsigned, rtx *, rtx);
8bf5636e 501void expand_vec_ceil (rtx, rtx, machine_mode, machine_mode);
83441e75 502void expand_vec_floor (rtx, rtx, machine_mode, machine_mode);
e2023d2d 503void expand_vec_nearbyint (rtx, rtx, machine_mode, machine_mode);
e4cf5f54 504void expand_vec_rint (rtx, rtx, machine_mode, machine_mode);
d324984f 505void expand_vec_round (rtx, rtx, machine_mode, machine_mode);
1c4ca595 506void expand_vec_trunc (rtx, rtx, machine_mode, machine_mode);
fcbbf158 507void expand_vec_roundeven (rtx, rtx, machine_mode, machine_mode);
d1e55666 508void expand_vec_lrint (rtx, rtx, machine_mode, machine_mode);
2cc4f58a 509void expand_vec_lround (rtx, rtx, machine_mode, machine_mode);
51f7bfaa 510void expand_vec_lceil (rtx, rtx, machine_mode, machine_mode);
8f52040e 511void expand_vec_lfloor (rtx, rtx, machine_mode, machine_mode);
a035d133 512#endif
51fd69ec 513bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode,
eb1cdb3e 514 bool, void (*)(rtx *, rtx), enum avl_type);
ec99ffab 515rtx gen_scalar_move_mask (machine_mode);
9c032218 516rtx gen_no_side_effects_vsetvl_rtx (machine_mode, rtx, rtx);
1bff101b
JZZ		 517
518/* RVV vector register sizes.
519 TODO: Currently, we only add RVV_32/RVV_64/RVV_128, we may need to
520 support other values in the future. */
521enum vlen_enum
522{
523 RVV_32 = 32,
524 RVV_64 = 64,
525 RVV_65536 = 65536
526};
527bool slide1_sew64_helper (int, machine_mode, machine_mode,
528 machine_mode, rtx *);
db4f7a9b 529rtx gen_avl_for_scalar_move (rtx);
51fd69ec 530void expand_tuple_move (rtx *);
9464e72b 531bool expand_block_move (rtx, rtx, rtx);
2d76f2b4 532machine_mode preferred_simd_mode (scalar_mode);
1349f530 533machine_mode get_mask_mode (machine_mode);
003f388c 534void expand_vec_series (rtx, rtx, rtx);
1c1a9d8e 535void expand_vec_init (rtx, rtx);
2418cdfc 536void expand_vec_perm (rtx, rtx, rtx, rtx);
55dcf277 537void expand_select_vl (rtx *);
d42d199e 538void expand_load_store (rtx *, bool);
f048af2a 539void expand_gather_scatter (rtx *, bool);
0d2673e9 540void expand_cond_len_ternop (unsigned, rtx *);
95d2ce05 541void prepare_ternary_operands (rtx *);
fe578886 542void expand_lanes_load_store (rtx *, bool);
e7545cad 543void expand_fold_extract_last (rtx *);
8a87ba0b
JZ		 544void expand_cond_unop (unsigned, rtx *);
545void expand_cond_binop (unsigned, rtx *);
546void expand_cond_ternop (unsigned, rtx *);
82bbbb73 547void expand_popcount (rtx *);
9c032218 548void expand_rawmemchr (machine_mode, rtx, rtx, rtx);
47ffabaf 549
5ed88078 550/* Rounding mode bitfield for fixed point VXRM. */
47ffabaf 551enum fixed_point_rounding_mode
5ed88078
JZ		 552{
553 VXRM_RNU,
554 VXRM_RNE,
555 VXRM_RDN,
556 VXRM_ROD
557};
47ffabaf 558
7f4644f8
PL		 559/* Rounding mode bitfield for floating point FRM. The value of enum comes
560 from the below link.
561 https://github.com/riscv/riscv-isa-manual/blob/main/src/f-st-ext.adoc#floating-point-control-and-status-register
562 */
47ffabaf 563enum floating_point_rounding_mode
8cd140d3 564{
7f4644f8
PL		 565 FRM_RNE = 0, /* Aka 0b000. */
566 FRM_RTZ = 1, /* Aka 0b001. */
567 FRM_RDN = 2, /* Aka 0b010. */
568 FRM_RUP = 3, /* Aka 0b011. */
569 FRM_RMM = 4, /* Aka 0b100. */
570 FRM_DYN = 7, /* Aka 0b111. */
4d1e97f5
PL		 571 FRM_STATIC_MIN = FRM_RNE,
572 FRM_STATIC_MAX = FRM_RMM,
4cede0de
PL		 573 FRM_DYN_EXIT = 8,
574 FRM_DYN_CALL = 9,
575 FRM_NONE = 10,
8cd140d3 576};
25907509 577
4cede0de 578enum floating_point_rounding_mode get_frm_mode (rtx);
25907509
RD		 579opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
580 poly_uint64);
581unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
d05aac04
JZ		 582bool cmp_lmul_le_one (machine_mode);
583bool cmp_lmul_gt_one (machine_mode);
f6c5e247 584bool gather_scatter_valid_offset_mode_p (machine_mode);
66c26e5c 585bool vls_mode_valid_p (machine_mode);
5e714992 586bool vlmax_avl_type_p (rtx_insn *);
8064e7e2
JZ		 587bool has_vl_op (rtx_insn *);
588bool tail_agnostic_p (rtx_insn *);
589void validate_change_or_fail (rtx, rtx *, rtx, bool);
590bool nonvlmax_avl_type_p (rtx_insn *);
591bool vlmax_avl_p (rtx);
592uint8_t get_sew (rtx_insn *);
593enum vlmul_type get_vlmul (rtx_insn *);
594int count_regno_occurrences (rtx_insn *, unsigned int);
7d935cdd
JZZ		 595}
596
cbd50570
JZZ		 597/* We classify builtin types into two classes:
598 1. General builtin class which is defined in riscv_builtins.
599 2. Vector builtin class which is a special builtin architecture
600 that implement intrinsic short into "pragma". */
601enum riscv_builtin_class
602{
603 RISCV_BUILTIN_GENERAL,
604 RISCV_BUILTIN_VECTOR
605};
606
607const unsigned int RISCV_BUILTIN_SHIFT = 1;
608
609/* Mask that selects the riscv_builtin_class part of a function code. */
610const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1;
611
df48285b 612/* Routines implemented in riscv-string.cc. */
949f1ccf 613extern bool riscv_expand_strcmp (rtx, rtx, rtx, rtx, rtx);
df48285b
CM		 614extern bool riscv_expand_strlen (rtx, rtx, rtx, rtx);
615
02fcaf41
CM		 616/* Routines implemented in thead.cc. */
617extern bool th_mempair_operands_p (rtx[4], bool, machine_mode);
618extern void th_mempair_order_operands (rtx[4], bool, machine_mode);
619extern void th_mempair_prepare_save_restore_operands (rtx[4], bool,
620 machine_mode,
621 int, HOST_WIDE_INT,
622 int, HOST_WIDE_INT);
623extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode);
624#ifdef RTX_CODE
625extern const char*
626th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE);
2d65622f
CM		 627extern bool th_memidx_legitimate_modify_p (rtx);
628extern bool th_memidx_legitimate_modify_p (rtx, bool);
629extern bool th_memidx_legitimate_index_p (rtx);
630extern bool th_memidx_legitimate_index_p (rtx, bool);
631extern bool th_classify_address (struct riscv_address_info *,
632 rtx, machine_mode, bool);
633extern const char *th_output_move (rtx, rtx);
634extern bool th_print_operand_address (FILE *, machine_mode, rtx);
02fcaf41
CM		 635#endif
636
065be0ff 637extern bool riscv_use_divmod_expander (void);
1d4d302a
YW		 638void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
639
09cae750 640#endif /* ! GCC_RISCV_PROTOS_H */
Mirror of https://gcc.gnu.org/git/gcc.git