]>
Commit | Line | Data |
---|---|---|
09cae750 | 1 | /* Definition of RISC-V target for GNU compiler. |
83ffe9cd | 2 | Copyright (C) 2011-2023 Free Software Foundation, Inc. |
09cae750 PD |
3 | Contributed by Andrew Waterman (andrew@sifive.com). |
4 | Based on MIPS target for GNU compiler. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef GCC_RISCV_PROTOS_H | |
23 | #define GCC_RISCV_PROTOS_H | |
24 | ||
942ab49b PN |
25 | #include "memmodel.h" |
26 | ||
09cae750 PD |
27 | /* Symbol types we understand. The order of this list must match that of |
28 | the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ | |
29 | enum riscv_symbol_type { | |
30 | SYMBOL_ABSOLUTE, | |
31 | SYMBOL_PCREL, | |
32 | SYMBOL_GOT_DISP, | |
33 | SYMBOL_TLS, | |
34 | SYMBOL_TLS_LE, | |
35 | SYMBOL_TLS_IE, | |
36 | SYMBOL_TLS_GD | |
37 | }; | |
38 | #define NUM_SYMBOL_TYPES (SYMBOL_TLS_GD + 1) | |
39 | ||
96ad6ab2 CM |
40 | /* Classifies an address. |
41 | ||
42 | ADDRESS_REG | |
43 | A natural register + offset address. The register satisfies | |
44 | riscv_valid_base_register_p and the offset is a const_arith_operand. | |
45 | ||
46 | ADDRESS_LO_SUM | |
47 | A LO_SUM rtx. The first operand is a valid base register and | |
48 | the second operand is a symbolic address. | |
49 | ||
50 | ADDRESS_CONST_INT | |
51 | A signed 16-bit constant address. | |
52 | ||
53 | ADDRESS_SYMBOLIC: | |
54 | A constant symbolic address. */ | |
55 | enum riscv_address_type { | |
56 | ADDRESS_REG, | |
57 | ADDRESS_LO_SUM, | |
58 | ADDRESS_CONST_INT, | |
59 | ADDRESS_SYMBOLIC | |
60 | }; | |
61 | ||
62 | /* Information about an address described by riscv_address_type. | |
63 | ||
64 | ADDRESS_CONST_INT | |
65 | No fields are used. | |
66 | ||
67 | ADDRESS_REG | |
68 | REG is the base register and OFFSET is the constant offset. | |
69 | ||
70 | ADDRESS_LO_SUM | |
71 | REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE | |
72 | is the type of symbol it references. | |
73 | ||
74 | ADDRESS_SYMBOLIC | |
75 | SYMBOL_TYPE is the type of symbol that the address references. */ | |
76 | struct riscv_address_info { | |
77 | enum riscv_address_type type; | |
78 | rtx reg; | |
79 | rtx offset; | |
80 | enum riscv_symbol_type symbol_type; | |
81 | }; | |
82 | ||
e53b6e56 | 83 | /* Routines implemented in riscv.cc. */ |
09cae750 PD |
84 | extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); |
85 | extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); | |
30699b99 | 86 | extern int riscv_float_const_rtx_index_for_fli (rtx); |
b8506a8a | 87 | extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool); |
42360427 CM |
88 | extern enum reg_class riscv_index_reg_class (); |
89 | extern int riscv_regno_ok_for_index_p (int); | |
b8506a8a | 90 | extern int riscv_address_insns (rtx, machine_mode, bool); |
09cae750 PD |
91 | extern int riscv_const_insns (rtx); |
92 | extern int riscv_split_const_insns (rtx); | |
93 | extern int riscv_load_store_insns (rtx, rtx_insn *); | |
94 | extern rtx riscv_emit_move (rtx, rtx); | |
05302544 | 95 | extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *); |
09cae750 PD |
96 | extern bool riscv_split_symbol_type (enum riscv_symbol_type); |
97 | extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type); | |
05302544 | 98 | extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode); |
b8506a8a | 99 | extern bool riscv_legitimize_move (machine_mode, rtx, rtx); |
09cae750 PD |
100 | extern rtx riscv_subword (rtx, bool); |
101 | extern bool riscv_split_64bit_move_p (rtx, rtx); | |
102 | extern void riscv_split_doubleword_move (rtx, rtx); | |
103 | extern const char *riscv_output_move (rtx, rtx); | |
8cad5b14 | 104 | extern const char *riscv_output_return (); |
4abcc500 LD |
105 | extern void riscv_declare_function_name (FILE *, const char *, tree); |
106 | extern void riscv_asm_output_alias (FILE *, const tree, const tree); | |
107 | extern void riscv_asm_output_external (FILE *, const tree, const char *); | |
3d1d3132 FG |
108 | extern bool |
109 | riscv_zcmp_valid_stack_adj_bytes_p (HOST_WIDE_INT, int); | |
02fcaf41 | 110 | |
09cae750 | 111 | #ifdef RTX_CODE |
8ae83274 | 112 | extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool *invert_ptr = 0); |
09cae750 PD |
113 | extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx); |
114 | extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx); | |
99bfdb07 | 115 | extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y); |
09cae750 | 116 | #endif |
8e7ffe12 | 117 | extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx); |
09cae750 PD |
118 | extern rtx riscv_legitimize_call_address (rtx); |
119 | extern void riscv_set_return_address (rtx, rtx); | |
120 | extern bool riscv_expand_block_move (rtx, rtx, rtx); | |
121 | extern rtx riscv_return_addr (int, rtx); | |
3496ca4e | 122 | extern poly_int64 riscv_initial_elimination_offset (int, int); |
09cae750 | 123 | extern void riscv_expand_prologue (void); |
fd1e52dc | 124 | extern void riscv_expand_epilogue (int); |
d0ebdd9f | 125 | extern bool riscv_epilogue_uses (unsigned int); |
09cae750 | 126 | extern bool riscv_can_use_return_insn (void); |
6ed01e6b | 127 | extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode); |
6ed01e6b | 128 | extern bool riscv_expand_block_move (rtx, rtx, rtx); |
88108b27 | 129 | extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *); |
d0e0c130 KC |
130 | extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *); |
131 | extern bool riscv_gpr_save_operation_p (rtx); | |
b4feb49c | 132 | extern void riscv_reinit (void); |
f556cd8b | 133 | extern poly_uint64 riscv_regmode_natural_size (machine_mode); |
7e924ba3 | 134 | extern bool riscv_v_ext_vector_mode_p (machine_mode); |
12847288 | 135 | extern bool riscv_v_ext_tuple_mode_p (machine_mode); |
33b153ff | 136 | extern bool riscv_v_ext_vls_mode_p (machine_mode); |
6ae5565e | 137 | extern int riscv_get_v_regno_alignment (machine_mode); |
787ac959 | 138 | extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); |
f797260a PN |
139 | extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); |
140 | extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); | |
942ab49b | 141 | extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); |
09cae750 | 142 | |
e53b6e56 | 143 | /* Routines implemented in riscv-c.cc. */ |
09cae750 | 144 | void riscv_cpu_cpp_builtins (cpp_reader *); |
7d935cdd | 145 | void riscv_register_pragmas (void); |
09cae750 | 146 | |
e53b6e56 | 147 | /* Routines implemented in riscv-builtins.cc. */ |
09cae750 | 148 | extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *); |
60bd33bc | 149 | extern bool riscv_gimple_fold_builtin (gimple_stmt_iterator *); |
b8506a8a | 150 | extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int); |
09cae750 PD |
151 | extern tree riscv_builtin_decl (unsigned int, bool); |
152 | extern void riscv_init_builtins (void); | |
153 | ||
e53b6e56 | 154 | /* Routines implemented in riscv-common.cc. */ |
f908b69c | 155 | extern std::string riscv_arch_str (bool version_p = true); |
b4feb49c | 156 | extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t); |
8e966210 | 157 | |
e0a5b313 KC |
158 | extern bool riscv_hard_regno_rename_ok (unsigned, unsigned); |
159 | ||
de6320a8 | 160 | rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt); |
9243c3d1 | 161 | rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt); |
de6320a8 | 162 | |
72eb8335 KC |
163 | /* Information about one CPU we know about. */ |
164 | struct riscv_cpu_info { | |
165 | /* This CPU's canonical name. */ | |
166 | const char *name; | |
167 | ||
168 | /* Default arch for this CPU, could be NULL if no default arch. */ | |
169 | const char *arch; | |
170 | ||
171 | /* Which automaton to use for tuning. */ | |
172 | const char *tune; | |
173 | }; | |
174 | ||
175 | extern const riscv_cpu_info *riscv_find_cpu (const char *); | |
176 | ||
b4feb49c | 177 | /* Routines implemented in riscv-selftests.cc. */ |
178 | #if CHECKING_P | |
179 | namespace selftest { | |
3b6d44f4 | 180 | void riscv_run_selftests (void); |
b4feb49c | 181 | } // namespace selftest |
182 | #endif | |
183 | ||
7d935cdd | 184 | namespace riscv_vector { |
fa144175 | 185 | #define RVV_VLMAX gen_rtx_REG (Pmode, X0_REGNUM) |
272e119d | 186 | #define RVV_VUNDEF(MODE) \ |
7caa1ae5 JZZ |
187 | gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)), \ |
188 | UNSPEC_VUNDEF) | |
b3176bdc | 189 | |
79ab19bc LD |
190 | /* These flags describe how to pass the operands to a rvv insn pattern. |
191 | e.g.: | |
192 | If a insn has this flags: | |
193 | HAS_DEST_P | HAS_MASK_P | USE_VUNDEF_MERGE_P | |
194 | | TU_POLICY_P | BINARY_OP_P | FRM_DYN_P | |
195 | that means: | |
196 | operands[0] is the dest operand | |
197 | operands[1] is the mask operand | |
198 | operands[2] is the merge operand | |
199 | operands[3] and operands[4] is the two operand to do the operation. | |
200 | operands[5] is the vl operand | |
201 | operands[6] is the tail policy operand | |
202 | operands[7] is the mask policy operands | |
203 | operands[8] is the rounding mode operands | |
204 | ||
205 | Then you can call `emit_vlmax_insn (flags, icode, ops)` to emit a insn. | |
206 | and ops[0] is the dest operand (operands[0]), ops[1] is the mask | |
207 | operand (operands[1]), ops[2] and ops[3] is the two | |
208 | operands (operands[3], operands[4]) to do the operation. Other operands | |
209 | will be created by emit_vlmax_insn according to the flags information. | |
210 | */ | |
211 | enum insn_flags : unsigned int | |
51fd69ec | 212 | { |
79ab19bc LD |
213 | /* flags for dest, mask, merge operands. */ |
214 | /* Means INSN has dest operand. False for STORE insn. */ | |
215 | HAS_DEST_P = 1 << 0, | |
216 | /* Means INSN has mask operand. */ | |
217 | HAS_MASK_P = 1 << 1, | |
218 | /* Means using ALL_TRUES for mask operand. */ | |
219 | USE_ALL_TRUES_MASK_P = 1 << 2, | |
220 | /* Means using ONE_TRUE for mask operand. */ | |
221 | USE_ONE_TRUE_MASK_P = 1 << 3, | |
222 | /* Means INSN has merge operand. */ | |
223 | HAS_MERGE_P = 1 << 4, | |
224 | /* Means using VUNDEF for merge operand. */ | |
225 | USE_VUNDEF_MERGE_P = 1 << 5, | |
226 | ||
227 | /* flags for tail policy and mask plicy operands. */ | |
228 | /* Means the tail policy is TAIL_UNDISTURBED. */ | |
229 | TU_POLICY_P = 1 << 6, | |
230 | /* Means the tail policy is default (return by get_prefer_tail_policy). */ | |
231 | TDEFAULT_POLICY_P = 1 << 7, | |
232 | /* Means the mask policy is MASK_UNDISTURBED. */ | |
233 | MU_POLICY_P = 1 << 8, | |
234 | /* Means the mask policy is default (return by get_prefer_mask_policy). */ | |
235 | MDEFAULT_POLICY_P = 1 << 9, | |
236 | ||
237 | /* flags for the number operands to do the operation. */ | |
238 | /* Means INSN need zero operand to do the operation. e.g. vid.v */ | |
239 | NULLARY_OP_P = 1 << 10, | |
240 | /* Means INSN need one operand to do the operation. */ | |
241 | UNARY_OP_P = 1 << 11, | |
242 | /* Means INSN need two operands to do the operation. */ | |
243 | BINARY_OP_P = 1 << 12, | |
244 | /* Means INSN need two operands to do the operation. */ | |
245 | TERNARY_OP_P = 1 << 13, | |
246 | ||
dd6e5d29 LD |
247 | /* flags for get vtype mode from the index number. default from dest operand. */ |
248 | VTYPE_MODE_FROM_OP1_P = 1 << 14, | |
79ab19bc LD |
249 | |
250 | /* flags for the floating-point rounding mode. */ | |
251 | /* Means INSN has FRM operand and the value is FRM_DYN. */ | |
252 | FRM_DYN_P = 1 << 15, | |
8bf5636e PL |
253 | |
254 | /* Means INSN has FRM operand and the value is FRM_RUP. */ | |
255 | FRM_RUP_P = 1 << 16, | |
83441e75 PL |
256 | |
257 | /* Means INSN has FRM operand and the value is FRM_RDN. */ | |
258 | FRM_RDN_P = 1 << 17, | |
51fd69ec | 259 | }; |
79ab19bc LD |
260 | |
261 | enum insn_type : unsigned int | |
262 | { | |
263 | /* some flags macros. */ | |
264 | /* For non-mask insn with tama. */ | |
265 | __NORMAL_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
266 | | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P, | |
267 | /* For non-mask insn with ta, without mask policy operand. */ | |
268 | __NORMAL_OP_TA = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
269 | | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P, | |
270 | /* For non-mask insn with ta, without mask operand and mask policy operand. */ | |
271 | __NORMAL_OP_TA2 | |
272 | = HAS_DEST_P | HAS_MERGE_P | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P, | |
273 | /* For non-mask insn with ma, without tail policy operand. */ | |
274 | __NORMAL_OP_MA = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
275 | | USE_VUNDEF_MERGE_P | MDEFAULT_POLICY_P, | |
276 | /* For mask insn with tama. */ | |
277 | __MASK_OP_TAMA = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | USE_VUNDEF_MERGE_P | |
278 | | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P, | |
279 | /* For mask insn with tamu. */ | |
280 | __MASK_OP_TAMU | |
281 | = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | TDEFAULT_POLICY_P | MU_POLICY_P, | |
282 | /* For mask insn with tuma. */ | |
283 | __MASK_OP_TUMA = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
284 | | TU_POLICY_P | MDEFAULT_POLICY_P, | |
285 | /* For mask insn with mu. */ | |
286 | __MASK_OP_MU = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | MU_POLICY_P, | |
287 | /* For mask insn with ta, without mask policy operand. */ | |
288 | __MASK_OP_TA = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | USE_VUNDEF_MERGE_P | |
289 | | TDEFAULT_POLICY_P, | |
290 | ||
291 | /* Nullary operator. e.g. vid.v */ | |
292 | NULLARY_OP = __NORMAL_OP | NULLARY_OP_P, | |
293 | ||
294 | /* Unary operator. */ | |
295 | UNARY_OP = __NORMAL_OP | UNARY_OP_P, | |
296 | UNARY_OP_TAMA = __MASK_OP_TAMA | UNARY_OP_P, | |
297 | UNARY_OP_TAMU = __MASK_OP_TAMU | UNARY_OP_P, | |
298 | UNARY_OP_FRM_DYN = UNARY_OP | FRM_DYN_P, | |
e2023d2d | 299 | UNARY_OP_TAMU_FRM_DYN = UNARY_OP_TAMU | FRM_DYN_P, |
8bf5636e | 300 | UNARY_OP_TAMU_FRM_RUP = UNARY_OP_TAMU | FRM_RUP_P, |
83441e75 | 301 | UNARY_OP_TAMU_FRM_RDN = UNARY_OP_TAMU | FRM_RDN_P, |
79ab19bc LD |
302 | |
303 | /* Binary operator. */ | |
304 | BINARY_OP = __NORMAL_OP | BINARY_OP_P, | |
305 | BINARY_OP_TAMA = __MASK_OP_TAMA | BINARY_OP_P, | |
306 | BINARY_OP_TAMU = __MASK_OP_TAMU | BINARY_OP_P, | |
307 | BINARY_OP_TUMA = __MASK_OP_TUMA | BINARY_OP_P, | |
308 | BINARY_OP_FRM_DYN = BINARY_OP | FRM_DYN_P, | |
309 | ||
310 | /* Ternary operator. Always have real merge operand. */ | |
311 | TERNARY_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
312 | | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | TERNARY_OP_P, | |
313 | TERNARY_OP_FRM_DYN = TERNARY_OP | FRM_DYN_P, | |
314 | ||
315 | /* For vwmacc, no merge operand. */ | |
316 | WIDEN_TERNARY_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | |
317 | | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | TERNARY_OP_P, | |
318 | WIDEN_TERNARY_OP_FRM_DYN = WIDEN_TERNARY_OP | FRM_DYN_P, | |
319 | ||
320 | /* For vmerge, no mask operand, no mask policy operand. */ | |
321 | MERGE_OP = __NORMAL_OP_TA2 | TERNARY_OP_P, | |
322 | ||
323 | /* For vm<compare>, no tail policy operand. */ | |
324 | COMPARE_OP = __NORMAL_OP_MA | TERNARY_OP_P, | |
325 | COMPARE_OP_MU = __MASK_OP_MU | TERNARY_OP_P, | |
326 | ||
327 | /* For scatter insn: no dest operand, no merge operand, no tail and mask | |
328 | policy operands. */ | |
329 | SCATTER_OP_M = HAS_MASK_P | TERNARY_OP_P, | |
330 | ||
331 | /* For vcpop.m, no merge operand, no tail and mask policy operands. */ | |
332 | CPOP_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | UNARY_OP_P | |
dd6e5d29 | 333 | | VTYPE_MODE_FROM_OP1_P, |
79ab19bc LD |
334 | |
335 | /* For mask instrunctions, no tail and mask policy operands. */ | |
336 | UNARY_MASK_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
337 | | USE_VUNDEF_MERGE_P | UNARY_OP_P, | |
338 | BINARY_MASK_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
339 | | USE_VUNDEF_MERGE_P | BINARY_OP_P, | |
340 | ||
341 | /* For vcompress.vm */ | |
342 | COMPRESS_OP = __NORMAL_OP_TA2 | BINARY_OP_P, | |
343 | /* has merge operand but use ta. */ | |
344 | COMPRESS_OP_MERGE | |
345 | = HAS_DEST_P | HAS_MERGE_P | TDEFAULT_POLICY_P | BINARY_OP_P, | |
346 | ||
347 | /* For vreduce, no mask policy operand. */ | |
dd6e5d29 | 348 | REDUCE_OP = __NORMAL_OP_TA | BINARY_OP_P | VTYPE_MODE_FROM_OP1_P, |
5bc8c83d | 349 | REDUCE_OP_M = __MASK_OP_TA | BINARY_OP_P | VTYPE_MODE_FROM_OP1_P, |
dd6e5d29 | 350 | REDUCE_OP_FRM_DYN = REDUCE_OP | FRM_DYN_P | VTYPE_MODE_FROM_OP1_P, |
79ab19bc | 351 | REDUCE_OP_M_FRM_DYN |
dd6e5d29 | 352 | = __MASK_OP_TA | BINARY_OP_P | FRM_DYN_P | VTYPE_MODE_FROM_OP1_P, |
79ab19bc LD |
353 | |
354 | /* For vmv.s.x/vfmv.s.f. */ | |
355 | SCALAR_MOVE_OP = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P | HAS_MERGE_P | |
356 | | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | |
357 | | UNARY_OP_P, | |
28f16f6d PL |
358 | |
359 | SCALAR_MOVE_MERGED_OP = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P | |
360 | | HAS_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | |
361 | | UNARY_OP_P, | |
79ab19bc LD |
362 | }; |
363 | ||
3b16afeb JZZ |
364 | enum vlmul_type |
365 | { | |
366 | LMUL_1 = 0, | |
367 | LMUL_2 = 1, | |
368 | LMUL_4 = 2, | |
369 | LMUL_8 = 3, | |
370 | LMUL_RESERVED = 4, | |
371 | LMUL_F8 = 5, | |
372 | LMUL_F4 = 6, | |
373 | LMUL_F2 = 7, | |
ec99ffab | 374 | NUM_LMUL = 8 |
3b16afeb | 375 | }; |
9243c3d1 | 376 | |
e99cdab8 LD |
377 | /* The RISC-V vsetvli pass uses "known vlmax" operations for optimization. |
378 | Whether or not an instruction actually is a vlmax operation is not | |
379 | recognizable from the length operand alone but the avl_type operand | |
380 | is used instead. In general, there are two cases: | |
381 | ||
382 | - Emit a vlmax operation by calling emit_vlmax_insn[_lra]. Here we emit | |
383 | a vsetvli with vlmax configuration and set the avl_type to VLMAX for | |
384 | VLA modes or VLS for VLS modes. | |
385 | - Emit an operation that uses the existing (last-set) length and | |
386 | set the avl_type to NONVLMAX. | |
387 | ||
388 | Sometimes we also need to set the VLMAX or VLS avl_type to an operation that | |
389 | already uses a given length register. This can happen during or after | |
390 | register allocation when we are not allowed to create a new register. | |
391 | For that case we also allow to set the avl_type to VLMAX or VLS. | |
392 | */ | |
9243c3d1 JZZ |
393 | enum avl_type |
394 | { | |
e99cdab8 LD |
395 | NONVLMAX = 0, |
396 | VLMAX = 1, | |
397 | VLS = 2, | |
9243c3d1 | 398 | }; |
7d935cdd | 399 | /* Routines implemented in riscv-vector-builtins.cc. */ |
3b6d44f4 JZZ |
400 | void init_builtins (void); |
401 | const char *mangle_builtin_type (const_tree); | |
509c10a6 | 402 | tree lookup_vector_type_attribute (const_tree); |
94a4b932 | 403 | bool builtin_type_p (const_tree); |
7d935cdd | 404 | #ifdef GCC_TARGET_H |
3b6d44f4 | 405 | bool verify_type_context (location_t, type_context_kind, const_tree, bool); |
631e86b7 JZ |
406 | bool expand_vec_perm_const (machine_mode, machine_mode, rtx, rtx, rtx, |
407 | const vec_perm_indices &); | |
7d935cdd | 408 | #endif |
3b6d44f4 JZZ |
409 | void handle_pragma_vector (void); |
410 | tree builtin_decl (unsigned, bool); | |
60bd33bc | 411 | gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *); |
3b6d44f4 | 412 | rtx expand_builtin (unsigned int, tree, rtx); |
7caa1ae5 JZZ |
413 | bool check_builtin_call (location_t, vec<location_t>, unsigned int, |
414 | tree, unsigned int, tree *); | |
3b6d44f4 | 415 | bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
51fd69ec | 416 | bool legitimize_move (rtx, rtx); |
cd0c433e | 417 | void emit_vlmax_vsetvl (machine_mode, rtx); |
40fc8e3d | 418 | void emit_hard_vlmax_vsetvl (machine_mode, rtx); |
79ab19bc LD |
419 | void emit_vlmax_insn (unsigned, unsigned, rtx *); |
420 | void emit_nonvlmax_insn (unsigned, unsigned, rtx *, rtx); | |
421 | void emit_vlmax_insn_lra (unsigned, unsigned, rtx *, rtx); | |
3b6d44f4 | 422 | enum vlmul_type get_vlmul (machine_mode); |
b3176bdc | 423 | rtx get_vlmax_rtx (machine_mode); |
3b6d44f4 | 424 | unsigned int get_ratio (machine_mode); |
12847288 JZZ |
425 | unsigned int get_nf (machine_mode); |
426 | machine_mode get_subpart_mode (machine_mode); | |
3b6d44f4 JZZ |
427 | int get_ta (rtx); |
428 | int get_ma (rtx); | |
429 | int get_avl_type (rtx); | |
430 | unsigned int calculate_ratio (unsigned int, enum vlmul_type); | |
f556cd8b JZZ |
431 | enum tail_policy |
432 | { | |
433 | TAIL_UNDISTURBED = 0, | |
434 | TAIL_AGNOSTIC = 1, | |
9243c3d1 | 435 | TAIL_ANY = 2, |
f556cd8b JZZ |
436 | }; |
437 | ||
438 | enum mask_policy | |
439 | { | |
440 | MASK_UNDISTURBED = 0, | |
441 | MASK_AGNOSTIC = 1, | |
9243c3d1 | 442 | MASK_ANY = 2, |
f556cd8b | 443 | }; |
8390a2af | 444 | |
e69d050f LD |
445 | /* Return true if VALUE is agnostic or any policy. */ |
446 | #define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1)) | |
447 | ||
9243c3d1 JZZ |
448 | enum tail_policy get_prefer_tail_policy (); |
449 | enum mask_policy get_prefer_mask_policy (); | |
a143c3f7 | 450 | rtx get_avl_type_rtx (enum avl_type); |
6c9bcb6c | 451 | opt_machine_mode get_vector_mode (scalar_mode, poly_uint64); |
12847288 | 452 | opt_machine_mode get_tuple_mode (machine_mode, unsigned int); |
3b6d44f4 JZZ |
453 | bool simm5_p (rtx); |
454 | bool neg_simm5_p (rtx); | |
a035d133 | 455 | #ifdef RTX_CODE |
3b6d44f4 | 456 | bool has_vi_variant_p (rtx_code, rtx); |
e0600a02 JZ |
457 | void expand_vec_cmp (rtx, rtx_code, rtx, rtx); |
458 | bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); | |
4d1c8b04 LD |
459 | void expand_cond_len_unop (unsigned, rtx *); |
460 | void expand_cond_len_binop (unsigned, rtx *); | |
e6413b5d | 461 | void expand_reduction (unsigned, unsigned, rtx *, rtx); |
8bf5636e | 462 | void expand_vec_ceil (rtx, rtx, machine_mode, machine_mode); |
83441e75 | 463 | void expand_vec_floor (rtx, rtx, machine_mode, machine_mode); |
e2023d2d | 464 | void expand_vec_nearbyint (rtx, rtx, machine_mode, machine_mode); |
e4cf5f54 | 465 | void expand_vec_rint (rtx, rtx, machine_mode, machine_mode); |
a035d133 | 466 | #endif |
51fd69ec | 467 | bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, |
3cb0fa12 | 468 | bool, void (*)(rtx *, rtx)); |
ec99ffab | 469 | rtx gen_scalar_move_mask (machine_mode); |
1bff101b JZZ |
470 | |
471 | /* RVV vector register sizes. | |
472 | TODO: Currently, we only add RVV_32/RVV_64/RVV_128, we may need to | |
473 | support other values in the future. */ | |
474 | enum vlen_enum | |
475 | { | |
476 | RVV_32 = 32, | |
477 | RVV_64 = 64, | |
478 | RVV_65536 = 65536 | |
479 | }; | |
480 | bool slide1_sew64_helper (int, machine_mode, machine_mode, | |
481 | machine_mode, rtx *); | |
db4f7a9b | 482 | rtx gen_avl_for_scalar_move (rtx); |
51fd69ec | 483 | void expand_tuple_move (rtx *); |
2d76f2b4 | 484 | machine_mode preferred_simd_mode (scalar_mode); |
1349f530 | 485 | machine_mode get_mask_mode (machine_mode); |
003f388c | 486 | void expand_vec_series (rtx, rtx, rtx); |
1c1a9d8e | 487 | void expand_vec_init (rtx, rtx); |
2418cdfc | 488 | void expand_vec_perm (rtx, rtx, rtx, rtx); |
55dcf277 | 489 | void expand_select_vl (rtx *); |
d42d199e | 490 | void expand_load_store (rtx *, bool); |
f048af2a | 491 | void expand_gather_scatter (rtx *, bool); |
0d2673e9 | 492 | void expand_cond_len_ternop (unsigned, rtx *); |
95d2ce05 | 493 | void prepare_ternary_operands (rtx *); |
fe578886 | 494 | void expand_lanes_load_store (rtx *, bool); |
e7545cad | 495 | void expand_fold_extract_last (rtx *); |
8a87ba0b JZ |
496 | void expand_cond_unop (unsigned, rtx *); |
497 | void expand_cond_binop (unsigned, rtx *); | |
498 | void expand_cond_ternop (unsigned, rtx *); | |
47ffabaf | 499 | |
5ed88078 | 500 | /* Rounding mode bitfield for fixed point VXRM. */ |
47ffabaf | 501 | enum fixed_point_rounding_mode |
5ed88078 JZ |
502 | { |
503 | VXRM_RNU, | |
504 | VXRM_RNE, | |
505 | VXRM_RDN, | |
506 | VXRM_ROD | |
507 | }; | |
47ffabaf | 508 | |
7f4644f8 PL |
509 | /* Rounding mode bitfield for floating point FRM. The value of enum comes |
510 | from the below link. | |
511 | https://github.com/riscv/riscv-isa-manual/blob/main/src/f-st-ext.adoc#floating-point-control-and-status-register | |
512 | */ | |
47ffabaf | 513 | enum floating_point_rounding_mode |
8cd140d3 | 514 | { |
7f4644f8 PL |
515 | FRM_RNE = 0, /* Aka 0b000. */ |
516 | FRM_RTZ = 1, /* Aka 0b001. */ | |
517 | FRM_RDN = 2, /* Aka 0b010. */ | |
518 | FRM_RUP = 3, /* Aka 0b011. */ | |
519 | FRM_RMM = 4, /* Aka 0b100. */ | |
520 | FRM_DYN = 7, /* Aka 0b111. */ | |
4d1e97f5 PL |
521 | FRM_STATIC_MIN = FRM_RNE, |
522 | FRM_STATIC_MAX = FRM_RMM, | |
4cede0de PL |
523 | FRM_DYN_EXIT = 8, |
524 | FRM_DYN_CALL = 9, | |
525 | FRM_NONE = 10, | |
8cd140d3 | 526 | }; |
25907509 | 527 | |
4cede0de | 528 | enum floating_point_rounding_mode get_frm_mode (rtx); |
25907509 RD |
529 | opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode, |
530 | poly_uint64); | |
531 | unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool); | |
d05aac04 JZ |
532 | bool cmp_lmul_le_one (machine_mode); |
533 | bool cmp_lmul_gt_one (machine_mode); | |
7d935cdd JZZ |
534 | } |
535 | ||
cbd50570 JZZ |
536 | /* We classify builtin types into two classes: |
537 | 1. General builtin class which is defined in riscv_builtins. | |
538 | 2. Vector builtin class which is a special builtin architecture | |
539 | that implement intrinsic short into "pragma". */ | |
540 | enum riscv_builtin_class | |
541 | { | |
542 | RISCV_BUILTIN_GENERAL, | |
543 | RISCV_BUILTIN_VECTOR | |
544 | }; | |
545 | ||
546 | const unsigned int RISCV_BUILTIN_SHIFT = 1; | |
547 | ||
548 | /* Mask that selects the riscv_builtin_class part of a function code. */ | |
549 | const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1; | |
550 | ||
df48285b | 551 | /* Routines implemented in riscv-string.cc. */ |
949f1ccf | 552 | extern bool riscv_expand_strcmp (rtx, rtx, rtx, rtx, rtx); |
df48285b CM |
553 | extern bool riscv_expand_strlen (rtx, rtx, rtx, rtx); |
554 | ||
02fcaf41 CM |
555 | /* Routines implemented in thead.cc. */ |
556 | extern bool th_mempair_operands_p (rtx[4], bool, machine_mode); | |
557 | extern void th_mempair_order_operands (rtx[4], bool, machine_mode); | |
558 | extern void th_mempair_prepare_save_restore_operands (rtx[4], bool, | |
559 | machine_mode, | |
560 | int, HOST_WIDE_INT, | |
561 | int, HOST_WIDE_INT); | |
562 | extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode); | |
563 | #ifdef RTX_CODE | |
564 | extern const char* | |
565 | th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); | |
566 | #endif | |
567 | ||
065be0ff | 568 | extern bool riscv_use_divmod_expander (void); |
1d4d302a YW |
569 | void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int); |
570 | ||
09cae750 | 571 | #endif /* ! GCC_RISCV_PROTOS_H */ |